From 07816e8117a2ecb6a126264f3c16ca02668ca2be Mon Sep 17 00:00:00 2001 From: =?utf8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 19 Sep 2025 22:29:50 +0300 Subject: [PATCH] drm/i915: Tweak the read latency fixup code MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit If WM0 latency is zero we need to bump it (and the WM1+ latencies) but a fixed amount. But any WM1+ level with zero latency must not be touched since that indicates that corresponding WM level isn't supported. Currently the loop doing that adjustment does work, but only because the previous loop modified the num_levels used as the loop boundary. This all seems a bit too fragile. Remove the num_levels adjustment and instead adjust the read latency loop to abort when it encounters a zero latency value. Reviewed-by: Luca Coelho Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20250919193000.17665-4-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/skl_watermark.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 2bf334fe63c98..2969cc58dabe9 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -3198,8 +3198,6 @@ adjust_wm_latency(struct intel_display *display, if (wm[level] == 0) { for (i = level + 1; i < num_levels; i++) wm[i] = 0; - - num_levels = level; break; } } @@ -3212,8 +3210,14 @@ adjust_wm_latency(struct intel_display *display, * from the punit when level 0 response data is 0us. */ if (wm[0] == 0) { - for (level = 0; level < num_levels; level++) + wm[0] += read_latency; + + for (level = 1; level < num_levels; level++) { + if (wm[level] == 0) + break; + wm[level] += read_latency; + } } /* -- 2.47.3