From 0a52d413afc6236cd120286be8cb44714c36bc3c Mon Sep 17 00:00:00 2001 From: Nick Chan Date: Thu, 20 Feb 2025 20:21:42 +0800 Subject: [PATCH] arm64: dts: apple: s5l8960x: Add CPU caches Add information about CPU caches in Apple A7 SoC. Signed-off-by: Nick Chan Link: https://lore.kernel.org/r/20250220-caches-v1-1-2c7011097768@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/s5l8960x.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/apple/s5l8960x.dtsi b/arch/arm64/boot/dts/apple/s5l8960x.dtsi index d820b0e430507..5b5175d6978c4 100644 --- a/arch/arm64/boot/dts/apple/s5l8960x.dtsi +++ b/arch/arm64/boot/dts/apple/s5l8960x.dtsi @@ -37,6 +37,9 @@ performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; }; cpu1: cpu@1 { @@ -47,6 +50,16 @@ performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x100000>; }; }; -- 2.47.3