From 0a9692e15bcb372f6f65ad33335443c9d79c9ce8 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 8 Sep 2015 17:07:01 +0200 Subject: [PATCH] net: zynq: Fix MDC setting for zynq Based on spec: "MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and write operations)" Zynq is running on 111MHz. Current setting is 32 which is 111/32=3.47 which is above of 2.5MHz. Using 48 divider will give us correct setting according spec (111/48=2.31). Signed-off-by: Michal Simek --- drivers/net/zynq_gem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index c54d31a47ff..eccd5acee92 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -61,7 +61,7 @@ #ifdef CONFIG_ARM64 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x0001C0000 /* Div pclk by 224, 540MHz */ #else -#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */ +#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x0000c0000 /* Div pclk by 48, max 120MHz */ #endif #ifdef CONFIG_ARM64 -- 2.47.3