From 0ba9b41e514101a52cae4eb6f2b16ef8ed82cebb Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Sat, 9 Mar 2013 00:13:46 +0530 Subject: [PATCH] spi: zynq: Fix to check CS0 and CS1 MIO's Checking CS0 and CS1 MIO's for single and dual qspi which is missing on the existing runtime qspi detection code. Signed-off-by: Jagannadha Sutradharudu Teki --- drivers/spi/zynq_qspips.c | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/drivers/spi/zynq_qspips.c b/drivers/spi/zynq_qspips.c index 0920e43e534..4dc71173740 100644 --- a/drivers/spi/zynq_qspips.c +++ b/drivers/spi/zynq_qspips.c @@ -751,22 +751,30 @@ static int xqspips_check_is_dual_flash(void __iomem *regs_base) mio_base = regs_base + 0x700; /* checking single QSPI MIO's */ - for (mio_pin_index = 2; mio_pin_index < 7; mio_pin_index++) { - val = xqspips_read(mio_base + 4 * mio_pin_index); - if ((val & mask) == type) - lower_mio++; + val = xqspips_read(mio_base + 4 * 1); + if ((val & mask) == type) { + lower_mio++; + for (mio_pin_index = 2; mio_pin_index < 7; mio_pin_index++) { + val = xqspips_read(mio_base + 4 * mio_pin_index); + if ((val & mask) == type) + lower_mio++; + } } /* checking dual QSPI MIO's */ - for (mio_pin_index = 8; mio_pin_index < 14; mio_pin_index++) { - val = xqspips_read(mio_base + 4 * mio_pin_index); - if ((val & mask) == type) - upper_mio++; + val = xqspips_read(mio_base + 4 * 0); + if ((val & mask) == type) { + upper_mio++; + for (mio_pin_index = 9; mio_pin_index < 14; mio_pin_index++) { + val = xqspips_read(mio_base + 4 * mio_pin_index); + if ((val & mask) == type) + upper_mio++; + } } - if ((lower_mio == 5) && (upper_mio == 6)) + if ((lower_mio == 6) && (upper_mio == 6)) is_dual = 1; - else if (lower_mio == 5) + else if (lower_mio == 6) is_dual = 0; return is_dual; -- 2.47.3