From 0f4af4e2672040e505c7b337d48ec7cf2c1687bf Mon Sep 17 00:00:00 2001 From: =?utf8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Thu, 9 Oct 2025 16:54:35 +0200 Subject: [PATCH] target/rx: Use MemOp type in gen_ld[u]() and gen_st() MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The @size argument is of MemOp type. All callers respect that. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20251009151607.26278-3-philmd@linaro.org> --- target/rx/translate.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/rx/translate.c b/target/rx/translate.c index 1c911cd9a6..744edd56af 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -161,19 +161,19 @@ static void gen_goto_tb(DisasContext *dc, unsigned tb_slot_idx, vaddr dest) } /* generic load wrapper */ -static inline void rx_gen_ld(unsigned int size, TCGv reg, TCGv mem) +static inline void rx_gen_ld(MemOp size, TCGv reg, TCGv mem) { tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_SIGN | MO_TE); } /* unsigned load wrapper */ -static inline void rx_gen_ldu(unsigned int size, TCGv reg, TCGv mem) +static inline void rx_gen_ldu(MemOp size, TCGv reg, TCGv mem) { tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_TE); } /* generic store wrapper */ -static inline void rx_gen_st(unsigned int size, TCGv reg, TCGv mem) +static inline void rx_gen_st(MemOp size, TCGv reg, TCGv mem) { tcg_gen_qemu_st_i32(reg, mem, 0, size | MO_TE); } -- 2.47.3