From 14e21522133f4c33fecd1e42edaddcb23d1431f1 Mon Sep 17 00:00:00 2001 From: Alan Lawrence Date: Wed, 14 May 2014 13:23:29 +0000 Subject: [PATCH] Add execution tests of ARM TRN Intrinsics. * gcc.target/arm/simd/vtrnqf32_1.c: New file. * gcc.target/arm/simd/vtrnqp16_1.c: New file. * gcc.target/arm/simd/vtrnqp8_1.c: New file. * gcc.target/arm/simd/vtrnqs16_1.c: New file. * gcc.target/arm/simd/vtrnqs32_1.c: New file. * gcc.target/arm/simd/vtrnqs8_1.c: New file. * gcc.target/arm/simd/vtrnqu16_1.c: New file. * gcc.target/arm/simd/vtrnqu32_1.c: New file. * gcc.target/arm/simd/vtrnqu8_1.c: New file. * gcc.target/arm/simd/vtrnf32_1.c: New file. * gcc.target/arm/simd/vtrnp16_1.c: New file. * gcc.target/arm/simd/vtrnp8_1.c: New file. * gcc.target/arm/simd/vtrns16_1.c: New file. * gcc.target/arm/simd/vtrns32_1.c: New file. * gcc.target/arm/simd/vtrns8_1.c: New file. * gcc.target/arm/simd/vtrnu16_1.c: New file. * gcc.target/arm/simd/vtrnu32_1.c: New file. * gcc.target/arm/simd/vtrnu8_1.c: New file. From-SVN: r210422 --- gcc/testsuite/ChangeLog | 21 +++++++++++++++++++ gcc/testsuite/gcc.target/arm/simd/vtrnf32_1.c | 12 +++++++++++ gcc/testsuite/gcc.target/arm/simd/vtrnp16_1.c | 12 +++++++++++ gcc/testsuite/gcc.target/arm/simd/vtrnp8_1.c | 12 +++++++++++ .../gcc.target/arm/simd/vtrnqf32_1.c | 12 +++++++++++ .../gcc.target/arm/simd/vtrnqp16_1.c | 12 +++++++++++ gcc/testsuite/gcc.target/arm/simd/vtrnqp8_1.c | 12 +++++++++++ .../gcc.target/arm/simd/vtrnqs16_1.c | 12 +++++++++++ .../gcc.target/arm/simd/vtrnqs32_1.c | 12 +++++++++++ gcc/testsuite/gcc.target/arm/simd/vtrnqs8_1.c | 12 +++++++++++ .../gcc.target/arm/simd/vtrnqu16_1.c | 12 +++++++++++ .../gcc.target/arm/simd/vtrnqu32_1.c | 12 +++++++++++ gcc/testsuite/gcc.target/arm/simd/vtrnqu8_1.c | 12 +++++++++++ gcc/testsuite/gcc.target/arm/simd/vtrns16_1.c | 12 +++++++++++ gcc/testsuite/gcc.target/arm/simd/vtrns32_1.c | 12 +++++++++++ gcc/testsuite/gcc.target/arm/simd/vtrns8_1.c | 12 +++++++++++ gcc/testsuite/gcc.target/arm/simd/vtrnu16_1.c | 12 +++++++++++ gcc/testsuite/gcc.target/arm/simd/vtrnu32_1.c | 12 +++++++++++ gcc/testsuite/gcc.target/arm/simd/vtrnu8_1.c | 12 +++++++++++ 19 files changed, 237 insertions(+) create mode 100644 gcc/testsuite/gcc.target/arm/simd/vtrnf32_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vtrnp16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vtrnp8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vtrnqf32_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vtrnqp16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vtrnqp8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vtrnqs16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vtrnqs32_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vtrnqs8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vtrnqu16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vtrnqu32_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vtrnqu8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vtrns16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vtrns32_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vtrns8_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vtrnu16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vtrnu32_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vtrnu8_1.c diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 410e4f3926fe..fa968bf51f9f 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,24 @@ +2014-05-14 Alan Lawrence + + * gcc.target/arm/simd/vtrnqf32_1.c: New file. + * gcc.target/arm/simd/vtrnqp16_1.c: New file. + * gcc.target/arm/simd/vtrnqp8_1.c: New file. + * gcc.target/arm/simd/vtrnqs16_1.c: New file. + * gcc.target/arm/simd/vtrnqs32_1.c: New file. + * gcc.target/arm/simd/vtrnqs8_1.c: New file. + * gcc.target/arm/simd/vtrnqu16_1.c: New file. + * gcc.target/arm/simd/vtrnqu32_1.c: New file. + * gcc.target/arm/simd/vtrnqu8_1.c: New file. + * gcc.target/arm/simd/vtrnf32_1.c: New file. + * gcc.target/arm/simd/vtrnp16_1.c: New file. + * gcc.target/arm/simd/vtrnp8_1.c: New file. + * gcc.target/arm/simd/vtrns16_1.c: New file. + * gcc.target/arm/simd/vtrns32_1.c: New file. + * gcc.target/arm/simd/vtrns8_1.c: New file. + * gcc.target/arm/simd/vtrnu16_1.c: New file. + * gcc.target/arm/simd/vtrnu32_1.c: New file. + * gcc.target/arm/simd/vtrnu8_1.c: New file. + 2014-05-14 Ilya Tocar * gcc.target/i386/clflushopt-1.c: New. diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnf32_1.c new file mode 100644 index 000000000000..0f9b6c9b8bd5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnf32_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrnf32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrnf32.x" + +/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnp16_1.c new file mode 100644 index 000000000000..0ff43198109d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnp16_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrnp16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrnp16.x" + +/* { dg-final { scan-assembler-times "vtrn\.16\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnp8_1.c new file mode 100644 index 000000000000..2b047e4d7594 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnp8_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrnp8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrnp8.x" + +/* { dg-final { scan-assembler-times "vtrn\.8\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqf32_1.c new file mode 100644 index 000000000000..dd4e8836f3cf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqf32_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrnQf32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrnqf32.x" + +/* { dg-final { scan-assembler-times "vtrn\.32\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqp16_1.c new file mode 100644 index 000000000000..374eee396de2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqp16_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrnQp16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrnqp16.x" + +/* { dg-final { scan-assembler-times "vtrn\.16\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqp8_1.c new file mode 100644 index 000000000000..b252fd5f3b0e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqp8_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrnQp8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrnqp8.x" + +/* { dg-final { scan-assembler-times "vtrn\.8\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqs16_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqs16_1.c new file mode 100644 index 000000000000..5f06d2a3b128 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqs16_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrnQs16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrnqs16.x" + +/* { dg-final { scan-assembler-times "vtrn\.16\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqs32_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqs32_1.c new file mode 100644 index 000000000000..221175c46c60 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqs32_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrnQs32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrnqs32.x" + +/* { dg-final { scan-assembler-times "vtrn\.32\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqs8_1.c new file mode 100644 index 000000000000..9352b37a7836 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqs8_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrnQs8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrnqs8.x" + +/* { dg-final { scan-assembler-times "vtrn\.8\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqu16_1.c new file mode 100644 index 000000000000..7f40109b2a3f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqu16_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrnQu16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrnqu16.x" + +/* { dg-final { scan-assembler-times "vtrn\.16\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqu32_1.c new file mode 100644 index 000000000000..1c61fc34f7c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqu32_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrnQu32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrnqu32.x" + +/* { dg-final { scan-assembler-times "vtrn\.32\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqu8_1.c new file mode 100644 index 000000000000..82f911d5a78f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqu8_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrnQu8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrnqu8.x" + +/* { dg-final { scan-assembler-times "vtrn\.8\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrns16_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrns16_1.c new file mode 100644 index 000000000000..af2c68f381f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrns16_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrns16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrns16.x" + +/* { dg-final { scan-assembler-times "vtrn\.16\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrns32_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrns32_1.c new file mode 100644 index 000000000000..35a98ea95514 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrns32_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrns32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrns32.x" + +/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrns8_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrns8_1.c new file mode 100644 index 000000000000..395015d1330a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrns8_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrns8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrns8.x" + +/* { dg-final { scan-assembler-times "vtrn\.8\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnu16_1.c new file mode 100644 index 000000000000..df0d963a5fad --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnu16_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrnu16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrnu16.x" + +/* { dg-final { scan-assembler-times "vtrn\.16\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnu32_1.c new file mode 100644 index 000000000000..764ed623f07e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnu32_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrnu32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrnu32.x" + +/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnu8_1.c new file mode 100644 index 000000000000..f5b4d68966ea --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vtrnu8_1.c @@ -0,0 +1,12 @@ +/* Test the `vtrnu8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vtrnu8.x" + +/* { dg-final { scan-assembler-times "vtrn\.8\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ -- 2.47.3