From 165b9e93525aaf88f9ef7dac6067e3ed040d9a2b Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Mon, 2 Dec 2013 23:39:12 +0100 Subject: [PATCH] re PR lto/59326 (FAIL: gcc.dg/vect/vect-simd-clone-*.c) PR lto/59326 * gcc.target/i386/i386.exp (check_effective_target_avx2): Move to... * lib/target-supports.exp (check_effective_target_avx2): ... here. (check_effective_target_vect_simd_clones): New. * gcc.dg/vect/vect-simd-clone-1.c: Add dg-require-effective-target vect_simd_clones. * gcc.dg/vect/vect-simd-clone-2.c: Likewise. * gcc.dg/vect/vect-simd-clone-3.c: Likewise. * gcc.dg/vect/vect-simd-clone-4.c: Likewise. * gcc.dg/vect/vect-simd-clone-5.c: Likewise. * gcc.dg/vect/vect-simd-clone-6.c: Likewise. * gcc.dg/vect/vect-simd-clone-7.c: Likewise. * gcc.dg/vect/vect-simd-clone-8.c: Likewise. * gcc.dg/vect/vect-simd-clone-9.c: Likewise. * gcc.dg/vect/vect-simd-clone-10.c: Likewise. * gcc.dg/vect/vect-simd-clone-11.c: Likewise. * gcc.dg/vect/vect-simd-clone-12.c: Likewise. From-SVN: r205606 --- gcc/testsuite/ChangeLog | 20 ++++++++++ gcc/testsuite/gcc.dg/vect/vect-simd-clone-1.c | 1 + .../gcc.dg/vect/vect-simd-clone-10.c | 1 + .../gcc.dg/vect/vect-simd-clone-11.c | 1 + .../gcc.dg/vect/vect-simd-clone-12.c | 1 + gcc/testsuite/gcc.dg/vect/vect-simd-clone-2.c | 1 + gcc/testsuite/gcc.dg/vect/vect-simd-clone-3.c | 1 + gcc/testsuite/gcc.dg/vect/vect-simd-clone-4.c | 1 + gcc/testsuite/gcc.dg/vect/vect-simd-clone-5.c | 1 + gcc/testsuite/gcc.dg/vect/vect-simd-clone-6.c | 1 + gcc/testsuite/gcc.dg/vect/vect-simd-clone-7.c | 1 + gcc/testsuite/gcc.dg/vect/vect-simd-clone-8.c | 1 + gcc/testsuite/gcc.dg/vect/vect-simd-clone-9.c | 1 + gcc/testsuite/gcc.target/i386/i386.exp | 12 ------ gcc/testsuite/lib/target-supports.exp | 38 +++++++++++++++++++ 15 files changed, 70 insertions(+), 12 deletions(-) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index f92967a671c1..b9c2b6e71983 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,23 @@ +2013-12-02 Jakub Jelinek + + PR lto/59326 + * gcc.target/i386/i386.exp (check_effective_target_avx2): Move to... + * lib/target-supports.exp (check_effective_target_avx2): ... here. + (check_effective_target_vect_simd_clones): New. + * gcc.dg/vect/vect-simd-clone-1.c: Add dg-require-effective-target + vect_simd_clones. + * gcc.dg/vect/vect-simd-clone-2.c: Likewise. + * gcc.dg/vect/vect-simd-clone-3.c: Likewise. + * gcc.dg/vect/vect-simd-clone-4.c: Likewise. + * gcc.dg/vect/vect-simd-clone-5.c: Likewise. + * gcc.dg/vect/vect-simd-clone-6.c: Likewise. + * gcc.dg/vect/vect-simd-clone-7.c: Likewise. + * gcc.dg/vect/vect-simd-clone-8.c: Likewise. + * gcc.dg/vect/vect-simd-clone-9.c: Likewise. + * gcc.dg/vect/vect-simd-clone-10.c: Likewise. + * gcc.dg/vect/vect-simd-clone-11.c: Likewise. + * gcc.dg/vect/vect-simd-clone-12.c: Likewise. + 2013-12-02 Bernd Edlinger * gcc.dg/pr56997-4.c: New testcase. diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-1.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-1.c index d802dfb7e271..9fdd05638899 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-1.c +++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-1.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_simd_clones } */ /* { dg-additional-options "-fopenmp-simd" } */ /* { dg-additional-options "-mavx" { target avx_runtime } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-10.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-10.c index 3f29b52a8c3b..923a9453c25f 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-10.c +++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-10.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_simd_clones } */ /* { dg-additional-options "-fopenmp-simd" } */ /* { dg-additional-options "-mavx" { target avx_runtime } } */ /* { dg-additional-sources vect-simd-clone-10a.c } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-11.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-11.c index 4cccf852d0e4..a04530e251eb 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-11.c +++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-11.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_simd_clones } */ /* { dg-additional-options "-fopenmp-simd" } */ /* { dg-additional-options "-mavx" { target avx_runtime } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-12.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-12.c index 5c94153ea808..279abd7c6824 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-12.c +++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-12.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_simd_clones } */ /* { dg-additional-options "-fopenmp-simd" } */ /* { dg-additional-options "-mavx" { target avx_runtime } } */ /* { dg-additional-sources vect-simd-clone-12a.c } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-2.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-2.c index 4447607ef518..0eae49db97ae 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-2.c +++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-2.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_simd_clones } */ /* { dg-additional-options "-fopenmp-simd" } */ /* { dg-additional-options "-mavx" { target avx_runtime } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-3.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-3.c index 222d88e3016f..857c6f783e3c 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-3.c +++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-3.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_simd_clones } */ /* { dg-additional-options "-fopenmp-simd" } */ /* { dg-additional-options "-mavx" { target avx_runtime } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-4.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-4.c index 5b0a93a53d7c..c64f1b0bfe55 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-4.c +++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-4.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_simd_clones } */ /* { dg-additional-options "-fopenmp-simd" } */ /* { dg-additional-options "-mavx" { target avx_runtime } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-5.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-5.c index fd1d5ffd3228..1d2b067a7d52 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-5.c +++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-5.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_simd_clones } */ /* { dg-additional-options "-fopenmp-simd" } */ /* { dg-additional-options "-mavx" { target avx_runtime } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-6.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-6.c index 5e5641476c53..26995da86e3e 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-6.c +++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-6.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_simd_clones } */ /* { dg-additional-options "-fopenmp-simd" } */ /* { dg-additional-options "-mavx" { target avx_runtime } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-7.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-7.c index 24856eaa41a0..2745c5e41d19 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-7.c +++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-7.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_simd_clones } */ /* { dg-additional-options "-fopenmp-simd" } */ /* { dg-additional-options "-mavx" { target avx_runtime } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-8.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-8.c index 19c25c9db490..e0b09b645d44 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-8.c +++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-8.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_simd_clones } */ /* { dg-additional-options "-fopenmp-simd" } */ /* { dg-additional-options "-mavx" { target avx_runtime } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-9.c b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-9.c index 95156b90f011..0c5ff4fa4382 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-simd-clone-9.c +++ b/gcc/testsuite/gcc.dg/vect/vect-simd-clone-9.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_simd_clones } */ /* { dg-additional-options "-fopenmp-simd" } */ /* { dg-additional-options "-mavx" { target avx_runtime } } */ diff --git a/gcc/testsuite/gcc.target/i386/i386.exp b/gcc/testsuite/gcc.target/i386/i386.exp index 15f744cf2de9..c7c26766bc21 100644 --- a/gcc/testsuite/gcc.target/i386/i386.exp +++ b/gcc/testsuite/gcc.target/i386/i386.exp @@ -209,18 +209,6 @@ proc check_effective_target_lzcnt { } { } "-mlzcnt" ] } -# Return 1 if avx2 instructions can be compiled. -proc check_effective_target_avx2 { } { - return [check_no_compiler_messages avx2 object { - typedef long long __v4di __attribute__ ((__vector_size__ (32))); - __v4di - mm256_is32_andnotsi256 (__v4di __X, __v4di __Y) - { - return __builtin_ia32_andnotsi256 (__X, __Y); - } - } "-O0 -mavx2" ] -} - # Return 1 if bmi instructions can be compiled. proc check_effective_target_bmi { } { return [check_no_compiler_messages bmi object { diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 104818d327e6..e0f097d62418 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -2146,6 +2146,32 @@ proc check_effective_target_vect_floatuint_cvt { } { return $et_vect_floatuint_cvt_saved } +# Return 1 if the target supports #pragma omp declare simd, 0 otherwise. +# +# This won't change for different subtargets so cache the result. + +proc check_effective_target_vect_simd_clones { } { + global et_vect_simd_clones_saved + + if [info exists et_vect_simd_clones_saved] { + verbose "check_effective_target_vect_simd_clones: using cached result" 2 + } else { + set et_vect_simd_clones_saved 0 + if { [istarget i?86-*-*] || [istarget x86_64-*-*] } { + # On i?86/x86_64 #pragma omp declare simd builds a sse2, avx and + # avx2 clone. Only the right clone for the specified arch will be + # chosen, but still we need to at least be able to assemble + # avx2. + if { [check_effective_target_avx2] } { + set et_vect_simd_clones_saved 1 + } + } + } + + verbose "check_effective_target_vect_simd_clones: returning $et_vect_simd_clones_saved" 2 + return $et_vect_simd_clones_saved +} + # Return 1 if this is a AArch64 target supporting big endian proc check_effective_target_aarch64_big_endian { } { return [check_no_compiler_messages aarch64_big_endian assembly { @@ -5106,6 +5132,18 @@ proc check_effective_target_avx { } { } "-O2 -mavx" ] } +# Return 1 if avx2 instructions can be compiled. +proc check_effective_target_avx2 { } { + return [check_no_compiler_messages avx2 object { + typedef long long __v4di __attribute__ ((__vector_size__ (32))); + __v4di + mm256_is32_andnotsi256 (__v4di __X, __v4di __Y) + { + return __builtin_ia32_andnotsi256 (__X, __Y); + } + } "-O0 -mavx2" ] +} + # Return 1 if sse instructions can be compiled. proc check_effective_target_sse { } { return [check_no_compiler_messages sse object { -- 2.47.3