From 2367c94cbb1876b789ff91f78fd7daf2c1d6fb93 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Wed, 8 Oct 2025 09:06:25 +0200 Subject: [PATCH] target/openrisc: Remove target_ulong use in raise_mmu_exception() MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit TCGCPUOps::tlb_fill() handler provides a vaddr type (since commit 7510454e3e7 "cpu: Turn cpu_handle_mmu_fault() into a CPUClass hook"). Do not inline get_phys_nommu(), rely on the linker to optimize at linking time. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Message-Id: <20251010070702.51484-5-philmd@linaro.org> --- target/openrisc/mmu.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index acea50c41e..ffb732e0d1 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -28,15 +28,14 @@ #include "qemu/host-utils.h" #include "hw/loader.h" -static inline void get_phys_nommu(hwaddr *phys_addr, int *prot, - target_ulong address) +static void get_phys_nommu(hwaddr *phys_addr, int *prot, vaddr address) { *phys_addr = address; *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; } static int get_phys_mmu(OpenRISCCPU *cpu, hwaddr *phys_addr, int *prot, - target_ulong addr, int need, bool super) + vaddr addr, int need, bool super) { int idx = (addr >> TARGET_PAGE_BITS) & TLB_MASK; uint32_t imr = cpu->env.tlb.itlb[idx].mr; @@ -95,7 +94,7 @@ static int get_phys_mmu(OpenRISCCPU *cpu, hwaddr *phys_addr, int *prot, } } -static void raise_mmu_exception(OpenRISCCPU *cpu, target_ulong address, +static void raise_mmu_exception(OpenRISCCPU *cpu, vaddr address, int exception) { CPUState *cs = CPU(cpu); -- 2.47.3