From 241257e5fb488df538422cd8b93fd22044fd4c4d Mon Sep 17 00:00:00 2001 From: Sasha Levin Date: Fri, 24 Apr 2020 21:52:43 -0400 Subject: [PATCH] Fixes for 4.19 Signed-off-by: Sasha Levin --- ...rm64-add-part-number-for-neoverse-n1.patch | 42 ++++++ ...karound-neoverse-n1-1542419-for-comp.patch | 60 ++++++++ ...e-ctr_el0.dic-on-systems-affected-by.patch | 140 ++++++++++++++++++ ...minline-size-on-systems-affected-by-.patch | 73 +++++++++ ...ang-warning-on-mismatched-value-regi.patch | 39 +++++ queue-4.19/series | 5 + 6 files changed, 359 insertions(+) create mode 100644 queue-4.19/arm64-add-part-number-for-neoverse-n1.patch create mode 100644 queue-4.19/arm64-compat-workaround-neoverse-n1-1542419-for-comp.patch create mode 100644 queue-4.19/arm64-errata-hide-ctr_el0.dic-on-systems-affected-by.patch create mode 100644 queue-4.19/arm64-fake-the-iminline-size-on-systems-affected-by-.patch create mode 100644 queue-4.19/arm64-silence-clang-warning-on-mismatched-value-regi.patch diff --git a/queue-4.19/arm64-add-part-number-for-neoverse-n1.patch b/queue-4.19/arm64-add-part-number-for-neoverse-n1.patch new file mode 100644 index 00000000000..23ce8c38cf5 --- /dev/null +++ b/queue-4.19/arm64-add-part-number-for-neoverse-n1.patch @@ -0,0 +1,42 @@ +From 01fa3e3f6af50d17b4e973723ceb63930babec75 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 24 Apr 2020 17:38:41 +0100 +Subject: arm64: Add part number for Neoverse N1 + +From: Marc Zyngier + +[ Upstream commit 0cf57b86859c49381addb3ce47be70aadf5fd2c0 ] + +New CPU, new part number. You know the drill. + +Signed-off-by: Marc Zyngier +Signed-off-by: Will Deacon +Signed-off-by: James Morse +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index fa770c070fddf..3cd936b1c79c1 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -80,6 +80,7 @@ + #define ARM_CPU_PART_CORTEX_A35 0xD04 + #define ARM_CPU_PART_CORTEX_A55 0xD05 + #define ARM_CPU_PART_CORTEX_A76 0xD0B ++#define ARM_CPU_PART_NEOVERSE_N1 0xD0C + + #define APM_CPU_PART_POTENZA 0x000 + +@@ -107,6 +108,7 @@ + #define MIDR_CORTEX_A35 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A35) + #define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55) + #define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76) ++#define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1) + #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) + #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) + #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) +-- +2.20.1 + diff --git a/queue-4.19/arm64-compat-workaround-neoverse-n1-1542419-for-comp.patch b/queue-4.19/arm64-compat-workaround-neoverse-n1-1542419-for-comp.patch new file mode 100644 index 00000000000..3f548941dbb --- /dev/null +++ b/queue-4.19/arm64-compat-workaround-neoverse-n1-1542419-for-comp.patch @@ -0,0 +1,60 @@ +From f950b40eefe4b006d75a3262216ad15339d58bbe Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 24 Apr 2020 17:38:44 +0100 +Subject: arm64: compat: Workaround Neoverse-N1 #1542419 for compat user-space + +From: James Morse + +[ Upstream commit: 222fc0c8503d98cec3cb2bac2780cdd21a6e31c0 ] + +Compat user-space is unable to perform ICIMVAU instructions from +user-space. Instead it uses a compat-syscall. Add the workaround for +Neoverse-N1 #1542419 to this code path. + +Signed-off-by: James Morse +Signed-off-by: Catalin Marinas +Signed-off-by: James Morse +Signed-off-by: Sasha Levin +--- + arch/arm64/kernel/sys_compat.c | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/arch/arm64/kernel/sys_compat.c b/arch/arm64/kernel/sys_compat.c +index 010212d35700e..5a9b220aef6cf 100644 +--- a/arch/arm64/kernel/sys_compat.c ++++ b/arch/arm64/kernel/sys_compat.c +@@ -19,6 +19,7 @@ + */ + + #include ++#include + #include + #include + #include +@@ -28,6 +29,7 @@ + + #include + #include ++#include + #include + + static long +@@ -41,6 +43,15 @@ __do_compat_cache_op(unsigned long start, unsigned long end) + if (fatal_signal_pending(current)) + return 0; + ++ if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) { ++ /* ++ * The workaround requires an inner-shareable tlbi. ++ * We pick the reserved-ASID to minimise the impact. ++ */ ++ __tlbi(aside1is, 0); ++ dsb(ish); ++ } ++ + ret = __flush_cache_user_range(start, start + chunk); + if (ret) + return ret; +-- +2.20.1 + diff --git a/queue-4.19/arm64-errata-hide-ctr_el0.dic-on-systems-affected-by.patch b/queue-4.19/arm64-errata-hide-ctr_el0.dic-on-systems-affected-by.patch new file mode 100644 index 00000000000..9e51f74a062 --- /dev/null +++ b/queue-4.19/arm64-errata-hide-ctr_el0.dic-on-systems-affected-by.patch @@ -0,0 +1,140 @@ +From 14776074d1c84e5778cb8a6b70aab389711a84ec Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 24 Apr 2020 17:38:42 +0100 +Subject: arm64: errata: Hide CTR_EL0.DIC on systems affected by Neoverse-N1 + #1542419 + +From: James Morse + +[ Upstream commit 05460849c3b51180d5ada3373d0449aea19075e4 ] + +Cores affected by Neoverse-N1 #1542419 could execute a stale instruction +when a branch is updated to point to freshly generated instructions. + +To workaround this issue we need user-space to issue unnecessary +icache maintenance that we can trap. Start by hiding CTR_EL0.DIC. + +Reviewed-by: Suzuki K Poulose +Signed-off-by: James Morse +Signed-off-by: Catalin Marinas +[ Removed cpu_enable_trap_ctr_access() hunk due to no 4afe8e79da92] +Signed-off-by: James Morse +Signed-off-by: Sasha Levin +--- + Documentation/arm64/silicon-errata.txt | 1 + + arch/arm64/Kconfig | 16 ++++++++++++++++ + arch/arm64/include/asm/cpucaps.h | 3 ++- + arch/arm64/kernel/cpu_errata.c | 22 ++++++++++++++++++++++ + arch/arm64/kernel/traps.c | 3 +++ + 5 files changed, 44 insertions(+), 1 deletion(-) + +diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt +index eeb3fc9d777b8..667ea906266ed 100644 +--- a/Documentation/arm64/silicon-errata.txt ++++ b/Documentation/arm64/silicon-errata.txt +@@ -59,6 +59,7 @@ stable kernels. + | ARM | Cortex-A73 | #858921 | ARM64_ERRATUM_858921 | + | ARM | Cortex-A55 | #1024718 | ARM64_ERRATUM_1024718 | + | ARM | Cortex-A76 | #1463225 | ARM64_ERRATUM_1463225 | ++| ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 | + | ARM | MMU-500 | #841119,#826419 | N/A | + | | | | | + | Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 | +diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig +index 51fe21f5d0783..1fe3e5cb29278 100644 +--- a/arch/arm64/Kconfig ++++ b/arch/arm64/Kconfig +@@ -499,6 +499,22 @@ config ARM64_ERRATUM_1463225 + + If unsure, say Y. + ++config ARM64_ERRATUM_1542419 ++ bool "Neoverse-N1: workaround mis-ordering of instruction fetches" ++ default y ++ help ++ This option adds a workaround for ARM Neoverse-N1 erratum ++ 1542419. ++ ++ Affected Neoverse-N1 cores could execute a stale instruction when ++ modified by another CPU. The workaround depends on a firmware ++ counterpart. ++ ++ Workaround the issue by hiding the DIC feature from EL0. This ++ forces user-space to perform cache maintenance. ++ ++ If unsure, say Y. ++ + config CAVIUM_ERRATUM_22375 + bool "Cavium erratum 22375, 24313" + default y +diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h +index c3de0bbf0e9a2..df8fe8ecc37e1 100644 +--- a/arch/arm64/include/asm/cpucaps.h ++++ b/arch/arm64/include/asm/cpucaps.h +@@ -53,7 +53,8 @@ + #define ARM64_HAS_STAGE2_FWB 32 + #define ARM64_WORKAROUND_1463225 33 + #define ARM64_SSBS 34 ++#define ARM64_WORKAROUND_1542419 35 + +-#define ARM64_NCAPS 35 ++#define ARM64_NCAPS 36 + + #endif /* __ASM_CPUCAPS_H */ +diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c +index 71888808ded72..76490b0cefcee 100644 +--- a/arch/arm64/kernel/cpu_errata.c ++++ b/arch/arm64/kernel/cpu_errata.c +@@ -643,6 +643,18 @@ needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry, + return false; + } + ++static bool __maybe_unused ++has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry, ++ int scope) ++{ ++ u32 midr = read_cpuid_id(); ++ bool has_dic = read_cpuid_cachetype() & BIT(CTR_DIC_SHIFT); ++ const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1); ++ ++ WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); ++ return is_midr_in_range(midr, &range) && has_dic; ++} ++ + #ifdef CONFIG_HARDEN_EL2_VECTORS + + static const struct midr_range arm64_harden_el2_vectors[] = { +@@ -834,6 +846,16 @@ const struct arm64_cpu_capabilities arm64_errata[] = { + ERRATA_MIDR_RANGE_LIST(tx2_family_cpus), + .matches = needs_tx2_tvm_workaround, + }, ++#endif ++#ifdef CONFIG_ARM64_ERRATUM_1542419 ++ { ++ /* we depend on the firmware portion for correctness */ ++ .desc = "ARM erratum 1542419 (kernel portion)", ++ .capability = ARM64_WORKAROUND_1542419, ++ .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, ++ .matches = has_neoverse_n1_erratum_1542419, ++ .cpu_enable = cpu_enable_trap_ctr_access, ++ }, + #endif + { + } +diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c +index c8dc3a3640e7e..253b7f84a5a0d 100644 +--- a/arch/arm64/kernel/traps.c ++++ b/arch/arm64/kernel/traps.c +@@ -481,6 +481,9 @@ static void ctr_read_handler(unsigned int esr, struct pt_regs *regs) + int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT; + unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0); + ++ if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) ++ val &= ~BIT(CTR_DIC_SHIFT); ++ + pt_regs_write_reg(regs, rt, val); + + arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); +-- +2.20.1 + diff --git a/queue-4.19/arm64-fake-the-iminline-size-on-systems-affected-by-.patch b/queue-4.19/arm64-fake-the-iminline-size-on-systems-affected-by-.patch new file mode 100644 index 00000000000..7ef92c19766 --- /dev/null +++ b/queue-4.19/arm64-fake-the-iminline-size-on-systems-affected-by-.patch @@ -0,0 +1,73 @@ +From 2ec0db7141b92cf8772d3f4d78117b9160d79b03 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 24 Apr 2020 17:38:43 +0100 +Subject: arm64: Fake the IminLine size on systems affected by Neoverse-N1 + #1542419 + +From: James Morse + +[ Upstream commit ee9d90be9ddace01b7fb126567e4b539fbe1f82f ] + +Systems affected by Neoverse-N1 #1542419 support DIC so do not need to +perform icache maintenance once new instructions are cleaned to the PoU. +For the errata workaround, the kernel hides DIC from user-space, so that +the unnecessary cache maintenance can be trapped by firmware. + +To reduce the number of traps, produce a fake IminLine value based on +PAGE_SIZE. + +Signed-off-by: James Morse +Reviewed-by: Suzuki K Poulose +Signed-off-by: Catalin Marinas +Signed-off-by: James Morse +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cache.h | 3 ++- + arch/arm64/kernel/traps.c | 8 +++++++- + 2 files changed, 9 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h +index 5ee5bca8c24b1..baa684782358c 100644 +--- a/arch/arm64/include/asm/cache.h ++++ b/arch/arm64/include/asm/cache.h +@@ -22,6 +22,7 @@ + #define CTR_L1IP_MASK 3 + #define CTR_DMINLINE_SHIFT 16 + #define CTR_IMINLINE_SHIFT 0 ++#define CTR_IMINLINE_MASK 0xf + #define CTR_ERG_SHIFT 20 + #define CTR_CWG_SHIFT 24 + #define CTR_CWG_MASK 15 +@@ -29,7 +30,7 @@ + #define CTR_DIC_SHIFT 29 + + #define CTR_CACHE_MINLINE_MASK \ +- (0xf << CTR_DMINLINE_SHIFT | 0xf << CTR_IMINLINE_SHIFT) ++ (0xf << CTR_DMINLINE_SHIFT | CTR_IMINLINE_MASK << CTR_IMINLINE_SHIFT) + + #define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK) + +diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c +index 253b7f84a5a0d..965595fe68045 100644 +--- a/arch/arm64/kernel/traps.c ++++ b/arch/arm64/kernel/traps.c +@@ -481,9 +481,15 @@ static void ctr_read_handler(unsigned int esr, struct pt_regs *regs) + int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT; + unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0); + +- if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) ++ if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) { ++ /* Hide DIC so that we can trap the unnecessary maintenance...*/ + val &= ~BIT(CTR_DIC_SHIFT); + ++ /* ... and fake IminLine to reduce the number of traps. */ ++ val &= ~CTR_IMINLINE_MASK; ++ val |= (PAGE_SHIFT - 2) & CTR_IMINLINE_MASK; ++ } ++ + pt_regs_write_reg(regs, rt, val); + + arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); +-- +2.20.1 + diff --git a/queue-4.19/arm64-silence-clang-warning-on-mismatched-value-regi.patch b/queue-4.19/arm64-silence-clang-warning-on-mismatched-value-regi.patch new file mode 100644 index 00000000000..6df7bebdad7 --- /dev/null +++ b/queue-4.19/arm64-silence-clang-warning-on-mismatched-value-regi.patch @@ -0,0 +1,39 @@ +From a587ab9f7cd78e991236a734f999ae0f196b11b4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 24 Apr 2020 17:38:45 +0100 +Subject: arm64: Silence clang warning on mismatched value/register sizes + +From: Catalin Marinas + +[ Upstream commit: 27a22fbdeedd6c5c451cf5f830d51782bf50c3a2 ] + +Clang reports a warning on the __tlbi(aside1is, 0) macro expansion since +the value size does not match the register size specified in the inline +asm. Construct the ASID value using the __TLBI_VADDR() macro. + +Fixes: 222fc0c8503d ("arm64: compat: Workaround Neoverse-N1 #1542419 for compat user-space") +Reported-by: Nathan Chancellor +Cc: James Morse +Signed-off-by: Catalin Marinas +Signed-off-by: James Morse +Signed-off-by: Sasha Levin +--- + arch/arm64/kernel/sys_compat.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/kernel/sys_compat.c b/arch/arm64/kernel/sys_compat.c +index 5a9b220aef6cf..3ef9d0a3ac1dc 100644 +--- a/arch/arm64/kernel/sys_compat.c ++++ b/arch/arm64/kernel/sys_compat.c +@@ -48,7 +48,7 @@ __do_compat_cache_op(unsigned long start, unsigned long end) + * The workaround requires an inner-shareable tlbi. + * We pick the reserved-ASID to minimise the impact. + */ +- __tlbi(aside1is, 0); ++ __tlbi(aside1is, __TLBI_VADDR(0, 0)); + dsb(ish); + } + +-- +2.20.1 + diff --git a/queue-4.19/series b/queue-4.19/series index e29c68df466..973e6d7ea5e 100644 --- a/queue-4.19/series +++ b/queue-4.19/series @@ -3,3 +3,8 @@ drm-msm-use-the-correct-dma_sync-calls-harder.patch bpftool-fix-printing-incorrect-pointer-in-btf_dump_ptr.patch crypto-mxs-dcp-make-symbols-sha1_null_hash-and-sha256_null_hash-static.patch vti4-removed-duplicate-log-message.patch +arm64-add-part-number-for-neoverse-n1.patch +arm64-errata-hide-ctr_el0.dic-on-systems-affected-by.patch +arm64-fake-the-iminline-size-on-systems-affected-by-.patch +arm64-compat-workaround-neoverse-n1-1542419-for-comp.patch +arm64-silence-clang-warning-on-mismatched-value-regi.patch -- 2.47.3