From 2e586d967a00307604ac158972ef2ffaa3adff40 Mon Sep 17 00:00:00 2001 From: nobody <> Date: Tue, 9 Mar 2004 20:50:57 +0000 Subject: [PATCH] This commit was manufactured by cvs2svn to create branch 'cagney_tramp-20040309-branch'. Sprout from gdb_6_1-branch 2004-02-29 23:00:22 UTC nobody 'This commit was manufactured by cvs2svn to create branch 'gdb_6_1-branch'.' Cherrypick from master 2004-03-09 20:50:56 UTC Jim Wilson 'Patch from Steve Ellcey for potential race condition.': ChangeLog bfd/ChangeLog bfd/archures.c bfd/bfd-in2.h bfd/cpu-frv.c bfd/cpu-sh.c bfd/elf.c bfd/elf32-frv.c bfd/elf32-sh.c bfd/elflink.c bfd/elfxx-ia64.c bfd/elfxx-mips.c bfd/version.h configure configure.in cpu/ChangeLog cpu/frv.cpu cpu/frv.opc gdb/ChangeLog gdb/MAINTAINERS gdb/amd64-linux-nat.c gdb/amd64-nat.c gdb/amd64bsd-nat.c gdb/amd64fbsd-nat.c gdb/arm-tdep.c gdb/config/alpha/fbsd.mt gdb/config/pa/tm-hppa.h gdb/config/pa/tm-hppa64.h gdb/config/rs6000/tm-rs6000.h gdb/cp-namespace.c gdb/cris-tdep.c gdb/doc/ChangeLog gdb/doc/gdb.texinfo gdb/dwarf2read.c gdb/gdbserver/ChangeLog gdb/gdbserver/Makefile.in gdb/gdbserver/linux-low.c gdb/gdbserver/server.c gdb/gdbserver/target.c gdb/gdbserver/target.h gdb/gdbtypes.c gdb/hppa-tdep.c gdb/i386-nat.c gdb/i386-tdep.h gdb/i386bsd-tdep.c gdb/i386nbsd-tdep.c gdb/i386obsd-tdep.c gdb/infcall.c gdb/infrun.c gdb/ppc-linux-nat.c gdb/rs6000-tdep.c gdb/sh-tdep.c gdb/sparc-tdep.c gdb/stabsread.c gdb/target.c gdb/testsuite/ChangeLog gdb/testsuite/gdb.asm/openbsd.inc gdb/testsuite/gdb.base/pc-fp.exp gdb/testsuite/gdb.cp/classes.cc gdb/testsuite/gdb.cp/classes.exp gdb/testsuite/gdb.cp/misc.cc gdb/testsuite/gdb.cp/rtti.exp gdb/testsuite/gdb.cp/rtti.h gdb/testsuite/gdb.cp/rtti1.cc gdb/testsuite/gdb.cp/rtti2.cc gdb/user-regs.c gdb/version.in include/elf/ChangeLog include/elf/frv.h include/elf/sh.h libiberty/ChangeLog libiberty/configure libiberty/testsuite/test-demangle.c opcodes/ChangeLog opcodes/frv-asm.c opcodes/frv-desc.c opcodes/frv-desc.h opcodes/frv-dis.c opcodes/frv-ibld.c opcodes/frv-opc.c opcodes/frv-opc.h opcodes/po/de.po opcodes/sh-dis.c opcodes/sh-opc.h sim/frv/ChangeLog sim/frv/Makefile.in sim/frv/arch.c sim/frv/arch.h sim/frv/cache.c sim/frv/cpu.h sim/frv/cpuall.h sim/frv/decode.c sim/frv/decode.h sim/frv/frv-sim.h sim/frv/frv.c sim/frv/interrupts.c sim/frv/memory.c sim/frv/mloop.in sim/frv/model.c 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sim/testsuite/sim/frv/fbnolr.cgs | 47 - sim/testsuite/sim/frv/fbo.cgs | 73 - sim/testsuite/sim/frv/fbolr.cgs | 90 - sim/testsuite/sim/frv/fbra.cgs | 75 - sim/testsuite/sim/frv/fbralr.cgs | 91 - sim/testsuite/sim/frv/fbu.cgs | 61 - sim/testsuite/sim/frv/fbue.cgs | 69 - sim/testsuite/sim/frv/fbuelr.cgs | 88 - sim/testsuite/sim/frv/fbug.cgs | 69 - sim/testsuite/sim/frv/fbuge.cgs | 73 - sim/testsuite/sim/frv/fbugelr.cgs | 90 - sim/testsuite/sim/frv/fbuglr.cgs | 88 - sim/testsuite/sim/frv/fbul.cgs | 69 - sim/testsuite/sim/frv/fbule.cgs | 73 - sim/testsuite/sim/frv/fbulelr.cgs | 90 - sim/testsuite/sim/frv/fbullr.cgs | 88 - sim/testsuite/sim/frv/fbulr.cgs | 84 - sim/testsuite/sim/frv/fcbeqlr.cgs | 262 - sim/testsuite/sim/frv/fcbgelr.cgs | 270 - sim/testsuite/sim/frv/fcbgtlr.cgs | 262 - sim/testsuite/sim/frv/fcblelr.cgs | 270 - sim/testsuite/sim/frv/fcblglr.cgs | 270 - sim/testsuite/sim/frv/fcbltlr.cgs | 262 - sim/testsuite/sim/frv/fcbnelr.cgs | 274 - sim/testsuite/sim/frv/fcbnolr.cgs | 185 - sim/testsuite/sim/frv/fcbolr.cgs | 274 - sim/testsuite/sim/frv/fcbralr.cgs | 276 - sim/testsuite/sim/frv/fcbuelr.cgs | 270 - sim/testsuite/sim/frv/fcbugelr.cgs | 274 - sim/testsuite/sim/frv/fcbuglr.cgs | 270 - sim/testsuite/sim/frv/fcbulelr.cgs | 274 - sim/testsuite/sim/frv/fcbullr.cgs | 270 - sim/testsuite/sim/frv/fcbulr.cgs | 262 - sim/testsuite/sim/frv/fckeq.cgs | 90 - sim/testsuite/sim/frv/fckge.cgs | 90 - sim/testsuite/sim/frv/fckgt.cgs | 90 - sim/testsuite/sim/frv/fckle.cgs | 90 - sim/testsuite/sim/frv/fcklg.cgs | 90 - sim/testsuite/sim/frv/fcklt.cgs | 90 - sim/testsuite/sim/frv/fckne.cgs | 90 - sim/testsuite/sim/frv/fckno.cgs | 90 - sim/testsuite/sim/frv/fcko.cgs | 90 - sim/testsuite/sim/frv/fckra.cgs | 90 - sim/testsuite/sim/frv/fcku.cgs | 90 - sim/testsuite/sim/frv/fckue.cgs | 90 - sim/testsuite/sim/frv/fckug.cgs | 90 - sim/testsuite/sim/frv/fckuge.cgs | 90 - sim/testsuite/sim/frv/fckul.cgs | 90 - sim/testsuite/sim/frv/fckule.cgs | 90 - sim/testsuite/sim/frv/fcmpd.cgs | 601 - sim/testsuite/sim/frv/fcmps.cgs | 600 - sim/testsuite/sim/frv/fdabss.cgs | 25 - sim/testsuite/sim/frv/fdadds.cgs | 134 - sim/testsuite/sim/frv/fdcmps.cgs | 985 - sim/testsuite/sim/frv/fddivs.cgs | 195 - sim/testsuite/sim/frv/fditos.cgs | 25 - sim/testsuite/sim/frv/fdivd.cgs | 128 - sim/testsuite/sim/frv/fdivs.cgs | 127 - sim/testsuite/sim/frv/fdmadds.cgs | 226 - sim/testsuite/sim/frv/fdmas.cgs | 265 - sim/testsuite/sim/frv/fdmovs.cgs | 45 - sim/testsuite/sim/frv/fdmss.cgs | 235 - sim/testsuite/sim/frv/fdmulcs.cgs | 201 - sim/testsuite/sim/frv/fdmuls.cgs | 193 - sim/testsuite/sim/frv/fdnegs.cgs | 25 - sim/testsuite/sim/frv/fdsads.cgs | 119 - sim/testsuite/sim/frv/fdsqrts.cgs | 17 - sim/testsuite/sim/frv/fdstoi.cgs | 23 - sim/testsuite/sim/frv/fdsubs.cgs | 117 - sim/testsuite/sim/frv/fdtoi.cgs | 32 - sim/testsuite/sim/frv/fitod.cgs | 26 - sim/testsuite/sim/frv/fitos.cgs | 25 - sim/testsuite/sim/frv/fmad.cgs | 161 - sim/testsuite/sim/frv/fmaddd.cgs | 143 - sim/testsuite/sim/frv/fmadds.cgs | 143 - sim/testsuite/sim/frv/fmas.cgs | 161 - sim/testsuite/sim/frv/fmovd.cgs | 48 - sim/testsuite/sim/frv/fmovs.cgs | 45 - sim/testsuite/sim/frv/fmsd.cgs | 146 - sim/testsuite/sim/frv/fmss.cgs | 146 - sim/testsuite/sim/frv/fmsubd.cgs | 144 - sim/testsuite/sim/frv/fmsubs.cgs | 144 - sim/testsuite/sim/frv/fmuld.cgs | 126 - sim/testsuite/sim/frv/fmuls.cgs | 125 - sim/testsuite/sim/frv/fnegd.cgs | 26 - sim/testsuite/sim/frv/fnegs.cgs | 25 - sim/testsuite/sim/frv/fnop.cgs | 12 - sim/testsuite/sim/frv/fr400/addss.cgs | 36 - sim/testsuite/sim/frv/fr400/allinsn.exp | 19 - sim/testsuite/sim/frv/fr400/csdiv.cgs | 187 - sim/testsuite/sim/frv/fr400/maddaccs.cgs | 131 - sim/testsuite/sim/frv/fr400/masaccs.cgs | 151 - sim/testsuite/sim/frv/fr400/maveh.cgs | 319 - sim/testsuite/sim/frv/fr400/mclracc.cgs | 79 - sim/testsuite/sim/frv/fr400/mhdseth.cgs | 22 - sim/testsuite/sim/frv/fr400/mhdsets.cgs | 20 - sim/testsuite/sim/frv/fr400/mhsethih.cgs | 22 - sim/testsuite/sim/frv/fr400/mhsethis.cgs | 25 - sim/testsuite/sim/frv/fr400/mhsetloh.cgs | 27 - sim/testsuite/sim/frv/fr400/mhsetlos.cgs | 25 - sim/testsuite/sim/frv/fr400/movgs.cgs | 50 - sim/testsuite/sim/frv/fr400/movsg.cgs | 65 - sim/testsuite/sim/frv/fr400/msubaccs.cgs | 131 - sim/testsuite/sim/frv/fr400/scutss.cgs | 642 - sim/testsuite/sim/frv/fr400/sdiv.cgs | 71 - sim/testsuite/sim/frv/fr400/sdivi.cgs | 70 - sim/testsuite/sim/frv/fr400/slass.cgs | 104 - sim/testsuite/sim/frv/fr400/smass.cgs | 359 - sim/testsuite/sim/frv/fr400/smsss.cgs | 354 - sim/testsuite/sim/frv/fr400/smu.cgs | 237 - sim/testsuite/sim/frv/fr400/subss.cgs | 43 - sim/testsuite/sim/frv/fr400/udiv.cgs | 46 - sim/testsuite/sim/frv/fr400/udivi.cgs | 47 - sim/testsuite/sim/frv/fr500/allinsn.exp | 19 - sim/testsuite/sim/frv/fr500/cmqaddhss.cgs | 444 - sim/testsuite/sim/frv/fr500/cmqaddhus.cgs | 360 - sim/testsuite/sim/frv/fr500/cmqsubhss.cgs | 448 - sim/testsuite/sim/frv/fr500/cmqsubhus.cgs | 370 - sim/testsuite/sim/frv/fr500/dcpl.cgs | 65 - sim/testsuite/sim/frv/fr500/dcul.cgs | 118 - sim/testsuite/sim/frv/fr500/mclracc.cgs | 79 - sim/testsuite/sim/frv/fr500/mqaddhss.cgs | 79 - sim/testsuite/sim/frv/fr500/mqaddhus.cgs | 65 - sim/testsuite/sim/frv/fr500/mqsubhss.cgs | 79 - sim/testsuite/sim/frv/fr500/mqsubhus.cgs | 66 - sim/testsuite/sim/frv/fr550/allinsn.exp | 19 - sim/testsuite/sim/frv/fr550/cmaddhss.cgs | 547 - sim/testsuite/sim/frv/fr550/cmaddhus.cgs | 481 - sim/testsuite/sim/frv/fr550/cmcpxiu.cgs | 492 - sim/testsuite/sim/frv/fr550/cmcpxru.cgs | 528 - sim/testsuite/sim/frv/fr550/cmmachs.cgs | 1545 -- sim/testsuite/sim/frv/fr550/cmmachu.cgs | 858 - sim/testsuite/sim/frv/fr550/cmqaddhss.cgs | 429 - sim/testsuite/sim/frv/fr550/cmqaddhus.cgs | 345 - sim/testsuite/sim/frv/fr550/cmqmachs.cgs | 1262 -- sim/testsuite/sim/frv/fr550/cmqmachu.cgs | 870 - sim/testsuite/sim/frv/fr550/cmqsubhss.cgs | 429 - sim/testsuite/sim/frv/fr550/cmqsubhus.cgs | 351 - sim/testsuite/sim/frv/fr550/cmsubhss.cgs | 547 - sim/testsuite/sim/frv/fr550/cmsubhus.cgs | 427 - sim/testsuite/sim/frv/fr550/dcpl.cgs | 65 - sim/testsuite/sim/frv/fr550/dcul.cgs | 118 - sim/testsuite/sim/frv/fr550/mabshs.cgs | 64 - sim/testsuite/sim/frv/fr550/maddaccs.cgs | 128 - sim/testsuite/sim/frv/fr550/maddhss.cgs | 97 - sim/testsuite/sim/frv/fr550/maddhus.cgs | 86 - sim/testsuite/sim/frv/fr550/masaccs.cgs | 148 - sim/testsuite/sim/frv/fr550/mdaddaccs.cgs | 102 - sim/testsuite/sim/frv/fr550/mdasaccs.cgs | 122 - sim/testsuite/sim/frv/fr550/mdsubaccs.cgs | 102 - sim/testsuite/sim/frv/fr550/mmachs.cgs | 259 - sim/testsuite/sim/frv/fr550/mmachu.cgs | 146 - sim/testsuite/sim/frv/fr550/mmrdhs.cgs | 263 - sim/testsuite/sim/frv/fr550/mmrdhu.cgs | 151 - sim/testsuite/sim/frv/fr550/mqaddhss.cgs | 76 - sim/testsuite/sim/frv/fr550/mqaddhus.cgs | 62 - sim/testsuite/sim/frv/fr550/mqmachs.cgs | 211 - sim/testsuite/sim/frv/fr550/mqmachu.cgs | 144 - sim/testsuite/sim/frv/fr550/mqmacxhs.cgs | 211 - sim/testsuite/sim/frv/fr550/mqsubhss.cgs | 76 - sim/testsuite/sim/frv/fr550/mqsubhus.cgs | 63 - sim/testsuite/sim/frv/fr550/mqxmachs.cgs | 211 - sim/testsuite/sim/frv/fr550/mqxmacxhs.cgs | 211 - sim/testsuite/sim/frv/fr550/msubaccs.cgs | 128 - sim/testsuite/sim/frv/fr550/msubhss.cgs | 97 - sim/testsuite/sim/frv/fr550/msubhus.cgs | 77 - sim/testsuite/sim/frv/fr550/mtrap.cgs | 50 - sim/testsuite/sim/frv/fr550/udiv.cgs | 48 - sim/testsuite/sim/frv/fr550/udivi.cgs | 49 - sim/testsuite/sim/frv/fsqrtd.cgs | 22 - sim/testsuite/sim/frv/fsqrts.cgs | 19 - sim/testsuite/sim/frv/fstoi.cgs | 24 - sim/testsuite/sim/frv/fsubd.cgs | 83 - sim/testsuite/sim/frv/fsubs.cgs | 82 - sim/testsuite/sim/frv/fteq.cgs | 101 - sim/testsuite/sim/frv/ftge.cgs | 109 - sim/testsuite/sim/frv/ftgt.cgs | 101 - sim/testsuite/sim/frv/ftieq.cgs | 100 - sim/testsuite/sim/frv/ftige.cgs | 108 - sim/testsuite/sim/frv/ftigt.cgs | 100 - sim/testsuite/sim/frv/ftile.cgs | 108 - sim/testsuite/sim/frv/ftilg.cgs | 108 - sim/testsuite/sim/frv/ftilt.cgs | 100 - sim/testsuite/sim/frv/ftine.cgs | 112 - sim/testsuite/sim/frv/ftino.cgs | 53 - sim/testsuite/sim/frv/ftio.cgs | 112 - sim/testsuite/sim/frv/ftira.cgs | 114 - sim/testsuite/sim/frv/ftiu.cgs | 100 - sim/testsuite/sim/frv/ftiue.cgs | 108 - sim/testsuite/sim/frv/ftiug.cgs | 108 - sim/testsuite/sim/frv/ftiuge.cgs | 112 - sim/testsuite/sim/frv/ftiul.cgs | 108 - sim/testsuite/sim/frv/ftle.cgs | 109 - sim/testsuite/sim/frv/ftlg.cgs | 109 - sim/testsuite/sim/frv/ftlt.cgs | 101 - sim/testsuite/sim/frv/ftne.cgs | 113 - sim/testsuite/sim/frv/ftno.cgs | 54 - sim/testsuite/sim/frv/fto.cgs | 113 - sim/testsuite/sim/frv/ftra.cgs | 115 - sim/testsuite/sim/frv/ftu.cgs | 101 - sim/testsuite/sim/frv/ftue.cgs | 109 - sim/testsuite/sim/frv/ftug.cgs | 109 - sim/testsuite/sim/frv/ftuge.cgs | 113 - sim/testsuite/sim/frv/ftul.cgs | 109 - sim/testsuite/sim/frv/ftule.cgs | 113 - sim/testsuite/sim/frv/icei.cgs | 15 - sim/testsuite/sim/frv/ici.cgs | 39 - sim/testsuite/sim/frv/icpl.cgs | 39 - sim/testsuite/sim/frv/icul.cgs | 53 - sim/testsuite/sim/frv/interrupts.exp | 19 - .../sim/frv/interrupts/Ipipe-fr400.cgs | 35 - .../sim/frv/interrupts/Ipipe-fr500.cgs | 35 - .../sim/frv/interrupts/badalign-fr550.cgs | 42 - sim/testsuite/sim/frv/interrupts/badalign.cgs | 73 - .../sim/frv/interrupts/compound-fr550.cgs | 54 - sim/testsuite/sim/frv/interrupts/compound.cgs | 66 - .../frv/interrupts/data_store_error-fr550.cgs | 53 - .../sim/frv/interrupts/data_store_error.cgs | 53 - .../sim/frv/interrupts/fp_exception-fr550.cgs | 185 - .../sim/frv/interrupts/fp_exception.cgs | 209 - sim/testsuite/sim/frv/interrupts/illinsn.cgs | 38 - .../interrupts/insn_access_error-fr550.cgs | 44 - .../sim/frv/interrupts/insn_access_error.cgs | 56 - .../sim/frv/interrupts/mp_exception.cgs | 289 - .../frv/interrupts/privileged_instruction.cgs | 54 - sim/testsuite/sim/frv/interrupts/regalign.cgs | 130 - sim/testsuite/sim/frv/interrupts/reset.cgs | 81 - .../sim/frv/interrupts/shadow_regs.cgs | 205 - sim/testsuite/sim/frv/interrupts/timer.cgs | 31 - sim/testsuite/sim/frv/jmpil.cgs | 17 - sim/testsuite/sim/frv/jmpl.cgs | 18 - sim/testsuite/sim/frv/jmpl.pcgs | 42 - sim/testsuite/sim/frv/ld.cgs | 29 - sim/testsuite/sim/frv/ldbf.cgs | 27 - sim/testsuite/sim/frv/ldbfi.cgs | 24 - sim/testsuite/sim/frv/ldbfu.cgs | 34 - sim/testsuite/sim/frv/ldc.cgs | 30 - sim/testsuite/sim/frv/ldcu.cgs | 34 - sim/testsuite/sim/frv/ldd.cgs | 43 - sim/testsuite/sim/frv/lddc.cgs | 45 - sim/testsuite/sim/frv/lddcu.cgs | 42 - sim/testsuite/sim/frv/lddf.cgs | 46 - sim/testsuite/sim/frv/lddfi.cgs | 34 - sim/testsuite/sim/frv/lddfu.cgs | 41 - sim/testsuite/sim/frv/lddi.cgs | 34 - sim/testsuite/sim/frv/lddu.cgs | 50 - sim/testsuite/sim/frv/ldf.cgs | 29 - sim/testsuite/sim/frv/ldfi.cgs | 26 - sim/testsuite/sim/frv/ldfu.cgs | 33 - sim/testsuite/sim/frv/ldhf.cgs | 27 - sim/testsuite/sim/frv/ldhfi.cgs | 24 - sim/testsuite/sim/frv/ldhfu.cgs | 33 - sim/testsuite/sim/frv/ldi.cgs | 26 - sim/testsuite/sim/frv/ldq.cgs | 64 - sim/testsuite/sim/frv/ldqc.cgs | 60 - sim/testsuite/sim/frv/ldqcu.cgs | 57 - sim/testsuite/sim/frv/ldqf.cgs | 61 - sim/testsuite/sim/frv/ldqfi.cgs | 51 - sim/testsuite/sim/frv/ldqfu.cgs | 58 - sim/testsuite/sim/frv/ldqi.cgs | 51 - sim/testsuite/sim/frv/ldqu.cgs | 71 - sim/testsuite/sim/frv/ldsb.cgs | 27 - sim/testsuite/sim/frv/ldsbi.cgs | 24 - sim/testsuite/sim/frv/ldsbu.cgs | 40 - sim/testsuite/sim/frv/ldsh.cgs | 27 - sim/testsuite/sim/frv/ldshi.cgs | 24 - sim/testsuite/sim/frv/ldshu.cgs | 39 - sim/testsuite/sim/frv/ldu.cgs | 39 - sim/testsuite/sim/frv/ldub.cgs | 27 - sim/testsuite/sim/frv/ldubi.cgs | 24 - sim/testsuite/sim/frv/ldubu.cgs | 39 - sim/testsuite/sim/frv/lduh.cgs | 27 - sim/testsuite/sim/frv/lduhi.cgs | 24 - sim/testsuite/sim/frv/lduhu.cgs | 39 - sim/testsuite/sim/frv/lrbranch.pcgs | 51 - sim/testsuite/sim/frv/mabshs.cgs | 67 - sim/testsuite/sim/frv/maddhss.cgs | 100 - sim/testsuite/sim/frv/maddhus.cgs | 89 - sim/testsuite/sim/frv/mand.cgs | 23 - sim/testsuite/sim/frv/maveh.cgs | 72 - sim/testsuite/sim/frv/mbtoh.cgs | 20 - sim/testsuite/sim/frv/mbtohe.cgs | 24 - sim/testsuite/sim/frv/mclracc.cgs | 79 - sim/testsuite/sim/frv/mcmpsh.cgs | 138 - sim/testsuite/sim/frv/mcmpuh.cgs | 138 - sim/testsuite/sim/frv/mcop1.cgs | 40 - sim/testsuite/sim/frv/mcop2.cgs | 40 - sim/testsuite/sim/frv/mcplhi.cgs | 53 - sim/testsuite/sim/frv/mcpli.cgs | 61 - sim/testsuite/sim/frv/mcpxis.cgs | 115 - sim/testsuite/sim/frv/mcpxiu.cgs | 76 - sim/testsuite/sim/frv/mcpxrs.cgs | 115 - sim/testsuite/sim/frv/mcpxru.cgs | 94 - sim/testsuite/sim/frv/mcut.cgs | 509 - sim/testsuite/sim/frv/mcuti.cgs | 381 - sim/testsuite/sim/frv/mcutss.cgs | 505 - sim/testsuite/sim/frv/mcutssi.cgs | 380 - sim/testsuite/sim/frv/mdaddaccs.cgs | 102 - sim/testsuite/sim/frv/mdasaccs.cgs | 122 - sim/testsuite/sim/frv/mdcutssi.cgs | 513 - sim/testsuite/sim/frv/mdpackh.cgs | 18 - sim/testsuite/sim/frv/mdrotli.cgs | 34 - sim/testsuite/sim/frv/mdsubaccs.cgs | 102 - sim/testsuite/sim/frv/mdunpackh.cgs | 26 - sim/testsuite/sim/frv/membar.cgs | 12 - sim/testsuite/sim/frv/mexpdhd.cgs | 27 - sim/testsuite/sim/frv/mexpdhw.cgs | 23 - sim/testsuite/sim/frv/mhdseth.cgs | 26 - sim/testsuite/sim/frv/mhdsets.cgs | 26 - sim/testsuite/sim/frv/mhsethih.cgs | 26 - sim/testsuite/sim/frv/mhsethis.cgs | 26 - sim/testsuite/sim/frv/mhsetloh.cgs | 26 - sim/testsuite/sim/frv/mhsetlos.cgs | 26 - sim/testsuite/sim/frv/mhtob.cgs | 25 - sim/testsuite/sim/frv/mmachs.cgs | 259 - sim/testsuite/sim/frv/mmachu.cgs | 146 - sim/testsuite/sim/frv/mmrdhs.cgs | 263 - sim/testsuite/sim/frv/mmrdhu.cgs | 151 - sim/testsuite/sim/frv/mmulhs.cgs | 141 - sim/testsuite/sim/frv/mmulhu.cgs | 82 - sim/testsuite/sim/frv/mmulxhs.cgs | 141 - sim/testsuite/sim/frv/mmulxhu.cgs | 82 - sim/testsuite/sim/frv/mnop.cgs | 12 - sim/testsuite/sim/frv/mnot.cgs | 18 - sim/testsuite/sim/frv/mor.cgs | 25 - sim/testsuite/sim/frv/mov.cgs | 18 - sim/testsuite/sim/frv/movfg.cgs | 16 - sim/testsuite/sim/frv/movfgd.cgs | 20 - sim/testsuite/sim/frv/movfgq.cgs | 29 - sim/testsuite/sim/frv/movgf.cgs | 16 - sim/testsuite/sim/frv/movgfd.cgs | 20 - sim/testsuite/sim/frv/movgfq.cgs | 29 - sim/testsuite/sim/frv/movgs.cgs | 22 - sim/testsuite/sim/frv/movsg.cgs | 16 - sim/testsuite/sim/frv/mpackh.cgs | 15 - sim/testsuite/sim/frv/mqcpxis.cgs | 103 - sim/testsuite/sim/frv/mqcpxiu.cgs | 60 - sim/testsuite/sim/frv/mqcpxrs.cgs | 103 - sim/testsuite/sim/frv/mqcpxru.cgs | 78 - sim/testsuite/sim/frv/mqmachs.cgs | 211 - sim/testsuite/sim/frv/mqmachu.cgs | 144 - sim/testsuite/sim/frv/mqmacxhs.cgs | 211 - sim/testsuite/sim/frv/mqmulhs.cgs | 125 - sim/testsuite/sim/frv/mqmulhu.cgs | 80 - sim/testsuite/sim/frv/mqmulxhs.cgs | 125 - sim/testsuite/sim/frv/mqmulxhu.cgs | 80 - sim/testsuite/sim/frv/mqsaths.cgs | 50 - sim/testsuite/sim/frv/mqxmachs.cgs | 211 - sim/testsuite/sim/frv/mqxmacxhs.cgs | 211 - sim/testsuite/sim/frv/mrdacc.cgs | 26 - sim/testsuite/sim/frv/mrdaccg.cgs | 26 - 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sim/testsuite/sim/sh64/media/trapa.cgs create mode 100644 sim/testsuite/sim/sh64/media/xor.cgs create mode 100644 sim/testsuite/sim/sh64/media/xori.cgs create mode 100644 sim/testsuite/sim/sh64/misc/fr-dr.s diff --git a/COPYING.LIBGLOSS b/COPYING.LIBGLOSS deleted file mode 100644 index 741bc2fe0de..00000000000 --- a/COPYING.LIBGLOSS +++ /dev/null @@ -1,297 +0,0 @@ -The libgloss subdirectory is a collection of software from several sources. -Each have their own copyrights embedded in each file that they concern. - -(1) University of California, Berkeley - -[1a] - -Copyright (c) 1990 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms are permitted -provided that the above copyright notice and this paragraph are -duplicated in all such forms and that any documentation, -and other materials related to such distribution and use -acknowledge that the software was developed -by the University of California, Berkeley. The name of the -University may not be used to endorse or promote products derived -from this software without specific prior written permission. -THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR -IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. - -[1b] - -Copyright (c) 1991, 2000 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions -are met: -1. Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. -2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. -3. All advertising materials mentioning features or use of this software - must display the following acknowledgement: - This product includes software developed by the University of - California, Berkeley and its contributors. -4. Neither the name of the University nor the names of its contributors - may be used to endorse or promote products derived from this software - without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE -FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -SUCH DAMAGE. - -[1c] - -Copyright (c) 1991, 1998, 2001 The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions -are met: -1. Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. -2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. -3. [rescinded 22 July 1999] -4. Neither the name of the University nor the names of its contributors - may be used to endorse or promote products derived from this software - without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE -FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -SUCH DAMAGE. - -------------------------------------------------------------- - Please note that in some of the above alternate licenses, there is a - statement regarding that acknowledgement must be made in any - advertising materials for products using the code. This restriction - no longer applies due to the following license change: - - ftp://ftp.cs.berkeley.edu/pub/4bsd/README.Impt.License.Change - - In some cases the defunct clause has been removed in modified newlib code and - in some cases, the clause has been left as-is. -------------------------------------------------------------- - -(2) DJ Delorie - -Copyright (C) 1993 DJ Delorie -All rights reserved. - -Redistribution and use in source and binary forms is permitted -provided that the above copyright notice and following paragraph are -duplicated in all such forms. - -This file is distributed WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - -(3) GPL (fr30 directory only) - -Copyright (C) 1998 Free Software Foundation, Inc. -Contributed by Cygnus Solutions. - -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. - -(4) Advanced Micro Devices - -Copyright 1989, 1990 Advanced Micro Devices, Inc. - -This software is the property of Advanced Micro Devices, Inc (AMD) which -specifically grants the user the right to modify, use and distribute this -software provided this notice is not removed or altered. All other rights -are reserved by AMD. - -AMD MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS -SOFTWARE. IN NO EVENT SHALL AMD BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL -DAMAGES IN CONNECTION WITH OR ARISING FROM THE FURNISHING, PERFORMANCE, OR -USE OF THIS SOFTWARE. - -So that all may benefit from your experience, please report any problems -or suggestions about this software to the 29K Technical Support Center at -800-29-29-AMD (800-292-9263) in the USA, or 0800-89-1131 in the UK, or -0031-11-1129 in Japan, toll free. The direct dial number is 512-462-4118. - -Advanced Micro Devices, Inc. -29K Support Products -Mail Stop 573 -5900 E. Ben White Blvd. -Austin, TX 78741 -800-292-9263 - -(5) Array Technology Corporation and MIPS (mips/lsi33k-stub.h) - -COPYRIGHT (C) 1991, 1992 ARRAY TECHNOLOGY CORPORATION - All Rights Reserved - -This software is confidential information which is proprietary to and -a trade secret of ARRAY Technology Corporation. Use, duplication, or -disclosure is subject to the terms of a separate license agreement. - -Copyright 1985 by MIPS Computer Systems, Inc. - -(6) University of Utah and the Computer Systems Laboratory (CSL) - [applies only to hppa*-*-pro* targets] - -Copyright (c) 1990,1994 The University of Utah and -the Computer Systems Laboratory (CSL). All rights reserved. - -Permission to use, copy, modify and distribute this software is hereby -granted provided that (1) source code retains these copyright, permission, -and disclaimer notices, and (2) redistributions including binaries -reproduce the notices in supporting documentation, and (3) all advertising -materials mentioning features or use of this software display the following -acknowledgement: ``This product includes software developed by the -Computer Systems Laboratory at the University of Utah.'' - -THE UNIVERSITY OF UTAH AND CSL ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS -IS" CONDITION. THE UNIVERSITY OF UTAH AND CSL DISCLAIM ANY LIABILITY OF -ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. - -CSL requests users of this software to return to csl-dist@cs.utah.edu any -improvements that they make and grant CSL redistribution rights. - -(7) Sun Microsystems - -Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved. - -Developed at SunPro, a Sun Microsystems, Inc. business. -Permission to use, copy, modify, and distribute this -software is freely granted, provided that this notice -is preserved. - -(8) Hewlett Packard - -(c) Copyright 1986 HEWLETT-PACKARD COMPANY - -To anyone who acknowledges that this file is provided "AS IS" -without any express or implied warranty: - permission to use, copy, modify, and distribute this file -for any purpose is hereby granted without fee, provided that -the above copyright notice and this notice appears in all -copies, and that the name of Hewlett-Packard Company not be -used in advertising or publicity pertaining to distribution -of the software without specific, written prior permission. -Hewlett-Packard Company makes no representations about the -suitability of this software for any purpose. - -(9) Hans-Peter Nilsson - -Copyright (C) 2001 Hans-Peter Nilsson - -Permission to use, copy, modify, and distribute this software is -freely granted, provided that the above copyright notice, this notice -and the following disclaimer are preserved with no changes. - -THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR -IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -PURPOSE. - -(10) No Copyright - -THIS SOFTWARE IS NOT COPYRIGHTED - -(11) Cygnus Support / Cygnus Solutions - -Copyright (c) 1995, 1996, 1997, 1998, 1999 Cygnus Support - -The authors hereby grant permission to use, copy, modify, distribute, -and license this software and its documentation for any purpose, provided -that existing copyright notices are retained in all copies and that this -notice is included verbatim in any distributions. No written agreement, -license, or royalty fee is required for any of the authorized uses. -Modifications to this software may be copyrighted by their authors -and need not follow the licensing terms described here, provided that -the new terms are clearly indicated on the first page of each file where -they apply. - ---------------------------------------------------------------- - Please note that the copyright above may be used with the name - Cygnus Solutions instead of Cygnus Support. Both names should - be considered interchangeable. These copyrights are now owned - by Red Hat Incorporated. ---------------------------------------------------------------- - -(12) Red Hat Incorporated - -Copyright (c) 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. - -The authors hereby grant permission to use, copy, modify, distribute, -and license this software and its documentation for any purpose, provided -that existing copyright notices are retained in all copies and that this -notice is included verbatim in any distributions. No written agreement, -license, or royalty fee is required for any of the authorized uses. -Modifications to this software may be copyrighted by their authors -and need not follow the licensing terms described here, provided that -the new terms are clearly indicated on the first page of each file where -they apply. - -(13) Default copyright - -Unless otherwise stated in each remaining libgloss file, the remaining -files in the libgloss subdirectory are governed by the following copyright. - -Copyright (c) 1994, 1997, 2001, 2002 Red Hat Incorporated. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - The name of Red Hat Incorporated may not be used to endorse - or promote products derived from this software without specific - prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/ChangeLog b/ChangeLog index de6ebae1c77..f14b131f996 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,9 @@ +2004-03-01 Richard Sandiford + + * configure.in (mips64*-*-linux*): Override mips*-*-linux* case + and disable libgcj. + * configure: Regenerated. + 2004-02-28 Nathanael Nerode PR bootstrap/7087 diff --git a/bfd/ChangeLog b/bfd/ChangeLog index d091b86f39a..22ab879ae29 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,60 @@ +2004-03-09 Steve Ellcey + + * elfxx-ia64.c (plt_full_entry): Change ld8 to ld8.acq. + +2004-03-05 Fred Fish + + * elfxx-mips.c (_bfd_mips_elf_finish_dynamic_symbol): Just force + mips16 symbols to be even rather than testing first for even/odd. + (_bfd_mips_elf_link_output_symbol_hook): Ditto. + +2004-03-05 Nathan Sidwell + + * elf.c (map_sections_to_segments): Ignore .tbss sections for + layout purposes. + +2004-03-03 Alexandre Oliva + + * elflink.c (bfd_elf_record_link_assignment): Mark undefweak and + undefined symbols as hash_new. + +2003-03-03 Andrew Stubbs + + * archures.c: Add bfd_mach_sh4_nommu_nofpu. + * cpu-sh.c: Ditto. + * elf32-sh.c: Ditto. + * bfd-in2.h: Regenerate. + +2004-03-02 Alexandre Oliva + + * elf32-frv.c (struct frv_pic_relocs_info): Added fixups and + dynrelocs. + (_frv_count_got_plt_entries): Initialize them. + (frv_pic_relocs_info_find): Add insert argument. Adjust all + callers. + (frv_pic_relocs_info_for_global): Likewise. + (frv_pic_relocs_info_for_local): Likewise. + (frv_pic_merge_early_relocs_info): New. + (_frv_resolve_final_relocs_info): Use it in case one entry maps to + another. + (_frv_add_dyn_reloc): Add entry argument. Adjust all callers. + Check that we don't exceed the allocated count for entry. + (_frv_add_rofixup): Likewise. + (_frv_emit_got_relocs_plt_entries): Adjust for coding standards. + (elf32_frv_finish_dynamic_sections): Improve error message in case + we emit too few rofixup entries. + +2004-03-01 Richard Sandiford + + * archures.c (bfd_mach_fr450): New. + * bfd-in2.h: Regenerate. + * cpu-frv.c (arch_info_450): New bfd_arch_info_type. + (arch_info_500): Link to it. + * elf32-frv.c (elf32_frv_machine, frv_elf_merge_private_bfd_data) + (frv_elf_print_private_bfd_data): Handle fr405 and fr450 header flags. + (frv_elf_arch_extension_p): New function. + (frv_elf_merge_private_bfd_data): Use it. + 2004-02-28 H.J. Lu * elf-bfd.h (_bfd_elf_link_add_archive_symbols): New prototype. diff --git a/bfd/archures.c b/bfd/archures.c index f8aeeef8838..0e2a08b831f 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -1,6 +1,6 @@ /* BFD library support routines for architectures. Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2000, 2001, 2002, 2003 + 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. Hacked by John Gilmore and Steve Chamberlain of Cygnus Support. @@ -230,6 +230,7 @@ DESCRIPTION .#define bfd_mach_sh3e 0x3e .#define bfd_mach_sh4 0x40 .#define bfd_mach_sh4_nofpu 0x41 +.#define bfd_mach_sh4_nommu_nofpu 0x42 .#define bfd_mach_sh4a 0x4a .#define bfd_mach_sh4a_nofpu 0x4b .#define bfd_mach_sh4al_dsp 0x4d @@ -285,6 +286,7 @@ DESCRIPTION .#define bfd_mach_frvsimple 2 .#define bfd_mach_fr300 300 .#define bfd_mach_fr400 400 +.#define bfd_mach_fr450 450 .#define bfd_mach_frvtomcat 499 {* fr500 prototype *} .#define bfd_mach_fr500 500 .#define bfd_mach_fr550 550 diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index 74bbccdac48..5963bb4e35c 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -1662,6 +1662,7 @@ enum bfd_architecture #define bfd_mach_sh3e 0x3e #define bfd_mach_sh4 0x40 #define bfd_mach_sh4_nofpu 0x41 +#define bfd_mach_sh4_nommu_nofpu 0x42 #define bfd_mach_sh4a 0x4a #define bfd_mach_sh4a_nofpu 0x4b #define bfd_mach_sh4al_dsp 0x4d @@ -1717,6 +1718,7 @@ enum bfd_architecture #define bfd_mach_frvsimple 2 #define bfd_mach_fr300 300 #define bfd_mach_fr400 400 +#define bfd_mach_fr450 450 #define bfd_mach_frvtomcat 499 /* fr500 prototype */ #define bfd_mach_fr500 500 #define bfd_mach_fr550 550 diff --git a/bfd/cpu-frv.c b/bfd/cpu-frv.c index f911881a505..499c66d48da 100644 --- a/bfd/cpu-frv.c +++ b/bfd/cpu-frv.c @@ -43,8 +43,11 @@ static const bfd_arch_info_type arch_info_300 static const bfd_arch_info_type arch_info_400 = FRV_ARCH (bfd_mach_fr400, "fr400", FALSE, &arch_info_300); +static const bfd_arch_info_type arch_info_450 + = FRV_ARCH (bfd_mach_fr450, "fr450", FALSE, &arch_info_400); + static const bfd_arch_info_type arch_info_500 - = FRV_ARCH (bfd_mach_fr500, "fr500", FALSE, &arch_info_400); + = FRV_ARCH (bfd_mach_fr500, "fr500", FALSE, &arch_info_450); static const bfd_arch_info_type arch_info_550 = FRV_ARCH (bfd_mach_fr550, "fr550", FALSE, &arch_info_500); diff --git a/bfd/cpu-sh.c b/bfd/cpu-sh.c index 2f33240bb07..be359df7090 100644 --- a/bfd/cpu-sh.c +++ b/bfd/cpu-sh.c @@ -1,5 +1,5 @@ /* BFD library support routines for the Renesas / SuperH SH architecture. - Copyright 1993, 1994, 1997, 1998, 2000, 2001, 2002, 2003 + Copyright 1993, 1994, 1997, 1998, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. Hacked by Steve Chamberlain of Cygnus Support. @@ -34,7 +34,8 @@ #define SH4A_NEXT &arch_info_struct[8] #define SH4AL_DSP_NEXT &arch_info_struct[9] #define SH4_NOFPU_NEXT &arch_info_struct[10] -#define SH4A_NOFPU_NEXT &arch_info_struct[11] +#define SH4_NOMMU_NOFPU_NEXT &arch_info_struct[11] +#define SH4A_NOFPU_NEXT &arch_info_struct[12] #define SH64_NEXT NULL static const bfd_arch_info_type arch_info_struct[] = @@ -179,6 +180,20 @@ static const bfd_arch_info_type arch_info_struct[] = bfd_default_scan, SH4_NOFPU_NEXT }, + { + 32, /* 32 bits in a word */ + 32, /* 32 bits in an address */ + 8, /* 8 bits in a byte */ + bfd_arch_sh, + bfd_mach_sh4_nommu_nofpu, + "sh", /* arch_name */ + "sh4-nommu-nofpu", /* printable name */ + 1, + FALSE, /* not the default */ + bfd_default_compatible, + bfd_default_scan, + SH4_NOMMU_NOFPU_NEXT + }, { 32, /* 32 bits in a word */ 32, /* 32 bits in an address */ diff --git a/bfd/elf.c b/bfd/elf.c index 5e31f893583..33b58f5bead 100644 --- a/bfd/elf.c +++ b/bfd/elf.c @@ -3360,7 +3360,9 @@ map_sections_to_segments (bfd *abfd) { if ((hdr->flags & SEC_READONLY) == 0) writable = TRUE; - last_hdr = hdr; + /* Ignore .tbss section for segment layout purposes. */ + if ((hdr->flags & (SEC_THREAD_LOCAL | SEC_LOAD)) != SEC_THREAD_LOCAL) + last_hdr = hdr; continue; } diff --git a/bfd/elf32-frv.c b/bfd/elf32-frv.c index a813ddcd8cc..de7a1132160 100644 --- a/bfd/elf32-frv.c +++ b/bfd/elf32-frv.c @@ -748,6 +748,10 @@ struct frv_pic_relocs_info relocations referencing the symbol. */ unsigned relocs32, relocsfd, relocsfdv; + /* The number of .rofixups entries and dynamic relocations allocated + for this symbol, minus any that might have already been used. */ + unsigned fixups, dynrelocs; + /* The offsets of the GOT entries assigned to symbol+addend, to the function descriptor's address, and to a function descriptor, respectively. Should be zero if unassigned. The offsets are @@ -789,10 +793,14 @@ frv_pic_relocs_info_eq (const void *entry1, const void *entry2) static struct frv_pic_relocs_info * frv_pic_relocs_info_find (struct htab *ht, bfd *abfd, - const struct frv_pic_relocs_info *entry) + const struct frv_pic_relocs_info *entry, + enum insert_option insert) { struct frv_pic_relocs_info **loc = - (struct frv_pic_relocs_info **) htab_find_slot (ht, entry, INSERT); + (struct frv_pic_relocs_info **) htab_find_slot (ht, entry, insert); + + if (! loc) + return NULL; if (*loc) return *loc; @@ -818,7 +826,8 @@ inline static struct frv_pic_relocs_info * frv_pic_relocs_info_for_global (struct htab *ht, bfd *abfd, struct elf_link_hash_entry *h, - bfd_vma addend) + bfd_vma addend, + enum insert_option insert) { struct frv_pic_relocs_info entry; @@ -826,7 +835,7 @@ frv_pic_relocs_info_for_global (struct htab *ht, entry.d.h = h; entry.addend = addend; - return frv_pic_relocs_info_find (ht, abfd, &entry); + return frv_pic_relocs_info_find (ht, abfd, &entry, insert); } /* Obtain the address of the entry in HT associated with the SYMNDXth @@ -836,7 +845,8 @@ inline static struct frv_pic_relocs_info * frv_pic_relocs_info_for_local (struct htab *ht, bfd *abfd, long symndx, - bfd_vma addend) + bfd_vma addend, + enum insert_option insert) { struct frv_pic_relocs_info entry; @@ -844,7 +854,59 @@ frv_pic_relocs_info_for_local (struct htab *ht, entry.d.abfd = abfd; entry.addend = addend; - return frv_pic_relocs_info_find (ht, abfd, &entry); + return frv_pic_relocs_info_find (ht, abfd, &entry, insert); +} + +/* Merge fields set by check_relocs() of two entries that end up being + mapped to the same (presumably global) symbol. */ + +inline static void +frv_pic_merge_early_relocs_info (struct frv_pic_relocs_info *e2, + struct frv_pic_relocs_info const *e1) +{ + e2->got12 |= e1->got12; + e2->gotlos |= e1->gotlos; + e2->gothilo |= e1->gothilo; + e2->fd |= e1->fd; + e2->fdgot12 |= e1->fdgot12; + e2->fdgotlos |= e1->fdgotlos; + e2->fdgothilo |= e1->fdgothilo; + e2->fdgoff12 |= e1->fdgoff12; + e2->fdgofflos |= e1->fdgofflos; + e2->fdgoffhilo |= e1->fdgoffhilo; + e2->gotoff |= e1->gotoff; + e2->call |= e1->call; + e2->sym |= e1->sym; + +#if 0 + /* These are set in _frv_count_got_plt_entries() or later, and this + function is only called in _frv_resolve_final_relocs_info(), that + runs just before it, so we don't have to worry about the fields + below. */ + + e2->plt |= e1->plt; + e2->privfd |= e1->privfd; + e2->lazyplt |= e1->lazyplt; + e2->done |= e1->done; + + e2->relocs32 += e1->relocs32; + e2->relocsfd += e1->relocsfd; + e2->relocsfdv += e1->relocsfdv; + e2->fixups += e1->fixups; + e2->dynrelocs += e1->dynrelocs; + + if (abs (e1->got_entry) < abs (e2->got_entry)) + e2->got_entry = e1->got_entry; + if (abs (e1->fdgot_entry) < abs (e2->fdgot_entry)) + e2->fdgot_entry = e1->fdgot_entry; + if (abs (e1->fd_entry) < abs (e2->fd_entry)) + e2->fd_entry = e1->fd_entry; + + if (e1->plt_entry < e2->plt_entry) + e2->plt_entry = e1->plt_entry; + if (e1->lzplt_entry < e2->lzplt_entry) + e2->lzplt_entry = e1->lzplt_entry; +#endif } /* Every block of 65535 lazy PLT entries shares a single call to the @@ -859,7 +921,8 @@ frv_pic_relocs_info_for_local (struct htab *ht, inline static bfd_vma _frv_add_dyn_reloc (bfd *output_bfd, asection *sreloc, bfd_vma offset, - int reloc_type, long dynindx, bfd_vma addend) + int reloc_type, long dynindx, bfd_vma addend, + struct frv_pic_relocs_info *entry) { Elf_Internal_Rela outrel; bfd_vma reloc_offset; @@ -874,13 +937,17 @@ _frv_add_dyn_reloc (bfd *output_bfd, asection *sreloc, bfd_vma offset, sreloc->contents + reloc_offset); sreloc->reloc_count++; + BFD_ASSERT (entry->dynrelocs > 0); + entry->dynrelocs--; + return reloc_offset; } /* Add a fixup to the ROFIXUP section. */ static bfd_vma -_frv_add_rofixup (bfd *output_bfd, asection *rofixup, bfd_vma offset) +_frv_add_rofixup (bfd *output_bfd, asection *rofixup, bfd_vma offset, + struct frv_pic_relocs_info *entry) { bfd_vma fixup_offset; @@ -894,7 +961,13 @@ _frv_add_rofixup (bfd *output_bfd, asection *rofixup, bfd_vma offset) bfd_put_32 (output_bfd, offset, rofixup->contents + fixup_offset); } rofixup->reloc_count++; - + + if (entry) + { + BFD_ASSERT (entry->fixups > 0); + entry->fixups--; + } + return fixup_offset; } @@ -999,13 +1072,13 @@ _frv_emit_got_relocs_plt_entries (struct frv_pic_relocs_info *entry, { if (sec) ad += sec->output_section->vma; - if (entry->symndx != -1 || - entry->d.h->root.type != bfd_link_hash_undefweak) + if (entry->symndx != -1 + || entry->d.h->root.type != bfd_link_hash_undefweak) _frv_add_rofixup (output_bfd, frv_gotfixup_section (info), frv_got_section (info)->output_section->vma + frv_got_section (info)->output_offset + frv_got_initial_offset (info) - + entry->got_entry); + + entry->got_entry, entry); } else _frv_add_dyn_reloc (output_bfd, frv_gotrel_section (info), @@ -1016,7 +1089,7 @@ _frv_emit_got_relocs_plt_entries (struct frv_pic_relocs_info *entry, + entry->got_entry) + frv_got_section (info)->output_section->vma + frv_got_section (info)->output_offset, - R_FRV_32, idx, ad); + R_FRV_32, idx, ad, entry); bfd_put_32 (output_bfd, ad, frv_got_section (info)->contents @@ -1089,7 +1162,7 @@ _frv_emit_got_relocs_plt_entries (struct frv_pic_relocs_info *entry, frv_got_section (info)->output_section->vma + frv_got_section (info)->output_offset + frv_got_initial_offset (info) - + entry->fdgot_entry); + + entry->fdgot_entry, entry); } else _frv_add_dyn_reloc (output_bfd, frv_gotrel_section (info), @@ -1100,7 +1173,7 @@ _frv_emit_got_relocs_plt_entries (struct frv_pic_relocs_info *entry, + entry->fdgot_entry) + frv_got_section (info)->output_section->vma + frv_got_section (info)->output_offset, - reloc, idx, ad); + reloc, idx, ad, entry); } bfd_put_32 (output_bfd, ad, @@ -1142,19 +1215,19 @@ _frv_emit_got_relocs_plt_entries (struct frv_pic_relocs_info *entry, if (sec) ad += sec->output_section->vma; ofst = 0; - if (entry->symndx != -1 || - entry->d.h->root.type != bfd_link_hash_undefweak) + if (entry->symndx != -1 + || entry->d.h->root.type != bfd_link_hash_undefweak) { _frv_add_rofixup (output_bfd, frv_gotfixup_section (info), frv_got_section (info)->output_section->vma + frv_got_section (info)->output_offset + frv_got_initial_offset (info) - + entry->fd_entry); + + entry->fd_entry, entry); _frv_add_rofixup (output_bfd, frv_gotfixup_section (info), frv_got_section (info)->output_section->vma + frv_got_section (info)->output_offset + frv_got_initial_offset (info) - + entry->fd_entry + 4); + + entry->fd_entry + 4, entry); } } else @@ -1170,7 +1243,7 @@ _frv_emit_got_relocs_plt_entries (struct frv_pic_relocs_info *entry, + entry->fd_entry) + frv_got_section (info)->output_section->vma + frv_got_section (info)->output_offset, - R_FRV_FUNCDESC_VALUE, idx, ad); + R_FRV_FUNCDESC_VALUE, idx, ad, entry); } /* If we've omitted the dynamic relocation, just emit the fixed @@ -1922,14 +1995,14 @@ elf32_frv_relocate_section (output_bfd, info, input_bfd, input_section, if (h != NULL) picrel = frv_pic_relocs_info_for_global (frv_relocs_info (info), input_bfd, h, - orig_addend); + orig_addend, INSERT); else /* In order to find the entry we created before, we must use the original addend, not the one that may have been modified by _bfd_elf_rela_local_sym(). */ picrel = frv_pic_relocs_info_for_local (frv_relocs_info (info), input_bfd, r_symndx, - orig_addend); + orig_addend, INSERT); if (! picrel) return FALSE; @@ -2092,7 +2165,8 @@ elf32_frv_relocate_section (output_bfd, info, input_bfd, input_section, (output_bfd, info, input_section, rel->r_offset) + input_section->output_section->vma - + input_section->output_offset); + + input_section->output_offset, + picrel); } } else if ((bfd_get_section_flags (output_bfd, @@ -2114,7 +2188,7 @@ elf32_frv_relocate_section (output_bfd, info, input_bfd, input_section, input_section, rel->r_offset) + input_section->output_section->vma + input_section->output_offset, - r_type, dynindx, addend); + r_type, dynindx, addend, picrel); } } @@ -2192,7 +2266,8 @@ elf32_frv_relocate_section (output_bfd, info, input_bfd, input_section, (output_bfd, info, input_section, rel->r_offset) + input_section->output_section->vma - + input_section->output_offset); + + input_section->output_offset, + picrel); if (r_type == R_FRV_FUNCDESC_VALUE) _frv_add_rofixup (output_bfd, @@ -2201,7 +2276,7 @@ elf32_frv_relocate_section (output_bfd, info, input_bfd, input_section, (output_bfd, info, input_section, rel->r_offset) + input_section->output_section->vma - + input_section->output_offset + 4); + + input_section->output_offset + 4, picrel); } } } @@ -2226,7 +2301,7 @@ elf32_frv_relocate_section (output_bfd, info, input_bfd, input_section, input_section, rel->r_offset) + input_section->output_section->vma + input_section->output_offset, - r_type, dynindx, addend); + r_type, dynindx, addend, picrel); } /* We want the addend in-place because dynamic relocations are REL. Setting relocation to it @@ -2806,6 +2881,7 @@ _frv_count_got_plt_entries (void **entryp, void *dinfo_) { struct frv_pic_relocs_info *entry = *entryp; struct _frv_dynamic_got_info *dinfo = dinfo_; + unsigned relocs = 0, fixups = 0; /* Allocate space for a GOT entry pointing to the symbol. */ if (entry->got12) @@ -2862,27 +2938,33 @@ _frv_count_got_plt_entries (void **entryp, void *dinfo_) dinfo->lzplt += 8; if (!dinfo->info->executable || dinfo->info->pie) - dinfo->relocs += entry->relocs32 + entry->relocsfd + entry->relocsfdv; + relocs = entry->relocs32 + entry->relocsfd + entry->relocsfdv; else { if (entry->symndx != -1 || FRV_SYM_LOCAL (dinfo->info, entry->d.h)) { if (entry->symndx != -1 - || entry->d.h->root.type != bfd_link_hash_undefweak) - dinfo->fixups += entry->relocs32 + 2 * entry->relocsfdv; + || entry->d.h->root.type != bfd_link_hash_undefweak) + fixups += entry->relocs32 + 2 * entry->relocsfdv; } else - dinfo->relocs += entry->relocs32 + entry->relocsfdv; + relocs += entry->relocs32 + entry->relocsfdv; + if (entry->symndx != -1 || FRV_FUNCDESC_LOCAL (dinfo->info, entry->d.h)) { if (entry->symndx != -1 || entry->d.h->root.type != bfd_link_hash_undefweak) - dinfo->fixups += entry->relocsfd; + fixups += entry->relocsfd; } else - dinfo->relocs += entry->relocsfd; + relocs += entry->relocsfd; } + entry->dynrelocs += relocs; + entry->fixups += fixups; + dinfo->relocs += relocs; + dinfo->fixups += fixups; + return 1; } @@ -3210,6 +3292,7 @@ _frv_resolve_final_relocs_info (void **entryp, void *p) if (entry->symndx == -1) { struct elf_link_hash_entry *h = entry->d.h; + struct frv_pic_relocs_info *oentry; while (h->root.type == bfd_link_hash_indirect || h->root.type == bfd_link_hash_warning) @@ -3218,6 +3301,17 @@ _frv_resolve_final_relocs_info (void **entryp, void *p) if (entry->d.h == h) return 1; + oentry = frv_pic_relocs_info_for_global (*htab, 0, h, entry->addend, + NO_INSERT); + + if (oentry) + { + /* Merge the two entries. */ + frv_pic_merge_early_relocs_info (oentry, entry); + htab_clear_slot (*htab, entryp); + return 1; + } + entry->d.h = h; /* If we can't find this entry with the new bfd hash, re-insert @@ -3581,13 +3675,22 @@ elf32_frv_finish_dynamic_sections (bfd *output_bfd, + hgot->root.u.def.section->output_offset; _frv_add_rofixup (output_bfd, frv_gotfixup_section (info), - got_value); + got_value, 0); } if (frv_gotfixup_section (info)->_raw_size != (frv_gotfixup_section (info)->reloc_count * 4)) { - if (!elf_hash_table (info)->dynamic_sections_created) + if (frv_gotfixup_section (info)->_raw_size + < frv_gotfixup_section (info)->reloc_count * 4) + { + info->callbacks->warning + (info, "LINKER BUG: .rofixup section size mismatch", + ".rofixup", NULL, NULL, 0); + abort (); + return FALSE; + } + else if (!elf_hash_table (info)->dynamic_sections_created) { info->callbacks->warning (info, "no dynamic sections, missing -melf32frvfd?", @@ -3931,12 +4034,12 @@ elf32_frv_check_relocs (abfd, info, sec, relocs) picrel = frv_pic_relocs_info_for_global (frv_relocs_info (info), abfd, h, - rel->r_addend); + rel->r_addend, INSERT); } else picrel = frv_pic_relocs_info_for_local (frv_relocs_info (info), abfd, r_symndx, - rel->r_addend); + rel->r_addend, INSERT); if (! picrel) return FALSE; break; @@ -4032,6 +4135,8 @@ elf32_frv_machine (abfd) default: break; case EF_FRV_CPU_FR550: return bfd_mach_fr550; case EF_FRV_CPU_FR500: return bfd_mach_fr500; + case EF_FRV_CPU_FR450: return bfd_mach_fr450; + case EF_FRV_CPU_FR405: return bfd_mach_fr400; case EF_FRV_CPU_FR400: return bfd_mach_fr400; case EF_FRV_CPU_FR300: return bfd_mach_fr300; case EF_FRV_CPU_SIMPLE: return bfd_mach_frvsimple; @@ -4082,6 +4187,33 @@ frv_elf_copy_private_bfd_data (ibfd, obfd) return TRUE; } +/* Return true if the architecture described by elf header flag + EXTENSION is an extension of the architecture described by BASE. */ + +static bfd_boolean +frv_elf_arch_extension_p (flagword base, flagword extension) +{ + if (base == extension) + return TRUE; + + /* CPU_GENERIC code can be merged with code for a specific + architecture, in which case the result is marked as being + for the specific architecture. Everything is therefore + an extension of CPU_GENERIC. */ + if (base == EF_FRV_CPU_GENERIC) + return TRUE; + + if (extension == EF_FRV_CPU_FR450) + if (base == EF_FRV_CPU_FR400 || base == EF_FRV_CPU_FR405) + return TRUE; + + if (extension == EF_FRV_CPU_FR405) + if (base == EF_FRV_CPU_FR400) + return TRUE; + + return FALSE; +} + /* Merge backend specific data from an object file to the output object file when linking. */ @@ -4266,13 +4398,10 @@ frv_elf_merge_private_bfd_data (ibfd, obfd) the generic cpu). */ new_partial = (new_flags & EF_FRV_CPU_MASK); old_partial = (old_flags & EF_FRV_CPU_MASK); - if (new_partial == old_partial) - ; - - else if (new_partial == EF_FRV_CPU_GENERIC) + if (frv_elf_arch_extension_p (new_partial, old_partial)) ; - else if (old_partial == EF_FRV_CPU_GENERIC) + else if (frv_elf_arch_extension_p (old_partial, new_partial)) old_flags = (old_flags & ~EF_FRV_CPU_MASK) | new_partial; else @@ -4284,6 +4413,8 @@ frv_elf_merge_private_bfd_data (ibfd, obfd) case EF_FRV_CPU_SIMPLE: strcat (new_opt, " -mcpu=simple"); break; case EF_FRV_CPU_FR550: strcat (new_opt, " -mcpu=fr550"); break; case EF_FRV_CPU_FR500: strcat (new_opt, " -mcpu=fr500"); break; + case EF_FRV_CPU_FR450: strcat (new_opt, " -mcpu=fr450"); break; + case EF_FRV_CPU_FR405: strcat (new_opt, " -mcpu=fr405"); break; case EF_FRV_CPU_FR400: strcat (new_opt, " -mcpu=fr400"); break; case EF_FRV_CPU_FR300: strcat (new_opt, " -mcpu=fr300"); break; case EF_FRV_CPU_TOMCAT: strcat (new_opt, " -mcpu=tomcat"); break; @@ -4296,6 +4427,8 @@ frv_elf_merge_private_bfd_data (ibfd, obfd) case EF_FRV_CPU_SIMPLE: strcat (old_opt, " -mcpu=simple"); break; case EF_FRV_CPU_FR550: strcat (old_opt, " -mcpu=fr550"); break; case EF_FRV_CPU_FR500: strcat (old_opt, " -mcpu=fr500"); break; + case EF_FRV_CPU_FR450: strcat (old_opt, " -mcpu=fr450"); break; + case EF_FRV_CPU_FR405: strcat (old_opt, " -mcpu=fr405"); break; case EF_FRV_CPU_FR400: strcat (old_opt, " -mcpu=fr400"); break; case EF_FRV_CPU_FR300: strcat (old_opt, " -mcpu=fr300"); break; case EF_FRV_CPU_TOMCAT: strcat (old_opt, " -mcpu=tomcat"); break; @@ -4363,6 +4496,8 @@ frv_elf_print_private_bfd_data (abfd, ptr) case EF_FRV_CPU_SIMPLE: fprintf (file, " -mcpu=simple"); break; case EF_FRV_CPU_FR550: fprintf (file, " -mcpu=fr550"); break; case EF_FRV_CPU_FR500: fprintf (file, " -mcpu=fr500"); break; + case EF_FRV_CPU_FR450: fprintf (file, " -mcpu=fr450"); break; + case EF_FRV_CPU_FR405: fprintf (file, " -mcpu=fr405"); break; case EF_FRV_CPU_FR400: fprintf (file, " -mcpu=fr400"); break; case EF_FRV_CPU_FR300: fprintf (file, " -mcpu=fr300"); break; case EF_FRV_CPU_TOMCAT: fprintf (file, " -mcpu=tomcat"); break; diff --git a/bfd/elf32-sh.c b/bfd/elf32-sh.c index c8a091d53ce..5ab56bcc141 100644 --- a/bfd/elf32-sh.c +++ b/bfd/elf32-sh.c @@ -1,5 +1,5 @@ /* Renesas / SuperH SH specific support for 32-bit ELF - Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. Contributed by Ian Lance Taylor, Cygnus Support. @@ -6876,6 +6876,9 @@ sh_elf_set_mach_from_flags (bfd *abfd) case EF_SH4AL_DSP: bfd_default_set_arch_mach (abfd, bfd_arch_sh, bfd_mach_sh4al_dsp); break; + case EF_SH4_NOMMU_NOFPU: + bfd_default_set_arch_mach (abfd, bfd_arch_sh, bfd_mach_sh4_nommu_nofpu); + break; default: return FALSE; } diff --git a/bfd/elflink.c b/bfd/elflink.c index b992c39cb18..50513648db6 100644 --- a/bfd/elflink.c +++ b/bfd/elflink.c @@ -430,6 +430,13 @@ bfd_elf_record_link_assignment (bfd *output_bfd ATTRIBUTE_UNUSED, if (h == NULL) return FALSE; + /* Since we're defining the symbol, don't let it seem to have not + been defined. record_dynamic_symbol and size_dynamic_sections + may depend on this. */ + if (h->root.type == bfd_link_hash_undefweak + || h->root.type == bfd_link_hash_undefined) + h->root.type = bfd_link_hash_new; + if (h->root.type == bfd_link_hash_new) h->elf_link_hash_flags &= ~ELF_LINK_NON_ELF; diff --git a/bfd/elfxx-ia64.c b/bfd/elfxx-ia64.c index 878511bb828..9c65696790f 100644 --- a/bfd/elfxx-ia64.c +++ b/bfd/elfxx-ia64.c @@ -635,7 +635,7 @@ static const bfd_byte plt_min_entry[PLT_MIN_ENTRY_SIZE] = static const bfd_byte plt_full_entry[PLT_FULL_ENTRY_SIZE] = { 0x0b, 0x78, 0x00, 0x02, 0x00, 0x24, /* [MMI] addl r15=0,r1;; */ - 0x00, 0x41, 0x3c, 0x30, 0x28, 0xc0, /* ld8 r16=[r15],8 */ + 0x00, 0x41, 0x3c, 0x70, 0x29, 0xc0, /* ld8.acq r16=[r15],8*/ 0x01, 0x08, 0x00, 0x84, /* mov r14=r1;; */ 0x11, 0x08, 0x00, 0x1e, 0x18, 0x10, /* [MIB] ld8 r1=[r15] */ 0x60, 0x80, 0x04, 0x80, 0x03, 0x00, /* mov b6=r16 */ diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c index f072f2627dd..17d5b02bc26 100644 --- a/bfd/elfxx-mips.c +++ b/bfd/elfxx-mips.c @@ -1,6 +1,6 @@ /* MIPS-specific support for ELF Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, - 2003 Free Software Foundation, Inc. + 2003, 2004 Free Software Foundation, Inc. Most of the information added by Ian Lance Taylor, Cygnus Support, . @@ -4891,9 +4891,8 @@ _bfd_mips_elf_link_output_symbol_hook && strcmp (input_sec->name, ".scommon") == 0) sym->st_shndx = SHN_MIPS_SCOMMON; - if (sym->st_other == STO_MIPS16 - && (sym->st_value & 1) != 0) - --sym->st_value; + if (sym->st_other == STO_MIPS16) + sym->st_value &= ~1; return TRUE; } @@ -6814,9 +6813,8 @@ _bfd_mips_elf_finish_dynamic_symbol (bfd *output_bfd, } /* If this is a mips16 symbol, force the value to be even. */ - if (sym->st_other == STO_MIPS16 - && (sym->st_value & 1) != 0) - --sym->st_value; + if (sym->st_other == STO_MIPS16) + sym->st_value &= ~1; return TRUE; } diff --git a/bfd/version.h b/bfd/version.h index 7a3a027d926..819f71effc2 100644 --- a/bfd/version.h +++ b/bfd/version.h @@ -1,3 +1,3 @@ -#define BFD_VERSION_DATE 20040301 +#define BFD_VERSION_DATE 20040309 #define BFD_VERSION @bfd_version@ #define BFD_VERSION_STRING @bfd_version_string@ diff --git a/configure b/configure index 13384a42ba8..29a93196816 100755 --- a/configure +++ b/configure @@ -1429,6 +1429,9 @@ case "${target}" in mipstx39-*-*) noconfigdirs="$noconfigdirs gprof ${libgcj}" # same as generic mips ;; + mips64*-*-linux*) + noconfigdirs="$noconfigdirs target-newlib ${libgcj}" + ;; mips*-*-linux*) noconfigdirs="$noconfigdirs target-newlib target-libgloss" ;; @@ -2852,7 +2855,7 @@ test -n "$target_alias" && ncn_target_tool_prefix=$target_alias- # Extract the first word of "${ncn_tool_prefix}ar", so it can be a program name with args. set dummy ${ncn_tool_prefix}ar; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2856: checking for $ac_word" >&5 +echo "configure:2859: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_AR'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2885,7 +2888,7 @@ if test -z "$ac_cv_prog_AR" ; then # Extract the first word of "ar", so it can be a program name with args. set dummy ar; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2889: checking for $ac_word" >&5 +echo "configure:2892: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_ncn_cv_AR'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2924,7 +2927,7 @@ fi # Extract the first word of "${ncn_tool_prefix}as", so it can be a program name with args. set dummy ${ncn_tool_prefix}as; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2928: checking for $ac_word" >&5 +echo "configure:2931: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_AS'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2957,7 +2960,7 @@ if test -z "$ac_cv_prog_AS" ; then # Extract the first word of "as", so it can be a program name with args. set dummy as; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2961: checking for $ac_word" >&5 +echo "configure:2964: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_ncn_cv_AS'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2996,7 +2999,7 @@ fi # Extract the first word of "${ncn_tool_prefix}dlltool", so it can be a program name with args. set dummy ${ncn_tool_prefix}dlltool; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3000: checking for $ac_word" >&5 +echo "configure:3003: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_DLLTOOL'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3029,7 +3032,7 @@ if test -z "$ac_cv_prog_DLLTOOL" ; then # Extract the first word of "dlltool", so it can be a program name with args. set dummy dlltool; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3033: checking for $ac_word" >&5 +echo "configure:3036: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_ncn_cv_DLLTOOL'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3068,7 +3071,7 @@ fi # Extract the first word of "${ncn_tool_prefix}ld", so it can be a program name with args. set dummy ${ncn_tool_prefix}ld; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3072: checking for $ac_word" >&5 +echo "configure:3075: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_LD'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3101,7 +3104,7 @@ if test -z "$ac_cv_prog_LD" ; then # Extract the first word of "ld", so it can be a program name with args. set dummy ld; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3105: checking for $ac_word" >&5 +echo "configure:3108: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_ncn_cv_LD'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3140,7 +3143,7 @@ fi # Extract the first word of "${ncn_tool_prefix}nm", so it can be a program name with args. set dummy ${ncn_tool_prefix}nm; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3144: checking for $ac_word" >&5 +echo "configure:3147: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_NM'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3173,7 +3176,7 @@ if test -z "$ac_cv_prog_NM" ; then # Extract the first word of "nm", so it can be a program name with args. set dummy nm; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3177: checking for $ac_word" >&5 +echo "configure:3180: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_ncn_cv_NM'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3212,7 +3215,7 @@ fi # Extract the first word of "${ncn_tool_prefix}ranlib", so it can be a program name with args. set dummy ${ncn_tool_prefix}ranlib; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3216: checking for $ac_word" >&5 +echo "configure:3219: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3245,7 +3248,7 @@ if test -z "$ac_cv_prog_RANLIB" ; then # Extract the first word of "ranlib", so it can be a program name with args. set dummy ranlib; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3249: checking for $ac_word" >&5 +echo "configure:3252: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_ncn_cv_RANLIB'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3284,7 +3287,7 @@ fi # Extract the first word of "${ncn_tool_prefix}windres", so it can be a program name with args. set dummy ${ncn_tool_prefix}windres; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3288: checking for $ac_word" >&5 +echo "configure:3291: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_WINDRES'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3317,7 +3320,7 @@ if test -z "$ac_cv_prog_WINDRES" ; then # Extract the first word of "windres", so it can be a program name with args. set dummy windres; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3321: checking for $ac_word" >&5 +echo "configure:3324: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_ncn_cv_WINDRES'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3356,7 +3359,7 @@ fi # Extract the first word of "${ncn_tool_prefix}objcopy", so it can be a program name with args. set dummy ${ncn_tool_prefix}objcopy; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3360: checking for $ac_word" >&5 +echo "configure:3363: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_OBJCOPY'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3389,7 +3392,7 @@ if test -z "$ac_cv_prog_OBJCOPY" ; then # Extract the first word of "objcopy", so it can be a program name with args. set dummy objcopy; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3393: checking for $ac_word" >&5 +echo "configure:3396: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_ncn_cv_OBJCOPY'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3428,7 +3431,7 @@ fi # Extract the first word of "${ncn_tool_prefix}objdump", so it can be a program name with args. set dummy ${ncn_tool_prefix}objdump; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3432: checking for $ac_word" >&5 +echo "configure:3435: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_OBJDUMP'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3461,7 +3464,7 @@ if test -z "$ac_cv_prog_OBJDUMP" ; then # Extract the first word of "objdump", so it can be a program name with args. set dummy objdump; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3465: checking for $ac_word" >&5 +echo "configure:3468: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_ncn_cv_OBJDUMP'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3510,7 +3513,7 @@ fi # Extract the first word of "${ncn_target_tool_prefix}ar", so it can be a program name with args. set dummy ${ncn_target_tool_prefix}ar; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3514: checking for $ac_word" >&5 +echo "configure:3517: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_AR_FOR_TARGET'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3543,7 +3546,7 @@ if test -z "$ac_cv_prog_AR_FOR_TARGET" ; then # Extract the first word of "ar", so it can be a program name with args. set dummy ar; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3547: checking for $ac_word" >&5 +echo "configure:3550: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_ncn_cv_AR_FOR_TARGET'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3582,7 +3585,7 @@ fi # Extract the first word of "${ncn_target_tool_prefix}as", so it can be a program name with args. set dummy ${ncn_target_tool_prefix}as; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3586: checking for $ac_word" >&5 +echo "configure:3589: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_AS_FOR_TARGET'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3615,7 +3618,7 @@ if test -z "$ac_cv_prog_AS_FOR_TARGET" ; then # Extract the first word of "as", so it can be a program name with args. set dummy as; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3619: checking for $ac_word" >&5 +echo "configure:3622: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_ncn_cv_AS_FOR_TARGET'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3654,7 +3657,7 @@ fi # Extract the first word of "${ncn_target_tool_prefix}dlltool", so it can be a program name with args. set dummy ${ncn_target_tool_prefix}dlltool; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3658: checking for $ac_word" >&5 +echo "configure:3661: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_DLLTOOL_FOR_TARGET'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3687,7 +3690,7 @@ if test -z "$ac_cv_prog_DLLTOOL_FOR_TARGET" ; then # Extract the first word of "dlltool", so it can be a program name with args. set dummy dlltool; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3691: checking for $ac_word" >&5 +echo "configure:3694: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_ncn_cv_DLLTOOL_FOR_TARGET'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3726,7 +3729,7 @@ fi # Extract the first word of "${ncn_target_tool_prefix}ld", so it can be a program name with args. set dummy ${ncn_target_tool_prefix}ld; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3730: checking for $ac_word" >&5 +echo "configure:3733: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_LD_FOR_TARGET'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3759,7 +3762,7 @@ if test -z "$ac_cv_prog_LD_FOR_TARGET" ; then # Extract the first word of "ld", so it can be a program name with args. set dummy ld; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3763: checking for $ac_word" >&5 +echo "configure:3766: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_ncn_cv_LD_FOR_TARGET'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3798,7 +3801,7 @@ fi # Extract the first word of "${ncn_target_tool_prefix}nm", so it can be a program name with args. set dummy ${ncn_target_tool_prefix}nm; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3802: checking for $ac_word" >&5 +echo "configure:3805: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_NM_FOR_TARGET'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3831,7 +3834,7 @@ if test -z "$ac_cv_prog_NM_FOR_TARGET" ; then # Extract the first word of "nm", so it can be a program name with args. set dummy nm; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3835: checking for $ac_word" >&5 +echo "configure:3838: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_ncn_cv_NM_FOR_TARGET'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3870,7 +3873,7 @@ fi # Extract the first word of "${ncn_target_tool_prefix}ranlib", so it can be a program name with args. set dummy ${ncn_target_tool_prefix}ranlib; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3874: checking for $ac_word" >&5 +echo "configure:3877: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB_FOR_TARGET'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3903,7 +3906,7 @@ if test -z "$ac_cv_prog_RANLIB_FOR_TARGET" ; then # Extract the first word of "ranlib", so it can be a program name with args. set dummy ranlib; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3907: checking for $ac_word" >&5 +echo "configure:3910: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_ncn_cv_RANLIB_FOR_TARGET'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3942,7 +3945,7 @@ fi # Extract the first word of "${ncn_target_tool_prefix}windres", so it can be a program name with args. set dummy ${ncn_target_tool_prefix}windres; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3946: checking for $ac_word" >&5 +echo "configure:3949: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_WINDRES_FOR_TARGET'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3975,7 +3978,7 @@ if test -z "$ac_cv_prog_WINDRES_FOR_TARGET" ; then # Extract the first word of "windres", so it can be a program name with args. set dummy windres; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3979: checking for $ac_word" >&5 +echo "configure:3982: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_ncn_cv_WINDRES_FOR_TARGET'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4042,7 +4045,7 @@ RANLIB_FOR_TARGET=${RANLIB_FOR_TARGET}${extra_ranlibflags_for_target} NM_FOR_TARGET=${NM_FOR_TARGET}${extra_nmflags_for_target} echo $ac_n "checking whether to enable maintainer-specific portions of Makefiles""... $ac_c" 1>&6 -echo "configure:4046: checking whether to enable maintainer-specific portions of Makefiles" >&5 +echo "configure:4049: checking whether to enable maintainer-specific portions of Makefiles" >&5 # Check whether --enable-maintainer-mode or --disable-maintainer-mode was given. if test "${enable_maintainer_mode+set}" = set; then enableval="$enable_maintainer_mode" diff --git a/configure.in b/configure.in index bfbb6a1b0e7..6b8154a3549 100644 --- a/configure.in +++ b/configure.in @@ -662,6 +662,9 @@ case "${target}" in mipstx39-*-*) noconfigdirs="$noconfigdirs gprof ${libgcj}" # same as generic mips ;; + mips64*-*-linux*) + noconfigdirs="$noconfigdirs target-newlib ${libgcj}" + ;; mips*-*-linux*) noconfigdirs="$noconfigdirs target-newlib target-libgloss" ;; diff --git a/cpu/ChangeLog b/cpu/ChangeLog index 2a7b8c4de02..ce4468bac77 100644 --- a/cpu/ChangeLog +++ b/cpu/ChangeLog @@ -1,3 +1,52 @@ +2004-03-01 Richard Sandiford + + * frv.cpu (define-arch frv): Add fr450 mach. + (define-mach fr450): New. + (define-model fr450): New. Add profile units to every fr450 insn. + (define-attr UNIT): Add MDCUTSSI. + (define-attr FR450-MAJOR): New enum. Add to every fr450 insn. + (define-attr AUDIO): New boolean. + (f-LRAE, f-LRAD, f-LRAS, f-TLBPRopx, f-TLBPRL) + (f-LRA-null, f-TLBPR-null): New fields. + (scr0, scr1, scr2, scr3, imavr1, damvr1, cxnr, ttbr) + (tplr, tppr, tpxr, timerh, timerl, timerd, btbr): New SPRs. + (LRAE, LRAD, LRAS, TLBPRopx, TLBPRL): New operands. + (LRA-null, TLBPR-null): New macros. + (iacc-multiply-r-r, slass, scutss, int-arith-ss-r-r): Add AUDIO attr. + (load-real-address): New macro. + (lrai, lrad, tlbpr): New instructions. + (media-cut-acc, media-cut-acc-ss): Add fr450-major argument. + (mcut, mcuti, mcutss, mcutssi): Adjust accordingly. + (mdcutssi): Change UNIT attribute to MDCUTSSI. + (media-low-clear-semantics, media-scope-limit-semantics) + (media-quad-limit, media-quad-shift): New macros. + (mqlclrhs, mqlmths, mqsllhi, mqsrahi): New instructions. + * frv.opc (frv_is_branch_major, frv_is_float_major, frv_is_media_major) + (frv_is_branch_insn, frv_is_float_insn, frv_is_media_insn) + (frv_vliw_reset, frv_vliw_add_insn): Handle bfd_mach_fr450. + (fr450_unit_mapping): New array. + (fr400_unit_mapping, fr500_unit_mapping, fr550_unit_mapping): Add entry + for new MDCUTSSI unit. + (fr450_check_insn_major_constraints): New function. + (check_insn_major_constraints): Use it. + +2004-03-01 Richard Sandiford + + * frv.cpu (nsdiv, nudiv, nsdivi, nudivi): Remove fr400 profiling unit. + (scutss): Change unit to I0. + (calll, callil, ccalll): Add missing FR550-MAJOR and profile unit. + (mqsaths): Fix FR400-MAJOR categorization. + (media-quad-multiply-cross-acc, media-quad-cross-multiply-cross-acc) + (media-quad-cross-multiply-acc): Change unit from MDUALACC to FMALL. + * frv.opc (fr400_check_insn_major_constraints): Check for (M-2,M-1) + combinations. + +2004-03-01 Richard Sandiford + + * frv.cpu (r-store, r-store-dual, r-store-quad): Delete. + (rstb, rsth, rst, rstd, rstq): Delete. + (rstbf, rsthf, rstf, rstdf, rstqf): Delete. + 2004-02-23 Nick Clifton * Apply these patches from Renesas: diff --git a/cpu/frv.cpu b/cpu/frv.cpu index 28e78338387..75b034c6edc 100644 --- a/cpu/frv.cpu +++ b/cpu/frv.cpu @@ -28,7 +28,7 @@ (name frv) ; name of cpu architecture (comment "Fujitsu FRV") (insn-lsb0? #t) - (machs frv fr550 fr500 fr400 tomcat simple) + (machs frv fr550 fr500 fr450 fr400 tomcat simple) (isas frv) ) @@ -1338,6 +1338,390 @@ ) ) +; FR450 machine +(define-mach + (name fr450) + (comment "FR450 cpu") + (cpu frvbf) +) +(define-model + (name fr450) (comment "FR450 model") (attrs) + (mach fr450) + (pipeline all "" () ((fetch) (decode) (execute) (writeback))) + ; `state' is a list of variables for recording model state + (state + ; State items + ; These are all masks with each bit representing one register. + (prev-fp-load DI) ; Previous use of FR register was floating point load + (prev-fr-p4 DI) ; Previous use of FR register was media unit 4 + (prev-fr-p6 DI) ; Previous use of FR register was media unit 6 + (prev-acc-p2 DI) ; Previous use of ACC register was media unit 2 + (prev-acc-p4 DI) ; Previous use of ACC register was media unit 4 + (cur-fp-load DI) ; Current use of FR register is floating point load + (cur-fr-p4 DI) ; Current use of FR register is media unit 4 + (cur-fr-p6 DI) ; Current use of FR register is media unit 6 + (cur-acc-p2 DI) ; Current use of ACC register is media unit 2 + (cur-acc-p4 DI) ; Current use of ACC register is media unit 4 + ) + (unit u-exec "Execution Unit" () + 1 1 ; issue done + () ; state + () ; inputs + () ; outputs + () ; profile action (default) + ) + ; Basic integer insn unit + (unit u-integer "Integer Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + ((GRk INT -1) (ICCi_1 INT -1)) ; outputs + () ; profile action (default) + ) + ; Integer multiplication unit + (unit u-imul "Integer Multiplication Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + ((GRdoublek INT -1) (ICCi_1 INT -1)) ; outputs + () ; profile action (default) + ) + ; Integer division unit + (unit u-idiv "Integer Division Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + ((GRk INT -1) (ICCi_1 INT -1)) ; outputs + () ; profile action (default) + ) + ; Branch unit + (unit u-branch "Branch Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1) + (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs + ((pc)) ; outputs + () ; profile action (default) + ) + ; Trap unit + (unit u-trap "Trap Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1) + (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Condition code check unit + (unit u-check "Check Unit" () + 1 1 ; issue done + () ; state + ((ICCi_3 INT -1) (FCCi_3 INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; GR set half unit + (unit u-set-hilo "GR Set Half" () + 1 1 ; issue done + () ; state + () ; inputs + ((GRkhi INT -1) (GRklo INT -1)) ; outputs + () ; profile action (default) + ) + ; GR load unit -- TODO doesn't handle quad + (unit u-gr-load "GR Load Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + ((GRk INT -1) (GRdoublek INT -1)) ; outputs + () ; profile action (default) + ) + ; GR store unit -- TODO doesn't handle quad + (unit u-gr-store "GR Store Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1) (GRk INT -1) (GRdoublek INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; FR load unit -- TODO doesn't handle quad + (unit u-fr-load "FR Load Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + ((FRintk INT -1) (FRdoublek INT -1)) ; outputs + () ; profile action (default) + ) + ; FR store unit -- TODO doesn't handle quad + (unit u-fr-store "FR Store Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Swap unit + (unit u-swap "Swap Unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + ((GRk INT -1)) ; outputs + () ; profile action (default) + ) + ; FR Move to GR unit + (unit u-fr2gr "FR Move to GR Unit" () + 1 1 ; issue done + () ; state + ((FRintk INT -1)) ; inputs + ((GRj INT -1)) ; outputs + () ; profile action (default) + ) + ; SPR Move to GR unit + (unit u-spr2gr "SPR Move to GR Unit" () + 1 1 ; issue done + () ; state + ((spr INT -1)) ; inputs + ((GRj INT -1)) ; outputs + () ; profile action (default) + ) + ; GR Move to FR unit + (unit u-gr2fr "GR Move to FR Unit" () + 1 1 ; issue done + () ; state + ((GRj INT -1)) ; inputs + ((FRintk INT -1)) ; outputs + () ; profile action (default) + ) + ; GR Move to SPR unit + (unit u-gr2spr "GR Move to SPR Unit" () + 1 1 ; issue done + () ; state + ((GRj INT -1)) ; inputs + ((spr INT -1)) ; outputs + () ; profile action (default) + ) + ; Media unit M1 -- see table 14-8 in the fr450 LSI + (unit u-media-1 "Media-1 unit" () + 1 1 ; issue done + () ; state + ((FRinti INT -1) (FRintj INT -1)) ; inputs + ((FRintk INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-1-quad "Media-1-quad unit" () + 1 1 ; issue done + () ; state + ((FRinti INT -1) (FRintj INT -1)) ; inputs + ((FRintk INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-hilo "Media-hilo unit -- a variation of the Media-1 unit" () + 1 1 ; issue done + () ; state + () ; inputs + ((FRkhi INT -1) (FRklo INT -1)) ; outputs + () ; profile action (default) + ) + ; Media unit M2 -- see table 14-8 in the fr450 LSI + (unit u-media-2 "Media-2 unit" () + 1 1 ; issue done + () ; state + ((FRinti INT -1) (FRintj INT -1)) ; inputs + ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-2-quad "Media-2-quad unit" () + 1 1 ; issue done + () ; state + ((FRinti INT -1) (FRintj INT -1)) ; inputs + ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-2-acc "Media-2-acc unit" () + 1 1 ; issue done + () ; state + ((ACC40Si INT -1)) ; inputs + ((ACC40Sk INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-2-acc-dual "Media-2-acc-dual unit" () + 1 1 ; issue done + () ; state + ((ACC40Si INT -1)) ; inputs + ((ACC40Sk INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-2-add-sub "Media-2-add-sub unit" () + 1 1 ; issue done + () ; state + ((ACC40Si INT -1)) ; inputs + ((ACC40Sk INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-2-add-sub-dual "Media-2-add-sub-dual unit" () + 1 1 ; issue done + () ; state + ((ACC40Si INT -1)) ; inputs + ((ACC40Sk INT -1)) ; outputs + () ; profile action (default) + ) + ; Media unit M3 -- see table 14-8 in the fr450 LSI + (unit u-media-3 "Media-3 unit" () + 1 1 ; issue done + () ; state + ((FRinti INT -1) (FRintj INT -1)) ; inputs + ((FRintk INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-3-dual "Media-3-dual unit" () + 1 1 ; issue done + () ; state + ((FRinti INT -1)) ; inputs + ((FRintk INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-3-quad "Media-3-quad unit" () + 1 1 ; issue done + () ; state + ((FRinti INT -1) (FRintj INT -1)) ; inputs + ((FRintk INT -1)) ; outputs + () ; profile action (default) + ) + ; Media unit M4 -- see table 14-8 in the fr450 LSI + (unit u-media-4 "Media-4 unit" () + 1 1 ; issue done + () ; state + ((ACC40Si INT -1) (FRintj INT -1)) ; inputs + ((ACC40Sk INT -1) (FRintk INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-4-accg "Media-4-accg unit" () + 1 1 ; issue done + () ; state + ((ACCGi INT -1) (FRinti INT -1)) ; inputs + ((ACCGk INT -1) (FRintk INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-4-acc-dual "Media-4-acc-dual unit" () + 1 1 ; issue done + () ; state + ((ACC40Si INT -1)) ; inputs + ((FRintk INT -1)) ; outputs + () ; profile action (default) + ) + (unit u-media-4-mclracca "Media-4 unit for MCLRACC with #A=1" () + 1 1 ; issue done + () ; state + () ; inputs + () ; outputs + () ; profile action (default) + ) + ; Media unit M6 -- see table 14-8 in the fr450 LSI + (unit u-media-6 "Media-6 unit" () + 1 1 ; issue done + () ; state + ((FRinti INT -1)) ; inputs + ((FRintk INT -1)) ; outputs + () ; profile action (default) + ) + ; Media unit M7 -- see table 14-8 in the fr450 LSI + (unit u-media-7 "Media-1 unit" () + 1 1 ; issue done + () ; state + ((FRinti INT -1) (FRintj INT -1)) ; inputs + ((FCCk INT -1)) ; outputs + () ; profile action (default) + ) + ; Media Dual Expand unit + (unit u-media-dual-expand "Media Dual Expand unit" () + 1 1 ; issue done + () ; state + ((FRinti INT -1)) ; inputs + ((FRintk INT -1)) ; outputs + () ; profile action (default) + ) + ; Media Dual half to byte unit + (unit u-media-dual-htob "Media Half to byte" () + 1 1 ; issue done + () ; state + ((FRintj INT -1)) ; inputs + ((FRintk INT -1)) ; outputs + () ; profile action (default) + ) + ; Barrier unit + (unit u-barrier "Barrier unit" () + 1 1 ; issue done + () ; state + () ; inputs + () ; outputs + () ; profile action (default) + ) + ; Memory Barrier unit + (unit u-membar "Memory Barrier unit" () + 1 1 ; issue done + () ; state + () ; inputs + () ; outputs + () ; profile action (default) + ) + ; Insn cache invalidate unit + (unit u-ici "Insn cache invalidate unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Data cache invalidate unit + (unit u-dci "Data cache invalidate unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Data cache flush unit + (unit u-dcf "Data cache flush unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Insn cache preload unit + (unit u-icpl "Insn cache preload unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Data cache preload unit + (unit u-dcpl "Data cache preload unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Insn cache unlock unit + (unit u-icul "Insn cache unlock unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) + ; Data cache unlock unit + (unit u-dcul "Data cache unlock unit" () + 1 1 ; issue done + () ; state + ((GRi INT -1) (GRj INT -1)) ; inputs + () ; outputs + () ; profile action (default) + ) +) + ; Simple machine - single issue integer machine (define-mach (name simple) @@ -1394,6 +1778,7 @@ SCAN ; scan, scani slotted differently on different machines DCPL ; dcpl slotted differently on different machines MDUALACC ; media dual acc slotted differently on different machines + MDCUTSSI ; mdcutssi insn slotted differently on different machines MCLRACC-1; mclracc A==1 slotted differently on different machines NUM_UNITS ) @@ -1413,6 +1798,20 @@ M-1 M-2 ) ) +(define-attr + (for insn) + (type enum) + (name FR450-MAJOR) + (comment "fr450 major insn categories") + ; The order of declaration is significant. Keep variations on the same major + ; together. + (values NONE + I-1 I-2 I-3 I-4 I-5 + B-1 B-2 B-3 B-4 B-5 B-6 + C-1 C-2 + M-1 M-2 M-3 M-4 M-5 M-6 + ) +) (define-attr (for insn) (type enum) @@ -1478,6 +1877,13 @@ (name PRESERVE-OVF) (comment "Preserve value of MSR.OVF") ) +; "Audio" instruction provided by the fr405 but not the original fr400 core. +(define-attr + (for insn) + (type boolean) + (name AUDIO) + (comment "Audio instruction added with FR405") +) ; null attribute -- used as a place holder for where an attribue is required. (define-attr (for insn) @@ -1633,6 +2039,13 @@ pc))) ) +(dnf f-LRAE "Load Real Address E flag" () 5 1) +(dnf f-LRAD "Load Real Address D flag" () 4 1) +(dnf f-LRAS "Load Real Address S flag" () 3 1) + +(dnf f-TLBPRopx "TLB Probe operation number" () 28 3) +(dnf f-TLBPRL "TLB Probe L flag" () 25 1) + (dnf f-ICCi_1-null "null field" (RESERVED) 11 2) (dnf f-ICCi_2-null "null field" (RESERVED) 26 2) (dnf f-ICCi_3-null "null field" (RESERVED) 1 2) @@ -1663,6 +2076,9 @@ (dnf f-misc-null-10 "null field" (RESERVED) 16 5) (dnf f-misc-null-11 "null field" (RESERVED) 5 1) +(dnf f-LRA-null "null field" (RESERVED) 2 3) +(dnf f-TLBPR-null "null field" (RESERVED) 30 2) + (dnf f-LI-off "null field" (RESERVED) 25 1) (dnf f-LI-on "null field" (RESERVED) 25 1) @@ -2121,6 +2537,8 @@ (sr0 768) (sr1 769) (sr2 770) (sr3 771) + (scr0 832) (scr1 833) (scr2 834) (scr3 835) + (fsr0 1024) (fsr1 1025) (fsr2 1026) (fsr3 1027) (fsr4 1028) (fsr5 1029) (fsr6 1030) (fsr7 1031) (fsr8 1032) (fsr9 1033) (fsr10 1034) (fsr11 1035) @@ -2355,7 +2773,11 @@ (dampr60 1916) (dampr61 1917) (dampr62 1918) (dampr63 1919) (amcr 1920) (stbar 1921) (mmcr 1922) - (dcr 2048) (brr 2049) (nmar 2050) + (iamvr1 1925) (damvr1 1927) + (cxnr 1936) (ttbr 1937) (tplr 1938) (tppr 1939) + (tpxr 1940) + (timerh 1952) (timerl 1953) (timerd 1954) + (dcr 2048) (brr 2049) (nmar 2050) (btbr 2051) (ibar0 2052) (ibar1 2053) (ibar2 2054) (ibar3 2055) (dbar0 2056) (dbar1 2057) (dbar2 2058) (dbar3 2059) @@ -2516,7 +2938,7 @@ (define-hardware (name h-iacc0) (comment "64 bit signed accumulator") - (attrs PROFILE VIRTUAL (MACH fr400)) + (attrs PROFILE VIRTUAL (MACH fr400,fr450)) (type register DI (1)) (indices extern-keyword iacc0-names) ; The single 64-bit integer accumulator is made up of two 32 bit @@ -2736,6 +3158,13 @@ (dnop label16 "18 bit pc relative address" () h-iaddr f-label16) (dnop label24 "26 bit pc relative address" () h-iaddr f-label24) +(dnop LRAE "Load Real Address E flag" () h-uint f-LRAE) +(dnop LRAD "Load Real Address D flag" () h-uint f-LRAD) +(dnop LRAS "Load Real Address S flag" () h-uint f-LRAS) + +(dnop TLBPRopx "TLB Probe operation number" () h-uint f-TLBPRopx) +(dnop TLBPRL "TLB Probe L flag" () h-uint f-TLBPRL) + (define-operand (name A0) (comment "A==0 operand of mclracc") @@ -2894,6 +3323,9 @@ (define-pmacro (misc-null-10) (f-misc-null-10 0)) (define-pmacro (misc-null-11) (f-misc-null-11 0)) +(define-pmacro (LRA-null) (f-LRA-null 0)) +(define-pmacro (TLBPR-null) (f-TLBPR-null 0)) + (define-pmacro (LI-on) (f-LI-on 1)) (define-pmacro (LI-off) (f-LI-off 0)) @@ -2984,11 +3416,12 @@ (define-pmacro (int-logic-r-r name operation op ope comment) (dni name (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1)) (.str name "$pack $GRi,$GRj,$GRk") (+ pack GRk op GRi (ICCi_1-null) ope GRj) (set GRk (operation GRi GRj)) - ((fr400 (unit u-integer)) + ((fr400 (unit u-integer)) (fr450 (unit u-integer)) (fr500 (unit u-integer)) (fr550 (unit u-integer))) ) ) @@ -3001,24 +3434,26 @@ (dni not ("not") - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1)) ("not$pack $GRj,$GRk") (+ pack GRk OP_01 (rs-null) (ICCi_1-null) OPE2_06 GRj) (set GRk (inv GRj)) - ((fr400 (unit u-integer)) + ((fr400 (unit u-integer)) (fr450 (unit u-integer)) (fr500 (unit u-integer)) (fr550 (unit u-integer))) ) (dni sdiv "signed division" - ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1)) + ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) + (FR400-MAJOR I-1) (FR450-MAJOR I-1)) "sdiv$pack $GRi,$GRj,$GRk" (+ pack GRk OP_00 GRi (ICCi_1-null) OPE2_0E GRj) (sequence () (c-call VOID "@cpu@_signed_integer_divide" GRi GRj (index-of GRk) 0) (clobber GRk)) - ((fr400 (unit u-idiv)) + ((fr400 (unit u-idiv)) (fr450 (unit u-idiv)) (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) ) @@ -3032,20 +3467,20 @@ (c-call VOID "@cpu@_signed_integer_divide" GRi GRj (index-of GRk) 1) (clobber GRk)) - ((fr400 (unit u-idiv)) - (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) + ((fr500 (unit u-idiv)) (fr550 (unit u-idiv))) ) (dni udiv "unsigned division reg/reg" - ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1)) + ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) + (FR400-MAJOR I-1) (FR450-MAJOR I-1)) "udiv$pack $GRi,$GRj,$GRk" (+ pack GRk OP_00 GRi (ICCi_1-null) OPE2_0F GRj) (sequence () (c-call VOID "@cpu@_unsigned_integer_divide" GRi GRj (index-of GRk) 0) (clobber GRk)) - ((fr400 (unit u-idiv)) + ((fr400 (unit u-idiv)) (fr450 (unit u-idiv)) (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) ) @@ -3059,8 +3494,7 @@ (c-call VOID "@cpu@_unsigned_integer_divide" GRi GRj (index-of GRk) 1) (clobber GRk)) - ((fr400 (unit u-idiv)) - (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) + ((fr500 (unit u-idiv)) (fr550 (unit u-idiv))) ) ; Multiplication @@ -3068,11 +3502,12 @@ (define-pmacro (multiply-r-r name signop op ope comment) (dni name (comment) - ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1)) + ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) + (FR400-MAJOR I-1) (FR450-MAJOR I-1)) (.str name "$pack $GRi,$GRj,$GRdoublek") (+ pack GRdoublek op GRi (ICCi_1-null) ope GRj) (set GRdoublek (mul DI (signop DI GRi) (signop DI GRj))) - ((fr400 (unit u-imul)) + ((fr400 (unit u-imul)) (fr450 (unit u-imul)) (fr500 (unit u-imul)) (fr550 (unit u-imul))) ) ) @@ -3119,11 +3554,12 @@ (define-pmacro (iacc-multiply-r-r name operation op ope comment) (dni name (comment) - ((UNIT IACC) (FR400-MAJOR I-1) (MACH fr400)) + ((UNIT IACC) (MACH fr400,fr450) + (FR400-MAJOR I-1) (FR450-MAJOR I-1) AUDIO) (.str name "$pack $GRi,$GRj") (+ pack (rd-null) op GRi ope GRj) ((.sym iacc- operation) (mul DI (ext DI GRi) (ext DI GRj))) - ((fr400 (unit u-integer))) + ((fr400 (unit u-integer)) (fr450 (unit u-integer))) ) ) @@ -3134,11 +3570,12 @@ (define-pmacro (int-shift-r-r name op ope comment) (dni name (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1)) (.str name "$pack $GRi,$GRj,$GRk") (+ pack GRk op GRi (ICCi_1-null) ope GRj) (set GRk (name GRi (and GRj #x1f))) - ((fr400 (unit u-integer)) + ((fr400 (unit u-integer)) (fr450 (unit u-integer)) (fr500 (unit u-integer)) (fr550 (unit u-integer))) ) ) @@ -3149,7 +3586,8 @@ (dni slass "shift left arith reg/reg with saturation" - ((UNIT IALL) (FR400-MAJOR I-1) (MACH fr400)) + ((UNIT IALL) (MACH fr400,fr450) + (FR400-MAJOR I-1) (FR450-MAJOR I-1) AUDIO) "slass$pack $GRi,$GRj,$GRk" (+ pack GRk OP_46 GRi OPE1_02 GRj) (set GRk (c-call SI "@cpu@_shift_left_arith_saturate" GRi GRj)) @@ -3158,7 +3596,8 @@ (dni scutss "Integer accumulator cut with saturation" - ((UNIT IALL) (FR400-MAJOR I-1) (MACH fr400)) + ((UNIT I0) (MACH fr400,fr450) + (FR400-MAJOR I-1) (FR450-MAJOR I-1) AUDIO) "scutss$pack $GRj,$GRk" (+ pack GRk OP_46 (rs-null) OPE1_04 GRj) (set GRk (c-call SI "@cpu@_iacc_cut" (reg h-iacc0 0) GRj)) @@ -3174,11 +3613,12 @@ (dni scan "scan" - ((UNIT SCAN) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + ((UNIT SCAN) (FR500-MAJOR I-1) (FR550-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1)) "scan$pack $GRi,$GRj,$GRk" (+ pack GRk OP_0B GRi (ICCi_1-null) OPE2_00 GRj) (scan-semantics GRi GRj GRk) - ((fr400 (unit u-integer)) + ((fr400 (unit u-integer)) (fr450 (unit u-integer)) (fr500 (unit u-integer)) (fr550 (unit u-integer))) ) @@ -3187,12 +3627,13 @@ (define-pmacro (conditional-int-logic name operation op ope comment) (dni name (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) (.str name "$pack $GRi,$GRj,$GRk,$CCi,$cond") (+ pack GRk op GRi CCi cond ope GRj) (if (eq CCi (or cond 2)) (set GRk (operation GRi GRj))) - ((fr400 (unit u-integer)) + ((fr400 (unit u-integer)) (fr450 (unit u-integer)) (fr500 (unit u-integer)) (fr550 (unit u-integer))) ) ) @@ -3205,29 +3646,32 @@ (dni cnot "conditional not" - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) "cnot$pack $GRj,$GRk,$CCi,$cond" (+ pack GRk OP_5A (rs-null) CCi cond OPE4_3 GRj) (if (eq CCi (or cond 2)) (set GRk (inv GRj))) - ((fr400 (unit u-integer)) + ((fr400 (unit u-integer)) (fr450 (unit u-integer)) (fr500 (unit u-integer)) (fr550 (unit u-integer))) ) (dni csmul "conditional signed multiply" - ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1) CONDITIONAL) + ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) + (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) "csmul$pack $GRi,$GRj,$GRdoublek,$CCi,$cond" (+ pack GRdoublek OP_58 GRi CCi cond OPE4_2 GRj) (if (eq CCi (or cond 2)) (set GRdoublek (mul DI (ext DI GRi) (ext DI GRj)))) - ((fr400 (unit u-imul)) + ((fr400 (unit u-imul)) (fr450 (unit u-imul)) (fr500 (unit u-imul)) (fr550 (unit u-imul))) ) (dni csdiv "conditional signed division" - ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1) CONDITIONAL) + ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) + (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) "csdiv$pack $GRi,$GRj,$GRk,$CCi,$cond" (+ pack GRk OP_58 GRi CCi cond OPE4_3 GRj) (if (eq CCi (or cond 2)) @@ -3235,13 +3679,14 @@ (c-call VOID "@cpu@_signed_integer_divide" GRi GRj (index-of GRk) 0) (clobber GRk))) - ((fr400 (unit u-idiv)) + ((fr400 (unit u-idiv)) (fr450 (unit u-idiv)) (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) ) (dni cudiv "conditional unsigned division" - ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1) CONDITIONAL) + ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) + (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) "cudiv$pack $GRi,$GRj,$GRk,$CCi,$cond" (+ pack GRk OP_59 GRi CCi cond OPE4_3 GRj) (if (eq CCi (or cond 2)) @@ -3249,19 +3694,20 @@ (c-call VOID "@cpu@_unsigned_integer_divide" GRi GRj (index-of GRk) 0) (clobber GRk))) - ((fr400 (unit u-idiv)) + ((fr400 (unit u-idiv)) (fr450 (unit u-idiv)) (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) ) (define-pmacro (conditional-shift name operation op ope comment) (dni name (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) (.str name "$pack $GRi,$GRj,$GRk,$CCi,$cond") (+ pack GRk op GRi CCi cond ope GRj) (if (eq CCi (or cond 2)) (set GRk (operation GRi (and GRj #x1f)))) - ((fr400 (unit u-integer)) + ((fr400 (unit u-integer)) (fr450 (unit u-integer)) (fr500 (unit u-integer)) (fr550 (unit u-integer))) ) ) @@ -3272,12 +3718,13 @@ (dni cscan "conditional scan" - ((UNIT SCAN) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL) + ((UNIT SCAN) (FR500-MAJOR I-1) (FR550-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) "cscan$pack $GRi,$GRj,$GRk,$CCi,$cond" (+ pack GRk OP_65 GRi CCi cond OPE4_3 GRj) (if (eq CCi (or cond 2)) (scan-semantics GRi GRj GRk)) - ((fr400 (unit u-integer)) + ((fr400 (unit u-integer)) (fr450 (unit u-integer)) (fr500 (unit u-integer)) (fr550 (unit u-integer))) ) @@ -3299,11 +3746,12 @@ (define-pmacro (int-arith-cc-r-r name operation op ope comment) (dni name (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1)) (.str name "$pack $GRi,$GRj,$GRk,$ICCi_1") (+ pack GRk op GRi ICCi_1 ope GRj) (int-arith-cc-semantics operation ICCi_1) - ((fr400 (unit u-integer)) + ((fr400 (unit u-integer)) (fr450 (unit u-integer)) (fr500 (unit u-integer)) (fr550 (unit u-integer))) ) ) @@ -3321,11 +3769,12 @@ (define-pmacro (int-logic-cc-r-r name op ope comment) (dni (.sym name cc) (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1)) (.str (.sym name cc) "$pack $GRi,$GRj,$GRk,$ICCi_1") (+ pack GRk op GRi ICCi_1 ope GRj) (int-logic-cc-semantics name ICCi_1) - ((fr400 (unit u-integer)) + ((fr400 (unit u-integer)) (fr450 (unit u-integer)) (fr500 (unit u-integer)) (fr550 (unit u-integer))) ) ) @@ -3348,11 +3797,12 @@ (define-pmacro (int-shift-cc-r-r name l-r op ope comment) (dni (.sym name cc) (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1)) (.str (.sym name cc) "$pack $GRi,$GRj,$GRk,$ICCi_1") (+ pack GRk op GRi ICCi_1 ope GRj) (int-shift-cc-semantics name l-r ICCi_1) - ((fr400 (unit u-integer)) + ((fr400 (unit u-integer)) (fr450 (unit u-integer)) (fr500 (unit u-integer)) (fr550 (unit u-integer))) ) ) @@ -3374,11 +3824,12 @@ (define-pmacro (multiply-cc-r-r name signop op ope comment) (dni name (comment) - ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1)) + ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) + (FR400-MAJOR I-1) (FR450-MAJOR I-1)) (.str name "$pack $GRi,$GRj,$GRdoublek,$ICCi_1") (+ pack GRdoublek op GRi ICCi_1 ope GRj) (multiply-cc-semantics signop GRi GRj GRdoublek ICCi_1) - ((fr400 (unit u-imul)) + ((fr400 (unit u-imul)) (fr450 (unit u-imul)) (fr500 (unit u-imul)) (fr550 (unit u-imul))) ) ) @@ -3392,13 +3843,14 @@ (define-pmacro (conditional-int-arith-cc name operation op ope comment) (dni name (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) (.str name "$pack $GRi,$GRj,$GRk,$CCi,$cond") (+ pack GRk op GRi CCi cond ope GRj) (if (eq CCi (or cond 2)) (int-arith-cc-semantics operation (reg h-iccr (and (index-of CCi) 3)))) - ((fr400 (unit u-integer)) + ((fr400 (unit u-integer)) (fr450 (unit u-integer)) (fr500 (unit u-integer)) (fr550 (unit u-integer))) ) ) @@ -3408,26 +3860,28 @@ (dni csmulcc "conditional signed multiply and set condition code" - ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1) CONDITIONAL) + ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) + (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) "csmulcc$pack $GRi,$GRj,$GRdoublek,$CCi,$cond" (+ pack GRdoublek OP_59 GRi CCi cond OPE4_2 GRj) (if (eq CCi (or cond 2)) (multiply-cc-semantics ext GRi GRj GRdoublek (reg h-iccr (and (index-of CCi) 3)))) - ((fr400 (unit u-imul)) + ((fr400 (unit u-imul)) (fr450 (unit u-imul)) (fr500 (unit u-imul)) (fr550 (unit u-imul))) ) (define-pmacro (conditional-int-logic-cc name operation op ope comment) (dni name (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) (.str name "$pack $GRi,$GRj,$GRk,$CCi,$cond") (+ pack GRk op GRi CCi cond ope GRj) (if (eq CCi (or cond 2)) (int-logic-cc-semantics operation (reg h-iccr (and (index-of CCi) 3)))) - ((fr400 (unit u-integer)) + ((fr400 (unit u-integer)) (fr450 (unit u-integer)) (fr500 (unit u-integer)) (fr550 (unit u-integer))) ) ) @@ -3439,13 +3893,14 @@ (define-pmacro (conditional-int-shift-cc name l-r op ope comment) (dni (.sym c name cc) (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) (.str (.sym c name cc) "$pack $GRi,$GRj,$GRk,$CCi,$cond") (+ pack GRk op GRi CCi cond ope GRj) (if (eq CCi (or cond 2)) (int-shift-cc-semantics name l-r (reg h-iccr (and (index-of CCi) 3)))) - ((fr400 (unit u-integer)) + ((fr400 (unit u-integer)) (fr450 (unit u-integer)) (fr500 (unit u-integer)) (fr550 (unit u-integer))) ) ) @@ -3459,11 +3914,12 @@ (define-pmacro (int-arith-x-r-r name operation op ope comment) (dni name (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1)) (.str name "$pack $GRi,$GRj,$GRk,$ICCi_1") (+ pack GRk op GRi ICCi_1 ope GRj) (set GRk ((.sym operation c) GRi GRj (cbit ICCi_1))) - ((fr400 (unit u-integer)) + ((fr400 (unit u-integer)) (fr450 (unit u-integer)) (fr500 (unit u-integer)) (fr550 (unit u-integer))) ) ) @@ -3474,7 +3930,8 @@ (define-pmacro (int-arith-x-cc-r-r name operation op ope comment) (dni name (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1)) (.str name "$pack $GRi,$GRj,$GRk,$ICCi_1") (+ pack GRk op GRi ICCi_1 ope GRj) (sequence ((WI tmp) (QI cc)) @@ -3485,7 +3942,7 @@ (set-z-and-n cc tmp) (set GRk tmp) (set ICCi_1 cc)) - ((fr400 (unit u-integer)) + ((fr400 (unit u-integer)) (fr450 (unit u-integer)) (fr500 (unit u-integer)) (fr550 (unit u-integer))) ) ) @@ -3497,7 +3954,8 @@ (define-pmacro (int-arith-ss-r-r name operation op ope comment) (dni name (comment) - ((UNIT IALL) (FR400-MAJOR I-1) (MACH fr400)) + ((UNIT IALL) (MACH fr400,fr450) + (FR400-MAJOR I-1) (FR450-MAJOR I-1) AUDIO) (.str name "$pack $GRi,$GRj,$GRk") (+ pack GRk op GRi ope GRj) (sequence () @@ -3512,7 +3970,7 @@ ((lt GRi 0) (const #x80000000)) (else (const 0))))) ) - ((fr400 (unit u-integer))) + ((fr400 (unit u-integer)) (fr450 (unit u-integer))) ) ) @@ -3524,11 +3982,12 @@ (define-pmacro (int-logic-r-simm name operation op comment) (dni name (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1)) (.str name "$pack $GRi,$s12,$GRk") (+ pack GRk op GRi s12) (set GRk (operation GRi s12)) - ((fr400 (unit u-integer)) + ((fr400 (unit u-integer)) (fr450 (unit u-integer)) (fr500 (unit u-integer)) (fr550 (unit u-integer))) ) ) @@ -3541,14 +4000,15 @@ (dni sdivi "signed division reg/immed" - ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1)) + ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) + (FR400-MAJOR I-1) (FR450-MAJOR I-1)) "sdivi$pack $GRi,$s12,$GRk" (+ pack GRk OP_1E GRi s12) (sequence () (c-call VOID "@cpu@_signed_integer_divide" GRi s12 (index-of GRk) 0) (clobber GRk)) - ((fr400 (unit u-idiv)) + ((fr400 (unit u-idiv)) (fr450 (unit u-idiv)) (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) ) @@ -3562,20 +4022,20 @@ (c-call VOID "@cpu@_signed_integer_divide" GRi s12 (index-of GRk) 1) (clobber GRk)) - ((fr400 (unit u-idiv)) - (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) + ((fr500 (unit u-idiv)) (fr550 (unit u-idiv))) ) (dni udivi "unsigned division reg/immed" - ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1)) + ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) + (FR400-MAJOR I-1) (FR450-MAJOR I-1)) "udivi$pack $GRi,$s12,$GRk" (+ pack GRk OP_1F GRi s12) (sequence () (c-call VOID "@cpu@_unsigned_integer_divide" GRi s12 (index-of GRk) 0) (clobber GRk)) - ((fr400 (unit u-idiv)) + ((fr400 (unit u-idiv)) (fr450 (unit u-idiv)) (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) ) @@ -3589,18 +4049,18 @@ (c-call VOID "@cpu@_unsigned_integer_divide" GRi s12 (index-of GRk) 1) (clobber GRk)) - ((fr400 (unit u-idiv)) - (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) + ((fr500 (unit u-idiv)) (fr550 (unit u-idiv))) ) (define-pmacro (multiply-r-simm name signop op comment) (dni name (comment) - ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1)) + ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) + (FR400-MAJOR I-1) (FR450-MAJOR I-1)) (.str name "$pack $GRi,$s12,$GRdoublek") (+ pack GRdoublek op GRi s12) (set GRdoublek (mul DI (signop DI GRi) (signop DI s12))) - ((fr400 (unit u-imul)) + ((fr400 (unit u-imul)) (fr450 (unit u-imul)) (fr500 (unit u-imul)) (fr550 (unit u-imul))) ) ) @@ -3611,11 +4071,12 @@ (define-pmacro (int-shift-r-simm name op comment) (dni (.sym name i) (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1)) (.str (.sym name i) "$pack $GRi,$s12,$GRk") (+ pack GRk op GRi s12) (set GRk (name GRi (and s12 #x1f))) - ((fr400 (unit u-integer)) + ((fr400 (unit u-integer)) (fr450 (unit u-integer)) (fr500 (unit u-integer)) (fr550 (unit u-integer))) ) ) @@ -3626,11 +4087,12 @@ (dni scani "scan immediate" - ((UNIT SCAN) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + ((UNIT SCAN) (FR500-MAJOR I-1) (FR550-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1)) "scani$pack $GRi,$s12,$GRk" (+ pack GRk OP_47 GRi s12) (scan-semantics GRi s12 GRk) - ((fr400 (unit u-integer)) + ((fr400 (unit u-integer)) (fr450 (unit u-integer)) (fr500 (unit u-integer)) (fr550 (unit u-integer))) ) @@ -3639,7 +4101,8 @@ (define-pmacro (int-arith-cc-r-simm name operation op comment) (dni name (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1)) (.str name "$pack $GRi,$s10,$GRk,$ICCi_1") (+ pack GRk op GRi ICCi_1 s10) (sequence ((BI tmp) (QI cc) (SI result)) @@ -3652,7 +4115,7 @@ (set-z-and-n cc result) (set GRk result) (set ICCi_1 cc)) - ((fr400 (unit u-integer)) + ((fr400 (unit u-integer)) (fr450 (unit u-integer)) (fr500 (unit u-integer)) (fr550 (unit u-integer))) ) ) @@ -3663,14 +4126,15 @@ (define-pmacro (int-logic-cc-r-simm name op comment) (dni (.sym name icc) (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1)) (.str (.sym name icc) "$pack $GRi,$s10,$GRk,$ICCi_1") (+ pack GRk op GRi ICCi_1 s10) (sequence ((SI tmp)) (set tmp (name GRi s10)) (set GRk tmp) (set-z-and-n ICCi_1 tmp)) - ((fr400 (unit u-integer)) + ((fr400 (unit u-integer)) (fr450 (unit u-integer)) (fr500 (unit u-integer)) (fr550 (unit u-integer))) ) ) @@ -3682,11 +4146,12 @@ (define-pmacro (multiply-cc-r-simm name signop op comment) (dni name (comment) - ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1)) + ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) + (FR400-MAJOR I-1) (FR450-MAJOR I-1)) (.str name "$pack $GRi,$s10,$GRdoublek,$ICCi_1") (+ pack GRdoublek op GRi ICCi_1 s10) (multiply-cc-semantics signop GRi s10 GRdoublek ICCi_1) - ((fr400 (unit u-imul)) + ((fr400 (unit u-imul)) (fr450 (unit u-imul)) (fr500 (unit u-imul)) (fr550 (unit u-imul))) ) ) @@ -3697,7 +4162,8 @@ (define-pmacro (int-shift-cc-r-simm name l-r op comment) (dni (.sym name icc) (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1)) (.str (.sym name icc) "$pack $GRi,$s10,$GRk,$ICCi_1") (+ pack GRk op GRi ICCi_1 s10) (sequence ((WI shift) (SI tmp) (QI cc)) @@ -3708,7 +4174,7 @@ (set GRk tmp) (set-z-and-n cc tmp) (set ICCi_1 cc)) - ((fr400 (unit u-integer)) + ((fr400 (unit u-integer)) (fr450 (unit u-integer)) (fr500 (unit u-integer)) (fr550 (unit u-integer))) ) ) @@ -3720,11 +4186,12 @@ (define-pmacro (int-arith-x-r-simm name operation op comment) (dni name (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1)) (.str name "$pack $GRi,$s10,$GRk,$ICCi_1") (+ pack GRk op GRi ICCi_1 s10) (set GRk ((.sym operation c) GRi s10 (cbit ICCi_1))) - ((fr400 (unit u-integer)) + ((fr400 (unit u-integer)) (fr450 (unit u-integer)) (fr500 (unit u-integer)) (fr550 (unit u-integer))) ) ) @@ -3735,7 +4202,8 @@ (define-pmacro (int-arith-x-cc-r-simm name operation op comment) (dni name (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1)) (.str name "$pack $GRi,$s10,$GRk,$ICCi_1") (+ pack GRk op GRi ICCi_1 s10) (sequence ((WI tmp) (QI cc)) @@ -3746,7 +4214,7 @@ (set-z-and-n cc tmp) (set GRk tmp) (set ICCi_1 cc)) - ((fr400 (unit u-integer)) + ((fr400 (unit u-integer)) (fr450 (unit u-integer)) (fr500 (unit u-integer)) (fr550 (unit u-integer))) ) ) @@ -3758,7 +4226,8 @@ (dni cmpb "Compare bytes" - ((UNIT IALL) (FR400-MAJOR I-1) (FR550-MAJOR I-1) (MACH fr400,fr550)) + ((UNIT IALL) (MACH fr400,fr450,fr550) (FR550-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1)) "cmpb$pack $GRi,$GRj,$ICCi_1" (+ pack (GRk-null) OP_00 GRi ICCi_1 OPE2_0C GRj) (sequence ((QI cc)) @@ -3767,12 +4236,14 @@ (set-v cc (eq (and GRi #x0000ff00) (and GRj #x0000ff00))) (set-c cc (eq (and GRi #x000000ff) (and GRj #x000000ff))) (set ICCi_1 cc)) - ((fr400 (unit u-integer)) (fr550 (unit u-integer))) + ((fr400 (unit u-integer)) (fr450 (unit u-integer)) + (fr550 (unit u-integer))) ) (dni cmpba "OR of Compare bytes" - ((UNIT IALL) (FR400-MAJOR I-1) (FR550-MAJOR I-1) (MACH fr400,fr550)) + ((UNIT IALL) (MACH fr400,fr450,fr550) (FR550-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1)) "cmpba$pack $GRi,$GRj,$ICCi_1" (+ pack (GRk-null) OP_00 GRi ICCi_1 OPE2_0D GRj) (sequence ((QI cc)) @@ -3785,49 +4256,54 @@ (eq (and GRi #x000000ff) (and GRj #x000000ff)))))) (set ICCi_1 cc)) - ((fr400 (unit u-integer)) (fr550 (unit u-integer))) + ((fr400 (unit u-integer)) (fr450 (unit u-integer)) + (fr550 (unit u-integer))) ) ; Format: Load immediate ; (dni setlo "set low order bits" - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1)) "setlo$pack $ulo16,$GRklo" (+ pack GRk OP_3D (misc-null-4) u16) (set GRklo u16) - ((fr400 (unit u-set-hilo)) + ((fr400 (unit u-set-hilo)) (fr450 (unit u-set-hilo)) (fr500 (unit u-set-hilo)) (fr550 (unit u-set-hilo))) ) (dni sethi "set high order bits" - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1)) "sethi$pack $uhi16,$GRkhi" (+ pack GRkhi OP_3E (misc-null-4) u16) (set GRkhi u16) - ((fr400 (unit u-set-hilo)) + ((fr400 (unit u-set-hilo)) (fr450 (unit u-set-hilo)) (fr500 (unit u-set-hilo)) (fr550 (unit u-set-hilo))) ) (dni setlos "set low order bits and extend sign" - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) + ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1)) "setlos$pack $slo16,$GRk" (+ pack GRk OP_3F (misc-null-4) s16) (set GRk s16) - ((fr400 (unit u-integer)) + ((fr400 (unit u-integer)) (fr450 (unit u-integer)) (fr500 (unit u-integer)) (fr550 (unit u-integer))) ) (define-pmacro (load-gr-r name mode op ope comment) (dni name (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2)) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) + (FR400-MAJOR I-2) (FR450-MAJOR I-2)) (.str name "$pack @($GRi,$GRj),$GRk") (+ pack GRk op GRi ope GRj) (set GRk (c-call mode (.str "@cpu@_read_mem_" mode) pc (add GRi GRj))) - ((fr400 (unit u-gr-load)) + ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) ) ) @@ -3841,11 +4317,12 @@ (define-pmacro (load-fr-r name mode op ope comment) (dni name (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) FR-ACCESS) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) + (FR400-MAJOR I-2) (FR450-MAJOR I-2) FR-ACCESS) (.str name "$pack @($GRi,$GRj),$FRintk") (+ pack FRintk op GRi ope GRj) (set FRintk (c-call mode (.str "@cpu@_read_mem_" mode) pc (add GRi GRj))) - ((fr400 (unit u-fr-load)) + ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) ) ) @@ -3940,7 +4417,8 @@ name not_gr mode op ope regtype attr profile comment) (dni name (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) attr) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) + (FR400-MAJOR I-2) (FR450-MAJOR I-2) attr) (.str name "$pack @($GRi,$GRj),$" regtype "doublek") (+ pack (.sym regtype doublek) op GRi ope GRj) (sequence ((WI address)) @@ -3950,10 +4428,12 @@ ) (load-double-r-r ldd 0 DI OP_02 OPE1_05 GR NA - ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) + ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) + (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load double word") (load-double-r-r lddf 1 DF OP_02 OPE1_0B FR FR-ACCESS - ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) + ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) + (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load double float") (load-double-r-r lddc 1 DI OP_02 OPE1_0E CPR (MACH frv) () "Load coprocessor double") @@ -4044,11 +4524,12 @@ (define-pmacro (load-gr-u name mode op ope comment) (dni name (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2)) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) + (FR400-MAJOR I-2) (FR450-MAJOR I-2)) (.str name "$pack @($GRi,$GRj),$GRk") (+ pack GRk op GRi ope GRj) (load-gr-u-semantics mode) - ((fr400 (unit u-gr-load)) + ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) ) ) @@ -4089,11 +4570,12 @@ (define-pmacro (load-fr-u name mode op ope comment) (dni name (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) FR-ACCESS) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) + (FR400-MAJOR I-2) (FR450-MAJOR I-2) FR-ACCESS) (.str name "$pack @($GRi,$GRj),$FRintk") (+ pack FRintk op GRi ope GRj) (load-non-gr-u-semantics mode FRint) - ((fr400 (unit u-fr-load)) + ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) ) ) @@ -4144,11 +4626,12 @@ (define-pmacro (load-double-gr-u name op ope comment) (dni name (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2)) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) + (FR400-MAJOR I-2) (FR450-MAJOR I-2)) (.str name "$pack @($GRi,$GRj),$GRdoublek") (+ pack GRdoublek op GRi ope GRj) (load-double-gr-u-semantics) - ((fr400 (unit u-gr-load)) + ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) ) ) @@ -4182,7 +4665,8 @@ name mode op ope regtype attr profile comment) (dni name (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) attr) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) + (FR400-MAJOR I-2) (FR450-MAJOR I-2) attr) (.str name "$pack @($GRi,$GRj),$" regtype "doublek") (+ pack (.sym regtype doublek) op GRi ope GRj) (load-double-non-gr-u-semantics mode regtype) @@ -4191,7 +4675,8 @@ ) (load-double-non-gr-u lddfu DF OP_02 OPE1_1B FR FR-ACCESS - ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) + ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) + (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load double float, update index") (load-double-non-gr-u lddcu DI OP_02 OPE1_1E CPR (MACH frv) () "Load coprocessor double float, update index") @@ -4289,7 +4774,8 @@ (define-pmacro (load-r-simm name mode op regtype attr profile comment) (dni name (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) attr) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) + (FR400-MAJOR I-2) (FR450-MAJOR I-2) attr) (.str name "$pack @($GRi,$d12),$" regtype "k") (+ pack (.sym regtype k) op GRi d12) (set (.sym regtype k) @@ -4299,29 +4785,37 @@ ) (load-r-simm ldsbi QI OP_30 GR NA - ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) + ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) + (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load signed byte") (load-r-simm ldshi HI OP_31 GR NA - ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) + ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) + (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load signed half") (load-r-simm ldi SI OP_32 GR NA - ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) + ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) + (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load word") (load-r-simm ldubi UQI OP_35 GR NA - ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) + ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) + (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load unsigned byte") (load-r-simm lduhi UHI OP_36 GR NA - ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) + ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) + (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load unsigned half") (load-r-simm ldbfi UQI OP_38 FRint FR-ACCESS - ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) + ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) + (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load byte float") (load-r-simm ldhfi UHI OP_39 FRint FR-ACCESS - ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) + ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) + (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load half float") (load-r-simm ldfi SI OP_3A FRint FR-ACCESS - ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) + ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) + (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load word float") (define-pmacro (ne-load-r-simm @@ -4362,7 +4856,8 @@ name not_gr mode op regtype attr profile comment) (dni name (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) attr) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) + (FR400-MAJOR I-2) (FR450-MAJOR I-2) attr) (.str name "$pack @($GRi,$d12),$" regtype "doublek") (+ pack (.sym regtype doublek) op GRi d12) (sequence ((WI address)) @@ -4372,10 +4867,12 @@ ) (load-double-r-simm lddi 0 DI OP_33 GR NA - ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) + ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) + (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load double word") (load-double-r-simm lddfi 1 DF OP_3B FR FR-ACCESS - ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) + ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) + (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load double float") (define-pmacro (ne-load-double-r-simm @@ -4438,7 +4935,8 @@ (define-pmacro (store-r-r name mode op ope reg attr profile comment) (dni name (comment) - ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) attr) + ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) + (FR400-MAJOR I-3) (FR450-MAJOR I-3) attr) (.str name "$pack $" reg "k,@($GRi,$GRj)") (+ pack (.sym reg k) op GRi ope GRj) (c-call VOID (.str "@cpu@_write_mem_" mode) @@ -4448,57 +4946,33 @@ ) (store-r-r stb QI OP_03 OPE1_00 GR NA - ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) + (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) "Store unsigned byte") (store-r-r sth HI OP_03 OPE1_01 GR NA - ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) + (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) "Store unsigned half") (store-r-r st SI OP_03 OPE1_02 GR NA - ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) + (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) "Store word") (store-r-r stbf QI OP_03 OPE1_08 FRint FR-ACCESS - ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) + (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) "Store byte float") (store-r-r sthf HI OP_03 OPE1_09 FRint FR-ACCESS - ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) + (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) "Store half float") (store-r-r stf SI OP_03 OPE1_0A FRint FR-ACCESS - ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) + (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) "Store word float") (store-r-r stc SI OP_03 OPE1_25 CPR (MACH frv) () "Store coprocessor word") -(define-pmacro (r-store name mode op ope reg size is_float profile comment) - (dni name - (comment) - ((UNIT STORE) (FR500-MAJOR I-3) (MACH frv)) - (.str name "$pack $" reg "k,@($GRi,$GRj)") - (+ pack (.sym reg k) op GRi ope GRj) - (sequence ((WI address)) - (set address (add GRi GRj)) - (c-call VOID (.str "@cpu@_write_mem_" mode) - pc address (.sym reg k)) - (c-call VOID "@cpu@_check_recovering_store" - address (index-of (.sym reg k)) size is_float)) - profile - ) -) - -(r-store rstb QI OP_03 OPE1_20 GR 1 0 - ((fr500 (unit u-gr-r-store))) "Store unsigned byte") -(r-store rsth HI OP_03 OPE1_21 GR 2 0 - ((fr500 (unit u-gr-r-store))) "Store unsigned half") -(r-store rst SI OP_03 OPE1_22 GR 4 0 - ((fr500 (unit u-gr-r-store))) "Store word") - -(r-store rstbf QI OP_03 OPE1_28 FRint 1 1 - ((fr500 (unit u-fr-r-store))) "Store byte float") -(r-store rsthf HI OP_03 OPE1_29 FRint 2 1 - ((fr500 (unit u-fr-r-store))) "Store half float") -(r-store rstf SI OP_03 OPE1_2A FRint 4 1 - ((fr500 (unit u-fr-r-store))) "Store word float") - ; Semantics for a store-double insn ; (define-pmacro (store-double-semantics mode regtype address arg) @@ -4511,7 +4985,8 @@ (define-pmacro (store-double-r-r name mode op ope regtype attr profile comment) (dni name (comment) - ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) attr) + ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) + (FR400-MAJOR I-3) (FR450-MAJOR I-3) attr) (.str name "$pack $" regtype "doublek,@($GRi,$GRj)") (+ pack (.sym regtype doublek) op GRi ope GRj) (sequence ((WI address)) @@ -4521,35 +4996,17 @@ ) (store-double-r-r std DI OP_03 OPE1_03 GR NA - ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) + (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) "Store double word") (store-double-r-r stdf DF OP_03 OPE1_0B FR FR-ACCESS - ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) + (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) "Store double float") (store-double-r-r stdc DI OP_03 OPE1_26 CPR (MACH frv) () "Store coprocessor double word") -(define-pmacro (r-store-double - name mode op ope regtype is_float attr profile comment) - (dni name - (comment) - ((UNIT STORE) (FR500-MAJOR I-3) (MACH frv) attr) - (.str name "$pack $" regtype "doublek,@($GRi,$GRj)") - (+ pack (.sym regtype doublek) op GRi ope GRj) - (sequence ((WI address)) - (store-double-semantics mode regtype address GRj) - (c-call VOID "@cpu@_check_recovering_store" - address (index-of (.sym regtype doublek)) 8 is_float)) - profile - ) -) - -(r-store-double rstd DI OP_03 OPE1_23 GR 0 NA - ((fr500 (unit u-gr-r-store))) "Store double word") -(r-store-double rstdf DF OP_03 OPE1_2B FR 1 FR-ACCESS - ((fr500 (unit u-fr-r-store))) "Store double float") - ; Semantics for a store-quad insn ; (define-pmacro (store-quad-semantics regtype address arg) @@ -4579,29 +5036,11 @@ (store-quad-r-r stqc OP_03 OPE1_27 CPR NA () "Store coprocessor quad word") -(define-pmacro (r-store-quad name op ope regtype is_float attr profile comment) - (dni name - (comment) - ((UNIT STORE) (FR500-MAJOR I-3) (MACH frv) attr) - (.str name "$pack $" regtype "k,@($GRi,$GRj)") - (+ pack (.sym regtype k) op GRi ope GRj) - (sequence ((WI address)) - (store-quad-semantics regtype address GRj) - (c-call VOID "@cpu@_check_recovering_store" - address (index-of (.sym regtype k)) 16 is_float)) - profile - ) -) - -(r-store-quad rstq OP_03 OPE1_24 GR 0 NA - ((fr500 (unit u-gr-r-store))) "Store quad word") -(r-store-quad rstqf OP_03 OPE1_2C FRint 1 FR-ACCESS - ((fr500 (unit u-fr-r-store))) "Store quad float") - (define-pmacro (store-r-r-u name mode op ope regtype attr profile comment) (dni name (comment) - ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) attr) + ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) + (FR400-MAJOR I-3) (FR450-MAJOR I-3) attr) (.str name "$pack $" regtype "k,@($GRi,$GRj)") (+ pack (.sym regtype k) op GRi ope GRj) (sequence ((UWI address)) @@ -4614,23 +5053,29 @@ ) (store-r-r-u stbu QI OP_03 OPE1_10 GR NA - ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) + (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) "Store unsigned byte, update index") (store-r-r-u sthu HI OP_03 OPE1_11 GR NA - ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) + (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) "Store unsigned half, update index") (store-r-r-u stu WI OP_03 OPE1_12 GR NA - ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) + (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) "Store word, update index") (store-r-r-u stbfu QI OP_03 OPE1_18 FRint FR-ACCESS - ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) + (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) "Store byte float, update index") (store-r-r-u sthfu HI OP_03 OPE1_19 FRint FR-ACCESS - ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) + (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) "Store half float, update index") (store-r-r-u stfu SI OP_03 OPE1_1A FRint FR-ACCESS - ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) + (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) "Store word float, update index") (store-r-r-u stcu SI OP_03 OPE1_2D CPR (MACH frv) () @@ -4640,7 +5085,8 @@ name mode op ope regtype attr profile comment) (dni name (comment) - ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) attr) + ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) + (FR400-MAJOR I-3) (FR450-MAJOR I-3) attr) (.str name "$pack $" regtype "doublek,@($GRi,$GRj)") (+ pack (.sym regtype doublek) op GRi ope GRj) (sequence ((WI address)) @@ -4651,10 +5097,12 @@ ) (store-double-r-r-u stdu DI OP_03 OPE1_13 GR NA - ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) + (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) "Store double word, update index") (store-double-r-r-u stdfu DF OP_03 OPE1_1B FR FR-ACCESS - ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) + (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) "Store double float,update index") (store-double-r-r-u stdcu DI OP_03 OPE1_2E CPR (MACH frv) () "Store coprocessor double word, update index") @@ -4684,7 +5132,8 @@ (define-pmacro (conditional-load name mode op ope regtype profile comment) (dni name (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) CONDITIONAL) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) + (FR400-MAJOR I-2) (FR450-MAJOR I-2) CONDITIONAL) (.str name "$pack @($GRi,$GRj),$" regtype "k,$CCi,$cond") (+ pack (.sym regtype k) op GRi CCi cond ope GRj) (if (eq CCi (or cond 2)) @@ -4695,36 +5144,45 @@ ) (conditional-load cldsb QI OP_5E OPE4_0 GR - ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) + ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) + (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load signed byte") (conditional-load cldub UQI OP_5E OPE4_1 GR - ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) + ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) + (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load unsigned byte") (conditional-load cldsh HI OP_5E OPE4_2 GR - ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) + ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) + (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load signed half") (conditional-load clduh UHI OP_5E OPE4_3 GR - ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) + ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) + (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load unsigned half") (conditional-load cld SI OP_5F OPE4_0 GR - ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) + ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) + (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load word") (conditional-load cldbf UQI OP_60 OPE4_0 FRint - ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) + ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) + (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load byte float") (conditional-load cldhf UHI OP_60 OPE4_1 FRint - ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) + ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) + (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load half float") (conditional-load cldf SI OP_60 OPE4_2 FRint - ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) + ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) + (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load word float") (define-pmacro (conditional-load-double name not_gr mode op ope regtype attr profile comment) (dni name (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) CONDITIONAL attr) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) + (FR400-MAJOR I-2) (FR450-MAJOR I-2) CONDITIONAL attr) (.str name "$pack @($GRi,$GRj),$" regtype "doublek,$CCi,$cond") (+ pack (.sym regtype doublek) op GRi CCi cond ope GRj) (if (eq CCi (or cond 2)) @@ -4735,10 +5193,12 @@ ) (conditional-load-double cldd 0 DI OP_5F OPE4_1 GR NA - ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) + ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) + (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load double word") (conditional-load-double clddf 1 DF OP_60 OPE4_3 FR FR-ACCESS - ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-fr-load))) + ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) + (fr500 (unit u-gr-load)) (fr550 (unit u-fr-load))) "Load double float") (dni cldq @@ -4755,7 +5215,8 @@ (define-pmacro (conditional-load-gr-u name mode op ope comment) (dni name (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) CONDITIONAL) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) + (FR400-MAJOR I-2) (FR450-MAJOR I-2) CONDITIONAL) (.str name "$pack @($GRi,$GRj),$GRk,$CCi,$cond") (+ pack GRk op GRi CCi cond ope GRj) (if (eq CCi (or cond 2)) @@ -4766,7 +5227,7 @@ pc address)) (if (ne (index-of GRi) (index-of GRk)) (set GRi address)))) - ((fr400 (unit u-gr-load)) + ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) ) ) @@ -4780,7 +5241,8 @@ (define-pmacro (conditional-load-non-gr-u name mode op ope regtype comment) (dni name (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) CONDITIONAL FR-ACCESS) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) + (FR400-MAJOR I-2) (FR450-MAJOR I-2) CONDITIONAL FR-ACCESS) (.str name "$pack @($GRi,$GRj),$" regtype "k,$CCi,$cond") (+ pack (.sym regtype k) op GRi CCi cond ope GRj) (if (eq CCi (or cond 2)) @@ -4790,7 +5252,7 @@ (c-call mode (.str "@cpu@_read_mem_" mode) pc address)) (set GRi address))) - ((fr400 (unit u-fr-load)) + ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) ) ) @@ -4802,7 +5264,8 @@ (dni clddu "Load double word, update" - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) CONDITIONAL) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) + (FR400-MAJOR I-2) (FR450-MAJOR I-2) CONDITIONAL) "clddu$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond" (+ pack GRdoublek OP_62 GRi CCi cond OPE4_1 GRj) (if (eq CCi (or cond 2)) @@ -4810,20 +5273,21 @@ (load-double-semantics 0 DI GR address GRj) (if (ne (index-of GRi) (index-of GRdoublek)) (set GRi address)))) - ((fr400 (unit u-gr-load)) + ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) ) (dni clddfu "Load double float, update" - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) CONDITIONAL FR-ACCESS) + ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) + (FR400-MAJOR I-2) (FR450-MAJOR I-2) CONDITIONAL FR-ACCESS) "clddfu$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond" (+ pack FRdoublek OP_63 GRi CCi cond OPE4_3 GRj) (if (eq CCi (or cond 2)) (sequence ((WI address)) (load-double-semantics 1 DF FR address GRj) (set GRi address))) - ((fr400 (unit u-fr-load)) + ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) ) @@ -4843,7 +5307,8 @@ (define-pmacro (conditional-store name mode op ope regtype profile comment) (dni name (comment) - ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) CONDITIONAL) + ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) + (FR400-MAJOR I-3) (FR450-MAJOR I-3) CONDITIONAL) (.str name "$pack $" regtype "k,@($GRi,$GRj),$CCi,$cond") (+ pack (.sym regtype k) op GRi CCi cond ope GRj) (if (eq CCi (or cond 2)) @@ -4854,30 +5319,37 @@ ) (conditional-store cstb QI OP_64 OPE4_0 GR - ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) + (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) "Store unsigned byte") (conditional-store csth HI OP_64 OPE4_1 GR - ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) + (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) "Store unsigned half") (conditional-store cst SI OP_64 OPE4_2 GR - ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) + (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) "Store word") (conditional-store cstbf QI OP_66 OPE4_0 FRint - ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) + (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) "Store byte float") (conditional-store csthf HI OP_66 OPE4_1 FRint - ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) + (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) "Store half float") (conditional-store cstf SI OP_66 OPE4_2 FRint - ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) + (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) "Store word float") (define-pmacro (conditional-store-double name mode op ope regtype attr profile comment) (dni name (comment) - ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) CONDITIONAL attr) + ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) + (FR400-MAJOR I-3) (FR450-MAJOR I-3) CONDITIONAL attr) (.str name "$pack $" regtype "doublek,@($GRi,$GRj),$CCi,$cond") (+ pack (.sym regtype doublek) op GRi CCi cond ope GRj) (if (eq CCi (or cond 2)) @@ -4888,10 +5360,12 @@ ) (conditional-store-double cstd DI OP_64 OPE4_3 GR NA - ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) + (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) "Store double word") (conditional-store-double cstdf DF OP_66 OPE4_3 FR FR-ACCESS - ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) + (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) "Store double float") (dni cstq @@ -4909,7 +5383,8 @@ name mode op ope regtype attr profile comment) (dni name (comment) - ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) CONDITIONAL attr) + ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) + (FR400-MAJOR I-3) (FR450-MAJOR I-3) CONDITIONAL attr) (.str name "$pack $" regtype "k,@($GRi,$GRj),$CCi,$cond") (+ pack (.sym regtype k) op GRi CCi cond ope GRj) (if (eq CCi (or cond 2)) @@ -4923,30 +5398,37 @@ ) (conditional-store-u cstbu QI OP_67 OPE4_0 GR NA - ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) + (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) "Store unsigned byte, update index") (conditional-store-u csthu HI OP_67 OPE4_1 GR NA - ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) + (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) "Store unsigned half, update index") (conditional-store-u cstu SI OP_67 OPE4_2 GR NA - ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) + (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) "Store word, update index") (conditional-store-u cstbfu QI OP_68 OPE4_0 FRint FR-ACCESS - ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) + (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) "Store byte float, update index") (conditional-store-u csthfu HI OP_68 OPE4_1 FRint FR-ACCESS - ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) + (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) "Store half float, update index") (conditional-store-u cstfu SI OP_68 OPE4_2 FRint FR-ACCESS - ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) + (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) "Store word float, update index") (define-pmacro (conditional-store-double-u name mode op ope regtype attr profile comment) (dni name (comment) - ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) CONDITIONAL attr) + ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) + (FR400-MAJOR I-3) (FR450-MAJOR I-3) CONDITIONAL attr) (.str name "$pack $" regtype "doublek,@($GRi,$GRj),$CCi,$cond") (+ pack (.sym regtype doublek) op GRi CCi cond ope GRj) (if (eq CCi (or cond 2)) @@ -4958,18 +5440,19 @@ ) (conditional-store-double-u cstdu DI OP_67 OPE4_3 GR NA - ((fr400 (unit u-gr-store)) + ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) "Store double word, update index") (conditional-store-double-u cstdfu DF OP_68 OPE4_3 FR FR-ACCESS - ((fr400 (unit u-fr-store)) + ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) "Store double float, update index") (define-pmacro (store-r-simm name mode op regtype attr profile comment) (dni name (comment) - ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) attr) + ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) + (FR400-MAJOR I-3) (FR450-MAJOR I-3) attr) (.str name "$pack $" regtype "k,@($GRi,$d12)") (+ pack (.sym regtype k) op GRi d12) (c-call VOID (.str "@cpu@_write_mem_" mode) @@ -4979,29 +5462,36 @@ ) (store-r-simm stbi QI OP_50 GR NA - ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) + (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) "Store unsigned byte") (store-r-simm sthi HI OP_51 GR NA - ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) + (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) "Store unsigned half") (store-r-simm sti SI OP_52 GR NA - ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) + ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) + (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) "Store word") (store-r-simm stbfi QI OP_4E FRint FR-ACCESS - ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) + (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) "Store byte float") (store-r-simm sthfi HI OP_4F FRint FR-ACCESS - ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) + (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) "Store half float") (store-r-simm stfi SI OP_55 FRint FR-ACCESS - ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) + ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) + (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) "Store word float") (define-pmacro (store-double-r-simm name mode op regtype attr profile comment) (dni name (comment) - ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) attr) + ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) + (FR400-MAJOR I-3) (FR450-MAJOR I-3) attr) (.str name "$pack $" regtype "doublek,@($GRi,$d12)") (+ pack (.sym regtype doublek) op GRi d12) (sequence ((WI address)) @@ -5011,11 +5501,11 @@ ) (store-double-r-simm stdi DI OP_53 GR NA - ((fr400 (unit u-gr-store)) + ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) "Store double word") (store-double-r-simm stdfi DF OP_56 FR FR-ACCESS - ((fr400 (unit u-fr-store)) + ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) "Store double float") @@ -5047,32 +5537,35 @@ (dni swap "Swap contents of memory with GR" - ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2)) + ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) + (FR400-MAJOR C-2) (FR450-MAJOR C-2)) "swap$pack @($GRi,$GRj),$GRk" (+ pack GRk OP_03 GRi OPE1_05 GRj) (swap-semantics GRi GRj GRk) - ((fr400 (unit u-swap)) + ((fr400 (unit u-swap)) (fr450 (unit u-swap)) (fr500 (unit u-swap)) (fr550 (unit u-swap))) ) (dni "swapi" "Swap contents of memory with GR" - ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2)) + ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) + (FR400-MAJOR C-2) (FR450-MAJOR C-2)) ("swapi$pack @($GRi,$d12),$GRk") (+ pack GRk OP_4D GRi d12) (swap-semantics GRi d12 GRk) - ((fr400 (unit u-swap)) + ((fr400 (unit u-swap)) (fr450 (unit u-swap)) (fr500 (unit u-swap)) (fr550 (unit u-swap))) ) (dni cswap "Conditionally swap contents of memory with GR" - ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2) CONDITIONAL) + ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) + (FR400-MAJOR C-2) (FR450-MAJOR C-2) CONDITIONAL) "cswap$pack @($GRi,$GRj),$GRk,$CCi,$cond" (+ pack GRk OP_65 GRi CCi cond OPE4_2 GRj) (if (eq CCi (or cond 2)) (swap-semantics GRi GRj GRk)) - ((fr400 (unit u-swap)) + ((fr400 (unit u-swap)) (fr450 (unit u-swap)) (fr500 (unit u-swap)) (fr550 (unit u-swap))) ) @@ -5090,13 +5583,17 @@ (register-transfer movgf OP_03 OPE1_15 GRj FRintk I0 - ((FR500-MAJOR I-4) (FR550-MAJOR I-5) (FR400-MAJOR I-4) FR-ACCESS) - ((fr400 (unit u-gr2fr)) (fr500 (unit u-gr2fr)) (fr550 (unit u-gr2fr))) + ((FR500-MAJOR I-4) (FR550-MAJOR I-5) + (FR400-MAJOR I-4) (FR450-MAJOR I-4) FR-ACCESS) + ((fr400 (unit u-gr2fr)) (fr450 (unit u-gr2fr)) + (fr500 (unit u-gr2fr)) (fr550 (unit u-gr2fr))) "transfer gr to fr") (register-transfer movfg OP_03 OPE1_0D FRintk GRj I0 - ((FR500-MAJOR I-4) (FR550-MAJOR I-5) (FR400-MAJOR I-4) FR-ACCESS) - ((fr400 (unit u-fr2gr)) (fr500 (unit u-fr2gr)) (fr550 (unit u-fr2gr))) + ((FR500-MAJOR I-4) (FR550-MAJOR I-5) + (FR400-MAJOR I-4) (FR450-MAJOR I-4) FR-ACCESS) + ((fr400 (unit u-fr2gr)) (fr450 (unit u-fr2gr)) + (fr500 (unit u-fr2gr)) (fr550 (unit u-fr2gr))) "transfer fr to gr") (define-pmacro (nextreg hw r offset) (reg hw (add (index-of r) offset))) @@ -5114,12 +5611,13 @@ (dni movgfd "move GR for FR double" - ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5) (FR400-MAJOR I-4) FR-ACCESS) + ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5) + (FR400-MAJOR I-4) (FR450-MAJOR I-4) FR-ACCESS) "movgfd$pack $GRj,$FRintk" (+ pack FRintk OP_03 (rs-null) OPE1_16 GRj) (register-transfer-double-from-gr-semantics 1) ; TODO -- doesn't handle second register in the pair - ((fr400 (unit u-gr2fr)) + ((fr400 (unit u-gr2fr)) (fr450 (unit u-gr2fr)) (fr500 (unit u-gr2fr)) (fr550 (unit u-gr2fr))) ) @@ -5132,12 +5630,13 @@ (dni movfgd "move FR for GR double" - ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5) (FR400-MAJOR I-4) FR-ACCESS) + ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5) + (FR400-MAJOR I-4) (FR450-MAJOR I-4) FR-ACCESS) "movfgd$pack $FRintk,$GRj" (+ pack FRintk OP_03 (rs-null) OPE1_0E GRj) (register-transfer-double-to-gr-semantics 1) ; TODO -- doesn't handle second register in the pair - ((fr400 (unit u-fr2gr)) + ((fr400 (unit u-fr2gr)) (fr450 (unit u-fr2gr)) (fr500 (unit u-fr2gr)) (fr550 (unit u-fr2gr))) ) @@ -5194,34 +5693,40 @@ ) (conditional-register-transfer cmovgf OP_69 OPE4_0 GRj FRintk I0 - ((FR500-MAJOR I-4) (FR550-MAJOR I-5) (FR400-MAJOR I-4)) - ((fr400 (unit u-gr2fr)) (fr500 (unit u-gr2fr)) (fr550 (unit u-gr2fr))) + ((FR500-MAJOR I-4) (FR550-MAJOR I-5) + (FR400-MAJOR I-4) (FR450-MAJOR I-4)) + ((fr400 (unit u-gr2fr)) (fr450 (unit u-gr2fr)) + (fr500 (unit u-gr2fr)) (fr550 (unit u-gr2fr))) "transfer gr to fr") (conditional-register-transfer cmovfg OP_69 OPE4_2 FRintk GRj I0 - ((FR500-MAJOR I-4) (FR550-MAJOR I-5) (FR400-MAJOR I-4)) - ((fr400 (unit u-fr2gr)) (fr500 (unit u-fr2gr)) (fr550 (unit u-fr2gr))) + ((FR500-MAJOR I-4) (FR550-MAJOR I-5) + (FR400-MAJOR I-4) (FR450-MAJOR I-4)) + ((fr400 (unit u-fr2gr)) (fr450 (unit u-fr2gr)) + (fr500 (unit u-fr2gr)) (fr550 (unit u-fr2gr))) "transfer fr to gr") (dni cmovgfd "Conditional move GR to FR double" - ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5) (FR400-MAJOR I-4) CONDITIONAL FR-ACCESS) + ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5) + (FR400-MAJOR I-4) (FR450-MAJOR I-4) CONDITIONAL FR-ACCESS) "cmovgfd$pack $GRj,$FRintk,$CCi,$cond" (+ pack FRintk OP_69 (rs-null) CCi cond OPE4_1 GRj) (register-transfer-double-from-gr-semantics (eq CCi (or cond 2))) ; TODO -- doesn't handle extra registers in double - ((fr400 (unit u-gr2fr)) + ((fr400 (unit u-gr2fr)) (fr450 (unit u-gr2fr)) (fr500 (unit u-gr2fr)) (fr550 (unit u-gr2fr))) ) (dni cmovfgd "Conditional move FR to GR double" - ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5) (FR400-MAJOR I-4) CONDITIONAL FR-ACCESS) + ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5) + (FR400-MAJOR I-4) (FR450-MAJOR I-4) CONDITIONAL FR-ACCESS) "cmovfgd$pack $FRintk,$GRj,$CCi,$cond" (+ pack FRintk OP_69 (rs-null) CCi cond OPE4_3 GRj) (register-transfer-double-to-gr-semantics (eq CCi (or cond 2))) ; TODO -- doesn't handle second register in the pair - ((fr400 (unit u-fr2gr)) + ((fr400 (unit u-fr2gr)) (fr450 (unit u-fr2gr)) (fr500 (unit u-fr2gr)) (fr550 (unit u-fr2gr))) ) @@ -5229,11 +5734,12 @@ name op ope reg_src reg_targ unitname comment) (dni name (comment) - ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2)) + ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) + (FR400-MAJOR C-2) (FR450-MAJOR C-2)) (.str name "$pack $" reg_src ",$" reg_targ) (+ pack reg_targ op ope reg_src) (set reg_targ reg_src) - ((fr400 (unit unitname)) + ((fr400 (unit unitname)) (fr450 (unit unitname)) (fr500 (unit unitname)) (fr550 (unit unitname))) ) ) @@ -5280,37 +5786,40 @@ (define-pmacro (conditional-branch-i prefix cc op cond comment) (dni (.sym prefix cc) (comment) - ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) (FR400-MAJOR B-1)) + ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) + (FR400-MAJOR B-1) (FR450-MAJOR B-1)) (.str (.sym prefix cc) "$pack $ICCi_2,$hint,$label16") (+ pack (.sym ICC_ cc) ICCi_2 op hint label16) (sequence () (c-call VOID "@cpu@_model_branch" label16 hint) (if (cond ICCi_2) (set pc label16))) - ((fr400 (unit u-branch)) + ((fr400 (unit u-branch)) (fr450 (unit u-branch)) (fr500 (unit u-branch)) (fr550 (unit u-branch))) ) ) (dni bra "integer branch equal" - ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) (FR400-MAJOR B-1)) + ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) + (FR400-MAJOR B-1) (FR450-MAJOR B-1)) "bra$pack $hint_taken$label16" (+ pack ICC_ra (ICCi_2-null) OP_06 hint_taken label16) (sequence () (c-call VOID "@cpu@_model_branch" label16 hint_taken) (set pc label16)) - ((fr400 (unit u-branch)) + ((fr400 (unit u-branch)) (fr450 (unit u-branch)) (fr500 (unit u-branch)) (fr550 (unit u-branch))) ) (dni bno "integer branch never" - ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) (FR400-MAJOR B-1)) + ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) + (FR400-MAJOR B-1) (FR450-MAJOR B-1)) "bno$pack$hint_not_taken" (+ pack ICC_nev (ICCi_2-null) OP_06 hint_not_taken (label16-null)) (c-call VOID "@cpu@_model_branch" label16 hint_not_taken) - ((fr400 (unit u-branch)) + ((fr400 (unit u-branch)) (fr450 (unit u-branch)) (fr500 (unit u-branch)) (fr550 (unit u-branch))) ) @@ -5332,36 +5841,39 @@ (define-pmacro (conditional-branch-f prefix cc op cond comment) (dni (.sym prefix cc) (comment) - ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) (FR400-MAJOR B-1) FR-ACCESS) + ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) + (FR400-MAJOR B-1) (FR450-MAJOR B-1) FR-ACCESS) (.str (.sym prefix cc) "$pack $FCCi_2,$hint,$label16") (+ pack (.sym FCC_ cc) FCCi_2 op hint label16) (sequence () (c-call VOID "@cpu@_model_branch" label16 hint) (if (cond FCCi_2) (set pc label16))) - ((fr400 (unit u-branch)) + ((fr400 (unit u-branch)) (fr450 (unit u-branch)) (fr500 (unit u-branch)) (fr550 (unit u-branch))) ) ) (dni fbra "float branch equal" - ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) (FR400-MAJOR B-1) FR-ACCESS) + ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) + (FR400-MAJOR B-1) (FR450-MAJOR B-1) FR-ACCESS) "fbra$pack $hint_taken$label16" (+ pack FCC_ra (FCCi_2-null) OP_07 hint_taken label16) (sequence () (c-call VOID "@cpu@_model_branch" label16 hint_taken) (set pc label16)) - ((fr400 (unit u-branch)) + ((fr400 (unit u-branch)) (fr450 (unit u-branch)) (fr500 (unit u-branch)) (fr550 (unit u-branch))) ) (dni fbno "float branch never" - ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) (FR400-MAJOR B-1) FR-ACCESS) + ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) + (FR400-MAJOR B-1) (FR450-MAJOR B-1) FR-ACCESS) "fbno$pack$hint_not_taken" (+ pack FCC_nev (FCCi_2-null) OP_07 hint_not_taken (label16-null)) (c-call VOID "@cpu@_model_branch" label16 hint_not_taken) - ((fr400 (unit u-branch)) + ((fr400 (unit u-branch)) (fr450 (unit u-branch)) (fr500 (unit u-branch)) (fr550 (unit u-branch))) ) @@ -5394,50 +5906,54 @@ (dni bctrlr "LCR conditional branch to lr" - ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) (FR400-MAJOR B-2)) + ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) + (FR400-MAJOR B-2) (FR450-MAJOR B-2)) ("bctrlr$pack $ccond,$hint") (+ pack (cond-null) (ICCi_2-null) OP_0E hint OPE3_01 ccond (s12-null)) (sequence () (c-call VOID "@cpu@_model_branch" (spr-lr) hint) (ctrlr-branch-semantics (const BI 1) ccond)) - ((fr400 (unit u-branch)) + ((fr400 (unit u-branch)) (fr450 (unit u-branch)) (fr500 (unit u-branch)) (fr550 (unit u-branch))) ) (define-pmacro (conditional-branch-cclr prefix cc i-f op ope cond attr comment) (dni (.sym prefix cc lr) (comment) - ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) (FR400-MAJOR B-3) attr) + ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) + (FR400-MAJOR B-3) (FR450-MAJOR B-3) attr) (.str (.sym prefix cc lr) "$pack $" i-f "CCi_2,$hint") (+ pack (.sym i-f CC_ cc) (.sym i-f CCi_2) op hint ope (ccond-null) (s12-null)) (sequence () (c-call VOID "@cpu@_model_branch" (spr-lr) hint) (if (cond (.sym i-f CCi_2)) (set pc (spr-lr)))) - ((fr400 (unit u-branch)) + ((fr400 (unit u-branch)) (fr450 (unit u-branch)) (fr500 (unit u-branch)) (fr550 (unit u-branch))) ) ) (dni bralr "integer cclr branch always" - ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) (FR400-MAJOR B-3)) + ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) + (FR400-MAJOR B-3) (FR450-MAJOR B-3)) "bralr$pack$hint_taken" (+ pack ICC_ra (ICCi_2-null) OP_0E hint_taken OPE3_02 (ccond-null) (s12-null)) (sequence () (c-call VOID "@cpu@_model_branch" (spr-lr) hint_taken) (set pc (spr-lr))) - ((fr400 (unit u-branch)) + ((fr400 (unit u-branch)) (fr450 (unit u-branch)) (fr500 (unit u-branch)) (fr550 (unit u-branch))) ) (dni bnolr "integer cclr branch never" - ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) (FR400-MAJOR B-3)) + ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) + (FR400-MAJOR B-3) (FR450-MAJOR B-3)) "bnolr$pack$hint_not_taken" (+ pack ICC_nev (ICCi_2-null) OP_0E hint_not_taken OPE3_02 (ccond-null) (s12-null)) (c-call VOID "@cpu@_model_branch" (spr-lr) hint_not_taken) - ((fr400 (unit u-branch)) + ((fr400 (unit u-branch)) (fr450 (unit u-branch)) (fr500 (unit u-branch)) (fr550 (unit u-branch))) ) @@ -5458,23 +5974,25 @@ (dni fbralr "float cclr branch always" - ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) (FR400-MAJOR B-3) FR-ACCESS) + ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) + (FR400-MAJOR B-3) (FR450-MAJOR B-3) FR-ACCESS) "fbralr$pack$hint_taken" (+ pack FCC_ra (FCCi_2-null) OP_0E hint_taken OPE3_06 (ccond-null) (s12-null)) (sequence () (c-call VOID "@cpu@_model_branch" (spr-lr) hint_taken) (set pc (spr-lr))) - ((fr400 (unit u-branch)) + ((fr400 (unit u-branch)) (fr450 (unit u-branch)) (fr500 (unit u-branch)) (fr550 (unit u-branch))) ) (dni fbnolr "float cclr branch never" - ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) (FR400-MAJOR B-3) FR-ACCESS) + ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) + (FR400-MAJOR B-3) (FR450-MAJOR B-3) FR-ACCESS) "fbnolr$pack$hint_not_taken" (+ pack FCC_nev (FCCi_2-null) OP_0E hint_not_taken OPE3_06 (ccond-null) (s12-null)) (c-call VOID "@cpu@_model_branch" (spr-lr) hint_not_taken) - ((fr400 (unit u-branch)) + ((fr400 (unit u-branch)) (fr450 (unit u-branch)) (fr500 (unit u-branch)) (fr550 (unit u-branch))) ) @@ -5496,38 +6014,41 @@ (define-pmacro (conditional-branch-ctrlr prefix cc i-f op ope cond attr comment) (dni (.sym prefix cc lr) (comment) - ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) (FR400-MAJOR B-2) attr) + ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) + (FR400-MAJOR B-2) (FR450-MAJOR B-2) attr) (.str (.sym prefix cc lr) "$pack $" i-f "CCi_2,$ccond,$hint") (+ pack (.sym i-f CC_ cc) (.sym i-f CCi_2) op hint ope ccond (s12-null)) (sequence () (c-call VOID "@cpu@_model_branch" (spr-lr) hint) (ctrlr-branch-semantics (cond (.sym i-f CCi_2)) ccond)) - ((fr400 (unit u-branch)) + ((fr400 (unit u-branch)) (fr450 (unit u-branch)) (fr500 (unit u-branch)) (fr550 (unit u-branch))) ) ) (dni bcralr "integer ctrlr branch always" - ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) (FR400-MAJOR B-2)) + ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) + (FR400-MAJOR B-2) (FR450-MAJOR B-2)) "bcralr$pack $ccond$hint_taken" (+ pack ICC_ra (ICCi_2-null) OP_0E hint_taken OPE3_03 ccond (s12-null)) (sequence () (c-call VOID "@cpu@_model_branch" (spr-lr) hint_taken) (ctrlr-branch-semantics (const BI 1) ccond)) - ((fr400 (unit u-branch)) + ((fr400 (unit u-branch)) (fr450 (unit u-branch)) (fr500 (unit u-branch)) (fr550 (unit u-branch))) ) (dni bcnolr "integer ctrlr branch never" - ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) (FR400-MAJOR B-2)) + ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) + (FR400-MAJOR B-2) (FR450-MAJOR B-2)) "bcnolr$pack$hint_not_taken" (+ pack ICC_nev (ICCi_2-null) OP_0E hint_not_taken OPE3_03 (ccond-null) (s12-null)) (sequence () (c-call VOID "@cpu@_model_branch" (spr-lr) hint_not_taken) (ctrlr-branch-semantics (const BI 0) ccond)) - ((fr400 (unit u-branch)) + ((fr400 (unit u-branch)) (fr450 (unit u-branch)) (fr500 (unit u-branch)) (fr550 (unit u-branch))) ) @@ -5548,25 +6069,27 @@ (dni fcbralr "float ctrlr branch always" - ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) (FR400-MAJOR B-2) FR-ACCESS) + ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) + (FR400-MAJOR B-2) (FR450-MAJOR B-2) FR-ACCESS) "fcbralr$pack $ccond$hint_taken" (+ pack FCC_ra (FCCi_2-null) OP_0E hint_taken OPE3_07 ccond (s12-null)) (sequence () (c-call VOID "@cpu@_model_branch" (spr-lr) hint_taken) (ctrlr-branch-semantics (const BI 1) ccond)) - ((fr400 (unit u-branch)) + ((fr400 (unit u-branch)) (fr450 (unit u-branch)) (fr500 (unit u-branch)) (fr550 (unit u-branch))) ) (dni fcbnolr "float ctrlr branch never" - ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) (FR400-MAJOR B-2) FR-ACCESS) + ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) + (FR400-MAJOR B-2) (FR450-MAJOR B-2) FR-ACCESS) "fcbnolr$pack$hint_not_taken" (+ pack FCC_nev (FCCi_2-null) OP_0E hint_not_taken OPE3_07 (ccond-null) (s12-null)) (sequence () (c-call VOID "@cpu@_model_branch" (spr-lr) hint_not_taken) (ctrlr-branch-semantics (const BI 0) ccond)) - ((fr400 (unit u-branch)) + ((fr400 (unit u-branch)) (fr450 (unit u-branch)) (fr500 (unit u-branch)) (fr550 (unit u-branch))) ) @@ -5596,60 +6119,66 @@ (dni jmpl "jump and link" - ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) (FR400-MAJOR I-5)) + ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) + (FR400-MAJOR I-5) (FR450-MAJOR I-5)) "jmpl$pack @($GRi,$GRj)" (+ pack (misc-null-1) (LI-off) OP_0C GRi (misc-null-2) GRj) (jump-and-link-semantics GRi GRj LI) - ((fr400 (unit u-branch)) + ((fr400 (unit u-branch)) (fr450 (unit u-branch)) (fr500 (unit u-branch)) (fr550 (unit u-branch))) ) (dni calll "call and link" - ((UNIT I0) (FR500-MAJOR I-5) (FR400-MAJOR I-5)) + ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) + (FR400-MAJOR I-5) (FR450-MAJOR I-5)) "calll$pack @($GRi,$GRj)" (+ pack (misc-null-1) (LI-on) OP_0C GRi (misc-null-2) GRj) (jump-and-link-semantics GRi GRj LI) - ((fr400 (unit u-branch)) - (fr500 (unit u-branch))) + ((fr400 (unit u-branch)) (fr450 (unit u-branch)) + (fr500 (unit u-branch)) (fr550 (unit u-branch))) ) (dni jmpil "jump immediate and link" - ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) (FR400-MAJOR I-5)) + ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) + (FR400-MAJOR I-5) (FR450-MAJOR I-5)) "jmpil$pack @($GRi,$s12)" (+ pack (misc-null-1) (LI-off) OP_0D GRi s12) (jump-and-link-semantics GRi s12 LI) - ((fr400 (unit u-branch)) + ((fr400 (unit u-branch)) (fr450 (unit u-branch)) (fr500 (unit u-branch)) (fr550 (unit u-branch))) ) (dni callil "call immediate and link" - ((UNIT I0) (FR500-MAJOR I-5) (FR400-MAJOR I-5)) + ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) + (FR400-MAJOR I-5) (FR450-MAJOR I-5)) "callil$pack @($GRi,$s12)" (+ pack (misc-null-1) (LI-on) OP_0D GRi s12) (jump-and-link-semantics GRi s12 LI) - ((fr400 (unit u-branch)) - (fr500 (unit u-branch))) + ((fr400 (unit u-branch)) (fr450 (unit u-branch)) + (fr500 (unit u-branch)) (fr550 (unit u-branch))) ) (dni call "call and link" - ((UNIT B0) (FR500-MAJOR B-4) (FR550-MAJOR B-4) (FR400-MAJOR B-4)) + ((UNIT B0) (FR500-MAJOR B-4) (FR550-MAJOR B-4) + (FR400-MAJOR B-4) (FR450-MAJOR B-4)) "call$pack $label24" (+ pack OP_0F label24) (sequence () (c-call VOID "@cpu@_set_write_next_vliw_addr_to_LR" 1) (set pc label24) (c-call VOID "@cpu@_model_branch" pc #x2)) ; hint branch taken - ((fr400 (unit u-branch)) + ((fr400 (unit u-branch)) (fr450 (unit u-branch)) (fr500 (unit u-branch)) (fr550 (unit u-branch))) ) (dni rett "return from trap" - ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2) PRIVILEGED) + ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) + (FR400-MAJOR C-2) (FR450-MAJOR C-2) PRIVILEGED) "rett$pack $debug" (+ pack (misc-null-1) debug OP_05 (rs-null) (s12-null)) ; frv_rett handles operating vs user mode @@ -5700,32 +6229,35 @@ (define-pmacro (trap-r prefix cc i-f op ope cond attr comment) (dni (.sym prefix cc) (comment) - ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1) attr) + ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) + (FR400-MAJOR C-1) (FR450-MAJOR C-1) attr) (.str (.sym prefix cc) "$pack $" i-f "CCi_2,$GRi,$GRj") (+ pack (.sym i-f CC_ cc) (.sym i-f CCi_2) op GRi (misc-null-3) ope GRj) (trap-semantics (cond (.sym i-f CCi_2)) GRi GRj) - ((fr400 (unit u-trap)) + ((fr400 (unit u-trap)) (fr450 (unit u-trap)) (fr500 (unit u-trap)) (fr550 (unit u-trap))) ) ) (dni tra "integer trap always" - ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1)) + ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) + (FR400-MAJOR C-1) (FR450-MAJOR C-1)) "tra$pack $GRi,$GRj" (+ pack ICC_ra (ICCi_2-null) OP_04 GRi (misc-null-3) OPE4_0 GRj) (trap-semantics (const BI 1) GRi GRj) - ((fr400 (unit u-trap)) + ((fr400 (unit u-trap)) (fr450 (unit u-trap)) (fr500 (unit u-trap)) (fr550 (unit u-trap))) ) (dni tno "integer trap never" - ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1)) + ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) + (FR400-MAJOR C-1) (FR450-MAJOR C-1)) "tno$pack" (+ pack ICC_nev (ICCi_2-null) OP_04 (GRi-null) (misc-null-3) OPE4_0 (GRj-null)) (trap-semantics (const BI 0) GRi GRj) - ((fr400 (unit u-trap)) + ((fr400 (unit u-trap)) (fr450 (unit u-trap)) (fr500 (unit u-trap)) (fr550 (unit u-trap))) ) @@ -5746,21 +6278,23 @@ (dni ftra "float trap always" - ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1) FR-ACCESS) + ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) + (FR400-MAJOR C-1) (FR450-MAJOR C-1) FR-ACCESS) "ftra$pack $GRi,$GRj" (+ pack FCC_ra (FCCi_2-null) OP_04 GRi (misc-null-3) OPE4_1 GRj) (trap-semantics (const BI 1) GRi GRj) - ((fr400 (unit u-trap)) + ((fr400 (unit u-trap)) (fr450 (unit u-trap)) (fr500 (unit u-trap)) (fr550 (unit u-trap))) ) (dni ftno "flost trap never" - ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1) FR-ACCESS) + ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) + (FR400-MAJOR C-1) (FR450-MAJOR C-1) FR-ACCESS) "ftno$pack" (+ pack FCC_nev (FCCi_2-null) OP_04 (GRi-null) (misc-null-3) OPE4_1 (GRj-null)) (trap-semantics (const BI 0) GRi GRj) - ((fr400 (unit u-trap)) + ((fr400 (unit u-trap)) (fr450 (unit u-trap)) (fr500 (unit u-trap)) (fr550 (unit u-trap))) ) @@ -5782,32 +6316,35 @@ (define-pmacro (trap-immed prefix cc i-f op cond attr comment) (dni (.sym prefix cc) (comment) - ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1) attr) + ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) + (FR400-MAJOR C-1) (FR450-MAJOR C-1) attr) (.str (.sym prefix cc) "$pack $" i-f "CCi_2,$GRi,$s12") (+ pack (.sym i-f CC_ cc) (.sym i-f CCi_2) op GRi s12) (trap-semantics (cond (.sym i-f CCi_2)) GRi s12) - ((fr400 (unit u-trap)) + ((fr400 (unit u-trap)) (fr450 (unit u-trap)) (fr500 (unit u-trap)) (fr550 (unit u-trap))) ) ) (dni tira "integer trap always" - ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1)) + ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) + (FR400-MAJOR C-1) (FR450-MAJOR C-1)) "tira$pack $GRi,$s12" (+ pack ICC_ra (ICCi_2-null) OP_1C GRi s12) (trap-semantics (const BI 1) GRi s12) - ((fr400 (unit u-trap)) + ((fr400 (unit u-trap)) (fr450 (unit u-trap)) (fr500 (unit u-trap)) (fr550 (unit u-trap))) ) (dni tino "integer trap never" - ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1)) + ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) + (FR400-MAJOR C-1) (FR450-MAJOR C-1)) "tino$pack" (+ pack ICC_nev (ICCi_2-null) OP_1C (GRi-null) (s12-null)) (trap-semantics (const BI 0) GRi s12) - ((fr400 (unit u-trap)) + ((fr400 (unit u-trap)) (fr450 (unit u-trap)) (fr500 (unit u-trap)) (fr550 (unit u-trap))) ) @@ -5828,7 +6365,8 @@ (dni ftira "float trap always" - ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1) FR-ACCESS) + ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) + (FR400-MAJOR C-1) (FR450-MAJOR C-1) FR-ACCESS) "ftira$pack $GRi,$s12" (+ pack FCC_ra (ICCi_2-null) OP_1D GRi s12) (trap-semantics (const BI 1) GRi s12) @@ -5838,11 +6376,12 @@ (dni ftino "float trap never" - ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1) FR-ACCESS) + ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) + (FR400-MAJOR C-1) (FR450-MAJOR C-1) FR-ACCESS) "ftino$pack" (+ pack FCC_nev (FCCi_2-null) OP_1D (GRi-null) (s12-null)) (trap-semantics (const BI 0) GRi s12) - ((fr400 (unit u-trap)) + ((fr400 (unit u-trap)) (fr450 (unit u-trap)) (fr500 (unit u-trap)) (fr550 (unit u-trap))) ) @@ -5863,7 +6402,8 @@ (dni break "break trap" - ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1)) + ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) + (FR400-MAJOR C-1) (FR450-MAJOR C-1)) "break$pack" (+ pack (rd-null) OP_04 (rs-null) (misc-null-3) OPE4_3 (GRj-null)) (sequence () @@ -5891,7 +6431,8 @@ (dni mtrap "media trap" - ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1) FR-ACCESS) + ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) + (FR400-MAJOR C-1) (FR450-MAJOR C-1) FR-ACCESS) "mtrap$pack" (+ pack (rd-null) OP_04 (rs-null) (misc-null-3) OPE4_2 (GRj-null)) (c-call VOID "frv_mtrap") @@ -5901,7 +6442,8 @@ (define-pmacro (condition-code-logic name operation ope comment) (dni name (comment) - ((UNIT B01) (FR500-MAJOR B-6) (FR550-MAJOR B-6) (FR400-MAJOR B-6)) + ((UNIT B01) (FR500-MAJOR B-6) (FR550-MAJOR B-6) + (FR400-MAJOR B-6) (FR450-MAJOR B-6)) (.str name "$pack $CRi,$CRj,$CRk") (+ pack (misc-null-6) CRk OP_0A (misc-null-7) CRi ope (misc-null-8) CRj) (set CRk (c-call UQI "@cpu@_cr_logic" operation CRi CRj)) @@ -5934,7 +6476,8 @@ (dni notcr ("not cccr register") - ((UNIT B01) (FR500-MAJOR B-6) (FR550-MAJOR B-6) (FR400-MAJOR B-6)) + ((UNIT B01) (FR500-MAJOR B-6) (FR550-MAJOR B-6) + (FR400-MAJOR B-6) (FR450-MAJOR B-6)) (.str notcr "$pack $CRj,$CRk") (+ pack (misc-null-6) CRk OP_0A (rs-null) OPE1_0B (misc-null-8) CRj) (set CRk (xor CRj 1)) @@ -5948,32 +6491,35 @@ (define-pmacro (check-int-condition-code prefix cc op cond comment) (dni (.sym prefix cc) (comment) - ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5)) + ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) + (FR400-MAJOR B-5) (FR450-MAJOR B-5)) (.str (.sym prefix cc) "$pack $ICCi_3,$CRj_int") (+ pack (.sym ICC_ cc) CRj_int op (misc-null-5) ICCi_3) (check-semantics (cond ICCi_3) CRj_int) - ((fr400 (unit u-check)) + ((fr400 (unit u-check)) (fr450 (unit u-check)) (fr500 (unit u-check)) (fr550 (unit u-check))) ) ) (dni ckra "check integer cc always" - ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5)) + ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) + (FR400-MAJOR B-5) (FR450-MAJOR B-5)) "ckra$pack $CRj_int" (+ pack ICC_ra CRj_int OP_08 (misc-null-5) (ICCi_3-null)) (check-semantics (const BI 1) CRj_int) - ((fr400 (unit u-check)) + ((fr400 (unit u-check)) (fr450 (unit u-check)) (fr500 (unit u-check)) (fr550 (unit u-check))) ) (dni ckno "check integer cc never" - ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5)) + ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) + (FR400-MAJOR B-5) (FR450-MAJOR B-5)) "ckno$pack $CRj_int" (+ pack ICC_nev CRj_int OP_08 (misc-null-5) (ICCi_3-null)) (check-semantics (const BI 0) CRj_int) - ((fr400 (unit u-check)) + ((fr400 (unit u-check)) (fr450 (unit u-check)) (fr500 (unit u-check)) (fr550 (unit u-check))) ) @@ -5995,32 +6541,35 @@ (define-pmacro (check-float-condition-code prefix cc op cond comment) (dni (.sym prefix cc) (comment) - ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) FR-ACCESS) + ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) + (FR400-MAJOR B-5) (FR450-MAJOR B-5) FR-ACCESS) (.str (.sym prefix cc) "$pack $FCCi_3,$CRj_float") (+ pack (.sym FCC_ cc) CRj_float op (misc-null-5) FCCi_3) (check-semantics (cond FCCi_3) CRj_float) - ((fr400 (unit u-check)) + ((fr400 (unit u-check)) (fr450 (unit u-check)) (fr500 (unit u-check)) (fr550 (unit u-check))) ) ) (dni fckra "check float cc always" - ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) FR-ACCESS) + ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) + (FR400-MAJOR B-5) (FR450-MAJOR B-5) FR-ACCESS) "fckra$pack $CRj_float" (+ pack FCC_ra CRj_float OP_09 (misc-null-5) FCCi_3) (check-semantics (const BI 1) CRj_float) - ((fr400 (unit u-check)) + ((fr400 (unit u-check)) (fr450 (unit u-check)) (fr500 (unit u-check)) (fr550 (unit u-check))) ) (dni fckno "check float cc never" - ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) FR-ACCESS) + ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) + (FR400-MAJOR B-5) (FR450-MAJOR B-5) FR-ACCESS) "fckno$pack $CRj_float" (+ pack FCC_nev CRj_float OP_09 (misc-null-5) FCCi_3) (check-semantics (const BI 0) CRj_float) - ((fr400 (unit u-check)) + ((fr400 (unit u-check)) (fr450 (unit u-check)) (fr500 (unit u-check)) (fr550 (unit u-check))) ) @@ -6042,41 +6591,44 @@ (define-pmacro (conditional-check-int-condition-code prefix cc op ope test comment) (dni (.sym prefix cc) (comment) - ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) CONDITIONAL) + ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) + (FR400-MAJOR B-5) (FR450-MAJOR B-5) CONDITIONAL) (.str (.sym prefix cc) "$pack $ICCi_3,$CRj_int,$CCi,$cond") (+ pack (.sym ICC_ cc) CRj_int op (rs-null) CCi cond ope (misc-null-9) ICCi_3) (if (eq CCi (or cond 2)) (check-semantics (test ICCi_3) CRj_int) (set CRj_int (cr-undefined))) - ((fr400 (unit u-check)) + ((fr400 (unit u-check)) (fr450 (unit u-check)) (fr500 (unit u-check)) (fr550 (unit u-check))) ) ) (dni cckra "conditional check integer cc always" - ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) CONDITIONAL) + ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) + (FR400-MAJOR B-5) (FR450-MAJOR B-5) CONDITIONAL) "cckra$pack $CRj_int,$CCi,$cond" (+ pack ICC_ra CRj_int OP_6A (rs-null) CCi cond OPE4_0 (misc-null-9) (ICCi_3-null)) (if (eq CCi (or cond 2)) (check-semantics (const BI 1) CRj_int) (set CRj_int (cr-undefined))) - ((fr400 (unit u-check)) + ((fr400 (unit u-check)) (fr450 (unit u-check)) (fr500 (unit u-check)) (fr550 (unit u-check))) ) (dni cckno "conditional check integer cc never" - ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) CONDITIONAL) + ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) + (FR400-MAJOR B-5) (FR450-MAJOR B-5) CONDITIONAL) "cckno$pack $CRj_int,$CCi,$cond" (+ pack ICC_nev CRj_int OP_6A (rs-null) CCi cond OPE4_0 (misc-null-9) (ICCi_3-null)) (if (eq CCi (or cond 2)) (check-semantics (const BI 0) CRj_int) (set CRj_int (cr-undefined))) - ((fr400 (unit u-check)) + ((fr400 (unit u-check)) (fr450 (unit u-check)) (fr500 (unit u-check)) (fr550 (unit u-check))) ) @@ -6098,41 +6650,44 @@ (define-pmacro (conditional-check-float-condition-code prefix cc op ope test comment) (dni (.sym prefix cc) (comment) - ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) CONDITIONAL FR-ACCESS) + ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) + (FR400-MAJOR B-5) (FR450-MAJOR B-5) CONDITIONAL FR-ACCESS) (.str (.sym prefix cc) "$pack $FCCi_3,$CRj_float,$CCi,$cond") (+ pack (.sym FCC_ cc) CRj_float op (rs-null) CCi cond ope (misc-null-9) FCCi_3) (if (eq CCi (or cond 2)) (check-semantics (test FCCi_3) CRj_float) (set CRj_float (cr-undefined))) - ((fr400 (unit u-check)) + ((fr400 (unit u-check)) (fr450 (unit u-check)) (fr500 (unit u-check)) (fr550 (unit u-check))) ) ) (dni cfckra "conditional check float cc always" - ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) CONDITIONAL FR-ACCESS) + ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) + (FR400-MAJOR B-5) (FR450-MAJOR B-5) CONDITIONAL FR-ACCESS) "cfckra$pack $CRj_float,$CCi,$cond" (+ pack FCC_ra CRj_float OP_6A (rs-null) CCi cond OPE4_1 (misc-null-9) (FCCi_3-null)) (if (eq CCi (or cond 2)) (check-semantics (const BI 1) CRj_float) (set CRj_float (cr-undefined))) - ((fr400 (unit u-check)) + ((fr400 (unit u-check)) (fr450 (unit u-check)) (fr500 (unit u-check)) (fr550 (unit u-check))) ) (dni cfckno "conditional check float cc never" - ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) CONDITIONAL FR-ACCESS) + ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) + (FR400-MAJOR B-5) (FR450-MAJOR B-5) CONDITIONAL FR-ACCESS) "cfckno$pack $CRj_float,$CCi,$cond" (+ pack FCC_nev CRj_float OP_6A (rs-null) CCi cond OPE4_1 (misc-null-9) (FCCi_3-null)) (if (eq CCi (or cond 2)) (check-semantics (const BI 0) CRj_float) (set CRj_float (cr-undefined))) - ((fr400 (unit u-check)) + ((fr400 (unit u-check)) (fr450 (unit u-check)) (fr500 (unit u-check)) (fr550 (unit u-check))) ) @@ -6153,30 +6708,33 @@ (dni cjmpl "conditional jump and link" - ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) (FR400-MAJOR I-5) CONDITIONAL) + ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) + (FR400-MAJOR I-5) (FR450-MAJOR I-5) CONDITIONAL) "cjmpl$pack @($GRi,$GRj),$CCi,$cond" (+ pack (misc-null-1) (LI-off) OP_6A GRi CCi cond OPE4_2 GRj) (if (eq CCi (or cond 2)) (jump-and-link-semantics GRi GRj LI)) - ((fr400 (unit u-branch)) + ((fr400 (unit u-branch)) (fr450 (unit u-branch)) (fr500 (unit u-branch)) (fr550 (unit u-branch))) ) (dni ccalll "conditional call and link" - ((UNIT I0) (FR500-MAJOR I-5) (FR400-MAJOR I-5) CONDITIONAL) + ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) + (FR400-MAJOR I-5) (FR450-MAJOR I-5) CONDITIONAL) "ccalll$pack @($GRi,$GRj),$CCi,$cond" (+ pack (misc-null-1) (LI-on) OP_6A GRi CCi cond OPE4_2 GRj) (if (eq CCi (or cond 2)) (jump-and-link-semantics GRi GRj LI)) - ((fr400 (unit u-branch)) - (fr500 (unit u-branch))) + ((fr400 (unit u-branch)) (fr450 (unit u-branch)) + (fr500 (unit u-branch)) (fr550 (unit u-branch))) ) (define-pmacro (cache-invalidate name cache all op ope profile comment) (dni name (comment) - ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2)) + ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) + (FR400-MAJOR C-2) (FR450-MAJOR C-2)) (.str name "$pack @($GRi,$GRj)") (+ pack (rd-null) op GRi ope GRj) (c-call VOID (.str "@cpu@_" cache "_cache_invalidate") (add GRi GRj) all) @@ -6185,16 +6743,19 @@ ) (cache-invalidate ici insn 0 OP_03 OPE1_38 - ((fr400 (unit u-ici)) (fr500 (unit u-ici)) (fr550 (unit u-ici))) + ((fr400 (unit u-ici)) (fr450 (unit u-ici)) + (fr500 (unit u-ici)) (fr550 (unit u-ici))) "invalidate insn cache") (cache-invalidate dci data 0 OP_03 OPE1_3C - ((fr400 (unit u-dci)) (fr500 (unit u-dci)) (fr550 (unit u-dci))) + ((fr400 (unit u-dci)) (fr450 (unit u-dci)) + (fr500 (unit u-dci)) (fr550 (unit u-dci))) "invalidate data cache") (define-pmacro (cache-invalidate-entry name cache op ope profile comment) (dni name (comment) - ((UNIT C) (FR400-MAJOR C-2) (FR550-MAJOR C-2) (MACH fr400,fr550)) + ((UNIT C) (MACH fr400,fr450,fr550) (FR550-MAJOR C-2) + (FR400-MAJOR C-2) (FR450-MAJOR C-2)) (.str name "$pack @($GRi,$GRj),$ae") (+ pack (misc-null-1) ae op GRi ope GRj) (if (eq ae 0) @@ -6205,31 +6766,35 @@ ) (cache-invalidate-entry icei insn OP_03 OPE1_39 - ((fr400 (unit u-ici)) (fr550 (unit u-ici))) + ((fr400 (unit u-ici)) (fr450 (unit u-ici)) + (fr550 (unit u-ici))) "invalidate insn cache entry") (cache-invalidate-entry dcei data OP_03 OPE1_3A - ((fr400 (unit u-dci)) (fr550 (unit u-dci))) + ((fr400 (unit u-dci)) (fr450 (unit u-dci)) + (fr550 (unit u-dci))) "invalidate data cache entry") (dni dcf "Data cache flush" - ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2)) + ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) + (FR400-MAJOR C-2) (FR450-MAJOR C-2)) "dcf$pack @($GRi,$GRj)" (+ pack (rd-null) OP_03 GRi OPE1_3D GRj) (c-call VOID "@cpu@_data_cache_flush" (add GRi GRj) 0) - ((fr400 (unit u-dcf)) + ((fr400 (unit u-dcf)) (fr450 (unit u-dcf)) (fr500 (unit u-dcf)) (fr550 (unit u-dcf))) ) (dni dcef "Data cache entry flush" - ((UNIT C) (FR400-MAJOR C-2) (FR550-MAJOR C-2) (MACH fr400,fr550)) + ((UNIT C) (MACH fr400,fr450,fr550) (FR550-MAJOR C-2) + (FR400-MAJOR C-2) (FR450-MAJOR C-2)) "dcef$pack @($GRi,$GRj),$ae" (+ pack (misc-null-1) ae OP_03 GRi OPE1_3B GRj) (if (eq ae 0) (c-call VOID "@cpu@_data_cache_flush" (add GRi GRj) -1) (c-call VOID "@cpu@_data_cache_flush" (add GRi GRj) ae)) - ((fr400 (unit u-dcf)) (fr550 (unit u-dcf))) + ((fr400 (unit u-dcf)) (fr450 (unit u-dcf)) (fr550 (unit u-dcf))) ) (define-pmacro (write-TLB name insn op ope comment) @@ -6263,7 +6828,8 @@ (define-pmacro (cache-preload name cache pipe attrs op ope profile comment) (dni name (comment) - (.splice (UNIT pipe) (FR500-MAJOR C-2) (FR400-MAJOR C-2) (.unsplice attrs)) + (.splice (UNIT pipe) (FR500-MAJOR C-2) + (FR400-MAJOR C-2) (.unsplice attrs)) (.str name "$pack $GRi,$GRj,$lock") (+ pack (misc-null-1) lock op GRi ope GRj) (c-call VOID (.str "@cpu@_" cache "_cache_preload") GRi GRj lock) @@ -6271,17 +6837,20 @@ ) ) -(cache-preload icpl insn C ((FR550-MAJOR C-2)) OP_03 OPE1_30 - ((fr400 (unit u-icpl)) (fr500 (unit u-icpl)) (fr550 (unit u-icpl))) +(cache-preload icpl insn C ((FR550-MAJOR C-2) (FR450-MAJOR C-2)) OP_03 OPE1_30 + ((fr400 (unit u-icpl)) (fr450 (unit u-icpl)) + (fr500 (unit u-icpl)) (fr550 (unit u-icpl))) "preload insn cache") -(cache-preload dcpl data DCPL ((FR550-MAJOR I-8)) OP_03 OPE1_34 - ((fr400 (unit u-dcpl)) (fr500 (unit u-dcpl)) (fr550 (unit u-dcpl))) +(cache-preload dcpl data DCPL ((FR550-MAJOR I-8) (FR450-MAJOR I-2)) OP_03 OPE1_34 + ((fr400 (unit u-dcpl)) (fr450 (unit u-dcpl)) + (fr500 (unit u-dcpl)) (fr550 (unit u-dcpl))) "preload data cache") (define-pmacro (cache-unlock name cache op ope profile comment) (dni name (comment) - ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2)) + ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) + (FR400-MAJOR C-2) (FR450-MAJOR C-2)) (.str name "$pack $GRi") (+ pack (rd-null) op GRi ope (GRj-null)) (c-call VOID (.str "@cpu@_" cache "_cache_unlock") GRi) @@ -6290,16 +6859,19 @@ ) (cache-unlock icul insn OP_03 OPE1_31 - ((fr400 (unit u-icul)) (fr500 (unit u-icul)) (fr550 (unit u-icul))) + ((fr400 (unit u-icul)) (fr450 (unit u-icul)) + (fr500 (unit u-icul)) (fr550 (unit u-icul))) "unlock insn cache") (cache-unlock dcul data OP_03 OPE1_35 - ((fr400 (unit u-dcul)) (fr500 (unit u-dcul)) (fr550 (unit u-dcul))) + ((fr400 (unit u-dcul)) (fr450 (unit u-dcul)) + (fr500 (unit u-dcul)) (fr550 (unit u-dcul))) "unlock data cache") (define-pmacro (barrier name insn op ope profile comment) (dni name (comment) - ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2)) + ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) + (FR400-MAJOR C-2) (FR450-MAJOR C-2)) (.str insn "$pack") (+ pack (rd-null) op (rs-null) ope (GRj-null)) (nop) ; sufficient implementation @@ -6308,12 +6880,38 @@ ) (barrier bar bar OP_03 OPE1_3E - ((fr400 (unit u-barrier)) (fr500 (unit u-barrier))) + ((fr400 (unit u-barrier)) (fr450 (unit u-barrier)) + (fr500 (unit u-barrier))) "barrier") (barrier membar membar OP_03 OPE1_3F - ((fr400 (unit u-membar)) (fr500 (unit u-membar))) + ((fr400 (unit u-membar)) (fr450 (unit u-membar)) + (fr500 (unit u-membar))) "memory barrier") +; Load real address instructions +(define-pmacro (load-real-address name insn what op ope) + (dni name + (.str "Load real address of " what) + ((UNIT C) (FR450-MAJOR C-2) (MACH fr450)) + (.str insn "$pack $GRi,$GRk,$LRAE,$LRAD,$LRAS") + (+ pack GRk op GRi ope LRAE LRAD LRAS (LRA-null)) + (nop) ; not simulated + () + ) +) + +(load-real-address lrai "lrai" "instruction" OP_03 OPE1_20) +(load-real-address lrad "lrad" "data" OP_03 OPE1_21) + +(dni tlbpr + "TLB Probe" + ((UNIT C) (FR450-MAJOR C-2) (MACH fr450)) + "tlbpr$pack $GRi,$GRj,$TLBPRopx,$TLBPRL" + (+ pack (TLBPR-null) TLBPRopx TLBPRL OP_03 GRi OPE1_24 GRj) + (nop) ; not simulated + () +) + ; Coprocessor operations (define-pmacro (cop-op num op) (dni (.sym cop num) @@ -7115,25 +7713,30 @@ (dni mhsetlos "Media set lower signed 12 bits" - ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-5) (FR400-MAJOR M-1)) + ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-5) + (FR400-MAJOR M-1) (FR450-MAJOR M-1)) "mhsetlos$pack $u12,$FRklo" (+ pack FRklo OP_78 OPE1_20 u12) (set FRklo u12) - ((fr400 (unit u-media-hilo)) (fr550 (unit u-media-set (out FRintk FRklo)))) + ((fr400 (unit u-media-hilo)) (fr450 (unit u-media-hilo)) + (fr550 (unit u-media-set (out FRintk FRklo)))) ) (dni mhsethis "Media set upper signed 12 bits" - ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-5) (FR400-MAJOR M-1)) + ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-5) + (FR400-MAJOR M-1) (FR450-MAJOR M-1)) "mhsethis$pack $u12,$FRkhi" (+ pack FRkhi OP_78 OPE1_22 u12) (set FRkhi u12) - ((fr400 (unit u-media-hilo)) (fr550 (unit u-media-set (out FRintk FRkhi)))) + ((fr400 (unit u-media-hilo)) (fr450 (unit u-media-hilo)) + (fr550 (unit u-media-set (out FRintk FRkhi)))) ) (dni mhdsets "Media dual set halfword signed 12 bits" - ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-5) (FR400-MAJOR M-1)) + ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-5) + (FR400-MAJOR M-1) (FR450-MAJOR M-1)) "mhdsets$pack $u12,$FRintk" (+ pack FRintk OP_78 OPE1_24 u12) (sequence () @@ -7141,7 +7744,8 @@ (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) (set (halfword hi FRintk 0) u12) (set (halfword lo FRintk 0) u12)) - ((fr400 (unit u-media-1)) (fr550 (unit u-media-set))) + ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) + (fr550 (unit u-media-set))) ) (define-pmacro (set-5-semantics target value) @@ -7155,11 +7759,13 @@ (define-pmacro (media-set-5 name hilo op ope comment) (dni name (comment) - ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-5) (FR400-MAJOR M-1)) + ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-5) + (FR400-MAJOR M-1) (FR450-MAJOR M-1)) (.str name "$pack $s5,$FRk" hilo) (+ pack (.sym FRk hilo) op (FRi-null) ope (misc-null-11) s5) (set-5-semantics (.sym FRk hilo) s5) - ((fr400 (unit u-media-hilo)) (fr550 (unit u-media-set (out FRintk (.sym FRk hilo))))) + ((fr400 (unit u-media-hilo)) (fr450 (unit u-media-hilo)) + (fr550 (unit u-media-set (out FRintk (.sym FRk hilo))))) ) ) @@ -7168,7 +7774,8 @@ (dni mhdseth "Media dual set halfword upper 5 bits" - ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-5) (FR400-MAJOR M-1)) + ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-5) + (FR400-MAJOR M-1) (FR450-MAJOR M-1)) "mhdseth$pack $s5,$FRintk" (+ pack FRintk OP_78 (FRi-null) OPE1_25 (misc-null-11) s5) (sequence () @@ -7176,17 +7783,19 @@ (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) (set-5-semantics (halfword hi FRintk 0) s5) (set-5-semantics (halfword lo FRintk 0) s5)) - ((fr400 (unit u-media-1)) (fr550 (unit u-media-set))) + ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) + (fr550 (unit u-media-set))) ) (define-pmacro (media-logic-r-r name operation op ope comment) (dni name (comment) - ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1)) + ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) + (FR400-MAJOR M-1) (FR450-MAJOR M-1)) (.str name "$pack $FRinti,$FRintj,$FRintk") (+ pack FRintk op FRinti ope FRintj) (set FRintk (operation FRinti FRintj)) - ((fr400 (unit u-media-1)) + ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) (fr500 (unit u-media)) (fr550 (unit u-media))) ) ) @@ -7198,12 +7807,13 @@ (define-pmacro (conditional-media-logic name operation op ope comment) (dni name (comment) - ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1) CONDITIONAL) + ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) + (FR400-MAJOR M-1) (FR450-MAJOR M-1) CONDITIONAL) (.str name "$pack $FRinti,$FRintj,$FRintk,$CCi,$cond") (+ pack FRintk op FRinti CCi cond ope FRintj) (if (eq CCi (or cond 2)) (set FRintk (operation FRinti FRintj))) - ((fr400 (unit u-media-1)) + ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) (fr500 (unit u-media)) (fr550 (unit u-media))) ) ) @@ -7214,33 +7824,36 @@ (dni mnot ("mnot") - ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1)) + ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) + (FR400-MAJOR M-1) (FR450-MAJOR M-1)) ("mnot$pack $FRintj,$FRintk") (+ pack FRintk OP_7B (rs-null) OPE1_03 FRintj) (set FRintk (inv FRintj)) - ((fr400 (unit u-media-1)) + ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) (fr500 (unit u-media)) (fr550 (unit u-media))) ) (dni cmnot ("cmnot") - ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1) CONDITIONAL) + ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) + (FR400-MAJOR M-1) (FR450-MAJOR M-1) CONDITIONAL) ("cmnot$pack $FRintj,$FRintk,$CCi,$cond") (+ pack FRintk OP_70 (rs-null) CCi cond OPE4_3 FRintj) (if (eq CCi (or cond 2)) (set FRintk (inv FRintj))) - ((fr400 (unit u-media-1)) + ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) (fr500 (unit u-media)) (fr550 (unit u-media))) ) (define-pmacro (media-rotate-r-r name operation op ope comment) (dni name (comment) - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1)) + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) + (FR400-MAJOR M-1) (FR450-MAJOR M-1)) (.str name "$pack $FRinti,$u6,$FRintk") (+ pack FRintk op FRinti ope u6) (set FRintk (operation FRinti (and u6 #x1f))) - ((fr400 (unit u-media-3)) + ((fr400 (unit u-media-3)) (fr450 (unit u-media-3)) (fr500 (unit u-media)) (fr550 (unit u-media))) ) ) @@ -7251,11 +7864,12 @@ (define-pmacro (media-cut-r-r name arg op ope comment) (dni name (comment) - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-2)) + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) + (FR400-MAJOR M-2) (FR450-MAJOR M-2)) (.str name "$pack $FRinti,$" arg ",$FRintk") (+ pack FRintk op FRinti ope arg) (set FRintk (c-call SI "@cpu@_cut" FRinti (nextreg h-fr_int FRinti 1) arg)) - ((fr400 (unit u-media-3)) + ((fr400 (unit u-media-3)) (fr450 (unit u-media-3)) (fr500 (unit u-media)) (fr550 (unit u-media))) ) ) @@ -7263,35 +7877,37 @@ (media-cut-r-r mwcut FRintj OP_7B OPE1_06 "media cut") (media-cut-r-r mwcuti u6 OP_7B OPE1_07 "media cut") -(define-pmacro (media-cut-acc name arg op ope comment) +(define-pmacro (media-cut-acc name arg op ope fr450-major comment) (dni name (comment) - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1)) + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) + (FR400-MAJOR M-1) (FR450-MAJOR fr450-major)) (.str name "$pack $ACC40Si,$" arg ",$FRintk") (+ pack FRintk op ACC40Si ope arg) (set FRintk (c-call SI "@cpu@_media_cut" ACC40Si arg)) - ((fr400 (unit u-media-4)) + ((fr400 (unit u-media-4)) (fr450 (unit u-media-4)) (fr500 (unit u-media)) (fr550 (unit u-media-3-acc))) ) ) -(media-cut-acc mcut FRintj OP_7B OPE1_2C "media accumulator cut reg") -(media-cut-acc mcuti s6 OP_7B OPE1_2E "media accumulator cut immed") +(media-cut-acc mcut FRintj OP_7B OPE1_2C M-1 "media accumulator cut reg") +(media-cut-acc mcuti s6 OP_7B OPE1_2E M-5 "media accumulator cut immed") -(define-pmacro (media-cut-acc-ss name arg op ope comment) +(define-pmacro (media-cut-acc-ss name arg op ope fr450-major comment) (dni name (comment) - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1)) + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) + (FR400-MAJOR M-1) (FR450-MAJOR fr450-major)) (.str name "$pack $ACC40Si,$" arg ",$FRintk") (+ pack FRintk op ACC40Si ope arg) (set FRintk (c-call SI "@cpu@_media_cut_ss" ACC40Si arg)) - ((fr400 (unit u-media-4)) + ((fr400 (unit u-media-4)) (fr450 (unit u-media-4)) (fr500 (unit u-media)) (fr550 (unit u-media-3-acc))) ) ) -(media-cut-acc-ss mcutss FRintj OP_7B OPE1_2D "media accumulator cut reg with saturation") -(media-cut-acc-ss mcutssi s6 OP_7B OPE1_2F "media accumulator cut immed with saturation") +(media-cut-acc-ss mcutss FRintj OP_7B OPE1_2D M-1 "media accumulator cut reg with saturation") +(media-cut-acc-ss mcutssi s6 OP_7B OPE1_2F M-5 "media accumulator cut immed with saturation") ; Dual Media Instructions ; @@ -7301,7 +7917,8 @@ (dni mdcutssi "Media dual cut with signed saturation" - ((UNIT FMLOW) (MACH fr400,fr550) (FR550-MAJOR M-3) (FR400-MAJOR M-2)) + ((UNIT MDCUTSSI) (MACH fr400,fr450,fr550) (FR550-MAJOR M-3) + (FR400-MAJOR M-2) (FR450-MAJOR M-6)) "mdcutssi$pack $ACC40Si,$s6,$FRintkeven" (+ pack FRintkeven OP_78 ACC40Si OPE1_0E s6) (if (register-unaligned ACC40Si 2) @@ -7314,7 +7931,10 @@ (c-call SI "@cpu@_media_cut_ss" (nextreg h-acc40S ACC40Si 1) s6))))) ((fr400 (unit u-media-4-acc-dual - (out FRintk FRintkeven))) (fr550 (unit u-media-3-acc-dual))) + (out FRintk FRintkeven))) + (fr450 (unit u-media-4-acc-dual + (out FRintk FRintkeven))) + (fr550 (unit u-media-3-acc-dual))) ) ; The (add (xxxx) (mul arg 0)) is a hack to get a reference to arg generated @@ -7329,18 +7949,20 @@ (dni maveh "Media dual average" - ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1)) + ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) + (FR400-MAJOR M-1) (FR450-MAJOR M-1)) "maveh$pack $FRinti,$FRintj,$FRintk" (+ pack FRintk OP_7B FRinti OPE1_08 FRintj) (set FRintk (c-call SI "@cpu@_media_average" FRinti FRintj)) - ((fr400 (unit u-media-1)) + ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) (fr500 (unit u-media)) (fr550 (unit u-media))) ) (define-pmacro (media-dual-shift name operation op ope profile comment) (dni name (comment) - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1)) + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) + (FR400-MAJOR M-1) (FR450-MAJOR M-1)) (.str name "$pack $FRinti,$u6,$FRintk") (+ pack FRintk op FRinti ope u6) (sequence () @@ -7356,19 +7978,23 @@ ) (media-dual-shift msllhi sll OP_7B OPE1_09 - ((fr400 (unit u-media-3)) (fr500 (unit u-media)) (fr550 (unit u-media))) + ((fr400 (unit u-media-3)) (fr450 (unit u-media-3)) + (fr500 (unit u-media)) (fr550 (unit u-media))) "Media dual shift left logical") (media-dual-shift msrlhi srl OP_7B OPE1_0A - ((fr400 (unit u-media-3)) (fr500 (unit u-media)) (fr550 (unit u-media))) + ((fr400 (unit u-media-3)) (fr450 (unit u-media-3)) + (fr500 (unit u-media)) (fr550 (unit u-media))) "Media dual shift right logical") (media-dual-shift msrahi sra OP_7B OPE1_0B - ((fr400 (unit u-media-6)) (fr500 (unit u-media)) (fr550 (unit u-media))) + ((fr400 (unit u-media-6)) (fr450 (unit u-media-6)) + (fr500 (unit u-media)) (fr550 (unit u-media))) "Media dual shift right arithmetic") (define-pmacro (media-dual-word-rotate-r-r name operation op ope comment) (dni name (comment) - ((UNIT FMLOW) (MACH fr400,fr550) (FR550-MAJOR M-3) (FR400-MAJOR M-2)) + ((UNIT FMLOW) (MACH fr400,fr450,fr550) (FR550-MAJOR M-3) + (FR400-MAJOR M-2) (FR450-MAJOR M-2)) (.str name "$pack $FRintieven,$s6,$FRintkeven") (+ pack FRintkeven op FRintieven ope s6) (if (orif (register-unaligned FRintieven 2) @@ -7381,7 +8007,11 @@ (and s6 #x1f))))) ((fr400 (unit u-media-3-quad (in FRinti FRintieven) - (out FRintk FRintkeven))) (fr550 (unit u-media-quad))) + (out FRintk FRintkeven))) + (fr450 (unit u-media-3-quad + (in FRinti FRintieven) + (out FRintk FRintkeven))) + (fr550 (unit u-media-quad))) ) ) @@ -7389,7 +8019,8 @@ (dni mcplhi "Media bit concatenate, halfword" - ((UNIT FMLOW) (MACH fr400,fr550) (FR550-MAJOR M-3) (FR400-MAJOR M-2)) + ((UNIT FMLOW) (MACH fr400,fr450,fr550) (FR550-MAJOR M-3) + (FR400-MAJOR M-2) (FR450-MAJOR M-2)) "mcplhi$pack $FRinti,$u6,$FRintk" (+ pack FRintk OP_78 FRinti OPE1_0C u6) (sequence ((HI arg1) (HI arg2) (HI shift)) @@ -7404,12 +8035,14 @@ (sub 15 shift))) (set arg1 (or HI arg1 arg2)))) (set (halfword hi FRintk 0) arg1)) - ((fr400 (unit u-media-3-dual)) (fr550 (unit u-media-3-dual))) + ((fr400 (unit u-media-3-dual)) (fr450 (unit u-media-3-dual)) + (fr550 (unit u-media-3-dual))) ) (dni mcpli "Media bit concatenate, word" - ((UNIT FMLOW) (MACH fr400,fr550) (FR550-MAJOR M-3) (FR400-MAJOR M-2)) + ((UNIT FMLOW) (MACH fr400,fr450,fr550) (FR550-MAJOR M-3) + (FR400-MAJOR M-2) (FR450-MAJOR M-2)) "mcpli$pack $FRinti,$u6,$FRintk" (+ pack FRintk OP_78 FRinti OPE1_0D u6) (sequence ((SI tmp) (SI shift)) @@ -7422,7 +8055,8 @@ (sub 31 shift))) (set tmp (or tmp tmp1)))) (set FRintk tmp)) - ((fr400 (unit u-media-3-dual)) (fr550 (unit u-media-3-dual))) + ((fr400 (unit u-media-3-dual)) (fr450 (unit u-media-3-dual)) + (fr550 (unit u-media-3-dual))) ) (define-pmacro (saturate arg max min result) @@ -7435,20 +8069,22 @@ (dni msaths "Media dual saturation signed" - ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1)) + ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) + (FR400-MAJOR M-1) (FR450-MAJOR M-1)) "msaths$pack $FRinti,$FRintj,$FRintk" (+ pack FRintk OP_7B FRinti OPE1_0C FRintj) (sequence ((HI argihi) (HI argilo) (HI argjhi) (HI argjlo)) (extract-hilo FRinti 0 FRintj 0 argihi argilo argjhi argjlo) (saturate argihi argjhi (inv argjhi) (halfword hi FRintk 0)) (saturate argilo argjlo (inv argjlo) (halfword lo FRintk 0))) - ((fr400 (unit u-media-1)) + ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) (fr500 (unit u-media)) (fr550 (unit u-media))) ) (dni mqsaths "Media quad saturation signed" - ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-2) (FR400-MAJOR M-1)) + ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-2) + (FR400-MAJOR M-2) (FR450-MAJOR M-2)) "mqsaths$pack $FRintieven,$FRintjeven,$FRintkeven" (+ pack FRintkeven OP_78 FRintieven OPE1_0F FRintjeven) (if (orif (register-unaligned FRintieven 2) @@ -7467,7 +8103,12 @@ ((fr400 (unit u-media-1-quad (in FRinti FRintieven) (in FRintj FRintjeven) - (out FRintk FRintkeven))) (fr550 (unit u-media-quad))) + (out FRintk FRintkeven))) + (fr450 (unit u-media-1-quad + (in FRinti FRintieven) + (in FRintj FRintjeven) + (out FRintk FRintkeven))) + (fr550 (unit u-media-quad))) ) (define-pmacro (saturate-unsigned arg max result) @@ -7478,21 +8119,23 @@ (dni msathu "Media dual saturation unsigned" - ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1)) + ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) + (FR400-MAJOR M-1) (FR450-MAJOR M-1)) "msathu$pack $FRinti,$FRintj,$FRintk" (+ pack FRintk OP_7B FRinti OPE1_0D FRintj) (sequence ((UHI argihi) (UHI argilo) (UHI argjhi) (UHI argjlo)) (extract-hilo FRinti 0 FRintj 0 argihi argilo argjhi argjlo) (saturate-unsigned argihi argjhi (halfword hi FRintk 0)) (saturate-unsigned argilo argjlo (halfword lo FRintk 0))) - ((fr400 (unit u-media-1)) + ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) (fr500 (unit u-media)) (fr550 (unit u-media))) ) (define-pmacro (media-dual-compare name mode op ope comment) (dni name (comment) - ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1)) + ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) + (FR400-MAJOR M-1) (FR450-MAJOR M-1)) (.str name "$pack $FRinti,$FRintj,$FCCk") (+ pack (cond-null) FCCk op FRinti ope FRintj) (if (register-unaligned FCCk 2) @@ -7503,7 +8146,7 @@ (compare-and-set-fcc argihi argjhi FCCk) (compare-and-set-fcc argilo argjlo (nextreg h-fccr FCCk 1)))) ; TODO - doesn't handle second FCC - ((fr400 (unit u-media-7)) + ((fr400 (unit u-media-7)) (fr450 (unit u-media-7)) (fr500 (unit u-media)) (fr550 (unit u-media))) ) ) @@ -7536,7 +8179,8 @@ (dni mabshs "Media dual absolute value, halfword" - ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-2) (FR400-MAJOR M-1)) + ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-2) + (FR400-MAJOR M-1) (FR450-MAJOR M-1)) "mabshs$pack $FRintj,$FRintk" (+ pack FRintk OP_78 (FRi-null) OPE1_0A FRintj) (sequence ((HI arghi) (HI arglo)) @@ -7548,7 +8192,8 @@ (halfword hi FRintk 0)) (saturate-v (abs arglo) 32767 -32768 (msr-sie-fri-lo) (halfword lo FRintk 0))) - ((fr400 (unit u-media-1)) (fr550 (unit u-media))) + ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) + (fr550 (unit u-media))) ) (define-pmacro (media-arith-sat-semantics @@ -7572,11 +8217,12 @@ (define-pmacro (media-dual-arith-sat name operation mode max min op ope comment) (dni name (comment) - ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1)) + ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) + (FR400-MAJOR M-1) (FR450-MAJOR M-1)) (.str name "$pack $FRinti,$FRintj,$FRintk") (+ pack FRintk op FRinti ope FRintj) (media-dual-arith-sat-semantics operation mode max min) - ((fr400 (unit u-media-1)) + ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) (fr500 (unit u-media)) (fr550 (unit u-media))) ) ) @@ -7591,12 +8237,13 @@ name operation mode max min op ope comment) (dni name (comment) - ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1) CONDITIONAL) + ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) + (FR400-MAJOR M-1) (FR450-MAJOR M-1) CONDITIONAL) (.str name "$pack $FRinti,$FRintj,$FRintk,$CCi,$cond") (+ pack FRintk op FRinti CCi cond ope FRintj) (if (eq CCi (or cond 2)) (media-dual-arith-sat-semantics operation mode max min)) - ((fr400 (unit u-media-1)) + ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) (fr500 (unit u-media)) (fr550 (unit u-media))) ) ) @@ -7637,7 +8284,8 @@ (define-pmacro (media-quad-arith-sat name operation mode max min op ope comment) (dni name (comment) - ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-2)) + ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) + (FR400-MAJOR M-2) (FR450-MAJOR M-2)) (.str name "$pack $FRintieven,$FRintjeven,$FRintkeven") (+ pack FRintkeven op FRintieven ope FRintjeven) (media-quad-arith-sat-semantics 1 operation mode max min) @@ -7645,6 +8293,10 @@ (in FRinti FRintieven) (in FRintj FRintjeven) (out FRintk FRintkeven))) + (fr450 (unit u-media-1-quad + (in FRinti FRintieven) + (in FRintj FRintjeven) + (out FRintk FRintkeven))) (fr500 (unit u-media-quad-arith (in FRinti FRintieven) (in FRintj FRintjeven) @@ -7662,7 +8314,8 @@ name operation mode max min op ope comment) (dni name (comment) - ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-2) CONDITIONAL) + ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) + (FR400-MAJOR M-2) (FR450-MAJOR M-2) CONDITIONAL) (.str name "$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond") (+ pack FRintkeven op FRintieven CCi cond ope FRintjeven) (media-quad-arith-sat-semantics (eq CCi (or cond 2)) @@ -7671,6 +8324,10 @@ (in FRinti FRintieven) (in FRintj FRintjeven) (out FRintk FRintkeven))) + (fr450 (unit u-media-1-quad + (in FRinti FRintieven) + (in FRintj FRintjeven) + (out FRintk FRintkeven))) (fr500 (unit u-media-quad-arith (in FRinti FRintieven) (in FRintj FRintjeven) @@ -7684,10 +8341,98 @@ (conditional-media-quad-arith-sat cmqsubhss sub HI 32767 -32768 OP_73 OPE4_2 "Conditional Media quad sub signed with saturation") (conditional-media-quad-arith-sat cmqsubhus sub UHI 65535 0 OP_73 OPE4_3 "Conditional Media quad sub unsigned with saturation") +;; Return A if |A| > |B| and B is positive. Return -A if |A| > |B| and +;; B is negative, saturating 0x8000 as 0x7fff. Return 0 otherwise. +(define-pmacro (media-low-clear-semantics a b) + (cond HI + ((le UHI (abs a) (abs b)) 0) + ((le HI 0 b) a) + ((eq HI a -32768) 32767) + (else (neg a)))) + +;; Return A if -|B| < A < |B|. Return -B if A <= -|B|, saturating 0x8000 +;; as 0x7fff. Return B if A >= |B|. +(define-pmacro (media-scope-limit-semantics a b) + (cond HI + ((andif (gt HI b -32768) + (ge HI a (abs b))) b) + ((gt HI a (neg (abs b))) a) + ((eq HI b -32768) 32767) + (else (neg b)))) + +(define-pmacro (media-quad-limit name operation op ope comment) + (dni name + comment + ((UNIT FM0) (MACH fr450) (FR450-MAJOR M-2)) + (.str name "$pack $FRintieven,$FRintjeven,$FRintkeven") + (+ pack FRintkeven op FRintieven ope FRintjeven) + (if (orif (register-unaligned FRintieven 2) + (orif (register-unaligned FRintjeven 2) + (register-unaligned FRintkeven 2))) + (c-call VOID "@cpu@_media_register_not_aligned") + (sequence ((HI a1) (HI a2) (HI a3) (HI a4) + (HI b1) (HI b2) (HI b3) (HI b4)) + ; hack to get FRintkeven referenced as a target + ; for profiling + (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) + (extract-hilo FRintieven 0 FRintjeven 0 a1 a2 b1 b2) + (extract-hilo FRintieven 1 FRintjeven 1 a3 a4 b3 b4) + (set (halfword hi FRintkeven 0) (operation a1 b1)) + (set (halfword lo FRintkeven 0) (operation a2 b2)) + (set (halfword hi FRintkeven 1) (operation a3 b3)) + (set (halfword lo FRintkeven 1) (operation a4 b4)))) + ((fr450 (unit u-media-1-quad + (in FRinti FRintieven) + (in FRintj FRintjeven) + (out FRintk FRintkeven)))) + ) +) + +(media-quad-limit mqlclrhs media-low-clear-semantics OP_78 OPE1_10 + "Media quad low clear") +(media-quad-limit mqlmths media-scope-limit-semantics OP_78 OPE1_14 + "Media quad scope limitation") + +(define-pmacro (media-quad-shift name operation op ope comment) + (dni name + (comment) + ((UNIT FM0) (MACH fr450) (FR450-MAJOR M-2)) + (.str name "$pack $FRintieven,$u6,$FRintkeven") + (+ pack FRintkeven op FRintieven ope u6) + (if (orif (register-unaligned FRintieven 2) + (register-unaligned FRintkeven 2)) + (c-call VOID "@cpu@_media_register_not_aligned") + (sequence () + ; hack to get these referenced for profiling + (set FRintieven (c-raw-call SI "frv_ref_SI" FRintieven)) + (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) + (set (halfword hi FRintkeven 0) + (operation HI (halfword hi FRintieven 0) + (and u6 #xf))) + (set (halfword lo FRintkeven 0) + (operation HI (halfword lo FRintieven 0) + (and u6 #xf))) + (set (halfword hi FRintkeven 1) + (operation HI (halfword hi FRintieven 1) + (and u6 #xf))) + (set (halfword lo FRintkeven 1) + (operation HI (halfword lo FRintieven 1) + (and u6 #xf))))) + ((fr450 (unit u-media-3-quad + (in FRinti FRintieven) + (in FRintj FRintieven) + (out FRintk FRintkeven)))) + ) +) + +(media-quad-shift mqsllhi sll OP_78 OPE1_11 "Media quad left shift") +(media-quad-shift mqsrahi sra OP_78 OPE1_13 "Media quad right shift") + (define-pmacro (media-acc-arith-sat name operation mode max min op ope comment) (dni name (comment) - ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-1)) + ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4) + (FR400-MAJOR M-1) (FR450-MAJOR M-3)) (.str name "$pack $ACC40Si,$ACC40Sk") (+ pack ACC40Sk op ACC40Si ope (ACCj-null)) (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Si)) @@ -7697,7 +8442,8 @@ (media-arith-sat-semantics operation ACC40Si (nextreg h-acc40S ACC40Si 1) ACC40Sk mode max min (msr-sie-acci))))) - ((fr400 (unit u-media-2-acc)) (fr550 (unit u-media-4-acc))) + ((fr400 (unit u-media-2-acc)) (fr450 (unit u-media-2-acc)) + (fr550 (unit u-media-4-acc))) ) ) @@ -7710,7 +8456,8 @@ comment) (dni name (comment) - ((UNIT MDUALACC) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-2)) + ((UNIT MDUALACC) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4) + (FR400-MAJOR M-2) (FR450-MAJOR M-4)) (.str name "$pack $ACC40Si,$ACC40Sk") (+ pack ACC40Sk op ACC40Si ope (ACCj-null)) (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Si)) @@ -7730,7 +8477,8 @@ (nextreg h-acc40S ACC40Sk 1) mode max min (msr-sie-acci-1))))))) - ((fr400 (unit u-media-2-acc-dual)) (fr550 (unit u-media-4-acc-dual))) + ((fr400 (unit u-media-2-acc-dual)) (fr450 (unit u-media-2-acc-dual)) + (fr550 (unit u-media-4-acc-dual))) ) ) @@ -7741,7 +8489,8 @@ (dni masaccs "Media add and subtract signed accumulator with saturation" - ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-1)) + ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4) + (FR400-MAJOR M-1) (FR450-MAJOR M-3)) "masaccs$pack $ACC40Si,$ACC40Sk" (+ pack ACC40Sk OP_78 ACC40Si OPE1_08 (ACCj-null)) (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Si)) @@ -7764,12 +8513,14 @@ #x7fffffffff (inv DI #x7fffffffff) (msr-sie-acci-1))))))) - ((fr400 (unit u-media-2-add-sub)) (fr550 (unit u-media-4-add-sub))) + ((fr400 (unit u-media-2-add-sub)) (fr450 (unit u-media-2-add-sub)) + (fr550 (unit u-media-4-add-sub))) ) (dni mdasaccs "Media add and subtract signed accumulator with saturation" - ((UNIT MDUALACC) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-2)) + ((UNIT MDUALACC) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4) + (FR400-MAJOR M-2) (FR450-MAJOR M-4)) "mdasaccs$pack $ACC40Si,$ACC40Sk" (+ pack ACC40Sk OP_78 ACC40Si OPE1_09 (ACCj-null)) (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Si)) @@ -7808,7 +8559,9 @@ #x7fffffffff (inv DI #x7fffffffff) (msr-sie-acci-3))))))) - ((fr400 (unit u-media-2-add-sub-dual)) (fr550 (unit u-media-4-add-sub-dual))) + ((fr400 (unit u-media-2-add-sub-dual)) + (fr450 (unit u-media-2-add-sub-dual)) + (fr550 (unit u-media-4-add-sub-dual))) ) (define-pmacro (media-multiply-semantics conv arg1 arg2 res) @@ -7831,11 +8584,12 @@ (define-pmacro (media-dual-multiply name mode conv rhs1 rhs2 op ope comment) (dni name (comment) - ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-1) PRESERVE-OVF) + ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) + (FR400-MAJOR M-1) (FR450-MAJOR M-3) PRESERVE-OVF) (.str name "$pack $FRinti,$FRintj,$ACC40Sk") (+ pack ACC40Sk op FRinti ope FRintj) (media-dual-multiply-semantics 1 mode conv rhs1 rhs2) - ((fr400 (unit u-media-2)) + ((fr400 (unit u-media-2)) (fr450 (unit u-media-2)) (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) ) ) @@ -7850,12 +8604,13 @@ name mode conv rhs1 rhs2 op ope comment) (dni name (comment) - ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-1) + ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) + (FR400-MAJOR M-1) (FR450-MAJOR M-3) PRESERVE-OVF CONDITIONAL) (.str name "$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond") (+ pack ACC40Sk op FRinti CCi cond ope FRintj) (media-dual-multiply-semantics (eq CCi (or cond 2)) mode conv rhs1 rhs2) - ((fr400 (unit u-media-2)) + ((fr400 (unit u-media-2)) (fr450 (unit u-media-2)) (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) ) ) @@ -7889,13 +8644,17 @@ (define-pmacro (media-quad-multiply name mode conv rhs1 rhs2 op ope comment) (dni name (comment) - ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-2) PRESERVE-OVF) + ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) + (FR400-MAJOR M-2) (FR450-MAJOR M-4) PRESERVE-OVF) (.str name "$pack $FRintieven,$FRintjeven,$ACC40Sk") (+ pack ACC40Sk op FRintieven ope FRintjeven) (media-quad-multiply-semantics 1 mode conv rhs1 rhs2) ((fr400 (unit u-media-2-quad (in FRinti FRintieven) (in FRintj FRintjeven))) + (fr450 (unit u-media-2-quad + (in FRinti FRintieven) + (in FRintj FRintjeven))) (fr500 (unit u-media-quad-mul (in FRinti FRintieven) (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) @@ -7912,7 +8671,8 @@ name mode conv rhs1 rhs2 op ope comment) (dni name (comment) - ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-2) + ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) + (FR400-MAJOR M-2) (FR450-MAJOR M-4) PRESERVE-OVF CONDITIONAL) (.str name "$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond") (+ pack ACC40Sk op FRintieven CCi cond ope FRintjeven) @@ -7920,6 +8680,9 @@ ((fr400 (unit u-media-2-quad (in FRinti FRintieven) (in FRintj FRintjeven))) + (fr450 (unit u-media-2-quad + (in FRinti FRintieven) + (in FRintj FRintjeven))) (fr500 (unit u-media-quad-mul (in FRinti FRintieven) (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) @@ -7957,11 +8720,12 @@ name mode conv addop rhw res max min op ope comment) (dni name (comment) - ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-1)) + ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) + (FR400-MAJOR M-1) (FR450-MAJOR M-3)) (.str name "$pack $FRinti,$FRintj,$" res) (+ pack res op FRinti ope FRintj) (media-dual-multiply-acc-semantics 1 mode conv addop rhw res max min) - ((fr400 (unit u-media-2)) + ((fr400 (unit u-media-2)) (fr450 (unit u-media-2)) (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) ) ) @@ -7990,12 +8754,13 @@ name mode conv addop rhw res max min op ope comment) (dni name (comment) - ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-1) CONDITIONAL) + ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) + (FR400-MAJOR M-1) (FR450-MAJOR M-3) CONDITIONAL) (.str name "$pack $FRinti,$FRintj,$" res ",$CCi,$cond") (+ pack res op FRinti CCi cond ope FRintj) (media-dual-multiply-acc-semantics (eq CCi (or cond 2)) mode conv addop rhw res max min) - ((fr400 (unit u-media-2)) + ((fr400 (unit u-media-2)) (fr450 (unit u-media-2)) (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) ) ) @@ -8044,13 +8809,17 @@ name mode conv addop rhw res max min op ope comment) (dni name (comment) - ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-2)) + ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) + (FR400-MAJOR M-2) (FR450-MAJOR M-4)) (.str name "$pack $FRintieven,$FRintjeven,$" res) (+ pack res op FRintieven ope FRintjeven) (media-quad-multiply-acc-semantics 1 mode conv addop rhw res max min) ((fr400 (unit u-media-2-quad (in FRinti FRintieven) (in FRintj FRintjeven))) + (fr450 (unit u-media-2-quad + (in FRinti FRintieven) + (in FRintj FRintjeven))) (fr500 (unit u-media-quad-mul (in FRinti FRintieven) (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) @@ -8071,7 +8840,8 @@ name mode conv addop rhw res max min op ope comment) (dni name (comment) - ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-2) CONDITIONAL) + ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) + (FR400-MAJOR M-2) (FR450-MAJOR M-4) CONDITIONAL) (.str name "$pack $FRintieven,$FRintjeven,$" res ",$CCi,$cond") (+ pack res op FRintieven CCi cond ope FRintjeven) (media-quad-multiply-acc-semantics (eq CCi (or cond 2)) @@ -8079,6 +8849,9 @@ ((fr400 (unit u-media-2-quad (in FRinti FRintieven) (in FRintj FRintjeven))) + (fr450 (unit u-media-2-quad + (in FRinti FRintieven) + (in FRintj FRintjeven))) (fr500 (unit u-media-quad-mul (in FRinti FRintieven) (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) @@ -8129,14 +8902,19 @@ name mode conv addop rhw res max min op ope comment) (dni name (comment) - ((UNIT MDUALACC) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-2)) + ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4) + (FR400-MAJOR M-2) (FR450-MAJOR M-4)) (.str name "$pack $FRintieven,$FRintjeven,$" res) (+ pack res op FRintieven ope FRintjeven) (media-quad-multiply-cross-acc-semantics 1 mode conv addop rhw res max min) ((fr400 (unit u-media-2-quad (in FRinti FRintieven) - (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) + (in FRintj FRintjeven))) + (fr450 (unit u-media-2-quad + (in FRinti FRintieven) + (in FRintj FRintjeven))) + (fr550 (unit u-media-4-quad))) ) ) @@ -8179,14 +8957,19 @@ name mode conv addop rhw res max min op ope comment) (dni name (comment) - ((UNIT MDUALACC) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-2)) + ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4) + (FR400-MAJOR M-2) (FR450-MAJOR M-4)) (.str name "$pack $FRintieven,$FRintjeven,$" res) (+ pack res op FRintieven ope FRintjeven) (media-quad-cross-multiply-cross-acc-semantics 1 mode conv addop rhw res max min) ((fr400 (unit u-media-2-quad (in FRinti FRintieven) - (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) + (in FRintj FRintjeven))) + (fr450 (unit u-media-2-quad + (in FRinti FRintieven) + (in FRintj FRintjeven))) + (fr550 (unit u-media-4-quad))) ) ) @@ -8229,14 +9012,19 @@ name mode conv addop rhw res max min op ope comment) (dni name (comment) - ((UNIT MDUALACC) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-2)) + ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4) + (FR400-MAJOR M-2) (FR450-MAJOR M-4)) (.str name "$pack $FRintieven,$FRintjeven,$" res) (+ pack res op FRintieven ope FRintjeven) (media-quad-cross-multiply-acc-semantics 1 mode conv addop rhw res max min) ((fr400 (unit u-media-2-quad (in FRinti FRintieven) - (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) + (in FRintj FRintjeven))) + (fr450 (unit u-media-2-quad + (in FRinti FRintieven) + (in FRintj FRintjeven))) + (fr550 (unit u-media-4-quad))) ) ) @@ -8283,11 +9071,12 @@ name mode conv rhs1 rhs2 max min op ope comment) (dni name (comment) - ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-1)) + ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) + (FR400-MAJOR M-1) (FR450-MAJOR M-3)) (.str name "$pack $FRinti,$FRintj,$ACC40Sk") (+ pack ACC40Sk op FRinti ope FRintj) (media-dual-complex-semantics mode conv rhs1 rhs2 max min) - ((fr400 (unit u-media-2)) + ((fr400 (unit u-media-2)) (fr450 (unit u-media-2)) (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) ) ) @@ -8296,11 +9085,12 @@ name mode conv rhs1 rhs2 max min op ope comment) (dni name (comment) - ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-1)) + ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) + (FR400-MAJOR M-1) (FR450-MAJOR M-3)) (.str name "$pack $FRinti,$FRintj,$ACC40Sk") (+ pack ACC40Sk op FRinti ope FRintj) (media-dual-complex-semantics-i mode conv rhs1 rhs2 max min) - ((fr400 (unit u-media-2)) + ((fr400 (unit u-media-2)) (fr450 (unit u-media-2)) (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) ) ) @@ -8329,12 +9119,13 @@ name mode conv rhs1 rhs2 max min op ope comment) (dni name (comment) - ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-1) CONDITIONAL) + ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) + (FR400-MAJOR M-1) (FR450-MAJOR M-3) CONDITIONAL) (.str name "$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond") (+ pack ACC40Sk op FRinti CCi cond ope FRintj) (if (eq CCi (or cond 2)) (media-dual-complex-semantics mode conv rhs1 rhs2 max min)) - ((fr400 (unit u-media-2)) + ((fr400 (unit u-media-2)) (fr450 (unit u-media-2)) (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) ) ) @@ -8343,12 +9134,13 @@ name mode conv rhs1 rhs2 max min op ope comment) (dni name (comment) - ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-1) CONDITIONAL) + ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) + (FR400-MAJOR M-1) (FR450-MAJOR M-3) CONDITIONAL) (.str name "$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond") (+ pack ACC40Sk op FRinti CCi cond ope FRintj) (if (eq CCi (or cond 2)) (media-dual-complex-semantics-i mode conv rhs1 rhs2 max min)) - ((fr400 (unit u-media-2)) + ((fr400 (unit u-media-2)) (fr450 (unit u-media-2)) (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) ) ) @@ -8377,7 +9169,8 @@ name mode conv rhs1 rhs2 max min op ope comment) (dni name (comment) - ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-2)) + ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) + (FR400-MAJOR M-2) (FR450-MAJOR M-4)) (.str name "$pack $FRintieven,$FRintjeven,$ACC40Sk") (+ pack ACC40Sk op FRintieven ope FRintjeven) (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) @@ -8401,6 +9194,9 @@ ((fr400 (unit u-media-2-quad (in FRinti FRintieven) (in FRintj FRintjeven))) + (fr450 (unit u-media-2-quad + (in FRinti FRintieven) + (in FRintj FRintjeven))) (fr500 (unit u-media-quad-complex (in FRinti FRintieven) (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) @@ -8411,7 +9207,8 @@ name mode conv rhs1 rhs2 max min op ope comment) (dni name (comment) - ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-2)) + ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) + (FR400-MAJOR M-2) (FR450-MAJOR M-4)) (.str name "$pack $FRintieven,$FRintjeven,$ACC40Sk") (+ pack ACC40Sk op FRintieven ope FRintjeven) (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) @@ -8435,6 +9232,9 @@ ((fr400 (unit u-media-2-quad (in FRinti FRintieven) (in FRintj FRintjeven))) + (fr450 (unit u-media-2-quad + (in FRinti FRintieven) + (in FRintj FRintjeven))) (fr500 (unit u-media-quad-complex (in FRinti FRintieven) (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) @@ -8479,21 +9279,23 @@ (dni mexpdhw "Media expand halfword to word" - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1)) + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) + (FR400-MAJOR M-1) (FR450-MAJOR M-1)) "mexpdhw$pack $FRinti,$u6,$FRintk" (+ pack FRintk OP_7B FRinti OPE1_32 u6) (media-expand-halfword-to-word-semantics 1) - ((fr400 (unit u-media-3)) + ((fr400 (unit u-media-3)) (fr450 (unit u-media-3)) (fr500 (unit u-media)) (fr550 (unit u-media))) ) (dni cmexpdhw "Conditional media expand halfword to word" - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1) CONDITIONAL) + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) + (FR400-MAJOR M-1) (FR450-MAJOR M-1) CONDITIONAL) "cmexpdhw$pack $FRinti,$u6,$FRintk,$CCi,$cond" (+ pack FRintk OP_76 FRinti CCi cond OPE4_2 u6) (media-expand-halfword-to-word-semantics (eq CCi (or cond 2))) - ((fr400 (unit u-media-3)) + ((fr400 (unit u-media-3)) (fr450 (unit u-media-3)) (fr500 (unit u-media)) (fr550 (unit u-media))) ) @@ -8515,41 +9317,51 @@ (dni mexpdhd "Media expand halfword to double" - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-2)) + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) + (FR400-MAJOR M-2) (FR450-MAJOR M-2)) "mexpdhd$pack $FRinti,$u6,$FRintkeven" (+ pack FRintkeven OP_7B FRinti OPE1_33 u6) (media-expand-halfword-to-double-semantics 1) ((fr400 (unit u-media-dual-expand - (out FRintk FRintkeven))) + (out FRintk FRintkeven))) + (fr450 (unit u-media-dual-expand + (out FRintk FRintkeven))) (fr500 (unit u-media-dual-expand - (out FRintk FRintkeven))) (fr550 (unit u-media-dual-expand))) + (out FRintk FRintkeven))) + (fr550 (unit u-media-dual-expand))) ) (dni cmexpdhd "Conditional media expand halfword to double" - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-2) CONDITIONAL) + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) + (FR400-MAJOR M-2) (FR450-MAJOR M-2) CONDITIONAL) "cmexpdhd$pack $FRinti,$u6,$FRintkeven,$CCi,$cond" (+ pack FRintkeven OP_76 FRinti CCi cond OPE4_3 u6) (media-expand-halfword-to-double-semantics (eq CCi (or cond 2))) ((fr400 (unit u-media-dual-expand (out FRintk FRintkeven))) + (fr450 (unit u-media-dual-expand + (out FRintk FRintkeven))) (fr500 (unit u-media-dual-expand - (out FRintk FRintkeven))) (fr550 (unit u-media-dual-expand))) + (out FRintk FRintkeven))) + (fr550 (unit u-media-dual-expand))) ) (dni mpackh "Media halfword pack" - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1)) + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) + (FR400-MAJOR M-1) (FR450-MAJOR M-1)) "mpackh$pack $FRinti,$FRintj,$FRintk" (+ pack FRintk OP_7B FRinti OPE1_34 FRintj) (media-pack FRinti FRintj FRintk 0) - ((fr400 (unit u-media-3)) + ((fr400 (unit u-media-3)) (fr450 (unit u-media-3)) (fr500 (unit u-media)) (fr550 (unit u-media))) ) (dni mdpackh "Media dual pack" - ((UNIT FM01) (FR500-MAJOR M-5) (FR550-MAJOR M-3) (FR400-MAJOR M-2)) + ((UNIT FM01) (FR500-MAJOR M-5) (FR550-MAJOR M-3) + (FR400-MAJOR M-2) (FR450-MAJOR M-2)) "mdpackh$pack $FRintieven,$FRintjeven,$FRintkeven" (+ pack FRintkeven OP_7B FRintieven OPE1_36 FRintjeven) (if (orif (register-unaligned FRintieven 2) @@ -8567,10 +9379,15 @@ (in FRinti FRintieven) (in FRintj FRintjeven) (out FRintk FRintkeven))) + (fr450 (unit u-media-3-quad + (in FRinti FRintieven) + (in FRintj FRintjeven) + (out FRintk FRintkeven))) (fr500 (unit u-media-quad-arith (in FRinti FRintieven) (in FRintj FRintjeven) - (out FRintk FRintkeven))) (fr550 (unit u-media-quad))) + (out FRintk FRintkeven))) + (fr550 (unit u-media-quad))) ) (define-pmacro (media-unpack src soff targ toff) @@ -8583,7 +9400,8 @@ (dni munpackh "Media halfword unpack" - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-2)) + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) + (FR400-MAJOR M-2) (FR450-MAJOR M-2)) "munpackh$pack $FRinti,$FRintkeven" (+ pack FRintkeven OP_7B FRinti OPE1_35 (FRj-null)) (if (register-unaligned FRintkeven 2) @@ -8595,8 +9413,11 @@ (media-unpack FRinti 0 FRintkeven 0))) ((fr400 (unit u-media-dual-expand (out FRintk FRintkeven))) + (fr450 (unit u-media-dual-expand + (out FRintk FRintkeven))) (fr500 (unit u-media-dual-expand - (out FRintk FRintkeven))) (fr550 (unit u-media-dual-expand))) + (out FRintk FRintkeven))) + (fr550 (unit u-media-dual-expand))) ) (dni mdunpackh @@ -8632,7 +9453,8 @@ (dni mbtoh "Media convert byte to halfword" - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-2)) + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) + (FR400-MAJOR M-2) (FR450-MAJOR M-2)) "mbtoh$pack $FRintj,$FRintkeven" (+ pack FRintkeven OP_7B (FRi-null) OPE1_38 FRintj) (sequence () @@ -8642,13 +9464,17 @@ (mbtoh-semantics 1)) ((fr400 (unit u-media-dual-expand (out FRintk FRintkeven))) + (fr450 (unit u-media-dual-expand + (out FRintk FRintkeven))) (fr500 (unit u-media-dual-btoh - (out FRintk FRintkeven))) (fr550 (unit u-media-dual-expand))) + (out FRintk FRintkeven))) + (fr550 (unit u-media-dual-expand))) ) (dni cmbtoh "Conditional media convert byte to halfword" - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-2) CONDITIONAL) + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) + (FR400-MAJOR M-2) (FR450-MAJOR M-2) CONDITIONAL) "cmbtoh$pack $FRintj,$FRintkeven,$CCi,$cond" (+ pack FRintkeven OP_77 (FRi-null) CCi cond OPE4_0 FRintj) (sequence () @@ -8658,8 +9484,12 @@ (mbtoh-semantics (eq CCi (or cond 2)))) ((fr400 (unit u-media-dual-expand (out FRintk FRintkeven))) + (fr450 (unit u-media-dual-expand + (out FRintk FRintkeven))) (fr500 (unit u-media-dual-btoh - (out FRintk FRintkeven))) (fr550 (unit u-media-dual-expand (in FRinti FRintj)))) + (out FRintk FRintkeven))) + (fr550 (unit u-media-dual-expand + (in FRinti FRintj)))) ) (define-pmacro (mhtob-semantics cond) @@ -8675,7 +9505,8 @@ (dni mhtob "Media convert halfword to byte" - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-2)) + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) + (FR400-MAJOR M-2) (FR450-MAJOR M-2)) "mhtob$pack $FRintjeven,$FRintk" (+ pack FRintk OP_7B (FRi-null) OPE1_39 FRintjeven) (sequence () @@ -8685,13 +9516,18 @@ (mhtob-semantics 1)) ((fr400 (unit u-media-dual-htob (in FRintj FRintjeven))) + (fr450 (unit u-media-dual-htob + (in FRintj FRintjeven))) (fr500 (unit u-media-dual-htob - (in FRintj FRintjeven))) (fr550 (unit u-media-3-dual (in FRinti FRintjeven)))) + (in FRintj FRintjeven))) + (fr550 (unit u-media-3-dual + (in FRinti FRintjeven)))) ) (dni cmhtob "Conditional media convert halfword to byte" - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-2) CONDITIONAL) + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) + (FR400-MAJOR M-2) (FR450-MAJOR M-2) CONDITIONAL) "cmhtob$pack $FRintjeven,$FRintk,$CCi,$cond" (+ pack FRintk OP_77 (FRi-null) CCi cond OPE4_1 FRintjeven) (sequence () @@ -8701,8 +9537,12 @@ (mhtob-semantics (eq CCi (or cond 2)))) ((fr400 (unit u-media-dual-htob (in FRintj FRintjeven))) + (fr450 (unit u-media-dual-htob + (in FRintj FRintjeven))) (fr500 (unit u-media-dual-htob - (in FRintj FRintjeven))) (fr550 (unit u-media-3-dual (in FRinti FRintjeven)))) + (in FRintj FRintjeven))) + (fr550 (unit u-media-3-dual + (in FRinti FRintjeven)))) ) (define-pmacro (mbtohe-semantics cond) @@ -8749,7 +9589,8 @@ ; Media NOP ; A special case of mclracc (dni mnop "Media nop" - ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-1) (FR400-MAJOR M-1)) + ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-1) + (FR400-MAJOR M-1) (FR450-MAJOR M-1)) "mnop$pack" (+ pack (f-ACC40Sk 63) OP_7B (f-A 1) (misc-null-10) OPE1_3B (FRj-null)) (nop) @@ -8759,66 +9600,72 @@ ; mclracc with #A==0 (dni mclracc-0 "Media clear accumulator(s)" - ((UNIT FM01) (FR500-MAJOR M-3) (FR550-MAJOR M-3) (FR400-MAJOR M-1)) + ((UNIT FM01) (FR500-MAJOR M-3) (FR550-MAJOR M-3) + (FR400-MAJOR M-1) (FR450-MAJOR M-3)) "mclracc$pack $ACC40Sk,$A0" (+ pack ACC40Sk OP_7B (f-A 0) (misc-null-10) OPE1_3B (FRj-null)) (c-call VOID "@cpu@_clear_accumulators" (index-of ACC40Sk) 0) - ((fr400 (unit u-media-4)) + ((fr400 (unit u-media-4)) (fr450 (unit u-media-4)) (fr500 (unit u-media)) (fr550 (unit u-media-3-mclracc))) ) ; mclracc with #A==1 (dni mclracc-1 "Media clear accumulator(s)" - ((UNIT MCLRACC-1) (FR500-MAJOR M-6) (FR550-MAJOR M-3) (FR400-MAJOR M-2)) + ((UNIT MCLRACC-1) (FR500-MAJOR M-6) (FR550-MAJOR M-3) + (FR400-MAJOR M-2) (FR450-MAJOR M-4)) "mclracc$pack $ACC40Sk,$A1" (+ pack ACC40Sk OP_7B (f-A 1) (misc-null-10) OPE1_3B (FRj-null)) (c-call VOID "@cpu@_clear_accumulators" (index-of ACC40Sk) 1) - ((fr400 (unit u-media-4)) + ((fr400 (unit u-media-4)) (fr450 (unit u-media-4-mclracca)) (fr500 (unit u-media)) (fr550 (unit u-media-3-mclracc))) ) (dni mrdacc "Media read accumulator" - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1)) + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) + (FR400-MAJOR M-1) (FR450-MAJOR M-5)) "mrdacc$pack $ACC40Si,$FRintk" (+ pack FRintk OP_7B ACC40Si OPE1_3C (FRj-null)) (set FRintk ACC40Si) - ((fr400 (unit u-media-4)) + ((fr400 (unit u-media-4)) (fr450 (unit u-media-4)) (fr500 (unit u-media)) (fr550 (unit u-media-3-acc))) ) (dni mrdaccg "Media read accumulator guard" - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1)) + ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) + (FR400-MAJOR M-1) (FR450-MAJOR M-5)) "mrdaccg$pack $ACCGi,$FRintk" (+ pack FRintk OP_7B ACCGi OPE1_3E (FRj-null)) (set FRintk ACCGi) - ((fr400 (unit u-media-4-accg)) + ((fr400 (unit u-media-4-accg)) (fr450 (unit u-media-4-accg)) (fr500 (unit u-media)) (fr550 (unit u-media-3-acc (in ACC40Si ACCGi)))) ) (dni mwtacc "Media write accumulator" - ((UNIT FM01) (FR500-MAJOR M-3) (FR550-MAJOR M-3) (FR400-MAJOR M-1)) + ((UNIT FM01) (FR500-MAJOR M-3) (FR550-MAJOR M-3) + (FR400-MAJOR M-1) (FR450-MAJOR M-3)) "mwtacc$pack $FRinti,$ACC40Sk" (+ pack ACC40Sk OP_7B FRinti OPE1_3D (FRj-null)) (set ACC40Sk (or (and ACC40Sk (const DI #xffffffff00000000)) FRinti)) - ((fr400 (unit u-media-4)) + ((fr400 (unit u-media-4)) (fr450 (unit u-media-4)) (fr500 (unit u-media)) (fr550 (unit u-media-3-wtacc))) ) (dni mwtaccg "Media write accumulator guard" - ((UNIT FM01) (FR500-MAJOR M-3) (FR550-MAJOR M-3) (FR400-MAJOR M-1)) + ((UNIT FM01) (FR500-MAJOR M-3) (FR550-MAJOR M-3) + (FR400-MAJOR M-1) (FR450-MAJOR M-3)) "mwtaccg$pack $FRinti,$ACCGk" (+ pack ACCGk OP_7B FRinti OPE1_3F (FRj-null)) (sequence () ; hack to get these referenced for profiling (c-raw-call VOID "frv_ref_SI" ACCGk) (set ACCGk FRinti)) - ((fr400 (unit u-media-4-accg)) + ((fr400 (unit u-media-4-accg)) (fr450 (unit u-media-4-accg)) (fr500 (unit u-media)) (fr550 (unit u-media-3-wtacc (in ACC40Sk ACCGk)))) ) @@ -8842,7 +9689,7 @@ ; On the other hand spending a little time in the decoder is often worth it. ; (dnmi nop "nop" - ((UNIT IALL) (FR500-MAJOR I-1) (FR400-MAJOR I-1)) + ((UNIT IALL) (FR500-MAJOR I-1) (FR400-MAJOR I-1) (FR450-MAJOR I-1)) "nop$pack" (emit ori pack (GRi 0) (s12 0) (GRk 0)) ) @@ -8859,37 +9706,43 @@ ; A return instruction (dnmi ret "return" - (NO-DIS (UNIT B01) (FR500-MAJOR B-3) (FR400-MAJOR B-3)) + (NO-DIS (UNIT B01) (FR500-MAJOR B-3) + (FR400-MAJOR B-3) (FR450-MAJOR B-3)) "ret$pack" (emit bralr pack (hint_taken 2)) ) (dnmi cmp "compare" - (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) (FR400-MAJOR I-1)) + (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1)) "cmp$pack $GRi,$GRj,$ICCi_1" (emit subcc pack GRi GRj (GRk 0) ICCi_1) ) (dnmi cmpi "compare immediate" - (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) (FR400-MAJOR I-1)) + (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1)) "cmpi$pack $GRi,$s10,$ICCi_1" (emit subicc pack GRi s10 (GRk 0) ICCi_1) ) (dnmi ccmp "conditional compare" - (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL) + (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) "ccmp$pack $GRi,$GRj,$CCi,$cond" (emit csubcc pack GRi GRj (GRk 0) CCi cond) ) (dnmi mov "move" - (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) (FR400-MAJOR I-1)) + (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1)) "mov$pack $GRi,$GRk" (emit ori pack GRi (s12 0) GRk) ) (dnmi cmov "conditional move" - (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL) + (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) + (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) "cmov$pack $GRi,$GRk,$CCi,$cond" (emit cor pack GRi (GRj 0) GRk CCi cond) ) diff --git a/cpu/frv.opc b/cpu/frv.opc index 03c0f3e1437..46985b6110a 100644 --- a/cpu/frv.opc +++ b/cpu/frv.opc @@ -90,6 +90,8 @@ static int find_major_in_vliw PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE)); static int fr400_check_insn_major_constraints PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE)); +static int fr450_check_insn_major_constraints + PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE)); static int fr500_check_insn_major_constraints PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE)); static int fr550_check_insn_major_constraints @@ -106,6 +108,10 @@ frv_is_branch_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) if (major >= FR400_MAJOR_B_1 && major <= FR400_MAJOR_B_6) return 1; /* is a branch */ break; + case bfd_mach_fr450: + if (major >= FR450_MAJOR_B_1 && major <= FR450_MAJOR_B_6) + return 1; /* is a branch */ + break; default: if (major >= FR500_MAJOR_B_1 && major <= FR500_MAJOR_B_6) return 1; /* is a branch */ @@ -121,6 +127,7 @@ frv_is_float_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) switch (mach) { case bfd_mach_fr400: + case bfd_mach_fr450: return 0; /* No float insns */ default: if (major >= FR500_MAJOR_F_1 && major <= FR500_MAJOR_F_8) @@ -140,6 +147,10 @@ frv_is_media_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) if (major >= FR400_MAJOR_M_1 && major <= FR400_MAJOR_M_2) return 1; /* is a media insn */ break; + case bfd_mach_fr450: + if (major >= FR450_MAJOR_M_1 && major <= FR450_MAJOR_M_6) + return 1; /* is a media insn */ + break; default: if (major >= FR500_MAJOR_M_1 && major <= FR500_MAJOR_M_8) return 1; /* is a media insn */ @@ -155,6 +166,9 @@ frv_is_branch_insn (const CGEN_INSN *insn) if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR), bfd_mach_fr400)) return 1; + if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR), + bfd_mach_fr450)) + return 1; if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR), bfd_mach_fr500)) return 1; @@ -168,6 +182,9 @@ frv_is_float_insn (const CGEN_INSN *insn) if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR), bfd_mach_fr400)) return 1; + if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR), + bfd_mach_fr450)) + return 1; if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR), bfd_mach_fr500)) return 1; @@ -181,6 +198,9 @@ frv_is_media_insn (const CGEN_INSN *insn) if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR), bfd_mach_fr400)) return 1; + if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR), + bfd_mach_fr450)) + return 1; if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR), bfd_mach_fr500)) return 1; @@ -291,6 +311,42 @@ static CGEN_ATTR_VALUE_TYPE fr400_unit_mapping[] = /* SCAN */ UNIT_I0, /* scan only in I0 unit. */ /* DCPL */ UNIT_C, /* dcpl only in C unit. */ /* MDUALACC */ UNIT_FM0, /* media dual acc insn only in FM0 unit. */ +/* MDCUTSSI */ UNIT_FM0, /* mdcutssi only in FM0 unit. */ +/* MCLRACC-1*/ UNIT_FM0 /* mclracc,A==1 insn only in FM0 unit. */ +}; + +/* Some insns are assigned specialized implementation units which map to + different actual implementation units on different machines. These + tables perform that mapping. */ +static CGEN_ATTR_VALUE_TYPE fr450_unit_mapping[] = +{ +/* unit in insn actual unit */ +/* NIL */ UNIT_NIL, +/* I0 */ UNIT_I0, +/* I1 */ UNIT_I1, +/* I01 */ UNIT_I01, +/* I2 */ UNIT_NIL, /* no I2 or I3 unit */ +/* I3 */ UNIT_NIL, +/* IALL */ UNIT_I01, /* only I0 and I1 units */ +/* FM0 */ UNIT_FM0, +/* FM1 */ UNIT_FM1, +/* FM01 */ UNIT_FM01, +/* FM2 */ UNIT_NIL, /* no F2 or M2 units */ +/* FM3 */ UNIT_NIL, /* no F3 or M3 units */ +/* FMALL */ UNIT_FM01,/* Only F0,F1,M0,M1 units */ +/* FMLOW */ UNIT_FM0, /* Only F0,M0 units */ +/* B0 */ UNIT_B0, /* branches only in B0 unit. */ +/* B1 */ UNIT_B0, +/* B01 */ UNIT_B0, +/* C */ UNIT_C, +/* MULT-DIV */ UNIT_I0, /* multiply and divide only in I0 unit. */ +/* IACC */ UNIT_I01, /* iacc multiply in I0 or I1 unit. */ +/* LOAD */ UNIT_I0, /* load only in I0 unit. */ +/* STORE */ UNIT_I0, /* store only in I0 unit. */ +/* SCAN */ UNIT_I0, /* scan only in I0 unit. */ +/* DCPL */ UNIT_I0, /* dcpl only in I0 unit. */ +/* MDUALACC */ UNIT_FM0, /* media dual acc insn only in FM0 unit. */ +/* MDCUTSSI */ UNIT_FM01, /* mdcutssi in FM0 or FM1. */ /* MCLRACC-1*/ UNIT_FM0 /* mclracc,A==1 insn only in FM0 unit. */ }; @@ -322,6 +378,7 @@ static CGEN_ATTR_VALUE_TYPE fr500_unit_mapping[] = /* SCAN */ UNIT_I01, /* scan in I0 or I1 unit. */ /* DCPL */ UNIT_C, /* dcpl only in C unit. */ /* MDUALACC */ UNIT_FM0, /* media dual acc insn only in FM0 unit. */ +/* MDCUTSSI */ UNIT_FM0, /* mdcutssi only in FM0 unit. */ /* MCLRACC-1*/ UNIT_FM01 /* mclracc,A==1 in FM0 or FM1 unit. */ }; @@ -353,6 +410,7 @@ static CGEN_ATTR_VALUE_TYPE fr550_unit_mapping[] = /* SCAN */ UNIT_IALL, /* scan in any integer unit. */ /* DCPL */ UNIT_I0, /* dcpl only in I0 unit. */ /* MDUALACC */ UNIT_FMALL,/* media dual acc insn in all media units */ +/* MDCUTSSI */ UNIT_FM01, /* mdcutssi in FM0 or FM1 unit. */ /* MCLRACC-1*/ UNIT_FM01 /* mclracc,A==1 in FM0 or FM1 unit. */ }; @@ -370,6 +428,10 @@ frv_vliw_reset (FRV_VLIW *vliw, unsigned long mach, unsigned long elf_flags) vliw->current_vliw = fr400_allowed_vliw; vliw->unit_mapping = fr400_unit_mapping; break; + case bfd_mach_fr450: + vliw->current_vliw = fr400_allowed_vliw; + vliw->unit_mapping = fr450_unit_mapping; + break; case bfd_mach_fr550: vliw->current_vliw = fr550_allowed_vliw; vliw->unit_mapping = fr550_unit_mapping; @@ -499,12 +561,51 @@ fr400_check_insn_major_constraints ( case FR400_MAJOR_M_2: return ! find_major_in_vliw (vliw, FR400_MAJOR_M_1) && ! find_major_in_vliw (vliw, FR400_MAJOR_M_2); + case FR400_MAJOR_M_1: + return !find_major_in_vliw (vliw, FR400_MAJOR_M_2); default: break; } return 1; } +static int +fr450_check_insn_major_constraints ( + FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major +) +{ + CGEN_ATTR_VALUE_TYPE other_major; + + /* Our caller guarantees there's at least one other instruction. */ + other_major = CGEN_INSN_ATTR_VALUE (vliw->insn[0], CGEN_INSN_FR450_MAJOR); + + /* (M4, M5) and (M4, M6) are allowed. */ + if (other_major == FR450_MAJOR_M_4) + if (major == FR450_MAJOR_M_5 || major == FR450_MAJOR_M_6) + return 1; + + /* Otherwise, instructions in even-numbered media categories cannot be + executed in parallel with other media instructions. */ + switch (major) + { + case FR450_MAJOR_M_2: + case FR450_MAJOR_M_4: + case FR450_MAJOR_M_6: + return !(other_major >= FR450_MAJOR_M_1 + && other_major <= FR450_MAJOR_M_6); + + case FR450_MAJOR_M_1: + case FR450_MAJOR_M_3: + case FR450_MAJOR_M_5: + return !(other_major == FR450_MAJOR_M_2 + || other_major == FR450_MAJOR_M_4 + || other_major == FR450_MAJOR_M_6); + + default: + return 1; + } +} + static int find_unit_in_vliw ( FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit @@ -742,6 +843,9 @@ check_insn_major_constraints ( case bfd_mach_fr400: rc = fr400_check_insn_major_constraints (vliw, major); break; + case bfd_mach_fr450: + rc = fr450_check_insn_major_constraints (vliw, major); + break; case bfd_mach_fr550: rc = fr550_check_insn_major_constraints (vliw, major, insn); break; @@ -782,6 +886,9 @@ frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn) case bfd_mach_fr400: major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR); break; + case bfd_mach_fr450: + major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR); + break; case bfd_mach_fr550: major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR550_MAJOR); break; diff --git a/gdb/ChangeLog b/gdb/ChangeLog index 6382a3d1118..486d14e2cb6 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,3 +1,224 @@ +2004-03-09 Daniel Jacobowitz + + * user-regs.c: Update copyright years. + (struct user_regs): Rename to gdb_user_regs. + (append_user_reg, builtin_user_regs, user_regs_init) + (user_reg_add, user_reg_map_name_to_regnum) + (usernum_to_user_reg): Update. + +2004-03-09 Daniel Jacobowitz + + * dwarf2read.c (skip_leb128, peek_die_abbrev, skip_one_die) + (skip_children): New functions. + (locate_pdi_sibling): Call skip_children. + +2004-03-09 Daniel Jacobowitz + + * arm-tdep.c (arm_use_struct_convention): Look through typedefs. + * gdbtypes.c (check_typedef): Update comments. + +2004-03-09 Daniel Jacobowitz + + * dwarf2read.c (struct comp_unit_head): Remove dwarf2_abbrevs array. + (struct dwarf2_cu): Add abbrev_obstack and dwarf2_abbrevs + pointer. Update comment about comp_unit_head. + (struct abbrev_info): Shorten two int flags. + (dwarf_alloc_abbrev): Take a CU argument. + (dwarf2_build_psymtabs_hard): Call dwarf2_free_abbrev_table + each time through the loop. Update cleanup argument. + (psymtab_to_symtab_1): Update cleanup call. + (dwarf2_read_abbrevs, dwarf2_alloc_abbrev): Allocate on the + abbrev_obstack. + (dwarf2_free_abbrev_table): Renamed from dwarf2_empty_abbrev_table. + Just call obstack_free and clear the pointer. + +2004-03-09 Daniel Jacobowitz + + * infrun.c (handle_inferior_event): Remove short-circuit code for + events in a different thread. + +2004-03-09 Daniel Jacobowitz + + * target.c (debug_to_xfer_memory): If targetdebug is 1, don't + print the whole transfer. + (initialize_targets): Update description of "set debug target". + +2004-03-09 Daniel Jacobowitz + + * arm-tdep.c (thumb_get_next_pc): Handle Thumb BLX. + +2004-03-08 Nathan J. Williams + + * MAINTAINERS (write after approval): Add myself. + +2004-03-08 Corinna Vinschen + + * sh-tdep.c (sh_print_registers_info): Use for loop. + Don't skip multiple registers when a float register is encountered. + +2004-03-08 Corinna Vinschen + + Fix PR tdep/1291. + * sh-tdep.c (sh_analyze_prologue): Align PC relative addressing + to official SH documentation. + +2004-03-07 Andrew Cagney + + * ppc-linux-nat.c (ppc_ptrace_cannot_fetch_store_register): Delete + unused function. + +2004-03-07 Daniel Jacobowitz + + * arm-tdep.c (thumb_get_next_pc): Handle BX. + (arm_get_next_pc): Handle BX and BLX. + +2004-03-07 Andrew Cagney + + * hppa-tdep.c: Replace DEPRECATED_FP_REGNUM with HPPA_FP_REGNUM, + FP0_REGNUM with HPPA_FP0_REGNUM, and SP_REGNUM with + HPPA_SP_REGNUM. + (hppa_register_raw_size, hppa_register_byte, hppa_read_fp) + (hppa_target_read_fp): Delete. + (hppa_gdbarch_init): Do not set deprecated register_raw_size, + register_virtual_size, max_register_raw_size, + max_register_virtual_size, register_byte, register_size, + target_read_fp, fp_regnum, and register_bytes. Set register_type + instead of register_virtual_type. + (hppa32_register_type, hppa64_register_type): Replace + hppa32_register_virtual_type and hppa64_register_virtual_type. + * config/pa/tm-hppa.h (HPPA_FP0_REGNUM, HPPA_SP_REGNUM) + (HPPA_FP_REGNUM): Define. + + * hppa-tdep.c (hppa_gdbarch_init): Add missing "break". + + * config/pa/tm-hppa.h (DEPRECATED_DO_REGISTERS_INFO) + (pa_do_registers_info): Delete. + * hppa-tdep.c (pa_do_registers_info, pa_do_strcat_registers_info) + (pa_print_registers, pa_print_fp_reg, pa_strcat_registers) + (pa_strcat_fp_reg, pa_register_look_aside): Delete. + + * infcall.c (legacy_push_dummy_code): Delete #ifdef + GDB_TARGET_IS_HPPA code. + * config/pa/tm-hppa.h (DEPRECATED_FIX_CALL_DUMMY) + (hppa_fix_call_dummy, DEPRECATED_CALL_DUMMY_HAS_COMPLETED) + (DEPRECATED_DUMMY_WRITE_SP, CALL_DUMMY): Delete. + * config/pa/tm-hppa64.h (CALL_DUMMY): Delete. + * hppa-tdep.c (hppa_frame_chain, hppa_frame_chain_valid) + (hppa_push_dummy_frame, hppa_pop_frame, hppa_push_arguments) + (hppa_fix_call_dummy, hppa64_stack_align, hppa_frame_saved_pc) + (hppa_init_extra_frame_info, hppa_saved_pc_after_call) + (hppa64_call_dummy_breakpoint_offset, hppa_frame_init_saved_regs) + (hppa_frameless_function_invocation, hppa64_store_return_value) + (hppa_store_struct_return, hppa64_extract_return_value) + (hppa64_use_struct_convention, hppa_frame_find_saved_regs) + (hppa32_call_dummy_length, hppa64_call_dummy_length) + (find_dummy_frame_regs, FUNC_LDIL_OFFSET, FUNC_LDO_OFFSET) + (find_proc_framesize, deposit_21, restore_pc_queue) + (find_return_regnum, pc_in_interrupt_handler, deposit_14) + (rp_saved, pc_in_linker_stub): Delete. + + Unconditionally enable 64-bit frame and ABI code. + * hppa-tdep.c (hppa_gdbarch_init): Do not set deprecated + call_dummy_breakpoint_offset, call_dummy_length, stack_align, + push_dummy_frame, fix_call_dummy, push_arguments, + call_dummy_location, extract_return_value, use_struct_convention, + store_return_value, store_struct_return, saved_pc_after_call, + init_frame_pc, frame_init_saved_regs, init_extra_frame_info, + frame_chain, frame_chain_valid, frameless_function_invocation, + frame_saved_pc, and pop_frame. + + * hppa-tdep.c: Replace PC_REGNUM with PCOQ_HEAD_REGNUM. + (hppa64_return_value, hppa64_push_dummy_call): Rewrite. + (hppa_gdbarch_init): Do not set PC_REGNUM. + +2004-03-06 Mark Kettenis + + * config/alpha/tm-fbsd.h: Remove file. + * config/alpha/fbsd.mt: Tweak comment. + (TM_FILE): Set to tm-alpha.h. + +2004-03-05 Andrew Cagney + + * infrun.c (step_over_function): When non-legacy code, and no + step_frame_id, use the unwinder to get the caller's frame ID. + +2004-03-05 Mark Kettenis + + * i386bsd-tdep.c (_initialize_i386bsd_tdep): Register + i386bsd_core_osabi_sniffer for bfd_arch_i386 instead of + bfd_arch_unknown. Adjust comment. + + * i386-nat.c: Fix typo in comment. Re-introduce paranoiac. + * i386obsd-tdep.c: Correct spelling in comment. + * i386nbsd-tdep.c: Correct spelling in comment. + * sparc-tdep.c: Correct spelling in comments. + +2004-03-05 David Carlton + + * cp-namespace.c (cp_lookup_transparent_type_loop): Fix recursion + bug. + +2004-03-05 Mark Kettenis + + * sparc-tdep.c: Fix typo in comment. + +2004-03-04 J. Brobecker + + * hppa-tdep.c (hppa_frame_cache): Avoid undefined return value. + +2004-03-04 Daniel Jacobowitz + + * dwarf2read.c: Add comment describing memory lifetimes. + (struct dwarf2_pinfo): Update comment. + (dwarf2_add_field, dwarf2_add_member_fn, read_structure_scope) + (read_enumeration, new_symbol): Don't use obsavestring. + +2004-03-04 Mark Kettenis + + * amd64-linux-nat.c (fill_fpregset): Call amd64_colletc_fxsave + instead of amd64_fill_fxsave. + * amd64bsd-nat.c (store_inferior_registers): Likewise. + * amd64fbsd-nat.c (fill_fpregset): Likewise. + + * sparc-tdep.c (sparc_frame_cache): Don't bail out if %fp is zero. + Reorganize code a bit. + +2004-03-04 Orjan Friberg + + * cris-tdep.c (cris_scan_prologue): Save the frame pointer's offset + when the frame pointer is pushed. Don't set the frame pointer's + address on the stack unless it's actually located there. + Set the SRP's address on the stack correctly when the PC is still in + the prologue. + (cris_return_value): New function. + (cris_gdbarch_init): Clear deprecated store_return_value, + extract_return_value. + +2004-03-02 Jim Blandy + + * stabsread.c (reg_value_complaint): The maximum register number + is one less than the number of registers. + +2004-03-02 Andrew Cagney + + * i386-tdep.h (enum i386_regnum): Add I386_DS_REGNUM, + I386_ES_REGNUM, I386_FS_REGNUM, and I386_GS_REGNUM. Remove + trailing comma and redundant assignment of I386_ST0_REGNUM. + * amd64-nat.c (amd64_collect_native_gregset): Zero-extend the + 32-bit segment registers. + +2004-03-01 Andrew Cagney + + * rs6000-tdep.c (rs6000_init_frame_pc_first): Fix compiler error, + use frame_relative_level and get_next_frame. + +2004-02-29 Andrew Cagney + + * rs6000-tdep.c (rs6000_init_frame_pc_first): New function. + (rs6000_gdbarch_init): Set deprecated_init_frame_pc_first. + * config/rs6000/tm-rs6000.h (DEPRECATED_INIT_FRAME_PC_FIRST): + Delete macro. + 2004-02-29 Daniel Jacobowitz * inflow.c (terminal_inferior): Don't give up the terminal if we diff --git a/gdb/MAINTAINERS b/gdb/MAINTAINERS index 59249867a8b..929d6602887 100644 --- a/gdb/MAINTAINERS +++ b/gdb/MAINTAINERS @@ -405,6 +405,7 @@ D Venkatasubramanian dvenkat@noida.hcltech.com Corinna Vinschen vinschen@redhat.com Keith Walker keith.walker@arm.com Kris Warkentin kewarken@qnx.com +Nathan Williams nathanw@wasabisystems.com Jim Wilson wilson@specifixinc.com Elena Zannoni ezannoni@redhat.com Eli Zaretskii eliz@gnu.org diff --git a/gdb/amd64-linux-nat.c b/gdb/amd64-linux-nat.c index ec0bfb92812..63417c40b09 100644 --- a/gdb/amd64-linux-nat.c +++ b/gdb/amd64-linux-nat.c @@ -176,7 +176,7 @@ supply_fpregset (elf_fpregset_t *fpregsetp) void fill_fpregset (elf_fpregset_t *fpregsetp, int regnum) { - amd64_fill_fxsave ((char *) fpregsetp, regnum); + amd64_collect_fxsave (current_regcache, regnum, fpregsetp); } /* Fetch all floating-point registers from process/thread TID and store diff --git a/gdb/amd64-nat.c b/gdb/amd64-nat.c index 1efe47a5698..31b360377be 100644 --- a/gdb/amd64-nat.c +++ b/gdb/amd64-nat.c @@ -139,6 +139,12 @@ amd64_collect_native_gregset (const struct regcache *regcache, if (regnum == -1 || regnum == i) memset (regs + amd64_native_gregset_reg_offset (i), 0, 8); } + /* Ditto for %cs, %ss, %ds, %es, %fs, and %gs. */ + for (i = I386_CS_REGNUM; i <= I386_GS_REGNUM; i++) + { + if (regnum == -1 || regnum == i) + memset (regs + amd64_native_gregset_reg_offset (i), 0, 8); + } } if (num_regs > NUM_REGS) diff --git a/gdb/amd64bsd-nat.c b/gdb/amd64bsd-nat.c index 4c7c04a881d..777fd690b39 100644 --- a/gdb/amd64bsd-nat.c +++ b/gdb/amd64bsd-nat.c @@ -98,7 +98,7 @@ store_inferior_registers (int regnum) (PTRACE_ARG3_TYPE) &fpregs, 0) == -1) perror_with_name ("Couldn't get floating point status"); - amd64_fill_fxsave ((char *) &fpregs, regnum); + amd64_collect_fxsave (current_regcache, regnum, &fpregs); if (ptrace (PT_SETFPREGS, PIDGET (inferior_ptid), (PTRACE_ARG3_TYPE) &fpregs, 0) == -1) diff --git a/gdb/amd64fbsd-nat.c b/gdb/amd64fbsd-nat.c index f08373422c2..61ce73cce9d 100644 --- a/gdb/amd64fbsd-nat.c +++ b/gdb/amd64fbsd-nat.c @@ -141,7 +141,7 @@ supply_fpregset (fpregset_t *fpregsetp) void fill_fpregset (fpregset_t *fpregsetp, int regnum) { - amd64_fill_fxsave ((char *) fpregsetp, regnum); + amd64_collect_fxsave (current_regcache, regnum, fpregsetp); } diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 9d53facf124..bf54a318d19 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -1651,11 +1651,25 @@ thumb_get_next_pc (CORE_ADDR pc) { nextpc = pc_val + (sbits (inst1, 0, 10) << 1); } - else if ((inst1 & 0xf800) == 0xf000) /* long branch with link */ + else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */ { unsigned short inst2 = read_memory_integer (pc + 2, 2); offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); nextpc = pc_val + offset; + /* For BLX make sure to clear the low bits. */ + if (bits (inst2, 11, 12) == 1) + nextpc = nextpc & 0xfffffffc; + } + else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */ + { + if (bits (inst1, 3, 6) == 0x0f) + nextpc = pc_val; + else + nextpc = read_register (bits (inst1, 3, 6)); + + nextpc = ADDR_BITS_REMOVE (nextpc); + if (nextpc == pc) + error ("Infinite loop detected"); } return nextpc; @@ -1697,6 +1711,20 @@ arm_get_next_pc (CORE_ADDR pc) && bits (this_instr, 4, 7) == 9) /* multiply */ error ("Illegal update to pc in instruction"); + /* BX , BLX */ + if (bits (this_instr, 4, 28) == 0x12fff1 + || bits (this_instr, 4, 28) == 0x12fff3) + { + rn = bits (this_instr, 0, 3); + result = (rn == 15) ? pc_val + 8 : read_register (rn); + nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); + + if (nextpc == pc) + error ("Infinite loop detected"); + + return nextpc; + } + /* Multiply into PC */ c = (status & FLAG_C) ? 1 : 0; rn = bits (this_instr, 16, 19); @@ -1862,6 +1890,10 @@ arm_get_next_pc (CORE_ADDR pc) { nextpc = BranchDest (pc, this_instr); + /* BLX */ + if (bits (this_instr, 28, 31) == INST_NV) + nextpc |= bit (this_instr, 24) << 1; + nextpc = ADDR_BITS_REMOVE (nextpc); if (nextpc == pc) error ("Infinite loop detected"); @@ -2141,6 +2173,8 @@ arm_use_struct_convention (int gcc_p, struct type *type) int nRc; enum type_code code; + CHECK_TYPEDEF (type); + /* In the ARM ABI, "integer" like aggregate types are returned in registers. For an aggregate type to be integer like, its size must be less than or equal to DEPRECATED_REGISTER_SIZE and the @@ -2198,7 +2232,7 @@ arm_use_struct_convention (int gcc_p, struct type *type) for (i = 0; i < TYPE_NFIELDS (type); i++) { enum type_code field_type_code; - field_type_code = TYPE_CODE (TYPE_FIELD_TYPE (type, i)); + field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i))); /* Is it a floating point type field? */ if (field_type_code == TYPE_CODE_FLT) diff --git a/gdb/config/alpha/fbsd.mt b/gdb/config/alpha/fbsd.mt index 24d2fd80b84..b126c682292 100644 --- a/gdb/config/alpha/fbsd.mt +++ b/gdb/config/alpha/fbsd.mt @@ -1,3 +1,3 @@ -# Target: FreeBSD/Alpha +# Target: FreeBSD/alpha TDEPFILES= alpha-tdep.o alpha-mdebug-tdep.o alphabsd-tdep.o alphafbsd-tdep.o -TM_FILE= tm-fbsd.h +TM_FILE= tm-alpha.h diff --git a/gdb/config/alpha/tm-fbsd.h b/gdb/config/alpha/tm-fbsd.h deleted file mode 100644 index c154366cc19..00000000000 --- a/gdb/config/alpha/tm-fbsd.h +++ /dev/null @@ -1,27 +0,0 @@ -/* Target-dependent definitions for FreeBSD/Alpha. - - Copyright 2000, 2001, 2002, 2004 Free Software Foundation, Inc. - - This file is part of GDB. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, - Boston, MA 02111-1307, USA. */ - -#ifndef TM_FBSD_H -#define TM_FBSD_H - -#include "alpha/tm-alpha.h" - -#endif /* TM_FBSD_H */ diff --git a/gdb/config/pa/tm-hppa.h b/gdb/config/pa/tm-hppa.h index 9924ffa9678..13dbd2876c3 100644 --- a/gdb/config/pa/tm-hppa.h +++ b/gdb/config/pa/tm-hppa.h @@ -26,9 +26,6 @@ #include "regcache.h" -/* Wonder if this is correct? Should be using push_dummy_call(). */ -#define DEPRECATED_DUMMY_WRITE_SP(SP) deprecated_write_sp (SP) - #define GDB_MULTI_ARCH 1 /* Hack, get around problem with including "arch-utils.h". */ @@ -62,6 +59,8 @@ extern int hppa_pc_requires_run_before_use (CORE_ADDR pc); other r registers. */ #define FLAGS_REGNUM 0 /* Various status flags */ #define RP_REGNUM 2 /* return pointer */ +#define HPPA_FP_REGNUM 3 /* The ABI's frame pointer, when used */ +#define HPPA_SP_REGNUM 30 /* Stack pointer. */ #define SAR_REGNUM 32 /* Shift Amount Register */ #define IPSW_REGNUM 41 /* Interrupt Processor Status Word */ #define PCOQ_HEAD_REGNUM 33 /* instruction offset queue head */ @@ -76,6 +75,7 @@ extern int hppa_pc_requires_run_before_use (CORE_ADDR pc); #define CCR_REGNUM 54 /* Coprocessor Configuration Register */ #define TR0_REGNUM 57 /* Temporary Registers (cr24 -> cr31) */ #define CR27_REGNUM 60 /* Base register for thread-local storage, cr27 */ +#define HPPA_FP0_REGNUM 64 /* First floating-point. */ #define FP4_REGNUM 72 #define ARG0_REGNUM 26 /* The first argument of a callee. */ @@ -93,12 +93,6 @@ extern int hppa_pc_requires_run_before_use (CORE_ADDR pc); (buf)[sizeof(CORE_ADDR) -1] &= ~0x3; \ } while (0) -/* Define DEPRECATED_DO_REGISTERS_INFO() to do machine-specific - formatting of register dumps. */ - -#define DEPRECATED_DO_REGISTERS_INFO(_regnum, fp) pa_do_registers_info (_regnum, fp) -extern void pa_do_registers_info (int, int); - /* PA specific macro to see if the current instruction is nullified. */ #ifndef INSTRUCTION_NULLIFIED extern int hppa_instruction_nullified (void); @@ -107,102 +101,8 @@ extern int hppa_instruction_nullified (void); #define INSTRUCTION_SIZE 4 -/* This sequence of words is the instructions - - ; Call stack frame has already been built by gdb. Since we could be calling - ; a varargs function, and we do not have the benefit of a stub to put things in - ; the right place, we load the first 4 word of arguments into both the general - ; and fp registers. - call_dummy - ldw -36(sp), arg0 - ldw -40(sp), arg1 - ldw -44(sp), arg2 - ldw -48(sp), arg3 - ldo -36(sp), r1 - fldws 0(0, r1), fr4 - fldds -4(0, r1), fr5 - fldws -8(0, r1), fr6 - fldds -12(0, r1), fr7 - ldil 0, r22 ; FUNC_LDIL_OFFSET must point here - ldo 0(r22), r22 ; FUNC_LDO_OFFSET must point here - ldsid (0,r22), r4 - ldil 0, r1 ; SR4EXPORT_LDIL_OFFSET must point here - ldo 0(r1), r1 ; SR4EXPORT_LDO_OFFSET must point here - ldsid (0,r1), r20 - combt,=,n r4, r20, text_space ; If target is in data space, do a - ble 0(sr5, r22) ; "normal" procedure call - copy r31, r2 - break 4, 8 - mtsp r21, sr0 - ble,n 0(sr0, r22) - text_space ; Otherwise, go through _sr4export, - ble (sr4, r1) ; which will return back here. - stw r31,-24(r30) - break 4, 8 - mtsp r21, sr0 - ble,n 0(sr0, r22) - nop ; To avoid kernel bugs - nop ; and keep the dummy 8 byte aligned - - The dummy decides if the target is in text space or data space. If - it's in data space, there's no problem because the target can - return back to the dummy. However, if the target is in text space, - the dummy calls the secret, undocumented routine _sr4export, which - calls a function in text space and can return to any space. Instead - of including fake instructions to represent saved registers, we - know that the frame is associated with the call dummy and treat it - specially. - - The trailing NOPs are needed to avoid a bug in HPUX, BSD and OSF1 - kernels. If the memory at the location pointed to by the PC is - 0xffffffff then a ptrace step call will fail (even if the instruction - is nullified). - - The code to pop a dummy frame single steps three instructions - starting with the last mtsp. This includes the nullified "instruction" - following the ble (which is uninitialized junk). If the - "instruction" following the last BLE is 0xffffffff, then the ptrace - will fail and the dummy frame is not correctly popped. - - By placing a NOP in the delay slot of the BLE instruction we can be - sure that we never try to execute a 0xffffffff instruction and - avoid the kernel bug. The second NOP is needed to keep the call - dummy 8 byte aligned. */ - -#define CALL_DUMMY {0x4BDA3FB9, 0x4BD93FB1, 0x4BD83FA9, 0x4BD73FA1,\ - 0x37C13FB9, 0x24201004, 0x2C391005, 0x24311006,\ - 0x2C291007, 0x22C00000, 0x36D60000, 0x02C010A4,\ - 0x20200000, 0x34210000, 0x002010b4, 0x82842022,\ - 0xe6c06000, 0x081f0242, 0x00010004, 0x00151820,\ - 0xe6c00002, 0xe4202000, 0x6bdf3fd1, 0x00010004,\ - 0x00151820, 0xe6c00002, 0x08000240, 0x08000240} - #define REG_PARM_STACK_SPACE 16 -/* If we've reached a trap instruction within the call dummy, then - we'll consider that to mean that we've reached the call dummy's - end after its successful completion. */ -#define DEPRECATED_CALL_DUMMY_HAS_COMPLETED(pc, sp, frame_address) \ - (DEPRECATED_PC_IN_CALL_DUMMY((pc), (sp), (frame_address)) && \ - (read_memory_integer((pc), 4) == BREAKPOINT32)) - -/* Insert the specified number of args and function address into a - call sequence of the above form stored at DUMMYNAME. - - On the hppa we need to call the stack dummy through $$dyncall. - Therefore our version of DEPRECATED_FIX_CALL_DUMMY takes an extra - argument, real_pc, which is the location where gdb should start up - the inferior to do the function call. */ - -/* FIXME: brobecker 2002-12-26. This macro is going to cause us some - problems before we can go to multiarch partial as it has been - diverted on HPUX to return the value of the PC! */ -/* NOTE: cagney/2003-05-03: This has been replaced by push_dummy_code. - Hopefully that has all the parameters HP/UX needs. */ -#define DEPRECATED_FIX_CALL_DUMMY hppa_fix_call_dummy -extern CORE_ADDR hppa_fix_call_dummy (char *, CORE_ADDR, CORE_ADDR, int, - struct value **, struct type *, int); - #define GDB_TARGET_IS_HPPA /* diff --git a/gdb/config/pa/tm-hppa64.h b/gdb/config/pa/tm-hppa64.h index 62bcebc7423..79fd15cea1c 100644 --- a/gdb/config/pa/tm-hppa64.h +++ b/gdb/config/pa/tm-hppa64.h @@ -57,52 +57,6 @@ extern int hpread_adjust_stack_address (CORE_ADDR); /* jimb: omitted dynamic linking stuff here */ -/* This sequence of words is the instructions - -; Call stack frame has already been built by gdb. Since we could be calling -; a varargs function, and we do not have the benefit of a stub to put things in -; the right place, we load the first 8 word of arguments into both the general -; and fp registers. -call_dummy - nop - copy %r4,%r29 - copy %r5,%r22 - copy %r6,%r27 - fldd -64(0,%r29),%fr4 - fldd -56(0,%r29),%fr5 - fldd -48(0,%r29),%fr6 - fldd -40(0,%r29),%fr7 - fldd -32(0,%r29),%fr8 - fldd -24(0,%r29),%fr9 - fldd -16(0,%r29),%fr10 - fldd -8(0,%r29),%fr11 - copy %r22,%r1 - ldd -64(%r29), %r26 - ldd -56(%r29), %r25 - ldd -48(%r29), %r24 - ldd -40(%r29), %r23 - ldd -32(%r29), %r22 - ldd -24(%r29), %r21 - ldd -16(%r29), %r20 - bve,l (%r1),%r2 - ldd -8(%r29), %r19 - break 4, 8 - mtsp %r21, %sr0 - ble 0(%sr0, %r22) - nop -*/ - -/* Call dummys are sized and written out in word sized hunks. So we have - to pack the instructions into words. Ugh. */ -#undef CALL_DUMMY -#define CALL_DUMMY {0x08000240349d0000LL, 0x34b6000034db0000LL, \ - 0x53a43f8353a53f93LL, 0x53a63fa353a73fb3LL,\ - 0x53a83fc353a93fd3LL, 0x2fa1100a2fb1100bLL,\ - 0x36c1000053ba3f81LL, 0x53b93f9153b83fa1LL,\ - 0x53b73fb153b63fc1LL, 0x53b53fd10fa110d4LL,\ - 0xe820f0000fb110d3LL, 0x0001000400151820LL,\ - 0xe6c0000008000240LL} - /* The PA64 ABI reserves 64 bytes of stack space for outgoing register parameters. */ #undef REG_PARM_STACK_SPACE diff --git a/gdb/config/rs6000/tm-rs6000.h b/gdb/config/rs6000/tm-rs6000.h index 4b8a09dc3c2..4422fcbf3c8 100644 --- a/gdb/config/rs6000/tm-rs6000.h +++ b/gdb/config/rs6000/tm-rs6000.h @@ -74,12 +74,6 @@ extern void aix_process_linenos (void); #define FP0_REGNUM 32 /* Floating point register 0 */ #define FPLAST_REGNUM 63 /* Last floating point register */ -/* Define other aspects of the stack frame. */ - -#define DEPRECATED_INIT_FRAME_PC_FIRST(fromleaf, prev) \ - (fromleaf ? DEPRECATED_SAVED_PC_AFTER_CALL (prev->next) : \ - prev->next ? DEPRECATED_FRAME_SAVED_PC (prev->next) : read_pc ()) - /* Notice when a new child process is started. */ #define TARGET_CREATE_INFERIOR_HOOK rs6000_create_inferior diff --git a/gdb/cp-namespace.c b/gdb/cp-namespace.c index a731352c6e4..910289ff3ce 100644 --- a/gdb/cp-namespace.c +++ b/gdb/cp-namespace.c @@ -603,7 +603,7 @@ static struct type * cp_lookup_transparent_type_loop (const char *name, const char *scope, int length) { - int scope_length = cp_find_first_component (scope + length); + int scope_length = length + cp_find_first_component (scope + length); char *full_name; /* If the current scope is followed by "::", look in the next diff --git a/gdb/cris-tdep.c b/gdb/cris-tdep.c index 14bac098475..5ac40b02553 100644 --- a/gdb/cris-tdep.c +++ b/gdb/cris-tdep.c @@ -792,6 +792,14 @@ cris_scan_prologue (CORE_ADDR pc, struct frame_info *next_frame, info->leaf_function = 0; } } + else if (insn_next == 0x8FEE) + { + /* push $r8 */ + if (info) + { + info->r8_offset = info->sp_offset; + } + } } else if (insn == 0x866E) { @@ -799,7 +807,6 @@ cris_scan_prologue (CORE_ADDR pc, struct frame_info *next_frame, if (info) { info->uses_frame = 1; - info->r8_offset = info->sp_offset; } continue; } @@ -947,6 +954,8 @@ cris_scan_prologue (CORE_ADDR pc, struct frame_info *next_frame, frame_unwind_unsigned_register (next_frame, CRIS_FP_REGNUM, &this_base); info->base = this_base; + info->saved_regs[CRIS_FP_REGNUM].addr = info->base; + /* The FP points at the last saved register. Adjust the FP back to before the first saved register giving the SP. */ info->prev_sp = info->base + info->r8_offset; @@ -961,8 +970,6 @@ cris_scan_prologue (CORE_ADDR pc, struct frame_info *next_frame, info->prev_sp = info->base + info->size; } - info->saved_regs[CRIS_FP_REGNUM].addr = info->base; - /* Calculate the addresses for the saved registers on the stack. */ /* FIXME: The address calculation should really be done on the fly while we're analyzing the prologue (we only hold one regsave value as it is @@ -981,8 +988,17 @@ cris_scan_prologue (CORE_ADDR pc, struct frame_info *next_frame, if (!info->leaf_function) { - /* SRP saved on the stack. */ - info->saved_regs[SRP_REGNUM].addr = info->base + 4; + /* SRP saved on the stack. But where? */ + if (info->r8_offset == 0) + { + /* R8 not pushed yet. */ + info->saved_regs[SRP_REGNUM].addr = info->base; + } + else + { + /* R8 pushed, but SP may or may not be moved to R8 yet. */ + info->saved_regs[SRP_REGNUM].addr = info->base + 4; + } } /* The PC is found in SRP (the actual register or located on the stack). */ @@ -1340,6 +1356,28 @@ cris_extract_return_value (struct type *type, struct regcache *regcache, error ("cris_extract_return_value: type length too large"); } +/* Handle the CRIS return value convention. */ + +static enum return_value_convention +cris_return_value (struct gdbarch *gdbarch, struct type *type, + struct regcache *regcache, void *readbuf, + const void *writebuf) +{ + if (TYPE_CODE (type) == TYPE_CODE_STRUCT + || TYPE_CODE (type) == TYPE_CODE_UNION + || TYPE_LENGTH (type) > 8) + /* Structs, unions, and anything larger than 8 bytes (2 registers) + goes on the stack. */ + return RETURN_VALUE_STRUCT_CONVENTION; + + if (readbuf) + cris_extract_return_value (type, regcache, readbuf); + if (writebuf) + cris_store_return_value (type, regcache, writebuf); + + return RETURN_VALUE_REGISTER_CONVENTION; +} + /* Returns 1 if the given type will be passed by pointer rather than directly. */ @@ -3792,9 +3830,7 @@ cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) internal_error (__FILE__, __LINE__, "cris_gdbarch_init: unknown byte order in info"); } - /* FIXME: Should be replaced by a cris_return_value implementation. */ - set_gdbarch_store_return_value (gdbarch, cris_store_return_value); - set_gdbarch_extract_return_value (gdbarch, cris_extract_return_value); + set_gdbarch_return_value (gdbarch, cris_return_value); set_gdbarch_deprecated_reg_struct_has_addr (gdbarch, cris_reg_struct_has_addr); set_gdbarch_use_struct_convention (gdbarch, always_use_struct_convention); @@ -3883,8 +3919,6 @@ cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) set_gdbarch_breakpoint_from_pc (gdbarch, cris_breakpoint_from_pc); - /* Prologue analyzer may have to be able to parse an incomplete - prologue (PC in prologue, that is). Check infrun.c. */ set_gdbarch_unwind_pc (gdbarch, cris_unwind_pc); set_gdbarch_unwind_sp (gdbarch, cris_unwind_sp); set_gdbarch_unwind_dummy_id (gdbarch, cris_unwind_dummy_id); diff --git a/gdb/doc/ChangeLog b/gdb/doc/ChangeLog index 6fbd7662892..a92080e4148 100644 --- a/gdb/doc/ChangeLog +++ b/gdb/doc/ChangeLog @@ -1,3 +1,8 @@ +2004-03-09 Daniel Jacobowitz + + * gdb.texinfo (Debugging Output): Document values for "set debug + target". + 2004-02-28 Andrew Cagney * gdb.texinfo (Contributors): Mention GDB 6.1 release engineer. diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo index 77b96a067e3..dac02de0ef2 100644 --- a/gdb/doc/gdb.texinfo +++ b/gdb/doc/gdb.texinfo @@ -13434,7 +13434,9 @@ info. @item set debug target Turns on or off display of @value{GDBN} target debugging info. This info includes what is going on at the target level of GDB, as it happens. The -default is off. +default is 0. Set it to 1 to track events, and to 2 to also track the +value of large memory transfers. Changes to this flag do not take effect +until the next time you connect to a target or use the @code{run} command. @kindex show debug target @item show debug target Displays the current state of displaying @value{GDBN} target debugging diff --git a/gdb/dwarf2read.c b/gdb/dwarf2read.c index 46c3cf4ed7e..ffc76c85875 100644 --- a/gdb/dwarf2read.c +++ b/gdb/dwarf2read.c @@ -50,6 +50,20 @@ #include "gdb_assert.h" #include +/* A note on memory usage for this file. + + At the present time, this code reads the debug info sections into + the objfile's objfile_obstack. A definite improvement for startup + time, on platforms which do not emit relocations for debug + sections, would be to use mmap instead. The object's complete + debug information is loaded into memory, partly to simplify + absolute DIE references. + + Whether using obstacks or mmap, the sections should remain loaded + until the objfile is released, and pointers into the section data + can be used for any other data associated to the objfile (symbol + names, type names, location expressions to name a few). */ + #ifndef DWARF2_REG_TO_REGNUM #define DWARF2_REG_TO_REGNUM(REG) (REG) #endif @@ -205,10 +219,6 @@ struct comp_unit_head struct comp_unit_head *next; - /* DWARF abbreviation table associated with this compilation unit */ - - struct abbrev_info *dwarf2_abbrevs[ABBREV_HASH_SIZE]; - /* Base address of this compilation unit. */ CORE_ADDR base_address; @@ -227,8 +237,7 @@ struct dwarf2_cu /* The header of the compilation unit. FIXME drow/2003-11-10: Some of the things from the comp_unit_head - should be moved to the dwarf2_cu structure; for instance the abbrevs - hash table. */ + should logically be moved to the dwarf2_cu structure. */ struct comp_unit_head header; struct function_range *first_fn, *last_fn, *cached_fn; @@ -258,6 +267,12 @@ struct dwarf2_cu FT_NUM_MEMBERS compile time constant, which is the number of predefined fundamental types gdb knows how to construct. */ struct type *ftypes[FT_NUM_MEMBERS]; /* Fundamental types */ + + /* DWARF abbreviation table associated with this compilation unit. */ + struct abbrev_info **dwarf2_abbrevs; + + /* Storage for the abbrev table. */ + struct obstack abbrev_obstack; }; /* The line number information for a compilation unit (found in the @@ -329,8 +344,8 @@ struct abbrev_info { unsigned int number; /* number identifying abbrev */ enum dwarf_tag tag; /* dwarf tag */ - int has_children; /* boolean */ - unsigned int num_attrs; /* number of attributes */ + unsigned short has_children; /* boolean */ + unsigned short num_attrs; /* number of attributes */ struct attr_abbrev *attrs; /* an array of attribute descriptions */ struct abbrev_info *next; /* next in chain */ }; @@ -444,12 +459,11 @@ static int isreg; /* Object lives in register. /* We put a pointer to this structure in the read_symtab_private field of the psymtab. - The complete dwarf information for an objfile is kept in the - objfile_obstack, so that absolute die references can be handled. + Most of the information in this structure is related to an entire - object file and could be passed via the sym_private field of the objfile. - It is however conceivable that dwarf2 might not be the only type - of symbols read from an object file. */ + object file and could be passed via the sym_private field of the + objfile. It is possible to have both dwarf2 and some other form + of debug symbols in one object file. */ struct dwarf2_pinfo { @@ -673,7 +687,7 @@ char *dwarf2_read_section (struct objfile *, asection *); static void dwarf2_read_abbrevs (bfd *abfd, struct dwarf2_cu *cu); -static void dwarf2_empty_abbrev_table (void *); +static void dwarf2_free_abbrev_table (void *); static struct abbrev_info *dwarf2_lookup_abbrev (unsigned int, struct dwarf2_cu *); @@ -720,6 +734,8 @@ static unsigned long read_unsigned_leb128 (bfd *, char *, unsigned int *); static long read_signed_leb128 (bfd *, char *, unsigned int *); +static char *skip_leb128 (bfd *, char *); + static void set_cu_language (unsigned int, struct dwarf2_cu *); static struct attribute *dwarf2_attr (struct die_info *, unsigned int, @@ -905,7 +921,7 @@ static void dwarf2_free_tmp_obstack (void *); static struct dwarf_block *dwarf_alloc_block (void); -static struct abbrev_info *dwarf_alloc_abbrev (void); +static struct abbrev_info *dwarf_alloc_abbrev (struct dwarf2_cu *); static struct die_info *dwarf_alloc_die (void); @@ -923,6 +939,9 @@ static void dwarf2_symbol_mark_computed (struct attribute *attr, struct symbol *sym, struct dwarf2_cu *cu); +static char *skip_one_die (char *info_ptr, struct abbrev_info *abbrev, + struct dwarf2_cu *cu); + /* Try to locate the sections we need for DWARF 2 debugging information and return true if we have enough to do something. */ @@ -1201,6 +1220,7 @@ dwarf2_build_psymtabs_hard (struct objfile *objfile, int mainline) left at all should be sufficient. */ while (info_ptr < dwarf_info_buffer + dwarf_info_size) { + struct cleanup *back_to_inner; struct dwarf2_cu cu; beg_of_comp_unit = info_ptr; @@ -1238,7 +1258,7 @@ dwarf2_build_psymtabs_hard (struct objfile *objfile, int mainline) /* Read the abbrevs for this compilation unit into a table */ dwarf2_read_abbrevs (abfd, &cu); - make_cleanup (dwarf2_empty_abbrev_table, cu.header.dwarf2_abbrevs); + back_to_inner = make_cleanup (dwarf2_free_abbrev_table, &cu); /* Read the compilation unit die */ info_ptr = read_partial_die (&comp_unit_die, abfd, info_ptr, @@ -1315,6 +1335,8 @@ dwarf2_build_psymtabs_hard (struct objfile *objfile, int mainline) info_ptr = beg_of_comp_unit + cu.header.length + cu.header.initial_length_size; + + do_cleanups (back_to_inner); } do_cleanups (back_to); } @@ -1748,8 +1770,154 @@ add_partial_enumeration (struct partial_die_info *enum_pdi, char *info_ptr, return info_ptr; } -/* Locate ORIG_PDI's sibling; INFO_PTR should point to the next DIE - after ORIG_PDI. */ +/* Read the initial uleb128 in the die at INFO_PTR in compilation unit CU. + Return the corresponding abbrev, or NULL if the number is zero (indicating + an empty DIE). In either case *BYTES_READ will be set to the length of + the initial number. */ + +static struct abbrev_info * +peek_die_abbrev (char *info_ptr, int *bytes_read, struct dwarf2_cu *cu) +{ + bfd *abfd = cu->objfile->obfd; + unsigned int abbrev_number; + struct abbrev_info *abbrev; + + abbrev_number = read_unsigned_leb128 (abfd, info_ptr, bytes_read); + + if (abbrev_number == 0) + return NULL; + + abbrev = dwarf2_lookup_abbrev (abbrev_number, cu); + if (!abbrev) + { + error ("Dwarf Error: Could not find abbrev number %d [in module %s]", abbrev_number, + bfd_get_filename (abfd)); + } + + return abbrev; +} + +/* Scan the debug information for CU starting at INFO_PTR. Returns a + pointer to the end of a series of DIEs, terminated by an empty + DIE. Any children of the skipped DIEs will also be skipped. */ + +static char * +skip_children (char *info_ptr, struct dwarf2_cu *cu) +{ + struct abbrev_info *abbrev; + unsigned int bytes_read; + + while (1) + { + abbrev = peek_die_abbrev (info_ptr, &bytes_read, cu); + if (abbrev == NULL) + return info_ptr + bytes_read; + else + info_ptr = skip_one_die (info_ptr + bytes_read, abbrev, cu); + } +} + +/* Scan the debug information for CU starting at INFO_PTR. INFO_PTR + should point just after the initial uleb128 of a DIE, and the + abbrev corresponding to that skipped uleb128 should be passed in + ABBREV. Returns a pointer to this DIE's sibling, skipping any + children. */ + +static char * +skip_one_die (char *info_ptr, struct abbrev_info *abbrev, + struct dwarf2_cu *cu) +{ + unsigned int bytes_read; + struct attribute attr; + bfd *abfd = cu->objfile->obfd; + unsigned int form, i; + + for (i = 0; i < abbrev->num_attrs; i++) + { + /* The only abbrev we care about is DW_AT_sibling. */ + if (abbrev->attrs[i].name == DW_AT_sibling) + { + read_attribute (&attr, &abbrev->attrs[i], + abfd, info_ptr, cu); + if (attr.form == DW_FORM_ref_addr) + complaint (&symfile_complaints, "ignoring absolute DW_AT_sibling"); + else + return dwarf_info_buffer + dwarf2_get_ref_die_offset (&attr, cu); + } + + /* If it isn't DW_AT_sibling, skip this attribute. */ + form = abbrev->attrs[i].form; + skip_attribute: + switch (form) + { + case DW_FORM_addr: + case DW_FORM_ref_addr: + info_ptr += cu->header.addr_size; + break; + case DW_FORM_data1: + case DW_FORM_ref1: + case DW_FORM_flag: + info_ptr += 1; + break; + case DW_FORM_data2: + case DW_FORM_ref2: + info_ptr += 2; + break; + case DW_FORM_data4: + case DW_FORM_ref4: + info_ptr += 4; + break; + case DW_FORM_data8: + case DW_FORM_ref8: + info_ptr += 8; + break; + case DW_FORM_string: + read_string (abfd, info_ptr, &bytes_read); + info_ptr += bytes_read; + break; + case DW_FORM_strp: + info_ptr += cu->header.offset_size; + break; + case DW_FORM_block: + info_ptr += read_unsigned_leb128 (abfd, info_ptr, &bytes_read); + info_ptr += bytes_read; + break; + case DW_FORM_block1: + info_ptr += 1 + read_1_byte (abfd, info_ptr); + break; + case DW_FORM_block2: + info_ptr += 2 + read_2_bytes (abfd, info_ptr); + break; + case DW_FORM_block4: + info_ptr += 4 + read_4_bytes (abfd, info_ptr); + break; + case DW_FORM_sdata: + case DW_FORM_udata: + case DW_FORM_ref_udata: + info_ptr = skip_leb128 (abfd, info_ptr); + break; + case DW_FORM_indirect: + form = read_unsigned_leb128 (abfd, info_ptr, &bytes_read); + info_ptr += bytes_read; + /* We need to continue parsing from here, so just go back to + the top. */ + goto skip_attribute; + + default: + error ("Dwarf Error: Cannot handle %s in DWARF reader [in module %s]", + dwarf_form_name (form), + bfd_get_filename (abfd)); + } + } + + if (abbrev->has_children) + return skip_children (info_ptr, cu); + else + return info_ptr; +} + +/* Locate ORIG_PDI's sibling; INFO_PTR should point to the start of + the next DIE after ORIG_PDI. */ static char * locate_pdi_sibling (struct partial_die_info *orig_pdi, char *info_ptr, @@ -1765,21 +1933,9 @@ locate_pdi_sibling (struct partial_die_info *orig_pdi, char *info_ptr, if (!orig_pdi->has_children) return info_ptr; - /* Okay, we don't know the sibling, but we have children that we - want to skip. So read children until we run into one without a - tag; return whatever follows it. */ + /* Skip the children the long way. */ - while (1) - { - struct partial_die_info pdi; - - info_ptr = read_partial_die (&pdi, abfd, info_ptr, cu); - - if (pdi.tag == 0) - return info_ptr; - else - info_ptr = locate_pdi_sibling (&pdi, info_ptr, abfd, cu); - } + return skip_children (info_ptr, cu); } /* Expand this partial symbol table into a full symbol table. */ @@ -1861,7 +2017,7 @@ psymtab_to_symtab_1 (struct partial_symtab *pst) /* Read the abbrevs for this compilation unit */ dwarf2_read_abbrevs (abfd, &cu); - make_cleanup (dwarf2_empty_abbrev_table, cu.header.dwarf2_abbrevs); + make_cleanup (dwarf2_free_abbrev_table, &cu); cu.header.offset = offset; @@ -2664,8 +2820,10 @@ dwarf2_add_field (struct field_info *fip, struct die_info *die, attr = dwarf2_attr (die, DW_AT_name, cu); if (attr && DW_STRING (attr)) fieldname = DW_STRING (attr); - fp->name = obsavestring (fieldname, strlen (fieldname), - &objfile->objfile_obstack); + + /* The name is already allocated along with this objfile, so we don't + need to duplicate it for the type. */ + fp->name = fieldname; /* Change accessibility for artificial fields (e.g. virtual table pointer or virtual base class pointer) to private. */ @@ -2696,11 +2854,11 @@ dwarf2_add_field (struct field_info *fip, struct die_info *die, /* Get physical name. */ physname = dwarf2_linkage_name (die, cu); - SET_FIELD_PHYSNAME (*fp, obsavestring (physname, strlen (physname), - &objfile->objfile_obstack)); + /* The name is already allocated along with this objfile, so we don't + need to duplicate it for the type. */ + SET_FIELD_PHYSNAME (*fp, physname ? physname : ""); FIELD_TYPE (*fp) = die_type (die, cu); - FIELD_NAME (*fp) = obsavestring (fieldname, strlen (fieldname), - &objfile->objfile_obstack); + FIELD_NAME (*fp) = fieldname; } else if (die->tag == DW_TAG_inheritance) { @@ -2868,8 +3026,9 @@ dwarf2_add_member_fn (struct field_info *fip, struct die_info *die, /* Fill in the member function field info. */ fnp = &new_fnfield->fnfield; - fnp->physname = obsavestring (physname, strlen (physname), - &objfile->objfile_obstack); + /* The name is already allocated along with this objfile, so we don't + need to duplicate it for the type. */ + fnp->physname = physname ? physname : ""; fnp->type = alloc_type (objfile); if (die->type && TYPE_CODE (die->type) == TYPE_CODE_FUNC) { @@ -3000,7 +3159,7 @@ read_structure_scope (struct die_info *die, struct dwarf2_cu *cu) struct objfile *objfile = cu->objfile; struct type *type; struct attribute *attr; - const char *name = NULL; + char *name = NULL; const char *previous_prefix = processing_current_prefix; struct cleanup *back_to = NULL; /* This says whether or not we want to try to update the structure's @@ -3045,8 +3204,9 @@ read_structure_scope (struct die_info *die, struct dwarf2_cu *cu) } else { - TYPE_TAG_NAME (type) = obsavestring (name, strlen (name), - &objfile->objfile_obstack); + /* The name is already allocated along with this objfile, so + we don't need to duplicate it for the type. */ + TYPE_TAG_NAME (type) = name; need_to_update_name = (cu->language == language_cplus); } } @@ -3251,7 +3411,7 @@ read_enumeration (struct die_info *die, struct dwarf2_cu *cu) attr = dwarf2_attr (die, DW_AT_name, cu); if (attr && DW_STRING (attr)) { - const char *name = DW_STRING (attr); + char *name = DW_STRING (attr); if (processing_has_namespace_info) { @@ -3263,8 +3423,9 @@ read_enumeration (struct die_info *die, struct dwarf2_cu *cu) } else { - TYPE_TAG_NAME (type) = obsavestring (name, strlen (name), - &objfile->objfile_obstack); + /* The name is already allocated along with this objfile, so + we don't need to duplicate it for the type. */ + TYPE_TAG_NAME (type) = name; } } @@ -4170,19 +4331,28 @@ dwarf2_read_abbrevs (bfd *abfd, struct dwarf2_cu *cu) struct abbrev_info *cur_abbrev; unsigned int abbrev_number, bytes_read, abbrev_name; unsigned int abbrev_form, hash_number; + struct attr_abbrev *cur_attrs; + unsigned int allocated_attrs; /* Initialize dwarf2 abbrevs */ - memset (cu_header->dwarf2_abbrevs, 0, - ABBREV_HASH_SIZE*sizeof (struct abbrev_info *)); + obstack_init (&cu->abbrev_obstack); + cu->dwarf2_abbrevs = obstack_alloc (&cu->abbrev_obstack, + (ABBREV_HASH_SIZE + * sizeof (struct abbrev_info *))); + memset (cu->dwarf2_abbrevs, 0, + ABBREV_HASH_SIZE * sizeof (struct abbrev_info *)); abbrev_ptr = dwarf_abbrev_buffer + cu_header->abbrev_offset; abbrev_number = read_unsigned_leb128 (abfd, abbrev_ptr, &bytes_read); abbrev_ptr += bytes_read; + allocated_attrs = ATTR_ALLOC_CHUNK; + cur_attrs = xmalloc (allocated_attrs * sizeof (struct attr_abbrev)); + /* loop until we reach an abbrev number of 0 */ while (abbrev_number) { - cur_abbrev = dwarf_alloc_abbrev (); + cur_abbrev = dwarf_alloc_abbrev (cu); /* read in abbrev header */ cur_abbrev->number = abbrev_number; @@ -4198,24 +4368,30 @@ dwarf2_read_abbrevs (bfd *abfd, struct dwarf2_cu *cu) abbrev_ptr += bytes_read; while (abbrev_name) { - if ((cur_abbrev->num_attrs % ATTR_ALLOC_CHUNK) == 0) + if (cur_abbrev->num_attrs == allocated_attrs) { - cur_abbrev->attrs = (struct attr_abbrev *) - xrealloc (cur_abbrev->attrs, - (cur_abbrev->num_attrs + ATTR_ALLOC_CHUNK) - * sizeof (struct attr_abbrev)); + allocated_attrs += ATTR_ALLOC_CHUNK; + cur_attrs + = xrealloc (cur_attrs, (allocated_attrs + * sizeof (struct attr_abbrev))); } - cur_abbrev->attrs[cur_abbrev->num_attrs].name = abbrev_name; - cur_abbrev->attrs[cur_abbrev->num_attrs++].form = abbrev_form; + cur_attrs[cur_abbrev->num_attrs].name = abbrev_name; + cur_attrs[cur_abbrev->num_attrs++].form = abbrev_form; abbrev_name = read_unsigned_leb128 (abfd, abbrev_ptr, &bytes_read); abbrev_ptr += bytes_read; abbrev_form = read_unsigned_leb128 (abfd, abbrev_ptr, &bytes_read); abbrev_ptr += bytes_read; } + cur_abbrev->attrs = obstack_alloc (&cu->abbrev_obstack, + (cur_abbrev->num_attrs + * sizeof (struct attr_abbrev))); + memcpy (cur_abbrev->attrs, cur_attrs, + cur_abbrev->num_attrs * sizeof (struct attr_abbrev)); + hash_number = abbrev_number % ABBREV_HASH_SIZE; - cur_abbrev->next = cu_header->dwarf2_abbrevs[hash_number]; - cu_header->dwarf2_abbrevs[hash_number] = cur_abbrev; + cur_abbrev->next = cu->dwarf2_abbrevs[hash_number]; + cu->dwarf2_abbrevs[hash_number] = cur_abbrev; /* Get next abbreviation. Under Irix6 the abbreviations for a compilation unit are not @@ -4232,32 +4408,19 @@ dwarf2_read_abbrevs (bfd *abfd, struct dwarf2_cu *cu) if (dwarf2_lookup_abbrev (abbrev_number, cu) != NULL) break; } + + xfree (cur_attrs); } -/* Empty the abbrev table for a new compilation unit. */ +/* Release the memory used by the abbrev table for a compilation unit. */ static void -dwarf2_empty_abbrev_table (void *ptr_to_abbrevs_table) +dwarf2_free_abbrev_table (void *ptr_to_cu) { - int i; - struct abbrev_info *abbrev, *next; - struct abbrev_info **abbrevs; + struct dwarf2_cu *cu = ptr_to_cu; - abbrevs = (struct abbrev_info **)ptr_to_abbrevs_table; - - for (i = 0; i < ABBREV_HASH_SIZE; ++i) - { - next = NULL; - abbrev = abbrevs[i]; - while (abbrev) - { - next = abbrev->next; - xfree (abbrev->attrs); - xfree (abbrev); - abbrev = next; - } - abbrevs[i] = NULL; - } + obstack_free (&cu->abbrev_obstack, NULL); + cu->dwarf2_abbrevs = NULL; } /* Lookup an abbrev_info structure in the abbrev hash table. */ @@ -4265,12 +4428,11 @@ dwarf2_empty_abbrev_table (void *ptr_to_abbrevs_table) static struct abbrev_info * dwarf2_lookup_abbrev (unsigned int number, struct dwarf2_cu *cu) { - struct comp_unit_head *cu_header = &cu->header; unsigned int hash_number; struct abbrev_info *abbrev; hash_number = number % ABBREV_HASH_SIZE; - abbrev = cu_header->dwarf2_abbrevs[hash_number]; + abbrev = cu->dwarf2_abbrevs[hash_number]; while (abbrev) { @@ -4927,6 +5089,22 @@ read_signed_leb128 (bfd *abfd, char *buf, unsigned int *bytes_read_ptr) return result; } +/* Return a pointer to just past the end of an LEB128 number in BUF. */ + +static char * +skip_leb128 (bfd *abfd, char *buf) +{ + int byte; + + while (1) + { + byte = bfd_get_8 (abfd, (bfd_byte *) buf); + buf++; + if ((byte & 128) == 0) + return buf; + } +} + static void set_cu_language (unsigned int lang, struct dwarf2_cu *cu) { @@ -5677,11 +5855,11 @@ new_symbol (struct die_info *die, struct type *type, struct dwarf2_cu *cu) { /* FIXME: carlton/2003-11-10: Should this use SYMBOL_SET_NAMES instead? (The same problem also - arises a further down in the function.) */ - SYMBOL_LINKAGE_NAME (sym) - = obsavestring (TYPE_TAG_NAME (type), - strlen (TYPE_TAG_NAME (type)), - &objfile->objfile_obstack); + arises further down in this function.) */ + /* The type's name is already allocated along with + this objfile, so we don't need to duplicate it + for the symbol. */ + SYMBOL_LINKAGE_NAME (sym) = TYPE_TAG_NAME (type); } } @@ -5712,11 +5890,11 @@ new_symbol (struct die_info *die, struct type *type, struct dwarf2_cu *cu) sizeof (struct symbol)); *typedef_sym = *sym; SYMBOL_DOMAIN (typedef_sym) = VAR_DOMAIN; + /* The symbol's name is already allocated along with + this objfile, so we don't need to duplicate it for + the type. */ if (TYPE_NAME (SYMBOL_TYPE (sym)) == 0) - TYPE_NAME (SYMBOL_TYPE (sym)) = - obsavestring (SYMBOL_NATURAL_NAME (sym), - strlen (SYMBOL_NATURAL_NAME (sym)), - &objfile->objfile_obstack); + TYPE_NAME (SYMBOL_TYPE (sym)) = SYMBOL_NATURAL_NAME (sym); add_symbol_to_list (typedef_sym, list_to_add); } } @@ -7585,11 +7763,12 @@ dwarf_alloc_block (void) } static struct abbrev_info * -dwarf_alloc_abbrev (void) +dwarf_alloc_abbrev (struct dwarf2_cu *cu) { struct abbrev_info *abbrev; - abbrev = (struct abbrev_info *) xmalloc (sizeof (struct abbrev_info)); + abbrev = (struct abbrev_info *) + obstack_alloc (&cu->abbrev_obstack, sizeof (struct abbrev_info)); memset (abbrev, 0, sizeof (struct abbrev_info)); return (abbrev); } diff --git a/gdb/gdbserver/ChangeLog b/gdb/gdbserver/ChangeLog index 156036087ec..8baf82e9f6e 100644 --- a/gdb/gdbserver/ChangeLog +++ b/gdb/gdbserver/ChangeLog @@ -1,3 +1,25 @@ +2004-03-04 Nathan J. Williams + + * server.c (main): Print child status or termination signal from + variable 'signal', not 'sig'. + +2004-03-04 Nathan J. Williams + + * linux-low.c (linux_read_memory): Change return type to + int. Check for and return error from ptrace(). + * target.c (read_inferior_memory): Change return type to int. Pass + back return status from the_target->read_memory(). + * target.h (struct target_ops): Adapt *read_memory() prototype. + Update comment. + (read_inferior_memory): Adapt prototype. + * server.c (main): Return an error packet if + read_inferior_memory() returns an error. + +2004-03-04 Daniel Jacobowitz + + * Makefile.in (distclean): Remove config.h, stamp-h, and config.log. + Unify with other clean targets. + 2004-02-29 Daniel Jacobowitz * server.c (handle_v_cont): Call set_desired_inferior. diff --git a/gdb/gdbserver/Makefile.in b/gdb/gdbserver/Makefile.in index 8554dae9afb..3af7eb46180 100644 --- a/gdb/gdbserver/Makefile.in +++ b/gdb/gdbserver/Makefile.in @@ -1,5 +1,5 @@ # Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, -# 1999, 2000, 2001, 2002 Free Software Foundation, Inc. +# 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. # This file is part of GDB. @@ -200,12 +200,8 @@ clean: rm -f reg-arm.c reg-i386.c reg-ia64.c reg-m68k.c reg-mips.c rm -f reg-ppc.c reg-sh.c reg-x86-64.c reg-i386-linux.c -distclean: clean - rm -f nm.h tm.h xm.h config.status - rm -f Makefile - -maintainer-clean realclean: clean - rm -f nm.h tm.h xm.h config.status +maintainer-clean realclean distclean: clean + rm -f nm.h tm.h xm.h config.status config.h stamp-h config.log rm -f Makefile STAGESTUFF=${OBS} ${TSOBS} ${NTSOBS} ${ADD_FILES} init.c init.o version.c gdb diff --git a/gdb/gdbserver/linux-low.c b/gdb/gdbserver/linux-low.c index ea155160e36..69b35c1032b 100644 --- a/gdb/gdbserver/linux-low.c +++ b/gdb/gdbserver/linux-low.c @@ -1281,7 +1281,7 @@ linux_store_registers (int regno) /* Copy LEN bytes from inferior's memory starting at MEMADDR to debugger memory starting at MYADDR. */ -static void +static int linux_read_memory (CORE_ADDR memaddr, char *myaddr, int len) { register int i; @@ -1298,11 +1298,16 @@ linux_read_memory (CORE_ADDR memaddr, char *myaddr, int len) /* Read all the longwords */ for (i = 0; i < count; i++, addr += sizeof (PTRACE_XFER_TYPE)) { + errno = 0; buffer[i] = ptrace (PTRACE_PEEKTEXT, inferior_pid, (PTRACE_ARG3_TYPE) addr, 0); + if (errno) + return errno; } /* Copy appropriate bytes out of the buffer. */ memcpy (myaddr, (char *) buffer + (memaddr & (sizeof (PTRACE_XFER_TYPE) - 1)), len); + + return 0; } /* Copy LEN bytes of data from debugger memory at MYADDR diff --git a/gdb/gdbserver/server.c b/gdb/gdbserver/server.c index fb667ef5e87..93e3ea431bb 100644 --- a/gdb/gdbserver/server.c +++ b/gdb/gdbserver/server.c @@ -462,8 +462,10 @@ main (int argc, char *argv[]) break; case 'm': decode_m_packet (&own_buf[1], &mem_addr, &len); - read_inferior_memory (mem_addr, mem_buf, len); - convert_int_to_ascii (mem_buf, own_buf, len); + if (read_inferior_memory (mem_addr, mem_buf, len) == 0) + convert_int_to_ascii (mem_buf, own_buf, len); + else + write_enn (own_buf); break; case 'M': decode_M_packet (&own_buf[1], &mem_addr, &len, mem_buf); @@ -571,9 +573,10 @@ main (int argc, char *argv[]) if (status == 'W') fprintf (stderr, - "\nChild exited with status %d\n", sig); + "\nChild exited with status %d\n", signal); if (status == 'X') - fprintf (stderr, "\nChild terminated with signal = 0x%x\n", sig); + fprintf (stderr, "\nChild terminated with signal = 0x%x\n", + signal); if (status == 'W' || status == 'X') { if (extended_protocol) diff --git a/gdb/gdbserver/target.c b/gdb/gdbserver/target.c index 1c2860a11e9..2c60e1777da 100644 --- a/gdb/gdbserver/target.c +++ b/gdb/gdbserver/target.c @@ -1,5 +1,5 @@ /* Target operations for the remote server for GDB. - Copyright 2002 + Copyright 2002, 2004 Free Software Foundation, Inc. Contributed by MontaVista Software. @@ -57,11 +57,13 @@ set_desired_inferior (int use_general) current_inferior = found; } -void +int read_inferior_memory (CORE_ADDR memaddr, char *myaddr, int len) { - (*the_target->read_memory) (memaddr, myaddr, len); + int res; + res = (*the_target->read_memory) (memaddr, myaddr, len); check_mem_read (memaddr, myaddr, len); + return res; } int diff --git a/gdb/gdbserver/target.h b/gdb/gdbserver/target.h index 88ff2d482d3..770ffcbbb05 100644 --- a/gdb/gdbserver/target.h +++ b/gdb/gdbserver/target.h @@ -102,9 +102,11 @@ struct target_ops /* Read memory from the inferior process. This should generally be called through read_inferior_memory, which handles breakpoint shadowing. - Read LEN bytes at MEMADDR into a buffer at MYADDR. */ + Read LEN bytes at MEMADDR into a buffer at MYADDR. + + Returns 0 on success and errno on failure. */ - void (*read_memory) (CORE_ADDR memaddr, char *myaddr, int len); + int (*read_memory) (CORE_ADDR memaddr, char *myaddr, int len); /* Write memory to the inferior process. This should generally be called through write_inferior_memory, which handles breakpoint shadowing. @@ -160,7 +162,7 @@ void set_target_ops (struct target_ops *); unsigned char mywait (char *statusp, int connected_wait); -void read_inferior_memory (CORE_ADDR memaddr, char *myaddr, int len); +int read_inferior_memory (CORE_ADDR memaddr, char *myaddr, int len); int write_inferior_memory (CORE_ADDR memaddr, const char *myaddr, int len); diff --git a/gdb/gdbtypes.c b/gdb/gdbtypes.c index 2dc3a46e07b..1349ffbbe19 100644 --- a/gdb/gdbtypes.c +++ b/gdb/gdbtypes.c @@ -1343,6 +1343,12 @@ get_destructor_fn_field (struct type *t, int *method_indexp, int *field_indexp) return 0; } +static void +stub_noname_complaint (void) +{ + complaint (&symfile_complaints, "stub type has NULL name"); +} + /* Added by Bryan Boreham, Kewill, Sun Sep 17 18:07:17 1989. If this is a stubbed struct (i.e. declared as struct foo *), see if @@ -1356,11 +1362,10 @@ get_destructor_fn_field (struct type *t, int *method_indexp, int *field_indexp) This used to be coded as a macro, but I don't think it is called often enough to merit such treatment. */ -static void -stub_noname_complaint (void) -{ - complaint (&symfile_complaints, "stub type has NULL name"); -} +/* Find the real type of TYPE. This function returns the real type, after + removing all layers of typedefs and completing opaque or stub types. + Completion changes the TYPE argument, but stripping of typedefs does + not. */ struct type * check_typedef (struct type *type) diff --git a/gdb/hppa-tdep.c b/gdb/hppa-tdep.c index ccbdcba21c8..f96a21132d1 100644 --- a/gdb/hppa-tdep.c +++ b/gdb/hppa-tdep.c @@ -76,26 +76,12 @@ static const int hppa32_num_regs = 128; static const int hppa64_num_regs = 96; -static const int hppa64_call_dummy_breakpoint_offset = 22 * 4; - -/* DEPRECATED_CALL_DUMMY_LENGTH is computed based on the size of a - word on the target machine, not the size of an instruction. Since - a word on this target holds two instructions we have to divide the - instruction size by two to get the word size of the dummy. */ -static const int hppa32_call_dummy_length = INSTRUCTION_SIZE * 28; -static const int hppa64_call_dummy_length = INSTRUCTION_SIZE * 26 / 2; - /* Get at various relevent fields of an instruction word. */ #define MASK_5 0x1f #define MASK_11 0x7ff #define MASK_14 0x3fff #define MASK_21 0x1fffff -/* Define offsets into the call dummy for the target function address. - See comments related to CALL_DUMMY for more info. */ -#define FUNC_LDIL_OFFSET (INSTRUCTION_SIZE * 9) -#define FUNC_LDO_OFFSET (INSTRUCTION_SIZE * 10) - /* Define offsets into the call dummy for the _sr4export address. See comments related to CALL_DUMMY for more info. */ #define SR4EXPORT_LDIL_OFFSET (INSTRUCTION_SIZE * 12) @@ -118,24 +104,12 @@ static unsigned extract_5R_store (unsigned int); static unsigned extract_5r_store (unsigned int); -static void hppa_frame_init_saved_regs (struct frame_info *frame); - -static void find_dummy_frame_regs (struct frame_info *, CORE_ADDR *); - -static int find_proc_framesize (CORE_ADDR); - -static int find_return_regnum (CORE_ADDR); - struct unwind_table_entry *find_unwind_entry (CORE_ADDR); static int extract_17 (unsigned int); -static unsigned deposit_21 (unsigned int, unsigned int); - static int extract_21 (unsigned); -static unsigned deposit_14 (int, unsigned int); - static int extract_14 (unsigned); static void unwind_command (char *, int); @@ -144,8 +118,6 @@ static int low_sign_extend (unsigned int, unsigned int); static int sign_extend (unsigned int, unsigned int); -static int restore_pc_queue (CORE_ADDR *); - static int hppa_alignof (struct type *); static int prologue_inst_adjust_sp (unsigned long); @@ -156,10 +128,6 @@ static int inst_saves_gr (unsigned long); static int inst_saves_fr (unsigned long); -static int pc_in_interrupt_handler (CORE_ADDR); - -static int pc_in_linker_stub (CORE_ADDR); - static int compare_unwind_entries (const void *, const void *); static void read_unwind_info (struct objfile *); @@ -168,11 +136,6 @@ static void internalize_unwinds (struct objfile *, struct unwind_table_entry *, asection *, unsigned int, unsigned int, CORE_ADDR); -static void pa_print_registers (char *, int, int); -static void pa_strcat_registers (char *, int, int, struct ui_file *); -static void pa_register_look_aside (char *, int, long *); -static void pa_print_fp_reg (int); -static void pa_strcat_fp_reg (int, struct ui_file *, enum precision_type); static void record_text_segment_lowaddr (bfd *, asection *, void *); /* FIXME: brobecker 2002-11-07: We will likely be able to make the following functions static, once we hppa is partially multiarched. */ @@ -181,39 +144,13 @@ CORE_ADDR hppa_skip_prologue (CORE_ADDR pc); CORE_ADDR hppa_skip_trampoline_code (CORE_ADDR pc); int hppa_in_solib_call_trampoline (CORE_ADDR pc, char *name); int hppa_in_solib_return_trampoline (CORE_ADDR pc, char *name); -CORE_ADDR hppa_saved_pc_after_call (struct frame_info *frame); int hppa_inner_than (CORE_ADDR lhs, CORE_ADDR rhs); -CORE_ADDR hppa64_stack_align (CORE_ADDR sp); int hppa_pc_requires_run_before_use (CORE_ADDR pc); int hppa_instruction_nullified (void); -int hppa_register_raw_size (int reg_nr); -int hppa_register_byte (int reg_nr); -struct type * hppa32_register_virtual_type (int reg_nr); -struct type * hppa64_register_virtual_type (int reg_nr); -void hppa_store_struct_return (CORE_ADDR addr, CORE_ADDR sp); -void hppa64_extract_return_value (struct type *type, char *regbuf, - char *valbuf); -int hppa64_use_struct_convention (int gcc_p, struct type *type); -void hppa64_store_return_value (struct type *type, char *valbuf); int hppa_cannot_store_register (int regnum); -void hppa_init_extra_frame_info (int fromleaf, struct frame_info *frame); -CORE_ADDR hppa_frame_chain (struct frame_info *frame); -int hppa_frame_chain_valid (CORE_ADDR chain, struct frame_info *thisframe); -int hppa_frameless_function_invocation (struct frame_info *frame); -CORE_ADDR hppa_frame_saved_pc (struct frame_info *frame); -CORE_ADDR hppa_frame_args_address (struct frame_info *fi); -int hppa_frame_num_args (struct frame_info *frame); -void hppa_push_dummy_frame (void); -void hppa_pop_frame (void); -CORE_ADDR hppa_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, - int nargs, struct value **args, - struct type *type, int gcc_p); -CORE_ADDR hppa_push_arguments (int nargs, struct value **args, CORE_ADDR sp, - int struct_return, CORE_ADDR struct_addr); CORE_ADDR hppa_smash_text_address (CORE_ADDR addr); CORE_ADDR hppa_target_read_pc (ptid_t ptid); void hppa_target_write_pc (CORE_ADDR v, ptid_t ptid); -CORE_ADDR hppa_target_read_fp (void); typedef struct { @@ -233,15 +170,6 @@ extern int hp_som_som_object_present; /* In breakpoint.c */ extern int exception_catchpoints_are_fragile; -/* Should call_function allocate stack space for a struct return? */ - -int -hppa64_use_struct_convention (int gcc_p, struct type *type) -{ - /* RM: struct upto 128 bits are returned in registers */ - return TYPE_LENGTH (type) > 16; -} - /* Handle 32/64-bit struct return conventions. */ static enum return_value_convention @@ -303,7 +231,8 @@ hppa64_return_value (struct gdbarch *gdbarch, are in r28, padded on the left. Aggregates less that 65 bits are in r28, right padded. Aggregates upto 128 bits are in r28 and r29, right padded. */ - if (TYPE_CODE (type) == TYPE_CODE_FLT) + if (TYPE_CODE (type) == TYPE_CODE_FLT + && TYPE_LENGTH (type) <= 8) { /* Floats are right aligned? */ int offset = register_size (gdbarch, FP4_REGNUM) - TYPE_LENGTH (type); @@ -333,15 +262,15 @@ hppa64_return_value (struct gdbarch *gdbarch, int b; for (b = 0; b < TYPE_LENGTH (type); b += 8) { - int part = (TYPE_LENGTH (type) - b - 1) % 8 + 1; + int part = min (8, TYPE_LENGTH (type) - b); if (readbuf != NULL) - regcache_cooked_read_part (regcache, 28, 0, part, + regcache_cooked_read_part (regcache, 28 + b / 8, 0, part, (char *) readbuf + b); if (writebuf != NULL) - regcache_cooked_write_part (regcache, 28, 0, part, + regcache_cooked_write_part (regcache, 28 + b / 8, 0, part, (const char *) writebuf + b); } - return RETURN_VALUE_REGISTER_CONVENTION; + return RETURN_VALUE_REGISTER_CONVENTION; } else return RETURN_VALUE_STRUCT_CONVENTION; @@ -408,16 +337,6 @@ extract_14 (unsigned word) return low_sign_extend (word & MASK_14, 14); } -/* deposit a 14 bit constant in a word */ - -static unsigned -deposit_14 (int opnd, unsigned word) -{ - unsigned sign = (opnd < 0 ? 1 : 0); - - return word | ((unsigned) opnd << 1 & MASK_14) | sign; -} - /* extract a 21 bit constant */ static int @@ -439,27 +358,6 @@ extract_21 (unsigned word) return sign_extend (val, 21) << 11; } -/* deposit a 21 bit constant in a word. Although 21 bit constants are - usually the top 21 bits of a 32 bit constant, we assume that only - the low 21 bits of opnd are relevant */ - -static unsigned -deposit_21 (unsigned opnd, unsigned word) -{ - unsigned val = 0; - - val |= get_field (opnd, 11 + 14, 11 + 18); - val <<= 2; - val |= get_field (opnd, 11 + 12, 11 + 13); - val <<= 2; - val |= get_field (opnd, 11 + 19, 11 + 20); - val <<= 11; - val |= get_field (opnd, 11 + 1, 11 + 11); - val <<= 1; - val |= get_field (opnd, 11 + 0, 11 + 0); - return word | val; -} - /* extract a 17 bit constant from branch instructions, returning the 19 bit signed value. */ @@ -902,2490 +800,426 @@ hpread_adjust_stack_address (CORE_ADDR func_addr) return u->Total_frame_size << 3; } -/* Called to determine if PC is in an interrupt handler of some - kind. */ - -static int -pc_in_interrupt_handler (CORE_ADDR pc) -{ - struct unwind_table_entry *u; - struct minimal_symbol *msym_us; - - u = find_unwind_entry (pc); - if (!u) - return 0; - - /* Oh joys. HPUX sets the interrupt bit for _sigreturn even though - its frame isn't a pure interrupt frame. Deal with this. */ - msym_us = lookup_minimal_symbol_by_pc (pc); - - return (u->HP_UX_interrupt_marker - && !PC_IN_SIGTRAMP (pc, DEPRECATED_SYMBOL_NAME (msym_us))); -} - -/* Called when no unwind descriptor was found for PC. Returns 1 if it - appears that PC is in a linker stub. +/* This function pushes a stack frame with arguments as part of the + inferior function calling mechanism. - ?!? Need to handle stubs which appear in PA64 code. */ + This is the version of the function for the 32-bit PA machines, in + which later arguments appear at lower addresses. (The stack always + grows towards higher addresses.) -static int -pc_in_linker_stub (CORE_ADDR pc) + We simply allocate the appropriate amount of stack space and put + arguments into their proper slots. */ + +CORE_ADDR +hppa32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, + struct regcache *regcache, CORE_ADDR bp_addr, + int nargs, struct value **args, CORE_ADDR sp, + int struct_return, CORE_ADDR struct_addr) { - int found_magic_instruction = 0; - int i; - char buf[4]; - - /* If unable to read memory, assume pc is not in a linker stub. */ - if (target_read_memory (pc, buf, 4) != 0) - return 0; - - /* We are looking for something like + /* NOTE: cagney/2004-02-27: This is a guess - its implemented by + reverse engineering testsuite failures. */ - ; $$dyncall jams RP into this special spot in the frame (RP') - ; before calling the "call stub" - ldw -18(sp),rp + /* Stack base address at which any pass-by-reference parameters are + stored. */ + CORE_ADDR struct_end = 0; + /* Stack base address at which the first parameter is stored. */ + CORE_ADDR param_end = 0; - ldsid (rp),r1 ; Get space associated with RP into r1 - mtsp r1,sp ; Move it into space register 0 - be,n 0(sr0),rp) ; back to your regularly scheduled program */ + /* The inner most end of the stack after all the parameters have + been pushed. */ + CORE_ADDR new_sp = 0; - /* Maximum known linker stub size is 4 instructions. Search forward - from the given PC, then backward. */ - for (i = 0; i < 4; i++) + /* Two passes. First pass computes the location of everything, + second pass writes the bytes out. */ + int write_pass; + for (write_pass = 0; write_pass < 2; write_pass++) { - /* If we hit something with an unwind, stop searching this direction. */ - - if (find_unwind_entry (pc + i * 4) != 0) - break; - - /* Check for ldsid (rp),r1 which is the magic instruction for a - return from a cross-space function call. */ - if (read_memory_integer (pc + i * 4, 4) == 0x004010a1) + CORE_ADDR struct_ptr = 0; + CORE_ADDR param_ptr = 0; + int reg = 27; /* NOTE: Registers go down. */ + int i; + for (i = 0; i < nargs; i++) { - found_magic_instruction = 1; - break; + struct value *arg = args[i]; + struct type *type = check_typedef (VALUE_TYPE (arg)); + /* The corresponding parameter that is pushed onto the + stack, and [possibly] passed in a register. */ + char param_val[8]; + int param_len; + memset (param_val, 0, sizeof param_val); + if (TYPE_LENGTH (type) > 8) + { + /* Large parameter, pass by reference. Store the value + in "struct" area and then pass its address. */ + param_len = 4; + struct_ptr += align_up (TYPE_LENGTH (type), 8); + if (write_pass) + write_memory (struct_end - struct_ptr, VALUE_CONTENTS (arg), + TYPE_LENGTH (type)); + store_unsigned_integer (param_val, 4, struct_end - struct_ptr); + } + else if (TYPE_CODE (type) == TYPE_CODE_INT + || TYPE_CODE (type) == TYPE_CODE_ENUM) + { + /* Integer value store, right aligned. "unpack_long" + takes care of any sign-extension problems. */ + param_len = align_up (TYPE_LENGTH (type), 4); + store_unsigned_integer (param_val, param_len, + unpack_long (type, + VALUE_CONTENTS (arg))); + } + else + { + /* Small struct value, store right aligned? */ + param_len = align_up (TYPE_LENGTH (type), 4); + memcpy (param_val + param_len - TYPE_LENGTH (type), + VALUE_CONTENTS (arg), TYPE_LENGTH (type)); + } + param_ptr += param_len; + reg -= param_len / 4; + if (write_pass) + { + write_memory (param_end - param_ptr, param_val, param_len); + if (reg >= 23) + { + regcache_cooked_write (regcache, reg, param_val); + if (param_len > 4) + regcache_cooked_write (regcache, reg + 1, param_val + 4); + } + } } - /* Add code to handle long call/branch and argument relocation stubs - here. */ - } - - if (found_magic_instruction != 0) - return 1; - - /* Now look backward. */ - for (i = 0; i < 4; i++) - { - /* If we hit something with an unwind, stop searching this direction. */ - - if (find_unwind_entry (pc - i * 4) != 0) - break; - /* Check for ldsid (rp),r1 which is the magic instruction for a - return from a cross-space function call. */ - if (read_memory_integer (pc - i * 4, 4) == 0x004010a1) + /* Update the various stack pointers. */ + if (!write_pass) { - found_magic_instruction = 1; - break; + struct_end = sp + struct_ptr; + /* PARAM_PTR already accounts for all the arguments passed + by the user. However, the ABI mandates minimum stack + space allocations for outgoing arguments. The ABI also + mandates minimum stack alignments which we must + preserve. */ + param_end = struct_end + max (align_up (param_ptr, 8), + REG_PARM_STACK_SPACE); } - /* Add code to handle long call/branch and argument relocation stubs - here. */ } - return found_magic_instruction; -} -static int -find_return_regnum (CORE_ADDR pc) -{ - struct unwind_table_entry *u; + /* If a structure has to be returned, set up register 28 to hold its + address */ + if (struct_return) + write_register (28, struct_addr); - u = find_unwind_entry (pc); + /* Set the return address. */ + regcache_cooked_write_unsigned (regcache, RP_REGNUM, bp_addr); - if (!u) - return RP_REGNUM; + /* The stack will have 32 bytes of additional space for a frame marker. */ + return param_end + 32; +} - if (u->Millicode) - return 31; +/* This function pushes a stack frame with arguments as part of the + inferior function calling mechanism. - return RP_REGNUM; -} + This is the version for the PA64, in which later arguments appear + at higher addresses. (The stack always grows towards higher + addresses.) -/* Return size of frame, or -1 if we should use a frame pointer. */ -static int -find_proc_framesize (CORE_ADDR pc) + We simply allocate the appropriate amount of stack space and put + arguments into their proper slots. + + This ABI also requires that the caller provide an argument pointer + to the callee, so we do that too. */ + +CORE_ADDR +hppa64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, + struct regcache *regcache, CORE_ADDR bp_addr, + int nargs, struct value **args, CORE_ADDR sp, + int struct_return, CORE_ADDR struct_addr) { - struct unwind_table_entry *u; - struct minimal_symbol *msym_us; + /* NOTE: cagney/2004-02-27: This is a guess - its implemented by + reverse engineering testsuite failures. */ - /* This may indicate a bug in our callers... */ - if (pc == (CORE_ADDR) 0) - return -1; + /* Stack base address at which any pass-by-reference parameters are + stored. */ + CORE_ADDR struct_end = 0; + /* Stack base address at which the first parameter is stored. */ + CORE_ADDR param_end = 0; - u = find_unwind_entry (pc); + /* The inner most end of the stack after all the parameters have + been pushed. */ + CORE_ADDR new_sp = 0; - if (!u) + /* Two passes. First pass computes the location of everything, + second pass writes the bytes out. */ + int write_pass; + for (write_pass = 0; write_pass < 2; write_pass++) { - if (pc_in_linker_stub (pc)) - /* Linker stubs have a zero size frame. */ - return 0; - else - return -1; + CORE_ADDR struct_ptr = 0; + CORE_ADDR param_ptr = 0; + int i; + for (i = 0; i < nargs; i++) + { + struct value *arg = args[i]; + struct type *type = check_typedef (VALUE_TYPE (arg)); + if ((TYPE_CODE (type) == TYPE_CODE_INT + || TYPE_CODE (type) == TYPE_CODE_ENUM) + && TYPE_LENGTH (type) <= 8) + { + /* Integer value store, right aligned. "unpack_long" + takes care of any sign-extension problems. */ + param_ptr += 8; + if (write_pass) + { + ULONGEST val = unpack_long (type, VALUE_CONTENTS (arg)); + int reg = 27 - param_ptr / 8; + write_memory_unsigned_integer (param_end - param_ptr, + val, 8); + if (reg >= 19) + regcache_cooked_write_unsigned (regcache, reg, val); + } + } + else + { + /* Small struct value, store left aligned? */ + int reg; + if (TYPE_LENGTH (type) > 8) + { + param_ptr = align_up (param_ptr, 16); + reg = 26 - param_ptr / 8; + param_ptr += align_up (TYPE_LENGTH (type), 16); + } + else + { + param_ptr = align_up (param_ptr, 8); + reg = 26 - param_ptr / 8; + param_ptr += align_up (TYPE_LENGTH (type), 8); + } + if (write_pass) + { + int byte; + write_memory (param_end - param_ptr, VALUE_CONTENTS (arg), + TYPE_LENGTH (type)); + for (byte = 0; byte < TYPE_LENGTH (type); byte += 8) + { + if (reg >= 19) + { + int len = min (8, TYPE_LENGTH (type) - byte); + regcache_cooked_write_part (regcache, reg, 0, len, + VALUE_CONTENTS (arg) + byte); + } + reg--; + } + } + } + } + /* Update the various stack pointers. */ + if (!write_pass) + { + struct_end = sp + struct_ptr; + /* PARAM_PTR already accounts for all the arguments passed + by the user. However, the ABI mandates minimum stack + space allocations for outgoing arguments. The ABI also + mandates minimum stack alignments which we must + preserve. */ + param_end = struct_end + max (align_up (param_ptr, 16), + REG_PARM_STACK_SPACE); + } } - msym_us = lookup_minimal_symbol_by_pc (pc); + /* If a structure has to be returned, set up register 28 to hold its + address */ + if (struct_return) + write_register (28, struct_addr); - /* If Save_SP is set, and we're not in an interrupt or signal caller, - then we have a frame pointer. Use it. */ - if (u->Save_SP - && !pc_in_interrupt_handler (pc) - && msym_us - && !PC_IN_SIGTRAMP (pc, DEPRECATED_SYMBOL_NAME (msym_us))) - return -1; + /* Set the return address. */ + regcache_cooked_write_unsigned (regcache, RP_REGNUM, bp_addr); - return u->Total_frame_size << 3; + /* The stack will have 32 bytes of additional space for a frame marker. */ + return param_end + 64; } -/* Return offset from sp at which rp is saved, or 0 if not saved. */ -static int rp_saved (CORE_ADDR); - -static int -rp_saved (CORE_ADDR pc) -{ - struct unwind_table_entry *u; - - /* A function at, and thus a return PC from, address 0? Not in HP-UX! */ - if (pc == (CORE_ADDR) 0) - return 0; - - u = find_unwind_entry (pc); - - if (!u) - { - if (pc_in_linker_stub (pc)) - /* This is the so-called RP'. */ - return -24; - else - return 0; - } - - if (u->Save_RP) - return (TARGET_PTR_BIT == 64 ? -16 : -20); - else if (u->stub_unwind.stub_type != 0) - { - switch (u->stub_unwind.stub_type) - { - case EXPORT: - case IMPORT: - return -24; - case PARAMETER_RELOCATION: - return -8; - default: - return 0; - } - } - else - return 0; -} - -int -hppa_frameless_function_invocation (struct frame_info *frame) +static CORE_ADDR +hppa32_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) { - struct unwind_table_entry *u; - - u = find_unwind_entry (get_frame_pc (frame)); - - if (u == 0) - return 0; - - return (u->Total_frame_size == 0 && u->stub_unwind.stub_type == 0); + /* HP frames are 64-byte (or cache line) aligned (yes that's _byte_ + and not _bit_)! */ + return align_up (addr, 64); } -/* Immediately after a function call, return the saved pc. - Can't go through the frames for this because on some machines - the new frame is not set up until the new function executes - some instructions. */ - -CORE_ADDR -hppa_saved_pc_after_call (struct frame_info *frame) -{ - int ret_regnum; - CORE_ADDR pc; - struct unwind_table_entry *u; - - ret_regnum = find_return_regnum (get_frame_pc (frame)); - pc = read_register (ret_regnum) & ~0x3; +/* Force all frames to 16-byte alignment. Better safe than sorry. */ - /* If PC is in a linker stub, then we need to dig the address - the stub will return to out of the stack. */ - u = find_unwind_entry (pc); - if (u && u->stub_unwind.stub_type != 0) - return DEPRECATED_FRAME_SAVED_PC (frame); - else - return pc; -} - -CORE_ADDR -hppa_frame_saved_pc (struct frame_info *frame) +static CORE_ADDR +hppa64_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) { - CORE_ADDR pc = get_frame_pc (frame); - struct unwind_table_entry *u; - CORE_ADDR old_pc = 0; - int spun_around_loop = 0; - int rp_offset = 0; - - /* BSD, HPUX & OSF1 all lay out the hardware state in the same manner - at the base of the frame in an interrupt handler. Registers within - are saved in the exact same order as GDB numbers registers. How - convienent. */ - if (pc_in_interrupt_handler (pc)) - return read_memory_integer (get_frame_base (frame) + PC_REGNUM * 4, - TARGET_PTR_BIT / 8) & ~0x3; - - if ((get_frame_pc (frame) >= get_frame_base (frame) - && (get_frame_pc (frame) - <= (get_frame_base (frame) - /* A call dummy is sized in words, but it is actually a - series of instructions. Account for that scaling - factor. */ - + ((DEPRECATED_REGISTER_SIZE / INSTRUCTION_SIZE) - * DEPRECATED_CALL_DUMMY_LENGTH) - /* Similarly we have to account for 64bit wide register - saves. */ - + (32 * DEPRECATED_REGISTER_SIZE) - /* We always consider FP regs 8 bytes long. */ - + (NUM_REGS - FP0_REGNUM) * 8 - /* Similarly we have to account for 64bit wide register - saves. */ - + (6 * DEPRECATED_REGISTER_SIZE))))) - { - return read_memory_integer ((get_frame_base (frame) - + (TARGET_PTR_BIT == 64 ? -16 : -20)), - TARGET_PTR_BIT / 8) & ~0x3; - } - -#ifdef FRAME_SAVED_PC_IN_SIGTRAMP - /* Deal with signal handler caller frames too. */ - if ((get_frame_type (frame) == SIGTRAMP_FRAME)) - { - CORE_ADDR rp; - FRAME_SAVED_PC_IN_SIGTRAMP (frame, &rp); - return rp & ~0x3; - } -#endif - - if (hppa_frameless_function_invocation (frame)) - { - int ret_regnum; - - ret_regnum = find_return_regnum (pc); - - /* If the next frame is an interrupt frame or a signal - handler caller, then we need to look in the saved - register area to get the return pointer (the values - in the registers may not correspond to anything useful). */ - if (get_next_frame (frame) - && ((get_frame_type (get_next_frame (frame)) == SIGTRAMP_FRAME) - || pc_in_interrupt_handler (get_frame_pc (get_next_frame (frame))))) - { - CORE_ADDR *saved_regs; - hppa_frame_init_saved_regs (get_next_frame (frame)); - saved_regs = deprecated_get_frame_saved_regs (get_next_frame (frame)); - if (read_memory_integer (saved_regs[FLAGS_REGNUM], - TARGET_PTR_BIT / 8) & 0x2) - { - pc = read_memory_integer (saved_regs[31], - TARGET_PTR_BIT / 8) & ~0x3; - - /* Syscalls are really two frames. The syscall stub itself - with a return pointer in %rp and the kernel call with - a return pointer in %r31. We return the %rp variant - if %r31 is the same as frame->pc. */ - if (pc == get_frame_pc (frame)) - pc = read_memory_integer (saved_regs[RP_REGNUM], - TARGET_PTR_BIT / 8) & ~0x3; - } - else - pc = read_memory_integer (saved_regs[RP_REGNUM], - TARGET_PTR_BIT / 8) & ~0x3; - } - else - pc = read_register (ret_regnum) & ~0x3; - } - else - { - spun_around_loop = 0; - old_pc = pc; - - restart: - rp_offset = rp_saved (pc); - - /* Similar to code in frameless function case. If the next - frame is a signal or interrupt handler, then dig the right - information out of the saved register info. */ - if (rp_offset == 0 - && get_next_frame (frame) - && ((get_frame_type (get_next_frame (frame)) == SIGTRAMP_FRAME) - || pc_in_interrupt_handler (get_frame_pc (get_next_frame (frame))))) - { - CORE_ADDR *saved_regs; - hppa_frame_init_saved_regs (get_next_frame (frame)); - saved_regs = deprecated_get_frame_saved_regs (get_next_frame (frame)); - if (read_memory_integer (saved_regs[FLAGS_REGNUM], - TARGET_PTR_BIT / 8) & 0x2) - { - pc = read_memory_integer (saved_regs[31], - TARGET_PTR_BIT / 8) & ~0x3; - - /* Syscalls are really two frames. The syscall stub itself - with a return pointer in %rp and the kernel call with - a return pointer in %r31. We return the %rp variant - if %r31 is the same as frame->pc. */ - if (pc == get_frame_pc (frame)) - pc = read_memory_integer (saved_regs[RP_REGNUM], - TARGET_PTR_BIT / 8) & ~0x3; - } - else - pc = read_memory_integer (saved_regs[RP_REGNUM], - TARGET_PTR_BIT / 8) & ~0x3; - } - else if (rp_offset == 0) - { - old_pc = pc; - pc = read_register (RP_REGNUM) & ~0x3; - } - else - { - old_pc = pc; - pc = read_memory_integer (get_frame_base (frame) + rp_offset, - TARGET_PTR_BIT / 8) & ~0x3; - } - } - - /* If PC is inside a linker stub, then dig out the address the stub - will return to. - - Don't do this for long branch stubs. Why? For some unknown reason - _start is marked as a long branch stub in hpux10. */ - u = find_unwind_entry (pc); - if (u && u->stub_unwind.stub_type != 0 - && u->stub_unwind.stub_type != LONG_BRANCH) - { - unsigned int insn; - - /* If this is a dynamic executable, and we're in a signal handler, - then the call chain will eventually point us into the stub for - _sigreturn. Unlike most cases, we'll be pointed to the branch - to the real sigreturn rather than the code after the real branch!. - - Else, try to dig the address the stub will return to in the normal - fashion. */ - insn = read_memory_integer (pc, 4); - if ((insn & 0xfc00e000) == 0xe8000000) - return (pc + extract_17 (insn) + 8) & ~0x3; - else - { - if (old_pc == pc) - spun_around_loop++; - - if (spun_around_loop > 1) - { - /* We're just about to go around the loop again with - no more hope of success. Die. */ - error ("Unable to find return pc for this frame"); - } - else - goto restart; - } - } - - return pc; + /* Just always 16-byte align. */ + return align_up (addr, 16); } - -/* We need to correct the PC and the FP for the outermost frame when we are - in a system call. */ - -void -hppa_init_extra_frame_info (int fromleaf, struct frame_info *frame) -{ - int flags; - int framesize; - - if (get_next_frame (frame) && !fromleaf) - return; - - /* If the next frame represents a frameless function invocation then - we have to do some adjustments that are normally done by - DEPRECATED_FRAME_CHAIN. (DEPRECATED_FRAME_CHAIN is not called in - this case.) */ - if (fromleaf) - { - /* Find the framesize of *this* frame without peeking at the PC - in the current frame structure (it isn't set yet). */ - framesize = find_proc_framesize (DEPRECATED_FRAME_SAVED_PC (get_next_frame (frame))); - - /* Now adjust our base frame accordingly. If we have a frame pointer - use it, else subtract the size of this frame from the current - frame. (we always want frame->frame to point at the lowest address - in the frame). */ - if (framesize == -1) - deprecated_update_frame_base_hack (frame, deprecated_read_fp ()); - else - deprecated_update_frame_base_hack (frame, get_frame_base (frame) - framesize); - return; - } - flags = read_register (FLAGS_REGNUM); - if (flags & 2) /* In system call? */ - deprecated_update_frame_pc_hack (frame, read_register (31) & ~0x3); - - /* The outermost frame is always derived from PC-framesize - - One might think frameless innermost frames should have - a frame->frame that is the same as the parent's frame->frame. - That is wrong; frame->frame in that case should be the *high* - address of the parent's frame. It's complicated as hell to - explain, but the parent *always* creates some stack space for - the child. So the child actually does have a frame of some - sorts, and its base is the high address in its parent's frame. */ - framesize = find_proc_framesize (get_frame_pc (frame)); - if (framesize == -1) - deprecated_update_frame_base_hack (frame, deprecated_read_fp ()); - else - deprecated_update_frame_base_hack (frame, read_register (SP_REGNUM) - framesize); -} - -/* Given a GDB frame, determine the address of the calling function's - frame. This will be used to create a new GDB frame struct, and - then DEPRECATED_INIT_EXTRA_FRAME_INFO and DEPRECATED_INIT_FRAME_PC - will be called for the new frame. - This may involve searching through prologues for several functions - at boundaries where GCC calls HP C code, or where code which has - a frame pointer calls code without a frame pointer. */ +/* elz: Used to lookup a symbol in the shared libraries. + This function calls shl_findsym, indirectly through a + call to __d_shl_get. __d_shl_get is in end.c, which is always + linked in by the hp compilers/linkers. + The call to shl_findsym cannot be made directly because it needs + to be active in target address space. + inputs: - minimal symbol pointer for the function we want to look up + - address in target space of the descriptor for the library + where we want to look the symbol up. + This address is retrieved using the + som_solib_get_solib_by_pc function (somsolib.c). + output: - real address in the library of the function. + note: the handle can be null, in which case shl_findsym will look for + the symbol in all the loaded shared libraries. + files to look at if you need reference on this stuff: + dld.c, dld_shl_findsym.c + end.c + man entry for shl_findsym */ CORE_ADDR -hppa_frame_chain (struct frame_info *frame) +find_stub_with_shl_get (struct minimal_symbol *function, CORE_ADDR handle) { - int my_framesize, caller_framesize; - struct unwind_table_entry *u; - CORE_ADDR frame_base; - struct frame_info *tmp_frame; - - /* A frame in the current frame list, or zero. */ - struct frame_info *saved_regs_frame = 0; - /* Where the registers were saved in saved_regs_frame. If - saved_regs_frame is zero, this is garbage. */ - CORE_ADDR *saved_regs = NULL; - - CORE_ADDR caller_pc; - - struct minimal_symbol *min_frame_symbol; - struct symbol *frame_symbol; - char *frame_symbol_name; - - /* If this is a threaded application, and we see the - routine "__pthread_exit", treat it as the stack root - for this thread. */ - min_frame_symbol = lookup_minimal_symbol_by_pc (get_frame_pc (frame)); - frame_symbol = find_pc_function (get_frame_pc (frame)); - - if ((min_frame_symbol != 0) /* && (frame_symbol == 0) */ ) - { - /* The test above for "no user function name" would defend - against the slim likelihood that a user might define a - routine named "__pthread_exit" and then try to debug it. - - If it weren't commented out, and you tried to debug the - pthread library itself, you'd get errors. - - So for today, we don't make that check. */ - frame_symbol_name = DEPRECATED_SYMBOL_NAME (min_frame_symbol); - if (frame_symbol_name != 0) - { - if (0 == strncmp (frame_symbol_name, - THREAD_INITIAL_FRAME_SYMBOL, - THREAD_INITIAL_FRAME_SYM_LEN)) - { - /* Pretend we've reached the bottom of the stack. */ - return (CORE_ADDR) 0; - } - } - } /* End of hacky code for threads. */ - - /* Handle HPUX, BSD, and OSF1 style interrupt frames first. These - are easy; at *sp we have a full save state strucutre which we can - pull the old stack pointer from. Also see frame_saved_pc for - code to dig a saved PC out of the save state structure. */ - if (pc_in_interrupt_handler (get_frame_pc (frame))) - frame_base = read_memory_integer (get_frame_base (frame) + SP_REGNUM * 4, - TARGET_PTR_BIT / 8); -#ifdef FRAME_BASE_BEFORE_SIGTRAMP - else if ((get_frame_type (frame) == SIGTRAMP_FRAME)) - { - FRAME_BASE_BEFORE_SIGTRAMP (frame, &frame_base); - } -#endif - else - frame_base = get_frame_base (frame); - - /* Get frame sizes for the current frame and the frame of the - caller. */ - my_framesize = find_proc_framesize (get_frame_pc (frame)); - caller_pc = DEPRECATED_FRAME_SAVED_PC (frame); - - /* If we can't determine the caller's PC, then it's not likely we can - really determine anything meaningful about its frame. We'll consider - this to be stack bottom. */ - if (caller_pc == (CORE_ADDR) 0) - return (CORE_ADDR) 0; - - caller_framesize = find_proc_framesize (DEPRECATED_FRAME_SAVED_PC (frame)); - - /* If caller does not have a frame pointer, then its frame - can be found at current_frame - caller_framesize. */ - if (caller_framesize != -1) - { - return frame_base - caller_framesize; - } - /* Both caller and callee have frame pointers and are GCC compiled - (SAVE_SP bit in unwind descriptor is on for both functions. - The previous frame pointer is found at the top of the current frame. */ - if (caller_framesize == -1 && my_framesize == -1) - { - return read_memory_integer (frame_base, TARGET_PTR_BIT / 8); - } - /* Caller has a frame pointer, but callee does not. This is a little - more difficult as GCC and HP C lay out locals and callee register save - areas very differently. - - The previous frame pointer could be in a register, or in one of - several areas on the stack. - - Walk from the current frame to the innermost frame examining - unwind descriptors to determine if %r3 ever gets saved into the - stack. If so return whatever value got saved into the stack. - If it was never saved in the stack, then the value in %r3 is still - valid, so use it. - - We use information from unwind descriptors to determine if %r3 - is saved into the stack (Entry_GR field has this information). */ - - for (tmp_frame = frame; tmp_frame; tmp_frame = get_next_frame (tmp_frame)) - { - u = find_unwind_entry (get_frame_pc (tmp_frame)); - - if (!u) - { - /* We could find this information by examining prologues. I don't - think anyone has actually written any tools (not even "strip") - which leave them out of an executable, so maybe this is a moot - point. */ - /* ??rehrauer: Actually, it's quite possible to stepi your way into - code that doesn't have unwind entries. For example, stepping into - the dynamic linker will give you a PC that has none. Thus, I've - disabled this warning. */ -#if 0 - warning ("Unable to find unwind for PC 0x%x -- Help!", get_frame_pc (tmp_frame)); -#endif - return (CORE_ADDR) 0; - } - - if (u->Save_SP - || (get_frame_type (tmp_frame) == SIGTRAMP_FRAME) - || pc_in_interrupt_handler (get_frame_pc (tmp_frame))) - break; - - /* Entry_GR specifies the number of callee-saved general registers - saved in the stack. It starts at %r3, so %r3 would be 1. */ - if (u->Entry_GR >= 1) - { - /* The unwind entry claims that r3 is saved here. However, - in optimized code, GCC often doesn't actually save r3. - We'll discover this if we look at the prologue. */ - hppa_frame_init_saved_regs (tmp_frame); - saved_regs = deprecated_get_frame_saved_regs (tmp_frame); - saved_regs_frame = tmp_frame; - - /* If we have an address for r3, that's good. */ - if (saved_regs[DEPRECATED_FP_REGNUM]) - break; - } - } - - if (tmp_frame) - { - /* We may have walked down the chain into a function with a frame - pointer. */ - if (u->Save_SP - && !(get_frame_type (tmp_frame) == SIGTRAMP_FRAME) - && !pc_in_interrupt_handler (get_frame_pc (tmp_frame))) - { - return read_memory_integer (get_frame_base (tmp_frame), TARGET_PTR_BIT / 8); - } - /* %r3 was saved somewhere in the stack. Dig it out. */ - else - { - /* Sick. - - For optimization purposes many kernels don't have the - callee saved registers into the save_state structure upon - entry into the kernel for a syscall; the optimization - is usually turned off if the process is being traced so - that the debugger can get full register state for the - process. - - This scheme works well except for two cases: - - * Attaching to a process when the process is in the - kernel performing a system call (debugger can't get - full register state for the inferior process since - the process wasn't being traced when it entered the - system call). - - * Register state is not complete if the system call - causes the process to core dump. - - - The following heinous code is an attempt to deal with - the lack of register state in a core dump. It will - fail miserably if the function which performs the - system call has a variable sized stack frame. */ - - if (tmp_frame != saved_regs_frame) - { - hppa_frame_init_saved_regs (tmp_frame); - saved_regs = deprecated_get_frame_saved_regs (tmp_frame); - } - - /* Abominable hack. */ - if (current_target.to_has_execution == 0 - && ((saved_regs[FLAGS_REGNUM] - && (read_memory_integer (saved_regs[FLAGS_REGNUM], - TARGET_PTR_BIT / 8) - & 0x2)) - || (saved_regs[FLAGS_REGNUM] == 0 - && read_register (FLAGS_REGNUM) & 0x2))) - { - u = find_unwind_entry (DEPRECATED_FRAME_SAVED_PC (frame)); - if (!u) - { - return read_memory_integer (saved_regs[DEPRECATED_FP_REGNUM], - TARGET_PTR_BIT / 8); - } - else - { - return frame_base - (u->Total_frame_size << 3); - } - } - - return read_memory_integer (saved_regs[DEPRECATED_FP_REGNUM], - TARGET_PTR_BIT / 8); - } - } - else - { - /* Get the innermost frame. */ - tmp_frame = frame; - while (get_next_frame (tmp_frame) != NULL) - tmp_frame = get_next_frame (tmp_frame); - - if (tmp_frame != saved_regs_frame) - { - hppa_frame_init_saved_regs (tmp_frame); - saved_regs = deprecated_get_frame_saved_regs (tmp_frame); - } - - /* Abominable hack. See above. */ - if (current_target.to_has_execution == 0 - && ((saved_regs[FLAGS_REGNUM] - && (read_memory_integer (saved_regs[FLAGS_REGNUM], - TARGET_PTR_BIT / 8) - & 0x2)) - || (saved_regs[FLAGS_REGNUM] == 0 - && read_register (FLAGS_REGNUM) & 0x2))) - { - u = find_unwind_entry (DEPRECATED_FRAME_SAVED_PC (frame)); - if (!u) - { - return read_memory_integer (saved_regs[DEPRECATED_FP_REGNUM], - TARGET_PTR_BIT / 8); - } - else - { - return frame_base - (u->Total_frame_size << 3); - } - } - - /* The value in %r3 was never saved into the stack (thus %r3 still - holds the value of the previous frame pointer). */ - return deprecated_read_fp (); - } -} - - -/* To see if a frame chain is valid, see if the caller looks like it - was compiled with gcc. */ + struct symbol *get_sym, *symbol2; + struct minimal_symbol *buff_minsym, *msymbol; + struct type *ftype; + struct value **args; + struct value *funcval; + struct value *val; -int -hppa_frame_chain_valid (CORE_ADDR chain, struct frame_info *thisframe) -{ - struct minimal_symbol *msym_us; - struct minimal_symbol *msym_start; - struct unwind_table_entry *u, *next_u = NULL; - struct frame_info *next; + int x, namelen, err_value, tmp = -1; + CORE_ADDR endo_buff_addr, value_return_addr, errno_return_addr; + CORE_ADDR stub_addr; - u = find_unwind_entry (get_frame_pc (thisframe)); - if (u == NULL) - return 1; + args = alloca (sizeof (struct value *) * 8); /* 6 for the arguments and one null one??? */ + funcval = find_function_in_inferior ("__d_shl_get"); + get_sym = lookup_symbol ("__d_shl_get", NULL, VAR_DOMAIN, NULL, NULL); + buff_minsym = lookup_minimal_symbol ("__buffer", NULL, NULL); + msymbol = lookup_minimal_symbol ("__shldp", NULL, NULL); + symbol2 = lookup_symbol ("__shldp", NULL, VAR_DOMAIN, NULL, NULL); + endo_buff_addr = SYMBOL_VALUE_ADDRESS (buff_minsym); + namelen = strlen (DEPRECATED_SYMBOL_NAME (function)); + value_return_addr = endo_buff_addr + namelen; + ftype = check_typedef (SYMBOL_TYPE (get_sym)); - /* We can't just check that the same of msym_us is "_start", because - someone idiotically decided that they were going to make a Ltext_end - symbol with the same address. This Ltext_end symbol is totally - indistinguishable (as nearly as I can tell) from the symbol for a function - which is (legitimately, since it is in the user's namespace) - named Ltext_end, so we can't just ignore it. */ - msym_us = lookup_minimal_symbol_by_pc (DEPRECATED_FRAME_SAVED_PC (thisframe)); - msym_start = lookup_minimal_symbol ("_start", NULL, NULL); - if (msym_us - && msym_start - && SYMBOL_VALUE_ADDRESS (msym_us) == SYMBOL_VALUE_ADDRESS (msym_start)) - return 0; + /* do alignment */ + if ((x = value_return_addr % 64) != 0) + value_return_addr = value_return_addr + 64 - x; - /* Grrrr. Some new idiot decided that they don't want _start for the - PRO configurations; $START$ calls main directly.... Deal with it. */ - msym_start = lookup_minimal_symbol ("$START$", NULL, NULL); - if (msym_us - && msym_start - && SYMBOL_VALUE_ADDRESS (msym_us) == SYMBOL_VALUE_ADDRESS (msym_start)) - return 0; + errno_return_addr = value_return_addr + 64; - next = get_next_frame (thisframe); - if (next) - next_u = find_unwind_entry (get_frame_pc (next)); - /* If this frame does not save SP, has no stack, isn't a stub, - and doesn't "call" an interrupt routine or signal handler caller, - then its not valid. */ - if (u->Save_SP || u->Total_frame_size || u->stub_unwind.stub_type != 0 - || (get_next_frame (thisframe) && (get_frame_type (get_next_frame (thisframe)) == SIGTRAMP_FRAME)) - || (next_u && next_u->HP_UX_interrupt_marker)) - return 1; + /* set up stuff needed by __d_shl_get in buffer in end.o */ - if (pc_in_linker_stub (get_frame_pc (thisframe))) - return 1; + target_write_memory (endo_buff_addr, DEPRECATED_SYMBOL_NAME (function), namelen); - return 0; -} + target_write_memory (value_return_addr, (char *) &tmp, 4); -/* These functions deal with saving and restoring register state - around a function call in the inferior. They keep the stack - double-word aligned; eventually, on an hp700, the stack will have - to be aligned to a 64-byte boundary. */ + target_write_memory (errno_return_addr, (char *) &tmp, 4); -void -hppa_push_dummy_frame (void) -{ - CORE_ADDR sp, pc, pcspace; - int regnum; - CORE_ADDR int_buffer; - double freg_buffer; - - pc = hppa_target_read_pc (inferior_ptid); - int_buffer = read_register (FLAGS_REGNUM); - if (int_buffer & 0x2) - { - const unsigned int sid = (pc >> 30) & 0x3; - if (sid == 0) - pcspace = read_register (SR4_REGNUM); - else - pcspace = read_register (SR4_REGNUM + 4 + sid); - } - else - pcspace = read_register (PCSQ_HEAD_REGNUM); + target_write_memory (SYMBOL_VALUE_ADDRESS (msymbol), + (char *) &handle, 4); - /* Space for "arguments"; the RP goes in here. */ - sp = read_register (SP_REGNUM) + 48; - int_buffer = read_register (RP_REGNUM) | 0x3; + /* now prepare the arguments for the call */ - /* The 32bit and 64bit ABIs save the return pointer into different - stack slots. */ - if (DEPRECATED_REGISTER_SIZE == 8) - write_memory (sp - 16, (char *) &int_buffer, DEPRECATED_REGISTER_SIZE); - else - write_memory (sp - 20, (char *) &int_buffer, DEPRECATED_REGISTER_SIZE); - - int_buffer = deprecated_read_fp (); - write_memory (sp, (char *) &int_buffer, DEPRECATED_REGISTER_SIZE); - - write_register (DEPRECATED_FP_REGNUM, sp); - - sp += 2 * DEPRECATED_REGISTER_SIZE; - - for (regnum = 1; regnum < 32; regnum++) - if (regnum != RP_REGNUM && regnum != DEPRECATED_FP_REGNUM) - sp = push_word (sp, read_register (regnum)); - - /* This is not necessary for the 64bit ABI. In fact it is dangerous. */ - if (DEPRECATED_REGISTER_SIZE != 8) - sp += 4; - - for (regnum = FP0_REGNUM; regnum < NUM_REGS; regnum++) - { - deprecated_read_register_bytes (DEPRECATED_REGISTER_BYTE (regnum), - (char *) &freg_buffer, 8); - sp = push_bytes (sp, (char *) &freg_buffer, 8); - } - sp = push_word (sp, read_register (IPSW_REGNUM)); - sp = push_word (sp, read_register (SAR_REGNUM)); - sp = push_word (sp, pc); - sp = push_word (sp, pcspace); - sp = push_word (sp, pc + 4); - sp = push_word (sp, pcspace); - write_register (SP_REGNUM, sp); -} - -static void -find_dummy_frame_regs (struct frame_info *frame, - CORE_ADDR frame_saved_regs[]) -{ - CORE_ADDR fp = get_frame_base (frame); - int i; - - /* The 32bit and 64bit ABIs save RP into different locations. */ - if (DEPRECATED_REGISTER_SIZE == 8) - frame_saved_regs[RP_REGNUM] = (fp - 16) & ~0x3; - else - frame_saved_regs[RP_REGNUM] = (fp - 20) & ~0x3; - - frame_saved_regs[DEPRECATED_FP_REGNUM] = fp; - - frame_saved_regs[1] = fp + (2 * DEPRECATED_REGISTER_SIZE); - - for (fp += 3 * DEPRECATED_REGISTER_SIZE, i = 3; i < 32; i++) - { - if (i != DEPRECATED_FP_REGNUM) - { - frame_saved_regs[i] = fp; - fp += DEPRECATED_REGISTER_SIZE; - } - } - - /* This is not necessary or desirable for the 64bit ABI. */ - if (DEPRECATED_REGISTER_SIZE != 8) - fp += 4; - - for (i = FP0_REGNUM; i < NUM_REGS; i++, fp += 8) - frame_saved_regs[i] = fp; - - frame_saved_regs[IPSW_REGNUM] = fp; - frame_saved_regs[SAR_REGNUM] = fp + DEPRECATED_REGISTER_SIZE; - frame_saved_regs[PCOQ_HEAD_REGNUM] = fp + 2 * DEPRECATED_REGISTER_SIZE; - frame_saved_regs[PCSQ_HEAD_REGNUM] = fp + 3 * DEPRECATED_REGISTER_SIZE; - frame_saved_regs[PCOQ_TAIL_REGNUM] = fp + 4 * DEPRECATED_REGISTER_SIZE; - frame_saved_regs[PCSQ_TAIL_REGNUM] = fp + 5 * DEPRECATED_REGISTER_SIZE; -} - -void -hppa_pop_frame (void) -{ - struct frame_info *frame = get_current_frame (); - CORE_ADDR fp, npc, target_pc; - int regnum; - CORE_ADDR *fsr; - double freg_buffer; - - fp = get_frame_base (frame); - hppa_frame_init_saved_regs (frame); - fsr = deprecated_get_frame_saved_regs (frame); - -#ifndef NO_PC_SPACE_QUEUE_RESTORE - if (fsr[IPSW_REGNUM]) /* Restoring a call dummy frame */ - restore_pc_queue (fsr); -#endif - - for (regnum = 31; regnum > 0; regnum--) - if (fsr[regnum]) - write_register (regnum, read_memory_integer (fsr[regnum], - DEPRECATED_REGISTER_SIZE)); - - for (regnum = NUM_REGS - 1; regnum >= FP0_REGNUM; regnum--) - if (fsr[regnum]) - { - read_memory (fsr[regnum], (char *) &freg_buffer, 8); - deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (regnum), - (char *) &freg_buffer, 8); - } - - if (fsr[IPSW_REGNUM]) - write_register (IPSW_REGNUM, - read_memory_integer (fsr[IPSW_REGNUM], - DEPRECATED_REGISTER_SIZE)); - - if (fsr[SAR_REGNUM]) - write_register (SAR_REGNUM, - read_memory_integer (fsr[SAR_REGNUM], - DEPRECATED_REGISTER_SIZE)); - - /* If the PC was explicitly saved, then just restore it. */ - if (fsr[PCOQ_TAIL_REGNUM]) - { - npc = read_memory_integer (fsr[PCOQ_TAIL_REGNUM], - DEPRECATED_REGISTER_SIZE); - write_register (PCOQ_TAIL_REGNUM, npc); - } - /* Else use the value in %rp to set the new PC. */ - else - { - npc = read_register (RP_REGNUM); - write_pc (npc); - } - - write_register (DEPRECATED_FP_REGNUM, read_memory_integer (fp, DEPRECATED_REGISTER_SIZE)); - - if (fsr[IPSW_REGNUM]) /* call dummy */ - write_register (SP_REGNUM, fp - 48); - else - write_register (SP_REGNUM, fp); - - /* The PC we just restored may be inside a return trampoline. If so - we want to restart the inferior and run it through the trampoline. - - Do this by setting a momentary breakpoint at the location the - trampoline returns to. - - Don't skip through the trampoline if we're popping a dummy frame. */ - target_pc = SKIP_TRAMPOLINE_CODE (npc & ~0x3) & ~0x3; - if (target_pc && !fsr[IPSW_REGNUM]) - { - struct symtab_and_line sal; - struct breakpoint *breakpoint; - struct cleanup *old_chain; - - /* Set up our breakpoint. Set it to be silent as the MI code - for "return_command" will print the frame we returned to. */ - sal = find_pc_line (target_pc, 0); - sal.pc = target_pc; - breakpoint = set_momentary_breakpoint (sal, null_frame_id, bp_finish); - breakpoint->silent = 1; - - /* So we can clean things up. */ - old_chain = make_cleanup_delete_breakpoint (breakpoint); - - /* Start up the inferior. */ - clear_proceed_status (); - proceed_to_finish = 1; - proceed ((CORE_ADDR) -1, TARGET_SIGNAL_DEFAULT, 0); - - /* Perform our cleanups. */ - do_cleanups (old_chain); - } - flush_cached_frames (); -} - -/* After returning to a dummy on the stack, restore the instruction - queue space registers. */ - -static int -restore_pc_queue (CORE_ADDR *fsr) -{ - CORE_ADDR pc = read_pc (); - CORE_ADDR new_pc = read_memory_integer (fsr[PCOQ_HEAD_REGNUM], - TARGET_PTR_BIT / 8); - struct target_waitstatus w; - int insn_count; - - /* Advance past break instruction in the call dummy. */ - write_register (PCOQ_HEAD_REGNUM, pc + 4); - write_register (PCOQ_TAIL_REGNUM, pc + 8); - - /* HPUX doesn't let us set the space registers or the space - registers of the PC queue through ptrace. Boo, hiss. - Conveniently, the call dummy has this sequence of instructions - after the break: - mtsp r21, sr0 - ble,n 0(sr0, r22) - - So, load up the registers and single step until we are in the - right place. */ - - write_register (21, read_memory_integer (fsr[PCSQ_HEAD_REGNUM], - DEPRECATED_REGISTER_SIZE)); - write_register (22, new_pc); - - for (insn_count = 0; insn_count < 3; insn_count++) - { - /* FIXME: What if the inferior gets a signal right now? Want to - merge this into wait_for_inferior (as a special kind of - watchpoint? By setting a breakpoint at the end? Is there - any other choice? Is there *any* way to do this stuff with - ptrace() or some equivalent?). */ - resume (1, 0); - target_wait (inferior_ptid, &w); - - if (w.kind == TARGET_WAITKIND_SIGNALLED) - { - stop_signal = w.value.sig; - terminal_ours_for_output (); - printf_unfiltered ("\nProgram terminated with signal %s, %s.\n", - target_signal_to_name (stop_signal), - target_signal_to_string (stop_signal)); - gdb_flush (gdb_stdout); - return 0; - } - } - target_terminal_ours (); - target_fetch_registers (-1); - return 1; -} - - -#ifdef PA20W_CALLING_CONVENTIONS - -/* This function pushes a stack frame with arguments as part of the - inferior function calling mechanism. - - This is the version for the PA64, in which later arguments appear - at higher addresses. (The stack always grows towards higher - addresses.) - - We simply allocate the appropriate amount of stack space and put - arguments into their proper slots. The call dummy code will copy - arguments into registers as needed by the ABI. - - This ABI also requires that the caller provide an argument pointer - to the callee, so we do that too. */ - -CORE_ADDR -hppa_push_arguments (int nargs, struct value **args, CORE_ADDR sp, - int struct_return, CORE_ADDR struct_addr) -{ - /* array of arguments' offsets */ - int *offset = (int *) alloca (nargs * sizeof (int)); - - /* array of arguments' lengths: real lengths in bytes, not aligned to - word size */ - int *lengths = (int *) alloca (nargs * sizeof (int)); - - /* The value of SP as it was passed into this function after - aligning. */ - CORE_ADDR orig_sp = DEPRECATED_STACK_ALIGN (sp); - - /* The number of stack bytes occupied by the current argument. */ - int bytes_reserved; - - /* The total number of bytes reserved for the arguments. */ - int cum_bytes_reserved = 0; - - /* Similarly, but aligned. */ - int cum_bytes_aligned = 0; - int i; - - /* Iterate over each argument provided by the user. */ - for (i = 0; i < nargs; i++) - { - struct type *arg_type = VALUE_TYPE (args[i]); - - /* Integral scalar values smaller than a register are padded on - the left. We do this by promoting them to full-width, - although the ABI says to pad them with garbage. */ - if (is_integral_type (arg_type) - && TYPE_LENGTH (arg_type) < DEPRECATED_REGISTER_SIZE) - { - args[i] = value_cast ((TYPE_UNSIGNED (arg_type) - ? builtin_type_unsigned_long - : builtin_type_long), - args[i]); - arg_type = VALUE_TYPE (args[i]); - } - - lengths[i] = TYPE_LENGTH (arg_type); - - /* Align the size of the argument to the word size for this - target. */ - bytes_reserved = (lengths[i] + DEPRECATED_REGISTER_SIZE - 1) & -DEPRECATED_REGISTER_SIZE; - - offset[i] = cum_bytes_reserved; - - /* Aggregates larger than eight bytes (the only types larger - than eight bytes we have) are aligned on a 16-byte boundary, - possibly padded on the right with garbage. This may leave an - empty word on the stack, and thus an unused register, as per - the ABI. */ - if (bytes_reserved > 8) - { - /* Round up the offset to a multiple of two slots. */ - int new_offset = ((offset[i] + 2*DEPRECATED_REGISTER_SIZE-1) - & -(2*DEPRECATED_REGISTER_SIZE)); - - /* Note the space we've wasted, if any. */ - bytes_reserved += new_offset - offset[i]; - offset[i] = new_offset; - } - - cum_bytes_reserved += bytes_reserved; - } - - /* CUM_BYTES_RESERVED already accounts for all the arguments - passed by the user. However, the ABIs mandate minimum stack space - allocations for outgoing arguments. - - The ABIs also mandate minimum stack alignments which we must - preserve. */ - cum_bytes_aligned = DEPRECATED_STACK_ALIGN (cum_bytes_reserved); - sp += max (cum_bytes_aligned, REG_PARM_STACK_SPACE); - - /* Now write each of the args at the proper offset down the stack. */ - for (i = 0; i < nargs; i++) - write_memory (orig_sp + offset[i], VALUE_CONTENTS (args[i]), lengths[i]); - - /* If a structure has to be returned, set up register 28 to hold its - address */ - if (struct_return) - write_register (28, struct_addr); - - /* For the PA64 we must pass a pointer to the outgoing argument list. - The ABI mandates that the pointer should point to the first byte of - storage beyond the register flushback area. - - However, the call dummy expects the outgoing argument pointer to - be passed in register %r4. */ - write_register (4, orig_sp + REG_PARM_STACK_SPACE); - - /* ?!? This needs further work. We need to set up the global data - pointer for this procedure. This assumes the same global pointer - for every procedure. The call dummy expects the dp value to - be passed in register %r6. */ - write_register (6, read_register (27)); - - /* The stack will have 64 bytes of additional space for a frame marker. */ - return sp + 64; -} - -#else - -/* This function pushes a stack frame with arguments as part of the - inferior function calling mechanism. - - This is the version of the function for the 32-bit PA machines, in - which later arguments appear at lower addresses. (The stack always - grows towards higher addresses.) - - We simply allocate the appropriate amount of stack space and put - arguments into their proper slots. The call dummy code will copy - arguments into registers as needed by the ABI. */ - -CORE_ADDR -hppa_push_arguments (int nargs, struct value **args, CORE_ADDR sp, - int struct_return, CORE_ADDR struct_addr) -{ - /* array of arguments' offsets */ - int *offset = (int *) alloca (nargs * sizeof (int)); - - /* array of arguments' lengths: real lengths in bytes, not aligned to - word size */ - int *lengths = (int *) alloca (nargs * sizeof (int)); - - /* The number of stack bytes occupied by the current argument. */ - int bytes_reserved; - - /* The total number of bytes reserved for the arguments. */ - int cum_bytes_reserved = 0; - - /* Similarly, but aligned. */ - int cum_bytes_aligned = 0; - int i; - - /* Iterate over each argument provided by the user. */ - for (i = 0; i < nargs; i++) - { - lengths[i] = TYPE_LENGTH (VALUE_TYPE (args[i])); - - /* Align the size of the argument to the word size for this - target. */ - bytes_reserved = (lengths[i] + DEPRECATED_REGISTER_SIZE - 1) & -DEPRECATED_REGISTER_SIZE; - - offset[i] = (cum_bytes_reserved - + (lengths[i] > 4 ? bytes_reserved : lengths[i])); - - /* If the argument is a double word argument, then it needs to be - double word aligned. */ - if ((bytes_reserved == 2 * DEPRECATED_REGISTER_SIZE) - && (offset[i] % 2 * DEPRECATED_REGISTER_SIZE)) - { - int new_offset = 0; - /* BYTES_RESERVED is already aligned to the word, so we put - the argument at one word more down the stack. - - This will leave one empty word on the stack, and one unused - register as mandated by the ABI. */ - new_offset = ((offset[i] + 2 * DEPRECATED_REGISTER_SIZE - 1) - & -(2 * DEPRECATED_REGISTER_SIZE)); - - if ((new_offset - offset[i]) >= 2 * DEPRECATED_REGISTER_SIZE) - { - bytes_reserved += DEPRECATED_REGISTER_SIZE; - offset[i] += DEPRECATED_REGISTER_SIZE; - } - } - - cum_bytes_reserved += bytes_reserved; - - } - - /* CUM_BYTES_RESERVED already accounts for all the arguments passed - by the user. However, the ABI mandates minimum stack space - allocations for outgoing arguments. - - The ABI also mandates minimum stack alignments which we must - preserve. */ - cum_bytes_aligned = DEPRECATED_STACK_ALIGN (cum_bytes_reserved); - sp += max (cum_bytes_aligned, REG_PARM_STACK_SPACE); - - /* Now write each of the args at the proper offset down the stack. - ?!? We need to promote values to a full register instead of skipping - words in the stack. */ - for (i = 0; i < nargs; i++) - write_memory (sp - offset[i], VALUE_CONTENTS (args[i]), lengths[i]); - - /* If a structure has to be returned, set up register 28 to hold its - address */ - if (struct_return) - write_register (28, struct_addr); - - /* The stack will have 32 bytes of additional space for a frame marker. */ - return sp + 32; -} - -#endif - -/* This function pushes a stack frame with arguments as part of the - inferior function calling mechanism. - - This is the version of the function for the 32-bit PA machines, in - which later arguments appear at lower addresses. (The stack always - grows towards higher addresses.) - - We simply allocate the appropriate amount of stack space and put - arguments into their proper slots. */ - -CORE_ADDR -hppa32_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, - struct regcache *regcache, CORE_ADDR bp_addr, - int nargs, struct value **args, CORE_ADDR sp, - int struct_return, CORE_ADDR struct_addr) -{ - /* NOTE: cagney/2004-02-27: This is a guess - its implemented by - reverse engineering testsuite failures. */ - - /* Stack base address at which any pass-by-reference parameters are - stored. */ - CORE_ADDR struct_end = 0; - /* Stack base address at which the first parameter is stored. */ - CORE_ADDR param_end = 0; - - /* The inner most end of the stack after all the parameters have - been pushed. */ - CORE_ADDR new_sp = 0; - - /* Two passes. First pass computes the location of everything, - second pass writes the bytes out. */ - int write_pass; - for (write_pass = 0; write_pass < 2; write_pass++) - { - CORE_ADDR struct_ptr = 0; - CORE_ADDR param_ptr = 0; - int reg = 27; /* NOTE: Registers go down. */ - int i; - for (i = 0; i < nargs; i++) - { - struct value *arg = args[i]; - struct type *type = check_typedef (VALUE_TYPE (arg)); - /* The corresponding parameter that is pushed onto the - stack, and [possibly] passed in a register. */ - char param_val[8]; - int param_len; - memset (param_val, 0, sizeof param_val); - if (TYPE_LENGTH (type) > 8) - { - /* Large parameter, pass by reference. Store the value - in "struct" area and then pass its address. */ - param_len = 4; - struct_ptr += align_up (TYPE_LENGTH (type), 8); - if (write_pass) - write_memory (struct_end - struct_ptr, VALUE_CONTENTS (arg), - TYPE_LENGTH (type)); - store_unsigned_integer (param_val, 4, struct_end - struct_ptr); - } - else if (TYPE_CODE (type) == TYPE_CODE_INT - || TYPE_CODE (type) == TYPE_CODE_ENUM) - { - /* Integer value store, right aligned. "unpack_long" - takes care of any sign-extension problems. */ - param_len = align_up (TYPE_LENGTH (type), 4); - store_unsigned_integer (param_val, param_len, - unpack_long (type, - VALUE_CONTENTS (arg))); - } - else - { - /* Small struct value, store right aligned? */ - param_len = align_up (TYPE_LENGTH (type), 4); - memcpy (param_val + param_len - TYPE_LENGTH (type), - VALUE_CONTENTS (arg), TYPE_LENGTH (type)); - } - param_ptr += param_len; - reg -= param_len / 4; - if (write_pass) - { - write_memory (param_end - param_ptr, param_val, param_len); - if (reg >= 23) - { - regcache_cooked_write (regcache, reg, param_val); - if (param_len > 4) - regcache_cooked_write (regcache, reg + 1, param_val + 4); - } - } - } - - /* Update the various stack pointers. */ - if (!write_pass) - { - struct_end = sp + struct_ptr; - /* PARAM_PTR already accounts for all the arguments passed - by the user. However, the ABI mandates minimum stack - space allocations for outgoing arguments. The ABI also - mandates minimum stack alignments which we must - preserve. */ - param_end = struct_end + max (align_up (param_ptr, 8), - REG_PARM_STACK_SPACE); - } - } - - /* If a structure has to be returned, set up register 28 to hold its - address */ - if (struct_return) - write_register (28, struct_addr); - - /* Set the return address. */ - regcache_cooked_write_unsigned (regcache, RP_REGNUM, bp_addr); - - /* The stack will have 32 bytes of additional space for a frame marker. */ - return param_end + 32; -} - -/* This function pushes a stack frame with arguments as part of the - inferior function calling mechanism. - - This is the version for the PA64, in which later arguments appear - at higher addresses. (The stack always grows towards higher - addresses.) - - We simply allocate the appropriate amount of stack space and put - arguments into their proper slots. - - This ABI also requires that the caller provide an argument pointer - to the callee, so we do that too. */ - -CORE_ADDR -hppa64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, - struct regcache *regcache, CORE_ADDR bp_addr, - int nargs, struct value **args, CORE_ADDR sp, - int struct_return, CORE_ADDR struct_addr) -{ - /* Array of arguments' offsets. */ - int *offset = (int *) alloca (nargs * sizeof (int)); - - /* Array of arguments' lengths: real lengths in bytes, not aligned - to word size. */ - int *lengths = (int *) alloca (nargs * sizeof (int)); - - /* The value of SP as it was passed into this function. */ - CORE_ADDR orig_sp = sp; - - /* The number of stack bytes occupied by the current argument. */ - int bytes_reserved; - - /* The total number of bytes reserved for the arguments. */ - int cum_bytes_reserved = 0; - - /* Similarly, but aligned. */ - int cum_bytes_aligned = 0; - int i; - - /* Iterate over each argument provided by the user. */ - for (i = 0; i < nargs; i++) - { - struct type *arg_type = VALUE_TYPE (args[i]); - - /* Integral scalar values smaller than a register are padded on - the left. We do this by promoting them to full-width, - although the ABI says to pad them with garbage. */ - if (is_integral_type (arg_type) - && TYPE_LENGTH (arg_type) < DEPRECATED_REGISTER_SIZE) - { - args[i] = value_cast ((TYPE_UNSIGNED (arg_type) - ? builtin_type_unsigned_long - : builtin_type_long), - args[i]); - arg_type = VALUE_TYPE (args[i]); - } - - lengths[i] = TYPE_LENGTH (arg_type); - - /* Align the size of the argument to the word size for this - target. */ - bytes_reserved = (lengths[i] + DEPRECATED_REGISTER_SIZE - 1) & -DEPRECATED_REGISTER_SIZE; - - offset[i] = cum_bytes_reserved; - - /* Aggregates larger than eight bytes (the only types larger - than eight bytes we have) are aligned on a 16-byte boundary, - possibly padded on the right with garbage. This may leave an - empty word on the stack, and thus an unused register, as per - the ABI. */ - if (bytes_reserved > 8) - { - /* Round up the offset to a multiple of two slots. */ - int new_offset = ((offset[i] + 2*DEPRECATED_REGISTER_SIZE-1) - & -(2*DEPRECATED_REGISTER_SIZE)); - - /* Note the space we've wasted, if any. */ - bytes_reserved += new_offset - offset[i]; - offset[i] = new_offset; - } - - cum_bytes_reserved += bytes_reserved; - } - - /* CUM_BYTES_RESERVED already accounts for all the arguments passed - by the user. However, the ABIs mandate minimum stack space - allocations for outgoing arguments. - - The ABIs also mandate minimum stack alignments which we must - preserve. */ - cum_bytes_aligned = align_up (cum_bytes_reserved, 16); - sp += max (cum_bytes_aligned, REG_PARM_STACK_SPACE); - - /* Now write each of the args at the proper offset down the - stack. */ - for (i = 0; i < nargs; i++) - write_memory (orig_sp + offset[i], VALUE_CONTENTS (args[i]), lengths[i]); - - /* If a structure has to be returned, set up register 28 to hold its - address */ - if (struct_return) - write_register (28, struct_addr); - - /* For the PA64 we must pass a pointer to the outgoing argument - list. The ABI mandates that the pointer should point to the - first byte of storage beyond the register flushback area. - - However, the call dummy expects the outgoing argument pointer to - be passed in register %r4. */ - write_register (4, orig_sp + REG_PARM_STACK_SPACE); - - /* ?!? This needs further work. We need to set up the global data - pointer for this procedure. This assumes the same global pointer - for every procedure. The call dummy expects the dp value to be - passed in register %r6. */ - write_register (6, read_register (27)); - - /* Set the return address. */ - regcache_cooked_write_unsigned (regcache, RP_REGNUM, bp_addr); - - /* The stack will have 64 bytes of additional space for a frame - marker. */ - return sp + 64; - -} - -static CORE_ADDR -hppa32_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) -{ - /* HP frames are 64-byte (or cache line) aligned (yes that's _byte_ - and not _bit_)! */ - return align_up (addr, 64); -} - -/* Force all frames to 16-byte alignment. Better safe than sorry. */ - -static CORE_ADDR -hppa64_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) -{ - /* Just always 16-byte align. */ - return align_up (addr, 16); -} - - -/* elz: Used to lookup a symbol in the shared libraries. - This function calls shl_findsym, indirectly through a - call to __d_shl_get. __d_shl_get is in end.c, which is always - linked in by the hp compilers/linkers. - The call to shl_findsym cannot be made directly because it needs - to be active in target address space. - inputs: - minimal symbol pointer for the function we want to look up - - address in target space of the descriptor for the library - where we want to look the symbol up. - This address is retrieved using the - som_solib_get_solib_by_pc function (somsolib.c). - output: - real address in the library of the function. - note: the handle can be null, in which case shl_findsym will look for - the symbol in all the loaded shared libraries. - files to look at if you need reference on this stuff: - dld.c, dld_shl_findsym.c - end.c - man entry for shl_findsym */ - -CORE_ADDR -find_stub_with_shl_get (struct minimal_symbol *function, CORE_ADDR handle) -{ - struct symbol *get_sym, *symbol2; - struct minimal_symbol *buff_minsym, *msymbol; - struct type *ftype; - struct value **args; - struct value *funcval; - struct value *val; - - int x, namelen, err_value, tmp = -1; - CORE_ADDR endo_buff_addr, value_return_addr, errno_return_addr; - CORE_ADDR stub_addr; - - - args = alloca (sizeof (struct value *) * 8); /* 6 for the arguments and one null one??? */ - funcval = find_function_in_inferior ("__d_shl_get"); - get_sym = lookup_symbol ("__d_shl_get", NULL, VAR_DOMAIN, NULL, NULL); - buff_minsym = lookup_minimal_symbol ("__buffer", NULL, NULL); - msymbol = lookup_minimal_symbol ("__shldp", NULL, NULL); - symbol2 = lookup_symbol ("__shldp", NULL, VAR_DOMAIN, NULL, NULL); - endo_buff_addr = SYMBOL_VALUE_ADDRESS (buff_minsym); - namelen = strlen (DEPRECATED_SYMBOL_NAME (function)); - value_return_addr = endo_buff_addr + namelen; - ftype = check_typedef (SYMBOL_TYPE (get_sym)); - - /* do alignment */ - if ((x = value_return_addr % 64) != 0) - value_return_addr = value_return_addr + 64 - x; - - errno_return_addr = value_return_addr + 64; - - - /* set up stuff needed by __d_shl_get in buffer in end.o */ - - target_write_memory (endo_buff_addr, DEPRECATED_SYMBOL_NAME (function), namelen); - - target_write_memory (value_return_addr, (char *) &tmp, 4); - - target_write_memory (errno_return_addr, (char *) &tmp, 4); - - target_write_memory (SYMBOL_VALUE_ADDRESS (msymbol), - (char *) &handle, 4); - - /* now prepare the arguments for the call */ - - args[0] = value_from_longest (TYPE_FIELD_TYPE (ftype, 0), 12); - args[1] = value_from_pointer (TYPE_FIELD_TYPE (ftype, 1), SYMBOL_VALUE_ADDRESS (msymbol)); - args[2] = value_from_pointer (TYPE_FIELD_TYPE (ftype, 2), endo_buff_addr); - args[3] = value_from_longest (TYPE_FIELD_TYPE (ftype, 3), TYPE_PROCEDURE); - args[4] = value_from_pointer (TYPE_FIELD_TYPE (ftype, 4), value_return_addr); - args[5] = value_from_pointer (TYPE_FIELD_TYPE (ftype, 5), errno_return_addr); - - /* now call the function */ - - val = call_function_by_hand (funcval, 6, args); - - /* now get the results */ - - target_read_memory (errno_return_addr, (char *) &err_value, sizeof (err_value)); - - target_read_memory (value_return_addr, (char *) &stub_addr, sizeof (stub_addr)); - if (stub_addr <= 0) - error ("call to __d_shl_get failed, error code is %d", err_value); - - return (stub_addr); -} - -/* Cover routine for find_stub_with_shl_get to pass to catch_errors */ -static int -cover_find_stub_with_shl_get (void *args_untyped) -{ - args_for_find_stub *args = args_untyped; - args->return_val = find_stub_with_shl_get (args->msym, args->solib_handle); - return 0; -} - -/* Insert the specified number of args and function address - into a call sequence of the above form stored at DUMMYNAME. - - On the hppa we need to call the stack dummy through $$dyncall. - Therefore our version of DEPRECATED_FIX_CALL_DUMMY takes an extra - argument, real_pc, which is the location where gdb should start up - the inferior to do the function call. - - This has to work across several versions of hpux, bsd, osf1. It has to - work regardless of what compiler was used to build the inferior program. - It should work regardless of whether or not end.o is available. It has - to work even if gdb can not call into the dynamic loader in the inferior - to query it for symbol names and addresses. - - Yes, all those cases should work. Luckily code exists to handle most - of them. The complexity is in selecting exactly what scheme should - be used to perform the inferior call. - - At the current time this routine is known not to handle cases where - the program was linked with HP's compiler without including end.o. - - Please contact Jeff Law (law@cygnus.com) before changing this code. */ - -CORE_ADDR -hppa_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs, - struct value **args, struct type *type, int gcc_p) -{ - CORE_ADDR dyncall_addr; - struct minimal_symbol *msymbol; - struct minimal_symbol *trampoline; - int flags = read_register (FLAGS_REGNUM); - struct unwind_table_entry *u = NULL; - CORE_ADDR new_stub = 0; - CORE_ADDR solib_handle = 0; - - /* Nonzero if we will use GCC's PLT call routine. This routine must be - passed an import stub, not a PLABEL. It is also necessary to set %r19 - (the PIC register) before performing the call. - - If zero, then we are using __d_plt_call (HP's PLT call routine) or we - are calling the target directly. When using __d_plt_call we want to - use a PLABEL instead of an import stub. */ - int using_gcc_plt_call = 1; - -#ifdef GDB_TARGET_IS_HPPA_20W - /* We currently use completely different code for the PA2.0W inferior - function call sequences. This needs to be cleaned up. */ - { - CORE_ADDR pcsqh, pcsqt, pcoqh, pcoqt, sr5; - struct target_waitstatus w; - int inst1, inst2; - char buf[4]; - int status; - struct objfile *objfile; - - /* We can not modify the PC space queues directly, so we start - up the inferior and execute a couple instructions to set the - space queues so that they point to the call dummy in the stack. */ - pcsqh = read_register (PCSQ_HEAD_REGNUM); - sr5 = read_register (SR5_REGNUM); - if (1) - { - pcoqh = read_register (PCOQ_HEAD_REGNUM); - pcoqt = read_register (PCOQ_TAIL_REGNUM); - if (target_read_memory (pcoqh, buf, 4) != 0) - error ("Couldn't modify space queue\n"); - inst1 = extract_unsigned_integer (buf, 4); - - if (target_read_memory (pcoqt, buf, 4) != 0) - error ("Couldn't modify space queue\n"); - inst2 = extract_unsigned_integer (buf, 4); - - /* BVE (r1) */ - *((int *) buf) = 0xe820d000; - if (target_write_memory (pcoqh, buf, 4) != 0) - error ("Couldn't modify space queue\n"); - - /* NOP */ - *((int *) buf) = 0x08000240; - if (target_write_memory (pcoqt, buf, 4) != 0) - { - *((int *) buf) = inst1; - target_write_memory (pcoqh, buf, 4); - error ("Couldn't modify space queue\n"); - } - - write_register (1, pc); - - /* Single step twice, the BVE instruction will set the space queue - such that it points to the PC value written immediately above - (ie the call dummy). */ - resume (1, 0); - target_wait (inferior_ptid, &w); - resume (1, 0); - target_wait (inferior_ptid, &w); - - /* Restore the two instructions at the old PC locations. */ - *((int *) buf) = inst1; - target_write_memory (pcoqh, buf, 4); - *((int *) buf) = inst2; - target_write_memory (pcoqt, buf, 4); - } - - /* The call dummy wants the ultimate destination address initially - in register %r5. */ - write_register (5, fun); - - /* We need to see if this objfile has a different DP value than our - own (it could be a shared library for example). */ - ALL_OBJFILES (objfile) - { - struct obj_section *s; - obj_private_data_t *obj_private; - - /* See if FUN is in any section within this shared library. */ - for (s = objfile->sections; s < objfile->sections_end; s++) - if (s->addr <= fun && fun < s->endaddr) - break; - - if (s >= objfile->sections_end) - continue; - - obj_private = (obj_private_data_t *) objfile->obj_private; - - /* The DP value may be different for each objfile. But within an - objfile each function uses the same dp value. Thus we do not need - to grope around the opd section looking for dp values. - - ?!? This is not strictly correct since we may be in a shared library - and want to call back into the main program. To make that case - work correctly we need to set obj_private->dp for the main program's - objfile, then remove this conditional. */ - if (obj_private->dp) - write_register (27, obj_private->dp); - break; - } - return pc; - } -#endif - -#ifndef GDB_TARGET_IS_HPPA_20W - /* Prefer __gcc_plt_call over the HP supplied routine because - __gcc_plt_call works for any number of arguments. */ - trampoline = NULL; - if (lookup_minimal_symbol ("__gcc_plt_call", NULL, NULL) == NULL) - using_gcc_plt_call = 0; - - msymbol = lookup_minimal_symbol ("$$dyncall", NULL, NULL); - if (msymbol == NULL) - error ("Can't find an address for $$dyncall trampoline"); - - dyncall_addr = SYMBOL_VALUE_ADDRESS (msymbol); - - /* FUN could be a procedure label, in which case we have to get - its real address and the value of its GOT/DP if we plan to - call the routine via gcc_plt_call. */ - if ((fun & 0x2) && using_gcc_plt_call) - { - /* Get the GOT/DP value for the target function. It's - at *(fun+4). Note the call dummy is *NOT* allowed to - trash %r19 before calling the target function. */ - write_register (19, read_memory_integer ((fun & ~0x3) + 4, - DEPRECATED_REGISTER_SIZE)); - - /* Now get the real address for the function we are calling, it's - at *fun. */ - fun = (CORE_ADDR) read_memory_integer (fun & ~0x3, - TARGET_PTR_BIT / 8); - } - else - { - -#ifndef GDB_TARGET_IS_PA_ELF - /* FUN could be an export stub, the real address of a function, or - a PLABEL. When using gcc's PLT call routine we must call an import - stub rather than the export stub or real function for lazy binding - to work correctly - - If we are using the gcc PLT call routine, then we need to - get the import stub for the target function. */ - if (using_gcc_plt_call && som_solib_get_got_by_pc (fun)) - { - struct objfile *objfile; - struct minimal_symbol *funsymbol, *stub_symbol; - CORE_ADDR newfun = 0; - - funsymbol = lookup_minimal_symbol_by_pc (fun); - if (!funsymbol) - error ("Unable to find minimal symbol for target function.\n"); - - /* Search all the object files for an import symbol with the - right name. */ - ALL_OBJFILES (objfile) - { - stub_symbol - = lookup_minimal_symbol_solib_trampoline - (DEPRECATED_SYMBOL_NAME (funsymbol), objfile); - - if (!stub_symbol) - stub_symbol = lookup_minimal_symbol (DEPRECATED_SYMBOL_NAME (funsymbol), - NULL, objfile); - - /* Found a symbol with the right name. */ - if (stub_symbol) - { - struct unwind_table_entry *u; - /* It must be a shared library trampoline. */ - if (MSYMBOL_TYPE (stub_symbol) != mst_solib_trampoline) - continue; - - /* It must also be an import stub. */ - u = find_unwind_entry (SYMBOL_VALUE (stub_symbol)); - if (u == NULL - || (u->stub_unwind.stub_type != IMPORT -#ifdef GDB_NATIVE_HPUX_11 - /* Sigh. The hpux 10.20 dynamic linker will blow - chunks if we perform a call to an unbound function - via the IMPORT_SHLIB stub. The hpux 11.00 dynamic - linker will blow chunks if we do not call the - unbound function via the IMPORT_SHLIB stub. - - We currently have no way to select bevahior on just - the target. However, we only support HPUX/SOM in - native mode. So we conditinalize on a native - #ifdef. Ugly. Ugly. Ugly */ - && u->stub_unwind.stub_type != IMPORT_SHLIB -#endif - )) - continue; - - /* OK. Looks like the correct import stub. */ - newfun = SYMBOL_VALUE (stub_symbol); - fun = newfun; - - /* If we found an IMPORT stub, then we want to stop - searching now. If we found an IMPORT_SHLIB, we want - to continue the search in the hopes that we will find - an IMPORT stub. */ - if (u->stub_unwind.stub_type == IMPORT) - break; - } - } - - /* Ouch. We did not find an import stub. Make an attempt to - do the right thing instead of just croaking. Most of the - time this will actually work. */ - if (newfun == 0) - write_register (19, som_solib_get_got_by_pc (fun)); - - u = find_unwind_entry (fun); - if (u - && (u->stub_unwind.stub_type == IMPORT - || u->stub_unwind.stub_type == IMPORT_SHLIB)) - trampoline = lookup_minimal_symbol ("__gcc_plt_call", NULL, NULL); - - /* If we found the import stub in the shared library, then we have - to set %r19 before we call the stub. */ - if (u && u->stub_unwind.stub_type == IMPORT_SHLIB) - write_register (19, som_solib_get_got_by_pc (fun)); - } -#endif - } - - /* If we are calling into another load module then have sr4export call the - magic __d_plt_call routine which is linked in from end.o. - - You can't use _sr4export to make the call as the value in sp-24 will get - fried and you end up returning to the wrong location. You can't call the - target as the code to bind the PLT entry to a function can't return to a - stack address. - - Also, query the dynamic linker in the inferior to provide a suitable - PLABEL for the target function. */ - if (!using_gcc_plt_call) - { - CORE_ADDR new_fun; - - /* Get a handle for the shared library containing FUN. Given the - handle we can query the shared library for a PLABEL. */ - solib_handle = som_solib_get_solib_by_pc (fun); - - if (solib_handle) - { - struct minimal_symbol *fmsymbol = lookup_minimal_symbol_by_pc (fun); - - trampoline = lookup_minimal_symbol ("__d_plt_call", NULL, NULL); - - if (trampoline == NULL) - { - error ("Can't find an address for __d_plt_call or __gcc_plt_call trampoline\nSuggest linking executable with -g or compiling with gcc."); - } - - /* This is where sr4export will jump to. */ - new_fun = SYMBOL_VALUE_ADDRESS (trampoline); - - /* If the function is in a shared library, then call __d_shl_get to - get a PLABEL for the target function. */ - new_stub = find_stub_with_shl_get (fmsymbol, solib_handle); - - if (new_stub == 0) - error ("Can't find an import stub for %s", DEPRECATED_SYMBOL_NAME (fmsymbol)); - - /* We have to store the address of the stub in __shlib_funcptr. */ - msymbol = lookup_minimal_symbol ("__shlib_funcptr", NULL, - (struct objfile *) NULL); - - if (msymbol == NULL) - error ("Can't find an address for __shlib_funcptr"); - target_write_memory (SYMBOL_VALUE_ADDRESS (msymbol), - (char *) &new_stub, 4); - - /* We want sr4export to call __d_plt_call, so we claim it is - the final target. Clear trampoline. */ - fun = new_fun; - trampoline = NULL; - } - } - - /* Store upper 21 bits of function address into ldil. fun will either be - the final target (most cases) or __d_plt_call when calling into a shared - library and __gcc_plt_call is not available. */ - store_unsigned_integer - (&dummy[FUNC_LDIL_OFFSET], - INSTRUCTION_SIZE, - deposit_21 (fun >> 11, - extract_unsigned_integer (&dummy[FUNC_LDIL_OFFSET], - INSTRUCTION_SIZE))); - - /* Store lower 11 bits of function address into ldo */ - store_unsigned_integer - (&dummy[FUNC_LDO_OFFSET], - INSTRUCTION_SIZE, - deposit_14 (fun & MASK_11, - extract_unsigned_integer (&dummy[FUNC_LDO_OFFSET], - INSTRUCTION_SIZE))); -#ifdef SR4EXPORT_LDIL_OFFSET - - { - CORE_ADDR trampoline_addr; - - /* We may still need sr4export's address too. */ - - if (trampoline == NULL) - { - msymbol = lookup_minimal_symbol ("_sr4export", NULL, NULL); - if (msymbol == NULL) - error ("Can't find an address for _sr4export trampoline"); - - trampoline_addr = SYMBOL_VALUE_ADDRESS (msymbol); - } - else - trampoline_addr = SYMBOL_VALUE_ADDRESS (trampoline); - - - /* Store upper 21 bits of trampoline's address into ldil */ - store_unsigned_integer - (&dummy[SR4EXPORT_LDIL_OFFSET], - INSTRUCTION_SIZE, - deposit_21 (trampoline_addr >> 11, - extract_unsigned_integer (&dummy[SR4EXPORT_LDIL_OFFSET], - INSTRUCTION_SIZE))); - - /* Store lower 11 bits of trampoline's address into ldo */ - store_unsigned_integer - (&dummy[SR4EXPORT_LDO_OFFSET], - INSTRUCTION_SIZE, - deposit_14 (trampoline_addr & MASK_11, - extract_unsigned_integer (&dummy[SR4EXPORT_LDO_OFFSET], - INSTRUCTION_SIZE))); - } -#endif - - write_register (22, pc); - - /* If we are in a syscall, then we should call the stack dummy - directly. $$dyncall is not needed as the kernel sets up the - space id registers properly based on the value in %r31. In - fact calling $$dyncall will not work because the value in %r22 - will be clobbered on the syscall exit path. - - Similarly if the current PC is in a shared library. Note however, - this scheme won't work if the shared library isn't mapped into - the same space as the stack. */ - if (flags & 2) - return pc; -#ifndef GDB_TARGET_IS_PA_ELF - else if (som_solib_get_got_by_pc (hppa_target_read_pc (inferior_ptid))) - return pc; -#endif - else - return dyncall_addr; -#endif -} - -/* If the pid is in a syscall, then the FP register is not readable. - We'll return zero in that case, rather than attempting to read it - and cause a warning. */ - -CORE_ADDR -hppa_read_fp (int pid) -{ - int flags = read_register (FLAGS_REGNUM); - - if (flags & 2) - { - return (CORE_ADDR) 0; - } - - /* This is the only site that may directly read_register () the FP - register. All others must use deprecated_read_fp (). */ - return read_register (DEPRECATED_FP_REGNUM); -} - -CORE_ADDR -hppa_target_read_fp (void) -{ - return hppa_read_fp (PIDGET (inferior_ptid)); -} - -/* Get the PC from %r31 if currently in a syscall. Also mask out privilege - bits. */ - -CORE_ADDR -hppa_target_read_pc (ptid_t ptid) -{ - int flags = read_register_pid (FLAGS_REGNUM, ptid); - - /* The following test does not belong here. It is OS-specific, and belongs - in native code. */ - /* Test SS_INSYSCALL */ - if (flags & 2) - return read_register_pid (31, ptid) & ~0x3; - - return read_register_pid (PC_REGNUM, ptid) & ~0x3; -} - -/* Write out the PC. If currently in a syscall, then also write the new - PC value into %r31. */ - -void -hppa_target_write_pc (CORE_ADDR v, ptid_t ptid) -{ - int flags = read_register_pid (FLAGS_REGNUM, ptid); - - /* The following test does not belong here. It is OS-specific, and belongs - in native code. */ - /* If in a syscall, then set %r31. Also make sure to get the - privilege bits set correctly. */ - /* Test SS_INSYSCALL */ - if (flags & 2) - write_register_pid (31, v | 0x3, ptid); - - write_register_pid (PC_REGNUM, v, ptid); - write_register_pid (PCOQ_TAIL_REGNUM, v + 4, ptid); -} - -/* return the alignment of a type in bytes. Structures have the maximum - alignment required by their fields. */ - -static int -hppa_alignof (struct type *type) -{ - int max_align, align, i; - CHECK_TYPEDEF (type); - switch (TYPE_CODE (type)) - { - case TYPE_CODE_PTR: - case TYPE_CODE_INT: - case TYPE_CODE_FLT: - return TYPE_LENGTH (type); - case TYPE_CODE_ARRAY: - return hppa_alignof (TYPE_FIELD_TYPE (type, 0)); - case TYPE_CODE_STRUCT: - case TYPE_CODE_UNION: - max_align = 1; - for (i = 0; i < TYPE_NFIELDS (type); i++) - { - /* Bit fields have no real alignment. */ - /* if (!TYPE_FIELD_BITPOS (type, i)) */ - if (!TYPE_FIELD_BITSIZE (type, i)) /* elz: this should be bitsize */ - { - align = hppa_alignof (TYPE_FIELD_TYPE (type, i)); - max_align = max (max_align, align); - } - } - return max_align; - default: - return 4; - } -} - -/* Print the register regnum, or all registers if regnum is -1 */ - -void -pa_do_registers_info (int regnum, int fpregs) -{ - char *raw_regs = alloca (DEPRECATED_REGISTER_BYTES); - int i; - - /* Make a copy of gdb's save area (may cause actual - reads from the target). */ - for (i = 0; i < NUM_REGS; i++) - frame_register_read (deprecated_selected_frame, i, - raw_regs + DEPRECATED_REGISTER_BYTE (i)); - - if (regnum == -1) - pa_print_registers (raw_regs, regnum, fpregs); - else if (regnum < FP4_REGNUM) - { - long reg_val[2]; - - /* Why is the value not passed through "extract_signed_integer" - as in "pa_print_registers" below? */ - pa_register_look_aside (raw_regs, regnum, ®_val[0]); - - if (!is_pa_2) - { - printf_unfiltered ("%s %lx\n", REGISTER_NAME (regnum), reg_val[1]); - } - else - { - /* Fancy % formats to prevent leading zeros. */ - if (reg_val[0] == 0) - printf_unfiltered ("%s %lx\n", REGISTER_NAME (regnum), reg_val[1]); - else - printf_unfiltered ("%s %lx%8.8lx\n", REGISTER_NAME (regnum), - reg_val[0], reg_val[1]); - } - } - else - /* Note that real floating point values only start at - FP4_REGNUM. FP0 and up are just status and error - registers, which have integral (bit) values. */ - pa_print_fp_reg (regnum); -} - -/********** new function ********************/ -void -pa_do_strcat_registers_info (int regnum, int fpregs, struct ui_file *stream, - enum precision_type precision) -{ - char *raw_regs = alloca (DEPRECATED_REGISTER_BYTES); - int i; - - /* Make a copy of gdb's save area (may cause actual - reads from the target). */ - for (i = 0; i < NUM_REGS; i++) - frame_register_read (deprecated_selected_frame, i, - raw_regs + DEPRECATED_REGISTER_BYTE (i)); - - if (regnum == -1) - pa_strcat_registers (raw_regs, regnum, fpregs, stream); - - else if (regnum < FP4_REGNUM) - { - long reg_val[2]; - - /* Why is the value not passed through "extract_signed_integer" - as in "pa_print_registers" below? */ - pa_register_look_aside (raw_regs, regnum, ®_val[0]); - - if (!is_pa_2) - { - fprintf_unfiltered (stream, "%s %lx", REGISTER_NAME (regnum), reg_val[1]); - } - else - { - /* Fancy % formats to prevent leading zeros. */ - if (reg_val[0] == 0) - fprintf_unfiltered (stream, "%s %lx", REGISTER_NAME (regnum), - reg_val[1]); - else - fprintf_unfiltered (stream, "%s %lx%8.8lx", REGISTER_NAME (regnum), - reg_val[0], reg_val[1]); - } - } - else - /* Note that real floating point values only start at - FP4_REGNUM. FP0 and up are just status and error - registers, which have integral (bit) values. */ - pa_strcat_fp_reg (regnum, stream, precision); -} - -/* If this is a PA2.0 machine, fetch the real 64-bit register - value. Otherwise use the info from gdb's saved register area. - - Note that reg_val is really expected to be an array of longs, - with two elements. */ -static void -pa_register_look_aside (char *raw_regs, int regnum, long *raw_val) -{ - static int know_which = 0; /* False */ - - int regaddr; - unsigned int offset; - int i; - int start; - - - char buf[MAX_REGISTER_SIZE]; - long long reg_val; - - if (!know_which) - { - if (CPU_PA_RISC2_0 == sysconf (_SC_CPU_VERSION)) - { - is_pa_2 = (1 == 1); - } - - know_which = 1; /* True */ - } - - raw_val[0] = 0; - raw_val[1] = 0; - - if (!is_pa_2) - { - raw_val[1] = *(long *) (raw_regs + DEPRECATED_REGISTER_BYTE (regnum)); - return; - } - - /* Code below copied from hppah-nat.c, with fixes for wide - registers, using different area of save_state, etc. */ - if (regnum == FLAGS_REGNUM || regnum >= FP0_REGNUM || - !HAVE_STRUCT_SAVE_STATE_T || !HAVE_STRUCT_MEMBER_SS_WIDE) - { - /* Use narrow regs area of save_state and default macro. */ - offset = U_REGS_OFFSET; - regaddr = register_addr (regnum, offset); - start = 1; - } - else - { - /* Use wide regs area, and calculate registers as 8 bytes wide. - - We'd like to do this, but current version of "C" doesn't - permit "offsetof": - - offset = offsetof(save_state_t, ss_wide); - - Note that to avoid "C" doing typed pointer arithmetic, we - have to cast away the type in our offset calculation: - otherwise we get an offset of 1! */ - - /* NB: save_state_t is not available before HPUX 9. - The ss_wide field is not available previous to HPUX 10.20, - so to avoid compile-time warnings, we only compile this for - PA 2.0 processors. This control path should only be followed - if we're debugging a PA 2.0 processor, so this should not cause - problems. */ - - /* #if the following code out so that this file can still be - compiled on older HPUX boxes (< 10.20) which don't have - this structure/structure member. */ -#if HAVE_STRUCT_SAVE_STATE_T == 1 && HAVE_STRUCT_MEMBER_SS_WIDE == 1 - save_state_t temp; - - offset = ((int) &temp.ss_wide) - ((int) &temp); - regaddr = offset + regnum * 8; - start = 0; -#endif - } - - for (i = start; i < 2; i++) - { - errno = 0; - raw_val[i] = call_ptrace (PT_RUREGS, PIDGET (inferior_ptid), - (PTRACE_ARG3_TYPE) regaddr, 0); - if (errno != 0) - { - /* Warning, not error, in case we are attached; sometimes the - kernel doesn't let us at the registers. */ - char *err = safe_strerror (errno); - char *msg = alloca (strlen (err) + 128); - sprintf (msg, "reading register %s: %s", REGISTER_NAME (regnum), err); - warning (msg); - goto error_exit; - } - - regaddr += sizeof (long); - } - - if (regnum == PCOQ_HEAD_REGNUM || regnum == PCOQ_TAIL_REGNUM) - raw_val[1] &= ~0x3; /* I think we're masking out space bits */ - -error_exit: - ; -} - -/* "Info all-reg" command */ - -static void -pa_print_registers (char *raw_regs, int regnum, int fpregs) -{ - int i, j; - /* Alas, we are compiled so that "long long" is 32 bits */ - long raw_val[2]; - long long_val; - int rows = 48, columns = 2; - - for (i = 0; i < rows; i++) - { - for (j = 0; j < columns; j++) - { - /* We display registers in column-major order. */ - int regnum = i + j * rows; - - /* Q: Why is the value passed through "extract_signed_integer", - while above, in "pa_do_registers_info" it isn't? - A: ? */ - pa_register_look_aside (raw_regs, regnum, &raw_val[0]); - - /* Even fancier % formats to prevent leading zeros - and still maintain the output in columns. */ - if (!is_pa_2) - { - /* Being big-endian, on this machine the low bits - (the ones we want to look at) are in the second longword. */ - long_val = extract_signed_integer (&raw_val[1], 4); - printf_filtered ("%10.10s: %8lx ", - REGISTER_NAME (regnum), long_val); - } - else - { - /* raw_val = extract_signed_integer(&raw_val, 8); */ - if (raw_val[0] == 0) - printf_filtered ("%10.10s: %8lx ", - REGISTER_NAME (regnum), raw_val[1]); - else - printf_filtered ("%10.10s: %8lx%8.8lx ", - REGISTER_NAME (regnum), - raw_val[0], raw_val[1]); - } - } - printf_unfiltered ("\n"); - } - - if (fpregs) - for (i = FP4_REGNUM; i < NUM_REGS; i++) /* FP4_REGNUM == 72 */ - pa_print_fp_reg (i); -} - -/************* new function ******************/ -static void -pa_strcat_registers (char *raw_regs, int regnum, int fpregs, - struct ui_file *stream) -{ - int i, j; - long raw_val[2]; /* Alas, we are compiled so that "long long" is 32 bits */ - long long_val; - enum precision_type precision; - - precision = unspecified_precision; - - for (i = 0; i < 18; i++) - { - for (j = 0; j < 4; j++) - { - /* Q: Why is the value passed through "extract_signed_integer", - while above, in "pa_do_registers_info" it isn't? - A: ? */ - pa_register_look_aside (raw_regs, i + (j * 18), &raw_val[0]); - - /* Even fancier % formats to prevent leading zeros - and still maintain the output in columns. */ - if (!is_pa_2) - { - /* Being big-endian, on this machine the low bits - (the ones we want to look at) are in the second longword. */ - long_val = extract_signed_integer (&raw_val[1], 4); - fprintf_filtered (stream, "%8.8s: %8lx ", - REGISTER_NAME (i + (j * 18)), long_val); - } - else - { - /* raw_val = extract_signed_integer(&raw_val, 8); */ - if (raw_val[0] == 0) - fprintf_filtered (stream, "%8.8s: %8lx ", - REGISTER_NAME (i + (j * 18)), raw_val[1]); - else - fprintf_filtered (stream, "%8.8s: %8lx%8.8lx ", - REGISTER_NAME (i + (j * 18)), raw_val[0], - raw_val[1]); - } - } - fprintf_unfiltered (stream, "\n"); - } - - if (fpregs) - for (i = FP4_REGNUM; i < NUM_REGS; i++) /* FP4_REGNUM == 72 */ - pa_strcat_fp_reg (i, stream, precision); -} - -static void -pa_print_fp_reg (int i) -{ - char raw_buffer[MAX_REGISTER_SIZE]; - char virtual_buffer[MAX_REGISTER_SIZE]; - - /* Get 32bits of data. */ - frame_register_read (deprecated_selected_frame, i, raw_buffer); - - /* Put it in the buffer. No conversions are ever necessary. */ - memcpy (virtual_buffer, raw_buffer, DEPRECATED_REGISTER_RAW_SIZE (i)); + args[0] = value_from_longest (TYPE_FIELD_TYPE (ftype, 0), 12); + args[1] = value_from_pointer (TYPE_FIELD_TYPE (ftype, 1), SYMBOL_VALUE_ADDRESS (msymbol)); + args[2] = value_from_pointer (TYPE_FIELD_TYPE (ftype, 2), endo_buff_addr); + args[3] = value_from_longest (TYPE_FIELD_TYPE (ftype, 3), TYPE_PROCEDURE); + args[4] = value_from_pointer (TYPE_FIELD_TYPE (ftype, 4), value_return_addr); + args[5] = value_from_pointer (TYPE_FIELD_TYPE (ftype, 5), errno_return_addr); - fputs_filtered (REGISTER_NAME (i), gdb_stdout); - print_spaces_filtered (8 - strlen (REGISTER_NAME (i)), gdb_stdout); - fputs_filtered ("(single precision) ", gdb_stdout); + /* now call the function */ - val_print (DEPRECATED_REGISTER_VIRTUAL_TYPE (i), virtual_buffer, 0, 0, gdb_stdout, 0, - 1, 0, Val_pretty_default); - printf_filtered ("\n"); + val = call_function_by_hand (funcval, 6, args); - /* If "i" is even, then this register can also be a double-precision - FP register. Dump it out as such. */ - if ((i % 2) == 0) - { - /* Get the data in raw format for the 2nd half. */ - frame_register_read (deprecated_selected_frame, i + 1, raw_buffer); + /* now get the results */ - /* Copy it into the appropriate part of the virtual buffer. */ - memcpy (virtual_buffer + DEPRECATED_REGISTER_RAW_SIZE (i), raw_buffer, - DEPRECATED_REGISTER_RAW_SIZE (i)); + target_read_memory (errno_return_addr, (char *) &err_value, sizeof (err_value)); - /* Dump it as a double. */ - fputs_filtered (REGISTER_NAME (i), gdb_stdout); - print_spaces_filtered (8 - strlen (REGISTER_NAME (i)), gdb_stdout); - fputs_filtered ("(double precision) ", gdb_stdout); + target_read_memory (value_return_addr, (char *) &stub_addr, sizeof (stub_addr)); + if (stub_addr <= 0) + error ("call to __d_shl_get failed, error code is %d", err_value); - val_print (builtin_type_double, virtual_buffer, 0, 0, gdb_stdout, 0, - 1, 0, Val_pretty_default); - printf_filtered ("\n"); - } + return (stub_addr); } -/*************** new function ***********************/ -static void -pa_strcat_fp_reg (int i, struct ui_file *stream, enum precision_type precision) +/* Cover routine for find_stub_with_shl_get to pass to catch_errors */ +static int +cover_find_stub_with_shl_get (void *args_untyped) { - char raw_buffer[MAX_REGISTER_SIZE]; - char virtual_buffer[MAX_REGISTER_SIZE]; + args_for_find_stub *args = args_untyped; + args->return_val = find_stub_with_shl_get (args->msym, args->solib_handle); + return 0; +} + +/* Get the PC from %r31 if currently in a syscall. Also mask out privilege + bits. */ - fputs_filtered (REGISTER_NAME (i), stream); - print_spaces_filtered (8 - strlen (REGISTER_NAME (i)), stream); +CORE_ADDR +hppa_target_read_pc (ptid_t ptid) +{ + int flags = read_register_pid (FLAGS_REGNUM, ptid); - /* Get 32bits of data. */ - frame_register_read (deprecated_selected_frame, i, raw_buffer); + /* The following test does not belong here. It is OS-specific, and belongs + in native code. */ + /* Test SS_INSYSCALL */ + if (flags & 2) + return read_register_pid (31, ptid) & ~0x3; - /* Put it in the buffer. No conversions are ever necessary. */ - memcpy (virtual_buffer, raw_buffer, DEPRECATED_REGISTER_RAW_SIZE (i)); + return read_register_pid (PCOQ_HEAD_REGNUM, ptid) & ~0x3; +} - if (precision == double_precision && (i % 2) == 0) - { +/* Write out the PC. If currently in a syscall, then also write the new + PC value into %r31. */ - char raw_buf[MAX_REGISTER_SIZE]; +void +hppa_target_write_pc (CORE_ADDR v, ptid_t ptid) +{ + int flags = read_register_pid (FLAGS_REGNUM, ptid); - /* Get the data in raw format for the 2nd half. */ - frame_register_read (deprecated_selected_frame, i + 1, raw_buf); + /* The following test does not belong here. It is OS-specific, and belongs + in native code. */ + /* If in a syscall, then set %r31. Also make sure to get the + privilege bits set correctly. */ + /* Test SS_INSYSCALL */ + if (flags & 2) + write_register_pid (31, v | 0x3, ptid); - /* Copy it into the appropriate part of the virtual buffer. */ - memcpy (virtual_buffer + DEPRECATED_REGISTER_RAW_SIZE (i), raw_buf, - DEPRECATED_REGISTER_RAW_SIZE (i)); + write_register_pid (PCOQ_HEAD_REGNUM, v, ptid); + write_register_pid (PCOQ_TAIL_REGNUM, v + 4, ptid); +} - val_print (builtin_type_double, virtual_buffer, 0, 0, stream, 0, - 1, 0, Val_pretty_default); +/* return the alignment of a type in bytes. Structures have the maximum + alignment required by their fields. */ - } - else +static int +hppa_alignof (struct type *type) +{ + int max_align, align, i; + CHECK_TYPEDEF (type); + switch (TYPE_CODE (type)) { - val_print (DEPRECATED_REGISTER_VIRTUAL_TYPE (i), virtual_buffer, 0, 0, stream, 0, - 1, 0, Val_pretty_default); + case TYPE_CODE_PTR: + case TYPE_CODE_INT: + case TYPE_CODE_FLT: + return TYPE_LENGTH (type); + case TYPE_CODE_ARRAY: + return hppa_alignof (TYPE_FIELD_TYPE (type, 0)); + case TYPE_CODE_STRUCT: + case TYPE_CODE_UNION: + max_align = 1; + for (i = 0; i < TYPE_NFIELDS (type); i++) + { + /* Bit fields have no real alignment. */ + /* if (!TYPE_FIELD_BITPOS (type, i)) */ + if (!TYPE_FIELD_BITSIZE (type, i)) /* elz: this should be bitsize */ + { + align = hppa_alignof (TYPE_FIELD_TYPE (type, i)); + max_align = max (max_align, align); + } + } + return max_align; + default: + return 4; } - } /* Return one if PC is in the call path of a trampoline, else return zero. @@ -3861,7 +1695,7 @@ hppa_skip_trampoline_code (CORE_ADDR pc) rp from sp - 8. */ if (prev_inst == 0x4bc23ff1) return (read_memory_integer - (read_register (SP_REGNUM) - 8, 4)) & ~0x3; + (read_register (HPPA_SP_REGNUM) - 8, 4)) & ~0x3; else { warning ("Unable to find restore of %%rp before bv (%%rp)."); @@ -3875,7 +1709,7 @@ hppa_skip_trampoline_code (CORE_ADDR pc) else if ((curr_inst & 0xffe0f000) == 0xe840d000) { return (read_memory_integer - (read_register (SP_REGNUM) - 24, TARGET_PTR_BIT / 8)) & ~0x3; + (read_register (HPPA_SP_REGNUM) - 24, TARGET_PTR_BIT / 8)) & ~0x3; } /* What about be,n 0(sr0,%rp)? It's just another way we return to @@ -3887,7 +1721,7 @@ hppa_skip_trampoline_code (CORE_ADDR pc) I guess we could check for the previous instruction being mtsp %r1,%sr0 if we want to do sanity checking. */ return (read_memory_integer - (read_register (SP_REGNUM) - 24, TARGET_PTR_BIT / 8)) & ~0x3; + (read_register (HPPA_SP_REGNUM) - 24, TARGET_PTR_BIT / 8)) & ~0x3; } /* Haven't found the branch yet, but we're still in the stub. @@ -4074,7 +1908,7 @@ restart: for (i = 3; i < u->Entry_GR + 3; i++) { /* Frame pointer gets saved into a special location. */ - if (u->Save_SP && i == DEPRECATED_FP_REGNUM) + if (u->Save_SP && i == HPPA_FP_REGNUM) continue; save_gr |= (1 << i); @@ -4335,262 +2169,6 @@ hppa_skip_prologue (CORE_ADDR pc) return (skip_prologue_hard_way (pc)); } -/* Put here the code to store, into the SAVED_REGS, the addresses of - the saved registers of frame described by FRAME_INFO. This - includes special registers such as pc and fp saved in special ways - in the stack frame. sp is even more special: the address we return - for it IS the sp for the next frame. */ - -void -hppa_frame_find_saved_regs (struct frame_info *frame_info, - CORE_ADDR frame_saved_regs[]) -{ - CORE_ADDR pc; - struct unwind_table_entry *u; - unsigned long inst, stack_remaining, save_gr, save_fr, save_rp, save_sp; - int status, i, reg; - char buf[4]; - int fp_loc = -1; - int final_iteration; - - /* Zero out everything. */ - memset (frame_saved_regs, '\0', SIZEOF_FRAME_SAVED_REGS); - - /* Call dummy frames always look the same, so there's no need to - examine the dummy code to determine locations of saved registers; - instead, let find_dummy_frame_regs fill in the correct offsets - for the saved registers. */ - if ((get_frame_pc (frame_info) >= get_frame_base (frame_info) - && (get_frame_pc (frame_info) - <= (get_frame_base (frame_info) - /* A call dummy is sized in words, but it is actually a - series of instructions. Account for that scaling - factor. */ - + ((DEPRECATED_REGISTER_SIZE / INSTRUCTION_SIZE) - * DEPRECATED_CALL_DUMMY_LENGTH) - /* Similarly we have to account for 64bit wide register - saves. */ - + (32 * DEPRECATED_REGISTER_SIZE) - /* We always consider FP regs 8 bytes long. */ - + (NUM_REGS - FP0_REGNUM) * 8 - /* Similarly we have to account for 64bit wide register - saves. */ - + (6 * DEPRECATED_REGISTER_SIZE))))) - find_dummy_frame_regs (frame_info, frame_saved_regs); - - /* Interrupt handlers are special too. They lay out the register - state in the exact same order as the register numbers in GDB. */ - if (pc_in_interrupt_handler (get_frame_pc (frame_info))) - { - for (i = 0; i < NUM_REGS; i++) - { - /* SP is a little special. */ - if (i == SP_REGNUM) - frame_saved_regs[SP_REGNUM] - = read_memory_integer (get_frame_base (frame_info) + SP_REGNUM * 4, - TARGET_PTR_BIT / 8); - else - frame_saved_regs[i] = get_frame_base (frame_info) + i * 4; - } - return; - } - -#ifdef FRAME_FIND_SAVED_REGS_IN_SIGTRAMP - /* Handle signal handler callers. */ - if ((get_frame_type (frame_info) == SIGTRAMP_FRAME)) - { - FRAME_FIND_SAVED_REGS_IN_SIGTRAMP (frame_info, frame_saved_regs); - return; - } -#endif - - /* Get the starting address of the function referred to by the PC - saved in frame. */ - pc = get_frame_func (frame_info); - - /* Yow! */ - u = find_unwind_entry (pc); - if (!u) - return; - - /* This is how much of a frame adjustment we need to account for. */ - stack_remaining = u->Total_frame_size << 3; - - /* Magic register saves we want to know about. */ - save_rp = u->Save_RP; - save_sp = u->Save_SP; - - /* Turn the Entry_GR field into a bitmask. */ - save_gr = 0; - for (i = 3; i < u->Entry_GR + 3; i++) - { - /* Frame pointer gets saved into a special location. */ - if (u->Save_SP && i == DEPRECATED_FP_REGNUM) - continue; - - save_gr |= (1 << i); - } - - /* Turn the Entry_FR field into a bitmask too. */ - save_fr = 0; - for (i = 12; i < u->Entry_FR + 12; i++) - save_fr |= (1 << i); - - /* The frame always represents the value of %sp at entry to the - current function (and is thus equivalent to the "saved" stack - pointer. */ - frame_saved_regs[SP_REGNUM] = get_frame_base (frame_info); - - /* Loop until we find everything of interest or hit a branch. - - For unoptimized GCC code and for any HP CC code this will never ever - examine any user instructions. - - For optimized GCC code we're faced with problems. GCC will schedule - its prologue and make prologue instructions available for delay slot - filling. The end result is user code gets mixed in with the prologue - and a prologue instruction may be in the delay slot of the first branch - or call. - - Some unexpected things are expected with debugging optimized code, so - we allow this routine to walk past user instructions in optimized - GCC code. */ - final_iteration = 0; - while ((save_gr || save_fr || save_rp || save_sp || stack_remaining > 0) - && pc <= get_frame_pc (frame_info)) - { - status = target_read_memory (pc, buf, 4); - inst = extract_unsigned_integer (buf, 4); - - /* Yow! */ - if (status != 0) - return; - - /* Note the interesting effects of this instruction. */ - stack_remaining -= prologue_inst_adjust_sp (inst); - - /* There are limited ways to store the return pointer into the - stack. */ - if (inst == 0x6bc23fd9) /* stw rp,-0x14(sr0,sp) */ - { - save_rp = 0; - frame_saved_regs[RP_REGNUM] = get_frame_base (frame_info) - 20; - } - else if (inst == 0x0fc212c1) /* std rp,-0x10(sr0,sp) */ - { - save_rp = 0; - frame_saved_regs[RP_REGNUM] = get_frame_base (frame_info) - 16; - } - - /* Note if we saved SP into the stack. This also happens to indicate - the location of the saved frame pointer. */ - if ( (inst & 0xffffc000) == 0x6fc10000 /* stw,ma r1,N(sr0,sp) */ - || (inst & 0xffffc00c) == 0x73c10008) /* std,ma r1,N(sr0,sp) */ - { - frame_saved_regs[DEPRECATED_FP_REGNUM] = get_frame_base (frame_info); - save_sp = 0; - } - - /* Account for general and floating-point register saves. */ - reg = inst_saves_gr (inst); - if (reg >= 3 && reg <= 18 - && (!u->Save_SP || reg != DEPRECATED_FP_REGNUM)) - { - save_gr &= ~(1 << reg); - - /* stwm with a positive displacement is a *post modify*. */ - if ((inst >> 26) == 0x1b - && extract_14 (inst) >= 0) - frame_saved_regs[reg] = get_frame_base (frame_info); - /* A std has explicit post_modify forms. */ - else if ((inst & 0xfc00000c) == 0x70000008) - frame_saved_regs[reg] = get_frame_base (frame_info); - else - { - CORE_ADDR offset; - - if ((inst >> 26) == 0x1c) - offset = (inst & 0x1 ? -1 << 13 : 0) | (((inst >> 4) & 0x3ff) << 3); - else if ((inst >> 26) == 0x03) - offset = low_sign_extend (inst & 0x1f, 5); - else - offset = extract_14 (inst); - - /* Handle code with and without frame pointers. */ - if (u->Save_SP) - frame_saved_regs[reg] - = get_frame_base (frame_info) + offset; - else - frame_saved_regs[reg] - = (get_frame_base (frame_info) + (u->Total_frame_size << 3) - + offset); - } - } - - - /* GCC handles callee saved FP regs a little differently. - - It emits an instruction to put the value of the start of - the FP store area into %r1. It then uses fstds,ma with - a basereg of %r1 for the stores. - - HP CC emits them at the current stack pointer modifying - the stack pointer as it stores each register. */ - - /* ldo X(%r3),%r1 or ldo X(%r30),%r1. */ - if ((inst & 0xffffc000) == 0x34610000 - || (inst & 0xffffc000) == 0x37c10000) - fp_loc = extract_14 (inst); - - reg = inst_saves_fr (inst); - if (reg >= 12 && reg <= 21) - { - /* Note +4 braindamage below is necessary because the FP status - registers are internally 8 registers rather than the expected - 4 registers. */ - save_fr &= ~(1 << reg); - if (fp_loc == -1) - { - /* 1st HP CC FP register store. After this instruction - we've set enough state that the GCC and HPCC code are - both handled in the same manner. */ - frame_saved_regs[reg + FP4_REGNUM + 4] = get_frame_base (frame_info); - fp_loc = 8; - } - else - { - frame_saved_regs[reg + FP0_REGNUM + 4] - = get_frame_base (frame_info) + fp_loc; - fp_loc += 8; - } - } - - /* Quit if we hit any kind of branch the previous iteration. */ - if (final_iteration) - break; - - /* We want to look precisely one instruction beyond the branch - if we have not found everything yet. */ - if (is_branch (inst)) - final_iteration = 1; - - /* Bump the PC. */ - pc += 4; - } -} - -/* XXX - deprecated. This is a compatibility function for targets - that do not yet implement DEPRECATED_FRAME_INIT_SAVED_REGS. */ -/* Find the addresses in which registers are saved in FRAME. */ - -static void -hppa_frame_init_saved_regs (struct frame_info *frame) -{ - if (deprecated_get_frame_saved_regs (frame) == NULL) - frame_saved_regs_zalloc (frame); - hppa_frame_find_saved_regs (frame, deprecated_get_frame_saved_regs (frame)); -} - struct hppa_frame_cache { CORE_ADDR base; @@ -4617,14 +2195,14 @@ hppa_frame_cache (struct frame_info *next_frame, void **this_cache) /* Yow! */ u = find_unwind_entry (frame_func_unwind (next_frame)); if (!u) - return; + return (*this_cache); /* Turn the Entry_GR field into a bitmask. */ saved_gr_mask = 0; for (i = 3; i < u->Entry_GR + 3; i++) { /* Frame pointer gets saved into a special location. */ - if (u->Save_SP && i == DEPRECATED_FP_REGNUM) + if (u->Save_SP && i == HPPA_FP_REGNUM) continue; saved_gr_mask |= (1 << i); @@ -4694,13 +2272,13 @@ hppa_frame_cache (struct frame_info *next_frame, void **this_cache) || (inst & 0xffffc00c) == 0x73c10008) /* std,ma r1,N(sr0,sp) */ { looking_for_sp = 0; - cache->saved_regs[DEPRECATED_FP_REGNUM].addr = 0; + cache->saved_regs[HPPA_FP_REGNUM].addr = 0; } /* Account for general and floating-point register saves. */ reg = inst_saves_gr (inst); if (reg >= 3 && reg <= 18 - && (!u->Save_SP || reg != DEPRECATED_FP_REGNUM)) + && (!u->Save_SP || reg != HPPA_FP_REGNUM)) { saved_gr_mask &= ~(1 << reg); if ((inst >> 26) == 0x1b && extract_14 (inst) >= 0) @@ -4760,7 +2338,7 @@ hppa_frame_cache (struct frame_info *next_frame, void **this_cache) } else { - cache->saved_regs[reg + FP0_REGNUM + 4].addr = fp_loc; + cache->saved_regs[reg + HPPA_FP0_REGNUM + 4].addr = fp_loc; fp_loc += 8; } } @@ -4779,10 +2357,10 @@ hppa_frame_cache (struct frame_info *next_frame, void **this_cache) /* The frame base always represents the value of %sp at entry to the current function (and is thus equivalent to the "saved" stack pointer. */ - CORE_ADDR this_sp = frame_unwind_register_unsigned (next_frame, SP_REGNUM); + CORE_ADDR this_sp = frame_unwind_register_unsigned (next_frame, HPPA_SP_REGNUM); /* FIXME: cagney/2004-02-22: This assumes that the frame has been created. If it hasn't everything will be out-of-wack. */ - if (u->Save_SP && trad_frame_addr_p (cache->saved_regs, SP_REGNUM)) + if (u->Save_SP && trad_frame_addr_p (cache->saved_regs, HPPA_SP_REGNUM)) /* Both we're expecting the SP to be saved and the SP has been saved. The entry SP value is saved at this frame's SP address. */ @@ -4791,7 +2369,7 @@ hppa_frame_cache (struct frame_info *next_frame, void **this_cache) /* The prologue has been slowly allocating stack space. Adjust the SP back. */ cache->base = this_sp - frame_size; - trad_frame_set_value (cache->saved_regs, SP_REGNUM, cache->base); + trad_frame_set_value (cache->saved_regs, HPPA_SP_REGNUM, cache->base); } /* The PC is found in the "return register", "Millicode" uses "r31" @@ -4901,14 +2479,14 @@ static struct frame_id hppa_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) { return frame_id_build (frame_unwind_register_unsigned (next_frame, - SP_REGNUM), + HPPA_SP_REGNUM), frame_pc_unwind (next_frame)); } static CORE_ADDR hppa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) { - return frame_unwind_register_signed (next_frame, PC_REGNUM) & ~3; + return frame_unwind_register_signed (next_frame, PCOQ_HEAD_REGNUM) & ~3; } /* Exception handling support for the HP-UX ANSI C++ compiler. @@ -5462,62 +3040,6 @@ hppa_skip_permanent_breakpoint (void) /* We can leave the tail's space the same, since there's no jump. */ } -/* Same as hppa32_store_return_value(), but for the PA64 ABI. */ - -void -hppa64_store_return_value (struct type *type, char *valbuf) -{ - if (TYPE_CODE (type) == TYPE_CODE_FLT) - deprecated_write_register_bytes - (DEPRECATED_REGISTER_BYTE (FP4_REGNUM) - + DEPRECATED_REGISTER_SIZE - TYPE_LENGTH (type), - valbuf, TYPE_LENGTH (type)); - else if (is_integral_type(type)) - deprecated_write_register_bytes - (DEPRECATED_REGISTER_BYTE (28) - + DEPRECATED_REGISTER_SIZE - TYPE_LENGTH (type), - valbuf, TYPE_LENGTH (type)); - else if (TYPE_LENGTH (type) <= 8) - deprecated_write_register_bytes - (DEPRECATED_REGISTER_BYTE (28),valbuf, TYPE_LENGTH (type)); - else if (TYPE_LENGTH (type) <= 16) - { - deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (28),valbuf, 8); - deprecated_write_register_bytes - (DEPRECATED_REGISTER_BYTE (29), valbuf + 8, TYPE_LENGTH (type) - 8); - } -} - -/* Same as hppa32_extract_return_value but for the PA64 ABI case. */ - -void -hppa64_extract_return_value (struct type *type, char *regbuf, char *valbuf) -{ - /* RM: Floats are returned in FR4R, doubles in FR4. - Integral values are in r28, padded on the left. - Aggregates less that 65 bits are in r28, right padded. - Aggregates upto 128 bits are in r28 and r29, right padded. */ - if (TYPE_CODE (type) == TYPE_CODE_FLT) - memcpy (valbuf, - regbuf + DEPRECATED_REGISTER_BYTE (FP4_REGNUM) - + DEPRECATED_REGISTER_SIZE - TYPE_LENGTH (type), - TYPE_LENGTH (type)); - else if (is_integral_type(type)) - memcpy (valbuf, - regbuf + DEPRECATED_REGISTER_BYTE (28) - + DEPRECATED_REGISTER_SIZE - TYPE_LENGTH (type), - TYPE_LENGTH (type)); - else if (TYPE_LENGTH (type) <= 8) - memcpy (valbuf, regbuf + DEPRECATED_REGISTER_BYTE (28), - TYPE_LENGTH (type)); - else if (TYPE_LENGTH (type) <= 16) - { - memcpy (valbuf, regbuf + DEPRECATED_REGISTER_BYTE (28), 8); - memcpy (valbuf + 8, regbuf + DEPRECATED_REGISTER_BYTE (29), - TYPE_LENGTH (type) - 8); - } -} - int hppa_reg_struct_has_addr (int gcc_p, struct type *type) { @@ -5533,13 +3055,6 @@ hppa_inner_than (CORE_ADDR lhs, CORE_ADDR rhs) return (lhs > rhs); } -CORE_ADDR -hppa64_stack_align (CORE_ADDR sp) -{ - /* The PA64 ABI mandates a 16 byte stack alignment. */ - return ((sp % 16) ? (sp + 15) & -16 : sp); -} - int hppa_pc_requires_run_before_use (CORE_ADDR pc) { @@ -5580,56 +3095,30 @@ hppa_instruction_nullified (void) return ((ipsw & 0x00200000) && !(flags & 0x2)); } -int -hppa_register_raw_size (int reg_nr) -{ - /* All registers have the same size. */ - return DEPRECATED_REGISTER_SIZE; -} - -/* Index within the register vector of the first byte of the space i - used for register REG_NR. */ - -int -hppa_register_byte (int reg_nr) -{ - struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); - - return reg_nr * tdep->bytes_per_address; -} - /* Return the GDB type object for the "standard" data type of data in register N. */ -struct type * -hppa32_register_virtual_type (int reg_nr) +static struct type * +hppa32_register_type (struct gdbarch *gdbarch, int reg_nr) { if (reg_nr < FP4_REGNUM) - return builtin_type_int; + return builtin_type_uint32; else - return builtin_type_float; + return builtin_type_ieee_single_big; } /* Return the GDB type object for the "standard" data type of data in register N. hppa64 version. */ -struct type * -hppa64_register_virtual_type (int reg_nr) +static struct type * +hppa64_register_type (struct gdbarch *gdbarch, int reg_nr) { if (reg_nr < FP4_REGNUM) - return builtin_type_unsigned_long_long; + return builtin_type_uint64; else - return builtin_type_double; + return builtin_type_ieee_double_big; } -/* Store the address of the place in which to copy the structure the - subroutine will return. This is called from call_function. */ - -void -hppa_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) -{ - write_register (28, addr); -} /* Return True if REGNUM is not a register available to the user through ptrace(). */ @@ -5740,24 +3229,18 @@ hppa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) case 4: set_gdbarch_num_regs (gdbarch, hppa32_num_regs); set_gdbarch_register_name (gdbarch, hppa32_register_name); - set_gdbarch_deprecated_register_virtual_type - (gdbarch, hppa32_register_virtual_type); + set_gdbarch_register_type (gdbarch, hppa32_register_type); break; case 8: set_gdbarch_num_regs (gdbarch, hppa64_num_regs); set_gdbarch_register_name (gdbarch, hppa64_register_name); - set_gdbarch_deprecated_register_virtual_type - (gdbarch, hppa64_register_virtual_type); + set_gdbarch_register_type (gdbarch, hppa64_register_type); break; default: internal_error (__FILE__, __LINE__, "Unsupported address size: %d", tdep->bytes_per_address); } - /* The following gdbarch vector elements depend on other parts of this - vector which have been set above, depending on the ABI. */ - set_gdbarch_deprecated_register_bytes - (gdbarch, gdbarch_num_regs (gdbarch) * tdep->bytes_per_address); set_gdbarch_long_bit (gdbarch, tdep->bytes_per_address * TARGET_CHAR_BIT); set_gdbarch_ptr_bit (gdbarch, tdep->bytes_per_address * TARGET_CHAR_BIT); @@ -5775,23 +3258,14 @@ hppa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) set_gdbarch_in_solib_return_trampoline (gdbarch, hppa_in_solib_return_trampoline); set_gdbarch_inner_than (gdbarch, hppa_inner_than); - set_gdbarch_deprecated_register_size (gdbarch, tdep->bytes_per_address); - set_gdbarch_deprecated_fp_regnum (gdbarch, 3); - set_gdbarch_sp_regnum (gdbarch, 30); - set_gdbarch_fp0_regnum (gdbarch, 64); - set_gdbarch_pc_regnum (gdbarch, PCOQ_HEAD_REGNUM); - set_gdbarch_deprecated_register_raw_size (gdbarch, hppa_register_raw_size); - set_gdbarch_deprecated_register_byte (gdbarch, hppa_register_byte); - set_gdbarch_deprecated_register_virtual_size (gdbarch, hppa_register_raw_size); - set_gdbarch_deprecated_max_register_raw_size (gdbarch, tdep->bytes_per_address); - set_gdbarch_deprecated_max_register_virtual_size (gdbarch, 8); + set_gdbarch_sp_regnum (gdbarch, HPPA_SP_REGNUM); + set_gdbarch_fp0_regnum (gdbarch, HPPA_FP0_REGNUM); set_gdbarch_cannot_store_register (gdbarch, hppa_cannot_store_register); set_gdbarch_addr_bits_remove (gdbarch, hppa_smash_text_address); set_gdbarch_smash_text_address (gdbarch, hppa_smash_text_address); set_gdbarch_believe_pcc_promotion (gdbarch, 1); set_gdbarch_read_pc (gdbarch, hppa_target_read_pc); set_gdbarch_write_pc (gdbarch, hppa_target_write_pc); - set_gdbarch_deprecated_target_read_fp (gdbarch, hppa_target_read_fp); /* Helper for function argument information. */ set_gdbarch_fetch_pointer_argument (gdbarch, hppa_fetch_pointer_argument); @@ -5812,26 +3286,11 @@ hppa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) set_gdbarch_frame_align (gdbarch, hppa32_frame_align); break; case 8: - if (0) - { - set_gdbarch_push_dummy_call (gdbarch, hppa64_push_dummy_call); - set_gdbarch_frame_align (gdbarch, hppa64_frame_align); - break; - } - else - { - set_gdbarch_deprecated_call_dummy_breakpoint_offset (gdbarch, hppa64_call_dummy_breakpoint_offset); - set_gdbarch_deprecated_call_dummy_length (gdbarch, hppa64_call_dummy_length); - set_gdbarch_deprecated_stack_align (gdbarch, hppa64_stack_align); - break; - set_gdbarch_deprecated_push_dummy_frame (gdbarch, hppa_push_dummy_frame); - /* set_gdbarch_deprecated_fix_call_dummy (gdbarch, hppa_fix_call_dummy); */ - set_gdbarch_deprecated_push_arguments (gdbarch, hppa_push_arguments); - set_gdbarch_deprecated_use_generic_dummy_frames (gdbarch, 0); - set_gdbarch_deprecated_pc_in_call_dummy (gdbarch, deprecated_pc_in_call_dummy_on_stack); - set_gdbarch_call_dummy_location (gdbarch, ON_STACK); - } + set_gdbarch_push_dummy_call (gdbarch, hppa64_push_dummy_call); + set_gdbarch_frame_align (gdbarch, hppa64_frame_align); break; + default: + internal_error (__FILE__, __LINE__, "bad switch"); } /* Struct return methods. */ @@ -5841,43 +3300,17 @@ hppa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) set_gdbarch_return_value (gdbarch, hppa32_return_value); break; case 8: - if (0) - set_gdbarch_return_value (gdbarch, hppa64_return_value); - else - { - set_gdbarch_deprecated_extract_return_value (gdbarch, hppa64_extract_return_value); - set_gdbarch_use_struct_convention (gdbarch, hppa64_use_struct_convention); - set_gdbarch_deprecated_store_return_value (gdbarch, hppa64_store_return_value); - set_gdbarch_deprecated_store_struct_return (gdbarch, hppa_store_struct_return); - } + set_gdbarch_return_value (gdbarch, hppa64_return_value); break; default: internal_error (__FILE__, __LINE__, "bad switch"); } /* Frame unwind methods. */ - switch (tdep->bytes_per_address) - { - case 4: - set_gdbarch_unwind_dummy_id (gdbarch, hppa_unwind_dummy_id); - set_gdbarch_unwind_pc (gdbarch, hppa_unwind_pc); - frame_unwind_append_sniffer (gdbarch, hppa_frame_unwind_sniffer); - frame_base_append_sniffer (gdbarch, hppa_frame_base_sniffer); - break; - case 8: - set_gdbarch_deprecated_saved_pc_after_call (gdbarch, hppa_saved_pc_after_call); - set_gdbarch_deprecated_init_frame_pc (gdbarch, deprecated_init_frame_pc_default); - set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, hppa_frame_init_saved_regs); - set_gdbarch_deprecated_init_extra_frame_info (gdbarch, hppa_init_extra_frame_info); - set_gdbarch_deprecated_frame_chain (gdbarch, hppa_frame_chain); - set_gdbarch_deprecated_frame_chain_valid (gdbarch, hppa_frame_chain_valid); - set_gdbarch_deprecated_frameless_function_invocation (gdbarch, hppa_frameless_function_invocation); - set_gdbarch_deprecated_frame_saved_pc (gdbarch, hppa_frame_saved_pc); - set_gdbarch_deprecated_pop_frame (gdbarch, hppa_pop_frame); - break; - default: - internal_error (__FILE__, __LINE__, "bad switch"); - } + set_gdbarch_unwind_dummy_id (gdbarch, hppa_unwind_dummy_id); + set_gdbarch_unwind_pc (gdbarch, hppa_unwind_pc); + frame_unwind_append_sniffer (gdbarch, hppa_frame_unwind_sniffer); + frame_base_append_sniffer (gdbarch, hppa_frame_base_sniffer); /* Hook in ABI-specific overrides, if they have been registered. */ gdbarch_init_osabi (info, gdbarch); diff --git a/gdb/i386-nat.c b/gdb/i386-nat.c index a20e9b06635..95b46096b51 100644 --- a/gdb/i386-nat.c +++ b/gdb/i386-nat.c @@ -454,7 +454,7 @@ i386_handle_nonaligned_watchpoint (i386_wp_op_t what, CORE_ADDR addr, int len, while (len > 0) { int align = addr % max_wp_len; - /* Four (eigth on AMD64) is the maximum length a debug register + /* Four (eight on AMD64) is the maximum length a debug register can watch. */ int try = (len > max_wp_len ? (max_wp_len - 1) : len - 1); int size = size_try_array[try][align]; @@ -582,7 +582,7 @@ i386_stopped_data_address (void) watchpoint, not a hardware breakpoint. The reason is that GDB doesn't call the target_stopped_data_address method except for data watchpoints. In other words, I'm - being paranoid. */ + being paranoiac. */ && I386_DR_GET_RW_LEN (i) != 0) { addr = dr_mirror[i]; diff --git a/gdb/i386-tdep.h b/gdb/i386-tdep.h index f164e9d849a..9cb87653e12 100644 --- a/gdb/i386-tdep.h +++ b/gdb/i386-tdep.h @@ -166,7 +166,11 @@ enum i386_regnum I386_EFLAGS_REGNUM, /* %eflags */ I386_CS_REGNUM, /* %cs */ I386_SS_REGNUM, /* %ss */ - I386_ST0_REGNUM = 16, /* %st(0) */ + I386_DS_REGNUM, /* %ds */ + I386_ES_REGNUM, /* %es */ + I386_FS_REGNUM, /* %fs */ + I386_GS_REGNUM, /* %gs */ + I386_ST0_REGNUM /* %st(0) */ }; #define I386_NUM_GREGS 16 diff --git a/gdb/i386bsd-tdep.c b/gdb/i386bsd-tdep.c index 9276c32b3f7..c23acb53aca 100644 --- a/gdb/i386bsd-tdep.c +++ b/gdb/i386bsd-tdep.c @@ -163,8 +163,7 @@ _initialize_i386bsd_tdep (void) gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_aout_flavour, i386bsd_aout_osabi_sniffer); - /* BFD doesn't set the architecture for NetBSD style a.out core - files. */ - gdbarch_register_osabi_sniffer (bfd_arch_unknown, bfd_target_unknown_flavour, + /* BFD doesn't set a flavour for NetBSD style a.out core files. */ + gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_unknown_flavour, i386bsd_core_osabi_sniffer); } diff --git a/gdb/i386nbsd-tdep.c b/gdb/i386nbsd-tdep.c index 82013b59fc0..3c5304ec85b 100644 --- a/gdb/i386nbsd-tdep.c +++ b/gdb/i386nbsd-tdep.c @@ -236,7 +236,7 @@ i386nbsd_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) tdep->struct_return = reg_struct_return; /* NetBSD has a `struct sigcontext' that's different from the - origional 4.3 BSD. */ + original 4.3 BSD. */ tdep->sc_reg_offset = i386nbsd_sc_reg_offset; tdep->sc_num_regs = ARRAY_SIZE (i386nbsd_sc_reg_offset); } diff --git a/gdb/i386obsd-tdep.c b/gdb/i386obsd-tdep.c index d8556ea460a..ada2222ec97 100644 --- a/gdb/i386obsd-tdep.c +++ b/gdb/i386obsd-tdep.c @@ -220,7 +220,7 @@ i386obsd_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) set_gdbarch_sigtramp_end (gdbarch, i386obsd_sigtramp_end); /* OpenBSD has a `struct sigcontext' that's different from the - origional 4.3 BSD. */ + original 4.3 BSD. */ tdep->sc_reg_offset = i386obsd_sc_reg_offset; tdep->sc_num_regs = ARRAY_SIZE (i386obsd_sc_reg_offset); } diff --git a/gdb/infcall.c b/gdb/infcall.c index 11ce018087c..b10f8071daf 100644 --- a/gdb/infcall.c +++ b/gdb/infcall.c @@ -277,10 +277,6 @@ legacy_push_dummy_code (struct gdbarch *gdbarch, (PUSH_DUMMY_BREAKPOINT?) should just do everything. */ if (!gdbarch_push_dummy_call_p (current_gdbarch)) { -#ifdef GDB_TARGET_IS_HPPA - (*real_pc) = DEPRECATED_FIX_CALL_DUMMY (dummy1, start_sp, funaddr, nargs, - args, value_type, using_gcc); -#else if (DEPRECATED_FIX_CALL_DUMMY_P ()) { /* gdb_assert (CALL_DUMMY_LOCATION == ON_STACK) true? */ @@ -288,7 +284,6 @@ legacy_push_dummy_code (struct gdbarch *gdbarch, value_type, using_gcc); } (*real_pc) = start_sp; -#endif } /* Yes, the offset is applied to the real_pc and not the dummy addr. Ulgh! Blame the HP/UX target. */ diff --git a/gdb/infrun.c b/gdb/infrun.c index 6bbee5e8176..19dd8075155 100644 --- a/gdb/infrun.c +++ b/gdb/infrun.c @@ -1883,61 +1883,9 @@ handle_inferior_event (struct execution_control_state *ecs) ecs->random_signal = 1; /* See if something interesting happened to the non-current thread. If - so, then switch to that thread, and eventually give control back to - the user. - - Note that if there's any kind of pending follow (i.e., of a fork, - vfork or exec), we don't want to do this now. Rather, we'll let - the next resume handle it. */ - if (!ptid_equal (ecs->ptid, inferior_ptid) && - (pending_follow.kind == TARGET_WAITKIND_SPURIOUS)) + so, then switch to that thread. */ + if (!ptid_equal (ecs->ptid, inferior_ptid)) { - int printed = 0; - - /* If it's a random signal for a non-current thread, notify user - if he's expressed an interest. */ - if (ecs->random_signal && signal_print[stop_signal]) - { -/* ??rehrauer: I don't understand the rationale for this code. If the - inferior will stop as a result of this signal, then the act of handling - the stop ought to print a message that's couches the stoppage in user - terms, e.g., "Stopped for breakpoint/watchpoint". If the inferior - won't stop as a result of the signal -- i.e., if the signal is merely - a side-effect of something GDB's doing "under the covers" for the - user, such as stepping threads over a breakpoint they shouldn't stop - for -- then the message seems to be a serious annoyance at best. - - For now, remove the message altogether. */ -#if 0 - printed = 1; - target_terminal_ours_for_output (); - printf_filtered ("\nProgram received signal %s, %s.\n", - target_signal_to_name (stop_signal), - target_signal_to_string (stop_signal)); - gdb_flush (gdb_stdout); -#endif - } - - /* If it's not SIGTRAP and not a signal we want to stop for, then - continue the thread. */ - - if (stop_signal != TARGET_SIGNAL_TRAP && !signal_stop[stop_signal]) - { - if (printed) - target_terminal_inferior (); - - /* Clear the signal if it should not be passed. */ - if (signal_program[stop_signal] == 0) - stop_signal = TARGET_SIGNAL_0; - - target_resume (ecs->ptid, 0, stop_signal); - prepare_to_wait (ecs); - return; - } - - /* It's a SIGTRAP or a signal we're interested in. Switch threads, - and fall into the rest of wait_for_inferior(). */ - context_switch (ecs); if (context_hook) @@ -2930,6 +2878,7 @@ static void step_over_function (struct execution_control_state *ecs) { struct symtab_and_line sr_sal; + struct frame_id sr_id; init_sal (&sr_sal); /* initialize to zeros */ @@ -2973,13 +2922,29 @@ step_over_function (struct execution_control_state *ecs) sr_sal.section = find_pc_overlay (sr_sal.pc); check_for_old_step_resume_breakpoint (); - step_resume_breakpoint = - set_momentary_breakpoint (sr_sal, get_frame_id (get_current_frame ()), - bp_step_resume); if (frame_id_p (step_frame_id) && !IN_SOLIB_DYNSYM_RESOLVE_CODE (sr_sal.pc)) - step_resume_breakpoint->frame_id = step_frame_id; + /* NOTE: cagney/2004-02-27: Use the global state's idea of the + stepping frame ID. I suspect this is done as it is lighter + weight than a call to get_prev_frame. */ + sr_id = step_frame_id; + else if (legacy_frame_p (current_gdbarch)) + /* NOTE: cagney/2004-02-27: This is the way it was 'cos this is + the way it always was. It should be using the unwound (or + caller's) ID, and not this (or the callee's) ID. It appeared + to work because: legacy architectures used the wrong end of the + frame for the ID.stack (inner-most rather than outer-most) so + that the callee's id.stack (un adjusted) matched the caller's + id.stack giving the "correct" id; more often than not + !IN_SOLIB_DYNSYM_RESOLVE_CODE and hence the code above (it was + originally later in the function) fixed the ID by using global + state. */ + sr_id = get_frame_id (get_current_frame ()); + else + sr_id = get_frame_id (get_prev_frame (get_current_frame ())); + + step_resume_breakpoint = set_momentary_breakpoint (sr_sal, sr_id, bp_step_resume); if (breakpoints_inserted) insert_breakpoints (); diff --git a/gdb/ppc-linux-nat.c b/gdb/ppc-linux-nat.c index 372ad0c7b48..619984a6c3b 100644 --- a/gdb/ppc-linux-nat.c +++ b/gdb/ppc-linux-nat.c @@ -164,12 +164,6 @@ ppc_register_u_addr (int regno) return u_addr; } -static int -ppc_ptrace_cannot_fetch_store_register (int regno) -{ - return (ppc_register_u_addr (regno) == -1); -} - /* The Linux kernel ptrace interface for AltiVec registers uses the registers set mechanism, as opposed to the interface for all the other registers, that stores/fetches each register individually. */ diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c index 5eef8959115..529fb3b00a8 100644 --- a/gdb/rs6000-tdep.c +++ b/gdb/rs6000-tdep.c @@ -210,6 +210,16 @@ rs6000_frame_init_saved_regs (struct frame_info *fi) frame_get_saved_regs (fi, NULL); } +static CORE_ADDR +rs6000_init_frame_pc_first (int fromleaf, struct frame_info *prev) +{ + return (fromleaf + ? DEPRECATED_SAVED_PC_AFTER_CALL (get_next_frame (prev)) + : frame_relative_level (prev) > 0 + ? DEPRECATED_FRAME_SAVED_PC (get_next_frame (prev)) + : read_pc ()); +} + static CORE_ADDR rs6000_frame_args_address (struct frame_info *fi) { @@ -2914,6 +2924,7 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, rs6000_frame_init_saved_regs); set_gdbarch_deprecated_init_extra_frame_info (gdbarch, rs6000_init_extra_frame_info); + set_gdbarch_deprecated_init_frame_pc_first (gdbarch, rs6000_init_frame_pc_first); if (!sysv_abi) { diff --git a/gdb/sh-tdep.c b/gdb/sh-tdep.c index 9cb5278c4d4..45833fcfdab 100644 --- a/gdb/sh-tdep.c +++ b/gdb/sh-tdep.c @@ -440,9 +440,9 @@ sh_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc, if (reg < 14) { sav_reg = reg; - offset = (((inst & 0xff) ^ 0x80) - 0x80) << 1; + offset = (inst & 0xff) << 1; sav_offset = - read_memory_integer (((pc + 4) & ~3) + offset, 2); + read_memory_integer ((pc + 4) + offset, 2); } } } @@ -450,13 +450,13 @@ sh_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc, { if (sav_reg < 0) { - reg = (inst & 0x0f00) >> 8; + reg = GET_TARGET_REG (inst); if (reg < 14) { sav_reg = reg; - offset = (((inst & 0xff) ^ 0x80) - 0x80) << 1; + offset = (inst & 0xff) << 2; sav_offset = - read_memory_integer (((pc + 4) & ~3) + offset, 4); + read_memory_integer (((pc & 0xfffffffc) + 4) + offset, 4); } } } @@ -1792,35 +1792,23 @@ sh_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, else /* do all (or most) registers */ { - regnum = 0; - while (regnum < NUM_REGS) + for (regnum = 0; regnum < NUM_REGS; ++regnum) { /* If the register name is empty, it is undefined for this processor, so don't display anything. */ if (REGISTER_NAME (regnum) == NULL || *(REGISTER_NAME (regnum)) == '\0') - { - regnum++; - continue; - } + continue; if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) { + /* true for "INFO ALL-REGISTERS" command */ if (fpregs) - { - /* true for "INFO ALL-REGISTERS" command */ - sh_do_fp_register (gdbarch, file, regnum); /* FP regs */ - regnum++; - } - else - regnum += (FP_LAST_REGNUM - FP0_REGNUM); /* skip FP regs */ + sh_do_fp_register (gdbarch, file, regnum); /* FP regs */ } else - { - sh_do_register (gdbarch, file, regnum); /* All other regs */ - regnum++; - } + sh_do_register (gdbarch, file, regnum); /* All other regs */ } if (fpregs) diff --git a/gdb/sparc-tdep.c b/gdb/sparc-tdep.c index 66dbac798c0..893648c8b36 100644 --- a/gdb/sparc-tdep.c +++ b/gdb/sparc-tdep.c @@ -43,12 +43,11 @@ struct regset; -/* This file implements the The SPARC 32-bit ABI as defined by the - section "Low-Level System Information" of the SPARC Compliance - Definition (SCD) 2.4.1, which is the 32-bit System V psABI for - SPARC. The SCD lists changes with respect to the origional 32-bit - psABI as defined in the "System V ABI, SPARC Processor - Supplement". +/* This file implements the SPARC 32-bit ABI as defined by the section + "Low-Level System Information" of the SPARC Compliance Definition + (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD + lists changes with respect to the original 32-bit psABI as defined + in the "System V ABI, SPARC Processor Supplement". Note that if we talk about SunOS, we mean SunOS 4.x, which was BSD-based, which is sometimes (retroactively?) referred to as @@ -186,7 +185,7 @@ sparc_integral_or_pointer_p (const struct type *type) { /* We have byte, half-word, word and extended-word/doubleword integral types. The doubleword is an extension to the - origional 32-bit ABI by the SCD 2.4.x. */ + original 32-bit ABI by the SCD 2.4.x. */ int len = TYPE_LENGTH (type); return (len == 1 || len == 2 || len == 4 || len == 8); } @@ -615,14 +614,6 @@ sparc_frame_cache (struct frame_info *next_frame, void **this_cache) cache = sparc_alloc_frame_cache (); *this_cache = cache; - /* In priciple, for normal frames, %fp (%i6) holds the frame - pointer, which holds the base address for the current stack - frame. */ - - cache->base = frame_unwind_register_unsigned (next_frame, SPARC_FP_REGNUM); - if (cache->base == 0) - return cache; - cache->pc = frame_func_unwind (next_frame); if (cache->pc != 0) { @@ -632,10 +623,18 @@ sparc_frame_cache (struct frame_info *next_frame, void **this_cache) if (cache->frameless_p) { - /* We didn't find a valid frame, which means that CACHE->base - currently holds the frame pointer for our calling frame. */ - cache->base = frame_unwind_register_unsigned (next_frame, - SPARC_SP_REGNUM); + /* This function is frameless, so %fp (%i6) holds the frame + pointer for our calling frame. Use %sp (%o6) as this frame's + base address. */ + cache->base = + frame_unwind_register_unsigned (next_frame, SPARC_SP_REGNUM); + } + else + { + /* For normal frames, %fp (%i6) holds the frame pointer, the + base address for the current stack frame. */ + cache->base = + frame_unwind_register_unsigned (next_frame, SPARC_FP_REGNUM); } return cache; diff --git a/gdb/stabsread.c b/gdb/stabsread.c index 5cee516bcb3..07c6fe0b8a2 100644 --- a/gdb/stabsread.c +++ b/gdb/stabsread.c @@ -178,11 +178,11 @@ invalid_cpp_abbrev_complaint (const char *arg1) } static void -reg_value_complaint (int arg1, int arg2, const char *arg3) +reg_value_complaint (int regnum, int num_regs, const char *sym) { complaint (&symfile_complaints, - "register number %d too large (max %d) in symbol %s", arg1, arg2, - arg3); + "register number %d too large (max %d) in symbol %s", + regnum, num_regs - 1, sym); } static void diff --git a/gdb/target.c b/gdb/target.c index ff47ac13bf7..d4ff6c05af6 100644 --- a/gdb/target.c +++ b/gdb/target.c @@ -1829,8 +1829,6 @@ debug_to_xfer_memory (CORE_ADDR memaddr, char *myaddr, int len, int write, (unsigned int) memaddr, /* possable truncate long long */ len, write ? "write" : "read", retval); - - if (retval > 0) { int i; @@ -1839,7 +1837,15 @@ debug_to_xfer_memory (CORE_ADDR memaddr, char *myaddr, int len, int write, for (i = 0; i < retval; i++) { if ((((long) &(myaddr[i])) & 0xf) == 0) - fprintf_unfiltered (gdb_stdlog, "\n"); + { + if (targetdebug < 2 && i > 0) + { + fprintf_unfiltered (gdb_stdlog, " ..."); + break; + } + fprintf_unfiltered (gdb_stdlog, "\n"); + } + fprintf_unfiltered (gdb_stdlog, " %02x", myaddr[i] & 0xff); } } @@ -2431,7 +2437,9 @@ initialize_targets (void) (add_set_cmd ("target", class_maintenance, var_zinteger, (char *) &targetdebug, "Set target debugging.\n\ -When non-zero, target debugging is enabled.", &setdebuglist), +When non-zero, target debugging is enabled. Higher numbers are more\n\ +verbose. Changes do not take effect until the next \"run\" or \"target\"\n\ +command.", &setdebuglist), &showdebuglist); add_setshow_boolean_cmd ("trust-readonly-sections", class_support, diff --git a/gdb/testsuite/ChangeLog b/gdb/testsuite/ChangeLog index 9e221746373..a1d5f1278e1 100644 --- a/gdb/testsuite/ChangeLog +++ b/gdb/testsuite/ChangeLog @@ -1,3 +1,40 @@ +2004-03-09 Michael Chastain + + From Corinna Vinschen with modifications. + * gdb.cp/classes.cc (enums1): Add a line to extend scope of + local variable obj_with_enum. + * gdb.cp/classes.exp (test_enums): Remove TODO note about FAIL + results with obj_with_enum. + +2004-03-09 Michael Chastain + + * gdb.cp/classes.cc: New file, copied from misc.cc. + * gdb.cp/classes.exp: Use classes.cc rather than misc.cc. + +2004-03-09 Michael Chastain + + * gdb.cp/misc.cc: Add copyright notice. + +2004-03-05 David Carlton + + * gdb.cp/rtti.exp: Add 'print *obj3' test. + * gdb.cp/rtti.h: Update copyright. + (namespace n2::n3): New. + * gdb.cp/rtti1.cc: (refer_to (n2::n3::C3 *)): New. + (n2::n3::func3): New. + (main): Call n2::n3::func3. + * gdb.cp/rtti2.cc: Update copyright. + (n2::create3): New. + +2004-03-04 Mark Kettenis + + * gdb.asm/openbsd.inc: Fix typo. + +2004-03-03 Fred Fish + + * gdb.base/pc-fp.exp (get_valueofx): Fix apparent typo to now set + "val" instead of unused "size". Update copyright year. + 2004-02-29 Daniel Jacobowitz * gdb.cp/ctti.exp: Handle unsigned char type. Expect templates diff --git a/gdb/testsuite/gdb.asm/openbsd.inc b/gdb/testsuite/gdb.asm/openbsd.inc index 90e3dbd0d25..5f5f5187cc7 100644 --- a/gdb/testsuite/gdb.asm/openbsd.inc +++ b/gdb/testsuite/gdb.asm/openbsd.inc @@ -1,6 +1,6 @@ comment "openbsd .note" -.section ".note.openbsdbsd.ident", "a" +.section ".note.openbsd.ident", "a" .p2align 2 .long 8 diff --git a/gdb/testsuite/gdb.base/pc-fp.exp b/gdb/testsuite/gdb.base/pc-fp.exp index f94e3314388..c7daf6f08a4 100644 --- a/gdb/testsuite/gdb.base/pc-fp.exp +++ b/gdb/testsuite/gdb.base/pc-fp.exp @@ -1,4 +1,4 @@ -# Copyright 2002 Free Software Foundation, Inc. +# Copyright 2002, 2004 Free Software Foundation, Inc. # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -65,7 +65,7 @@ proc get_valueofx { fmt exp default } { pass "get value of ${exp} ($val)" } timeout { - set size ${default} + set val ${default} fail "get value of ${exp} (timeout)" } } diff --git a/gdb/testsuite/gdb.cp/classes.cc b/gdb/testsuite/gdb.cp/classes.cc new file mode 100644 index 00000000000..d09f38fc36d --- /dev/null +++ b/gdb/testsuite/gdb.cp/classes.cc @@ -0,0 +1,608 @@ +/* This testcase is part of GDB, the GNU debugger. + + Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2004 + Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +// Test various -*- C++ -*- things. + +// ====================== basic C++ types ======================= +bool v_bool; +bool v_bool_array[2]; + +typedef struct fleep fleep; +struct fleep { int a; } s; + +// ====================== simple class structures ======================= + +struct default_public_struct { + // defaults to public: + int a; + int b; +}; + +struct explicit_public_struct { + public: + int a; + int b; +}; + +struct protected_struct { + protected: + int a; + int b; +}; + +struct private_struct { + private: + int a; + int b; +}; + +struct mixed_protection_struct { + public: + int a; + int b; + private: + int c; + int d; + protected: + int e; + int f; + public: + int g; + private: + int h; + protected: + int i; +}; + +class public_class { + public: + int a; + int b; +}; + +class protected_class { + protected: + int a; + int b; +}; + +class default_private_class { + // defaults to private: + int a; + int b; +}; + +class explicit_private_class { + private: + int a; + int b; +}; + +class mixed_protection_class { + public: + int a; + int b; + private: + int c; + int d; + protected: + int e; + int f; + public: + int g; + private: + int h; + protected: + int i; +}; + +class const_vol_method_class { +public: + int a; + int b; + int foo (int &) const; + int bar (int &) volatile; + int baz (int &) const volatile; +}; + +int const_vol_method_class::foo (int & ir) const +{ + return ir + 3; +} +int const_vol_method_class::bar (int & ir) volatile +{ + return ir + 4; +} +int const_vol_method_class::baz (int & ir) const volatile +{ + return ir + 5; +} + +// ========================= simple inheritance ========================== + +class A { + public: + int a; + int x; +}; + +A g_A; + +class B : public A { + public: + int b; + int x; +}; + +B g_B; + +class C : public A { + public: + int c; + int x; +}; + +C g_C; + +class D : public B, public C { + public: + int d; + int x; +}; + +D g_D; + +class E : public D { + public: + int e; + int x; +}; + +E g_E; + +class class_with_anon_union +{ + public: + int one; + union + { + int a; + long b; + }; +}; + +class_with_anon_union g_anon_union; + +void inheritance2 (void) +{ +} + +void inheritance1 (void) +{ + int ival; + int *intp; + + // {A::a, A::x} + + g_A.A::a = 1; + g_A.A::x = 2; + + // {{A::a,A::x},B::b,B::x} + + g_B.A::a = 3; + g_B.A::x = 4; + g_B.B::b = 5; + g_B.B::x = 6; + + // {{A::a,A::x},C::c,C::x} + + g_C.A::a = 7; + g_C.A::x = 8; + g_C.C::c = 9; + g_C.C::x = 10; + + // {{{A::a,A::x},B::b,B::x},{{A::a,A::x},C::c,C::x},D::d,D::x} + + // The following initialization code is non-portable, but allows us + // to initialize all members of g_D until we can fill in the missing + // initialization code with legal C++ code. + + for (intp = (int *) &g_D, ival = 11; + intp < ((int *) &g_D + sizeof (g_D) / sizeof (int)); + intp++, ival++) + { + *intp = ival; + } + + // Overlay the nonportable initialization with legal initialization. + + // ????? = 11; (g_D.A::a = 11; is ambiguous) + // ????? = 12; (g_D.A::x = 12; is ambiguous) +/* djb 6-3-2000 + + This should take care of it. Rather than try to initialize using an ambiguous + construct, use 2 unambiguous ones for each. Since the ambiguous a/x member is + coming from C, and B, initialize D's C::a, and B::a, and D's C::x and B::x. + */ + g_D.C::a = 15; + g_D.C::x = 12; + g_D.B::a = 11; + g_D.B::x = 12; + g_D.B::b = 13; + g_D.B::x = 14; + // ????? = 15; + // ????? = 16; + g_D.C::c = 17; + g_D.C::x = 18; + g_D.D::d = 19; + g_D.D::x = 20; + + + // {{{{A::a,A::x},B::b,B::x},{{A::a,A::x},C::c,C::x},D::d,D::x}},E::e,E::x} + + // The following initialization code is non-portable, but allows us + // to initialize all members of g_D until we can fill in the missing + // initialization code with legal C++ code. + + for (intp = (int *) &g_E, ival = 21; + intp < ((int *) &g_E + sizeof (g_E) / sizeof (int)); + intp++, ival++) + { + *intp = ival; + } + + // Overlay the nonportable initialization with legal initialization. + + // ????? = 21; (g_E.A::a = 21; is ambiguous) + // ????? = 22; (g_E.A::x = 22; is ambiguous) + g_E.B::b = 23; + g_E.B::x = 24; + // ????? = 25; + // ????? = 26; + g_E.C::c = 27; + g_E.C::x = 28; + g_E.D::d = 29; + g_E.D::x = 30; + g_E.E::e = 31; + g_E.E::x = 32; + + g_anon_union.one = 1; + g_anon_union.a = 2; + + inheritance2 (); +} + +// ======================== static member functions ===================== + +class Static { +public: + static void ii(int, int); +}; +void Static::ii (int, int) { } + +// ======================== virtual base classes========================= + +class vA { + public: + int va; + int vx; +}; + +vA g_vA; + +class vB : public virtual vA { + public: + int vb; + int vx; +}; + +vB g_vB; + +class vC : public virtual vA { + public: + int vc; + int vx; +}; + +vC g_vC; + +class vD : public virtual vB, public virtual vC { + public: + int vd; + int vx; +}; + +vD g_vD; + +class vE : public virtual vD { + public: + int ve; + int vx; +}; + +vE g_vE; + +void inheritance4 (void) +{ +} + +void inheritance3 (void) +{ + int ival; + int *intp; + + // {vA::va, vA::vx} + + g_vA.vA::va = 1; + g_vA.vA::vx = 2; + + // {{vA::va, vA::vx}, vB::vb, vB::vx} + + g_vB.vA::va = 3; + g_vB.vA::vx = 4; + g_vB.vB::vb = 5; + g_vB.vB::vx = 6; + + // {{vA::va, vA::vx}, vC::vc, vC::vx} + + g_vC.vA::va = 7; + g_vC.vA::vx = 8; + g_vC.vC::vc = 9; + g_vC.vC::vx = 10; + + // {{{{vA::va, vA::vx}, vB::vb, vB::vx}, vC::vc, vC::vx}, vD::vd,vD::vx} + + g_vD.vA::va = 11; + g_vD.vA::vx = 12; + g_vD.vB::vb = 13; + g_vD.vB::vx = 14; + g_vD.vC::vc = 15; + g_vD.vC::vx = 16; + g_vD.vD::vd = 17; + g_vD.vD::vx = 18; + + + // {{{{{vA::va,vA::vx},vB::vb,vB::vx},vC::vc,vC::vx},vD::vd,vD::vx},vE::ve,vE::vx} + + g_vD.vA::va = 19; + g_vD.vA::vx = 20; + g_vD.vB::vb = 21; + g_vD.vB::vx = 22; + g_vD.vC::vc = 23; + g_vD.vC::vx = 24; + g_vD.vD::vd = 25; + g_vD.vD::vx = 26; + g_vE.vE::ve = 27; + g_vE.vE::vx = 28; + + inheritance4 (); +} + +// ====================================================================== + +class Base1 { + public: + int x; + Base1(int i) { x = i; } +}; + +class Foo +{ + public: + int x; + int y; + static int st; + Foo (int i, int j) { x = i; y = j; } + int operator! (); + operator int (); + int times (int y); +}; + +class Bar : public Base1, public Foo { + public: + int z; + Bar (int i, int j, int k) : Base1 (10*k), Foo (i, j) { z = k; } +}; + +int Foo::operator! () { return !x; } + +int Foo::times (int y) { return x * y; } + +int Foo::st = 100; + +Foo::operator int() { return x; } + +Foo foo(10, 11); +Bar bar(20, 21, 22); + +class ClassWithEnum { +public: + enum PrivEnum { red, green, blue, yellow = 42 }; + PrivEnum priv_enum; + int x; +}; + +void enums2 (void) +{ +} + +/* classes.exp relies on statement order in this function for testing + enumeration fields. */ + +void enums1 () +{ + ClassWithEnum obj_with_enum; + obj_with_enum.priv_enum = ClassWithEnum::red; + obj_with_enum.x = 0; + enums2 (); + obj_with_enum.priv_enum = ClassWithEnum::green; + obj_with_enum.x = 1; +} + +class ClassParam { +public: + int Aptr_a (A *a) { return a->a; } + int Aptr_x (A *a) { return a->x; } + int Aref_a (A &a) { return a.a; } + int Aref_x (A &a) { return a.x; } + int Aval_a (A a) { return a.a; } + int Aval_x (A a) { return a.x; } +}; + +ClassParam class_param; + +class Contains_static_instance +{ + public: + int x; + int y; + Contains_static_instance (int i, int j) { x = i; y = j; } + static Contains_static_instance null; +}; + +Contains_static_instance Contains_static_instance::null(0,0); +Contains_static_instance csi(10,20); + +class Contains_nested_static_instance +{ + public: + class Nested + { + public: + Nested(int i) : z(i) {} + int z; + static Contains_nested_static_instance xx; + }; + + Contains_nested_static_instance(int i, int j) : x(i), y(j) {} + + int x; + int y; + + static Contains_nested_static_instance null; + static Nested yy; +}; + +Contains_nested_static_instance Contains_nested_static_instance::null(0, 0); +Contains_nested_static_instance::Nested Contains_nested_static_instance::yy(5); +Contains_nested_static_instance + Contains_nested_static_instance::Nested::xx(1,2); +Contains_nested_static_instance cnsi(30,40); + +typedef struct { + int one; + int two; +} tagless_struct; +tagless_struct v_tagless; + +/* Try to get the compiler to allocate a class in a register. */ +class small { + public: + int x; + int method (); +}; + +int +small::method () +{ + return x + 5; +} + +void marker_reg1 () {} + +int +register_class () +{ + /* We don't call any methods for v, so gcc version cygnus-2.3.3-930220 + might put this variable in a register. This is a lose, though, because + it means that GDB can't call any methods for that variable. */ + register small v; + + int i; + + /* Perform a computation sufficiently complicated that optimizing compilers + won't optimized out the variable. If some compiler constant-folds this + whole loop, maybe using a parameter to this function here would help. */ + v.x = 0; + for (i = 0; i < 13; ++i) + v.x += i; + --v.x; /* v.x is now 77 */ + marker_reg1 (); + return v.x + 5; +} + +void dummy() +{ + v_bool = true; + v_bool_array[0] = false; + v_bool_array[1] = v_bool; +} + +void use_methods () +{ + /* Refer to methods so that they don't get optimized away. */ + int i; + i = class_param.Aptr_a (&g_A); + i = class_param.Aptr_x (&g_A); + i = class_param.Aref_a (g_A); + i = class_param.Aref_x (g_A); + i = class_param.Aval_a (g_A); + i = class_param.Aval_x (g_A); +} + + +int +main() +{ +#ifdef usestubs + set_debug_traps(); + breakpoint(); +#endif + dummy(); + inheritance1 (); + inheritance3 (); + enums1 (); + register_class (); + + /* FIXME: pmi gets optimized out. Need to do some more computation with + it or something. (No one notices, because the test is xfail'd anyway, + but that probably won't always be true...). */ + int Foo::* pmi = &Foo::y; + + /* Make sure the AIX linker doesn't remove the variable. */ + v_tagless.one = 5; + + use_methods (); + + return foo.*pmi; +} + +/* Create an instance for some classes, otherwise they get optimized away. */ + +default_public_struct default_public_s; +explicit_public_struct explicit_public_s; +protected_struct protected_s; +private_struct private_s; +mixed_protection_struct mixed_protection_s; +public_class public_c; +protected_class protected_c; +default_private_class default_private_c; +explicit_private_class explicit_private_c; +mixed_protection_class mixed_protection_c; diff --git a/gdb/testsuite/gdb.cp/classes.exp b/gdb/testsuite/gdb.cp/classes.exp index 12428be5d69..0b723e591f6 100644 --- a/gdb/testsuite/gdb.cp/classes.exp +++ b/gdb/testsuite/gdb.cp/classes.exp @@ -27,7 +27,7 @@ if $tracelevel then { if { [skip_cplus_tests] } { continue } -set testfile "misc" +set testfile "classes" set srcfile ${testfile}.cc set binfile ${objdir}/${subdir}/${testfile} @@ -633,11 +633,6 @@ proc test_enums {} { gdb_test "next" "" - # TODO: with gcc HEAD 2003-12-28 21:08:30 UTC -gdwarf-2, - # gdb says that obj_with_enum is out of scope here and the - # tests after this FAIL. This needs investigation. - # -- chastain 2003-12-30 - # print the object again gdb_test "print obj_with_enum" \ diff --git a/gdb/testsuite/gdb.cp/misc.cc b/gdb/testsuite/gdb.cp/misc.cc index 286c02bc6df..7d69ed225ae 100644 --- a/gdb/testsuite/gdb.cp/misc.cc +++ b/gdb/testsuite/gdb.cp/misc.cc @@ -1,3 +1,23 @@ +/* This testcase is part of GDB, the GNU debugger. + + Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 + Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + // Test various -*- C++ -*- things. // ====================== basic C++ types ======================= diff --git a/gdb/testsuite/gdb.cp/rtti.exp b/gdb/testsuite/gdb.cp/rtti.exp index 0a8a2d70b31..18f3cc295da 100644 --- a/gdb/testsuite/gdb.cp/rtti.exp +++ b/gdb/testsuite/gdb.cp/rtti.exp @@ -140,5 +140,10 @@ gdb_continue_to_breakpoint "end of constructors in func" gdb_test "print *obj" "\\$\[0-9\]* = { = .*}" +gdb_breakpoint [gdb_get_line_number "func3-constructs-done"] +gdb_continue_to_breakpoint "end of constructors in func3" + +gdb_test "print *obj3" "\\$\[0-9\]* = { = .*}" + gdb_exit return 0 diff --git a/gdb/testsuite/gdb.cp/rtti.h b/gdb/testsuite/gdb.cp/rtti.h index 879896d0dc8..c3249252f09 100644 --- a/gdb/testsuite/gdb.cp/rtti.h +++ b/gdb/testsuite/gdb.cp/rtti.h @@ -1,6 +1,6 @@ /* Code to go along with tests in rtti.exp. - Copyright 2003 Free Software Foundation, Inc. + Copyright 2003, 2004 Free Software Foundation, Inc. Contributed by David Carlton and by Kealia, Inc. @@ -45,4 +45,12 @@ namespace n2 { }; extern C2 *create2(); + + namespace n3 { + class C3 : public C2 { + public: + }; + } + + extern n3::C3 *create3(); } diff --git a/gdb/testsuite/gdb.cp/rtti1.cc b/gdb/testsuite/gdb.cp/rtti1.cc index de8e12fc8e4..d32ac047d44 100644 --- a/gdb/testsuite/gdb.cp/rtti1.cc +++ b/gdb/testsuite/gdb.cp/rtti1.cc @@ -63,16 +63,33 @@ void refer_to (n2::C2 *obj) // Do nothing. } +void refer_to (n2::n3::C3 *obj) +{ + // Do nothing. +} + namespace n2 { void func () { C2 *obj = create2 (); - refer_to (obj); // func-constructs-done + refer_to (obj); // func-constructs-done return; } + + namespace n3 + { + void func3 () + { + C3 *obj3 = create3 (); + + refer_to (obj3); // func3-constructs-done + + return; + } + } } int main() @@ -84,6 +101,7 @@ int main() C2 *e2 = create2(); n2::func(); // main-constructs-done + n2::n3::func3(); return 0; } diff --git a/gdb/testsuite/gdb.cp/rtti2.cc b/gdb/testsuite/gdb.cp/rtti2.cc index 8bb1ed6c99f..353a1f8c7b8 100644 --- a/gdb/testsuite/gdb.cp/rtti2.cc +++ b/gdb/testsuite/gdb.cp/rtti2.cc @@ -1,6 +1,6 @@ /* Code to go along with tests in rtti.exp. - Copyright 2003 Free Software Foundation, Inc. + Copyright 2003, 2004 Free Software Foundation, Inc. Contributed by David Carlton and by Kealia, Inc. @@ -33,4 +33,8 @@ namespace n2 { return new D2(0, 0); } + n3::C3 *create3() { + return new n3::C3(); + } + } diff --git a/gdb/testsuite/gdb.objc/Makefile.in b/gdb/testsuite/gdb.objc/Makefile.in deleted file mode 100644 index 381e48a0789..00000000000 --- a/gdb/testsuite/gdb.objc/Makefile.in +++ /dev/null @@ -1,22 +0,0 @@ -VPATH = @srcdir@ -srcdir = @srcdir@ - -EXECUTABLES = basicclass - -all: - @echo "Nothing to be done for all..." - -info: -install-info: -dvi: -install: -uninstall: force -installcheck: -check: - -clean mostlyclean: - -rm -f *~ *.o *.ci - -rm -f core ${EXECUTABLES} - -distclean maintainer-clean realclean: clean - -rm -f Makefile config.status config.log diff --git a/gdb/testsuite/gdb.objc/basicclass.exp b/gdb/testsuite/gdb.objc/basicclass.exp deleted file mode 100644 index c92534bdbea..00000000000 --- a/gdb/testsuite/gdb.objc/basicclass.exp +++ /dev/null @@ -1,195 +0,0 @@ -# Copyright 2003, 2004 Free Software Foundation, Inc. - -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - -# This file was written by Adam Fedor (fedor@gnu.org) - -if $tracelevel then { - strace $tracelevel -} - -set testfile "basicclass" -set srcfile ${testfile}.m -set binfile ${objdir}/${subdir}/${testfile} - -# -# Objective-C program compilation isn't standard. We need to figure out -# which libraries to link in. Most of the time it uses pthread -# -if {[gdb_compile_objc "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable [list debug ]] != "" } { - return -1 -} - -# -# Deduce language of main() -# - -proc deduce_language_of_main {} { - global gdb_prompt - - # See what language gdb thinks main() is, prior to reading full symbols. - # I think this fails for COFF targets. - send_gdb "show language\n" - gdb_expect { - -re ".* source language is \"auto; currently objective-c\".*$gdb_prompt $" { - pass "deduced language is Objective-C, before full symbols" - } - -re ".*$gdb_prompt $" { - fail "source language not correct for Objective-C (psymtabs only)" - return - } - timeout { - fail "can't show language (timeout)" - return - } - } - - runto_main - - # See if our idea of the language has changed. - - send_gdb "show language\n" - gdb_expect { - -re ".* source language is \"auto; currently objective-c\".*$gdb_prompt $" { - pass "deduced language is Objective-C, after full symbols" - } - -re ".*$gdb_prompt $" { - fail "source language not correct for Objective-C (full symbols)" - return - } - timeout { - fail "can't show language (timeout)" - return - } - } -} - -proc do_objc_tests {} { - global prms_id - global bug_id - global subdir - global objdir - global srcdir - global binfile - global gdb_prompt - - set prms_id 0 - set bug_id 0 - - # Start with a fresh gdb. - - gdb_exit - gdb_start - gdb_reinitialize_dir $srcdir/$subdir - gdb_load $binfile - - deduce_language_of_main -} - -do_objc_tests - -# -# Breakpoint tests -# -gdb_test "break doIt" \ - "Breakpoint.*at.* file .*$srcfile, line.29.*" \ - "breakpoint method" - -gdb_test "break takeArg:" \ - "Breakpoint.*at.* file .*$srcfile, line.34.*" \ - "breakpoint method with colon" - -gdb_test "break newWithArg:" \ - "Breakpoint.*at.* file .*$srcfile, line.22.*" \ - "breakpoint class method with colon" - -# -# Continue until breakpoint (test re-setting breakpoint) -# -gdb_test continue \ - "Continuing\\..*Breakpoint \[0-9\]+, -.BasicClass takeArg:. \\(self=.*, _cmd=.*, arg=.*\\) at .*$srcfile:34.*" \ - "continue until method breakpoint" - -# -# Test resetting breakpoints when re-running program -# -gdb_run_cmd -gdb_expect { - -re "Breakpoint \[0-9\]+,.*main .*argc.*argv.* at .*$srcfile:.*$gdb_prompt $"\ - { pass "resetting breakpoints when rerunning" } - -re ".*$gdb_prompt $" { fail "resetting breakpoints when rerunning" } - timeout { fail "resetting breakpoints when rerunning" } -} - -# -# Continue until breakpoint (test re-setting breakpoint) -# -gdb_test continue \ - "Continuing\\..*Breakpoint \[0-9\]+, -.BasicClass takeArg:. \\(self=.*, _cmd=.*, arg=.*\\) at .*$srcfile:34.*" \ - "continue until method breakpoint" - -# -# Test printing objects -# -gdb_test "print object" \ - "\\$\[0-9\] = .*0x0" \ - " print an ivar of self" - -gdb_test "print self" \ - "\\$\[0-9\] = \\(.*BasicClass \\*\\) 0x\[0-9a-f\]+" \ - " print self" - -gdb_test "print \*self" \ - "\\$\[0-9\] = \{isa = 0x\[0-9a-f\]+, object = 0x0\}" \ - " print contents of self" - -# -# Break in a category -# -gdb_test "break hiddenMethod" \ - "Breakpoint.*at.* file .*$srcfile, line.61." \ - "breakpoint in category method" - - -# -# Continue until breakpoint (test re-setting category breakpoint) -# -gdb_test continue \ - "Continuing\\..*Breakpoint \[0-9\]+, -.BasicClass\\(Private\\) hiddenMethod. \\(self=.*, _cmd=.*\\) at .*$srcfile:61.*" \ - "continue until category method" - -# -# Test calling Objective-C methods -# -gdb_test "print \[self printHi\]" \ - "Hi.*\\$\[0-9\] = \\(.*objc_object \\*\\) 0x\[0-9a-f\]+" \ - "Call an Objective-C method with no arguments" - -gdb_test "print \[self printNumber: 42\]" \ - "42.*\\$\[0-9\] = 43" \ - "Call an Objective-C method with one argument" - -# -# Test printing the object description -# -gdb_test "print-object object" \ - "BasicClass gdb test object" \ - "Use of the print-object command" - -gdb_test "po self" \ - "BasicClass gdb test object" \ - "Use of the po (print-object) command" - - diff --git a/gdb/testsuite/gdb.objc/basicclass.m b/gdb/testsuite/gdb.objc/basicclass.m deleted file mode 100644 index 0de12db25a1..00000000000 --- a/gdb/testsuite/gdb.objc/basicclass.m +++ /dev/null @@ -1,81 +0,0 @@ -#include - -@interface BasicClass: Object -{ - id object; -} -+ newWithArg: arg; -- doIt; -- takeArg: arg; -- printHi; -- (int) printNumber: (int)number; -- (const char *) myDescription; -@end - -@interface BasicClass (Private) -- hiddenMethod; -@end - -@implementation BasicClass -+ newWithArg: arg -{ - id obj = [self new]; - [obj takeArg: arg]; - return obj; -} - -- doIt -{ - return self; -} - -- takeArg: arg -{ - object = arg; - [self hiddenMethod]; - return self; -} - -- printHi -{ - printf("Hi\n"); - return self; -} - -- (int) printNumber: (int)number -{ - printf("%d\n", number); - return number+1; -} - -- (const char *) myDescription -{ - return "BasicClass gdb test object"; -} - -@end - -@implementation BasicClass (Private) -- hiddenMethod -{ - return self; -} -@end - -int main (int argc, const char *argv[]) -{ - id obj; - obj = [BasicClass new]; - [obj takeArg: obj]; - return 0; -} - -const char *_NSPrintForDebugger(id object) -{ - /* This is not really what _NSPrintForDebugger should do, but it - is a simple test if gdb can call this function */ - if (object && [object respondsTo: @selector(myDescription)]) - return [object myDescription]; - - return NULL; -} diff --git a/gdb/testsuite/gdb.objc/nondebug.exp b/gdb/testsuite/gdb.objc/nondebug.exp deleted file mode 100644 index 9c7a7443524..00000000000 --- a/gdb/testsuite/gdb.objc/nondebug.exp +++ /dev/null @@ -1,77 +0,0 @@ -# Copyright 2003 Free Software Foundation, Inc. - -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - -# This file tests decoding non-debuggable Objective-C symbols - -# This file was written by Adam Fedor (fedor@gnu.org) - -if $tracelevel then { - strace $tracelevel -} - -set testfile "nondebug" -set srcfile ${testfile}.m -set binfile ${objdir}/${subdir}/${testfile} - -# -# Objective-C program compilation isn't standard. We need to figure out -# which libraries to link in. Most of the time it uses pthread -# -if {[gdb_compile_objc "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable [list ] ] != "" } { - return -1 -} - -proc do_objc_tests {} { - global prms_id - global bug_id - global subdir - global objdir - global srcdir - global binfile - global gdb_prompt - - set prms_id 0 - set bug_id 0 - - # Start with a fresh gdb. - - gdb_exit - gdb_start - gdb_reinitialize_dir $srcdir/$subdir - gdb_load $binfile - -} - -do_objc_tests - -# -# Break on multiply defined non-debuggable symbol (PR objc/1236) -# -set name "break on non-debuggable method" -gdb_test_multiple "break someMethod" $name \ -{ - -re "\\\[0\\\] cancel\r\n\\\[1\\\] all\r\n\\\[2\\\]\[ \]+-.NonDebug someMethod.*\\\[3\\\]\[ \]+-.NonDebug2 someMethod.*" { - send_gdb "2\n" - exp_continue - } - -re "\\\[0\\\] cancel\r\n\\\[1\\\] all\r\n> " { - gdb_test "0" "" "" - kfail "gdb/1236" $name - } - -re "Breakpoint \[0-9\]+ at 0x\[0-9a-f\]+.*$gdb_prompt $" { pass $name } - -re ".*$gdb_prompt $" { kfail "gdb/1236" $name } -} - diff --git a/gdb/testsuite/gdb.objc/nondebug.m b/gdb/testsuite/gdb.objc/nondebug.m deleted file mode 100644 index dcbdde936c7..00000000000 --- a/gdb/testsuite/gdb.objc/nondebug.m +++ /dev/null @@ -1,38 +0,0 @@ -#include - -@interface NonDebug: Object -{ -} -@end -@interface NonDebug2: Object -{ -} -@end - -@implementation NonDebug - -- someMethod -{ - printf("method someMethod\n"); - return self; -} - -@end -@implementation NonDebug2 - -- someMethod -{ - printf("method2 someMethod\n"); - return self; -} - -@end - - -int main (int argc, const char *argv[]) -{ - id obj; - obj = [NonDebug new]; - [obj someMethod]; - return 0; -} diff --git a/gdb/testsuite/gdb.objc/objcdecode.exp b/gdb/testsuite/gdb.objc/objcdecode.exp deleted file mode 100644 index e00bffeae77..00000000000 --- a/gdb/testsuite/gdb.objc/objcdecode.exp +++ /dev/null @@ -1,86 +0,0 @@ -# Copyright 2003 Free Software Foundation, Inc. - -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - -# This file tests decoding of Objective-C symbols - -# This file was written by Adam Fedor (fedor@gnu.org) - -if $tracelevel then { - strace $tracelevel -} - -set testfile "objcdecode" -set srcfile ${testfile}.m -set binfile ${objdir}/${subdir}/${testfile} - -# -# Objective-C program compilation isn't standard. We need to figure out -# which libraries to link in. Most of the time it uses pthread -# -if {[gdb_compile_objc "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable [list debug ]] != "" } { - return -1 -} - -proc do_objc_tests {} { - global prms_id - global bug_id - global subdir - global objdir - global srcdir - global binfile - global gdb_prompt - - set prms_id 0 - set bug_id 0 - - # Start with a fresh gdb. - - gdb_exit - gdb_start - gdb_reinitialize_dir $srcdir/$subdir - gdb_load $binfile - -} - -do_objc_tests - -# -# Break on multiply defined method (PR objc/1236) -# -set name "break on multiply defined method" -gdb_test_multiple "break multipleDef" $name \ -{ - -re "\\\[0\\\] cancel\r\n\\\[1\\\] all\r\n\\\[2\\\] -.Decode multipleDef. at .*\r\n\\\[3\\\] multipleDef at .*\r\n> $" { - send_gdb "3\n" - exp_continue - } - -re "Breakpoint \[0-9\]+ at 0x\[0-9a-f\]+: file .*\r\n$gdb_prompt $" { pass $name } - -re ".*$gdb_prompt $" { kfail "gdb/1236" $name } -} - -set name "continue after break on multiply defined symbol" -gdb_test_multiple "run" $name \ -{ - -re "Starting program.*Breakpoint \[0-9\]+, multipleDef \\\(\\\) at .*\r\n$gdb_prompt $" { - pass $name - } - -re "Starting program.*\\\[0\\\] cancel\r\n\\\[1\\\] all\r\n\\\[2\\\] -.Decode multipleDef. at .*\r\n\\\[3\\\] multipleDef at .*\r\n> $" { - send_gdb "0\n" - kfail "gdb/1238" $name - # gdb is in a bad state here. - # It would be difficult to do any more tests after this. - } -} diff --git a/gdb/testsuite/gdb.objc/objcdecode.m b/gdb/testsuite/gdb.objc/objcdecode.m deleted file mode 100644 index 5e99618d115..00000000000 --- a/gdb/testsuite/gdb.objc/objcdecode.m +++ /dev/null @@ -1,49 +0,0 @@ -#include - -@interface Decode: Object -{ -} -- multipleDef; -- (const char *) myDescription; -@end - -@implementation Decode - -- multipleDef -{ - printf("method multipleDef\n"); - return self; -} - -- (const char *) myDescription -{ - return "Decode gdb test object"; -} - -@end - -int -multipleDef() -{ - printf("function multipleDef\n"); - return 0; -} - -int main (int argc, const char *argv[]) -{ - id obj; - obj = [Decode new]; - multipleDef(); - [obj multipleDef]; - return 0; -} - -const char *_NSPrintForDebugger(id object) -{ - /* This is not really what _NSPrintForDebugger should do, but it - is a simple test if gdb can call this function */ - if (object && [object respondsTo: @selector(myDescription)]) - return [object myDescription]; - - return NULL; -} diff --git a/gdb/user-regs.c b/gdb/user-regs.c index 470a518796a..9de177f2843 100644 --- a/gdb/user-regs.c +++ b/gdb/user-regs.c @@ -1,6 +1,6 @@ /* User visible, per-frame registers, for GDB, the GNU debugger. - Copyright 2002 Free Software Foundation, Inc. + Copyright 2002, 2003, 2004 Free Software Foundation, Inc. Contributed by Red Hat. @@ -45,14 +45,20 @@ struct user_reg struct user_reg *next; }; -struct user_regs +/* This structure is named gdb_user_regs instead of user_regs to avoid + conflicts with any "struct user_regs" in system headers. For instance, + on ARM GNU/Linux native builds, nm-linux.h includes includes + includes includes , which + declares "struct user_regs". */ + +struct gdb_user_regs { struct user_reg *first; struct user_reg **last; }; static void -append_user_reg (struct user_regs *regs, const char *name, +append_user_reg (struct gdb_user_regs *regs, const char *name, user_reg_read_ftype *read, struct user_reg *reg) { /* The caller is responsible for allocating memory needed to store @@ -68,7 +74,7 @@ append_user_reg (struct user_regs *regs, const char *name, /* An array of the builtin user registers. */ -static struct user_regs builtin_user_regs = { NULL, &builtin_user_regs.first }; +static struct gdb_user_regs builtin_user_regs = { NULL, &builtin_user_regs.first }; void user_reg_add_builtin (const char *name, user_reg_read_ftype *read) @@ -86,7 +92,7 @@ static void * user_regs_init (struct gdbarch *gdbarch) { struct user_reg *reg; - struct user_regs *regs = GDBARCH_OBSTACK_ZALLOC (gdbarch, struct user_regs); + struct gdb_user_regs *regs = GDBARCH_OBSTACK_ZALLOC (gdbarch, struct gdb_user_regs); regs->last = ®s->first; for (reg = builtin_user_regs.first; reg != NULL; reg = reg->next) append_user_reg (regs, reg->name, reg->read, @@ -98,7 +104,7 @@ void user_reg_add (struct gdbarch *gdbarch, const char *name, user_reg_read_ftype *read) { - struct user_regs *regs = gdbarch_data (gdbarch, user_regs_data); + struct gdb_user_regs *regs = gdbarch_data (gdbarch, user_regs_data); if (regs == NULL) { /* ULGH, called during architecture initialization. Patch @@ -137,7 +143,7 @@ user_reg_map_name_to_regnum (struct gdbarch *gdbarch, const char *name, /* Search the user name space. */ { - struct user_regs *regs = gdbarch_data (gdbarch, user_regs_data); + struct gdb_user_regs *regs = gdbarch_data (gdbarch, user_regs_data); struct user_reg *reg; int nr; for (nr = 0, reg = regs->first; reg != NULL; reg = reg->next, nr++) @@ -155,7 +161,7 @@ user_reg_map_name_to_regnum (struct gdbarch *gdbarch, const char *name, static struct user_reg * usernum_to_user_reg (struct gdbarch *gdbarch, int usernum) { - struct user_regs *regs = gdbarch_data (gdbarch, user_regs_data); + struct gdb_user_regs *regs = gdbarch_data (gdbarch, user_regs_data); struct user_reg *reg; for (reg = regs->first; reg != NULL; reg = reg->next) { diff --git a/gdb/version.in b/gdb/version.in index 5e3690770c1..909e279ceda 100644 --- a/gdb/version.in +++ b/gdb/version.in @@ -1 +1 @@ -2004-02-29-cvs +2004-03-09-cvs diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog index ea008d62423..6e4d604b2d0 100644 --- a/include/elf/ChangeLog +++ b/include/elf/ChangeLog @@ -1,3 +1,11 @@ +2003-03-03 Andrew Stubbs + + * sh.h: Add EF_SH4_NOMMU_NOFPU. + +2004-03-01 Richard Sandiford + + * frv.h (EF_FRV_CPU_FR405, EF_FRV_CPU_FR450): Define. + 2004-01-28 Roland McGrath * common.h (AT_SECURE): New macro. diff --git a/include/elf/frv.h b/include/elf/frv.h index 8246a21bd41..a6b8a7d145d 100644 --- a/include/elf/frv.h +++ b/include/elf/frv.h @@ -91,6 +91,8 @@ END_RELOC_NUMBERS(R_FRV_max) #define EF_FRV_CPU_TOMCAT 0x04000000 /* Tomcat, FR500 prototype */ #define EF_FRV_CPU_FR400 0x05000000 /* FRV400 */ #define EF_FRV_CPU_FR550 0x06000000 /* FRV550 */ +#define EF_FRV_CPU_FR405 0x07000000 +#define EF_FRV_CPU_FR450 0x08000000 /* Mask of PIC related bits */ #define EF_FRV_PIC_FLAGS (EF_FRV_PIC | EF_FRV_LIBPIC | EF_FRV_BIGPIC \ diff --git a/include/elf/sh.h b/include/elf/sh.h index 15d460d36b4..c46a5ff149f 100644 --- a/include/elf/sh.h +++ b/include/elf/sh.h @@ -1,5 +1,5 @@ /* SH ELF support for BFD. - Copyright 1998, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + Copyright 1998, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. This file is part of BFD, the Binary File Descriptor library. @@ -39,6 +39,7 @@ #define EF_SH4_NOFPU 0x10 #define EF_SH4A_NOFPU 0x11 +#define EF_SH4_NOMMU_NOFPU 0x12 /* This one can only mix in objects from other EF_SH5 objects. */ #define EF_SH5 10 diff --git a/libiberty/ChangeLog b/libiberty/ChangeLog index b9d6e73f89e..a3de6c2a6d1 100644 --- a/libiberty/ChangeLog +++ b/libiberty/ChangeLog @@ -1,3 +1,13 @@ +2004-03-09 Hans-Peter Nilsson + + * configure: Regenerate for config/accross.m4 correction. + +2004-03-07 Andreas Jaeger + + * testsuite/test-demangle.c: Include and for + prototypes. + (main): Initialize style. + 2004-02-24 Ian Lance Taylor * cp-demangle.h (enum d_builtin_type_print): Add D_PRINT_UNSIGNED, diff --git a/libiberty/configure b/libiberty/configure index 2f65976692d..78d30130d48 100755 --- a/libiberty/configure +++ b/libiberty/configure @@ -1,9 +1,8 @@ #! /bin/sh # Guess values for system-dependent variables and create Makefiles. -# Generated by GNU Autoconf 2.57. +# Generated by GNU Autoconf 2.58. # -# Copyright 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, 2002 -# Free Software Foundation, Inc. +# Copyright (C) 2003 Free Software Foundation, Inc. # This configure script is free software; the Free Software Foundation # gives unlimited permission to copy, distribute and modify it. ## --------------------- ## @@ -20,9 +19,10 @@ if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then elif test -n "${BASH_VERSION+set}" && (set -o posix) >/dev/null 2>&1; then set -o posix fi +DUALCASE=1; export DUALCASE # for MKS sh # Support unset when possible. -if (FOO=FOO; unset FOO) >/dev/null 2>&1; then +if ( (MAIL=60; unset MAIL) || exit) >/dev/null 2>&1; then as_unset=unset else as_unset=false @@ -41,7 +41,7 @@ for as_var in \ LC_MEASUREMENT LC_MESSAGES LC_MONETARY LC_NAME LC_NUMERIC LC_PAPER \ LC_TELEPHONE LC_TIME do - if (set +x; test -n "`(eval $as_var=C; export $as_var) 2>&1`"); then + if (set +x; test -z "`(eval $as_var=C; export $as_var) 2>&1`"); then eval $as_var=C; export $as_var else $as_unset $as_var @@ -218,16 +218,17 @@ rm -f conf$$ conf$$.exe conf$$.file if mkdir -p . 2>/dev/null; then as_mkdir_p=: else + test -d ./-p && rmdir ./-p as_mkdir_p=false fi as_executable_p="test -f" # Sed expression to map a string onto a valid CPP name. -as_tr_cpp="sed y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g" +as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'" # Sed expression to map a string onto a valid variable name. -as_tr_sh="sed y%*+%pp%;s%[^_$as_cr_alnum]%_%g" +as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'" # IFS @@ -667,7 +668,7 @@ done # Be sure to have absolute paths. for ac_var in bindir sbindir libexecdir datadir sysconfdir sharedstatedir \ - localstatedir libdir includedir oldincludedir infodir mandir + localstatedir libdir includedir oldincludedir infodir mandir do eval ac_val=$`echo $ac_var` case $ac_val in @@ -707,10 +708,10 @@ if test -z "$srcdir"; then # Try the directory containing this script, then its parent. ac_confdir=`(dirname "$0") 2>/dev/null || $as_expr X"$0" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ - X"$0" : 'X\(//\)[^/]' \| \ - X"$0" : 'X\(//\)$' \| \ - X"$0" : 'X\(/\)' \| \ - . : '\(.\)' 2>/dev/null || + X"$0" : 'X\(//\)[^/]' \| \ + X"$0" : 'X\(//\)$' \| \ + X"$0" : 'X\(/\)' \| \ + . : '\(.\)' 2>/dev/null || echo X"$0" | sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; } /^X\(\/\/\)[^/].*/{ s//\1/; q; } @@ -802,9 +803,9 @@ _ACEOF cat <<_ACEOF Installation directories: --prefix=PREFIX install architecture-independent files in PREFIX - [$ac_default_prefix] + [$ac_default_prefix] --exec-prefix=EPREFIX install architecture-dependent files in EPREFIX - [PREFIX] + [PREFIX] By default, \`make install' will install all the files in \`$ac_default_prefix/bin', \`$ac_default_prefix/lib' etc. You can specify @@ -901,12 +902,42 @@ case $srcdir in ac_srcdir=$ac_top_builddir$srcdir$ac_dir_suffix ac_top_srcdir=$ac_top_builddir$srcdir ;; esac -# Don't blindly perform a `cd "$ac_dir"/$ac_foo && pwd` since $ac_foo can be -# absolute. -ac_abs_builddir=`cd "$ac_dir" && cd $ac_builddir && pwd` -ac_abs_top_builddir=`cd "$ac_dir" && cd ${ac_top_builddir}. && pwd` -ac_abs_srcdir=`cd "$ac_dir" && cd $ac_srcdir && pwd` -ac_abs_top_srcdir=`cd "$ac_dir" && cd $ac_top_srcdir && pwd` +case "$ac_dir" in +.) ac_abs_builddir=$ac_builddir;; +*) + case $ac_builddir in + .) ac_abs_builddir="$ac_dir";; + [\\/]* | ?:[\\/]* ) ac_abs_builddir=$ac_builddir;; + *) ac_abs_builddir="$ac_dir"/$ac_builddir;; + esac;; +esac +case "$ac_dir" in +.) ac_abs_top_builddir=${ac_top_builddir}.;; +*) + case ${ac_top_builddir}. in + .) ac_abs_top_builddir="$ac_dir";; + [\\/]* | ?:[\\/]* ) ac_abs_top_builddir=${ac_top_builddir}.;; + *) ac_abs_top_builddir="$ac_dir"/${ac_top_builddir}.;; + esac;; +esac +case "$ac_dir" in +.) ac_abs_srcdir=$ac_srcdir;; +*) + case $ac_srcdir in + .) ac_abs_srcdir="$ac_dir";; + [\\/]* | ?:[\\/]* ) ac_abs_srcdir=$ac_srcdir;; + *) ac_abs_srcdir="$ac_dir"/$ac_srcdir;; + esac;; +esac +case "$ac_dir" in +.) ac_abs_top_srcdir=$ac_top_srcdir;; +*) + case $ac_top_srcdir in + .) ac_abs_top_srcdir="$ac_dir";; + [\\/]* | ?:[\\/]* ) ac_abs_top_srcdir=$ac_top_srcdir;; + *) ac_abs_top_srcdir="$ac_dir"/$ac_top_srcdir;; + esac;; +esac cd $ac_dir # Check for guested configure; otherwise get Cygnus style configure. @@ -917,7 +948,7 @@ ac_abs_top_srcdir=`cd "$ac_dir" && cd $ac_top_srcdir && pwd` echo $SHELL $ac_srcdir/configure --help=recursive elif test -f $ac_srcdir/configure.ac || - test -f $ac_srcdir/configure.in; then + test -f $ac_srcdir/configure.in; then echo $ac_configure --help else @@ -931,8 +962,7 @@ test -n "$ac_init_help" && exit 0 if $ac_init_version; then cat <<\_ACEOF -Copyright 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, 2002 -Free Software Foundation, Inc. +Copyright (C) 2003 Free Software Foundation, Inc. This configure script is free software; the Free Software Foundation gives unlimited permission to copy, distribute and modify it. _ACEOF @@ -944,7 +974,7 @@ This file contains any messages produced by compilers while running configure, to aid debugging if configure makes a mistake. It was created by $as_me, which was -generated by GNU Autoconf 2.57. Invocation command line was +generated by GNU Autoconf 2.58. Invocation command line was $ $0 $@ @@ -1021,19 +1051,19 @@ do 2) ac_configure_args1="$ac_configure_args1 '$ac_arg'" if test $ac_must_keep_next = true; then - ac_must_keep_next=false # Got value, back to normal. + ac_must_keep_next=false # Got value, back to normal. else - case $ac_arg in - *=* | --config-cache | -C | -disable-* | --disable-* \ - | -enable-* | --enable-* | -gas | --g* | -nfp | --nf* \ - | -q | -quiet | --q* | -silent | --sil* | -v | -verb* \ - | -with-* | --with-* | -without-* | --without-* | --x) - case "$ac_configure_args0 " in - "$ac_configure_args1"*" '$ac_arg' "* ) continue ;; - esac - ;; - -* ) ac_must_keep_next=true ;; - esac + case $ac_arg in + *=* | --config-cache | -C | -disable-* | --disable-* \ + | -enable-* | --enable-* | -gas | --g* | -nfp | --nf* \ + | -q | -quiet | --q* | -silent | --sil* | -v | -verb* \ + | -with-* | --with-* | -without-* | --without-* | --x) + case "$ac_configure_args0 " in + "$ac_configure_args1"*" '$ac_arg' "* ) continue ;; + esac + ;; + -* ) ac_must_keep_next=true ;; + esac fi ac_configure_args="$ac_configure_args$ac_sep'$ac_arg'" # Get rid of the leading space. @@ -1067,12 +1097,12 @@ _ASBOX case `(ac_space='"'"' '"'"'; set | grep ac_space) 2>&1` in *ac_space=\ *) sed -n \ - "s/'"'"'/'"'"'\\\\'"'"''"'"'/g; - s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='"'"'\\2'"'"'/p" + "s/'"'"'/'"'"'\\\\'"'"''"'"'/g; + s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='"'"'\\2'"'"'/p" ;; *) sed -n \ - "s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1=\\2/p" + "s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1=\\2/p" ;; esac; } @@ -1101,7 +1131,7 @@ _ASBOX for ac_var in $ac_subst_files do eval ac_val=$`echo $ac_var` - echo "$ac_var='"'"'$ac_val'"'"'" + echo "$ac_var='"'"'$ac_val'"'"'" done | sort echo fi @@ -1120,7 +1150,7 @@ _ASBOX echo "$as_me: caught signal $ac_signal" echo "$as_me: exit $exit_status" } >&5 - rm -f core core.* *.core && + rm -f core *.core && rm -rf conftest* confdefs* conf$$* $ac_clean_files && exit $exit_status ' 0 @@ -1200,7 +1230,7 @@ fi # value. ac_cache_corrupted=false for ac_var in `(set) 2>&1 | - sed -n 's/^ac_env_\([a-zA-Z_0-9]*\)_set=.*/\1/p'`; do + sed -n 's/^ac_env_\([a-zA-Z_0-9]*\)_set=.*/\1/p'`; do eval ac_old_set=\$ac_cv_env_${ac_var}_set eval ac_new_set=\$ac_env_${ac_var}_set eval ac_old_val="\$ac_cv_env_${ac_var}_value" @@ -1217,13 +1247,13 @@ echo "$as_me: error: \`$ac_var' was not set in the previous run" >&2;} ,);; *) if test "x$ac_old_val" != "x$ac_new_val"; then - { echo "$as_me:$LINENO: error: \`$ac_var' has changed since the previous run:" >&5 + { echo "$as_me:$LINENO: error: \`$ac_var' has changed since the previous run:" >&5 echo "$as_me: error: \`$ac_var' has changed since the previous run:" >&2;} - { echo "$as_me:$LINENO: former value: $ac_old_val" >&5 + { echo "$as_me:$LINENO: former value: $ac_old_val" >&5 echo "$as_me: former value: $ac_old_val" >&2;} - { echo "$as_me:$LINENO: current value: $ac_new_val" >&5 + { echo "$as_me:$LINENO: current value: $ac_new_val" >&5 echo "$as_me: current value: $ac_new_val" >&2;} - ac_cache_corrupted=: + ac_cache_corrupted=: fi;; esac # Pass precious variables to config.status. @@ -2030,7 +2060,6 @@ ac_compiler=`set X $ac_compile; echo $2` (exit $ac_status); } cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -2064,7 +2093,6 @@ if test x$gcc_no_link = xyes; then EXEEXT= else cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -2084,8 +2112,8 @@ ac_clean_files="$ac_clean_files a.out a.exe b.out" # Try to create an executable without -o first, disregard a.out. # It will help us diagnose broken compilers, and finding out an intuition # of exeext. -echo "$as_me:$LINENO: checking for C compiler default output" >&5 -echo $ECHO_N "checking for C compiler default output... $ECHO_C" >&6 +echo "$as_me:$LINENO: checking for C compiler default output file name" >&5 +echo $ECHO_N "checking for C compiler default output file name... $ECHO_C" >&6 ac_link_default=`echo "$ac_link" | sed 's/ -o *conftest[^ ]*//'` if { (eval echo "$as_me:$LINENO: \"$ac_link_default\"") >&5 (eval $ac_link_default) 2>&5 @@ -2105,23 +2133,23 @@ do test -f "$ac_file" || continue case $ac_file in *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.o | *.obj ) - ;; + ;; conftest.$ac_ext ) - # This is the source file. - ;; + # This is the source file. + ;; [ab].out ) - # We found the default executable, but exeext='' is most - # certainly right. - break;; + # We found the default executable, but exeext='' is most + # certainly right. + break;; *.* ) - ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'` - # FIXME: I believe we export ac_cv_exeext for Libtool, - # but it would be cool to find out if it's true. Does anybody - # maintain Libtool? --akim. - export ac_cv_exeext - break;; + ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'` + # FIXME: I believe we export ac_cv_exeext for Libtool, + # but it would be cool to find out if it's true. Does anybody + # maintain Libtool? --akim. + export ac_cv_exeext + break;; * ) - break;; + break;; esac done else @@ -2195,8 +2223,8 @@ for ac_file in conftest.exe conftest conftest.*; do case $ac_file in *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.o | *.obj ) ;; *.* ) ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'` - export ac_cv_exeext - break;; + export ac_cv_exeext + break;; * ) break;; esac done @@ -2222,7 +2250,6 @@ if test "${ac_cv_objext+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -2273,7 +2300,6 @@ if test "${ac_cv_c_compiler_gnu+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -2293,11 +2319,21 @@ main () _ACEOF rm -f conftest.$ac_objext if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>&5 + (eval $ac_compile) 2>conftest.er1 ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && - { ac_try='test -s conftest.$ac_objext' + { ac_try='test -z "$ac_c_werror_flag" + || test ! -s conftest.err' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest.$ac_objext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? @@ -2310,7 +2346,7 @@ sed 's/^/| /' conftest.$ac_ext >&5 ac_compiler_gnu=no fi -rm -f conftest.$ac_objext conftest.$ac_ext +rm -f conftest.err conftest.$ac_objext conftest.$ac_ext ac_cv_c_compiler_gnu=$ac_compiler_gnu fi @@ -2326,7 +2362,6 @@ if test "${ac_cv_prog_cc_g+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -2343,11 +2378,21 @@ main () _ACEOF rm -f conftest.$ac_objext if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>&5 + (eval $ac_compile) 2>conftest.er1 ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && - { ac_try='test -s conftest.$ac_objext' + { ac_try='test -z "$ac_c_werror_flag" + || test ! -s conftest.err' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest.$ac_objext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? @@ -2360,7 +2405,7 @@ sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_prog_cc_g=no fi -rm -f conftest.$ac_objext conftest.$ac_ext +rm -f conftest.err conftest.$ac_objext conftest.$ac_ext fi echo "$as_me:$LINENO: result: $ac_cv_prog_cc_g" >&5 echo "${ECHO_T}$ac_cv_prog_cc_g" >&6 @@ -2387,7 +2432,6 @@ else ac_cv_prog_cc_stdc=no ac_save_CC=$CC cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -2415,6 +2459,16 @@ static char *f (char * (*g) (char **, int), char **p, ...) va_end (v); return s; } + +/* OSF 4.0 Compaq cc is some sort of almost-ANSI by default. It has + function prototypes and stuff, but not '\xHH' hex character constants. + These don't provoke an error unfortunately, instead are silently treated + as 'x'. The following induces an error, until -std1 is added to get + proper ANSI mode. Curiously '\x00'!='x' always comes out true, for an + array size at least. It's necessary to write '\x00'==0 to get something + that's true only with -std1. */ +int osf4_cc_array ['\x00' == 0 ? 1 : -1]; + int test (int i, double x); struct s1 {int (*f) (int a);}; struct s2 {int (*f) (double a);}; @@ -2441,11 +2495,21 @@ do CC="$ac_save_CC $ac_arg" rm -f conftest.$ac_objext if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>&5 + (eval $ac_compile) 2>conftest.er1 ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && - { ac_try='test -s conftest.$ac_objext' + { ac_try='test -z "$ac_c_werror_flag" + || test ! -s conftest.err' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest.$ac_objext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? @@ -2458,7 +2522,7 @@ else sed 's/^/| /' conftest.$ac_ext >&5 fi -rm -f conftest.$ac_objext +rm -f conftest.err conftest.$ac_objext done rm -f conftest.$ac_ext conftest.$ac_objext CC=$ac_save_CC @@ -2486,19 +2550,28 @@ cat >conftest.$ac_ext <<_ACEOF _ACEOF rm -f conftest.$ac_objext if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>&5 + (eval $ac_compile) 2>conftest.er1 ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && - { ac_try='test -s conftest.$ac_objext' + { ac_try='test -z "$ac_c_werror_flag" + || test ! -s conftest.err' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest.$ac_objext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then for ac_declaration in \ - ''\ - '#include ' \ + '' \ 'extern "C" void std::exit (int) throw (); using std::exit;' \ 'extern "C" void std::exit (int); using std::exit;' \ 'extern "C" void exit (int) throw ();' \ @@ -2506,14 +2579,13 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 'void exit (int);' do cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ -#include $ac_declaration +#include int main () { @@ -2524,11 +2596,21 @@ exit (42); _ACEOF rm -f conftest.$ac_objext if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>&5 + (eval $ac_compile) 2>conftest.er1 ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && - { ac_try='test -s conftest.$ac_objext' + { ac_try='test -z "$ac_c_werror_flag" + || test ! -s conftest.err' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest.$ac_objext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? @@ -2541,9 +2623,8 @@ sed 's/^/| /' conftest.$ac_ext >&5 continue fi -rm -f conftest.$ac_objext conftest.$ac_ext +rm -f conftest.err conftest.$ac_objext conftest.$ac_ext cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -2560,11 +2641,21 @@ exit (42); _ACEOF rm -f conftest.$ac_objext if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>&5 + (eval $ac_compile) 2>conftest.er1 ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && - { ac_try='test -s conftest.$ac_objext' + { ac_try='test -z "$ac_c_werror_flag" + || test ! -s conftest.err' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest.$ac_objext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? @@ -2576,7 +2667,7 @@ else sed 's/^/| /' conftest.$ac_ext >&5 fi -rm -f conftest.$ac_objext conftest.$ac_ext +rm -f conftest.err conftest.$ac_objext conftest.$ac_ext done rm -f conftest* if test -n "$ac_declaration"; then @@ -2590,7 +2681,7 @@ else sed 's/^/| /' conftest.$ac_ext >&5 fi -rm -f conftest.$ac_objext conftest.$ac_ext +rm -f conftest.err conftest.$ac_objext conftest.$ac_ext ac_ext=c ac_cpp='$CPP $CPPFLAGS' ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' @@ -2625,7 +2716,6 @@ do # On the NeXT, cc -E runs the code through the compiler's parser, # not just through cpp. "Syntax error" is here to catch this case. cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -2636,7 +2726,7 @@ cat >>conftest.$ac_ext <<_ACEOF #else # include #endif - Syntax error + Syntax error _ACEOF if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5 (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1 @@ -2648,6 +2738,7 @@ if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5 (exit $ac_status); } >/dev/null; then if test -s conftest.err; then ac_cpp_err=$ac_c_preproc_warn_flag + ac_cpp_err=$ac_cpp_err$ac_c_werror_flag else ac_cpp_err= fi @@ -2668,7 +2759,6 @@ rm -f conftest.err conftest.$ac_ext # OK, works on sane cases. Now check whether non-existent headers # can be detected and how. cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -2686,6 +2776,7 @@ if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5 (exit $ac_status); } >/dev/null; then if test -s conftest.err; then ac_cpp_err=$ac_c_preproc_warn_flag + ac_cpp_err=$ac_cpp_err$ac_c_werror_flag else ac_cpp_err= fi @@ -2732,7 +2823,6 @@ do # On the NeXT, cc -E runs the code through the compiler's parser, # not just through cpp. "Syntax error" is here to catch this case. cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -2743,7 +2833,7 @@ cat >>conftest.$ac_ext <<_ACEOF #else # include #endif - Syntax error + Syntax error _ACEOF if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5 (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1 @@ -2755,6 +2845,7 @@ if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5 (exit $ac_status); } >/dev/null; then if test -s conftest.err; then ac_cpp_err=$ac_c_preproc_warn_flag + ac_cpp_err=$ac_cpp_err$ac_c_werror_flag else ac_cpp_err= fi @@ -2775,7 +2866,6 @@ rm -f conftest.err conftest.$ac_ext # OK, works on sane cases. Now check whether non-existent headers # can be detected and how. cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -2793,6 +2883,7 @@ if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5 (exit $ac_status); } >/dev/null; then if test -s conftest.err; then ac_cpp_err=$ac_c_preproc_warn_flag + ac_cpp_err=$ac_cpp_err$ac_c_werror_flag else ac_cpp_err= fi @@ -2852,7 +2943,6 @@ if eval "test \"\${ac_cv_prog_cc_${ac_cc}_c_o+set}\" = set"; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -2903,11 +2993,11 @@ then echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; then - # cc works too. - : + # cc works too. + : else - # cc exists but doesn't like -o. - eval ac_cv_prog_cc_${ac_cc}_c_o=no + # cc exists but doesn't like -o. + eval ac_cv_prog_cc_${ac_cc}_c_o=no fi fi fi @@ -2946,7 +3036,6 @@ if test "${ac_cv_c_const+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -3009,11 +3098,21 @@ main () _ACEOF rm -f conftest.$ac_objext if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>&5 + (eval $ac_compile) 2>conftest.er1 ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && - { ac_try='test -s conftest.$ac_objext' + { ac_try='test -z "$ac_c_werror_flag" + || test ! -s conftest.err' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest.$ac_objext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? @@ -3026,7 +3125,7 @@ sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_c_const=no fi -rm -f conftest.$ac_objext conftest.$ac_ext +rm -f conftest.err conftest.$ac_objext conftest.$ac_ext fi echo "$as_me:$LINENO: result: $ac_cv_c_const" >&5 echo "${ECHO_T}$ac_cv_c_const" >&6 @@ -3046,7 +3145,6 @@ else ac_cv_c_inline=no for ac_kw in inline __inline__ __inline; do cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -3061,11 +3159,21 @@ $ac_kw foo_t foo () {return 0; } _ACEOF rm -f conftest.$ac_objext if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>&5 + (eval $ac_compile) 2>conftest.er1 ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && - { ac_try='test -s conftest.$ac_objext' + { ac_try='test -z "$ac_c_werror_flag" + || test ! -s conftest.err' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest.$ac_objext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? @@ -3077,23 +3185,27 @@ else sed 's/^/| /' conftest.$ac_ext >&5 fi -rm -f conftest.$ac_objext conftest.$ac_ext +rm -f conftest.err conftest.$ac_objext conftest.$ac_ext done fi echo "$as_me:$LINENO: result: $ac_cv_c_inline" >&5 echo "${ECHO_T}$ac_cv_c_inline" >&6 + + case $ac_cv_c_inline in inline | yes) ;; - no) -cat >>confdefs.h <<\_ACEOF -#define inline -_ACEOF - ;; - *) cat >>confdefs.h <<_ACEOF -#define inline $ac_cv_c_inline + *) + case $ac_cv_c_inline in + no) ac_val=;; + *) ac_val=$ac_cv_c_inline;; + esac + cat >>confdefs.h <<_ACEOF +#ifndef __cplusplus +#define inline $ac_val +#endif _ACEOF - ;; + ;; esac echo "$as_me:$LINENO: checking whether byte ordering is bigendian" >&5 @@ -3104,7 +3216,6 @@ else ac_cv_c_bigendian=unknown # See if sys/param.h defines the BYTE_ORDER macro. cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -3125,11 +3236,21 @@ main () _ACEOF rm -f conftest.$ac_objext if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>&5 + (eval $ac_compile) 2>conftest.er1 ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && - { ac_try='test -s conftest.$ac_objext' + { ac_try='test -z "$ac_c_werror_flag" + || test ! -s conftest.err' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest.$ac_objext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? @@ -3137,7 +3258,6 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 (exit $ac_status); }; }; then # It does; now see whether it defined to BIG_ENDIAN or not. cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -3158,11 +3278,21 @@ main () _ACEOF rm -f conftest.$ac_objext if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>&5 + (eval $ac_compile) 2>conftest.er1 ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && - { ac_try='test -s conftest.$ac_objext' + { ac_try='test -z "$ac_c_werror_flag" + || test ! -s conftest.err' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest.$ac_objext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? @@ -3175,19 +3305,18 @@ sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_c_bigendian=no fi -rm -f conftest.$ac_objext conftest.$ac_ext +rm -f conftest.err conftest.$ac_objext conftest.$ac_ext else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi -rm -f conftest.$ac_objext conftest.$ac_ext +rm -f conftest.err conftest.$ac_objext conftest.$ac_ext if test $ac_cv_c_bigendian = unknown; then if test "$cross_compiling" = yes; then echo $ac_n "cross-compiling... " 2>&6 else cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -3224,7 +3353,7 @@ sed 's/^/| /' conftest.$ac_ext >&5 ( exit $ac_status ) ac_cv_c_bigendian=yes fi -rm -f core core.* *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext +rm -f core *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext fi fi fi @@ -3244,7 +3373,7 @@ void _ebcdic() { char* s = (char*) ebcdic_mm; s = (char*) ebcdic_ii; } int main() { _ascii (); _ebcdic (); return 0; } EOF if test -f conftest.c ; then - if ${CC-cc} ${CFLAGS} conftest.c -o conftest.o && test -f conftest.o ; then + if ${CC-cc} ${CFLAGS} -c conftest.c -o conftest.o && test -f conftest.o ; then if test `grep -l BIGenDianSyS conftest.o` ; then echo $ac_n ' big endian probe OK, ' 1>&6 ac_cv_c_bigendian=yes @@ -3284,9 +3413,9 @@ cat >>confdefs.h <<_ACEOF _ACEOF if test $ac_cv_c_bigendian = unknown; then - { { echo "$as_me:$LINENO: error: unknown endianess - sorry" >&5 -echo "$as_me: error: unknown endianess - sorry" >&2;} - { (exit please pre-set ac_cv_c_bigendian); exit please pre-set ac_cv_c_bigendian; }; } + { { echo "$as_me:$LINENO: error: unknown endianess - sorry, please pre-set ac_cv_c_bigendian" >&5 +echo "$as_me: error: unknown endianess - sorry, please pre-set ac_cv_c_bigendian" >&2;} + { (exit 1); exit 1; }; } fi @@ -3307,6 +3436,7 @@ fi # AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag # AFS /usr/afsws/bin/install, which mishandles nonexistent args # SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff" +# OS/2's system install, which has a completely different semantic # ./install, which can be erroneously created by make from ./install.sh. echo "$as_me:$LINENO: checking for a BSD-compatible install" >&5 echo $ECHO_N "checking for a BSD-compatible install... $ECHO_C" >&6 @@ -3323,6 +3453,7 @@ do case $as_dir/ in ./ | .// | /cC/* | \ /etc/* | /usr/sbin/* | /usr/etc/* | /sbin/* | /usr/afsws/bin/* | \ + ?:\\/os2\\/install\\/* | ?:\\/OS2\\/INSTALL\\/* | \ /usr/ucb/* ) ;; *) # OSF1 and SCO ODT 3.0 have their own names for install. @@ -3330,20 +3461,20 @@ case $as_dir/ in # by default. for ac_prog in ginstall scoinst install; do for ac_exec_ext in '' $ac_executable_extensions; do - if $as_executable_p "$as_dir/$ac_prog$ac_exec_ext"; then - if test $ac_prog = install && - grep dspmsg "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then - # AIX install. It has an incompatible calling convention. - : - elif test $ac_prog = install && - grep pwplus "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then - # program-specific install script used by HP pwplus--don't use. - : - else - ac_cv_path_install="$as_dir/$ac_prog$ac_exec_ext -c" - break 3 - fi - fi + if $as_executable_p "$as_dir/$ac_prog$ac_exec_ext"; then + if test $ac_prog = install && + grep dspmsg "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then + # AIX install. It has an incompatible calling convention. + : + elif test $ac_prog = install && + grep pwplus "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then + # program-specific install script used by HP pwplus--don't use. + : + else + ac_cv_path_install="$as_dir/$ac_prog$ac_exec_ext -c" + break 3 + fi + fi done done ;; @@ -3413,7 +3544,6 @@ if eval "test \"\${$as_ac_Header+set}\" = set"; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -3431,6 +3561,7 @@ if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5 (exit $ac_status); } >/dev/null; then if test -s conftest.err; then ac_cpp_err=$ac_c_preproc_warn_flag + ac_cpp_err=$ac_cpp_err$ac_c_werror_flag else ac_cpp_err= fi @@ -3463,7 +3594,6 @@ if test "${ac_cv_header_sys_wait_h+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -3490,11 +3620,21 @@ main () _ACEOF rm -f conftest.$ac_objext if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>&5 + (eval $ac_compile) 2>conftest.er1 ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && - { ac_try='test -s conftest.$ac_objext' + { ac_try='test -z "$ac_c_werror_flag" + || test ! -s conftest.err' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest.$ac_objext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? @@ -3507,7 +3647,7 @@ sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_header_sys_wait_h=no fi -rm -f conftest.$ac_objext conftest.$ac_ext +rm -f conftest.err conftest.$ac_objext conftest.$ac_ext fi echo "$as_me:$LINENO: result: $ac_cv_header_sys_wait_h" >&5 echo "${ECHO_T}$ac_cv_header_sys_wait_h" >&6 @@ -3525,7 +3665,6 @@ if test "${ac_cv_header_time+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -3546,11 +3685,21 @@ return 0; _ACEOF rm -f conftest.$ac_objext if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>&5 + (eval $ac_compile) 2>conftest.er1 ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && - { ac_try='test -s conftest.$ac_objext' + { ac_try='test -z "$ac_c_werror_flag" + || test ! -s conftest.err' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest.$ac_objext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? @@ -3563,7 +3712,7 @@ sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_header_time=no fi -rm -f conftest.$ac_objext conftest.$ac_ext +rm -f conftest.err conftest.$ac_objext conftest.$ac_ext fi echo "$as_me:$LINENO: result: $ac_cv_header_time" >&5 echo "${ECHO_T}$ac_cv_header_time" >&6 @@ -3582,7 +3731,6 @@ if test "${libiberty_cv_declare_errno+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -3599,11 +3747,21 @@ int x = errno; _ACEOF rm -f conftest.$ac_objext if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>&5 + (eval $ac_compile) 2>conftest.er1 ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && - { ac_try='test -s conftest.$ac_objext' + { ac_try='test -z "$ac_c_werror_flag" + || test ! -s conftest.err' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest.$ac_objext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? @@ -3616,7 +3774,7 @@ sed 's/^/| /' conftest.$ac_ext >&5 libiberty_cv_declare_errno=yes fi -rm -f conftest.$ac_objext conftest.$ac_ext +rm -f conftest.err conftest.$ac_objext conftest.$ac_ext fi echo "$as_me:$LINENO: result: $libiberty_cv_declare_errno" >&5 echo "${ECHO_T}$libiberty_cv_declare_errno" >&6 @@ -3650,7 +3808,6 @@ if test "${ac_cv_header_stdc+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -3671,11 +3828,21 @@ main () _ACEOF rm -f conftest.$ac_objext if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>&5 + (eval $ac_compile) 2>conftest.er1 ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && - { ac_try='test -s conftest.$ac_objext' + { ac_try='test -z "$ac_c_werror_flag" + || test ! -s conftest.err' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest.$ac_objext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? @@ -3688,12 +3855,11 @@ sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_header_stdc=no fi -rm -f conftest.$ac_objext conftest.$ac_ext +rm -f conftest.err conftest.$ac_objext conftest.$ac_ext if test $ac_cv_header_stdc = yes; then # SunOS 4.x string.h does not declare mem*, contrary to ANSI. cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -3715,7 +3881,6 @@ fi if test $ac_cv_header_stdc = yes; then # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI. cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -3740,7 +3905,6 @@ if test $ac_cv_header_stdc = yes; then : else cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -3752,9 +3916,9 @@ cat >>conftest.$ac_ext <<_ACEOF # define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c)) #else # define ISLOWER(c) \ - (('a' <= (c) && (c) <= 'i') \ - || ('j' <= (c) && (c) <= 'r') \ - || ('s' <= (c) && (c) <= 'z')) + (('a' <= (c) && (c) <= 'i') \ + || ('j' <= (c) && (c) <= 'r') \ + || ('s' <= (c) && (c) <= 'z')) # define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c)) #endif @@ -3765,7 +3929,7 @@ main () int i; for (i = 0; i < 256; i++) if (XOR (islower (i), ISLOWER (i)) - || toupper (i) != TOUPPER (i)) + || toupper (i) != TOUPPER (i)) exit(2); exit (0); } @@ -3790,7 +3954,7 @@ sed 's/^/| /' conftest.$ac_ext >&5 ( exit $ac_status ) ac_cv_header_stdc=no fi -rm -f core core.* *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext +rm -f core *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext fi fi fi @@ -3815,7 +3979,7 @@ fi for ac_header in sys/types.h sys/stat.h stdlib.h string.h memory.h strings.h \ - inttypes.h stdint.h unistd.h + inttypes.h stdint.h unistd.h do as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh` echo "$as_me:$LINENO: checking for $ac_header" >&5 @@ -3824,7 +3988,6 @@ if eval "test \"\${$as_ac_Header+set}\" = set"; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -3842,6 +4005,7 @@ if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5 (exit $ac_status); } >/dev/null; then if test -s conftest.err; then ac_cpp_err=$ac_c_preproc_warn_flag + ac_cpp_err=$ac_cpp_err$ac_c_werror_flag else ac_cpp_err= fi @@ -3875,7 +4039,6 @@ if test "${ac_cv_type_uintptr_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -3895,11 +4058,21 @@ if (sizeof (uintptr_t)) _ACEOF rm -f conftest.$ac_objext if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>&5 + (eval $ac_compile) 2>conftest.er1 ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && - { ac_try='test -s conftest.$ac_objext' + { ac_try='test -z "$ac_c_werror_flag" + || test ! -s conftest.err' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest.$ac_objext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? @@ -3912,7 +4085,7 @@ sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_type_uintptr_t=no fi -rm -f conftest.$ac_objext conftest.$ac_ext +rm -f conftest.err conftest.$ac_objext conftest.$ac_ext fi echo "$as_me:$LINENO: result: $ac_cv_type_uintptr_t" >&5 echo "${ECHO_T}$ac_cv_type_uintptr_t" >&6 @@ -3941,7 +4114,6 @@ if test "${ac_cv_type_pid_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -3961,11 +4133,21 @@ if (sizeof (pid_t)) _ACEOF rm -f conftest.$ac_objext if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>&5 + (eval $ac_compile) 2>conftest.er1 ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && - { ac_try='test -s conftest.$ac_objext' + { ac_try='test -z "$ac_c_werror_flag" + || test ! -s conftest.err' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest.$ac_objext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? @@ -3978,7 +4160,7 @@ sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_type_pid_t=no fi -rm -f conftest.$ac_objext conftest.$ac_ext +rm -f conftest.err conftest.$ac_objext conftest.$ac_ext fi echo "$as_me:$LINENO: result: $ac_cv_type_pid_t" >&5 echo "${ECHO_T}$ac_cv_type_pid_t" >&6 @@ -4139,7 +4321,6 @@ echo "$as_me: error: Link tests are not allowed after GCC_NO_EXECUTABLES." >&2;} { (exit 1); exit 1; }; } fi cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -4186,11 +4367,21 @@ return f != $ac_func; _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 - (eval $ac_link) 2>&5 + (eval $ac_link) 2>conftest.er1 ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && - { ac_try='test -s conftest$ac_exeext' + { ac_try='test -z "$ac_c_werror_flag" + || test ! -s conftest.err' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest$ac_exeext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? @@ -4203,7 +4394,8 @@ sed 's/^/| /' conftest.$ac_ext >&5 eval "$as_ac_var=no" fi -rm -f conftest.$ac_objext conftest$ac_exeext conftest.$ac_ext +rm -f conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext fi echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5 echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6 @@ -4250,12 +4442,54 @@ if test -n "${with_target_subdir}"; then # newlib provide and which ones we will be expected to provide. if test "x${with_newlib}" = "xyes"; then - LIBOBJS="$LIBOBJS asprintf.$ac_objext" - LIBOBJS="$LIBOBJS basename.$ac_objext" - LIBOBJS="$LIBOBJS insque.$ac_objext" - LIBOBJS="$LIBOBJS random.$ac_objext" - LIBOBJS="$LIBOBJS strdup.$ac_objext" - LIBOBJS="$LIBOBJS vasprintf.$ac_objext" + case $LIBOBJS in + "asprintf.$ac_objext" | \ + *" asprintf.$ac_objext" | \ + "asprintf.$ac_objext "* | \ + *" asprintf.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS asprintf.$ac_objext" ;; +esac + + case $LIBOBJS in + "basename.$ac_objext" | \ + *" basename.$ac_objext" | \ + "basename.$ac_objext "* | \ + *" basename.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS basename.$ac_objext" ;; +esac + + case $LIBOBJS in + "insque.$ac_objext" | \ + *" insque.$ac_objext" | \ + "insque.$ac_objext "* | \ + *" insque.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS insque.$ac_objext" ;; +esac + + case $LIBOBJS in + "random.$ac_objext" | \ + *" random.$ac_objext" | \ + "random.$ac_objext "* | \ + *" random.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS random.$ac_objext" ;; +esac + + case $LIBOBJS in + "strdup.$ac_objext" | \ + *" strdup.$ac_objext" | \ + "strdup.$ac_objext "* | \ + *" strdup.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS strdup.$ac_objext" ;; +esac + + case $LIBOBJS in + "vasprintf.$ac_objext" | \ + *" vasprintf.$ac_objext" | \ + "vasprintf.$ac_objext "* | \ + *" vasprintf.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS vasprintf.$ac_objext" ;; +esac + for f in $funcs; do case "$f" in @@ -4337,16 +4571,86 @@ if test -z "${setobjs}"; then # Handle VxWorks configuration specially, since on VxWorks the # libraries are actually on the target board, not in the file # system. - LIBOBJS="$LIBOBJS basename.$ac_objext" - LIBOBJS="$LIBOBJS getpagesize.$ac_objext" - LIBOBJS="$LIBOBJS insque.$ac_objext" - LIBOBJS="$LIBOBJS random.$ac_objext" - LIBOBJS="$LIBOBJS strcasecmp.$ac_objext" - LIBOBJS="$LIBOBJS strncasecmp.$ac_objext" - LIBOBJS="$LIBOBJS strdup.$ac_objext" - LIBOBJS="$LIBOBJS vfork.$ac_objext" - LIBOBJS="$LIBOBJS waitpid.$ac_objext" - LIBOBJS="$LIBOBJS vasprintf.$ac_objext" + case $LIBOBJS in + "basename.$ac_objext" | \ + *" basename.$ac_objext" | \ + "basename.$ac_objext "* | \ + *" basename.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS basename.$ac_objext" ;; +esac + + case $LIBOBJS in + "getpagesize.$ac_objext" | \ + *" getpagesize.$ac_objext" | \ + "getpagesize.$ac_objext "* | \ + *" getpagesize.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS getpagesize.$ac_objext" ;; +esac + + case $LIBOBJS in + "insque.$ac_objext" | \ + *" insque.$ac_objext" | \ + "insque.$ac_objext "* | \ + *" insque.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS insque.$ac_objext" ;; +esac + + case $LIBOBJS in + "random.$ac_objext" | \ + *" random.$ac_objext" | \ + "random.$ac_objext "* | \ + *" random.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS random.$ac_objext" ;; +esac + + case $LIBOBJS in + "strcasecmp.$ac_objext" | \ + *" strcasecmp.$ac_objext" | \ + "strcasecmp.$ac_objext "* | \ + *" strcasecmp.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS strcasecmp.$ac_objext" ;; +esac + + case $LIBOBJS in + "strncasecmp.$ac_objext" | \ + *" strncasecmp.$ac_objext" | \ + "strncasecmp.$ac_objext "* | \ + *" strncasecmp.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS strncasecmp.$ac_objext" ;; +esac + + case $LIBOBJS in + "strdup.$ac_objext" | \ + *" strdup.$ac_objext" | \ + "strdup.$ac_objext "* | \ + *" strdup.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS strdup.$ac_objext" ;; +esac + + case $LIBOBJS in + "vfork.$ac_objext" | \ + *" vfork.$ac_objext" | \ + "vfork.$ac_objext "* | \ + *" vfork.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS vfork.$ac_objext" ;; +esac + + case $LIBOBJS in + "waitpid.$ac_objext" | \ + *" waitpid.$ac_objext" | \ + "waitpid.$ac_objext "* | \ + *" waitpid.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS waitpid.$ac_objext" ;; +esac + + case $LIBOBJS in + "vasprintf.$ac_objext" | \ + *" vasprintf.$ac_objext" | \ + "vasprintf.$ac_objext "* | \ + *" vasprintf.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS vasprintf.$ac_objext" ;; +esac + for f in $funcs; do case "$f" in basename | getpagesize | insque | random | strcasecmp) @@ -4399,7 +4703,14 @@ if test -z "${setobjs}"; then if test -n "${with_target_subdir}" then funcs="`echo $funcs | sed -e 's/random//'`" - LIBOBJS="$LIBOBJS random.$ac_objext" + case $LIBOBJS in + "random.$ac_objext" | \ + *" random.$ac_objext" | \ + "random.$ac_objext "* | \ + *" random.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS random.$ac_objext" ;; +esac + vars="`echo $vars | sed -e 's/sys_siglist//'`" checkfuncs="`echo $checkfuncs | sed -e 's/strsignal//' -e 's/psignal//'`" fi @@ -4448,7 +4759,6 @@ echo "$as_me: error: Link tests are not allowed after GCC_NO_EXECUTABLES." >&2;} { (exit 1); exit 1; }; } fi cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -4472,11 +4782,21 @@ strerror (); _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 - (eval $ac_link) 2>&5 + (eval $ac_link) 2>conftest.er1 ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && - { ac_try='test -s conftest$ac_exeext' + { ac_try='test -z "$ac_c_werror_flag" + || test ! -s conftest.err' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest$ac_exeext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? @@ -4488,7 +4808,8 @@ else sed 's/^/| /' conftest.$ac_ext >&5 fi -rm -f conftest.$ac_objext conftest$ac_exeext conftest.$ac_ext +rm -f conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext if test "$ac_cv_search_strerror" = no; then for ac_lib in cposix; do LIBS="-l$ac_lib $ac_func_search_save_LIBS" @@ -4498,7 +4819,6 @@ echo "$as_me: error: Link tests are not allowed after GCC_NO_EXECUTABLES." >&2;} { (exit 1); exit 1; }; } fi cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -4522,11 +4842,21 @@ strerror (); _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 - (eval $ac_link) 2>&5 + (eval $ac_link) 2>conftest.er1 ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && - { ac_try='test -s conftest$ac_exeext' + { ac_try='test -z "$ac_c_werror_flag" + || test ! -s conftest.err' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest$ac_exeext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? @@ -4539,7 +4869,8 @@ else sed 's/^/| /' conftest.$ac_ext >&5 fi -rm -f conftest.$ac_objext conftest$ac_exeext conftest.$ac_ext +rm -f conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext done fi LIBS=$ac_func_search_save_LIBS @@ -4566,7 +4897,6 @@ echo "$as_me: error: Link tests are not allowed after GCC_NO_EXECUTABLES." >&2;} { (exit 1); exit 1; }; } fi cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -4613,11 +4943,21 @@ return f != $ac_func; _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 - (eval $ac_link) 2>&5 + (eval $ac_link) 2>conftest.er1 ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && - { ac_try='test -s conftest$ac_exeext' + { ac_try='test -z "$ac_c_werror_flag" + || test ! -s conftest.err' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest$ac_exeext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? @@ -4630,7 +4970,8 @@ sed 's/^/| /' conftest.$ac_ext >&5 eval "$as_ac_var=no" fi -rm -f conftest.$ac_objext conftest$ac_exeext conftest.$ac_ext +rm -f conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext fi echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5 echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6 @@ -4640,7 +4981,14 @@ if test `eval echo '${'$as_ac_var'}'` = yes; then _ACEOF else - LIBOBJS="$LIBOBJS $ac_func.$ac_objext" + case $LIBOBJS in + "$ac_func.$ac_objext" | \ + *" $ac_func.$ac_objext" | \ + "$ac_func.$ac_objext "* | \ + *" $ac_func.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS $ac_func.$ac_objext" ;; +esac + fi done @@ -4651,7 +4999,6 @@ if test "${ac_cv_os_cray+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -4689,7 +5036,6 @@ echo "$as_me: error: Link tests are not allowed after GCC_NO_EXECUTABLES." >&2;} { (exit 1); exit 1; }; } fi cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -4736,11 +5082,21 @@ return f != $ac_func; _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 - (eval $ac_link) 2>&5 + (eval $ac_link) 2>conftest.er1 ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && - { ac_try='test -s conftest$ac_exeext' + { ac_try='test -z "$ac_c_werror_flag" + || test ! -s conftest.err' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest$ac_exeext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? @@ -4753,7 +5109,8 @@ sed 's/^/| /' conftest.$ac_ext >&5 eval "$as_ac_var=no" fi -rm -f conftest.$ac_objext conftest$ac_exeext conftest.$ac_ext +rm -f conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext fi echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5 echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6 @@ -4777,7 +5134,6 @@ else ac_cv_c_stack_direction=0 else cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -4820,7 +5176,7 @@ sed 's/^/| /' conftest.$ac_ext >&5 ( exit $ac_status ) ac_cv_c_stack_direction=-1 fi -rm -f core core.* *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext +rm -f core *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext fi fi echo "$as_me:$LINENO: result: $ac_cv_c_stack_direction" >&5 @@ -4842,7 +5198,6 @@ if eval "test \"\${$as_ac_Header+set}\" = set"; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -4860,6 +5215,7 @@ if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5 (exit $ac_status); } >/dev/null; then if test -s conftest.err; then ac_cpp_err=$ac_c_preproc_warn_flag + ac_cpp_err=$ac_cpp_err$ac_c_werror_flag else ac_cpp_err= fi @@ -4902,7 +5258,6 @@ echo "$as_me: error: Link tests are not allowed after GCC_NO_EXECUTABLES." >&2;} { (exit 1); exit 1; }; } fi cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -4949,11 +5304,21 @@ return f != $ac_func; _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 - (eval $ac_link) 2>&5 + (eval $ac_link) 2>conftest.er1 ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && - { ac_try='test -s conftest$ac_exeext' + { ac_try='test -z "$ac_c_werror_flag" + || test ! -s conftest.err' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest$ac_exeext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? @@ -4966,7 +5331,8 @@ sed 's/^/| /' conftest.$ac_ext >&5 eval "$as_ac_var=no" fi -rm -f conftest.$ac_objext conftest$ac_exeext conftest.$ac_ext +rm -f conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext fi echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5 echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6 @@ -4996,9 +5362,9 @@ else /* Some systems only have a dummy stub for fork() */ int main () { - if (fork() < 0) - exit (1); - exit (0); + if (fork() < 0) + exit (1); + exit (0); } _ACEOF rm -f conftest$ac_exeext @@ -5021,7 +5387,7 @@ sed 's/^/| /' conftest.$ac_ext >&5 ( exit $ac_status ) ac_cv_func_fork_works=no fi -rm -f core core.* *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext +rm -f core *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext fi fi echo "$as_me:$LINENO: result: $ac_cv_func_fork_works" >&5 @@ -5054,7 +5420,6 @@ else ac_cv_func_vfork_works=cross else cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -5176,7 +5541,7 @@ sed 's/^/| /' conftest.$ac_ext >&5 ( exit $ac_status ) ac_cv_func_vfork_works=no fi -rm -f core core.* *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext +rm -f core *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext fi fi echo "$as_me:$LINENO: result: $ac_cv_func_vfork_works" >&5 @@ -5184,7 +5549,7 @@ echo "${ECHO_T}$ac_cv_func_vfork_works" >&6 fi; if test "x$ac_cv_func_fork_works" = xcross; then - ac_cv_func_vfork_works=ac_cv_func_vfork + ac_cv_func_vfork_works=$ac_cv_func_vfork { echo "$as_me:$LINENO: WARNING: result $ac_cv_func_vfork_works guessed because of cross compilation" >&5 echo "$as_me: WARNING: result $ac_cv_func_vfork_works guessed because of cross compilation" >&2;} fi @@ -5211,7 +5576,14 @@ _ACEOF fi if test $ac_cv_func_vfork_works = no; then - LIBOBJS="$LIBOBJS vfork.$ac_objext" + case $LIBOBJS in + "vfork.$ac_objext" | \ + *" vfork.$ac_objext" | \ + "vfork.$ac_objext "* | \ + *" vfork.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS vfork.$ac_objext" ;; +esac + fi # We only need _doprnt if we might use it to implement v*printf. if test $ac_cv_func_vprintf != yes \ @@ -5232,7 +5604,6 @@ echo "$as_me: error: Link tests are not allowed after GCC_NO_EXECUTABLES." >&2;} { (exit 1); exit 1; }; } fi cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -5279,11 +5650,21 @@ return f != $ac_func; _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 - (eval $ac_link) 2>&5 + (eval $ac_link) 2>conftest.er1 ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && - { ac_try='test -s conftest$ac_exeext' + { ac_try='test -z "$ac_c_werror_flag" + || test ! -s conftest.err' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest$ac_exeext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? @@ -5296,7 +5677,8 @@ sed 's/^/| /' conftest.$ac_ext >&5 eval "$as_ac_var=no" fi -rm -f conftest.$ac_objext conftest$ac_exeext conftest.$ac_ext +rm -f conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext fi echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5 echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6 @@ -5306,7 +5688,14 @@ if test `eval echo '${'$as_ac_var'}'` = yes; then _ACEOF else - LIBOBJS="$LIBOBJS $ac_func.$ac_objext" + case $LIBOBJS in + "$ac_func.$ac_objext" | \ + *" $ac_func.$ac_objext" | \ + "$ac_func.$ac_objext "* | \ + *" $ac_func.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS $ac_func.$ac_objext" ;; +esac + fi done @@ -5327,7 +5716,6 @@ echo "$as_me: error: Link tests are not allowed after GCC_NO_EXECUTABLES." >&2;} { (exit 1); exit 1; }; } fi cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -5374,11 +5762,21 @@ return f != $ac_func; _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 - (eval $ac_link) 2>&5 + (eval $ac_link) 2>conftest.er1 ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && - { ac_try='test -s conftest$ac_exeext' + { ac_try='test -z "$ac_c_werror_flag" + || test ! -s conftest.err' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest$ac_exeext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? @@ -5391,7 +5789,8 @@ sed 's/^/| /' conftest.$ac_ext >&5 eval "$as_ac_var=no" fi -rm -f conftest.$ac_objext conftest$ac_exeext conftest.$ac_ext +rm -f conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext fi echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5 echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6 @@ -5417,7 +5816,6 @@ echo "$as_me: error: Link tests are not allowed after GCC_NO_EXECUTABLES." >&2;} { (exit 1); exit 1; }; } fi cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -5434,11 +5832,21 @@ extern int $v []; p = $v; _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 - (eval $ac_link) 2>&5 + (eval $ac_link) 2>conftest.er1 ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && - { ac_try='test -s conftest$ac_exeext' + { ac_try='test -z "$ac_c_werror_flag" + || test ! -s conftest.err' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest$ac_exeext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? @@ -5451,7 +5859,8 @@ sed 's/^/| /' conftest.$ac_ext >&5 eval "libiberty_cv_var_$v=no" fi -rm -f conftest.$ac_objext conftest$ac_exeext conftest.$ac_ext +rm -f conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext fi if eval "test \"`echo '$libiberty_cv_var_'$v`\" = yes"; then @@ -5473,7 +5882,6 @@ echo "${ECHO_T}no" >&6 echo "$as_me:$LINENO: checking for external symbol _system_configuration" >&5 echo $ECHO_N "checking for external symbol _system_configuration... $ECHO_C" >&6 cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -5490,11 +5898,21 @@ double x = _system_configuration.physmem; _ACEOF rm -f conftest.$ac_objext if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>&5 + (eval $ac_compile) 2>conftest.er1 ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && - { ac_try='test -s conftest.$ac_objext' + { ac_try='test -z "$ac_c_werror_flag" + || test ! -s conftest.err' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest.$ac_objext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? @@ -5514,7 +5932,7 @@ sed 's/^/| /' conftest.$ac_ext >&5 echo "$as_me:$LINENO: result: no" >&5 echo "${ECHO_T}no" >&6 fi -rm -f conftest.$ac_objext conftest.$ac_ext +rm -f conftest.err conftest.$ac_objext conftest.$ac_ext for ac_func in $checkfuncs @@ -5531,7 +5949,6 @@ echo "$as_me: error: Link tests are not allowed after GCC_NO_EXECUTABLES." >&2;} { (exit 1); exit 1; }; } fi cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -5578,11 +5995,21 @@ return f != $ac_func; _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 - (eval $ac_link) 2>&5 + (eval $ac_link) 2>conftest.er1 ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && - { ac_try='test -s conftest$ac_exeext' + { ac_try='test -z "$ac_c_werror_flag" + || test ! -s conftest.err' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest$ac_exeext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? @@ -5595,7 +6022,8 @@ sed 's/^/| /' conftest.$ac_ext >&5 eval "$as_ac_var=no" fi -rm -f conftest.$ac_objext conftest$ac_exeext conftest.$ac_ext +rm -f conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext fi echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5 echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6 @@ -5613,7 +6041,6 @@ if test "${libiberty_cv_decl_needed_canonicalize_file_name+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -5645,11 +6072,21 @@ char *(*pfn) = (char *(*)) canonicalize_file_name _ACEOF rm -f conftest.$ac_objext if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5 - (eval $ac_compile) 2>&5 + (eval $ac_compile) 2>conftest.er1 ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && - { ac_try='test -s conftest.$ac_objext' + { ac_try='test -z "$ac_c_werror_flag" + || test ! -s conftest.err' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest.$ac_objext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? @@ -5662,7 +6099,7 @@ sed 's/^/| /' conftest.$ac_ext >&5 libiberty_cv_decl_needed_canonicalize_file_name=yes fi -rm -f conftest.$ac_objext conftest.$ac_ext +rm -f conftest.err conftest.$ac_objext conftest.$ac_ext fi echo "$as_me:$LINENO: result: $libiberty_cv_decl_needed_canonicalize_file_name" >&5 @@ -5704,7 +6141,6 @@ if eval "test \"\${$as_ac_Header+set}\" = set"; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -5722,6 +6158,7 @@ if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5 (exit $ac_status); } >/dev/null; then if test -s conftest.err; then ac_cpp_err=$ac_c_preproc_warn_flag + ac_cpp_err=$ac_cpp_err$ac_c_werror_flag else ac_cpp_err= fi @@ -5763,7 +6200,6 @@ echo "$as_me: error: Link tests are not allowed after GCC_NO_EXECUTABLES." >&2;} { (exit 1); exit 1; }; } fi cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -5810,11 +6246,21 @@ return f != $ac_func; _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5 - (eval $ac_link) 2>&5 + (eval $ac_link) 2>conftest.er1 ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && - { ac_try='test -s conftest$ac_exeext' + { ac_try='test -z "$ac_c_werror_flag" + || test ! -s conftest.err' + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 + (eval $ac_try) 2>&5 + ac_status=$? + echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; } && + { ac_try='test -s conftest$ac_exeext' { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5 (eval $ac_try) 2>&5 ac_status=$? @@ -5827,7 +6273,8 @@ sed 's/^/| /' conftest.$ac_ext >&5 eval "$as_ac_var=no" fi -rm -f conftest.$ac_objext conftest$ac_exeext conftest.$ac_ext +rm -f conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext fi echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5 echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6 @@ -5848,7 +6295,6 @@ else ac_cv_func_mmap_fixed_mapped=no else cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -5956,9 +6402,9 @@ main () data2 = (char *) malloc (2 * pagesize); if (!data2) exit (1); - data2 += (pagesize - ((int) data2 & (pagesize - 1))) & (pagesize - 1); + data2 += (pagesize - ((long) data2 & (pagesize - 1))) & (pagesize - 1); if (data2 != mmap (data2, pagesize, PROT_READ | PROT_WRITE, - MAP_PRIVATE | MAP_FIXED, fd, 0L)) + MAP_PRIVATE | MAP_FIXED, fd, 0L)) exit (1); for (i = 0; i < pagesize; ++i) if (*(data + i) != *(data2 + i)) @@ -6001,7 +6447,7 @@ sed 's/^/| /' conftest.$ac_ext >&5 ( exit $ac_status ) ac_cv_func_mmap_fixed_mapped=no fi -rm -f core core.* *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext +rm -f core *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext fi fi echo "$as_me:$LINENO: result: $ac_cv_func_mmap_fixed_mapped" >&5 @@ -6026,7 +6472,6 @@ else ac_cv_func_strncmp_works=no else cat >conftest.$ac_ext <<_ACEOF -#line $LINENO "configure" /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext @@ -6114,14 +6559,21 @@ sed 's/^/| /' conftest.$ac_ext >&5 ( exit $ac_status ) ac_cv_func_strncmp_works=no fi -rm -f core core.* *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext +rm -f core *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext fi rm -f core core.* *.core fi echo "$as_me:$LINENO: result: $ac_cv_func_strncmp_works" >&5 echo "${ECHO_T}$ac_cv_func_strncmp_works" >&6 if test $ac_cv_func_strncmp_works = no ; then - LIBOBJS="$LIBOBJS strncmp.$ac_objext" + case $LIBOBJS in + "strncmp.$ac_objext" | \ + *" strncmp.$ac_objext" | \ + "strncmp.$ac_objext "* | \ + *" strncmp.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS strncmp.$ac_objext" ;; +esac + fi @@ -6175,13 +6627,13 @@ _ACEOF # `set' does not quote correctly, so add quotes (double-quote # substitution turns \\\\ into \\, and sed turns \\ into \). sed -n \ - "s/'/'\\\\''/g; - s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p" + "s/'/'\\\\''/g; + s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p" ;; *) # `set' quotes correctly as required by POSIX, so do not add quotes. sed -n \ - "s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1=\\2/p" + "s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1=\\2/p" ;; esac; } | @@ -6211,13 +6663,13 @@ test "x$exec_prefix" = xNONE && exec_prefix='${prefix}' # trailing colons and then remove the whole line if VPATH becomes empty # (actually we leave an empty line to preserve line numbers). if test "x$srcdir" = x.; then - ac_vpsub='/^[ ]*VPATH[ ]*=/{ + ac_vpsub='/^[ ]*VPATH[ ]*=/{ s/:*\$(srcdir):*/:/; s/:*\${srcdir}:*/:/; s/:*@srcdir@:*/:/; -s/^\([^=]*=[ ]*\):*/\1/; +s/^\([^=]*=[ ]*\):*/\1/; s/:*$//; -s/^[^=]*=[ ]*$//; +s/^[^=]*=[ ]*$//; }' fi @@ -6228,7 +6680,7 @@ ac_ltlibobjs= for ac_i in : $LIBOBJS; do test "x$ac_i" = x: && continue # 1. Remove the extension, and $U if already installed. ac_i=`echo "$ac_i" | - sed 's/\$U\././;s/\.o$//;s/\.obj$//'` + sed 's/\$U\././;s/\.o$//;s/\.obj$//'` # 2. Add them. ac_libobjs="$ac_libobjs $ac_i\$U.$ac_objext" ac_ltlibobjs="$ac_ltlibobjs $ac_i"'$U.lo' @@ -6272,9 +6724,10 @@ if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then elif test -n "${BASH_VERSION+set}" && (set -o posix) >/dev/null 2>&1; then set -o posix fi +DUALCASE=1; export DUALCASE # for MKS sh # Support unset when possible. -if (FOO=FOO; unset FOO) >/dev/null 2>&1; then +if ( (MAIL=60; unset MAIL) || exit) >/dev/null 2>&1; then as_unset=unset else as_unset=false @@ -6293,7 +6746,7 @@ for as_var in \ LC_MEASUREMENT LC_MESSAGES LC_MONETARY LC_NAME LC_NUMERIC LC_PAPER \ LC_TELEPHONE LC_TIME do - if (set +x; test -n "`(eval $as_var=C; export $as_var) 2>&1`"); then + if (set +x; test -z "`(eval $as_var=C; export $as_var) 2>&1`"); then eval $as_var=C; export $as_var else $as_unset $as_var @@ -6472,16 +6925,17 @@ rm -f conf$$ conf$$.exe conf$$.file if mkdir -p . 2>/dev/null; then as_mkdir_p=: else + test -d ./-p && rmdir ./-p as_mkdir_p=false fi as_executable_p="test -f" # Sed expression to map a string onto a valid CPP name. -as_tr_cpp="sed y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g" +as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'" # Sed expression to map a string onto a valid variable name. -as_tr_sh="sed y%*+%pp%;s%[^_$as_cr_alnum]%_%g" +as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'" # IFS @@ -6508,7 +6962,7 @@ _ASBOX cat >&5 <<_CSEOF This file was extended by $as_me, which was -generated by GNU Autoconf 2.57. Invocation command line was +generated by GNU Autoconf 2.58. Invocation command line was CONFIG_FILES = $CONFIG_FILES CONFIG_HEADERS = $CONFIG_HEADERS @@ -6552,9 +7006,9 @@ Usage: $0 [OPTIONS] [FILE]... -d, --debug don't remove temporary files --recheck update $as_me by reconfiguring in the same conditions --file=FILE[:TEMPLATE] - instantiate the configuration file FILE + instantiate the configuration file FILE --header=FILE[:TEMPLATE] - instantiate the configuration header FILE + instantiate the configuration header FILE Configuration files: $config_files @@ -6571,11 +7025,10 @@ _ACEOF cat >>$CONFIG_STATUS <<_ACEOF ac_cs_version="\\ config.status -configured by $0, generated by GNU Autoconf 2.57, +configured by $0, generated by GNU Autoconf 2.58, with options \\"`echo "$ac_configure_args" | sed 's/[\\""\`\$]/\\\\&/g'`\\" -Copyright 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001 -Free Software Foundation, Inc. +Copyright (C) 2003 Free Software Foundation, Inc. This config.status script is free software; the Free Software Foundation gives unlimited permission to copy, distribute and modify it." srcdir=$srcdir @@ -6851,9 +7304,9 @@ _ACEOF (echo ':t /@[a-zA-Z_][a-zA-Z_0-9]*@/!b' && cat $tmp/subs.frag) >$tmp/subs-$ac_sed_frag.sed if test -z "$ac_sed_cmds"; then - ac_sed_cmds="sed -f $tmp/subs-$ac_sed_frag.sed" + ac_sed_cmds="sed -f $tmp/subs-$ac_sed_frag.sed" else - ac_sed_cmds="$ac_sed_cmds | sed -f $tmp/subs-$ac_sed_frag.sed" + ac_sed_cmds="$ac_sed_cmds | sed -f $tmp/subs-$ac_sed_frag.sed" fi ac_sed_frag=`expr $ac_sed_frag + 1` ac_beg=$ac_end @@ -6871,21 +7324,21 @@ for ac_file in : $CONFIG_FILES; do test "x$ac_file" = x: && continue # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in". case $ac_file in - | *:- | *:-:* ) # input from stdin - cat >$tmp/stdin - ac_file_in=`echo "$ac_file" | sed 's,[^:]*:,,'` - ac_file=`echo "$ac_file" | sed 's,:.*,,'` ;; + cat >$tmp/stdin + ac_file_in=`echo "$ac_file" | sed 's,[^:]*:,,'` + ac_file=`echo "$ac_file" | sed 's,:.*,,'` ;; *:* ) ac_file_in=`echo "$ac_file" | sed 's,[^:]*:,,'` - ac_file=`echo "$ac_file" | sed 's,:.*,,'` ;; + ac_file=`echo "$ac_file" | sed 's,:.*,,'` ;; * ) ac_file_in=$ac_file.in ;; esac # Compute @srcdir@, @top_srcdir@, and @INSTALL@ for subdirectories. ac_dir=`(dirname "$ac_file") 2>/dev/null || $as_expr X"$ac_file" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ - X"$ac_file" : 'X\(//\)[^/]' \| \ - X"$ac_file" : 'X\(//\)$' \| \ - X"$ac_file" : 'X\(/\)' \| \ - . : '\(.\)' 2>/dev/null || + X"$ac_file" : 'X\(//\)[^/]' \| \ + X"$ac_file" : 'X\(//\)$' \| \ + X"$ac_file" : 'X\(/\)' \| \ + . : '\(.\)' 2>/dev/null || echo X"$ac_file" | sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; } /^X\(\/\/\)[^/].*/{ s//\1/; q; } @@ -6901,10 +7354,10 @@ echo X"$ac_file" | as_dirs="$as_dir $as_dirs" as_dir=`(dirname "$as_dir") 2>/dev/null || $as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ - X"$as_dir" : 'X\(//\)[^/]' \| \ - X"$as_dir" : 'X\(//\)$' \| \ - X"$as_dir" : 'X\(/\)' \| \ - . : '\(.\)' 2>/dev/null || + X"$as_dir" : 'X\(//\)[^/]' \| \ + X"$as_dir" : 'X\(//\)$' \| \ + X"$as_dir" : 'X\(/\)' \| \ + . : '\(.\)' 2>/dev/null || echo X"$as_dir" | sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; } /^X\(\/\/\)[^/].*/{ s//\1/; q; } @@ -6942,12 +7395,42 @@ case $srcdir in ac_srcdir=$ac_top_builddir$srcdir$ac_dir_suffix ac_top_srcdir=$ac_top_builddir$srcdir ;; esac -# Don't blindly perform a `cd "$ac_dir"/$ac_foo && pwd` since $ac_foo can be -# absolute. -ac_abs_builddir=`cd "$ac_dir" && cd $ac_builddir && pwd` -ac_abs_top_builddir=`cd "$ac_dir" && cd ${ac_top_builddir}. && pwd` -ac_abs_srcdir=`cd "$ac_dir" && cd $ac_srcdir && pwd` -ac_abs_top_srcdir=`cd "$ac_dir" && cd $ac_top_srcdir && pwd` +case "$ac_dir" in +.) ac_abs_builddir=$ac_builddir;; +*) + case $ac_builddir in + .) ac_abs_builddir="$ac_dir";; + [\\/]* | ?:[\\/]* ) ac_abs_builddir=$ac_builddir;; + *) ac_abs_builddir="$ac_dir"/$ac_builddir;; + esac;; +esac +case "$ac_dir" in +.) ac_abs_top_builddir=${ac_top_builddir}.;; +*) + case ${ac_top_builddir}. in + .) ac_abs_top_builddir="$ac_dir";; + [\\/]* | ?:[\\/]* ) ac_abs_top_builddir=${ac_top_builddir}.;; + *) ac_abs_top_builddir="$ac_dir"/${ac_top_builddir}.;; + esac;; +esac +case "$ac_dir" in +.) ac_abs_srcdir=$ac_srcdir;; +*) + case $ac_srcdir in + .) ac_abs_srcdir="$ac_dir";; + [\\/]* | ?:[\\/]* ) ac_abs_srcdir=$ac_srcdir;; + *) ac_abs_srcdir="$ac_dir"/$ac_srcdir;; + esac;; +esac +case "$ac_dir" in +.) ac_abs_top_srcdir=$ac_top_srcdir;; +*) + case $ac_top_srcdir in + .) ac_abs_top_srcdir="$ac_dir";; + [\\/]* | ?:[\\/]* ) ac_abs_top_srcdir=$ac_top_srcdir;; + *) ac_abs_top_srcdir="$ac_dir"/$ac_top_srcdir;; + esac;; +esac case $INSTALL in @@ -6969,7 +7452,7 @@ echo "$as_me: creating $ac_file" >&6;} configure_input="$ac_file. " fi configure_input=$configure_input"Generated from `echo $ac_file_in | - sed 's,.*/,,'` by configure." + sed 's,.*/,,'` by configure." # First look for the input files in the build tree, otherwise in the # src tree. @@ -6978,24 +7461,24 @@ echo "$as_me: creating $ac_file" >&6;} case $f in -) echo $tmp/stdin ;; [\\/$]*) - # Absolute (can't be DOS-style, as IFS=:) - test -f "$f" || { { echo "$as_me:$LINENO: error: cannot find input file: $f" >&5 + # Absolute (can't be DOS-style, as IFS=:) + test -f "$f" || { { echo "$as_me:$LINENO: error: cannot find input file: $f" >&5 echo "$as_me: error: cannot find input file: $f" >&2;} { (exit 1); exit 1; }; } - echo $f;; + echo "$f";; *) # Relative - if test -f "$f"; then - # Build tree - echo $f - elif test -f "$srcdir/$f"; then - # Source tree - echo $srcdir/$f - else - # /dev/null tree - { { echo "$as_me:$LINENO: error: cannot find input file: $f" >&5 + if test -f "$f"; then + # Build tree + echo "$f" + elif test -f "$srcdir/$f"; then + # Source tree + echo "$srcdir/$f" + else + # /dev/null tree + { { echo "$as_me:$LINENO: error: cannot find input file: $f" >&5 echo "$as_me: error: cannot find input file: $f" >&2;} { (exit 1); exit 1; }; } - fi;; + fi;; esac done` || { (exit 1); exit 1; } _ACEOF @@ -7037,12 +7520,12 @@ cat >>$CONFIG_STATUS <<\_ACEOF # NAME is the cpp macro being defined and VALUE is the value it is being given. # # ac_d sets the value in "#define NAME VALUE" lines. -ac_dA='s,^\([ ]*\)#\([ ]*define[ ][ ]*\)' -ac_dB='[ ].*$,\1#\2' +ac_dA='s,^\([ ]*\)#\([ ]*define[ ][ ]*\)' +ac_dB='[ ].*$,\1#\2' ac_dC=' ' ac_dD=',;t' # ac_u turns "#undef NAME" without trailing blanks into "#define NAME VALUE". -ac_uA='s,^\([ ]*\)#\([ ]*\)undef\([ ][ ]*\)' +ac_uA='s,^\([ ]*\)#\([ ]*\)undef\([ ][ ]*\)' ac_uB='$,\1#\2define\3' ac_uC=' ' ac_uD=',;t' @@ -7051,11 +7534,11 @@ for ac_file in : $CONFIG_HEADERS; do test "x$ac_file" = x: && continue # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in". case $ac_file in - | *:- | *:-:* ) # input from stdin - cat >$tmp/stdin - ac_file_in=`echo "$ac_file" | sed 's,[^:]*:,,'` - ac_file=`echo "$ac_file" | sed 's,:.*,,'` ;; + cat >$tmp/stdin + ac_file_in=`echo "$ac_file" | sed 's,[^:]*:,,'` + ac_file=`echo "$ac_file" | sed 's,:.*,,'` ;; *:* ) ac_file_in=`echo "$ac_file" | sed 's,[^:]*:,,'` - ac_file=`echo "$ac_file" | sed 's,:.*,,'` ;; + ac_file=`echo "$ac_file" | sed 's,:.*,,'` ;; * ) ac_file_in=$ac_file.in ;; esac @@ -7069,28 +7552,29 @@ echo "$as_me: creating $ac_file" >&6;} case $f in -) echo $tmp/stdin ;; [\\/$]*) - # Absolute (can't be DOS-style, as IFS=:) - test -f "$f" || { { echo "$as_me:$LINENO: error: cannot find input file: $f" >&5 + # Absolute (can't be DOS-style, as IFS=:) + test -f "$f" || { { echo "$as_me:$LINENO: error: cannot find input file: $f" >&5 echo "$as_me: error: cannot find input file: $f" >&2;} { (exit 1); exit 1; }; } - echo $f;; + # Do quote $f, to prevent DOS paths from being IFS'd. + echo "$f";; *) # Relative - if test -f "$f"; then - # Build tree - echo $f - elif test -f "$srcdir/$f"; then - # Source tree - echo $srcdir/$f - else - # /dev/null tree - { { echo "$as_me:$LINENO: error: cannot find input file: $f" >&5 + if test -f "$f"; then + # Build tree + echo "$f" + elif test -f "$srcdir/$f"; then + # Source tree + echo "$srcdir/$f" + else + # /dev/null tree + { { echo "$as_me:$LINENO: error: cannot find input file: $f" >&5 echo "$as_me: error: cannot find input file: $f" >&2;} { (exit 1); exit 1; }; } - fi;; + fi;; esac done` || { (exit 1); exit 1; } # Remove the trailing spaces. - sed 's/[ ]*$//' $ac_file_inputs >$tmp/in + sed 's/[ ]*$//' $ac_file_inputs >$tmp/in _ACEOF @@ -7113,9 +7597,9 @@ s/[\\&,]/\\&/g s,[\\$`],\\&,g t clear : clear -s,^[ ]*#[ ]*define[ ][ ]*\([^ (][^ (]*\)\(([^)]*)\)[ ]*\(.*\)$,${ac_dA}\1${ac_dB}\1\2${ac_dC}\3${ac_dD},gp +s,^[ ]*#[ ]*define[ ][ ]*\([^ (][^ (]*\)\(([^)]*)\)[ ]*\(.*\)$,${ac_dA}\1${ac_dB}\1\2${ac_dC}\3${ac_dD},gp t end -s,^[ ]*#[ ]*define[ ][ ]*\([^ ][^ ]*\)[ ]*\(.*\)$,${ac_dA}\1${ac_dB}\1${ac_dC}\2${ac_dD},gp +s,^[ ]*#[ ]*define[ ][ ]*\([^ ][^ ]*\)[ ]*\(.*\)$,${ac_dA}\1${ac_dB}\1${ac_dC}\2${ac_dD},gp : end _ACEOF # If some macros were called several times there might be several times @@ -7129,13 +7613,13 @@ rm -f confdef2sed.sed # example, in the case of _POSIX_SOURCE, which is predefined and required # on some systems where configure will not decide to define it. cat >>conftest.undefs <<\_ACEOF -s,^[ ]*#[ ]*undef[ ][ ]*[a-zA-Z_][a-zA-Z_0-9]*,/* & */, +s,^[ ]*#[ ]*undef[ ][ ]*[a-zA-Z_][a-zA-Z_0-9]*,/* & */, _ACEOF # Break up conftest.defines because some shells have a limit on the size # of here documents, and old seds have small limits too (100 cmds). echo ' # Handle all the #define templates only if necessary.' >>$CONFIG_STATUS -echo ' if grep "^[ ]*#[ ]*define" $tmp/in >/dev/null; then' >>$CONFIG_STATUS +echo ' if grep "^[ ]*#[ ]*define" $tmp/in >/dev/null; then' >>$CONFIG_STATUS echo ' # If there are no defines, we may have an empty if/fi' >>$CONFIG_STATUS echo ' :' >>$CONFIG_STATUS rm -f conftest.tail @@ -7144,7 +7628,7 @@ do # Write a limited-size here document to $tmp/defines.sed. echo ' cat >$tmp/defines.sed <>$CONFIG_STATUS # Speed up: don't consider the non `#define' lines. - echo '/^[ ]*#[ ]*define/!b' >>$CONFIG_STATUS + echo '/^[ ]*#[ ]*define/!b' >>$CONFIG_STATUS # Work around the forget-to-reset-the-flag bug. echo 't clr' >>$CONFIG_STATUS echo ': clr' >>$CONFIG_STATUS @@ -7171,7 +7655,7 @@ do # Write a limited-size here document to $tmp/undefs.sed. echo ' cat >$tmp/undefs.sed <>$CONFIG_STATUS # Speed up: don't consider the non `#undef' - echo '/^[ ]*#[ ]*undef/!b' >>$CONFIG_STATUS + echo '/^[ ]*#[ ]*undef/!b' >>$CONFIG_STATUS # Work around the forget-to-reset-the-flag bug. echo 't clr' >>$CONFIG_STATUS echo ': clr' >>$CONFIG_STATUS @@ -7205,10 +7689,10 @@ echo "$as_me: $ac_file is unchanged" >&6;} else ac_dir=`(dirname "$ac_file") 2>/dev/null || $as_expr X"$ac_file" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ - X"$ac_file" : 'X\(//\)[^/]' \| \ - X"$ac_file" : 'X\(//\)$' \| \ - X"$ac_file" : 'X\(/\)' \| \ - . : '\(.\)' 2>/dev/null || + X"$ac_file" : 'X\(//\)[^/]' \| \ + X"$ac_file" : 'X\(//\)$' \| \ + X"$ac_file" : 'X\(/\)' \| \ + . : '\(.\)' 2>/dev/null || echo X"$ac_file" | sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; } /^X\(\/\/\)[^/].*/{ s//\1/; q; } @@ -7224,10 +7708,10 @@ echo X"$ac_file" | as_dirs="$as_dir $as_dirs" as_dir=`(dirname "$as_dir") 2>/dev/null || $as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ - X"$as_dir" : 'X\(//\)[^/]' \| \ - X"$as_dir" : 'X\(//\)$' \| \ - X"$as_dir" : 'X\(/\)' \| \ - . : '\(.\)' 2>/dev/null || + X"$as_dir" : 'X\(//\)[^/]' \| \ + X"$as_dir" : 'X\(//\)$' \| \ + X"$as_dir" : 'X\(/\)' \| \ + . : '\(.\)' 2>/dev/null || echo X"$as_dir" | sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; } /^X\(\/\/\)[^/].*/{ s//\1/; q; } @@ -7259,16 +7743,41 @@ for ac_file in : $CONFIG_COMMANDS; do test "x$ac_file" = x: && continue ac_source=`echo "$ac_file" | sed 's,[^:]*:,,'` ac_dir=`(dirname "$ac_dest") 2>/dev/null || $as_expr X"$ac_dest" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ - X"$ac_dest" : 'X\(//\)[^/]' \| \ - X"$ac_dest" : 'X\(//\)$' \| \ - X"$ac_dest" : 'X\(/\)' \| \ - . : '\(.\)' 2>/dev/null || + X"$ac_dest" : 'X\(//\)[^/]' \| \ + X"$ac_dest" : 'X\(//\)$' \| \ + X"$ac_dest" : 'X\(/\)' \| \ + . : '\(.\)' 2>/dev/null || echo X"$ac_dest" | sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; } /^X\(\/\/\)[^/].*/{ s//\1/; q; } /^X\(\/\/\)$/{ s//\1/; q; } /^X\(\/\).*/{ s//\1/; q; } s/.*/./; q'` + { if $as_mkdir_p; then + mkdir -p "$ac_dir" + else + as_dir="$ac_dir" + as_dirs= + while test ! -d "$as_dir"; do + as_dirs="$as_dir $as_dirs" + as_dir=`(dirname "$as_dir") 2>/dev/null || +$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ + X"$as_dir" : 'X\(//\)[^/]' \| \ + X"$as_dir" : 'X\(//\)$' \| \ + X"$as_dir" : 'X\(/\)' \| \ + . : '\(.\)' 2>/dev/null || +echo X"$as_dir" | + sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; } + /^X\(\/\/\)[^/].*/{ s//\1/; q; } + /^X\(\/\/\)$/{ s//\1/; q; } + /^X\(\/\).*/{ s//\1/; q; } + s/.*/./; q'` + done + test ! -n "$as_dirs" || mkdir $as_dirs + fi || { { echo "$as_me:$LINENO: error: cannot create directory \"$ac_dir\"" >&5 +echo "$as_me: error: cannot create directory \"$ac_dir\"" >&2;} + { (exit 1); exit 1; }; }; } + ac_builddir=. if test "$ac_dir" != .; then @@ -7294,12 +7803,42 @@ case $srcdir in ac_srcdir=$ac_top_builddir$srcdir$ac_dir_suffix ac_top_srcdir=$ac_top_builddir$srcdir ;; esac -# Don't blindly perform a `cd "$ac_dir"/$ac_foo && pwd` since $ac_foo can be -# absolute. -ac_abs_builddir=`cd "$ac_dir" && cd $ac_builddir && pwd` -ac_abs_top_builddir=`cd "$ac_dir" && cd ${ac_top_builddir}. && pwd` -ac_abs_srcdir=`cd "$ac_dir" && cd $ac_srcdir && pwd` -ac_abs_top_srcdir=`cd "$ac_dir" && cd $ac_top_srcdir && pwd` +case "$ac_dir" in +.) ac_abs_builddir=$ac_builddir;; +*) + case $ac_builddir in + .) ac_abs_builddir="$ac_dir";; + [\\/]* | ?:[\\/]* ) ac_abs_builddir=$ac_builddir;; + *) ac_abs_builddir="$ac_dir"/$ac_builddir;; + esac;; +esac +case "$ac_dir" in +.) ac_abs_top_builddir=${ac_top_builddir}.;; +*) + case ${ac_top_builddir}. in + .) ac_abs_top_builddir="$ac_dir";; + [\\/]* | ?:[\\/]* ) ac_abs_top_builddir=${ac_top_builddir}.;; + *) ac_abs_top_builddir="$ac_dir"/${ac_top_builddir}.;; + esac;; +esac +case "$ac_dir" in +.) ac_abs_srcdir=$ac_srcdir;; +*) + case $ac_srcdir in + .) ac_abs_srcdir="$ac_dir";; + [\\/]* | ?:[\\/]* ) ac_abs_srcdir=$ac_srcdir;; + *) ac_abs_srcdir="$ac_dir"/$ac_srcdir;; + esac;; +esac +case "$ac_dir" in +.) ac_abs_top_srcdir=$ac_top_srcdir;; +*) + case $ac_top_srcdir in + .) ac_abs_top_srcdir="$ac_dir";; + [\\/]* | ?:[\\/]* ) ac_abs_top_srcdir=$ac_top_srcdir;; + *) ac_abs_top_srcdir="$ac_dir"/$ac_top_srcdir;; + esac;; +esac { echo "$as_me:$LINENO: executing $ac_dest commands" >&5 diff --git a/libiberty/testsuite/test-demangle.c b/libiberty/testsuite/test-demangle.c index 6e00d1416d7..4d515fab534 100644 --- a/libiberty/testsuite/test-demangle.c +++ b/libiberty/testsuite/test-demangle.c @@ -26,6 +26,12 @@ #include #include "libiberty.h" #include "demangle.h" +#ifdef HAVE_STRING_H +#include +#endif +#if HAVE_STDLIB_H +# include +#endif struct line { @@ -119,7 +125,7 @@ main(argc, argv) int argc; char **argv; { - enum demangling_styles style; + enum demangling_styles style = auto_demangling; int no_params; int is_v3_ctor; int is_v3_dtor; diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 783165bee73..47790f36b7f 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,32 @@ +2004-03-08 Nick Clifton + + * po/de.po: Updated German translation. + +2003-03-03 Andrew Stubbs + + * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in + nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu. + * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions + accordingly. + +2004-03-01 Richard Sandiford + + * frv-asm.c: Regenerate. + * frv-desc.c: Regenerate. + * frv-desc.h: Regenerate. + * frv-dis.c: Regenerate. + * frv-ibld.c: Regenerate. + * frv-opc.c: Regenerate. + * frv-opc.h: Regenerate. + +2004-03-01 Richard Sandiford + + * frv-desc.c, frv-opc.c: Regenerate. + +2004-03-01 Richard Sandiford + + * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate. + 2004-02-26 Andrew Stubbs * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4. diff --git a/opcodes/frv-asm.c b/opcodes/frv-asm.c index 145b56a2a79..98df36bf458 100644 --- a/opcodes/frv-asm.c +++ b/opcodes/frv-asm.c @@ -860,6 +860,21 @@ frv_cgen_parse_operand (cd, opindex, strp, fields) case FRV_OPERAND_LI : errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_LI, &fields->f_LI); break; + case FRV_OPERAND_LRAD : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_LRAD, &fields->f_LRAD); + break; + case FRV_OPERAND_LRAE : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_LRAE, &fields->f_LRAE); + break; + case FRV_OPERAND_LRAS : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_LRAS, &fields->f_LRAS); + break; + case FRV_OPERAND_TLBPRL : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_TLBPRL, &fields->f_TLBPRL); + break; + case FRV_OPERAND_TLBPROPX : + errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_TLBPROPX, &fields->f_TLBPRopx); + break; case FRV_OPERAND_AE : errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_AE, &fields->f_ae); break; diff --git a/opcodes/frv-desc.c b/opcodes/frv-desc.c index 35659c7b420..7e0b3b424a8 100644 --- a/opcodes/frv-desc.c +++ b/opcodes/frv-desc.c @@ -49,6 +49,7 @@ static const CGEN_ATTR_ENTRY MACH_attr[] = { "frv", MACH_FRV }, { "fr550", MACH_FR550 }, { "fr500", MACH_FR500 }, + { "fr450", MACH_FR450 }, { "fr400", MACH_FR400 }, { "tomcat", MACH_TOMCAT }, { "simple", MACH_SIMPLE }, @@ -90,6 +91,7 @@ static const CGEN_ATTR_ENTRY UNIT_attr[] = { "SCAN", UNIT_SCAN }, { "DCPL", UNIT_DCPL }, { "MDUALACC", UNIT_MDUALACC }, + { "MDCUTSSI", UNIT_MDCUTSSI }, { "MCLRACC_1", UNIT_MCLRACC_1 }, { "NUM_UNITS", UNIT_NUM_UNITS }, { 0, 0 } @@ -116,6 +118,31 @@ static const CGEN_ATTR_ENTRY FR400_MAJOR_attr[] = { 0, 0 } }; +static const CGEN_ATTR_ENTRY FR450_MAJOR_attr[] = +{ + { "NONE", FR450_MAJOR_NONE }, + { "I_1", FR450_MAJOR_I_1 }, + { "I_2", FR450_MAJOR_I_2 }, + { "I_3", FR450_MAJOR_I_3 }, + { "I_4", FR450_MAJOR_I_4 }, + { "I_5", FR450_MAJOR_I_5 }, + { "B_1", FR450_MAJOR_B_1 }, + { "B_2", FR450_MAJOR_B_2 }, + { "B_3", FR450_MAJOR_B_3 }, + { "B_4", FR450_MAJOR_B_4 }, + { "B_5", FR450_MAJOR_B_5 }, + { "B_6", FR450_MAJOR_B_6 }, + { "C_1", FR450_MAJOR_C_1 }, + { "C_2", FR450_MAJOR_C_2 }, + { "M_1", FR450_MAJOR_M_1 }, + { "M_2", FR450_MAJOR_M_2 }, + { "M_3", FR450_MAJOR_M_3 }, + { "M_4", FR450_MAJOR_M_4 }, + { "M_5", FR450_MAJOR_M_5 }, + { "M_6", FR450_MAJOR_M_6 }, + { 0, 0 } +}; + static const CGEN_ATTR_ENTRY FR500_MAJOR_attr[] = { { "NONE", FR500_MAJOR_NONE }, @@ -225,6 +252,7 @@ const CGEN_ATTR_TABLE frv_cgen_insn_attr_table[] = { "MACH", & MACH_attr[0], & MACH_attr[0] }, { "UNIT", & UNIT_attr[0], & UNIT_attr[0] }, { "FR400-MAJOR", & FR400_MAJOR_attr[0], & FR400_MAJOR_attr[0] }, + { "FR450-MAJOR", & FR450_MAJOR_attr[0], & FR450_MAJOR_attr[0] }, { "FR500-MAJOR", & FR500_MAJOR_attr[0], & FR500_MAJOR_attr[0] }, { "FR550-MAJOR", & FR550_MAJOR_attr[0], & FR550_MAJOR_attr[0] }, { "ALIAS", &bool_attr[0], &bool_attr[0] }, @@ -242,6 +270,7 @@ const CGEN_ATTR_TABLE frv_cgen_insn_attr_table[] = { "CONDITIONAL", &bool_attr[0], &bool_attr[0] }, { "FR-ACCESS", &bool_attr[0], &bool_attr[0] }, { "PRESERVE-OVF", &bool_attr[0], &bool_attr[0] }, + { "AUDIO", &bool_attr[0], &bool_attr[0] }, { 0, 0, 0 } }; @@ -260,6 +289,7 @@ static const CGEN_MACH frv_cgen_mach_table[] = { { "fr500", "fr500", MACH_FR500, 0 }, { "tomcat", "tomcat", MACH_TOMCAT, 0 }, { "fr400", "fr400", MACH_FR400, 0 }, + { "fr450", "fr450", MACH_FR450, 0 }, { "simple", "simple", MACH_SIMPLE, 0 }, { 0, 0, 0, 0 } }; @@ -804,6 +834,10 @@ static CGEN_KEYWORD_ENTRY frv_cgen_opval_spr_names_entries[] = { "sr1", 769, {0, {0}}, 0, 0 }, { "sr2", 770, {0, {0}}, 0, 0 }, { "sr3", 771, {0, {0}}, 0, 0 }, + { "scr0", 832, {0, {0}}, 0, 0 }, + { "scr1", 833, {0, {0}}, 0, 0 }, + { "scr2", 834, {0, {0}}, 0, 0 }, + { "scr3", 835, {0, {0}}, 0, 0 }, { "fsr0", 1024, {0, {0}}, 0, 0 }, { "fsr1", 1025, {0, {0}}, 0, 0 }, { "fsr2", 1026, {0, {0}}, 0, 0 }, @@ -1449,9 +1483,20 @@ static CGEN_KEYWORD_ENTRY frv_cgen_opval_spr_names_entries[] = { "amcr", 1920, {0, {0}}, 0, 0 }, { "stbar", 1921, {0, {0}}, 0, 0 }, { "mmcr", 1922, {0, {0}}, 0, 0 }, + { "iamvr1", 1925, {0, {0}}, 0, 0 }, + { "damvr1", 1927, {0, {0}}, 0, 0 }, + { "cxnr", 1936, {0, {0}}, 0, 0 }, + { "ttbr", 1937, {0, {0}}, 0, 0 }, + { "tplr", 1938, {0, {0}}, 0, 0 }, + { "tppr", 1939, {0, {0}}, 0, 0 }, + { "tpxr", 1940, {0, {0}}, 0, 0 }, + { "timerh", 1952, {0, {0}}, 0, 0 }, + { "timerl", 1953, {0, {0}}, 0, 0 }, + { "timerd", 1954, {0, {0}}, 0, 0 }, { "dcr", 2048, {0, {0}}, 0, 0 }, { "brr", 2049, {0, {0}}, 0, 0 }, { "nmar", 2050, {0, {0}}, 0, 0 }, + { "btbr", 2051, {0, {0}}, 0, 0 }, { "ibar0", 2052, {0, {0}}, 0, 0 }, { "ibar1", 2053, {0, {0}}, 0, 0 }, { "ibar2", 2054, {0, {0}}, 0, 0 }, @@ -1505,7 +1550,7 @@ static CGEN_KEYWORD_ENTRY frv_cgen_opval_spr_names_entries[] = CGEN_KEYWORD frv_cgen_opval_spr_names = { & frv_cgen_opval_spr_names_entries[0], - 1007, + 1022, 0, 0, 0, 0, "" }; @@ -1817,7 +1862,7 @@ const CGEN_HW_ENTRY frv_cgen_hw_table[] = { "h-accg", HW_H_ACCG, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_accg_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<f_LI, 0, pc, length); break; + case FRV_OPERAND_LRAD : + print_normal (cd, info, fields->f_LRAD, 0, pc, length); + break; + case FRV_OPERAND_LRAE : + print_normal (cd, info, fields->f_LRAE, 0, pc, length); + break; + case FRV_OPERAND_LRAS : + print_normal (cd, info, fields->f_LRAS, 0, pc, length); + break; + case FRV_OPERAND_TLBPRL : + print_normal (cd, info, fields->f_TLBPRL, 0, pc, length); + break; + case FRV_OPERAND_TLBPROPX : + print_normal (cd, info, fields->f_TLBPRopx, 0, pc, length); + break; case FRV_OPERAND_AE : print_normal (cd, info, fields->f_ae, 0|(1<f_LI, 0, 0, 25, 1, 32, total_length, buffer); break; + case FRV_OPERAND_LRAD : + errmsg = insert_normal (cd, fields->f_LRAD, 0, 0, 4, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_LRAE : + errmsg = insert_normal (cd, fields->f_LRAE, 0, 0, 5, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_LRAS : + errmsg = insert_normal (cd, fields->f_LRAS, 0, 0, 3, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_TLBPRL : + errmsg = insert_normal (cd, fields->f_TLBPRL, 0, 0, 25, 1, 32, total_length, buffer); + break; + case FRV_OPERAND_TLBPROPX : + errmsg = insert_normal (cd, fields->f_TLBPRopx, 0, 0, 28, 3, 32, total_length, buffer); + break; case FRV_OPERAND_AE : errmsg = insert_normal (cd, fields->f_ae, 0, 0, 25, 1, 32, total_length, buffer); break; @@ -1016,6 +1031,21 @@ frv_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) case FRV_OPERAND_LI : length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 1, 32, total_length, pc, & fields->f_LI); break; + case FRV_OPERAND_LRAD : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 1, 32, total_length, pc, & fields->f_LRAD); + break; + case FRV_OPERAND_LRAE : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 1, 32, total_length, pc, & fields->f_LRAE); + break; + case FRV_OPERAND_LRAS : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 3, 1, 32, total_length, pc, & fields->f_LRAS); + break; + case FRV_OPERAND_TLBPRL : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 1, 32, total_length, pc, & fields->f_TLBPRL); + break; + case FRV_OPERAND_TLBPROPX : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_TLBPRopx); + break; case FRV_OPERAND_AE : length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 1, 32, total_length, pc, & fields->f_ae); break; @@ -1302,6 +1332,21 @@ frv_cgen_get_int_operand (cd, opindex, fields) case FRV_OPERAND_LI : value = fields->f_LI; break; + case FRV_OPERAND_LRAD : + value = fields->f_LRAD; + break; + case FRV_OPERAND_LRAE : + value = fields->f_LRAE; + break; + case FRV_OPERAND_LRAS : + value = fields->f_LRAS; + break; + case FRV_OPERAND_TLBPRL : + value = fields->f_TLBPRL; + break; + case FRV_OPERAND_TLBPROPX : + value = fields->f_TLBPRopx; + break; case FRV_OPERAND_AE : value = fields->f_ae; break; @@ -1539,6 +1584,21 @@ frv_cgen_get_vma_operand (cd, opindex, fields) case FRV_OPERAND_LI : value = fields->f_LI; break; + case FRV_OPERAND_LRAD : + value = fields->f_LRAD; + break; + case FRV_OPERAND_LRAE : + value = fields->f_LRAE; + break; + case FRV_OPERAND_LRAS : + value = fields->f_LRAS; + break; + case FRV_OPERAND_TLBPRL : + value = fields->f_TLBPRL; + break; + case FRV_OPERAND_TLBPROPX : + value = fields->f_TLBPRopx; + break; case FRV_OPERAND_AE : value = fields->f_ae; break; @@ -1785,6 +1845,21 @@ frv_cgen_set_int_operand (cd, opindex, fields, value) case FRV_OPERAND_LI : fields->f_LI = value; break; + case FRV_OPERAND_LRAD : + fields->f_LRAD = value; + break; + case FRV_OPERAND_LRAE : + fields->f_LRAE = value; + break; + case FRV_OPERAND_LRAS : + fields->f_LRAS = value; + break; + case FRV_OPERAND_TLBPRL : + fields->f_TLBPRL = value; + break; + case FRV_OPERAND_TLBPROPX : + fields->f_TLBPRopx = value; + break; case FRV_OPERAND_AE : fields->f_ae = value; break; @@ -2019,6 +2094,21 @@ frv_cgen_set_vma_operand (cd, opindex, fields, value) case FRV_OPERAND_LI : fields->f_LI = value; break; + case FRV_OPERAND_LRAD : + fields->f_LRAD = value; + break; + case FRV_OPERAND_LRAE : + fields->f_LRAE = value; + break; + case FRV_OPERAND_LRAS : + fields->f_LRAS = value; + break; + case FRV_OPERAND_TLBPRL : + fields->f_TLBPRL = value; + break; + case FRV_OPERAND_TLBPROPX : + fields->f_TLBPRopx = value; + break; case FRV_OPERAND_AE : fields->f_ae = value; break; diff --git a/opcodes/frv-opc.c b/opcodes/frv-opc.c index 1560d207dce..2e307e03076 100644 --- a/opcodes/frv-opc.c +++ b/opcodes/frv-opc.c @@ -44,6 +44,8 @@ static int find_major_in_vliw PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE)); static int fr400_check_insn_major_constraints PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE)); +static int fr450_check_insn_major_constraints + PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE)); static int fr500_check_insn_major_constraints PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE)); static int fr550_check_insn_major_constraints @@ -60,6 +62,10 @@ frv_is_branch_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) if (major >= FR400_MAJOR_B_1 && major <= FR400_MAJOR_B_6) return 1; /* is a branch */ break; + case bfd_mach_fr450: + if (major >= FR450_MAJOR_B_1 && major <= FR450_MAJOR_B_6) + return 1; /* is a branch */ + break; default: if (major >= FR500_MAJOR_B_1 && major <= FR500_MAJOR_B_6) return 1; /* is a branch */ @@ -75,6 +81,7 @@ frv_is_float_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) switch (mach) { case bfd_mach_fr400: + case bfd_mach_fr450: return 0; /* No float insns */ default: if (major >= FR500_MAJOR_F_1 && major <= FR500_MAJOR_F_8) @@ -94,6 +101,10 @@ frv_is_media_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) if (major >= FR400_MAJOR_M_1 && major <= FR400_MAJOR_M_2) return 1; /* is a media insn */ break; + case bfd_mach_fr450: + if (major >= FR450_MAJOR_M_1 && major <= FR450_MAJOR_M_6) + return 1; /* is a media insn */ + break; default: if (major >= FR500_MAJOR_M_1 && major <= FR500_MAJOR_M_8) return 1; /* is a media insn */ @@ -109,6 +120,9 @@ frv_is_branch_insn (const CGEN_INSN *insn) if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR), bfd_mach_fr400)) return 1; + if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR), + bfd_mach_fr450)) + return 1; if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR), bfd_mach_fr500)) return 1; @@ -122,6 +136,9 @@ frv_is_float_insn (const CGEN_INSN *insn) if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR), bfd_mach_fr400)) return 1; + if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR), + bfd_mach_fr450)) + return 1; if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR), bfd_mach_fr500)) return 1; @@ -135,6 +152,9 @@ frv_is_media_insn (const CGEN_INSN *insn) if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR), bfd_mach_fr400)) return 1; + if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR), + bfd_mach_fr450)) + return 1; if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR), bfd_mach_fr500)) return 1; @@ -245,6 +265,42 @@ static CGEN_ATTR_VALUE_TYPE fr400_unit_mapping[] = /* SCAN */ UNIT_I0, /* scan only in I0 unit. */ /* DCPL */ UNIT_C, /* dcpl only in C unit. */ /* MDUALACC */ UNIT_FM0, /* media dual acc insn only in FM0 unit. */ +/* MDCUTSSI */ UNIT_FM0, /* mdcutssi only in FM0 unit. */ +/* MCLRACC-1*/ UNIT_FM0 /* mclracc,A==1 insn only in FM0 unit. */ +}; + +/* Some insns are assigned specialized implementation units which map to + different actual implementation units on different machines. These + tables perform that mapping. */ +static CGEN_ATTR_VALUE_TYPE fr450_unit_mapping[] = +{ +/* unit in insn actual unit */ +/* NIL */ UNIT_NIL, +/* I0 */ UNIT_I0, +/* I1 */ UNIT_I1, +/* I01 */ UNIT_I01, +/* I2 */ UNIT_NIL, /* no I2 or I3 unit */ +/* I3 */ UNIT_NIL, +/* IALL */ UNIT_I01, /* only I0 and I1 units */ +/* FM0 */ UNIT_FM0, +/* FM1 */ UNIT_FM1, +/* FM01 */ UNIT_FM01, +/* FM2 */ UNIT_NIL, /* no F2 or M2 units */ +/* FM3 */ UNIT_NIL, /* no F3 or M3 units */ +/* FMALL */ UNIT_FM01,/* Only F0,F1,M0,M1 units */ +/* FMLOW */ UNIT_FM0, /* Only F0,M0 units */ +/* B0 */ UNIT_B0, /* branches only in B0 unit. */ +/* B1 */ UNIT_B0, +/* B01 */ UNIT_B0, +/* C */ UNIT_C, +/* MULT-DIV */ UNIT_I0, /* multiply and divide only in I0 unit. */ +/* IACC */ UNIT_I01, /* iacc multiply in I0 or I1 unit. */ +/* LOAD */ UNIT_I0, /* load only in I0 unit. */ +/* STORE */ UNIT_I0, /* store only in I0 unit. */ +/* SCAN */ UNIT_I0, /* scan only in I0 unit. */ +/* DCPL */ UNIT_I0, /* dcpl only in I0 unit. */ +/* MDUALACC */ UNIT_FM0, /* media dual acc insn only in FM0 unit. */ +/* MDCUTSSI */ UNIT_FM01, /* mdcutssi in FM0 or FM1. */ /* MCLRACC-1*/ UNIT_FM0 /* mclracc,A==1 insn only in FM0 unit. */ }; @@ -276,6 +332,7 @@ static CGEN_ATTR_VALUE_TYPE fr500_unit_mapping[] = /* SCAN */ UNIT_I01, /* scan in I0 or I1 unit. */ /* DCPL */ UNIT_C, /* dcpl only in C unit. */ /* MDUALACC */ UNIT_FM0, /* media dual acc insn only in FM0 unit. */ +/* MDCUTSSI */ UNIT_FM0, /* mdcutssi only in FM0 unit. */ /* MCLRACC-1*/ UNIT_FM01 /* mclracc,A==1 in FM0 or FM1 unit. */ }; @@ -307,6 +364,7 @@ static CGEN_ATTR_VALUE_TYPE fr550_unit_mapping[] = /* SCAN */ UNIT_IALL, /* scan in any integer unit. */ /* DCPL */ UNIT_I0, /* dcpl only in I0 unit. */ /* MDUALACC */ UNIT_FMALL,/* media dual acc insn in all media units */ +/* MDCUTSSI */ UNIT_FM01, /* mdcutssi in FM0 or FM1 unit. */ /* MCLRACC-1*/ UNIT_FM01 /* mclracc,A==1 in FM0 or FM1 unit. */ }; @@ -324,6 +382,10 @@ frv_vliw_reset (FRV_VLIW *vliw, unsigned long mach, unsigned long elf_flags) vliw->current_vliw = fr400_allowed_vliw; vliw->unit_mapping = fr400_unit_mapping; break; + case bfd_mach_fr450: + vliw->current_vliw = fr400_allowed_vliw; + vliw->unit_mapping = fr450_unit_mapping; + break; case bfd_mach_fr550: vliw->current_vliw = fr550_allowed_vliw; vliw->unit_mapping = fr550_unit_mapping; @@ -453,12 +515,51 @@ fr400_check_insn_major_constraints ( case FR400_MAJOR_M_2: return ! find_major_in_vliw (vliw, FR400_MAJOR_M_1) && ! find_major_in_vliw (vliw, FR400_MAJOR_M_2); + case FR400_MAJOR_M_1: + return !find_major_in_vliw (vliw, FR400_MAJOR_M_2); default: break; } return 1; } +static int +fr450_check_insn_major_constraints ( + FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major +) +{ + CGEN_ATTR_VALUE_TYPE other_major; + + /* Our caller guarantees there's at least one other instruction. */ + other_major = CGEN_INSN_ATTR_VALUE (vliw->insn[0], CGEN_INSN_FR450_MAJOR); + + /* (M4, M5) and (M4, M6) are allowed. */ + if (other_major == FR450_MAJOR_M_4) + if (major == FR450_MAJOR_M_5 || major == FR450_MAJOR_M_6) + return 1; + + /* Otherwise, instructions in even-numbered media categories cannot be + executed in parallel with other media instructions. */ + switch (major) + { + case FR450_MAJOR_M_2: + case FR450_MAJOR_M_4: + case FR450_MAJOR_M_6: + return !(other_major >= FR450_MAJOR_M_1 + && other_major <= FR450_MAJOR_M_6); + + case FR450_MAJOR_M_1: + case FR450_MAJOR_M_3: + case FR450_MAJOR_M_5: + return !(other_major == FR450_MAJOR_M_2 + || other_major == FR450_MAJOR_M_4 + || other_major == FR450_MAJOR_M_6); + + default: + return 1; + } +} + static int find_unit_in_vliw ( FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit @@ -696,6 +797,9 @@ check_insn_major_constraints ( case bfd_mach_fr400: rc = fr400_check_insn_major_constraints (vliw, major); break; + case bfd_mach_fr450: + rc = fr450_check_insn_major_constraints (vliw, major); + break; case bfd_mach_fr550: rc = fr550_check_insn_major_constraints (vliw, major, insn); break; @@ -736,6 +840,9 @@ frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn) case bfd_mach_fr400: major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR); break; + case bfd_mach_fr450: + major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR); + break; case bfd_mach_fr550: major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR550_MAJOR); break; @@ -1149,6 +1256,14 @@ static const CGEN_IFMT ifmt_bar = { 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_RD_NULL) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_GRJ_NULL) }, { 0 } } }; +static const CGEN_IFMT ifmt_lrai = { + 32, 32, 0x1fc0fc7, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_LRAE) }, { F (F_LRAD) }, { F (F_LRAS) }, { F (F_LRA_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tlbpr = { + 32, 32, 0x61fc0fc0, { { F (F_PACK) }, { F (F_TLBPR_NULL) }, { F (F_TLBPROPX) }, { F (F_TLBPRL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } } +}; + static const CGEN_IFMT ifmt_cop1 = { 32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_CPRK) }, { F (F_OP) }, { F (F_CPRI) }, { F (F_S6_1) }, { F (F_CPRJ) }, { 0 } } }; @@ -1297,6 +1412,10 @@ static const CGEN_IFMT ifmt_cmqaddhss = { 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } }; +static const CGEN_IFMT ifmt_mqsllhi = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_U6) }, { 0 } } +}; + static const CGEN_IFMT ifmt_maddaccs = { 32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_ACC40SI) }, { F (F_OPE1) }, { F (F_ACCJ_NULL) }, { 0 } } }; @@ -2486,42 +2605,6 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, OP (PACK), ' ', OP (CPRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, & ifmt_ldc, { 0xc0940 } }, -/* rstb$pack $GRk,@($GRi,$GRj) */ - { - { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, - & ifmt_slass, { 0xc0800 } - }, -/* rsth$pack $GRk,@($GRi,$GRj) */ - { - { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, - & ifmt_slass, { 0xc0840 } - }, -/* rst$pack $GRk,@($GRi,$GRj) */ - { - { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, - & ifmt_slass, { 0xc0880 } - }, -/* rstbf$pack $FRintk,@($GRi,$GRj) */ - { - { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, - & ifmt_ldbf, { 0xc0a00 } - }, -/* rsthf$pack $FRintk,@($GRi,$GRj) */ - { - { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, - & ifmt_ldbf, { 0xc0a40 } - }, -/* rstf$pack $FRintk,@($GRi,$GRj) */ - { - { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, - & ifmt_ldbf, { 0xc0a80 } - }, /* std$pack $GRdoublek,@($GRi,$GRj) */ { { 0, 0, 0, 0 }, @@ -2540,18 +2623,6 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, OP (PACK), ' ', OP (CPRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, & ifmt_lddc, { 0xc0980 } }, -/* rstd$pack $GRdoublek,@($GRi,$GRj) */ - { - { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (GRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, - & ifmt_ldd, { 0xc08c0 } - }, -/* rstdf$pack $FRdoublek,@($GRi,$GRj) */ - { - { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRDOUBLEK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, - & ifmt_lddf, { 0xc0ac0 } - }, /* stq$pack $GRk,@($GRi,$GRj) */ { { 0, 0, 0, 0 }, @@ -2570,18 +2641,6 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, OP (PACK), ' ', OP (CPRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, & ifmt_ldc, { 0xc09c0 } }, -/* rstq$pack $GRk,@($GRi,$GRj) */ - { - { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (GRK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, - & ifmt_slass, { 0xc0900 } - }, -/* rstqf$pack $FRintk,@($GRi,$GRj) */ - { - { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTK), ',', '@', '(', OP (GRI), ',', OP (GRJ), ')', 0 } }, - & ifmt_ldbf, { 0xc0b00 } - }, /* stbu$pack $GRk,@($GRi,$GRj) */ { { 0, 0, 0, 0 }, @@ -4616,6 +4675,24 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, OP (PACK), 0 } }, & ifmt_bar, { 0xc0fc0 } }, +/* lrai$pack $GRi,$GRk,$LRAE,$LRAD,$LRAS */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRK), ',', OP (LRAE), ',', OP (LRAD), ',', OP (LRAS), 0 } }, + & ifmt_lrai, { 0xc0800 } + }, +/* lrad$pack $GRi,$GRk,$LRAE,$LRAD,$LRAS */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRK), ',', OP (LRAE), ',', OP (LRAD), ',', OP (LRAS), 0 } }, + & ifmt_lrai, { 0xc0840 } + }, +/* tlbpr$pack $GRi,$GRj,$TLBPRopx,$TLBPRL */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (TLBPROPX), ',', OP (TLBPRL), 0 } }, + & ifmt_tlbpr, { 0xc0900 } + }, /* cop1$pack $s6_1,$CPRi,$CPRj,$CPRk */ { { 0, 0, 0, 0 }, @@ -5498,6 +5575,30 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), ',', OP (CCI), ',', OP (COND), 0 } }, & ifmt_cmqaddhss, { 0x1cc00c0 } }, +/* mqlclrhs$pack $FRintieven,$FRintjeven,$FRintkeven */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mqsaths, { 0x1e00400 } + }, +/* mqlmths$pack $FRintieven,$FRintjeven,$FRintkeven */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mqsaths, { 0x1e00500 } + }, +/* mqsllhi$pack $FRintieven,$u6,$FRintkeven */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (U6), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mqsllhi, { 0x1e00440 } + }, +/* mqsrahi$pack $FRintieven,$u6,$FRintkeven */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (U6), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mqsllhi, { 0x1e004c0 } + }, /* maddaccs$pack $ACC40Si,$ACC40Sk */ { { 0, 0, 0, 0 }, @@ -5966,37 +6067,37 @@ static const CGEN_IBASE frv_cgen_macro_insn_table[] = /* nop$pack */ { -1, "nop", "nop", 32, - { 0|A(ALIAS), { (1<\n" +"Project-Id-Version: opcodes 2.14rel030712\n" +"POT-Creation-Date: 2003-07-11 13:56+0930\n" +"PO-Revision-Date: 2004-02-28 12:30+0100\n" +"Last-Translator: Roland Illig \n" "Language-Team: German \n" "MIME-Version: 1.0\n" "Content-Type: text/plain; charset=utf-8\n" @@ -25,56 +25,60 @@ msgstr "Sprunghinweis ist nicht ausgerichtet (unaligned)." msgid "Illegal limm reference in last instruction!\n" msgstr "Ungültige limm-Referenz in der letzten Anweisung!\n" -#: arm-dis.c:507 +#: arm-dis.c:554 msgid "" -msgstr "" +msgstr "" -#: arm-dis.c:1010 +#: arm-dis.c:1162 #, c-format msgid "Unrecognised register name set: %s\n" msgstr "Unbekannte Registernamensmenge: %s\n" -#: arm-dis.c:1017 +#: arm-dis.c:1169 #, c-format msgid "Unrecognised disassembler option: %s\n" msgstr "Unbekannte Disassembler-Option: %s\n" -#: arm-dis.c:1191 +#: arm-dis.c:1343 msgid "" "\n" "The following ARM specific disassembler options are supported for use with\n" "the -M switch:\n" msgstr "" +"\n" +"Die folgenden ARM-spezifischen Disassembleroptionen werden in Kombination\n" +"mit dem Schalter »-M« unterstützt:\n" -#: avr-dis.c:118 avr-dis.c:128 +#: avr-dis.c:117 avr-dis.c:127 msgid "undefined" msgstr "undefiniert" -#: avr-dis.c:180 +#: avr-dis.c:179 msgid "Internal disassembler error" msgstr "Interner Disassemblerfehler." -#: avr-dis.c:228 +#: avr-dis.c:227 #, c-format msgid "unknown constraint `%c'" -msgstr "" +msgstr "Unbekannte Einschränkung »%c«" -#: cgen-asm.c:346 fr30-ibld.c:195 frv-ibld.c:195 m32r-ibld.c:195 -#: openrisc-ibld.c:195 xstormy16-ibld.c:195 +#: cgen-asm.c:348 fr30-ibld.c:195 frv-ibld.c:195 ip2k-ibld.c:195 +#: iq2000-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 xstormy16-ibld.c:195 #, c-format msgid "operand out of range (%ld not between %ld and %ld)" -msgstr "" +msgstr "Operand außerhalb des gültigen Bereichs (%ld ist nicht zwischen %ld und %ld)" -#: cgen-asm.c:367 +#: cgen-asm.c:369 #, c-format msgid "operand out of range (%lu not between %lu and %lu)" -msgstr "" +msgstr "Operand außerhalb des gültigen Bereichs (%lu ist nicht zwischen %lu und %lu)" #: d30v-dis.c:312 #, c-format msgid "" msgstr "" +# Can't happen. #. Can't happen. #: dis-buf.c:57 #, c-format @@ -84,286 +88,641 @@ msgstr "Unbekannter Fehler %d\n" #: dis-buf.c:62 #, c-format msgid "Address 0x%x is out of bounds.\n" -msgstr "" +msgstr "Adresse 0x%x ist außerhalb des gültigen Bereichs.\n" -#: fr30-asm.c:323 frv-asm.c:595 m32r-asm.c:325 openrisc-asm.c:244 -#: xstormy16-asm.c:231 +#: fr30-asm.c:323 frv-asm.c:626 ip2k-asm.c:574 iq2000-asm.c:460 m32r-asm.c:325 +#: openrisc-asm.c:261 xstormy16-asm.c:284 #, c-format msgid "Unrecognized field %d while parsing.\n" -msgstr "" +msgstr "Unbekanntes Feld %d beim Parsen entdeckt.\n" -#: fr30-asm.c:373 frv-asm.c:645 m32r-asm.c:375 openrisc-asm.c:294 -#: xstormy16-asm.c:281 +#: fr30-asm.c:373 frv-asm.c:676 ip2k-asm.c:624 iq2000-asm.c:510 m32r-asm.c:375 +#: openrisc-asm.c:311 xstormy16-asm.c:334 msgid "missing mnemonic in syntax string" -msgstr "" +msgstr "Fehlender Mnemonic im Syntaxstring" +# We couldn't parse it. #. We couldn't parse it. -#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 frv-asm.c:781 -#: frv-asm.c:785 frv-asm.c:872 frv-asm.c:974 m32r-asm.c:511 m32r-asm.c:515 -#: m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:430 openrisc-asm.c:434 -#: openrisc-asm.c:521 openrisc-asm.c:623 xstormy16-asm.c:417 -#: xstormy16-asm.c:421 xstormy16-asm.c:508 xstormy16-asm.c:610 +#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 frv-asm.c:812 +#: frv-asm.c:816 frv-asm.c:903 frv-asm.c:1005 ip2k-asm.c:760 ip2k-asm.c:764 +#: ip2k-asm.c:851 ip2k-asm.c:953 iq2000-asm.c:646 iq2000-asm.c:650 +#: iq2000-asm.c:737 iq2000-asm.c:839 m32r-asm.c:511 m32r-asm.c:515 +#: m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:447 openrisc-asm.c:451 +#: openrisc-asm.c:538 openrisc-asm.c:640 xstormy16-asm.c:470 +#: xstormy16-asm.c:474 xstormy16-asm.c:561 xstormy16-asm.c:663 msgid "unrecognized instruction" -msgstr "" +msgstr "Unbekannter Befehl" -#: fr30-asm.c:556 frv-asm.c:828 m32r-asm.c:558 openrisc-asm.c:477 -#: xstormy16-asm.c:464 +#: fr30-asm.c:556 frv-asm.c:859 ip2k-asm.c:807 iq2000-asm.c:693 m32r-asm.c:558 +#: openrisc-asm.c:494 xstormy16-asm.c:517 #, c-format msgid "syntax error (expected char `%c', found `%c')" msgstr "Syntaxfehler (erwartetes Zeichen »%c«, gefunden »%c«)" -#: fr30-asm.c:566 frv-asm.c:838 m32r-asm.c:568 openrisc-asm.c:487 -#: xstormy16-asm.c:474 +#: fr30-asm.c:566 frv-asm.c:869 ip2k-asm.c:817 iq2000-asm.c:703 m32r-asm.c:568 +#: openrisc-asm.c:504 xstormy16-asm.c:527 #, c-format msgid "syntax error (expected char `%c', found end of instruction)" -msgstr "" +msgstr "Syntaxfehler (Zeichen »%c« erwartet, Befehlsende bekommen)" -#: fr30-asm.c:594 frv-asm.c:866 m32r-asm.c:596 openrisc-asm.c:515 -#: xstormy16-asm.c:502 +#: fr30-asm.c:594 frv-asm.c:897 ip2k-asm.c:845 iq2000-asm.c:731 m32r-asm.c:596 +#: openrisc-asm.c:532 xstormy16-asm.c:555 msgid "junk at end of line" -msgstr "" +msgstr "Müll am Ende der Zeile" -#: fr30-asm.c:701 frv-asm.c:973 m32r-asm.c:703 openrisc-asm.c:622 -#: xstormy16-asm.c:609 +#: fr30-asm.c:701 frv-asm.c:1004 ip2k-asm.c:952 iq2000-asm.c:838 +#: m32r-asm.c:703 openrisc-asm.c:639 xstormy16-asm.c:662 msgid "unrecognized form of instruction" -msgstr "" +msgstr "Unbekannte Befehlsform" -#: fr30-asm.c:713 frv-asm.c:985 m32r-asm.c:715 openrisc-asm.c:634 -#: xstormy16-asm.c:621 +#: fr30-asm.c:713 frv-asm.c:1016 ip2k-asm.c:964 iq2000-asm.c:850 +#: m32r-asm.c:715 openrisc-asm.c:651 xstormy16-asm.c:674 #, c-format msgid "bad instruction `%.50s...'" -msgstr "" +msgstr "Falscher Befehl »%.50s...«" -#: fr30-asm.c:716 frv-asm.c:988 m32r-asm.c:718 openrisc-asm.c:637 -#: xstormy16-asm.c:624 +#: fr30-asm.c:716 frv-asm.c:1019 ip2k-asm.c:967 iq2000-asm.c:853 +#: m32r-asm.c:718 openrisc-asm.c:654 xstormy16-asm.c:677 #, c-format msgid "bad instruction `%.50s'" -msgstr "" +msgstr "Falscher Befehl »%.50s«" +# Default text to print if an instruction isn't recognized. #. Default text to print if an instruction isn't recognized. -#: fr30-dis.c:39 frv-dis.c:39 m32r-dis.c:39 mmix-dis.c:282 openrisc-dis.c:39 -#: xstormy16-dis.c:39 +#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 m32r-dis.c:41 +#: mmix-dis.c:284 openrisc-dis.c:41 xstormy16-dis.c:41 msgid "*unknown*" -msgstr "" +msgstr "*unbekannt*" -#: fr30-dis.c:318 frv-dis.c:360 m32r-dis.c:249 openrisc-dis.c:136 -#: xstormy16-dis.c:169 +#: fr30-dis.c:320 frv-dis.c:371 ip2k-dis.c:329 iq2000-dis.c:192 m32r-dis.c:251 +#: openrisc-dis.c:138 xstormy16-dis.c:171 #, c-format msgid "Unrecognized field %d while printing insn.\n" -msgstr "" +msgstr "Unbekanntes Feld %d beim Schreiben des Befehls.\n" -#: fr30-ibld.c:166 frv-ibld.c:166 m32r-ibld.c:166 openrisc-ibld.c:166 -#: xstormy16-ibld.c:166 +#: fr30-ibld.c:166 frv-ibld.c:166 ip2k-ibld.c:166 iq2000-ibld.c:166 +#: m32r-ibld.c:166 openrisc-ibld.c:166 xstormy16-ibld.c:166 #, c-format msgid "operand out of range (%ld not between %ld and %lu)" -msgstr "" +msgstr "Operand außerhalb des gültigen Bereichs (%ld ist nicht zwischen %ld und %lu)" -#: fr30-ibld.c:179 frv-ibld.c:179 m32r-ibld.c:179 openrisc-ibld.c:179 -#: xstormy16-ibld.c:179 +#: fr30-ibld.c:179 frv-ibld.c:179 ip2k-ibld.c:179 iq2000-ibld.c:179 +#: m32r-ibld.c:179 openrisc-ibld.c:179 xstormy16-ibld.c:179 #, c-format msgid "operand out of range (%lu not between 0 and %lu)" -msgstr "" +msgstr "Operand außerhalb des gültigen Bereichs (%lu ist nicht zwischen 0 und %lu)" -#: fr30-ibld.c:730 frv-ibld.c:820 m32r-ibld.c:659 openrisc-ibld.c:633 -#: xstormy16-ibld.c:678 +#: fr30-ibld.c:730 frv-ibld.c:829 ip2k-ibld.c:607 iq2000-ibld.c:713 +#: m32r-ibld.c:659 openrisc-ibld.c:633 xstormy16-ibld.c:678 #, c-format msgid "Unrecognized field %d while building insn.\n" -msgstr "" +msgstr "Unbekanntes Feld %d beim Erzeugen des Befehls.\n" -#: fr30-ibld.c:937 frv-ibld.c:1103 m32r-ibld.c:792 openrisc-ibld.c:735 -#: xstormy16-ibld.c:826 +#: fr30-ibld.c:937 frv-ibld.c:1121 ip2k-ibld.c:684 iq2000-ibld.c:890 +#: m32r-ibld.c:792 openrisc-ibld.c:735 xstormy16-ibld.c:826 #, c-format msgid "Unrecognized field %d while decoding insn.\n" -msgstr "" +msgstr "Unbekannted Feld %d beim Decodieren des Befehls.\n" -#: fr30-ibld.c:1086 frv-ibld.c:1348 m32r-ibld.c:902 openrisc-ibld.c:815 -#: xstormy16-ibld.c:939 +#: fr30-ibld.c:1086 frv-ibld.c:1375 ip2k-ibld.c:761 iq2000-ibld.c:1024 +#: m32r-ibld.c:902 openrisc-ibld.c:815 xstormy16-ibld.c:939 #, c-format msgid "Unrecognized field %d while getting int operand.\n" -msgstr "" +msgstr "Unbekanntes Feld %d beim Holen des int-Operanden.\n" -#: fr30-ibld.c:1215 frv-ibld.c:1573 m32r-ibld.c:992 openrisc-ibld.c:875 -#: xstormy16-ibld.c:1032 +#: fr30-ibld.c:1215 frv-ibld.c:1609 ip2k-ibld.c:818 iq2000-ibld.c:1138 +#: m32r-ibld.c:992 openrisc-ibld.c:875 xstormy16-ibld.c:1032 #, c-format msgid "Unrecognized field %d while getting vma operand.\n" -msgstr "" +msgstr "Unbekanntes Feld %d beim Holen des vma-Operanden.\n" -#: fr30-ibld.c:1349 frv-ibld.c:1807 m32r-ibld.c:1090 openrisc-ibld.c:944 -#: xstormy16-ibld.c:1134 +#: fr30-ibld.c:1349 frv-ibld.c:1852 ip2k-ibld.c:880 iq2000-ibld.c:1261 +#: m32r-ibld.c:1090 openrisc-ibld.c:944 xstormy16-ibld.c:1134 #, c-format msgid "Unrecognized field %d while setting int operand.\n" -msgstr "" +msgstr "Unbekanntes Feld %d beim Setzen des int-Operanden.\n" -#: fr30-ibld.c:1471 frv-ibld.c:2029 m32r-ibld.c:1176 openrisc-ibld.c:1001 -#: xstormy16-ibld.c:1224 +#: fr30-ibld.c:1471 frv-ibld.c:2083 ip2k-ibld.c:930 iq2000-ibld.c:1372 +#: m32r-ibld.c:1176 openrisc-ibld.c:1001 xstormy16-ibld.c:1224 #, c-format msgid "Unrecognized field %d while setting vma operand.\n" -msgstr "" +msgstr "Unbekanntes Feld %d beim Holen des vma-Operanden.\n" + +#: frv-asm.c:365 +msgid "register number must be even" +msgstr "Die Registernummer muss gerade sein." -#: h8300-dis.c:385 +#: h8300-dis.c:377 #, c-format -msgid "Hmmmm %x" -msgstr "" +msgid "Hmmmm 0x%x" +msgstr "Hmmmm 0x%x" -#: h8300-dis.c:396 +#: h8300-dis.c:760 #, c-format -msgid "Don't understand %x \n" -msgstr "" +msgid "Don't understand 0x%x \n" +msgstr "Ich verstehe »0x%x« nicht.\n" #: h8500-dis.c:143 #, c-format msgid "can't cope with insert %d\n" -msgstr "" +msgstr "Kann nicht mit »inserv %d« umgehen.\n" +# Couldn't understand anything. #. Couldn't understand anything. #: h8500-dis.c:350 #, c-format msgid "%02x\t\t*unknown*" -msgstr "" +msgstr "%02x\t\t*unbekannt*" -#: i386-dis.c:1649 +#: i386-dis.c:1699 msgid "" -msgstr "" +msgstr "" + +#: ia64-gen.c:295 +#, c-format +msgid "%s: Error: " +msgstr "%s: Fehler:" + +#: ia64-gen.c:308 +#, c-format +msgid "%s: Warning: " +msgstr "%s: Warnung:" + +#: ia64-gen.c:494 ia64-gen.c:728 +#, c-format +msgid "multiple note %s not handled\n" +msgstr "Mehrfache Bemerkung »%s« nicht verarbeitet.\n" + +#: ia64-gen.c:605 +msgid "can't find ia64-ic.tbl for reading\n" +msgstr "Kann »ia64-ic.tbl« nicht zum Lesen finden\n" + +#: ia64-gen.c:810 +#, c-format +msgid "can't find %s for reading\n" +msgstr "Kann »%s« nicht zum Lesen finden\n" + +#: ia64-gen.c:1034 +#, c-format +msgid "" +"most recent format '%s'\n" +"appears more restrictive than '%s'\n" +msgstr "Das letzte Format »%s« scheint strenger zu sein als »%s«.\n" + +#: ia64-gen.c:1045 +#, c-format +msgid "overlapping field %s->%s\n" +msgstr "Überlappendes Feld »%s->%s«.\n" + +#: ia64-gen.c:1236 +#, c-format +msgid "overwriting note %d with note %d (IC:%s)\n" +msgstr "Überschreibe Bemerkung %d mit Bemerkung %d (IC:%s)\n" + +#: ia64-gen.c:1435 +#, c-format +msgid "don't know how to specify %% dependency %s\n" +msgstr "Keine Ahnung, wie ich die Abhängigkeit »%% %s« angeben soll.\n" + +#: ia64-gen.c:1457 +#, c-format +msgid "Don't know how to specify # dependency %s\n" +msgstr "Keine Ahnung, wie ich die Abhängigkeit »# %s« angeben soll.\n" + +#: ia64-gen.c:1496 +#, c-format +msgid "IC:%s [%s] has no terminals or sub-classes\n" +msgstr "IC:%s [%s] hat weder Terminale noch Unterklassen\n" + +#: ia64-gen.c:1499 +#, c-format +msgid "IC:%s has no terminals or sub-classes\n" +msgstr "IC:%s hat weder Terminale noch Unterklassen\n" + +#: ia64-gen.c:1508 +#, c-format +msgid "no insns mapped directly to terminal IC %s [%s]" +msgstr "Kein Befehl ist dem Terminal-IC »%s [%s]« direkt zugeordnet" + +#: ia64-gen.c:1511 +#, c-format +msgid "no insns mapped directly to terminal IC %s\n" +msgstr "Kein Befehl ist dem Terminal-IC »%s« direkt zugeordnet.\n" + +#: ia64-gen.c:1522 +#, c-format +msgid "class %s is defined but not used\n" +msgstr "Die Klasse »%s« wurde definiert, aber nicht benutzt.\n" + +#: ia64-gen.c:1533 +#, c-format +msgid "Warning: rsrc %s (%s) has no chks%s\n" +msgstr "Warnung: Die Ressource »%s (%s)« hat keine »chks%s«.\n" + +#: ia64-gen.c:1537 +#, c-format +msgid "rsrc %s (%s) has no regs\n" +msgstr "Die Ressource »%s (%s)« hat keine Register\n" + +#: ia64-gen.c:2436 +#, c-format +msgid "IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "IC Bemerkung %d in Opcode »%s (IC:%s)« verträgt sich nicht mit Ressource %s Bemerkung %d.\n" + +#: ia64-gen.c:2464 +#, c-format +msgid "IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "IC Bemerkung %d für Opcode »%s (IC:%s)« verträgt sich nicht mit Ressource %s Bemerkung %d.\n" + +#: ia64-gen.c:2478 +#, c-format +msgid "opcode %s has no class (ops %d %d %d)\n" +msgstr "Opcode %s hat keine Klasse (Operanden %d %d %d)\n" + +#: ia64-gen.c:2789 +#, c-format +msgid "unable to change directory to \"%s\", errno = %s\n" +msgstr "Kann nicht in das Verzeichnis »%s« wechseln, errno = %s\n" + +# We've been passed a w. Return with an error message so that +# cgen will try the next parsing option. +#. We've been passed a w. Return with an error message so that +#. cgen will try the next parsing option. +#: ip2k-asm.c:92 +msgid "W keyword invalid in FR operand slot." +msgstr "Schlüsselwort »W« ist im Operandenplatz »FR« ungültig." + +# Invalid offset present. +#. Invalid offset present. +#: ip2k-asm.c:122 +msgid "offset(IP) is not a valid form" +msgstr "»offset(IP)« ist keine gültige Form." + +# Found something there in front of (DP) but it's out +# of range. +#. Found something there in front of (DP) but it's out +#. of range. +#: ip2k-asm.c:175 +msgid "(DP) offset out of range." +msgstr "(DP) Offset außerhalb des gültigen Bereichs." + +# Found something there in front of (SP) but it's out +# of range. +#. Found something there in front of (SP) but it's out +#. of range. +#: ip2k-asm.c:221 +msgid "(SP) offset out of range." +msgstr "(SP) Offset außerhalb des gültigen Bereichs." + +#: ip2k-asm.c:241 +msgid "illegal use of parentheses" +msgstr "Unerlaubte Benutzung von Klammern." + +#: ip2k-asm.c:248 +msgid "operand out of range (not between 1 and 255)" +msgstr "Operand außerhalb des gültigen Bereichs (1 bis 255)." + +# Something is very wrong. opindex has to be one of the above. +#. Something is very wrong. opindex has to be one of the above. +#: ip2k-asm.c:273 +msgid "parse_addr16: invalid opindex." +msgstr "parse_addr16: Ungültiger Operatorindex." + +#: ip2k-asm.c:353 +msgid "Byte address required. - must be even." +msgstr "Byteadresse benötigt -- muss gerade sein." + +#: ip2k-asm.c:362 +msgid "cgen_parse_address returned a symbol. Literal required." +msgstr "cgen_parse_address: Gebe Symbol zurück. Sollte eigentlich ein Literal sein." + +#: ip2k-asm.c:420 +#, c-format +msgid "%operator operand is not a symbol" +msgstr "Der Operand %operator muss ein Symbol sein." + +#: ip2k-asm.c:474 +msgid "Attempt to find bit index of 0" +msgstr "Versuch, ein gesetztes Bit von 0 zu bestimmen" + +#: iq2000-asm.c:110 iq2000-asm.c:141 +msgid "immediate value cannot be register" +msgstr "Ein Direktoperand kann kein Register sein." + +#: iq2000-asm.c:120 iq2000-asm.c:151 +msgid "immediate value out of range" +msgstr "Direktoperand außerhalb des gültigen Bereichs." + +#: iq2000-asm.c:180 +msgid "21-bit offset out of range" +msgstr "21-Bit-Offset außerhalb des gültigen Bereichs" + +#: iq2000-asm.c:205 iq2000-asm.c:235 iq2000-asm.c:272 iq2000-asm.c:305 +#: openrisc-asm.c:96 openrisc-asm.c:155 +msgid "missing `)'" +msgstr "Fehlende »)«." #: m10200-dis.c:199 #, c-format msgid "unknown\t0x%02x" -msgstr "" +msgstr "unbekannt\t0x%02x" #: m10200-dis.c:339 #, c-format msgid "unknown\t0x%04lx" -msgstr "" +msgstr "unbekannt\t0x%04lx" -#: m10300-dis.c:685 +#: m10300-dis.c:766 #, c-format msgid "unknown\t0x%04x" -msgstr "" +msgstr "unbekannt\t0x%04x" #: m68k-dis.c:429 #, c-format msgid "\n" -msgstr "" +msgstr "\n" #: m68k-dis.c:1007 #, c-format msgid "" -msgstr "" +msgstr "" -#: m88k-dis.c:255 +#: m88k-dis.c:746 #, c-format msgid "# " -msgstr "" +msgstr "# " + +#: mips-dis.c:699 +msgid "# internal error, incomplete extension sequence (+)" +msgstr "# Interner Fehler, unvollständige Erweiterungsfolge (+)" + +#: mips-dis.c:742 +#, c-format +msgid "# internal error, undefined extension sequence (+%c)" +msgstr "# Interner Fehler, undefinierte Erweiterungsfolge (+%c)" -#: mips-dis.c:337 +#: mips-dis.c:1000 #, c-format msgid "# internal error, undefined modifier(%c)" -msgstr "" +msgstr "# Interner Fehler, undefinierter Modifikator (%c)" -#: mips-dis.c:1209 +#: mips-dis.c:1751 #, c-format msgid "# internal disassembler error, unrecognised modifier (%c)" +msgstr "# Interner Fehler im Disassembler: unerkannter Modifikator (%c)" + +#: mips-dis.c:1763 +msgid "" +"\n" +"The following MIPS specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" +"\n" +"Die folgenden MIPS-spezifischen Disassembleroptionen werden zusammen\n" +"mit dem Schalter »-M« unterstützt (mehrere Optionen sollten durch\n" +"Kommata getrennt werden):\n" + +#: mips-dis.c:1767 +msgid "" +"\n" +" gpr-names=ABI Print GPR names according to specified ABI.\n" +" Default: based on binary being disassembled.\n" msgstr "" +"\n" +" gpr-names=ABI Gib GPR-Namen entsprechend des angegebenen ABI aus.\n" +" Standard: abhängig von der Binärdatei, die\n" +" disassembliert wird.\n" + +#: mips-dis.c:1771 +msgid "" +"\n" +" fpr-names=ABI Print FPR names according to specified ABI.\n" +" Default: numeric.\n" +msgstr "" +"\n" +" fpr-names=ABI Gib FPR-Namen entsprechend des angegebenen ABI aus.\n" +" Standard: numerisch.\n" + +#: mips-dis.c:1775 +msgid "" +"\n" +" cp0-names=ARCH Print CP0 register names according to\n" +" specified architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" cp0-names=ARCH Gib CP0-Registernamen entsprechend der angegebenen\n" +" Architektur aus.\n" +" Standard: abhängig von der Binärdatei, die\n" +" disassembliert wird.\n" + +#: mips-dis.c:1780 +msgid "" +"\n" +" hwr-names=ARCH Print HWR names according to specified \n" +"\t\t\t architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" +"\n" +" hwr-names=ARCH Gib HWR-Namen entsprechend der angegebenen\n" +" Architektur aus.\n" +" Standard: abhängig von der Binärdatei, die\n" +" verarbeitet wird.\n" + +#: mips-dis.c:1785 +msgid "" +"\n" +" reg-names=ABI Print GPR and FPR names according to\n" +" specified ABI.\n" +msgstr "" +"\n" +" reg-names=ABI Gib GPR- und FPR-Namen entsprechend des\n" +" angegebenen ABI aus.\n" + +#: mips-dis.c:1789 +msgid "" +"\n" +" reg-names=ARCH Print CP0 register and HWR names according to\n" +" specified architecture.\n" +msgstr "" +"\n" +" reg-names=ARCH Gib CP0-Register und HWR-Namen entsprechend der\n" +" angegebenen Architektur aus.\n" + +#: mips-dis.c:1793 +msgid "" +"\n" +" For the options above, the following values are supported for \"ABI\":\n" +" " +msgstr "" +"\n" +" Für die obigen Optionen werden die folgenden Werte für »ABI« unterstützt:\n" +" " + +#: mips-dis.c:1798 mips-dis.c:1806 mips-dis.c:1808 +msgid "\n" +msgstr "\n" + +#: mips-dis.c:1800 +msgid "" +"\n" +" For the options above, The following values are supported for \"ARCH\":\n" +" " +msgstr "" +"\n" +" Für die obigen Optionen werden die folgenden Werte für »ARCH« unterstützt:\n" +" " #: mmix-dis.c:34 #, c-format msgid "Bad case %d (%s) in %s:%d\n" -msgstr "" +msgstr "Interner Fehler: case %d (%s) in %s:%d\n" #: mmix-dis.c:44 #, c-format msgid "Internal: Non-debugged code (test-case missing): %s:%d" -msgstr "" +msgstr "Intern: Nicht gedebuggter Code (Testfall fehlt): %s:%d" #: mmix-dis.c:53 msgid "(unknown)" -msgstr "" +msgstr "(unbekannt)" -#: mmix-dis.c:517 +#: mmix-dis.c:519 #, c-format msgid "*unknown operands type: %d*" -msgstr "" +msgstr "Unbekannter Operandentyp: %d*" +# I and Z are output operands and can`t be immediate +# * A is an address and we can`t have the address of +# * an immediate either. We don't know how much to increase +# * aoffsetp by since whatever generated this is broken +# * anyway! #. I and Z are output operands and can`t be immediate #. * A is an address and we can`t have the address of #. * an immediate either. We don't know how much to increase #. * aoffsetp by since whatever generated this is broken #. * anyway! #. -#: ns32k-dis.c:628 +#: ns32k-dis.c:631 msgid "$" -msgstr "" +msgstr "$" -#: ppc-opc.c:777 ppc-opc.c:810 +#: ppc-opc.c:781 ppc-opc.c:809 msgid "invalid conditional option" -msgstr "" +msgstr "Ungültige bedingte Option" -#: ppc-opc.c:812 +#: ppc-opc.c:811 msgid "attempt to set y bit when using + or - modifier" -msgstr "" +msgstr "Versuch, das y-Bit zusammen mit dem Modifikator »+« oder »-« zu setzen." + +#: ppc-opc.c:840 +msgid "offset not a multiple of 16" +msgstr "Offset muss ein Vielfaches von 16 sein" + +#: ppc-opc.c:860 +msgid "offset not a multiple of 2" +msgstr "Offset muss ein Vielfaches von 2 sein" -#: ppc-opc.c:844 ppc-opc.c:896 +#: ppc-opc.c:862 +msgid "offset greater than 62" +msgstr "Offset darf nicht größer als 62 sein" + +#: ppc-opc.c:881 ppc-opc.c:927 ppc-opc.c:975 msgid "offset not a multiple of 4" -msgstr "" +msgstr "Offset muss ein Vielfaches von 4 sein" + +#: ppc-opc.c:883 +msgid "offset greater than 124" +msgstr "Offset darf nicht größer als 124 sein" -#: ppc-opc.c:869 +#: ppc-opc.c:902 +msgid "offset not a multiple of 8" +msgstr "Offset muss ein Vielfaches von 8 sein" + +#: ppc-opc.c:904 +msgid "offset greater than 248" +msgstr "Offset darf nicht größer als 248 sein" + +#: ppc-opc.c:950 msgid "offset not between -2048 and 2047" -msgstr "" +msgstr "Offset muss im Bereich von -2048 bis 2047 liegen" -#: ppc-opc.c:894 +#: ppc-opc.c:973 msgid "offset not between -8192 and 8191" -msgstr "" +msgstr "Offset muss im Bereich von -8192 bis 8191 liegen" + +#: ppc-opc.c:1011 +msgid "ignoring invalid mfcr mask" +msgstr "Ignoriere ungültige mfcr-Maske." -#: ppc-opc.c:922 +#: ppc-opc.c:1059 msgid "ignoring least significant bits in branch offset" -msgstr "" +msgstr "Ignoriere niedrigste Bits im Verzweigungsoffset" -#: ppc-opc.c:956 ppc-opc.c:993 +#: ppc-opc.c:1090 ppc-opc.c:1125 msgid "illegal bitmask" -msgstr "" +msgstr "Ungültige Bitmaske" -#: ppc-opc.c:1066 +#: ppc-opc.c:1192 msgid "value out of range" -msgstr "" +msgstr "Wert außerhalb des gültigen Bereichs" -#: ppc-opc.c:1142 +#: ppc-opc.c:1262 msgid "index register in load range" -msgstr "" +msgstr "Indexregister im Ladebereich (load range)" -#: ppc-opc.c:1158 +#: ppc-opc.c:1279 +msgid "source and target register operands must be different" +msgstr "Die Operanden für das Quell- und Zielregister müssen verschieden sein" + +#: ppc-opc.c:1294 msgid "invalid register operand when updating" -msgstr "" +msgstr "Ungültiger Registeroperand beim Aktualisieren" + +#: ppc-opc.c:1335 +msgid "target register operand must be even" +msgstr "Der Zielregisteroperand muss gerade sein" -#. Mark as non-valid instruction -#: sparc-dis.c:750 +#: ppc-opc.c:1350 +msgid "source register operand must be even" +msgstr "Der Quellregisteroperand muss gerade sein" + +# Mark as non-valid instruction. +#. Mark as non-valid instruction. +#: sparc-dis.c:760 msgid "unknown" -msgstr "" +msgstr "unbekannt" -#: sparc-dis.c:825 +#: sparc-dis.c:835 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" -msgstr "" +msgstr "Interner Fehler: Ungültiger SPARC-Opcode: \"%s\", %#.8lx, %#.8lx\n" -#: sparc-dis.c:836 +#: sparc-dis.c:846 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" -msgstr "" +msgstr "Interner Fehler: Ungültiger SPARC-Opcode: \"%s\", %#.8lx, %#.8lx\n" -#: sparc-dis.c:885 +#: sparc-dis.c:895 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" -msgstr "" +msgstr "Interner Fehler: Ungültiger SPARC-Opcode: \"%s\" == \"%s\"\n" -#: v850-dis.c:224 +#: v850-dis.c:221 #, c-format msgid "unknown operand shift: %x\n" -msgstr "" +msgstr "Unbekannte Operandenverschiebung: %x\n" -#: v850-dis.c:236 +#: v850-dis.c:233 #, c-format msgid "unknown pop reg: %d\n" -msgstr "" +msgstr "Unbekanntes pop-Register: %d\n" +# The functions used to insert and extract complicated operands. +# Note: There is a conspiracy between these functions and +# v850_insert_operand() in gas/config/tc-v850.c. Error messages +# containing the string 'out of range' will be ignored unless a +# specific command line option is given to GAS. #. The functions used to insert and extract complicated operands. #. Note: There is a conspiracy between these functions and #. v850_insert_operand() in gas/config/tc-v850.c. Error messages @@ -371,72 +730,84 @@ msgstr "" #. specific command line option is given to GAS. #: v850-opc.c:68 msgid "displacement value is not in range and is not aligned" -msgstr "" +msgstr "Der Abstandswert ist außerhalb des gültigen Bereichs und nicht ausgerichtet" #: v850-opc.c:69 msgid "displacement value is out of range" -msgstr "" +msgstr "Der Abstandswert ist außerhalb des fültigen Bereichs." #: v850-opc.c:70 msgid "displacement value is not aligned" -msgstr "" +msgstr "Der Abstandswert ist nicht ausgerichtet." #: v850-opc.c:72 msgid "immediate value is out of range" -msgstr "" +msgstr "Direktwert außerhalb des gültigen Bereichs" #: v850-opc.c:83 msgid "branch value not in range and to odd offset" -msgstr "" +msgstr "Verzweigungswert außerhalb des gültigen Bereichs und zu einem ungeraden Offset." #: v850-opc.c:85 v850-opc.c:117 msgid "branch value out of range" -msgstr "" +msgstr "Verzweigungswert außerhalb des gültigen Bereichs." #: v850-opc.c:88 v850-opc.c:120 msgid "branch to odd offset" -msgstr "" +msgstr "Verzweigung auf ungeraden Offset" #: v850-opc.c:115 msgid "branch value not in range and to an odd offset" -msgstr "" +msgstr "Verzweigungswert außerhalb des gültigen Bereichs und zu einem ungeraden Offset." #: v850-opc.c:346 msgid "invalid register for stack adjustment" -msgstr "" +msgstr "Ungültiges Register für Stackanpassung." #: v850-opc.c:370 msgid "immediate value not in range and not even" -msgstr "" +msgstr "Direktwert außerhalb des gültigen Bereichs und nicht gerade" #: v850-opc.c:375 msgid "immediate value must be even" msgstr "Der Direktoperand muss gerade sein." -#: xstormy16-asm.c:74 +#: xstormy16-asm.c:76 msgid "Bad register in preincrement" -msgstr "" +msgstr "Ungültiges Register beim Pre-Increment" -#: xstormy16-asm.c:79 +#: xstormy16-asm.c:81 msgid "Bad register in postincrement" -msgstr "" +msgstr "Ungültiges Register beim Post-Increment" -#: xstormy16-asm.c:81 +#: xstormy16-asm.c:83 msgid "Bad register name" msgstr "Falscher Registername." -#: xstormy16-asm.c:85 +#: xstormy16-asm.c:87 msgid "Label conflicts with register name" -msgstr "" +msgstr "Sprungmarke verträgt sich nicht mit dem Registername" -#: xstormy16-asm.c:89 +#: xstormy16-asm.c:91 msgid "Label conflicts with `Rx'" -msgstr "" +msgstr "Sprungmarke verträgt sich nicht mit »Rx«" -#: xstormy16-asm.c:91 +#: xstormy16-asm.c:93 msgid "Bad immediate expression" -msgstr "" +msgstr "Ungültiger Direktausdruck" + +#: xstormy16-asm.c:115 +msgid "No relocation for small immediate" +msgstr "Keine Verlagerung für kleine Direktwerte" -#: xstormy16-asm.c:120 +#: xstormy16-asm.c:125 msgid "Small operand was not an immediate number" -msgstr "" +msgstr "Kleiner Operand war keine Direktzahl." + +#: xstormy16-asm.c:164 +msgid "Operand is not a symbol" +msgstr "Operand muss ein Symbol sein" + +#: xstormy16-asm.c:172 +msgid "Syntax error: No trailing ')'" +msgstr "Syntaxfehler: Kein abschließendes »)«" diff --git a/opcodes/sh-dis.c b/opcodes/sh-dis.c index 2512f966d35..840823e0206 100644 --- a/opcodes/sh-dis.c +++ b/opcodes/sh-dis.c @@ -1,5 +1,5 @@ /* Disassemble SH instructions. - Copyright 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2003 + Copyright 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify @@ -433,8 +433,10 @@ print_insn_sh (memaddr, info) case bfd_mach_sh3e: target_arch = arch_sh3e; break; - case bfd_mach_sh4: case bfd_mach_sh4_nofpu: + target_arch = arch_sh4_nofpu; + break; + case bfd_mach_sh4: target_arch = arch_sh4; break; case bfd_mach_sh4a: @@ -444,6 +446,9 @@ print_insn_sh (memaddr, info) case bfd_mach_sh4al_dsp: target_arch = arch_sh4al_dsp; break; + case bfd_mach_sh4_nommu_nofpu: + target_arch = arch_sh4_nommu_nofpu; + break; case bfd_mach_sh5: #ifdef INCLUDE_SHMEDIA status = print_insn_sh64 (memaddr, info); diff --git a/opcodes/sh-opc.h b/opcodes/sh-opc.h index 0ef1fab42a6..a1877b33ae7 100644 --- a/opcodes/sh-opc.h +++ b/opcodes/sh-opc.h @@ -1,5 +1,5 @@ /* Definitions for SH opcodes. - Copyright 1993, 1994, 1995, 1997, 1999, 2000, 2003 + Copyright 1993, 1994, 1995, 1997, 1999, 2000, 2003, 2004 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify @@ -188,12 +188,13 @@ sh_dsp_reg_nums; #define arch_sh4al_dsp 0x0400 #define arch_sh4_nofpu 0x1000 #define arch_sh4a_nofpu 0x2000 +#define arch_sh4_nommu_nofpu 0x4000 /* no mmu nor fpu */ #define arch_sh1_up (arch_sh1 | arch_sh2_up) #define arch_sh2_up (arch_sh2 | arch_sh2e_up | arch_sh3_up | arch_sh_dsp) #define arch_sh2e_up (arch_sh2e | arch_sh3e_up) #define arch_sh3_up (arch_sh3 | arch_sh3e_up | arch_sh3_dsp_up \ - | arch_sh4_nofp_up) + | arch_sh4_nommu_nofpu_up) #define arch_sh3e_up (arch_sh3e | arch_sh4_up) #define arch_sh4_up (arch_sh4 | arch_sh4a_up) #define arch_sh4a_up (arch_sh4a) @@ -202,9 +203,14 @@ sh_dsp_reg_nums; #define arch_sh3_dsp_up (arch_sh3_dsp | arch_sh4al_dsp_up) #define arch_sh4al_dsp_up (arch_sh4al_dsp) +#define arch_sh4_nommu_nofpu_up (arch_sh4_nommu_nofpu | arch_sh4_nofp_up) + #define arch_sh4_nofp_up (arch_sh4_nofpu | arch_sh4_up | arch_sh4a_nofp_up) #define arch_sh4a_nofp_up (arch_sh4a_nofpu | arch_sh4a_up | arch_sh4al_dsp_up) +#define arch_sh_any_with_mmu (arch_sh3 | arch_sh3e_up | arch_sh3_dsp_up \ + | arch_sh4_nofp_up) /* arch _sh3_up omitting arch_sh4_nommu_nofpu */ + typedef struct { char *name; @@ -297,6 +303,8 @@ const sh_opcode_info sh_table[] = /* 0100nnnn00011110 ldc ,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh1_up}, +/* 0100nnnn00111010 ldc ,SGR */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}, + /* 0100nnnn00101110 ldc ,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh1_up}, /* 0100nnnn01011110 ldc ,MOD */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up}, @@ -309,7 +317,7 @@ const sh_opcode_info sh_table[] = /* 0100nnnn01001110 ldc ,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_up}, -/* 0100nnnn11111010 ldc ,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nofp_up}, +/* 0100nnnn11111010 ldc ,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}, /* 0100nnnn1xxx1110 ldc ,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_up}, @@ -319,6 +327,8 @@ const sh_opcode_info sh_table[] = /* 0100nnnn00100111 ldc.l @+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh1_up}, +/* 0100nnnn00110110 ldc.l @+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up}, + /* 0100nnnn01010111 ldc.l @+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up}, /* 0100nnnn01110111 ldc.l @+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up}, @@ -329,7 +339,7 @@ const sh_opcode_info sh_table[] = /* 0100nnnn01000111 ldc.l @+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_up}, -/* 0100nnnn11110110 ldc.l @+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nofp_up}, +/* 0100nnnn11110110 ldc.l @+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up}, /* 0100nnnn1xxx0111 ldc.l ,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_up}, @@ -384,7 +394,7 @@ const sh_opcode_info sh_table[] = /* 0100nnnn01100110 lds.l @+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}, -/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}, +/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh_any_with_mmu}, /* 0100nnnnmmmm1111 mac.w @+,@+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh1_up}, @@ -457,7 +467,7 @@ const sh_opcode_info sh_table[] = /* 11000001i8*2.... mov.w R0,@(,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh1_up}, /* 11000111i8p4.... mova @(,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh1_up}, -/* 0000nnnn11000011 movca.l R0,@ */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nofp_up}, +/* 0000nnnn11000011 movca.l R0,@ */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up}, /* 0000nnnn01110011 movco.l r0,@ */{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofp_up}, /* 0000mmmm01100011 movli.l @,r0 */{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofp_up}, @@ -482,11 +492,11 @@ const sh_opcode_info sh_table[] = /* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh1_up}, /* 0110nnnnmmmm0111 not , */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh1_up}, -/* 0000nnnn10010011 ocbi @ */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nofp_up}, +/* 0000nnnn10010011 ocbi @ */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up}, -/* 0000nnnn10100011 ocbp @ */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nofp_up}, +/* 0000nnnn10100011 ocbp @ */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up}, -/* 0000nnnn10110011 ocbwb @ */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nofp_up}, +/* 0000nnnn10110011 ocbwb @ */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up}, /* 11001011i8*1.... or #,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh1_up}, @@ -495,7 +505,7 @@ const sh_opcode_info sh_table[] = /* 11001111i8*1.... or.b #,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh1_up}, -/* 0000nnnn10000011 pref @ */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh4_nofp_up}, +/* 0000nnnn10000011 pref @ */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh4_nommu_nofpu_up}, /* 0000nnnn11010011 prefi @ */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofp_up}, @@ -567,9 +577,9 @@ const sh_opcode_info sh_table[] = /* 0000nnnn01000010 stc SPC, */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_up}, -/* 0000nnnn00111010 stc SGR, */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nofp_up}, +/* 0000nnnn00111010 stc SGR, */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}, -/* 0000nnnn11111010 stc DBR, */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nofp_up}, +/* 0000nnnn11111010 stc DBR, */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}, /* 0000nnnn1xxx0010 stc Rn_BANK, */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_up}, @@ -589,9 +599,9 @@ const sh_opcode_info sh_table[] = /* 0100nnnn00010011 stc.l GBR,@- */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh1_up}, -/* 0100nnnn00110010 stc.l SGR,@- */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nofp_up}, +/* 0100nnnn00110010 stc.l SGR,@- */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}, -/* 0100nnnn11110010 stc.l DBR,@- */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nofp_up}, +/* 0100nnnn11110010 stc.l DBR,@- */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}, /* 0100nnnn1xxx0011 stc.l Rn_BANK,@- */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_up}, diff --git a/sim/frv/ChangeLog b/sim/frv/ChangeLog index 68b33ec1b09..5c7c51ddd5a 100644 --- a/sim/frv/ChangeLog +++ b/sim/frv/ChangeLog @@ -1,3 +1,57 @@ +2004-03-01 Richard Sandiford + + * Makefile.in (SIM_OBJS): Add profile-fr450.o. + (profile-fr450.o): New dependency. + (stamp-cpu): Add fr450 to the list of machs. + * sim-frv.h (SPR_IS_ACC): New macro. + (H_SPR_ACC4, H_SPR_ACC63, H_SPR_ACCG4, H_SPR_ACCG63): Delete. + * cache.c (frv_cache_init, non_cache_access): Handle bfd_mach_fr450. + * frv.c (check_register_alignment, check_fr_register_alignment) + (check_memory_alignment, do_media_average): Likewise. + (frvbf_clear_accumulators): Likewise. Use a mask of valid registers + rather than a consecutive range. + * interrupts.c (frv_queue_illegal_instruction_interrupt) + (frv_queue_non_implemented_instruction_interrupt): Handle + bfd_mach_fr450. + * memory.c (check_data_read_address, check_readwrite_address) + (check_insn_read_address, check_write_address): Likewise. + * mloop.in (@cpu@_simulate_insn_prefetch): Likewise. + * profile.c (reset_gr_flags, reset_fr_flags, reset_acc_flags) + (frvbf_model_insn_before, frvbf_model_insn_after): Likewise. + * profile-fr450.c: New file. + * registers.c (fr450_spr): New array. + (frv_register_control_init): Check its size. Use it for fr450. + (frv_check_register_access): Handle bfd_mach_fr450. + (frv_check_spr_read_access): Likewise. Generalize accumulator check. + * traps.c (frv_core_signal, frvbf_media_cr_not_aligned): Likewise. + (frvbf_media_acc_not_aligned): Likewise. + (frvbf_media_register_not_aligned): Likewise. + * arch.c: Regenerate. + * arch.h: Regenerate. + * cpu.h: Regenerate. + * cpuall.h: Regenerate. + * decode.h: Regenerate. + * model.c: Regenerate. + +2004-03-01 Richard Sandiford + + * cache.c (frv_cache_init): Change fr400 cache statistics to match + the fr405. + (non_cache_access): Add missing breaks. + * interrupts.c (set_exception_status_registers): Always set EAR15 + for data_access_errors. + * memory.c (fr400_check_write_address): Remove redundant alignment + check. + * model.c: Regenerate. + +2004-03-01 Richard Sandiford + + * frv.c (frvbf_iacc_cut): Rework, taking rounding into account. + +2004-03-01 Richard Sandiford + + * decode.c, decode.h, model.c, sem.c: Regenerate. + 2003-11-24 Kevin Buettner * frv-sim.h (GR_REGNUM_MAX, FR_REGNUM_MAX, PC_REGNUM, SPR_REGNUM_MIN) diff --git a/sim/frv/Makefile.in b/sim/frv/Makefile.in index adc11caa962..c2bcb36e7c4 100644 --- a/sim/frv/Makefile.in +++ b/sim/frv/Makefile.in @@ -35,7 +35,7 @@ SIM_OBJS = \ sim-if.o arch.o \ $(FRV_OBJS) \ traps.o interrupts.o memory.o cache.o pipeline.o \ - profile.o profile-fr400.o profile-fr500.o profile-fr550.o options.o \ + profile.o profile-fr400.o profile-fr450.o profile-fr500.o profile-fr550.o options.o \ devices.o reset.o registers.o \ $(CONFIG_DEVICES) @@ -80,6 +80,7 @@ reset.o: reset.c $(FRVBF_INCLUDE_DEPS) registers.o: registers.c $(FRVBF_INCLUDE_DEPS) profile.o: profile.c profile-fr400.h profile-fr500.h profile-fr550.h $(FRVBF_INCLUDE_DEPS) profile-fr400.o: profile-fr400.c profile-fr400.h $(FRVBF_INCLUDE_DEPS) +profile-fr450.o: profile-fr450.c $(FRVBF_INCLUDE_DEPS) profile-fr500.o: profile-fr500.c profile-fr500.h $(FRVBF_INCLUDE_DEPS) profile-fr550.o: profile-fr550.c profile-fr550.h $(FRVBF_INCLUDE_DEPS) sim-if.o: sim-if.c $(FRVBF_INCLUDE_DEPS) $(srcdir)/../common/sim-core.h eng.h @@ -121,7 +122,7 @@ arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(srcdir)/../../cpu/frv.cpu $(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \ - cpu=frvbf mach=frv,fr550,fr500,fr400,tomcat,simple SUFFIX= \ + cpu=frvbf mach=frv,fr550,fr500,fr450,fr400,tomcat,simple SUFFIX= \ archfile=$(srcdir)/../../cpu/frv.cpu \ FLAGS="with-scache with-profile=fn with-generic-write with-parallel-only" \ EXTRAFILES="$(CGEN_CPU_SEM)" diff --git a/sim/frv/arch.c b/sim/frv/arch.c index d0ac82f8dd3..de377bd5ac3 100644 --- a/sim/frv/arch.c +++ b/sim/frv/arch.c @@ -42,6 +42,9 @@ const MACH *sim_machs[] = #ifdef HAVE_CPU_FRVBF & fr400_mach, #endif +#ifdef HAVE_CPU_FRVBF + & fr450_mach, +#endif #ifdef HAVE_CPU_FRVBF & simple_mach, #endif diff --git a/sim/frv/arch.h b/sim/frv/arch.h index 6f26965b4d2..1d8820193a3 100644 --- a/sim/frv/arch.h +++ b/sim/frv/arch.h @@ -30,7 +30,7 @@ with this program; if not, write to the Free Software Foundation, Inc., /* Enum declaration for model types. */ typedef enum model_type { MODEL_FRV, MODEL_FR550, MODEL_FR500, MODEL_TOMCAT - , MODEL_FR400, MODEL_SIMPLE, MODEL_MAX + , MODEL_FR400, MODEL_FR450, MODEL_SIMPLE, MODEL_MAX } MODEL_TYPE; #define MAX_MODELS ((int) MODEL_MAX) @@ -74,7 +74,19 @@ typedef enum unit_type { , UNIT_FR400_U_SWAP, UNIT_FR400_U_FR_STORE, UNIT_FR400_U_FR_LOAD, UNIT_FR400_U_GR_STORE , UNIT_FR400_U_GR_LOAD, UNIT_FR400_U_SET_HILO, UNIT_FR400_U_CHECK, UNIT_FR400_U_TRAP , UNIT_FR400_U_BRANCH, UNIT_FR400_U_IDIV, UNIT_FR400_U_IMUL, UNIT_FR400_U_INTEGER - , UNIT_FR400_U_EXEC, UNIT_SIMPLE_U_EXEC, UNIT_MAX + , UNIT_FR400_U_EXEC, UNIT_FR450_U_DCUL, UNIT_FR450_U_ICUL, UNIT_FR450_U_DCPL + , UNIT_FR450_U_ICPL, UNIT_FR450_U_DCF, UNIT_FR450_U_DCI, UNIT_FR450_U_ICI + , UNIT_FR450_U_MEMBAR, UNIT_FR450_U_BARRIER, UNIT_FR450_U_MEDIA_DUAL_HTOB, UNIT_FR450_U_MEDIA_DUAL_EXPAND + , UNIT_FR450_U_MEDIA_7, UNIT_FR450_U_MEDIA_6, UNIT_FR450_U_MEDIA_4_MCLRACCA, UNIT_FR450_U_MEDIA_4_ACC_DUAL + , UNIT_FR450_U_MEDIA_4_ACCG, UNIT_FR450_U_MEDIA_4, UNIT_FR450_U_MEDIA_3_QUAD, UNIT_FR450_U_MEDIA_3_DUAL + , UNIT_FR450_U_MEDIA_3, UNIT_FR450_U_MEDIA_2_ADD_SUB_DUAL, UNIT_FR450_U_MEDIA_2_ADD_SUB, UNIT_FR450_U_MEDIA_2_ACC_DUAL + , UNIT_FR450_U_MEDIA_2_ACC, UNIT_FR450_U_MEDIA_2_QUAD, UNIT_FR450_U_MEDIA_2, UNIT_FR450_U_MEDIA_HILO + , UNIT_FR450_U_MEDIA_1_QUAD, UNIT_FR450_U_MEDIA_1, UNIT_FR450_U_GR2SPR, UNIT_FR450_U_GR2FR + , UNIT_FR450_U_SPR2GR, UNIT_FR450_U_FR2GR, UNIT_FR450_U_SWAP, UNIT_FR450_U_FR_STORE + , UNIT_FR450_U_FR_LOAD, UNIT_FR450_U_GR_STORE, UNIT_FR450_U_GR_LOAD, UNIT_FR450_U_SET_HILO + , UNIT_FR450_U_CHECK, UNIT_FR450_U_TRAP, UNIT_FR450_U_BRANCH, UNIT_FR450_U_IDIV + , UNIT_FR450_U_IMUL, UNIT_FR450_U_INTEGER, UNIT_FR450_U_EXEC, UNIT_SIMPLE_U_EXEC + , UNIT_MAX } UNIT_TYPE; #define MAX_UNITS (1) diff --git a/sim/frv/cache.c b/sim/frv/cache.c index 7b2635b6d26..060568225ab 100644 --- a/sim/frv/cache.c +++ b/sim/frv/cache.c @@ -38,8 +38,9 @@ frv_cache_init (SIM_CPU *cpu, FRV_CACHE *cache) switch (STATE_ARCHITECTURE (sd)->mach) { case bfd_mach_fr400: + case bfd_mach_fr450: if (cache->configured_sets == 0) - cache->configured_sets = 128; + cache->configured_sets = 512; if (cache->configured_ways == 0) cache->configured_ways = 2; if (cache->line_size == 0) @@ -205,9 +206,11 @@ non_cache_access (FRV_CACHE *cache, USI address) switch (STATE_ARCHITECTURE (sd)->mach) { case bfd_mach_fr400: + case bfd_mach_fr450: if (address >= 0xff000000 || address >= 0xfe000000 && address <= 0xfeffffff) return 1; /* non-cache access */ + break; case bfd_mach_fr550: if (address >= 0xff000000 || address >= 0xfeff0000 && address <= 0xfeffffff) @@ -219,6 +222,7 @@ non_cache_access (FRV_CACHE *cache, USI address) } else if (address >= 0xfe400000 && address <= 0xfe407fff) return 1; /* non-cache access */ + break; default: if (address >= 0xff000000 || address >= 0xfeff0000 && address <= 0xfeffffff) @@ -230,6 +234,7 @@ non_cache_access (FRV_CACHE *cache, USI address) } else if (address >= 0xfe400000 && address <= 0xfe403fff) return 1; /* non-cache access */ + break; } hsr0 = GET_HSR0 (); diff --git a/sim/frv/cpu.h b/sim/frv/cpu.h index 6325368dfe8..62572673656 100644 --- a/sim/frv/cpu.h +++ b/sim/frv/cpu.h @@ -397,6 +397,19 @@ typedef struct { DI cur_acc_p4; } MODEL_FR400_DATA; +typedef struct { + DI prev_fp_load; + DI prev_fr_p4; + DI prev_fr_p6; + DI prev_acc_p2; + DI prev_acc_p4; + DI cur_fp_load; + DI cur_fr_p4; + DI cur_fr_p6; + DI cur_acc_p2; + DI cur_acc_p4; +} MODEL_FR450_DATA; + typedef struct { int empty; } MODEL_SIMPLE_DATA; @@ -1261,6 +1274,23 @@ union sem_fields { unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0; unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0; } sfmt_cmaddhss; + struct { /* */ + UINT f_FRi; + UINT f_FRk; + UINT f_u6; + unsigned char in_FRintieven; + unsigned char in_FRintkeven; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0; + unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0; + unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1; + unsigned char out_FRintieven; + unsigned char out_FRintkeven; + unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0; + unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_1; + unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0; + unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_1; + } sfmt_mqsllhi; struct { /* */ UINT f_FRi; UINT f_FRj; @@ -3149,6 +3179,50 @@ struct scache { f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ f_GRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ +#define EXTRACT_IFMT_LRAI_VARS \ + UINT f_pack; \ + UINT f_GRk; \ + UINT f_op; \ + UINT f_GRi; \ + UINT f_ope1; \ + UINT f_LRAE; \ + UINT f_LRAD; \ + UINT f_LRAS; \ + UINT f_LRA_null; \ + unsigned int length; +#define EXTRACT_IFMT_LRAI_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_LRAE = EXTRACT_LSB0_UINT (insn, 32, 5, 1); \ + f_LRAD = EXTRACT_LSB0_UINT (insn, 32, 4, 1); \ + f_LRAS = EXTRACT_LSB0_UINT (insn, 32, 3, 1); \ + f_LRA_null = EXTRACT_LSB0_UINT (insn, 32, 2, 3); \ + +#define EXTRACT_IFMT_TLBPR_VARS \ + UINT f_pack; \ + UINT f_TLBPR_null; \ + UINT f_TLBPRopx; \ + UINT f_TLBPRL; \ + UINT f_op; \ + UINT f_GRi; \ + UINT f_ope1; \ + UINT f_GRj; \ + unsigned int length; +#define EXTRACT_IFMT_TLBPR_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_TLBPR_null = EXTRACT_LSB0_UINT (insn, 32, 30, 2); \ + f_TLBPRopx = EXTRACT_LSB0_UINT (insn, 32, 28, 3); \ + f_TLBPRL = EXTRACT_LSB0_UINT (insn, 32, 25, 1); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + #define EXTRACT_IFMT_COP1_VARS \ UINT f_pack; \ UINT f_CPRk; \ @@ -3836,6 +3910,23 @@ struct scache { f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \ f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ +#define EXTRACT_IFMT_MQSLLHI_VARS \ + UINT f_pack; \ + UINT f_FRk; \ + UINT f_op; \ + UINT f_FRi; \ + UINT f_ope1; \ + UINT f_u6; \ + unsigned int length; +#define EXTRACT_IFMT_MQSLLHI_CODE \ + length = 4; \ + f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \ + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \ + f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \ + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \ + f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \ + f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \ + #define EXTRACT_IFMT_MADDACCS_VARS \ UINT f_pack; \ UINT f_ACC40Sk; \ diff --git a/sim/frv/cpuall.h b/sim/frv/cpuall.h index 4d1cb6830f4..44b52b315a7 100644 --- a/sim/frv/cpuall.h +++ b/sim/frv/cpuall.h @@ -39,6 +39,7 @@ extern const MACH fr550_mach; extern const MACH fr500_mach; extern const MACH tomcat_mach; extern const MACH fr400_mach; +extern const MACH fr450_mach; extern const MACH simple_mach; #ifndef WANT_CPU diff --git a/sim/frv/decode.c b/sim/frv/decode.c index ef6be5ad614..620cbdfc766 100644 --- a/sim/frv/decode.c +++ b/sim/frv/decode.c @@ -223,22 +223,12 @@ static const struct insn_sem frvbf_insn_sem[] = { FRV_INSN_STHF, FRVBF_INSN_STHF, FRVBF_SFMT_STBF }, { FRV_INSN_STF, FRVBF_INSN_STF, FRVBF_SFMT_STBF }, { FRV_INSN_STC, FRVBF_INSN_STC, FRVBF_SFMT_STC }, - { FRV_INSN_RSTB, FRVBF_INSN_RSTB, FRVBF_SFMT_RSTB }, - { FRV_INSN_RSTH, FRVBF_INSN_RSTH, FRVBF_SFMT_RSTB }, - { FRV_INSN_RST, FRVBF_INSN_RST, FRVBF_SFMT_RSTB }, - { FRV_INSN_RSTBF, FRVBF_INSN_RSTBF, FRVBF_SFMT_RSTBF }, - { FRV_INSN_RSTHF, FRVBF_INSN_RSTHF, FRVBF_SFMT_RSTBF }, - { FRV_INSN_RSTF, FRVBF_INSN_RSTF, FRVBF_SFMT_RSTBF }, { FRV_INSN_STD, FRVBF_INSN_STD, FRVBF_SFMT_STD }, { FRV_INSN_STDF, FRVBF_INSN_STDF, FRVBF_SFMT_STDF }, { FRV_INSN_STDC, FRVBF_INSN_STDC, FRVBF_SFMT_STDC }, - { FRV_INSN_RSTD, FRVBF_INSN_RSTD, FRVBF_SFMT_RSTD }, - { FRV_INSN_RSTDF, FRVBF_INSN_RSTDF, FRVBF_SFMT_RSTDF }, { FRV_INSN_STQ, FRVBF_INSN_STQ, FRVBF_SFMT_LDQ }, { FRV_INSN_STQF, FRVBF_INSN_STQF, FRVBF_SFMT_LDQF }, { FRV_INSN_STQC, FRVBF_INSN_STQC, FRVBF_SFMT_LDQC }, - { FRV_INSN_RSTQ, FRVBF_INSN_RSTQ, FRVBF_SFMT_LDQ }, - { FRV_INSN_RSTQF, FRVBF_INSN_RSTQF, FRVBF_SFMT_LDQF }, { FRV_INSN_STBU, FRVBF_INSN_STBU, FRVBF_SFMT_STBU }, { FRV_INSN_STHU, FRVBF_INSN_STHU, FRVBF_SFMT_STBU }, { FRV_INSN_STU, FRVBF_INSN_STU, FRVBF_SFMT_STBU }, @@ -578,6 +568,9 @@ static const struct insn_sem frvbf_insn_sem[] = { FRV_INSN_DCUL, FRVBF_INSN_DCUL, FRVBF_SFMT_ICUL }, { FRV_INSN_BAR, FRVBF_INSN_BAR, FRVBF_SFMT_REI }, { FRV_INSN_MEMBAR, FRVBF_INSN_MEMBAR, FRVBF_SFMT_REI }, + { FRV_INSN_LRAI, FRVBF_INSN_LRAI, FRVBF_SFMT_REI }, + { FRV_INSN_LRAD, FRVBF_INSN_LRAD, FRVBF_SFMT_REI }, + { FRV_INSN_TLBPR, FRVBF_INSN_TLBPR, FRVBF_SFMT_REI }, { FRV_INSN_COP1, FRVBF_INSN_COP1, FRVBF_SFMT_REI }, { FRV_INSN_COP2, FRVBF_INSN_COP2, FRVBF_SFMT_REI }, { FRV_INSN_CLRGR, FRVBF_INSN_CLRGR, FRVBF_SFMT_CLRGR }, @@ -725,6 +718,10 @@ static const struct insn_sem frvbf_insn_sem[] = { FRV_INSN_CMQADDHUS, FRVBF_INSN_CMQADDHUS, FRVBF_SFMT_CMQADDHSS }, { FRV_INSN_CMQSUBHSS, FRVBF_INSN_CMQSUBHSS, FRVBF_SFMT_CMQADDHSS }, { FRV_INSN_CMQSUBHUS, FRVBF_INSN_CMQSUBHUS, FRVBF_SFMT_CMQADDHSS }, + { FRV_INSN_MQLCLRHS, FRVBF_INSN_MQLCLRHS, FRVBF_SFMT_MQSATHS }, + { FRV_INSN_MQLMTHS, FRVBF_INSN_MQLMTHS, FRVBF_SFMT_MQSATHS }, + { FRV_INSN_MQSLLHI, FRVBF_INSN_MQSLLHI, FRVBF_SFMT_MQSLLHI }, + { FRV_INSN_MQSRAHI, FRVBF_INSN_MQSRAHI, FRVBF_SFMT_MQSLLHI }, { FRV_INSN_MADDACCS, FRVBF_INSN_MADDACCS, FRVBF_SFMT_MADDACCS }, { FRV_INSN_MSUBACCS, FRVBF_INSN_MSUBACCS, FRVBF_SFMT_MADDACCS }, { FRV_INSN_MDADDACCS, FRVBF_INSN_MDADDACCS, FRVBF_SFMT_MDADDACCS }, @@ -1014,19 +1011,12 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, case 26 : itype = FRVBF_INSN_STFU; goto extract_sfmt_stbfu; case 27 : itype = FRVBF_INSN_STDFU; goto extract_sfmt_stdfu; case 28 : itype = FRVBF_INSN_STQFU; goto extract_sfmt_ldqfu; - case 32 : itype = FRVBF_INSN_RSTB; goto extract_sfmt_rstb; - case 33 : itype = FRVBF_INSN_RSTH; goto extract_sfmt_rstb; - case 34 : itype = FRVBF_INSN_RST; goto extract_sfmt_rstb; - case 35 : itype = FRVBF_INSN_RSTD; goto extract_sfmt_rstd; - case 36 : itype = FRVBF_INSN_RSTQ; goto extract_sfmt_ldq; + case 32 : itype = FRVBF_INSN_LRAI; goto extract_sfmt_rei; + case 33 : itype = FRVBF_INSN_LRAD; goto extract_sfmt_rei; + case 36 : itype = FRVBF_INSN_TLBPR; goto extract_sfmt_rei; case 37 : itype = FRVBF_INSN_STC; goto extract_sfmt_stc; case 38 : itype = FRVBF_INSN_STDC; goto extract_sfmt_stdc; case 39 : itype = FRVBF_INSN_STQC; goto extract_sfmt_ldqc; - case 40 : itype = FRVBF_INSN_RSTBF; goto extract_sfmt_rstbf; - case 41 : itype = FRVBF_INSN_RSTHF; goto extract_sfmt_rstbf; - case 42 : itype = FRVBF_INSN_RSTF; goto extract_sfmt_rstbf; - case 43 : itype = FRVBF_INSN_RSTDF; goto extract_sfmt_rstdf; - case 44 : itype = FRVBF_INSN_RSTQF; goto extract_sfmt_ldqf; case 45 : itype = FRVBF_INSN_STCU; goto extract_sfmt_stcu; case 46 : itype = FRVBF_INSN_STDCU; goto extract_sfmt_stdcu; case 47 : itype = FRVBF_INSN_STQCU; goto extract_sfmt_ldqcu; @@ -1858,7 +1848,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, } case 120 : { - unsigned int val = (((insn >> 7) & (1 << 4)) | ((insn >> 6) & (15 << 0))); + unsigned int val = (((insn >> 6) & (63 << 0))); switch (val) { case 0 : itype = FRVBF_INSN_MQXMACHS; goto extract_sfmt_mqmachs; @@ -1876,12 +1866,16 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, case 13 : itype = FRVBF_INSN_MCPLI; goto extract_sfmt_mcpli; case 14 : itype = FRVBF_INSN_MDCUTSSI; goto extract_sfmt_mdcutssi; case 15 : itype = FRVBF_INSN_MQSATHS; goto extract_sfmt_mqsaths; - case 16 : itype = FRVBF_INSN_MHSETLOS; goto extract_sfmt_mhsetlos; - case 17 : itype = FRVBF_INSN_MHSETLOH; goto extract_sfmt_mhsetloh; - case 18 : itype = FRVBF_INSN_MHSETHIS; goto extract_sfmt_mhsethis; - case 19 : itype = FRVBF_INSN_MHSETHIH; goto extract_sfmt_mhsethih; - case 20 : itype = FRVBF_INSN_MHDSETS; goto extract_sfmt_mhdsets; - case 21 : itype = FRVBF_INSN_MHDSETH; goto extract_sfmt_mhdseth; + case 16 : itype = FRVBF_INSN_MQLCLRHS; goto extract_sfmt_mqsaths; + case 17 : itype = FRVBF_INSN_MQSLLHI; goto extract_sfmt_mqsllhi; + case 19 : itype = FRVBF_INSN_MQSRAHI; goto extract_sfmt_mqsllhi; + case 20 : itype = FRVBF_INSN_MQLMTHS; goto extract_sfmt_mqsaths; + case 32 : itype = FRVBF_INSN_MHSETLOS; goto extract_sfmt_mhsetlos; + case 33 : itype = FRVBF_INSN_MHSETLOH; goto extract_sfmt_mhsetloh; + case 34 : itype = FRVBF_INSN_MHSETHIS; goto extract_sfmt_mhsethis; + case 35 : itype = FRVBF_INSN_MHSETHIH; goto extract_sfmt_mhsethih; + case 36 : itype = FRVBF_INSN_MHDSETS; goto extract_sfmt_mhdsets; + case 37 : itype = FRVBF_INSN_MHDSETH; goto extract_sfmt_mhdseth; default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty; } } @@ -4613,70 +4607,6 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, FLD (in_GRj) = f_GRj; } #endif -#undef FLD - return idesc; - } - - extract_sfmt_rstb: - { - const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_cswap.f - UINT f_GRk; - UINT f_GRi; - UINT f_GRj; - - f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); - f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); - f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); - - /* Record the fields for the semantic handler. */ - FLD (f_GRi) = f_GRi; - FLD (f_GRj) = f_GRj; - FLD (f_GRk) = f_GRk; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rstb", "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, "f_GRk 0x%x", 'x', f_GRk, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_GRi) = f_GRi; - FLD (in_GRj) = f_GRj; - FLD (in_GRk) = f_GRk; - } -#endif -#undef FLD - return idesc; - } - - extract_sfmt_rstbf: - { - const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_cstbfu.f - UINT f_FRk; - UINT f_GRi; - UINT f_GRj; - - f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); - f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); - f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); - - /* Record the fields for the semantic handler. */ - FLD (f_FRk) = f_FRk; - FLD (f_GRi) = f_GRi; - FLD (f_GRj) = f_GRj; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rstbf", "f_FRk 0x%x", 'x', f_FRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_FRintk) = f_FRk; - FLD (in_GRi) = f_GRi; - FLD (in_GRj) = f_GRj; - } -#endif #undef FLD return idesc; } @@ -4773,70 +4703,6 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, FLD (in_GRj) = f_GRj; } #endif -#undef FLD - return idesc; - } - - extract_sfmt_rstd: - { - const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_cstdu.f - UINT f_GRk; - UINT f_GRi; - UINT f_GRj; - - f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); - f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); - f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); - - /* Record the fields for the semantic handler. */ - FLD (f_GRk) = f_GRk; - FLD (f_GRi) = f_GRi; - FLD (f_GRj) = f_GRj; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rstd", "f_GRk 0x%x", 'x', f_GRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_GRdoublek) = f_GRk; - FLD (in_GRi) = f_GRi; - FLD (in_GRj) = f_GRj; - } -#endif -#undef FLD - return idesc; - } - - extract_sfmt_rstdf: - { - const IDESC *idesc = &frvbf_insn_data[itype]; - CGEN_INSN_INT insn = entire_insn; -#define FLD(f) abuf->fields.sfmt_cstdfu.f - UINT f_FRk; - UINT f_GRi; - UINT f_GRj; - - f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); - f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); - f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); - - /* Record the fields for the semantic handler. */ - FLD (f_FRk) = f_FRk; - FLD (f_GRi) = f_GRi; - FLD (f_GRj) = f_GRj; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rstdf", "f_FRk 0x%x", 'x', f_FRk, "f_GRi 0x%x", 'x', f_GRi, "f_GRj 0x%x", 'x', f_GRj, (char *) 0)); - -#if WITH_PROFILE_MODEL_P - /* Record the fields for profiling. */ - if (PROFILE_MODEL_P (current_cpu)) - { - FLD (in_FRdoublek) = f_FRk; - FLD (in_GRi) = f_GRi; - FLD (in_GRj) = f_GRj; - } -#endif #undef FLD return idesc; } @@ -9603,6 +9469,47 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc, FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1)); } #endif +#undef FLD + return idesc; + } + + extract_sfmt_mqsllhi: + { + const IDESC *idesc = &frvbf_insn_data[itype]; + CGEN_INSN_INT insn = entire_insn; +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + UINT f_FRk; + UINT f_FRi; + UINT f_u6; + + f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); + f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); + f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6); + + /* Record the fields for the semantic handler. */ + FLD (f_FRi) = f_FRi; + FLD (f_FRk) = f_FRk; + FLD (f_u6) = f_u6; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mqsllhi", "f_FRi 0x%x", 'x', f_FRi, "f_FRk 0x%x", 'x', f_FRk, "f_u6 0x%x", 'x', f_u6, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + FLD (in_FRintieven) = f_FRi; + FLD (in_FRintkeven) = f_FRk; + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0)); + FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1)); + FLD (out_FRintieven) = f_FRi; + FLD (out_FRintkeven) = f_FRk; + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0)); + FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1)); + } +#endif #undef FLD return idesc; } diff --git a/sim/frv/decode.h b/sim/frv/decode.h index 9741d366092..e1f1cd4bea3 100644 --- a/sim/frv/decode.h +++ b/sim/frv/decode.h @@ -79,150 +79,149 @@ typedef enum frvbf_insn_type { , FRVBF_INSN_NLDFI, FRVBF_INSN_LDDI, FRVBF_INSN_LDDFI, FRVBF_INSN_NLDDI , FRVBF_INSN_NLDDFI, FRVBF_INSN_LDQI, FRVBF_INSN_LDQFI, FRVBF_INSN_NLDQFI , FRVBF_INSN_STB, FRVBF_INSN_STH, FRVBF_INSN_ST, FRVBF_INSN_STBF - , FRVBF_INSN_STHF, FRVBF_INSN_STF, FRVBF_INSN_STC, FRVBF_INSN_RSTB - , FRVBF_INSN_RSTH, FRVBF_INSN_RST, FRVBF_INSN_RSTBF, FRVBF_INSN_RSTHF - , FRVBF_INSN_RSTF, FRVBF_INSN_STD, FRVBF_INSN_STDF, FRVBF_INSN_STDC - , FRVBF_INSN_RSTD, FRVBF_INSN_RSTDF, FRVBF_INSN_STQ, FRVBF_INSN_STQF - , FRVBF_INSN_STQC, FRVBF_INSN_RSTQ, FRVBF_INSN_RSTQF, FRVBF_INSN_STBU - , FRVBF_INSN_STHU, FRVBF_INSN_STU, FRVBF_INSN_STBFU, FRVBF_INSN_STHFU - , FRVBF_INSN_STFU, FRVBF_INSN_STCU, FRVBF_INSN_STDU, FRVBF_INSN_STDFU - , FRVBF_INSN_STDCU, FRVBF_INSN_STQU, FRVBF_INSN_STQFU, FRVBF_INSN_STQCU - , FRVBF_INSN_CLDSB, FRVBF_INSN_CLDUB, FRVBF_INSN_CLDSH, FRVBF_INSN_CLDUH - , FRVBF_INSN_CLD, FRVBF_INSN_CLDBF, FRVBF_INSN_CLDHF, FRVBF_INSN_CLDF - , FRVBF_INSN_CLDD, FRVBF_INSN_CLDDF, FRVBF_INSN_CLDQ, FRVBF_INSN_CLDSBU - , FRVBF_INSN_CLDUBU, FRVBF_INSN_CLDSHU, FRVBF_INSN_CLDUHU, FRVBF_INSN_CLDU - , FRVBF_INSN_CLDBFU, FRVBF_INSN_CLDHFU, FRVBF_INSN_CLDFU, FRVBF_INSN_CLDDU - , FRVBF_INSN_CLDDFU, FRVBF_INSN_CLDQU, FRVBF_INSN_CSTB, FRVBF_INSN_CSTH - , FRVBF_INSN_CST, FRVBF_INSN_CSTBF, FRVBF_INSN_CSTHF, FRVBF_INSN_CSTF - , FRVBF_INSN_CSTD, FRVBF_INSN_CSTDF, FRVBF_INSN_CSTQ, FRVBF_INSN_CSTBU - , FRVBF_INSN_CSTHU, FRVBF_INSN_CSTU, FRVBF_INSN_CSTBFU, FRVBF_INSN_CSTHFU - , FRVBF_INSN_CSTFU, FRVBF_INSN_CSTDU, FRVBF_INSN_CSTDFU, FRVBF_INSN_STBI - , FRVBF_INSN_STHI, FRVBF_INSN_STI, FRVBF_INSN_STBFI, FRVBF_INSN_STHFI - , FRVBF_INSN_STFI, FRVBF_INSN_STDI, FRVBF_INSN_STDFI, FRVBF_INSN_STQI - , FRVBF_INSN_STQFI, FRVBF_INSN_SWAP, FRVBF_INSN_SWAPI, FRVBF_INSN_CSWAP - , FRVBF_INSN_MOVGF, FRVBF_INSN_MOVFG, FRVBF_INSN_MOVGFD, FRVBF_INSN_MOVFGD - , FRVBF_INSN_MOVGFQ, FRVBF_INSN_MOVFGQ, FRVBF_INSN_CMOVGF, FRVBF_INSN_CMOVFG - , FRVBF_INSN_CMOVGFD, FRVBF_INSN_CMOVFGD, FRVBF_INSN_MOVGS, FRVBF_INSN_MOVSG - , FRVBF_INSN_BRA, FRVBF_INSN_BNO, FRVBF_INSN_BEQ, FRVBF_INSN_BNE - , FRVBF_INSN_BLE, FRVBF_INSN_BGT, FRVBF_INSN_BLT, FRVBF_INSN_BGE - , FRVBF_INSN_BLS, FRVBF_INSN_BHI, FRVBF_INSN_BC, FRVBF_INSN_BNC - , FRVBF_INSN_BN, FRVBF_INSN_BP, FRVBF_INSN_BV, FRVBF_INSN_BNV - , FRVBF_INSN_FBRA, FRVBF_INSN_FBNO, FRVBF_INSN_FBNE, FRVBF_INSN_FBEQ - , FRVBF_INSN_FBLG, FRVBF_INSN_FBUE, FRVBF_INSN_FBUL, FRVBF_INSN_FBGE - , FRVBF_INSN_FBLT, FRVBF_INSN_FBUGE, FRVBF_INSN_FBUG, FRVBF_INSN_FBLE - , FRVBF_INSN_FBGT, FRVBF_INSN_FBULE, FRVBF_INSN_FBU, FRVBF_INSN_FBO - , FRVBF_INSN_BCTRLR, FRVBF_INSN_BRALR, FRVBF_INSN_BNOLR, FRVBF_INSN_BEQLR - , FRVBF_INSN_BNELR, FRVBF_INSN_BLELR, FRVBF_INSN_BGTLR, FRVBF_INSN_BLTLR - , FRVBF_INSN_BGELR, FRVBF_INSN_BLSLR, FRVBF_INSN_BHILR, FRVBF_INSN_BCLR - , FRVBF_INSN_BNCLR, FRVBF_INSN_BNLR, FRVBF_INSN_BPLR, FRVBF_INSN_BVLR - , FRVBF_INSN_BNVLR, FRVBF_INSN_FBRALR, FRVBF_INSN_FBNOLR, FRVBF_INSN_FBEQLR - , FRVBF_INSN_FBNELR, FRVBF_INSN_FBLGLR, FRVBF_INSN_FBUELR, FRVBF_INSN_FBULLR - , FRVBF_INSN_FBGELR, FRVBF_INSN_FBLTLR, FRVBF_INSN_FBUGELR, FRVBF_INSN_FBUGLR - , FRVBF_INSN_FBLELR, FRVBF_INSN_FBGTLR, FRVBF_INSN_FBULELR, FRVBF_INSN_FBULR - , FRVBF_INSN_FBOLR, FRVBF_INSN_BCRALR, FRVBF_INSN_BCNOLR, FRVBF_INSN_BCEQLR - , FRVBF_INSN_BCNELR, FRVBF_INSN_BCLELR, FRVBF_INSN_BCGTLR, FRVBF_INSN_BCLTLR - , FRVBF_INSN_BCGELR, FRVBF_INSN_BCLSLR, FRVBF_INSN_BCHILR, FRVBF_INSN_BCCLR - , FRVBF_INSN_BCNCLR, FRVBF_INSN_BCNLR, FRVBF_INSN_BCPLR, FRVBF_INSN_BCVLR - , FRVBF_INSN_BCNVLR, FRVBF_INSN_FCBRALR, FRVBF_INSN_FCBNOLR, FRVBF_INSN_FCBEQLR - , FRVBF_INSN_FCBNELR, FRVBF_INSN_FCBLGLR, FRVBF_INSN_FCBUELR, FRVBF_INSN_FCBULLR - , FRVBF_INSN_FCBGELR, FRVBF_INSN_FCBLTLR, FRVBF_INSN_FCBUGELR, FRVBF_INSN_FCBUGLR - , FRVBF_INSN_FCBLELR, FRVBF_INSN_FCBGTLR, FRVBF_INSN_FCBULELR, FRVBF_INSN_FCBULR - , FRVBF_INSN_FCBOLR, FRVBF_INSN_JMPL, FRVBF_INSN_CALLL, FRVBF_INSN_JMPIL - , FRVBF_INSN_CALLIL, FRVBF_INSN_CALL, FRVBF_INSN_RETT, FRVBF_INSN_REI - , FRVBF_INSN_TRA, FRVBF_INSN_TNO, FRVBF_INSN_TEQ, FRVBF_INSN_TNE - , FRVBF_INSN_TLE, FRVBF_INSN_TGT, FRVBF_INSN_TLT, FRVBF_INSN_TGE - , FRVBF_INSN_TLS, FRVBF_INSN_THI, FRVBF_INSN_TC, FRVBF_INSN_TNC - , FRVBF_INSN_TN, FRVBF_INSN_TP, FRVBF_INSN_TV, FRVBF_INSN_TNV - , FRVBF_INSN_FTRA, FRVBF_INSN_FTNO, FRVBF_INSN_FTNE, FRVBF_INSN_FTEQ - , FRVBF_INSN_FTLG, FRVBF_INSN_FTUE, FRVBF_INSN_FTUL, FRVBF_INSN_FTGE - , FRVBF_INSN_FTLT, FRVBF_INSN_FTUGE, FRVBF_INSN_FTUG, FRVBF_INSN_FTLE - , FRVBF_INSN_FTGT, FRVBF_INSN_FTULE, FRVBF_INSN_FTU, FRVBF_INSN_FTO - , FRVBF_INSN_TIRA, FRVBF_INSN_TINO, FRVBF_INSN_TIEQ, FRVBF_INSN_TINE - , FRVBF_INSN_TILE, FRVBF_INSN_TIGT, FRVBF_INSN_TILT, FRVBF_INSN_TIGE - , FRVBF_INSN_TILS, FRVBF_INSN_TIHI, FRVBF_INSN_TIC, FRVBF_INSN_TINC - , FRVBF_INSN_TIN, FRVBF_INSN_TIP, FRVBF_INSN_TIV, FRVBF_INSN_TINV - , FRVBF_INSN_FTIRA, FRVBF_INSN_FTINO, FRVBF_INSN_FTINE, FRVBF_INSN_FTIEQ - , FRVBF_INSN_FTILG, FRVBF_INSN_FTIUE, FRVBF_INSN_FTIUL, FRVBF_INSN_FTIGE - , FRVBF_INSN_FTILT, FRVBF_INSN_FTIUGE, FRVBF_INSN_FTIUG, FRVBF_INSN_FTILE - , FRVBF_INSN_FTIGT, FRVBF_INSN_FTIULE, FRVBF_INSN_FTIU, FRVBF_INSN_FTIO - , FRVBF_INSN_BREAK, FRVBF_INSN_MTRAP, FRVBF_INSN_ANDCR, FRVBF_INSN_ORCR - , FRVBF_INSN_XORCR, FRVBF_INSN_NANDCR, FRVBF_INSN_NORCR, FRVBF_INSN_ANDNCR - , FRVBF_INSN_ORNCR, FRVBF_INSN_NANDNCR, FRVBF_INSN_NORNCR, FRVBF_INSN_NOTCR - , FRVBF_INSN_CKRA, FRVBF_INSN_CKNO, FRVBF_INSN_CKEQ, FRVBF_INSN_CKNE - , FRVBF_INSN_CKLE, FRVBF_INSN_CKGT, FRVBF_INSN_CKLT, FRVBF_INSN_CKGE - , FRVBF_INSN_CKLS, FRVBF_INSN_CKHI, FRVBF_INSN_CKC, FRVBF_INSN_CKNC - , FRVBF_INSN_CKN, FRVBF_INSN_CKP, FRVBF_INSN_CKV, FRVBF_INSN_CKNV - , FRVBF_INSN_FCKRA, FRVBF_INSN_FCKNO, FRVBF_INSN_FCKNE, FRVBF_INSN_FCKEQ - , FRVBF_INSN_FCKLG, FRVBF_INSN_FCKUE, FRVBF_INSN_FCKUL, FRVBF_INSN_FCKGE - , FRVBF_INSN_FCKLT, FRVBF_INSN_FCKUGE, FRVBF_INSN_FCKUG, FRVBF_INSN_FCKLE - , FRVBF_INSN_FCKGT, FRVBF_INSN_FCKULE, FRVBF_INSN_FCKU, FRVBF_INSN_FCKO - , FRVBF_INSN_CCKRA, FRVBF_INSN_CCKNO, FRVBF_INSN_CCKEQ, FRVBF_INSN_CCKNE - , FRVBF_INSN_CCKLE, FRVBF_INSN_CCKGT, FRVBF_INSN_CCKLT, FRVBF_INSN_CCKGE - , FRVBF_INSN_CCKLS, FRVBF_INSN_CCKHI, FRVBF_INSN_CCKC, FRVBF_INSN_CCKNC - , FRVBF_INSN_CCKN, FRVBF_INSN_CCKP, FRVBF_INSN_CCKV, FRVBF_INSN_CCKNV - , FRVBF_INSN_CFCKRA, FRVBF_INSN_CFCKNO, FRVBF_INSN_CFCKNE, FRVBF_INSN_CFCKEQ - , FRVBF_INSN_CFCKLG, FRVBF_INSN_CFCKUE, FRVBF_INSN_CFCKUL, FRVBF_INSN_CFCKGE - , FRVBF_INSN_CFCKLT, FRVBF_INSN_CFCKUGE, FRVBF_INSN_CFCKUG, FRVBF_INSN_CFCKLE - , FRVBF_INSN_CFCKGT, FRVBF_INSN_CFCKULE, FRVBF_INSN_CFCKU, FRVBF_INSN_CFCKO - , FRVBF_INSN_CJMPL, FRVBF_INSN_CCALLL, FRVBF_INSN_ICI, FRVBF_INSN_DCI - , FRVBF_INSN_ICEI, FRVBF_INSN_DCEI, FRVBF_INSN_DCF, FRVBF_INSN_DCEF - , FRVBF_INSN_WITLB, FRVBF_INSN_WDTLB, FRVBF_INSN_ITLBI, FRVBF_INSN_DTLBI - , FRVBF_INSN_ICPL, FRVBF_INSN_DCPL, FRVBF_INSN_ICUL, FRVBF_INSN_DCUL - , FRVBF_INSN_BAR, FRVBF_INSN_MEMBAR, FRVBF_INSN_COP1, FRVBF_INSN_COP2 - , FRVBF_INSN_CLRGR, FRVBF_INSN_CLRFR, FRVBF_INSN_CLRGA, FRVBF_INSN_CLRFA - , FRVBF_INSN_COMMITGR, FRVBF_INSN_COMMITFR, FRVBF_INSN_COMMITGA, FRVBF_INSN_COMMITFA - , FRVBF_INSN_FITOS, FRVBF_INSN_FSTOI, FRVBF_INSN_FITOD, FRVBF_INSN_FDTOI - , FRVBF_INSN_FDITOS, FRVBF_INSN_FDSTOI, FRVBF_INSN_NFDITOS, FRVBF_INSN_NFDSTOI - , FRVBF_INSN_CFITOS, FRVBF_INSN_CFSTOI, FRVBF_INSN_NFITOS, FRVBF_INSN_NFSTOI - , FRVBF_INSN_FMOVS, FRVBF_INSN_FMOVD, FRVBF_INSN_FDMOVS, FRVBF_INSN_CFMOVS - , FRVBF_INSN_FNEGS, FRVBF_INSN_FNEGD, FRVBF_INSN_FDNEGS, FRVBF_INSN_CFNEGS - , FRVBF_INSN_FABSS, FRVBF_INSN_FABSD, FRVBF_INSN_FDABSS, FRVBF_INSN_CFABSS - , FRVBF_INSN_FSQRTS, FRVBF_INSN_FDSQRTS, FRVBF_INSN_NFDSQRTS, FRVBF_INSN_FSQRTD - , FRVBF_INSN_CFSQRTS, FRVBF_INSN_NFSQRTS, FRVBF_INSN_FADDS, FRVBF_INSN_FSUBS - , FRVBF_INSN_FMULS, FRVBF_INSN_FDIVS, FRVBF_INSN_FADDD, FRVBF_INSN_FSUBD - , FRVBF_INSN_FMULD, FRVBF_INSN_FDIVD, FRVBF_INSN_CFADDS, FRVBF_INSN_CFSUBS - , FRVBF_INSN_CFMULS, FRVBF_INSN_CFDIVS, FRVBF_INSN_NFADDS, FRVBF_INSN_NFSUBS - , FRVBF_INSN_NFMULS, FRVBF_INSN_NFDIVS, FRVBF_INSN_FCMPS, FRVBF_INSN_FCMPD - , FRVBF_INSN_CFCMPS, FRVBF_INSN_FDCMPS, FRVBF_INSN_FMADDS, FRVBF_INSN_FMSUBS - , FRVBF_INSN_FMADDD, FRVBF_INSN_FMSUBD, FRVBF_INSN_FDMADDS, FRVBF_INSN_NFDMADDS - , FRVBF_INSN_CFMADDS, FRVBF_INSN_CFMSUBS, FRVBF_INSN_NFMADDS, FRVBF_INSN_NFMSUBS - , FRVBF_INSN_FMAS, FRVBF_INSN_FMSS, FRVBF_INSN_FDMAS, FRVBF_INSN_FDMSS - , FRVBF_INSN_NFDMAS, FRVBF_INSN_NFDMSS, FRVBF_INSN_CFMAS, FRVBF_INSN_CFMSS - , FRVBF_INSN_FMAD, FRVBF_INSN_FMSD, FRVBF_INSN_NFMAS, FRVBF_INSN_NFMSS - , FRVBF_INSN_FDADDS, FRVBF_INSN_FDSUBS, FRVBF_INSN_FDMULS, FRVBF_INSN_FDDIVS - , FRVBF_INSN_FDSADS, FRVBF_INSN_FDMULCS, FRVBF_INSN_NFDMULCS, FRVBF_INSN_NFDADDS - , FRVBF_INSN_NFDSUBS, FRVBF_INSN_NFDMULS, FRVBF_INSN_NFDDIVS, FRVBF_INSN_NFDSADS - , FRVBF_INSN_NFDCMPS, FRVBF_INSN_MHSETLOS, FRVBF_INSN_MHSETHIS, FRVBF_INSN_MHDSETS - , FRVBF_INSN_MHSETLOH, FRVBF_INSN_MHSETHIH, FRVBF_INSN_MHDSETH, FRVBF_INSN_MAND - , FRVBF_INSN_MOR, FRVBF_INSN_MXOR, FRVBF_INSN_CMAND, FRVBF_INSN_CMOR - , FRVBF_INSN_CMXOR, FRVBF_INSN_MNOT, FRVBF_INSN_CMNOT, FRVBF_INSN_MROTLI - , FRVBF_INSN_MROTRI, FRVBF_INSN_MWCUT, FRVBF_INSN_MWCUTI, FRVBF_INSN_MCUT - , FRVBF_INSN_MCUTI, FRVBF_INSN_MCUTSS, FRVBF_INSN_MCUTSSI, FRVBF_INSN_MDCUTSSI - , FRVBF_INSN_MAVEH, FRVBF_INSN_MSLLHI, FRVBF_INSN_MSRLHI, FRVBF_INSN_MSRAHI - , FRVBF_INSN_MDROTLI, FRVBF_INSN_MCPLHI, FRVBF_INSN_MCPLI, FRVBF_INSN_MSATHS - , FRVBF_INSN_MQSATHS, FRVBF_INSN_MSATHU, FRVBF_INSN_MCMPSH, FRVBF_INSN_MCMPUH - , FRVBF_INSN_MABSHS, FRVBF_INSN_MADDHSS, FRVBF_INSN_MADDHUS, FRVBF_INSN_MSUBHSS - , FRVBF_INSN_MSUBHUS, FRVBF_INSN_CMADDHSS, FRVBF_INSN_CMADDHUS, FRVBF_INSN_CMSUBHSS - , FRVBF_INSN_CMSUBHUS, FRVBF_INSN_MQADDHSS, FRVBF_INSN_MQADDHUS, FRVBF_INSN_MQSUBHSS - , FRVBF_INSN_MQSUBHUS, FRVBF_INSN_CMQADDHSS, FRVBF_INSN_CMQADDHUS, FRVBF_INSN_CMQSUBHSS - , FRVBF_INSN_CMQSUBHUS, FRVBF_INSN_MADDACCS, FRVBF_INSN_MSUBACCS, FRVBF_INSN_MDADDACCS - , FRVBF_INSN_MDSUBACCS, FRVBF_INSN_MASACCS, FRVBF_INSN_MDASACCS, FRVBF_INSN_MMULHS - , FRVBF_INSN_MMULHU, FRVBF_INSN_MMULXHS, FRVBF_INSN_MMULXHU, FRVBF_INSN_CMMULHS - , FRVBF_INSN_CMMULHU, FRVBF_INSN_MQMULHS, FRVBF_INSN_MQMULHU, FRVBF_INSN_MQMULXHS - , FRVBF_INSN_MQMULXHU, FRVBF_INSN_CMQMULHS, FRVBF_INSN_CMQMULHU, FRVBF_INSN_MMACHS - , FRVBF_INSN_MMACHU, FRVBF_INSN_MMRDHS, FRVBF_INSN_MMRDHU, FRVBF_INSN_CMMACHS - , FRVBF_INSN_CMMACHU, FRVBF_INSN_MQMACHS, FRVBF_INSN_MQMACHU, FRVBF_INSN_CMQMACHS - , FRVBF_INSN_CMQMACHU, FRVBF_INSN_MQXMACHS, FRVBF_INSN_MQXMACXHS, FRVBF_INSN_MQMACXHS - , FRVBF_INSN_MCPXRS, FRVBF_INSN_MCPXRU, FRVBF_INSN_MCPXIS, FRVBF_INSN_MCPXIU - , FRVBF_INSN_CMCPXRS, FRVBF_INSN_CMCPXRU, FRVBF_INSN_CMCPXIS, FRVBF_INSN_CMCPXIU - , FRVBF_INSN_MQCPXRS, FRVBF_INSN_MQCPXRU, FRVBF_INSN_MQCPXIS, FRVBF_INSN_MQCPXIU - , FRVBF_INSN_MEXPDHW, FRVBF_INSN_CMEXPDHW, FRVBF_INSN_MEXPDHD, FRVBF_INSN_CMEXPDHD - , FRVBF_INSN_MPACKH, FRVBF_INSN_MDPACKH, FRVBF_INSN_MUNPACKH, FRVBF_INSN_MDUNPACKH - , FRVBF_INSN_MBTOH, FRVBF_INSN_CMBTOH, FRVBF_INSN_MHTOB, FRVBF_INSN_CMHTOB - , FRVBF_INSN_MBTOHE, FRVBF_INSN_CMBTOHE, FRVBF_INSN_MNOP, FRVBF_INSN_MCLRACC_0 - , FRVBF_INSN_MCLRACC_1, FRVBF_INSN_MRDACC, FRVBF_INSN_MRDACCG, FRVBF_INSN_MWTACC - , FRVBF_INSN_MWTACCG, FRVBF_INSN_MCOP1, FRVBF_INSN_MCOP2, FRVBF_INSN_FNOP - , FRVBF_INSN__MAX + , FRVBF_INSN_STHF, FRVBF_INSN_STF, FRVBF_INSN_STC, FRVBF_INSN_STD + , FRVBF_INSN_STDF, FRVBF_INSN_STDC, FRVBF_INSN_STQ, FRVBF_INSN_STQF + , FRVBF_INSN_STQC, FRVBF_INSN_STBU, FRVBF_INSN_STHU, FRVBF_INSN_STU + , FRVBF_INSN_STBFU, FRVBF_INSN_STHFU, FRVBF_INSN_STFU, FRVBF_INSN_STCU + , FRVBF_INSN_STDU, FRVBF_INSN_STDFU, FRVBF_INSN_STDCU, FRVBF_INSN_STQU + , FRVBF_INSN_STQFU, FRVBF_INSN_STQCU, FRVBF_INSN_CLDSB, FRVBF_INSN_CLDUB + , FRVBF_INSN_CLDSH, FRVBF_INSN_CLDUH, FRVBF_INSN_CLD, FRVBF_INSN_CLDBF + , FRVBF_INSN_CLDHF, FRVBF_INSN_CLDF, FRVBF_INSN_CLDD, FRVBF_INSN_CLDDF + , FRVBF_INSN_CLDQ, FRVBF_INSN_CLDSBU, FRVBF_INSN_CLDUBU, FRVBF_INSN_CLDSHU + , FRVBF_INSN_CLDUHU, FRVBF_INSN_CLDU, FRVBF_INSN_CLDBFU, FRVBF_INSN_CLDHFU + , FRVBF_INSN_CLDFU, FRVBF_INSN_CLDDU, FRVBF_INSN_CLDDFU, FRVBF_INSN_CLDQU + , FRVBF_INSN_CSTB, FRVBF_INSN_CSTH, FRVBF_INSN_CST, FRVBF_INSN_CSTBF + , FRVBF_INSN_CSTHF, FRVBF_INSN_CSTF, FRVBF_INSN_CSTD, FRVBF_INSN_CSTDF + , FRVBF_INSN_CSTQ, FRVBF_INSN_CSTBU, FRVBF_INSN_CSTHU, FRVBF_INSN_CSTU + , FRVBF_INSN_CSTBFU, FRVBF_INSN_CSTHFU, FRVBF_INSN_CSTFU, FRVBF_INSN_CSTDU + , FRVBF_INSN_CSTDFU, FRVBF_INSN_STBI, FRVBF_INSN_STHI, FRVBF_INSN_STI + , FRVBF_INSN_STBFI, FRVBF_INSN_STHFI, FRVBF_INSN_STFI, FRVBF_INSN_STDI + , FRVBF_INSN_STDFI, FRVBF_INSN_STQI, FRVBF_INSN_STQFI, FRVBF_INSN_SWAP + , FRVBF_INSN_SWAPI, FRVBF_INSN_CSWAP, FRVBF_INSN_MOVGF, FRVBF_INSN_MOVFG + , FRVBF_INSN_MOVGFD, FRVBF_INSN_MOVFGD, FRVBF_INSN_MOVGFQ, FRVBF_INSN_MOVFGQ + , FRVBF_INSN_CMOVGF, FRVBF_INSN_CMOVFG, FRVBF_INSN_CMOVGFD, FRVBF_INSN_CMOVFGD + , FRVBF_INSN_MOVGS, FRVBF_INSN_MOVSG, FRVBF_INSN_BRA, FRVBF_INSN_BNO + , FRVBF_INSN_BEQ, FRVBF_INSN_BNE, FRVBF_INSN_BLE, FRVBF_INSN_BGT + , FRVBF_INSN_BLT, FRVBF_INSN_BGE, FRVBF_INSN_BLS, FRVBF_INSN_BHI + , FRVBF_INSN_BC, FRVBF_INSN_BNC, FRVBF_INSN_BN, FRVBF_INSN_BP + , FRVBF_INSN_BV, FRVBF_INSN_BNV, FRVBF_INSN_FBRA, FRVBF_INSN_FBNO + , FRVBF_INSN_FBNE, FRVBF_INSN_FBEQ, FRVBF_INSN_FBLG, FRVBF_INSN_FBUE + , FRVBF_INSN_FBUL, FRVBF_INSN_FBGE, FRVBF_INSN_FBLT, FRVBF_INSN_FBUGE + , FRVBF_INSN_FBUG, FRVBF_INSN_FBLE, FRVBF_INSN_FBGT, FRVBF_INSN_FBULE + , FRVBF_INSN_FBU, FRVBF_INSN_FBO, FRVBF_INSN_BCTRLR, FRVBF_INSN_BRALR + , FRVBF_INSN_BNOLR, FRVBF_INSN_BEQLR, FRVBF_INSN_BNELR, FRVBF_INSN_BLELR + , FRVBF_INSN_BGTLR, FRVBF_INSN_BLTLR, FRVBF_INSN_BGELR, FRVBF_INSN_BLSLR + , FRVBF_INSN_BHILR, FRVBF_INSN_BCLR, FRVBF_INSN_BNCLR, FRVBF_INSN_BNLR + , FRVBF_INSN_BPLR, FRVBF_INSN_BVLR, FRVBF_INSN_BNVLR, FRVBF_INSN_FBRALR + , FRVBF_INSN_FBNOLR, FRVBF_INSN_FBEQLR, FRVBF_INSN_FBNELR, FRVBF_INSN_FBLGLR + , FRVBF_INSN_FBUELR, FRVBF_INSN_FBULLR, FRVBF_INSN_FBGELR, FRVBF_INSN_FBLTLR + , FRVBF_INSN_FBUGELR, FRVBF_INSN_FBUGLR, FRVBF_INSN_FBLELR, FRVBF_INSN_FBGTLR + , FRVBF_INSN_FBULELR, FRVBF_INSN_FBULR, FRVBF_INSN_FBOLR, FRVBF_INSN_BCRALR + , FRVBF_INSN_BCNOLR, FRVBF_INSN_BCEQLR, FRVBF_INSN_BCNELR, FRVBF_INSN_BCLELR + , FRVBF_INSN_BCGTLR, FRVBF_INSN_BCLTLR, FRVBF_INSN_BCGELR, FRVBF_INSN_BCLSLR + , FRVBF_INSN_BCHILR, FRVBF_INSN_BCCLR, FRVBF_INSN_BCNCLR, FRVBF_INSN_BCNLR + , FRVBF_INSN_BCPLR, FRVBF_INSN_BCVLR, FRVBF_INSN_BCNVLR, FRVBF_INSN_FCBRALR + , FRVBF_INSN_FCBNOLR, FRVBF_INSN_FCBEQLR, FRVBF_INSN_FCBNELR, FRVBF_INSN_FCBLGLR + , FRVBF_INSN_FCBUELR, FRVBF_INSN_FCBULLR, FRVBF_INSN_FCBGELR, FRVBF_INSN_FCBLTLR + , FRVBF_INSN_FCBUGELR, FRVBF_INSN_FCBUGLR, FRVBF_INSN_FCBLELR, FRVBF_INSN_FCBGTLR + , FRVBF_INSN_FCBULELR, FRVBF_INSN_FCBULR, FRVBF_INSN_FCBOLR, FRVBF_INSN_JMPL + , FRVBF_INSN_CALLL, FRVBF_INSN_JMPIL, FRVBF_INSN_CALLIL, FRVBF_INSN_CALL + , FRVBF_INSN_RETT, FRVBF_INSN_REI, FRVBF_INSN_TRA, FRVBF_INSN_TNO + , FRVBF_INSN_TEQ, FRVBF_INSN_TNE, FRVBF_INSN_TLE, FRVBF_INSN_TGT + , FRVBF_INSN_TLT, FRVBF_INSN_TGE, FRVBF_INSN_TLS, FRVBF_INSN_THI + , FRVBF_INSN_TC, FRVBF_INSN_TNC, FRVBF_INSN_TN, FRVBF_INSN_TP + , FRVBF_INSN_TV, FRVBF_INSN_TNV, FRVBF_INSN_FTRA, FRVBF_INSN_FTNO + , FRVBF_INSN_FTNE, FRVBF_INSN_FTEQ, FRVBF_INSN_FTLG, FRVBF_INSN_FTUE + , FRVBF_INSN_FTUL, FRVBF_INSN_FTGE, FRVBF_INSN_FTLT, FRVBF_INSN_FTUGE + , FRVBF_INSN_FTUG, FRVBF_INSN_FTLE, FRVBF_INSN_FTGT, FRVBF_INSN_FTULE + , FRVBF_INSN_FTU, FRVBF_INSN_FTO, FRVBF_INSN_TIRA, FRVBF_INSN_TINO + , FRVBF_INSN_TIEQ, FRVBF_INSN_TINE, FRVBF_INSN_TILE, FRVBF_INSN_TIGT + , FRVBF_INSN_TILT, FRVBF_INSN_TIGE, FRVBF_INSN_TILS, FRVBF_INSN_TIHI + , FRVBF_INSN_TIC, FRVBF_INSN_TINC, FRVBF_INSN_TIN, FRVBF_INSN_TIP + , FRVBF_INSN_TIV, FRVBF_INSN_TINV, FRVBF_INSN_FTIRA, FRVBF_INSN_FTINO + , FRVBF_INSN_FTINE, FRVBF_INSN_FTIEQ, FRVBF_INSN_FTILG, FRVBF_INSN_FTIUE + , FRVBF_INSN_FTIUL, FRVBF_INSN_FTIGE, FRVBF_INSN_FTILT, FRVBF_INSN_FTIUGE + , FRVBF_INSN_FTIUG, FRVBF_INSN_FTILE, FRVBF_INSN_FTIGT, FRVBF_INSN_FTIULE + , FRVBF_INSN_FTIU, FRVBF_INSN_FTIO, FRVBF_INSN_BREAK, FRVBF_INSN_MTRAP + , FRVBF_INSN_ANDCR, FRVBF_INSN_ORCR, FRVBF_INSN_XORCR, FRVBF_INSN_NANDCR + , FRVBF_INSN_NORCR, FRVBF_INSN_ANDNCR, FRVBF_INSN_ORNCR, FRVBF_INSN_NANDNCR + , FRVBF_INSN_NORNCR, FRVBF_INSN_NOTCR, FRVBF_INSN_CKRA, FRVBF_INSN_CKNO + , FRVBF_INSN_CKEQ, FRVBF_INSN_CKNE, FRVBF_INSN_CKLE, FRVBF_INSN_CKGT + , FRVBF_INSN_CKLT, FRVBF_INSN_CKGE, FRVBF_INSN_CKLS, FRVBF_INSN_CKHI + , FRVBF_INSN_CKC, FRVBF_INSN_CKNC, FRVBF_INSN_CKN, FRVBF_INSN_CKP + , FRVBF_INSN_CKV, FRVBF_INSN_CKNV, FRVBF_INSN_FCKRA, FRVBF_INSN_FCKNO + , FRVBF_INSN_FCKNE, FRVBF_INSN_FCKEQ, FRVBF_INSN_FCKLG, FRVBF_INSN_FCKUE + , FRVBF_INSN_FCKUL, FRVBF_INSN_FCKGE, FRVBF_INSN_FCKLT, FRVBF_INSN_FCKUGE + , FRVBF_INSN_FCKUG, FRVBF_INSN_FCKLE, FRVBF_INSN_FCKGT, FRVBF_INSN_FCKULE + , FRVBF_INSN_FCKU, FRVBF_INSN_FCKO, FRVBF_INSN_CCKRA, FRVBF_INSN_CCKNO + , FRVBF_INSN_CCKEQ, FRVBF_INSN_CCKNE, FRVBF_INSN_CCKLE, FRVBF_INSN_CCKGT + , FRVBF_INSN_CCKLT, FRVBF_INSN_CCKGE, FRVBF_INSN_CCKLS, FRVBF_INSN_CCKHI + , FRVBF_INSN_CCKC, FRVBF_INSN_CCKNC, FRVBF_INSN_CCKN, FRVBF_INSN_CCKP + , FRVBF_INSN_CCKV, FRVBF_INSN_CCKNV, FRVBF_INSN_CFCKRA, FRVBF_INSN_CFCKNO + , FRVBF_INSN_CFCKNE, FRVBF_INSN_CFCKEQ, FRVBF_INSN_CFCKLG, FRVBF_INSN_CFCKUE + , FRVBF_INSN_CFCKUL, FRVBF_INSN_CFCKGE, FRVBF_INSN_CFCKLT, FRVBF_INSN_CFCKUGE + , FRVBF_INSN_CFCKUG, FRVBF_INSN_CFCKLE, FRVBF_INSN_CFCKGT, FRVBF_INSN_CFCKULE + , FRVBF_INSN_CFCKU, FRVBF_INSN_CFCKO, FRVBF_INSN_CJMPL, FRVBF_INSN_CCALLL + , FRVBF_INSN_ICI, FRVBF_INSN_DCI, FRVBF_INSN_ICEI, FRVBF_INSN_DCEI + , FRVBF_INSN_DCF, FRVBF_INSN_DCEF, FRVBF_INSN_WITLB, FRVBF_INSN_WDTLB + , FRVBF_INSN_ITLBI, FRVBF_INSN_DTLBI, FRVBF_INSN_ICPL, FRVBF_INSN_DCPL + , FRVBF_INSN_ICUL, FRVBF_INSN_DCUL, FRVBF_INSN_BAR, FRVBF_INSN_MEMBAR + , FRVBF_INSN_LRAI, FRVBF_INSN_LRAD, FRVBF_INSN_TLBPR, FRVBF_INSN_COP1 + , FRVBF_INSN_COP2, FRVBF_INSN_CLRGR, FRVBF_INSN_CLRFR, FRVBF_INSN_CLRGA + , FRVBF_INSN_CLRFA, FRVBF_INSN_COMMITGR, FRVBF_INSN_COMMITFR, FRVBF_INSN_COMMITGA + , FRVBF_INSN_COMMITFA, FRVBF_INSN_FITOS, FRVBF_INSN_FSTOI, FRVBF_INSN_FITOD + , FRVBF_INSN_FDTOI, FRVBF_INSN_FDITOS, FRVBF_INSN_FDSTOI, FRVBF_INSN_NFDITOS + , FRVBF_INSN_NFDSTOI, FRVBF_INSN_CFITOS, FRVBF_INSN_CFSTOI, FRVBF_INSN_NFITOS + , FRVBF_INSN_NFSTOI, FRVBF_INSN_FMOVS, FRVBF_INSN_FMOVD, FRVBF_INSN_FDMOVS + , FRVBF_INSN_CFMOVS, FRVBF_INSN_FNEGS, FRVBF_INSN_FNEGD, FRVBF_INSN_FDNEGS + , FRVBF_INSN_CFNEGS, FRVBF_INSN_FABSS, FRVBF_INSN_FABSD, FRVBF_INSN_FDABSS + , FRVBF_INSN_CFABSS, FRVBF_INSN_FSQRTS, FRVBF_INSN_FDSQRTS, FRVBF_INSN_NFDSQRTS + , FRVBF_INSN_FSQRTD, FRVBF_INSN_CFSQRTS, FRVBF_INSN_NFSQRTS, FRVBF_INSN_FADDS + , FRVBF_INSN_FSUBS, FRVBF_INSN_FMULS, FRVBF_INSN_FDIVS, FRVBF_INSN_FADDD + , FRVBF_INSN_FSUBD, FRVBF_INSN_FMULD, FRVBF_INSN_FDIVD, FRVBF_INSN_CFADDS + , FRVBF_INSN_CFSUBS, FRVBF_INSN_CFMULS, FRVBF_INSN_CFDIVS, FRVBF_INSN_NFADDS + , FRVBF_INSN_NFSUBS, FRVBF_INSN_NFMULS, FRVBF_INSN_NFDIVS, FRVBF_INSN_FCMPS + , FRVBF_INSN_FCMPD, FRVBF_INSN_CFCMPS, FRVBF_INSN_FDCMPS, FRVBF_INSN_FMADDS + , FRVBF_INSN_FMSUBS, FRVBF_INSN_FMADDD, FRVBF_INSN_FMSUBD, FRVBF_INSN_FDMADDS + , FRVBF_INSN_NFDMADDS, FRVBF_INSN_CFMADDS, FRVBF_INSN_CFMSUBS, FRVBF_INSN_NFMADDS + , FRVBF_INSN_NFMSUBS, FRVBF_INSN_FMAS, FRVBF_INSN_FMSS, FRVBF_INSN_FDMAS + , FRVBF_INSN_FDMSS, FRVBF_INSN_NFDMAS, FRVBF_INSN_NFDMSS, FRVBF_INSN_CFMAS + , FRVBF_INSN_CFMSS, FRVBF_INSN_FMAD, FRVBF_INSN_FMSD, FRVBF_INSN_NFMAS + , FRVBF_INSN_NFMSS, FRVBF_INSN_FDADDS, FRVBF_INSN_FDSUBS, FRVBF_INSN_FDMULS + , FRVBF_INSN_FDDIVS, FRVBF_INSN_FDSADS, FRVBF_INSN_FDMULCS, FRVBF_INSN_NFDMULCS + , FRVBF_INSN_NFDADDS, FRVBF_INSN_NFDSUBS, FRVBF_INSN_NFDMULS, FRVBF_INSN_NFDDIVS + , FRVBF_INSN_NFDSADS, FRVBF_INSN_NFDCMPS, FRVBF_INSN_MHSETLOS, FRVBF_INSN_MHSETHIS + , FRVBF_INSN_MHDSETS, FRVBF_INSN_MHSETLOH, FRVBF_INSN_MHSETHIH, FRVBF_INSN_MHDSETH + , FRVBF_INSN_MAND, FRVBF_INSN_MOR, FRVBF_INSN_MXOR, FRVBF_INSN_CMAND + , FRVBF_INSN_CMOR, FRVBF_INSN_CMXOR, FRVBF_INSN_MNOT, FRVBF_INSN_CMNOT + , FRVBF_INSN_MROTLI, FRVBF_INSN_MROTRI, FRVBF_INSN_MWCUT, FRVBF_INSN_MWCUTI + , FRVBF_INSN_MCUT, FRVBF_INSN_MCUTI, FRVBF_INSN_MCUTSS, FRVBF_INSN_MCUTSSI + , FRVBF_INSN_MDCUTSSI, FRVBF_INSN_MAVEH, FRVBF_INSN_MSLLHI, FRVBF_INSN_MSRLHI + , FRVBF_INSN_MSRAHI, FRVBF_INSN_MDROTLI, FRVBF_INSN_MCPLHI, FRVBF_INSN_MCPLI + , FRVBF_INSN_MSATHS, FRVBF_INSN_MQSATHS, FRVBF_INSN_MSATHU, FRVBF_INSN_MCMPSH + , FRVBF_INSN_MCMPUH, FRVBF_INSN_MABSHS, FRVBF_INSN_MADDHSS, FRVBF_INSN_MADDHUS + , FRVBF_INSN_MSUBHSS, FRVBF_INSN_MSUBHUS, FRVBF_INSN_CMADDHSS, FRVBF_INSN_CMADDHUS + , FRVBF_INSN_CMSUBHSS, FRVBF_INSN_CMSUBHUS, FRVBF_INSN_MQADDHSS, FRVBF_INSN_MQADDHUS + , FRVBF_INSN_MQSUBHSS, FRVBF_INSN_MQSUBHUS, FRVBF_INSN_CMQADDHSS, FRVBF_INSN_CMQADDHUS + , FRVBF_INSN_CMQSUBHSS, FRVBF_INSN_CMQSUBHUS, FRVBF_INSN_MQLCLRHS, FRVBF_INSN_MQLMTHS + , FRVBF_INSN_MQSLLHI, FRVBF_INSN_MQSRAHI, FRVBF_INSN_MADDACCS, FRVBF_INSN_MSUBACCS + , FRVBF_INSN_MDADDACCS, FRVBF_INSN_MDSUBACCS, FRVBF_INSN_MASACCS, FRVBF_INSN_MDASACCS + , FRVBF_INSN_MMULHS, FRVBF_INSN_MMULHU, FRVBF_INSN_MMULXHS, FRVBF_INSN_MMULXHU + , FRVBF_INSN_CMMULHS, FRVBF_INSN_CMMULHU, FRVBF_INSN_MQMULHS, FRVBF_INSN_MQMULHU + , FRVBF_INSN_MQMULXHS, FRVBF_INSN_MQMULXHU, FRVBF_INSN_CMQMULHS, FRVBF_INSN_CMQMULHU + , FRVBF_INSN_MMACHS, FRVBF_INSN_MMACHU, FRVBF_INSN_MMRDHS, FRVBF_INSN_MMRDHU + , FRVBF_INSN_CMMACHS, FRVBF_INSN_CMMACHU, FRVBF_INSN_MQMACHS, FRVBF_INSN_MQMACHU + , FRVBF_INSN_CMQMACHS, FRVBF_INSN_CMQMACHU, FRVBF_INSN_MQXMACHS, FRVBF_INSN_MQXMACXHS + , FRVBF_INSN_MQMACXHS, FRVBF_INSN_MCPXRS, FRVBF_INSN_MCPXRU, FRVBF_INSN_MCPXIS + , FRVBF_INSN_MCPXIU, FRVBF_INSN_CMCPXRS, FRVBF_INSN_CMCPXRU, FRVBF_INSN_CMCPXIS + , FRVBF_INSN_CMCPXIU, FRVBF_INSN_MQCPXRS, FRVBF_INSN_MQCPXRU, FRVBF_INSN_MQCPXIS + , FRVBF_INSN_MQCPXIU, FRVBF_INSN_MEXPDHW, FRVBF_INSN_CMEXPDHW, FRVBF_INSN_MEXPDHD + , FRVBF_INSN_CMEXPDHD, FRVBF_INSN_MPACKH, FRVBF_INSN_MDPACKH, FRVBF_INSN_MUNPACKH + , FRVBF_INSN_MDUNPACKH, FRVBF_INSN_MBTOH, FRVBF_INSN_CMBTOH, FRVBF_INSN_MHTOB + , FRVBF_INSN_CMHTOB, FRVBF_INSN_MBTOHE, FRVBF_INSN_CMBTOHE, FRVBF_INSN_MNOP + , FRVBF_INSN_MCLRACC_0, FRVBF_INSN_MCLRACC_1, FRVBF_INSN_MRDACC, FRVBF_INSN_MRDACCG + , FRVBF_INSN_MWTACC, FRVBF_INSN_MWTACCG, FRVBF_INSN_MCOP1, FRVBF_INSN_MCOP2 + , FRVBF_INSN_FNOP, FRVBF_INSN__MAX } FRVBF_INSN_TYPE; /* Enum declaration for semantic formats in cpu family frvbf. */ @@ -245,8 +244,7 @@ typedef enum frvbf_sfmt_type { , FRVBF_SFMT_LDBFI, FRVBF_SFMT_NLDSBI, FRVBF_SFMT_NLDBFI, FRVBF_SFMT_LDDI , FRVBF_SFMT_LDDFI, FRVBF_SFMT_NLDDI, FRVBF_SFMT_NLDDFI, FRVBF_SFMT_LDQI , FRVBF_SFMT_LDQFI, FRVBF_SFMT_NLDQFI, FRVBF_SFMT_STB, FRVBF_SFMT_STBF - , FRVBF_SFMT_STC, FRVBF_SFMT_RSTB, FRVBF_SFMT_RSTBF, FRVBF_SFMT_STD - , FRVBF_SFMT_STDF, FRVBF_SFMT_STDC, FRVBF_SFMT_RSTD, FRVBF_SFMT_RSTDF + , FRVBF_SFMT_STC, FRVBF_SFMT_STD, FRVBF_SFMT_STDF, FRVBF_SFMT_STDC , FRVBF_SFMT_STBU, FRVBF_SFMT_STBFU, FRVBF_SFMT_STCU, FRVBF_SFMT_STDU , FRVBF_SFMT_STDFU, FRVBF_SFMT_STDCU, FRVBF_SFMT_STQU, FRVBF_SFMT_CLDSB , FRVBF_SFMT_CLDBF, FRVBF_SFMT_CLDD, FRVBF_SFMT_CLDDF, FRVBF_SFMT_CLDQ @@ -283,16 +281,17 @@ typedef enum frvbf_sfmt_type { , FRVBF_SFMT_MWCUTI, FRVBF_SFMT_MCUT, FRVBF_SFMT_MCUTI, FRVBF_SFMT_MDCUTSSI , FRVBF_SFMT_MSLLHI, FRVBF_SFMT_MDROTLI, FRVBF_SFMT_MCPLHI, FRVBF_SFMT_MCPLI , FRVBF_SFMT_MSATHS, FRVBF_SFMT_MQSATHS, FRVBF_SFMT_MCMPSH, FRVBF_SFMT_MABSHS - , FRVBF_SFMT_CMADDHSS, FRVBF_SFMT_CMQADDHSS, FRVBF_SFMT_MADDACCS, FRVBF_SFMT_MDADDACCS - , FRVBF_SFMT_MASACCS, FRVBF_SFMT_MDASACCS, FRVBF_SFMT_MMULHS, FRVBF_SFMT_CMMULHS - , FRVBF_SFMT_MQMULHS, FRVBF_SFMT_CMQMULHS, FRVBF_SFMT_MMACHS, FRVBF_SFMT_MMACHU - , FRVBF_SFMT_CMMACHS, FRVBF_SFMT_CMMACHU, FRVBF_SFMT_MQMACHS, FRVBF_SFMT_MQMACHU - , FRVBF_SFMT_CMQMACHS, FRVBF_SFMT_CMQMACHU, FRVBF_SFMT_MCPXRS, FRVBF_SFMT_CMCPXRS - , FRVBF_SFMT_MQCPXRS, FRVBF_SFMT_MEXPDHW, FRVBF_SFMT_CMEXPDHW, FRVBF_SFMT_MEXPDHD - , FRVBF_SFMT_CMEXPDHD, FRVBF_SFMT_MPACKH, FRVBF_SFMT_MDPACKH, FRVBF_SFMT_MUNPACKH - , FRVBF_SFMT_MDUNPACKH, FRVBF_SFMT_MBTOH, FRVBF_SFMT_CMBTOH, FRVBF_SFMT_MHTOB - , FRVBF_SFMT_CMHTOB, FRVBF_SFMT_MBTOHE, FRVBF_SFMT_CMBTOHE, FRVBF_SFMT_MCLRACC_0 - , FRVBF_SFMT_MRDACC, FRVBF_SFMT_MRDACCG, FRVBF_SFMT_MWTACC, FRVBF_SFMT_MWTACCG + , FRVBF_SFMT_CMADDHSS, FRVBF_SFMT_CMQADDHSS, FRVBF_SFMT_MQSLLHI, FRVBF_SFMT_MADDACCS + , FRVBF_SFMT_MDADDACCS, FRVBF_SFMT_MASACCS, FRVBF_SFMT_MDASACCS, FRVBF_SFMT_MMULHS + , FRVBF_SFMT_CMMULHS, FRVBF_SFMT_MQMULHS, FRVBF_SFMT_CMQMULHS, FRVBF_SFMT_MMACHS + , FRVBF_SFMT_MMACHU, FRVBF_SFMT_CMMACHS, FRVBF_SFMT_CMMACHU, FRVBF_SFMT_MQMACHS + , FRVBF_SFMT_MQMACHU, FRVBF_SFMT_CMQMACHS, FRVBF_SFMT_CMQMACHU, FRVBF_SFMT_MCPXRS + , FRVBF_SFMT_CMCPXRS, FRVBF_SFMT_MQCPXRS, FRVBF_SFMT_MEXPDHW, FRVBF_SFMT_CMEXPDHW + , FRVBF_SFMT_MEXPDHD, FRVBF_SFMT_CMEXPDHD, FRVBF_SFMT_MPACKH, FRVBF_SFMT_MDPACKH + , FRVBF_SFMT_MUNPACKH, FRVBF_SFMT_MDUNPACKH, FRVBF_SFMT_MBTOH, FRVBF_SFMT_CMBTOH + , FRVBF_SFMT_MHTOB, FRVBF_SFMT_CMHTOB, FRVBF_SFMT_MBTOHE, FRVBF_SFMT_CMBTOHE + , FRVBF_SFMT_MCLRACC_0, FRVBF_SFMT_MRDACC, FRVBF_SFMT_MRDACCG, FRVBF_SFMT_MWTACC + , FRVBF_SFMT_MWTACCG } FRVBF_SFMT_TYPE; /* Function unit handlers (user written). */ @@ -445,6 +444,52 @@ extern int frvbf_model_fr400_u_idiv (SIM_CPU *, const IDESC *, int /*unit_num*/, extern int frvbf_model_fr400_u_imul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRdoublek*/, INT /*ICCi_1*/); extern int frvbf_model_fr400_u_integer (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*ICCi_1*/); extern int frvbf_model_fr400_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int frvbf_model_fr450_u_dcul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr450_u_icul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr450_u_dcpl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr450_u_icpl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr450_u_dcf (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr450_u_dci (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr450_u_ici (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/); +extern int frvbf_model_fr450_u_membar (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int frvbf_model_fr450_u_barrier (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int frvbf_model_fr450_u_media_dual_htob (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintj*/, INT /*FRintk*/); +extern int frvbf_model_fr450_u_media_dual_expand (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintk*/); +extern int frvbf_model_fr450_u_media_7 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FCCk*/); +extern int frvbf_model_fr450_u_media_6 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintk*/); +extern int frvbf_model_fr450_u_media_4_mclracca (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int frvbf_model_fr450_u_media_4_acc_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*FRintk*/); +extern int frvbf_model_fr450_u_media_4_accg (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACCGi*/, INT /*FRinti*/, INT /*ACCGk*/, INT /*FRintk*/); +extern int frvbf_model_fr450_u_media_4 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*FRintj*/, INT /*ACC40Sk*/, INT /*FRintk*/); +extern int frvbf_model_fr450_u_media_3_quad (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FRintk*/); +extern int frvbf_model_fr450_u_media_3_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintk*/); +extern int frvbf_model_fr450_u_media_3 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FRintk*/); +extern int frvbf_model_fr450_u_media_2_add_sub_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/); +extern int frvbf_model_fr450_u_media_2_add_sub (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/); +extern int frvbf_model_fr450_u_media_2_acc_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/); +extern int frvbf_model_fr450_u_media_2_acc (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/); +extern int frvbf_model_fr450_u_media_2_quad (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*ACC40Sk*/, INT /*ACC40Uk*/); +extern int frvbf_model_fr450_u_media_2 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*ACC40Sk*/, INT /*ACC40Uk*/); +extern int frvbf_model_fr450_u_media_hilo (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRkhi*/, INT /*FRklo*/); +extern int frvbf_model_fr450_u_media_1_quad (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FRintk*/); +extern int frvbf_model_fr450_u_media_1 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FRintk*/); +extern int frvbf_model_fr450_u_gr2spr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRj*/, INT /*spr*/); +extern int frvbf_model_fr450_u_gr2fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRj*/, INT /*FRintk*/); +extern int frvbf_model_fr450_u_spr2gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*spr*/, INT /*GRj*/); +extern int frvbf_model_fr450_u_fr2gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintk*/, INT /*GRj*/); +extern int frvbf_model_fr450_u_swap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/); +extern int frvbf_model_fr450_u_fr_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*FRintk*/, INT /*FRdoublek*/); +extern int frvbf_model_fr450_u_fr_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*FRintk*/, INT /*FRdoublek*/); +extern int frvbf_model_fr450_u_gr_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*GRdoublek*/); +extern int frvbf_model_fr450_u_gr_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*GRdoublek*/); +extern int frvbf_model_fr450_u_set_hilo (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRkhi*/, INT /*GRklo*/); +extern int frvbf_model_fr450_u_check (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ICCi_3*/, INT /*FCCi_3*/); +extern int frvbf_model_fr450_u_trap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*ICCi_2*/, INT /*FCCi_2*/); +extern int frvbf_model_fr450_u_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*ICCi_2*/, INT /*FCCi_2*/); +extern int frvbf_model_fr450_u_idiv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*ICCi_1*/); +extern int frvbf_model_fr450_u_imul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRdoublek*/, INT /*ICCi_1*/); +extern int frvbf_model_fr450_u_integer (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*ICCi_1*/); +extern int frvbf_model_fr450_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); extern int frvbf_model_simple_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); /* Profiling before/after handlers (user written) */ diff --git a/sim/frv/frv-sim.h b/sim/frv/frv-sim.h index 39da19c37be..ce5d492766d 100644 --- a/sim/frv/frv-sim.h +++ b/sim/frv/frv-sim.h @@ -23,11 +23,8 @@ with this program; if not, write to the Free Software Foundation, Inc., #include "sim-options.h" -/* Not defined in the cgen cpu file for access restriction purposes. */ -#define H_SPR_ACC4 1412 -#define H_SPR_ACC63 1471 -#define H_SPR_ACCG4 1476 -#define H_SPR_ACCG63 1535 +/* True if SPR is the number of accumulator or accumulator guard register. */ +#define SPR_IS_ACC(SPR) ((SPR) >= 1408 && (SPR) <= 1535) /* Initialization of the frv cpu. */ void frv_initialize (SIM_CPU *, SIM_DESC); diff --git a/sim/frv/frv.c b/sim/frv/frv.c index de1ff1d0529..e82f3d006fd 100644 --- a/sim/frv/frv.c +++ b/sim/frv/frv.c @@ -1,5 +1,6 @@ /* frv simulator support code - Copyright (C) 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc. + Copyright (C) 1998, 1999, 2000, 2001, 2003, 2004 Free Software + Foundation, Inc. Contributed by Red Hat. This file is part of the GNU simulators. @@ -172,7 +173,15 @@ check_register_alignment (SIM_CPU *current_cpu, UINT reg, int align_mask) SIM_DESC sd = CPU_STATE (current_cpu); switch (STATE_ARCHITECTURE (sd)->mach) { + /* Note: there is a discrepancy between V2.2 of the FR400 + instruction manual and the various FR4xx LSI specs. + The former claims that unaligned registers cause a + register_exception while the latter say it's an + illegal_instruction. The LSI specs appear to be + correct; in fact, the FR4xx series is not documented + as having a register_exception. */ case bfd_mach_fr400: + case bfd_mach_fr450: case bfd_mach_fr550: frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); break; @@ -200,7 +209,9 @@ check_fr_register_alignment (SIM_CPU *current_cpu, UINT reg, int align_mask) SIM_DESC sd = CPU_STATE (current_cpu); switch (STATE_ARCHITECTURE (sd)->mach) { + /* See comment in check_register_alignment(). */ case bfd_mach_fr400: + case bfd_mach_fr450: case bfd_mach_fr550: frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); break; @@ -232,7 +243,9 @@ check_memory_alignment (SIM_CPU *current_cpu, SI address, int align_mask) SIM_DESC sd = CPU_STATE (current_cpu); switch (STATE_ARCHITECTURE (sd)->mach) { + /* See comment in check_register_alignment(). */ case bfd_mach_fr400: + case bfd_mach_fr450: frv_queue_data_access_error_interrupt (current_cpu, address); break; case bfd_mach_frvtomcat: @@ -989,10 +1002,11 @@ void frvbf_clear_accumulators (SIM_CPU *current_cpu, SI acc_ix, int A) { SIM_DESC sd = CPU_STATE (current_cpu); - int acc_num = - (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr500) ? 8 : - (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550) ? 8 : - (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400) ? 4 : + int acc_mask = + (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr500) ? 7 : + (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550) ? 7 : + (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr450) ? 11 : + (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400) ? 3 : 63; FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu); @@ -1002,15 +1016,16 @@ frvbf_clear_accumulators (SIM_CPU *current_cpu, SI acc_ix, int A) { /* This instruction is a nop if the referenced accumulator is not implemented. */ - if (acc_ix < acc_num) + if ((acc_ix & acc_mask) == acc_ix) sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, acc_ix, 0); } else { /* Clear all implemented accumulators. */ int i; - for (i = 0; i < acc_num; ++i) - sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, i, 0); + for (i = 0; i <= acc_mask; ++i) + if ((i & acc_mask) == i) + sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, i, 0); } } @@ -1100,25 +1115,53 @@ frvbf_media_cut_ss (SIM_CPU *current_cpu, DI acc, SI cut_point) SI frvbf_iacc_cut (SIM_CPU *current_cpu, DI acc, SI cut_point) { - /* The cut point is the lower 6 bits (signed) of what we are passed. */ + DI lower, upper; + + /* The cut point is the lower 7 bits (signed) of what we are passed. */ cut_point = cut_point << 25 >> 25; - if (cut_point <= -32) - cut_point = -31; /* Special case for full shiftout. */ + /* Conceptually, the operation is on a 128-bit sign-extension of ACC. + The top bit of the return value corresponds to bit (63 - CUT_POINT) + of this 128-bit value. - /* Negative cuts (cannot saturate). */ + Since we can't deal with 128-bit values very easily, convert the + operation into an equivalent 64-bit one. */ if (cut_point < 0) - return acc >> (32 + -cut_point); + { + /* Avoid an undefined shift operation. */ + if (cut_point == -64) + acc >>= 63; + else + acc >>= -cut_point; + cut_point = 0; + } - /* Positive cuts will saturate if significant bits are shifted out. */ - if (acc != ((acc << cut_point) >> cut_point)) - if (acc >= 0) - return 0x7fffffff; - else - return 0x80000000; + /* Get the shifted but unsaturated result. Set LOWER to the lowest + 32 bits of the result and UPPER to the result >> 31. */ + if (cut_point < 32) + { + /* The cut loses the (32 - CUT_POINT) least significant bits. + Round the result up if the most significant of these lost bits + is 1. */ + lower = acc >> (32 - cut_point); + if (lower < 0x7fffffff) + if (acc & LSBIT64 (32 - cut_point - 1)) + lower++; + upper = lower >> 31; + } + else + { + lower = acc << (cut_point - 32); + upper = acc >> (63 - cut_point); + } - /* No saturate, just cut. */ - return ((acc << cut_point) >> 32); + /* Saturate the result. */ + if (upper < -1) + return ~0x7fffffff; + else if (upper > 0) + return 0x7fffffff; + else + return lower; } /* Compute the result of shift-left-arithmetic-with-saturation (SLASS). */ @@ -1179,12 +1222,14 @@ do_media_average (SIM_CPU *current_cpu, HI arg1, HI arg2) HI result = sum >> 1; int rounding_value; - /* On fr400 and fr550, check the rounding mode. On other machines rounding is always - toward negative infinity and the result is already correctly rounded. */ + /* On fr4xx and fr550, check the rounding mode. On other machines + rounding is always toward negative infinity and the result is + already correctly rounded. */ switch (STATE_ARCHITECTURE (sd)->mach) { /* Need to check rounding mode. */ case bfd_mach_fr400: + case bfd_mach_fr450: case bfd_mach_fr550: /* Check whether rounding will be required. Rounding will be required if the sum is an odd number. */ diff --git a/sim/frv/interrupts.c b/sim/frv/interrupts.c index 540ee06e28d..6c40f1dd111 100644 --- a/sim/frv/interrupts.c +++ b/sim/frv/interrupts.c @@ -239,6 +239,7 @@ frv_queue_illegal_instruction_interrupt ( switch (STATE_ARCHITECTURE (sd)->mach) { case bfd_mach_fr400: + case bfd_mach_fr450: case bfd_mach_fr550: break; default: @@ -299,6 +300,7 @@ frv_queue_non_implemented_instruction_interrupt ( switch (STATE_ARCHITECTURE (sd)->mach) { case bfd_mach_fr400: + case bfd_mach_fr450: case bfd_mach_fr550: break; default: @@ -845,8 +847,7 @@ set_exception_status_registers ( break; case FRV_DATA_ACCESS_ERROR: reg_index = 15; /* Use ESR15, EPCR15. */ - if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr400) - set_ear = 1; + set_ear = 1; break; case FRV_DATA_ACCESS_EXCEPTION: set_daec = 1; diff --git a/sim/frv/memory.c b/sim/frv/memory.c index 4dbc65242ac..2249904133c 100644 --- a/sim/frv/memory.c +++ b/sim/frv/memory.c @@ -73,6 +73,7 @@ check_data_read_address (SIM_CPU *current_cpu, SI address, int align_mask) switch (STATE_ARCHITECTURE (sd)->mach) { case bfd_mach_fr400: + case bfd_mach_fr450: address = fr400_check_data_read_address (current_cpu, address, align_mask); break; @@ -149,6 +150,7 @@ check_readwrite_address (SIM_CPU *current_cpu, SI address, int align_mask) switch (STATE_ARCHITECTURE (sd)->mach) { case bfd_mach_fr400: + case bfd_mach_fr450: address = fr400_check_readwrite_address (current_cpu, address, align_mask); break; @@ -240,6 +242,7 @@ check_insn_read_address (SIM_CPU *current_cpu, PCADDR address, int align_mask) switch (STATE_ARCHITECTURE (sd)->mach) { case bfd_mach_fr400: + case bfd_mach_fr450: address = fr400_check_insn_read_address (current_cpu, address, align_mask); break; @@ -679,18 +682,6 @@ frvbf_read_imem_USI (SIM_CPU *current_cpu, PCADDR vpc) static SI fr400_check_write_address (SIM_CPU *current_cpu, SI address, int align_mask) { - if (address & align_mask) - { - /* On the fr400, this causes a data_access_error. */ - /* Make sure that this exception is not masked. */ - USI isr = GET_ISR (); - if (! GET_ISR_EMAM (isr)) - { - /* Bad alignment causes a data_access_error on fr400. */ - frv_queue_data_access_error_interrupt (current_cpu, address); - } - address &= ~align_mask; - } if (align_mask == 7 && address >= 0xfe800000 && address <= 0xfeffffff) frv_queue_program_interrupt (current_cpu, FRV_DATA_STORE_ERROR); @@ -735,6 +726,7 @@ check_write_address (SIM_CPU *current_cpu, SI address, int align_mask) switch (STATE_ARCHITECTURE (sd)->mach) { case bfd_mach_fr400: + case bfd_mach_fr450: address = fr400_check_write_address (current_cpu, address, align_mask); break; case bfd_mach_frvtomcat: diff --git a/sim/frv/mloop.in b/sim/frv/mloop.in index 073d81d7569..24c34c9c651 100644 --- a/sim/frv/mloop.in +++ b/sim/frv/mloop.in @@ -391,6 +391,7 @@ static void switch (STATE_ARCHITECTURE (sd)->mach) { case bfd_mach_fr400: + case bfd_mach_fr450: simulate_dual_insn_prefetch (current_cpu, vpc, 8); break; case bfd_mach_frvtomcat: diff --git a/sim/frv/model.c b/sim/frv/model.c index 864c1800b74..17dae3132b3 100644 --- a/sim/frv/model.c +++ b/sim/frv/model.c @@ -2866,102 +2866,6 @@ model_frv_stc (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } -static int -model_frv_rstb (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_frv_rsth (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_frv_rst (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_frv_rstbf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_frv_rsthf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_frv_rstf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - static int model_frv_std (SIM_CPU *current_cpu, void *sem_arg) { @@ -3010,38 +2914,6 @@ model_frv_stdc (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } -static int -model_frv_rstd (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_frv_rstdf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - static int model_frv_stq (SIM_CPU *current_cpu, void *sem_arg) { @@ -3090,38 +2962,6 @@ model_frv_stqc (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } -static int -model_frv_rstq (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_smulcc.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_frv_rstqf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - static int model_frv_stbu (SIM_CPU *current_cpu, void *sem_arg) { @@ -8546,6 +8386,54 @@ model_frv_membar (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } +static int +model_frv_lrai (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_lrad (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_tlbpr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + static int model_frv_cop1 (SIM_CPU *current_cpu, void *sem_arg) { @@ -10898,6 +10786,70 @@ model_frv_cmqsubhus (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } +static int +model_frv_mqlclrhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mqlmths (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mqsllhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_frv_mqsrahi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + static int model_frv_maddaccs (SIM_CPU *current_cpu, void *sem_arg) { @@ -16252,102 +16204,6 @@ model_fr550_stc (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } -static int -model_fr550_rstb (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_fr550_rsth (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_fr550_rst (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_fr550_rstbf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_fr550_rsthf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_fr550_rstf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - static int model_fr550_std (SIM_CPU *current_cpu, void *sem_arg) { @@ -16416,38 +16272,6 @@ model_fr550_stdc (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } -static int -model_fr550_rstd (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_fr550_rstdf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - static int model_fr550_stq (SIM_CPU *current_cpu, void *sem_arg) { @@ -16496,38 +16320,6 @@ model_fr550_stqc (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } -static int -model_fr550_rstq (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_smulcc.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_fr550_rstqf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - static int model_fr550_stbu (SIM_CPU *current_cpu, void *sem_arg) { @@ -20583,7 +20375,16 @@ model_fr550_calll (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); } return cycles; #undef FLD @@ -20622,7 +20423,14 @@ model_fr550_callil (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + referenced |= 1 << 0; + referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); } return cycles; #undef FLD @@ -23744,7 +23552,16 @@ model_fr550_ccalll (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); } return cycles; #undef FLD @@ -24062,6 +23879,54 @@ model_fr550_membar (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } +static int +model_fr550_lrai (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_lrad (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_tlbpr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + static int model_fr550_cop1 (SIM_CPU *current_cpu, void *sem_arg) { @@ -27353,6 +27218,70 @@ model_fr550_cmqsubhus (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } +static int +model_fr550_mqlclrhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mqlmths (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mqsllhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr550_mqsrahi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + static int model_fr550_maddaccs (SIM_CPU *current_cpu, void *sem_arg) { @@ -33250,162 +33179,6 @@ model_fr500_stc (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } -static int -model_fr500_rstb (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT in_GRk = -1; - INT in_GRdoublek = -1; - in_GRi = FLD (in_GRi); - in_GRj = FLD (in_GRj); - in_GRk = FLD (in_GRk); - referenced |= 1 << 0; - referenced |= 1 << 1; - referenced |= 1 << 2; - cycles += frvbf_model_fr500_u_gr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); - } - return cycles; -#undef FLD -} - -static int -model_fr500_rsth (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT in_GRk = -1; - INT in_GRdoublek = -1; - in_GRi = FLD (in_GRi); - in_GRj = FLD (in_GRj); - in_GRk = FLD (in_GRk); - referenced |= 1 << 0; - referenced |= 1 << 1; - referenced |= 1 << 2; - cycles += frvbf_model_fr500_u_gr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); - } - return cycles; -#undef FLD -} - -static int -model_fr500_rst (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT in_GRk = -1; - INT in_GRdoublek = -1; - in_GRi = FLD (in_GRi); - in_GRj = FLD (in_GRj); - in_GRk = FLD (in_GRk); - referenced |= 1 << 0; - referenced |= 1 << 1; - referenced |= 1 << 2; - cycles += frvbf_model_fr500_u_gr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); - } - return cycles; -#undef FLD -} - -static int -model_fr500_rstbf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT in_FRintk = -1; - INT in_FRdoublek = -1; - in_GRi = FLD (in_GRi); - in_GRj = FLD (in_GRj); - in_FRintk = FLD (in_FRintk); - referenced |= 1 << 0; - referenced |= 1 << 1; - referenced |= 1 << 2; - cycles += frvbf_model_fr500_u_fr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); - } - return cycles; -#undef FLD -} - -static int -model_fr500_rsthf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT in_FRintk = -1; - INT in_FRdoublek = -1; - in_GRi = FLD (in_GRi); - in_GRj = FLD (in_GRj); - in_FRintk = FLD (in_FRintk); - referenced |= 1 << 0; - referenced |= 1 << 1; - referenced |= 1 << 2; - cycles += frvbf_model_fr500_u_fr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); - } - return cycles; -#undef FLD -} - -static int -model_fr500_rstf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT in_FRintk = -1; - INT in_FRdoublek = -1; - in_GRi = FLD (in_GRi); - in_GRj = FLD (in_GRj); - in_FRintk = FLD (in_FRintk); - referenced |= 1 << 0; - referenced |= 1 << 1; - referenced |= 1 << 2; - cycles += frvbf_model_fr500_u_fr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); - } - return cycles; -#undef FLD -} - static int model_fr500_std (SIM_CPU *current_cpu, void *sem_arg) { @@ -33474,58 +33247,6 @@ model_fr500_stdc (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } -static int -model_fr500_rstd (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT in_GRk = -1; - INT in_GRdoublek = -1; - in_GRi = FLD (in_GRi); - in_GRj = FLD (in_GRj); - in_GRdoublek = FLD (in_GRdoublek); - referenced |= 1 << 0; - referenced |= 1 << 1; - referenced |= 1 << 3; - cycles += frvbf_model_fr500_u_gr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); - } - return cycles; -#undef FLD -} - -static int -model_fr500_rstdf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT in_FRintk = -1; - INT in_FRdoublek = -1; - in_GRi = FLD (in_GRi); - in_GRj = FLD (in_GRj); - in_FRdoublek = FLD (in_FRdoublek); - referenced |= 1 << 0; - referenced |= 1 << 1; - referenced |= 1 << 3; - cycles += frvbf_model_fr500_u_fr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); - } - return cycles; -#undef FLD -} - static int model_fr500_stq (SIM_CPU *current_cpu, void *sem_arg) { @@ -33590,54 +33311,6 @@ model_fr500_stqc (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } -static int -model_fr500_rstq (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_smulcc.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT in_GRk = -1; - INT in_GRdoublek = -1; - in_GRi = FLD (in_GRi); - in_GRj = FLD (in_GRj); - referenced |= 1 << 0; - referenced |= 1 << 1; - cycles += frvbf_model_fr500_u_gr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); - } - return cycles; -#undef FLD -} - -static int -model_fr500_rstqf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT in_FRintk = -1; - INT in_FRdoublek = -1; - in_GRi = FLD (in_GRi); - in_GRj = FLD (in_GRj); - referenced |= 1 << 0; - referenced |= 1 << 1; - cycles += frvbf_model_fr500_u_fr_r_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); - } - return cycles; -#undef FLD -} - static int model_fr500_stbu (SIM_CPU *current_cpu, void *sem_arg) { @@ -41223,6 +40896,54 @@ model_fr500_membar (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } +static int +model_fr500_lrai (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_lrad (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_tlbpr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + static int model_fr500_cop1 (SIM_CPU *current_cpu, void *sem_arg) { @@ -44863,6 +44584,70 @@ model_fr500_cmqsubhus (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } +static int +model_fr500_mqlclrhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mqlmths (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mqsllhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr500_mqsrahi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + static int model_fr500_maddaccs (SIM_CPU *current_cpu, void *sem_arg) { @@ -49217,102 +49002,6 @@ model_tomcat_stc (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } -static int -model_tomcat_rstb (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_tomcat_rsth (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_tomcat_rst (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_tomcat_rstbf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_tomcat_rsthf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_tomcat_rstf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - static int model_tomcat_std (SIM_CPU *current_cpu, void *sem_arg) { @@ -49361,38 +49050,6 @@ model_tomcat_stdc (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } -static int -model_tomcat_rstd (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_tomcat_rstdf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - static int model_tomcat_stq (SIM_CPU *current_cpu, void *sem_arg) { @@ -49441,38 +49098,6 @@ model_tomcat_stqc (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } -static int -model_tomcat_rstq (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_smulcc.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_tomcat_rstqf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - static int model_tomcat_stbu (SIM_CPU *current_cpu, void *sem_arg) { @@ -54897,6 +54522,54 @@ model_tomcat_membar (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } +static int +model_tomcat_lrai (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_lrad (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_tlbpr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + static int model_tomcat_cop1 (SIM_CPU *current_cpu, void *sem_arg) { @@ -57249,6 +56922,70 @@ model_tomcat_cmqsubhus (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } +static int +model_tomcat_mqlclrhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mqlmths (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mqsllhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_tomcat_mqsrahi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + static int model_tomcat_maddaccs (SIM_CPU *current_cpu, void *sem_arg) { @@ -58511,17 +58248,7 @@ model_fr400_nsdiv (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT out_GRk = -1; - INT out_ICCi_1 = -1; - in_GRi = FLD (in_GRi); - in_GRj = FLD (in_GRj); - out_GRk = FLD (out_GRk); - referenced |= 1 << 0; - referenced |= 1 << 1; - referenced |= 1 << 2; - cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); } return cycles; #undef FLD @@ -58563,17 +58290,7 @@ model_fr400_nudiv (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT out_GRk = -1; - INT out_ICCi_1 = -1; - in_GRi = FLD (in_GRi); - in_GRj = FLD (in_GRj); - out_GRk = FLD (out_GRk); - referenced |= 1 << 0; - referenced |= 1 << 1; - referenced |= 1 << 2; - cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); } return cycles; #undef FLD @@ -59996,6 +59713,22 @@ model_fr400_sdivi (SIM_CPU *current_cpu, void *sem_arg) static int model_fr400_nsdivi (SIM_CPU *current_cpu, void *sem_arg) { +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_udivi (SIM_CPU *current_cpu, void *sem_arg) +{ #define FLD(f) abuf->fields.sfmt_swapi.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; @@ -60018,9 +59751,25 @@ model_fr400_nsdivi (SIM_CPU *current_cpu, void *sem_arg) } static int -model_fr400_udivi (SIM_CPU *current_cpu, void *sem_arg) +model_fr400_nudivi (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_smuli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -60029,20 +59778,44 @@ model_fr400_udivi (SIM_CPU *current_cpu, void *sem_arg) int UNUSED insn_referenced = abuf->written; INT in_GRi = -1; INT in_GRj = -1; - INT out_GRk = -1; + INT out_GRdoublek = -1; INT out_ICCi_1 = -1; in_GRi = FLD (in_GRi); - out_GRk = FLD (out_GRk); + out_GRdoublek = FLD (out_GRdoublek); referenced |= 1 << 0; referenced |= 1 << 2; - cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + cycles += frvbf_model_fr400_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); } return cycles; #undef FLD } static int -model_fr400_nudivi (SIM_CPU *current_cpu, void *sem_arg) +model_fr400_umuli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRdoublek = FLD (out_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr400_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr400_slli (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_swapi.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); @@ -60059,16 +59832,16 @@ model_fr400_nudivi (SIM_CPU *current_cpu, void *sem_arg) out_GRk = FLD (out_GRk); referenced |= 1 << 0; referenced |= 1 << 2; - cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); } return cycles; #undef FLD } static int -model_fr400_smuli (SIM_CPU *current_cpu, void *sem_arg) +model_fr400_srli (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_smuli.f +#define FLD(f) abuf->fields.sfmt_swapi.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -60077,22 +59850,22 @@ model_fr400_smuli (SIM_CPU *current_cpu, void *sem_arg) int UNUSED insn_referenced = abuf->written; INT in_GRi = -1; INT in_GRj = -1; - INT out_GRdoublek = -1; + INT out_GRk = -1; INT out_ICCi_1 = -1; in_GRi = FLD (in_GRi); - out_GRdoublek = FLD (out_GRdoublek); + out_GRk = FLD (out_GRk); referenced |= 1 << 0; referenced |= 1 << 2; - cycles += frvbf_model_fr400_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); } return cycles; #undef FLD } static int -model_fr400_umuli (SIM_CPU *current_cpu, void *sem_arg) +model_fr400_srai (SIM_CPU *current_cpu, void *sem_arg) { -#define FLD(f) abuf->fields.sfmt_smuli.f +#define FLD(f) abuf->fields.sfmt_swapi.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); const IDESC * UNUSED idesc = abuf->idesc; int cycles = 0; @@ -60101,92 +59874,20 @@ model_fr400_umuli (SIM_CPU *current_cpu, void *sem_arg) int UNUSED insn_referenced = abuf->written; INT in_GRi = -1; INT in_GRj = -1; - INT out_GRdoublek = -1; + INT out_GRk = -1; INT out_ICCi_1 = -1; in_GRi = FLD (in_GRi); - out_GRdoublek = FLD (out_GRdoublek); + out_GRk = FLD (out_GRk); referenced |= 1 << 0; referenced |= 1 << 2; - cycles += frvbf_model_fr400_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); } return cycles; #undef FLD } static int -model_fr400_slli (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_swapi.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT out_GRk = -1; - INT out_ICCi_1 = -1; - in_GRi = FLD (in_GRi); - out_GRk = FLD (out_GRk); - referenced |= 1 << 0; - referenced |= 1 << 2; - cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); - } - return cycles; -#undef FLD -} - -static int -model_fr400_srli (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_swapi.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT out_GRk = -1; - INT out_ICCi_1 = -1; - in_GRi = FLD (in_GRi); - out_GRk = FLD (out_GRk); - referenced |= 1 << 0; - referenced |= 1 << 2; - cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); - } - return cycles; -#undef FLD -} - -static int -model_fr400_srai (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_swapi.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - INT in_GRi = -1; - INT in_GRj = -1; - INT out_GRk = -1; - INT out_ICCi_1 = -1; - in_GRi = FLD (in_GRi); - out_GRk = FLD (out_GRk); - referenced |= 1 << 0; - referenced |= 1 << 2; - cycles += frvbf_model_fr400_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); - } - return cycles; -#undef FLD -} - -static int -model_fr400_scani (SIM_CPU *current_cpu, void *sem_arg) +model_fr400_scani (SIM_CPU *current_cpu, void *sem_arg) { #define FLD(f) abuf->fields.sfmt_swapi.f const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); @@ -62367,102 +62068,6 @@ model_fr400_stc (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } -static int -model_fr400_rstb (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_fr400_rsth (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_fr400_rst (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_fr400_rstbf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_fr400_rsthf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_fr400_rstf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - static int model_fr400_std (SIM_CPU *current_cpu, void *sem_arg) { @@ -62531,38 +62136,6 @@ model_fr400_stdc (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } -static int -model_fr400_rstd (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_fr400_rstdf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - static int model_fr400_stq (SIM_CPU *current_cpu, void *sem_arg) { @@ -62611,38 +62184,6 @@ model_fr400_stqc (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } -static int -model_fr400_rstq (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_smulcc.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_fr400_rstqf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - static int model_fr400_stbu (SIM_CPU *current_cpu, void *sem_arg) { @@ -70200,6 +69741,54 @@ model_fr400_membar (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } +static int +model_fr400_lrai (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_lrad (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_tlbpr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + static int model_fr400_cop1 (SIM_CPU *current_cpu, void *sem_arg) { @@ -72912,6 +72501,70 @@ model_fr400_cmqsubhus (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } +static int +model_fr400_mqlclrhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mqlmths (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mqsllhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr400_mqsrahi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + static int model_fr400_maddaccs (SIM_CPU *current_cpu, void *sem_arg) { @@ -74436,6 +74089,16051 @@ model_fr400_fnop (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } +static int +model_fr450_add (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_and (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_or (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_xor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_not (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_scutss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sdiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nsdiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_udiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nudiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_smul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_umul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_smu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smass.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_smass (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smass.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_smsss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smass.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sll (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_srl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_slass (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_scutss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_scutss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_scan (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cadd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_csub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cand (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cxor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cnot (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_csmul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_csdiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cudiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_csll (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_csrl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_csra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cscan (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_addcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_subcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_andcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_orcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_xorcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sllcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_srlcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sracc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_smulcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_umulcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_caddcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_csubcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_csmulcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_csmulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_candcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_corcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cxorcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_csllcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_csrlcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_csracc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_caddcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_addx (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_subx (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_addxcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_subxcc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_addss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_subss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_addi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_subi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_andi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ori (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_xori (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sdivi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nsdivi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_udivi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nudivi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_smuli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRdoublek = FLD (out_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_umuli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRdoublek = FLD (out_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_slli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_srli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_srai (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_scani (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_addicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_subicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_andicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_oricc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_xoricc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_smulicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRdoublek = FLD (out_GRdoublek); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_umulicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRdoublek = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRdoublek = FLD (out_GRdoublek); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sllicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_srlicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sraicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_addxi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_subxi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_addxicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_subxicc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addicc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 2; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmpb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmpba (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_ICCi_1 = FLD (out_ICCi_1); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_setlo (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_setlo.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT out_GRkhi = -1; + INT out_GRklo = -1; + out_GRklo = FLD (out_GRklo); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_set_hilo (current_cpu, idesc, 0, referenced, out_GRkhi, out_GRklo); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sethi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_sethi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT out_GRkhi = -1; + INT out_GRklo = -1; + out_GRkhi = FLD (out_GRkhi); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_set_hilo (current_cpu, idesc, 0, referenced, out_GRkhi, out_GRklo); + } + return cycles; +#undef FLD +} + +static int +model_fr450_setlos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_setlos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_ICCi_1 = -1; + out_GRk = FLD (out_GRk); + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldsb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldsh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_lduh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldhf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldsb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldsh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nlduh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_addcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldhf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_lddf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRdoublek = FLD (out_FRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_lddc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nlddf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldqf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldqc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldqf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldsbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldubu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldshu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_lduhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldsbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldubu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldshu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nlduhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldhfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldhfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_lddu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nlddu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_lddfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRdoublek = FLD (out_FRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_lddcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nlddfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldqu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldqu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldqfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldqcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldqfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldsbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldshi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldubi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_lduhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldbfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldhfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldsbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldubi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldshi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nlduhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldbfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldhfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_lddi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 4)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_lddfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + out_FRdoublek = FLD (out_FRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nlddi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smuli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nlddfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldqi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ldqfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nldqfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sth (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_st (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sthf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_std (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRdoublek = FLD (in_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stdf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRdoublek = FLD (in_FRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stdc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_smulcc.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stqf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stqc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sthu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sthfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stdu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRdoublek = FLD (in_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stdfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRdoublek = FLD (in_FRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stdcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stqu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stqfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stqcu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdcu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cldsb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cldub (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cldsh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_clduh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cldbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cldhf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cldf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cldd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_clddf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cldq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cldsbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 8)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cldubu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 8)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cldshu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 8)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_clduhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 8)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cldu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldsbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 8)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cldbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cldhfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cldfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cldbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_clddu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + INT out_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRdoublek = FLD (out_GRdoublek); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 7)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_clddfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_clddfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_FRintk = -1; + INT out_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_FRdoublek = FLD (out_FRdoublek); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cldqu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cstb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_csth (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cst (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cstbf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_csthf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cstf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cstd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRdoublek = FLD (in_GRdoublek); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cstdf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRdoublek = FLD (in_FRdoublek); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cstq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cstbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_csthu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cstu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRk = FLD (in_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cstbfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_csthfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cstfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstbfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRintk = FLD (in_FRintk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cstdu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_GRdoublek = FLD (in_GRdoublek); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cstdfu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cstdfu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FRdoublek = FLD (in_FRdoublek); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 1)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sthi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sti (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRk = FLD (in_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stbfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_sthfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_FRintk = FLD (in_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stdi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_GRk = -1; + INT in_GRdoublek = -1; + in_GRi = FLD (in_GRi); + in_GRdoublek = FLD (in_GRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stdfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_FRintk = -1; + INT in_FRdoublek = -1; + in_GRi = FLD (in_GRi); + in_FRdoublek = FLD (in_FRdoublek); + referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stqi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_stqfi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stdfi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_swap (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_swap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_swapi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + in_GRi = FLD (in_GRi); + out_GRk = FLD (out_GRk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_swap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cswap (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cswap.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT out_GRk = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + out_GRk = FLD (out_GRk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_swap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_movgf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRj = -1; + INT out_FRintk = -1; + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_movfg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintk = -1; + INT out_GRj = -1; + in_FRintk = FLD (in_FRintk); + out_GRj = FLD (out_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr450_movgfd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRj = -1; + INT out_FRintk = -1; + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 4)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_movfgd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintk = -1; + INT out_GRj = -1; + in_FRintk = FLD (in_FRintk); + out_GRj = FLD (out_GRj); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 4)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr450_movgfq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movgfq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_movfgq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movfgq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmovgf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRj = -1; + INT out_FRintk = -1; + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmovfg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintk = -1; + INT out_GRj = -1; + in_FRintk = FLD (in_FRintk); + out_GRj = FLD (out_GRj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmovgfd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovgfd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRj = -1; + INT out_FRintk = -1; + in_GRj = FLD (in_GRj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 6)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmovfgd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmovfgd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintk = -1; + INT out_GRj = -1; + in_FRintk = FLD (in_FRintk); + out_GRj = FLD (out_GRj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 6)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr450_movgs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movgs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRj = -1; + INT out_spr = -1; + in_GRj = FLD (in_GRj); + out_spr = FLD (out_spr); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_gr2spr (current_cpu, idesc, 0, referenced, in_GRj, out_spr); + } + return cycles; +#undef FLD +} + +static int +model_fr450_movsg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_movsg.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_spr = -1; + INT out_GRj = -1; + in_spr = FLD (in_spr); + out_GRj = FLD (out_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_spr2gr (current_cpu, idesc, 0, referenced, in_spr, out_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_beq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ble (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_blt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bnc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bn (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bnv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_beq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fblg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fblt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fble (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbo (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fbne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bctrlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bralr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bnolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_beqlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bnelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_blelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bgtlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bltlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bgelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_blslr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bhilr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bclr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bnclr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bnlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bplr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bvlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bnvlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbralr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbnolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbeqlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbnelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fblglr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbuelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbullr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbgelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbltlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbugelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbuglr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fblelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbgtlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbulelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbulr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fbolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 3)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bcralr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bcnolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bceqlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bcnelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bclelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bcgtlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bcltlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bcgelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bclslr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bchilr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bcclr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bcnclr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bcnlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bcplr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bcvlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bcnvlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_bceqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_ICCi_2 = FLD (in_ICCi_2); + referenced |= 1 << 2; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcbralr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + if (insn_referenced & (1 << 5)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcbnolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcbeqlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcbnelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcblglr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcbuelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcbullr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcbgelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcbltlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcbugelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcbuglr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcblelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcbgtlr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcbulelr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcbulr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcbolr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcbeqlr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_FCCi_2 = FLD (in_FCCi_2); + referenced |= 1 << 3; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_jmpl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_calll (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_jmpil (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + referenced |= 1 << 0; + referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_callil (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + referenced |= 1 << 0; + referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_call (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_call.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_rett (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_rett.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_rei (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_teq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tlt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_thi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tnc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tn (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tnv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_teq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fteq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftlg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftlt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fto (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tira (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tino (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tieq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tine (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tile (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tigt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tilt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tige (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tils (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tihi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tic (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tinc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tin (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tip (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tiv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tinv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_tieq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_ICCi_2 = FLD (in_ICCi_2); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftira (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftino (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftine (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftieq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftilg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftiue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftiul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftige (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftilt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftiuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftiug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftile (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftigt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftiule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftiu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ftio (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ftine.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_FCCi_2 = FLD (in_FCCi_2); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_break (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_break.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mtrap (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_andcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_orcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_xorcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nandcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_norcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_andncr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_orncr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nandncr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_norncr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_notcr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_andcr.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ckra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ckno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ckeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ckne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ckle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ckgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cklt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ckge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ckls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ckhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ckc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cknc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ckn (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ckp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ckv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cknv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fckra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fckno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fckne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fckeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcklg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fckue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fckul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fckge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcklt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fckuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fckug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fckle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fckgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fckule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcku (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcko (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cckra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cckno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cckeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cckne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cckle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cckgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ccklt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cckge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cckls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cckhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cckc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ccknc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cckn (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cckp (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cckv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ccknv (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cckeq.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_ICCi_3 = FLD (in_ICCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfckra (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfckno (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfckne (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfckeq (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfcklg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfckue (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfckul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfckge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfcklt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfckuge (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfckug (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfckle (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfckgt (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfckule (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfcku (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfcko (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfckne.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ICCi_3 = -1; + INT in_FCCi_3 = -1; + in_FCCi_3 = FLD (in_FCCi_3); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cjmpl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ccalll (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cjmpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + INT in_ICCi_2 = -1; + INT in_FCCi_2 = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 6)) referenced |= 1 << 4; + cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); + } + return cycles; +#undef FLD +} + +static int +model_fr450_ici (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_ici (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr450_dci (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_dci (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr450_icei (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icei.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_ici (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr450_dcei (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icei.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_dci (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr450_dcf (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_dcf (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr450_dcef (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icei.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_dcf (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr450_witlb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_wdtlb (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_itlbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_dtlbi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_icpl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_icpl (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr450_dcpl (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_icpl.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + in_GRj = FLD (in_GRj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_dcpl (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr450_icul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_icul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr450_dcul (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_jmpil.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_GRi = -1; + INT in_GRj = -1; + in_GRi = FLD (in_GRi); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_dcul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj); + } + return cycles; +#undef FLD +} + +static int +model_fr450_bar (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_barrier (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_membar (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_membar (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_lrai (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_lrad (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_tlbpr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cop1 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cop2 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_clrgr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_swapi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_clrfr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_clrga (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_clrfa (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_commitgr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_setlos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_commitfr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsethis.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_commitga (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_commitfa (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fitos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fitod (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fitod.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdtoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdtoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fditos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfditos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfdstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfitos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfitos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfitos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fditos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfstoi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdstoi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fmovs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fmovd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdmovs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfmovs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fnegs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fnegd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdnegs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfnegs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fabss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fabsd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdabss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfabss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfdsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fsqrtd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfsqrts (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_faddd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fsubd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fmuld (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdivd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfdivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfdivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcmps (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfcmps.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fcmpd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fcmpd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfcmps (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfcmps.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdcmps (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_nfdcmps.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fmsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fmaddd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fmsubd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fmaddd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfdmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfmsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfmadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfmsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfdmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfdmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cfmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cfmas.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fmad (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fmsd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfmas (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfmss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fddivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdsads (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fdmulcs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfdmulcs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfdadds (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfdsubs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfdmuls (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfddivs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfdsads (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_fdmadds.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_nfdcmps (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_nfdcmps.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mhsetlos (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsetlos.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT out_FRkhi = -1; + INT out_FRklo = -1; + out_FRklo = FLD (out_FRklo); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_hilo (current_cpu, idesc, 0, referenced, out_FRkhi, out_FRklo); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mhsethis (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsethis.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT out_FRkhi = -1; + INT out_FRklo = -1; + out_FRkhi = FLD (out_FRkhi); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_media_hilo (current_cpu, idesc, 0, referenced, out_FRkhi, out_FRklo); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mhdsets (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhdsets.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mhsetloh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsetloh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT out_FRkhi = -1; + INT out_FRklo = -1; + out_FRklo = FLD (out_FRklo); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_hilo (current_cpu, idesc, 0, referenced, out_FRkhi, out_FRklo); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mhsethih (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhsethih.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT out_FRkhi = -1; + INT out_FRklo = -1; + out_FRkhi = FLD (out_FRkhi); + referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_media_hilo (current_cpu, idesc, 0, referenced, out_FRkhi, out_FRklo); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mhdseth (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mhdseth.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mand (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mxor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmand (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmxor (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 4)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mnot (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmnot (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmand.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 3)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mrotli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mrotri (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mwcut (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mwcuti (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mcut (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_FRintk = -1; + in_ACC40Si = FLD (in_ACC40Si); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mcuti (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_FRintk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mcutss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_FRintk = -1; + in_ACC40Si = FLD (in_ACC40Si); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mcutssi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_FRintk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mdcutssi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdcutssi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT out_FRintk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_FRintk = FLD (out_FRintkeven); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_media_4_acc_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_maveh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcut.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_msllhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_msllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_msrlhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_msllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_msrahi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_msllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_6 (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mdrotli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdrotli.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_3_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mcplhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcplhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_3_dual (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mcpli (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_3_dual (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_msaths (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqsaths (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_msathu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mcmpsh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcmpsh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FCCk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FCCk = FLD (out_FCCk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_7 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FCCk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mcmpuh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcmpsh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FCCk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_FCCk = FLD (out_FCCk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_7 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FCCk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mabshs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mabshs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRintj = FLD (in_FRintj); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_maddhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_maddhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_msubhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_msubhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + referenced |= 1 << 0; + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmaddhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmaddhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmsubhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmsubhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqaddhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqaddhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqsubhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqsubhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmqaddhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmqaddhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmqsubhss (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmqsubhus (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqlclrhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqlmths (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqsllhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintieven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_3_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqsrahi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintieven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_3_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_maddaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT out_ACC40Sk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 4)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_2_acc (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_msubaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT out_ACC40Sk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 4)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_2_acc (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mdaddaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT out_ACC40Sk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 6)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_2_acc_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mdsubaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT out_ACC40Sk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 6)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_2_acc_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_masaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT out_ACC40Sk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 4)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_2_add_sub (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mdasaccs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT out_ACC40Sk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 6)) referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_2_add_sub_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mmulhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mmulhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mmulxhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mmulxhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmmulhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmmulhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqmulhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqmulhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqmulxhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqmulxhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmqmulhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 15)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmqmulhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 15)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mmachu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Uk = FLD (out_ACC40Uk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mmrdhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mmrdhu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Uk = FLD (out_ACC40Uk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmmachu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Uk = FLD (out_ACC40Uk); + if (insn_referenced & (1 << 2)) referenced |= 1 << 0; + if (insn_referenced & (1 << 3)) referenced |= 1 << 1; + if (insn_referenced & (1 << 13)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 17)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqmachu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Uk = FLD (out_ACC40Uk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 17)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmqmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 19)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmqmachu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachu.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Uk = FLD (out_ACC40Uk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 19)) referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqxmachs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 17)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqxmacxhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 17)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqmacxhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 17)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mcpxrs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mcpxru (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mcpxis (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mcpxiu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + if (insn_referenced & (1 << 1)) referenced |= 1 << 1; + if (insn_referenced & (1 << 9)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmcpxrs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmcpxru (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmcpxis (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmcpxiu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + in_FRinti = FLD (in_FRinti); + in_FRintj = FLD (in_FRintj); + out_ACC40Sk = FLD (out_ACC40Sk); + if (insn_referenced & (1 << 1)) referenced |= 1 << 0; + if (insn_referenced & (1 << 2)) referenced |= 1 << 1; + if (insn_referenced & (1 << 11)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqcpxrs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqcpxru (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqcpxis (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mqcpxiu (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_ACC40Uk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + if (insn_referenced & (1 << 13)) referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mexpdhw (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhw.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + cycles += frvbf_model_fr450_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmexpdhw (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhw.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + cycles += frvbf_model_fr450_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mexpdhd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmexpdhd (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmexpdhd.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mpackh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + cycles += frvbf_model_fr450_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mdpackh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdpackh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT in_FRintj = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRintieven); + in_FRintj = FLD (in_FRintjeven); + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_3_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_munpackh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_munpackh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_FRintk = FLD (out_FRintkeven); + if (insn_referenced & (1 << 0)) referenced |= 1 << 0; + cycles += frvbf_model_fr450_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mdunpackh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdunpackh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mbtoh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtoh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmbtoh (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtoh.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRinti = -1; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintkeven); + cycles += frvbf_model_fr450_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mhtob (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmhtob.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintj = -1; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintk); + in_FRintj = FLD (in_FRintjeven); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_dual_htob (current_cpu, idesc, 0, referenced, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmhtob (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmhtob.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_FRintj = -1; + INT out_FRintk = -1; + out_FRintk = FLD (out_FRintk); + in_FRintj = FLD (in_FRintjeven); + referenced |= 1 << 1; + cycles += frvbf_model_fr450_u_media_dual_htob (current_cpu, idesc, 0, referenced, in_FRintj, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mbtohe (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtohe.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_cmbtohe (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmbtohe.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mnop (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mclracc_0 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_FRintk = -1; + cycles += frvbf_model_fr450_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mclracc_1 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mdasaccs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_media_4_mclracca (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mrdacc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mcuti.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_FRintk = -1; + in_ACC40Si = FLD (in_ACC40Si); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mrdaccg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mrdaccg.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACCGi = -1; + INT in_FRinti = -1; + INT out_ACCGk = -1; + INT out_FRintk = -1; + in_ACCGi = FLD (in_ACCGi); + out_FRintk = FLD (out_FRintk); + referenced |= 1 << 0; + referenced |= 1 << 3; + cycles += frvbf_model_fr450_u_media_4_accg (current_cpu, idesc, 0, referenced, in_ACCGi, in_FRinti, out_ACCGk, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mwtacc (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmmachs.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACC40Si = -1; + INT in_FRintj = -1; + INT out_ACC40Sk = -1; + INT out_FRintk = -1; + out_ACC40Sk = FLD (out_ACC40Sk); + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mwtaccg (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mwtaccg.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + INT in_ACCGi = -1; + INT in_FRinti = -1; + INT out_ACCGk = -1; + INT out_FRintk = -1; + in_FRinti = FLD (in_FRinti); + out_ACCGk = FLD (out_ACCGk); + referenced |= 1 << 1; + referenced |= 1 << 2; + cycles += frvbf_model_fr450_u_media_4_accg (current_cpu, idesc, 0, referenced, in_ACCGi, in_FRinti, out_ACCGk, out_FRintk); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mcop1 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_mcop2 (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_fr450_fnop (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + static int model_simple_add (SIM_CPU *current_cpu, void *sem_arg) { @@ -77268,102 +92966,6 @@ model_simple_stc (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } -static int -model_simple_rstb (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_simple_rsth (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_simple_rst (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_simple_rstbf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_simple_rsthf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_simple_rstf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - static int model_simple_std (SIM_CPU *current_cpu, void *sem_arg) { @@ -77412,38 +93014,6 @@ model_simple_stdc (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } -static int -model_simple_rstd (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_simple_rstdf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - static int model_simple_stq (SIM_CPU *current_cpu, void *sem_arg) { @@ -77492,38 +93062,6 @@ model_simple_stqc (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } -static int -model_simple_rstq (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_smulcc.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - -static int -model_simple_rstqf (SIM_CPU *current_cpu, void *sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdfu.f - const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); - const IDESC * UNUSED idesc = abuf->idesc; - int cycles = 0; - { - int referenced = 0; - int UNUSED insn_referenced = abuf->written; - cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); - } - return cycles; -#undef FLD -} - static int model_simple_stbu (SIM_CPU *current_cpu, void *sem_arg) { @@ -82948,6 +98486,54 @@ model_simple_membar (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } +static int +model_simple_lrai (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_lrad (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_tlbpr (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + static int model_simple_cop1 (SIM_CPU *current_cpu, void *sem_arg) { @@ -85300,6 +100886,70 @@ model_simple_cmqsubhus (SIM_CPU *current_cpu, void *sem_arg) #undef FLD } +static int +model_simple_mqlclrhs (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mqlmths (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mqsllhi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + +static int +model_simple_mqsrahi (SIM_CPU *current_cpu, void *sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); + const IDESC * UNUSED idesc = abuf->idesc; + int cycles = 0; + { + int referenced = 0; + int UNUSED insn_referenced = abuf->written; + cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced); + } + return cycles; +#undef FLD +} + static int model_simple_maddaccs (SIM_CPU *current_cpu, void *sem_arg) { @@ -86561,22 +102211,12 @@ static const INSN_TIMING frv_timing[] = { { FRVBF_INSN_STHF, model_frv_sthf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STF, model_frv_stf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STC, model_frv_stc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTB, model_frv_rstb, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTH, model_frv_rsth, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RST, model_frv_rst, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTBF, model_frv_rstbf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTHF, model_frv_rsthf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTF, model_frv_rstf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STD, model_frv_std, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STDF, model_frv_stdf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STDC, model_frv_stdc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTD, model_frv_rstd, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTDF, model_frv_rstdf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STQ, model_frv_stq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STQF, model_frv_stqf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STQC, model_frv_stqc, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTQ, model_frv_rstq, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTQF, model_frv_rstqf, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STBU, model_frv_stbu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STHU, model_frv_sthu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STU, model_frv_stu, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, @@ -86916,6 +102556,9 @@ static const INSN_TIMING frv_timing[] = { { FRVBF_INSN_DCUL, model_frv_dcul, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_BAR, model_frv_bar, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MEMBAR, model_frv_membar, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LRAI, model_frv_lrai, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LRAD, model_frv_lrad, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TLBPR, model_frv_tlbpr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_COP1, model_frv_cop1, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_COP2, model_frv_cop2, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_CLRGR, model_frv_clrgr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, @@ -87063,6 +102706,10 @@ static const INSN_TIMING frv_timing[] = { { FRVBF_INSN_CMQADDHUS, model_frv_cmqaddhus, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_CMQSUBHSS, model_frv_cmqsubhss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_CMQSUBHUS, model_frv_cmqsubhus, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQLCLRHS, model_frv_mqlclrhs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQLMTHS, model_frv_mqlmths, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQSLLHI, model_frv_mqsllhi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQSRAHI, model_frv_mqsrahi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MADDACCS, model_frv_maddaccs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MSUBACCS, model_frv_msubaccs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MDADDACCS, model_frv_mdaddaccs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } }, @@ -87318,22 +102965,12 @@ static const INSN_TIMING fr550_timing[] = { { FRVBF_INSN_STHF, model_fr550_sthf, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } }, { FRVBF_INSN_STF, model_fr550_stf, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } }, { FRVBF_INSN_STC, model_fr550_stc, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTB, model_fr550_rstb, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTH, model_fr550_rsth, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RST, model_fr550_rst, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTBF, model_fr550_rstbf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTHF, model_fr550_rsthf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTF, model_fr550_rstf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STD, model_fr550_std, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } }, { FRVBF_INSN_STDF, model_fr550_stdf, { { (int) UNIT_FR550_U_FR_STORE, 1, 1 } } }, { FRVBF_INSN_STDC, model_fr550_stdc, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTD, model_fr550_rstd, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTDF, model_fr550_rstdf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STQ, model_fr550_stq, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STQF, model_fr550_stqf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STQC, model_fr550_stqc, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTQ, model_fr550_rstq, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTQF, model_fr550_rstqf, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STBU, model_fr550_stbu, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } }, { FRVBF_INSN_STHU, model_fr550_sthu, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } }, { FRVBF_INSN_STU, model_fr550_stu, { { (int) UNIT_FR550_U_GR_STORE, 1, 1 } } }, @@ -87509,9 +103146,9 @@ static const INSN_TIMING fr550_timing[] = { { FRVBF_INSN_FCBULR, model_fr550_fcbulr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, { FRVBF_INSN_FCBOLR, model_fr550_fcbolr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, { FRVBF_INSN_JMPL, model_fr550_jmpl, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, - { FRVBF_INSN_CALLL, model_fr550_calll, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CALLL, model_fr550_calll, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, { FRVBF_INSN_JMPIL, model_fr550_jmpil, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, - { FRVBF_INSN_CALLIL, model_fr550_callil, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CALLIL, model_fr550_callil, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, { FRVBF_INSN_CALL, model_fr550_call, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, { FRVBF_INSN_RETT, model_fr550_rett, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, { FRVBF_INSN_REI, model_fr550_rei, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, @@ -87656,7 +103293,7 @@ static const INSN_TIMING fr550_timing[] = { { FRVBF_INSN_CFCKU, model_fr550_cfcku, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, { FRVBF_INSN_CFCKO, model_fr550_cfcko, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } }, { FRVBF_INSN_CJMPL, model_fr550_cjmpl, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, - { FRVBF_INSN_CCALLL, model_fr550_ccalll, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CCALLL, model_fr550_ccalll, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } }, { FRVBF_INSN_ICI, model_fr550_ici, { { (int) UNIT_FR550_U_ICI, 1, 1 } } }, { FRVBF_INSN_DCI, model_fr550_dci, { { (int) UNIT_FR550_U_DCI, 1, 1 } } }, { FRVBF_INSN_ICEI, model_fr550_icei, { { (int) UNIT_FR550_U_ICI, 1, 1 } } }, @@ -87673,6 +103310,9 @@ static const INSN_TIMING fr550_timing[] = { { FRVBF_INSN_DCUL, model_fr550_dcul, { { (int) UNIT_FR550_U_DCUL, 1, 1 } } }, { FRVBF_INSN_BAR, model_fr550_bar, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MEMBAR, model_fr550_membar, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LRAI, model_fr550_lrai, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LRAD, model_fr550_lrad, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TLBPR, model_fr550_tlbpr, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, { FRVBF_INSN_COP1, model_fr550_cop1, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, { FRVBF_INSN_COP2, model_fr550_cop2, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, { FRVBF_INSN_CLRGR, model_fr550_clrgr, { { (int) UNIT_FR550_U_CLRGR, 1, 1 } } }, @@ -87820,6 +103460,10 @@ static const INSN_TIMING fr550_timing[] = { { FRVBF_INSN_CMQADDHUS, model_fr550_cmqaddhus, { { (int) UNIT_FR550_U_MEDIA_QUAD, 1, 1 } } }, { FRVBF_INSN_CMQSUBHSS, model_fr550_cmqsubhss, { { (int) UNIT_FR550_U_MEDIA_QUAD, 1, 1 } } }, { FRVBF_INSN_CMQSUBHUS, model_fr550_cmqsubhus, { { (int) UNIT_FR550_U_MEDIA_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQLCLRHS, model_fr550_mqlclrhs, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQLMTHS, model_fr550_mqlmths, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQSLLHI, model_fr550_mqsllhi, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQSRAHI, model_fr550_mqsrahi, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MADDACCS, model_fr550_maddaccs, { { (int) UNIT_FR550_U_MEDIA_4_ACC, 1, 1 } } }, { FRVBF_INSN_MSUBACCS, model_fr550_msubaccs, { { (int) UNIT_FR550_U_MEDIA_4_ACC, 1, 1 } } }, { FRVBF_INSN_MDADDACCS, model_fr550_mdaddaccs, { { (int) UNIT_FR550_U_MEDIA_4_ACC_DUAL, 1, 1 } } }, @@ -88075,22 +103719,12 @@ static const INSN_TIMING fr500_timing[] = { { FRVBF_INSN_STHF, model_fr500_sthf, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } }, { FRVBF_INSN_STF, model_fr500_stf, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } }, { FRVBF_INSN_STC, model_fr500_stc, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTB, model_fr500_rstb, { { (int) UNIT_FR500_U_GR_R_STORE, 1, 1 } } }, - { FRVBF_INSN_RSTH, model_fr500_rsth, { { (int) UNIT_FR500_U_GR_R_STORE, 1, 1 } } }, - { FRVBF_INSN_RST, model_fr500_rst, { { (int) UNIT_FR500_U_GR_R_STORE, 1, 1 } } }, - { FRVBF_INSN_RSTBF, model_fr500_rstbf, { { (int) UNIT_FR500_U_FR_R_STORE, 1, 1 } } }, - { FRVBF_INSN_RSTHF, model_fr500_rsthf, { { (int) UNIT_FR500_U_FR_R_STORE, 1, 1 } } }, - { FRVBF_INSN_RSTF, model_fr500_rstf, { { (int) UNIT_FR500_U_FR_R_STORE, 1, 1 } } }, { FRVBF_INSN_STD, model_fr500_std, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, { FRVBF_INSN_STDF, model_fr500_stdf, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } }, { FRVBF_INSN_STDC, model_fr500_stdc, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTD, model_fr500_rstd, { { (int) UNIT_FR500_U_GR_R_STORE, 1, 1 } } }, - { FRVBF_INSN_RSTDF, model_fr500_rstdf, { { (int) UNIT_FR500_U_FR_R_STORE, 1, 1 } } }, { FRVBF_INSN_STQ, model_fr500_stq, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, { FRVBF_INSN_STQF, model_fr500_stqf, { { (int) UNIT_FR500_U_FR_STORE, 1, 1 } } }, { FRVBF_INSN_STQC, model_fr500_stqc, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTQ, model_fr500_rstq, { { (int) UNIT_FR500_U_GR_R_STORE, 1, 1 } } }, - { FRVBF_INSN_RSTQF, model_fr500_rstqf, { { (int) UNIT_FR500_U_FR_R_STORE, 1, 1 } } }, { FRVBF_INSN_STBU, model_fr500_stbu, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, { FRVBF_INSN_STHU, model_fr500_sthu, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, { FRVBF_INSN_STU, model_fr500_stu, { { (int) UNIT_FR500_U_GR_STORE, 1, 1 } } }, @@ -88430,6 +104064,9 @@ static const INSN_TIMING fr500_timing[] = { { FRVBF_INSN_DCUL, model_fr500_dcul, { { (int) UNIT_FR500_U_DCUL, 1, 1 } } }, { FRVBF_INSN_BAR, model_fr500_bar, { { (int) UNIT_FR500_U_BARRIER, 1, 1 } } }, { FRVBF_INSN_MEMBAR, model_fr500_membar, { { (int) UNIT_FR500_U_MEMBAR, 1, 1 } } }, + { FRVBF_INSN_LRAI, model_fr500_lrai, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LRAD, model_fr500_lrad, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TLBPR, model_fr500_tlbpr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, { FRVBF_INSN_COP1, model_fr500_cop1, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, { FRVBF_INSN_COP2, model_fr500_cop2, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, { FRVBF_INSN_CLRGR, model_fr500_clrgr, { { (int) UNIT_FR500_U_CLRGR, 1, 1 } } }, @@ -88577,6 +104214,10 @@ static const INSN_TIMING fr500_timing[] = { { FRVBF_INSN_CMQADDHUS, model_fr500_cmqaddhus, { { (int) UNIT_FR500_U_MEDIA_QUAD_ARITH, 1, 1 } } }, { FRVBF_INSN_CMQSUBHSS, model_fr500_cmqsubhss, { { (int) UNIT_FR500_U_MEDIA_QUAD_ARITH, 1, 1 } } }, { FRVBF_INSN_CMQSUBHUS, model_fr500_cmqsubhus, { { (int) UNIT_FR500_U_MEDIA_QUAD_ARITH, 1, 1 } } }, + { FRVBF_INSN_MQLCLRHS, model_fr500_mqlclrhs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQLMTHS, model_fr500_mqlmths, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQSLLHI, model_fr500_mqsllhi, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQSRAHI, model_fr500_mqsrahi, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MADDACCS, model_fr500_maddaccs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MSUBACCS, model_fr500_msubaccs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MDADDACCS, model_fr500_mdaddaccs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } }, @@ -88832,22 +104473,12 @@ static const INSN_TIMING tomcat_timing[] = { { FRVBF_INSN_STHF, model_tomcat_sthf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STF, model_tomcat_stf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STC, model_tomcat_stc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTB, model_tomcat_rstb, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTH, model_tomcat_rsth, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RST, model_tomcat_rst, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTBF, model_tomcat_rstbf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTHF, model_tomcat_rsthf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTF, model_tomcat_rstf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STD, model_tomcat_std, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STDF, model_tomcat_stdf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STDC, model_tomcat_stdc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTD, model_tomcat_rstd, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTDF, model_tomcat_rstdf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STQ, model_tomcat_stq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STQF, model_tomcat_stqf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STQC, model_tomcat_stqc, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTQ, model_tomcat_rstq, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTQF, model_tomcat_rstqf, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STBU, model_tomcat_stbu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STHU, model_tomcat_sthu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STU, model_tomcat_stu, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, @@ -89187,6 +104818,9 @@ static const INSN_TIMING tomcat_timing[] = { { FRVBF_INSN_DCUL, model_tomcat_dcul, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_BAR, model_tomcat_bar, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MEMBAR, model_tomcat_membar, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LRAI, model_tomcat_lrai, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LRAD, model_tomcat_lrad, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TLBPR, model_tomcat_tlbpr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_COP1, model_tomcat_cop1, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_COP2, model_tomcat_cop2, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_CLRGR, model_tomcat_clrgr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, @@ -89334,6 +104968,10 @@ static const INSN_TIMING tomcat_timing[] = { { FRVBF_INSN_CMQADDHUS, model_tomcat_cmqaddhus, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_CMQSUBHSS, model_tomcat_cmqsubhss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_CMQSUBHUS, model_tomcat_cmqsubhus, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQLCLRHS, model_tomcat_mqlclrhs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQLMTHS, model_tomcat_mqlmths, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQSLLHI, model_tomcat_mqsllhi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQSRAHI, model_tomcat_mqsrahi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MADDACCS, model_tomcat_maddaccs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MSUBACCS, model_tomcat_msubaccs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MDADDACCS, model_tomcat_mdaddaccs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } }, @@ -89419,9 +105057,9 @@ static const INSN_TIMING fr400_timing[] = { { FRVBF_INSN_XOR, model_fr400_xor, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, { FRVBF_INSN_NOT, model_fr400_not, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, { FRVBF_INSN_SDIV, model_fr400_sdiv, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, - { FRVBF_INSN_NSDIV, model_fr400_nsdiv, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_NSDIV, model_fr400_nsdiv, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_UDIV, model_fr400_udiv, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, - { FRVBF_INSN_NUDIV, model_fr400_nudiv, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_NUDIV, model_fr400_nudiv, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_SMUL, model_fr400_smul, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } }, { FRVBF_INSN_UMUL, model_fr400_umul, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } }, { FRVBF_INSN_SMU, model_fr400_smu, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, @@ -89477,9 +105115,9 @@ static const INSN_TIMING fr400_timing[] = { { FRVBF_INSN_ORI, model_fr400_ori, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, { FRVBF_INSN_XORI, model_fr400_xori, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, { FRVBF_INSN_SDIVI, model_fr400_sdivi, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, - { FRVBF_INSN_NSDIVI, model_fr400_nsdivi, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_NSDIVI, model_fr400_nsdivi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_UDIVI, model_fr400_udivi, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, - { FRVBF_INSN_NUDIVI, model_fr400_nudivi, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_NUDIVI, model_fr400_nudivi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_SMULI, model_fr400_smuli, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } }, { FRVBF_INSN_UMULI, model_fr400_umuli, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } }, { FRVBF_INSN_SLLI, model_fr400_slli, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } }, @@ -89589,22 +105227,12 @@ static const INSN_TIMING fr400_timing[] = { { FRVBF_INSN_STHF, model_fr400_sthf, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } }, { FRVBF_INSN_STF, model_fr400_stf, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } }, { FRVBF_INSN_STC, model_fr400_stc, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTB, model_fr400_rstb, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTH, model_fr400_rsth, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RST, model_fr400_rst, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTBF, model_fr400_rstbf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTHF, model_fr400_rsthf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTF, model_fr400_rstf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STD, model_fr400_std, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } }, { FRVBF_INSN_STDF, model_fr400_stdf, { { (int) UNIT_FR400_U_FR_STORE, 1, 1 } } }, { FRVBF_INSN_STDC, model_fr400_stdc, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTD, model_fr400_rstd, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTDF, model_fr400_rstdf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STQ, model_fr400_stq, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STQF, model_fr400_stqf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STQC, model_fr400_stqc, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTQ, model_fr400_rstq, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTQF, model_fr400_rstqf, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STBU, model_fr400_stbu, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } }, { FRVBF_INSN_STHU, model_fr400_sthu, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } }, { FRVBF_INSN_STU, model_fr400_stu, { { (int) UNIT_FR400_U_GR_STORE, 1, 1 } } }, @@ -89944,6 +105572,9 @@ static const INSN_TIMING fr400_timing[] = { { FRVBF_INSN_DCUL, model_fr400_dcul, { { (int) UNIT_FR400_U_DCUL, 1, 1 } } }, { FRVBF_INSN_BAR, model_fr400_bar, { { (int) UNIT_FR400_U_BARRIER, 1, 1 } } }, { FRVBF_INSN_MEMBAR, model_fr400_membar, { { (int) UNIT_FR400_U_MEMBAR, 1, 1 } } }, + { FRVBF_INSN_LRAI, model_fr400_lrai, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LRAD, model_fr400_lrad, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TLBPR, model_fr400_tlbpr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_COP1, model_fr400_cop1, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_COP2, model_fr400_cop2, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_CLRGR, model_fr400_clrgr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, @@ -90091,6 +105722,10 @@ static const INSN_TIMING fr400_timing[] = { { FRVBF_INSN_CMQADDHUS, model_fr400_cmqaddhus, { { (int) UNIT_FR400_U_MEDIA_1_QUAD, 1, 1 } } }, { FRVBF_INSN_CMQSUBHSS, model_fr400_cmqsubhss, { { (int) UNIT_FR400_U_MEDIA_1_QUAD, 1, 1 } } }, { FRVBF_INSN_CMQSUBHUS, model_fr400_cmqsubhus, { { (int) UNIT_FR400_U_MEDIA_1_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQLCLRHS, model_fr400_mqlclrhs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQLMTHS, model_fr400_mqlmths, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQSLLHI, model_fr400_mqsllhi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQSRAHI, model_fr400_mqsrahi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MADDACCS, model_fr400_maddaccs, { { (int) UNIT_FR400_U_MEDIA_2_ACC, 1, 1 } } }, { FRVBF_INSN_MSUBACCS, model_fr400_msubaccs, { { (int) UNIT_FR400_U_MEDIA_2_ACC, 1, 1 } } }, { FRVBF_INSN_MDADDACCS, model_fr400_mdaddaccs, { { (int) UNIT_FR400_U_MEDIA_2_ACC_DUAL, 1, 1 } } }, @@ -90160,6 +105795,760 @@ static const INSN_TIMING fr400_timing[] = { { FRVBF_INSN_FNOP, model_fr400_fnop, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } }, }; +/* Model timing data for `fr450'. */ + +static const INSN_TIMING fr450_timing[] = { + { FRVBF_INSN_X_INVALID, 0, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_AFTER, 0, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_BEFORE, 0, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_CHAIN, 0, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_X_BEGIN, 0, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ADD, model_fr450_add, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUB, model_fr450_sub, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_AND, model_fr450_and, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_OR, model_fr450_or, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_XOR, model_fr450_xor, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_NOT, model_fr450_not, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SDIV, model_fr450_sdiv, { { (int) UNIT_FR450_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_NSDIV, model_fr450_nsdiv, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_UDIV, model_fr450_udiv, { { (int) UNIT_FR450_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_NUDIV, model_fr450_nudiv, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SMUL, model_fr450_smul, { { (int) UNIT_FR450_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_UMUL, model_fr450_umul, { { (int) UNIT_FR450_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_SMU, model_fr450_smu, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SMASS, model_fr450_smass, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SMSSS, model_fr450_smsss, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SLL, model_fr450_sll, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRL, model_fr450_srl, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRA, model_fr450_sra, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SLASS, model_fr450_slass, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SCUTSS, model_fr450_scutss, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SCAN, model_fr450_scan, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CADD, model_fr450_cadd, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSUB, model_fr450_csub, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CAND, model_fr450_cand, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_COR, model_fr450_cor, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CXOR, model_fr450_cxor, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CNOT, model_fr450_cnot, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSMUL, model_fr450_csmul, { { (int) UNIT_FR450_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_CSDIV, model_fr450_csdiv, { { (int) UNIT_FR450_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_CUDIV, model_fr450_cudiv, { { (int) UNIT_FR450_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_CSLL, model_fr450_csll, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSRL, model_fr450_csrl, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSRA, model_fr450_csra, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSCAN, model_fr450_cscan, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDCC, model_fr450_addcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBCC, model_fr450_subcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ANDCC, model_fr450_andcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ORCC, model_fr450_orcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_XORCC, model_fr450_xorcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SLLCC, model_fr450_sllcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRLCC, model_fr450_srlcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRACC, model_fr450_sracc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SMULCC, model_fr450_smulcc, { { (int) UNIT_FR450_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_UMULCC, model_fr450_umulcc, { { (int) UNIT_FR450_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_CADDCC, model_fr450_caddcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSUBCC, model_fr450_csubcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSMULCC, model_fr450_csmulcc, { { (int) UNIT_FR450_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_CANDCC, model_fr450_candcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CORCC, model_fr450_corcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CXORCC, model_fr450_cxorcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSLLCC, model_fr450_csllcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSRLCC, model_fr450_csrlcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CSRACC, model_fr450_csracc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDX, model_fr450_addx, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBX, model_fr450_subx, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDXCC, model_fr450_addxcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBXCC, model_fr450_subxcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDSS, model_fr450_addss, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBSS, model_fr450_subss, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDI, model_fr450_addi, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBI, model_fr450_subi, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ANDI, model_fr450_andi, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ORI, model_fr450_ori, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_XORI, model_fr450_xori, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SDIVI, model_fr450_sdivi, { { (int) UNIT_FR450_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_NSDIVI, model_fr450_nsdivi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_UDIVI, model_fr450_udivi, { { (int) UNIT_FR450_U_IDIV, 1, 1 } } }, + { FRVBF_INSN_NUDIVI, model_fr450_nudivi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SMULI, model_fr450_smuli, { { (int) UNIT_FR450_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_UMULI, model_fr450_umuli, { { (int) UNIT_FR450_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_SLLI, model_fr450_slli, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRLI, model_fr450_srli, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRAI, model_fr450_srai, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SCANI, model_fr450_scani, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDICC, model_fr450_addicc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBICC, model_fr450_subicc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ANDICC, model_fr450_andicc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ORICC, model_fr450_oricc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_XORICC, model_fr450_xoricc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SMULICC, model_fr450_smulicc, { { (int) UNIT_FR450_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_UMULICC, model_fr450_umulicc, { { (int) UNIT_FR450_U_IMUL, 1, 1 } } }, + { FRVBF_INSN_SLLICC, model_fr450_sllicc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRLICC, model_fr450_srlicc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SRAICC, model_fr450_sraicc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDXI, model_fr450_addxi, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBXI, model_fr450_subxi, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_ADDXICC, model_fr450_addxicc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SUBXICC, model_fr450_subxicc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CMPB, model_fr450_cmpb, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_CMPBA, model_fr450_cmpba, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_SETLO, model_fr450_setlo, { { (int) UNIT_FR450_U_SET_HILO, 1, 1 } } }, + { FRVBF_INSN_SETHI, model_fr450_sethi, { { (int) UNIT_FR450_U_SET_HILO, 1, 1 } } }, + { FRVBF_INSN_SETLOS, model_fr450_setlos, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } }, + { FRVBF_INSN_LDSB, model_fr450_ldsb, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDUB, model_fr450_ldub, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDSH, model_fr450_ldsh, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDUH, model_fr450_lduh, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LD, model_fr450_ld, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDBF, model_fr450_ldbf, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDHF, model_fr450_ldhf, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDF, model_fr450_ldf, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDC, model_fr450_ldc, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDSB, model_fr450_nldsb, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUB, model_fr450_nldub, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDSH, model_fr450_nldsh, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUH, model_fr450_nlduh, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLD, model_fr450_nld, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDBF, model_fr450_nldbf, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDHF, model_fr450_nldhf, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDF, model_fr450_nldf, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDD, model_fr450_ldd, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDDF, model_fr450_lddf, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDDC, model_fr450_lddc, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDD, model_fr450_nldd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDDF, model_fr450_nlddf, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQ, model_fr450_ldq, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQF, model_fr450_ldqf, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQC, model_fr450_ldqc, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQ, model_fr450_nldq, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQF, model_fr450_nldqf, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDSBU, model_fr450_ldsbu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDUBU, model_fr450_ldubu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDSHU, model_fr450_ldshu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDUHU, model_fr450_lduhu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDU, model_fr450_ldu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDSBU, model_fr450_nldsbu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUBU, model_fr450_nldubu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDSHU, model_fr450_nldshu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUHU, model_fr450_nlduhu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDU, model_fr450_nldu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDBFU, model_fr450_ldbfu, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDHFU, model_fr450_ldhfu, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDFU, model_fr450_ldfu, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDCU, model_fr450_ldcu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDBFU, model_fr450_nldbfu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDHFU, model_fr450_nldhfu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDFU, model_fr450_nldfu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDDU, model_fr450_lddu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDDU, model_fr450_nlddu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDDFU, model_fr450_lddfu, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDDCU, model_fr450_lddcu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDDFU, model_fr450_nlddfu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQU, model_fr450_ldqu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQU, model_fr450_nldqu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQFU, model_fr450_ldqfu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQCU, model_fr450_ldqcu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQFU, model_fr450_nldqfu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDSBI, model_fr450_ldsbi, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDSHI, model_fr450_ldshi, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDI, model_fr450_ldi, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDUBI, model_fr450_ldubi, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDUHI, model_fr450_lduhi, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDBFI, model_fr450_ldbfi, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDHFI, model_fr450_ldhfi, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDFI, model_fr450_ldfi, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDSBI, model_fr450_nldsbi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUBI, model_fr450_nldubi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDSHI, model_fr450_nldshi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDUHI, model_fr450_nlduhi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDI, model_fr450_nldi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDBFI, model_fr450_nldbfi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDHFI, model_fr450_nldhfi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDFI, model_fr450_nldfi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDDI, model_fr450_lddi, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_LDDFI, model_fr450_lddfi, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_NLDDI, model_fr450_nlddi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDDFI, model_fr450_nlddfi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQI, model_fr450_ldqi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LDQFI, model_fr450_ldqfi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NLDQFI, model_fr450_nldqfi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STB, model_fr450_stb, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STH, model_fr450_sth, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_ST, model_fr450_st, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STBF, model_fr450_stbf, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STHF, model_fr450_sthf, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STF, model_fr450_stf, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STC, model_fr450_stc, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STD, model_fr450_std, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STDF, model_fr450_stdf, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STDC, model_fr450_stdc, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQ, model_fr450_stq, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQF, model_fr450_stqf, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQC, model_fr450_stqc, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STBU, model_fr450_stbu, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STHU, model_fr450_sthu, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STU, model_fr450_stu, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STBFU, model_fr450_stbfu, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STHFU, model_fr450_sthfu, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STFU, model_fr450_stfu, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STCU, model_fr450_stcu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STDU, model_fr450_stdu, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STDFU, model_fr450_stdfu, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STDCU, model_fr450_stdcu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQU, model_fr450_stqu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQFU, model_fr450_stqfu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQCU, model_fr450_stqcu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDSB, model_fr450_cldsb, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDUB, model_fr450_cldub, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDSH, model_fr450_cldsh, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDUH, model_fr450_clduh, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLD, model_fr450_cld, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDBF, model_fr450_cldbf, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDHF, model_fr450_cldhf, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDF, model_fr450_cldf, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDD, model_fr450_cldd, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDDF, model_fr450_clddf, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDQ, model_fr450_cldq, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLDSBU, model_fr450_cldsbu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDUBU, model_fr450_cldubu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDSHU, model_fr450_cldshu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDUHU, model_fr450_clduhu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDU, model_fr450_cldu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDBFU, model_fr450_cldbfu, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDHFU, model_fr450_cldhfu, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDFU, model_fr450_cldfu, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDDU, model_fr450_clddu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDDFU, model_fr450_clddfu, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } }, + { FRVBF_INSN_CLDQU, model_fr450_cldqu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTB, model_fr450_cstb, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTH, model_fr450_csth, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CST, model_fr450_cst, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTBF, model_fr450_cstbf, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTHF, model_fr450_csthf, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTF, model_fr450_cstf, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTD, model_fr450_cstd, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTDF, model_fr450_cstdf, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTQ, model_fr450_cstq, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CSTBU, model_fr450_cstbu, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTHU, model_fr450_csthu, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTU, model_fr450_cstu, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTBFU, model_fr450_cstbfu, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTHFU, model_fr450_csthfu, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTFU, model_fr450_cstfu, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTDU, model_fr450_cstdu, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_CSTDFU, model_fr450_cstdfu, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STBI, model_fr450_stbi, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STHI, model_fr450_sthi, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STI, model_fr450_sti, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STBFI, model_fr450_stbfi, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STHFI, model_fr450_sthfi, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STFI, model_fr450_stfi, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STDI, model_fr450_stdi, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } }, + { FRVBF_INSN_STDFI, model_fr450_stdfi, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } }, + { FRVBF_INSN_STQI, model_fr450_stqi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_STQFI, model_fr450_stqfi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_SWAP, model_fr450_swap, { { (int) UNIT_FR450_U_SWAP, 1, 1 } } }, + { FRVBF_INSN_SWAPI, model_fr450_swapi, { { (int) UNIT_FR450_U_SWAP, 1, 1 } } }, + { FRVBF_INSN_CSWAP, model_fr450_cswap, { { (int) UNIT_FR450_U_SWAP, 1, 1 } } }, + { FRVBF_INSN_MOVGF, model_fr450_movgf, { { (int) UNIT_FR450_U_GR2FR, 1, 1 } } }, + { FRVBF_INSN_MOVFG, model_fr450_movfg, { { (int) UNIT_FR450_U_FR2GR, 1, 1 } } }, + { FRVBF_INSN_MOVGFD, model_fr450_movgfd, { { (int) UNIT_FR450_U_GR2FR, 1, 1 } } }, + { FRVBF_INSN_MOVFGD, model_fr450_movfgd, { { (int) UNIT_FR450_U_FR2GR, 1, 1 } } }, + { FRVBF_INSN_MOVGFQ, model_fr450_movgfq, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MOVFGQ, model_fr450_movfgq, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMOVGF, model_fr450_cmovgf, { { (int) UNIT_FR450_U_GR2FR, 1, 1 } } }, + { FRVBF_INSN_CMOVFG, model_fr450_cmovfg, { { (int) UNIT_FR450_U_FR2GR, 1, 1 } } }, + { FRVBF_INSN_CMOVGFD, model_fr450_cmovgfd, { { (int) UNIT_FR450_U_GR2FR, 1, 1 } } }, + { FRVBF_INSN_CMOVFGD, model_fr450_cmovfgd, { { (int) UNIT_FR450_U_FR2GR, 1, 1 } } }, + { FRVBF_INSN_MOVGS, model_fr450_movgs, { { (int) UNIT_FR450_U_GR2SPR, 1, 1 } } }, + { FRVBF_INSN_MOVSG, model_fr450_movsg, { { (int) UNIT_FR450_U_SPR2GR, 1, 1 } } }, + { FRVBF_INSN_BRA, model_fr450_bra, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNO, model_fr450_bno, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BEQ, model_fr450_beq, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNE, model_fr450_bne, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BLE, model_fr450_ble, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BGT, model_fr450_bgt, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BLT, model_fr450_blt, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BGE, model_fr450_bge, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BLS, model_fr450_bls, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BHI, model_fr450_bhi, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BC, model_fr450_bc, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNC, model_fr450_bnc, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BN, model_fr450_bn, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BP, model_fr450_bp, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BV, model_fr450_bv, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNV, model_fr450_bnv, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBRA, model_fr450_fbra, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBNO, model_fr450_fbno, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBNE, model_fr450_fbne, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBEQ, model_fr450_fbeq, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBLG, model_fr450_fblg, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUE, model_fr450_fbue, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUL, model_fr450_fbul, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBGE, model_fr450_fbge, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBLT, model_fr450_fblt, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUGE, model_fr450_fbuge, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUG, model_fr450_fbug, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBLE, model_fr450_fble, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBGT, model_fr450_fbgt, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBULE, model_fr450_fbule, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBU, model_fr450_fbu, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBO, model_fr450_fbo, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCTRLR, model_fr450_bctrlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BRALR, model_fr450_bralr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNOLR, model_fr450_bnolr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BEQLR, model_fr450_beqlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNELR, model_fr450_bnelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BLELR, model_fr450_blelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BGTLR, model_fr450_bgtlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BLTLR, model_fr450_bltlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BGELR, model_fr450_bgelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BLSLR, model_fr450_blslr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BHILR, model_fr450_bhilr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCLR, model_fr450_bclr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNCLR, model_fr450_bnclr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNLR, model_fr450_bnlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BPLR, model_fr450_bplr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BVLR, model_fr450_bvlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BNVLR, model_fr450_bnvlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBRALR, model_fr450_fbralr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBNOLR, model_fr450_fbnolr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBEQLR, model_fr450_fbeqlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBNELR, model_fr450_fbnelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBLGLR, model_fr450_fblglr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUELR, model_fr450_fbuelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBULLR, model_fr450_fbullr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBGELR, model_fr450_fbgelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBLTLR, model_fr450_fbltlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUGELR, model_fr450_fbugelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBUGLR, model_fr450_fbuglr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBLELR, model_fr450_fblelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBGTLR, model_fr450_fbgtlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBULELR, model_fr450_fbulelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBULR, model_fr450_fbulr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FBOLR, model_fr450_fbolr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCRALR, model_fr450_bcralr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCNOLR, model_fr450_bcnolr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCEQLR, model_fr450_bceqlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCNELR, model_fr450_bcnelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCLELR, model_fr450_bclelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCGTLR, model_fr450_bcgtlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCLTLR, model_fr450_bcltlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCGELR, model_fr450_bcgelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCLSLR, model_fr450_bclslr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCHILR, model_fr450_bchilr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCCLR, model_fr450_bcclr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCNCLR, model_fr450_bcnclr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCNLR, model_fr450_bcnlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCPLR, model_fr450_bcplr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCVLR, model_fr450_bcvlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_BCNVLR, model_fr450_bcnvlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBRALR, model_fr450_fcbralr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBNOLR, model_fr450_fcbnolr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBEQLR, model_fr450_fcbeqlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBNELR, model_fr450_fcbnelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBLGLR, model_fr450_fcblglr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBUELR, model_fr450_fcbuelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBULLR, model_fr450_fcbullr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBGELR, model_fr450_fcbgelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBLTLR, model_fr450_fcbltlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBUGELR, model_fr450_fcbugelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBUGLR, model_fr450_fcbuglr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBLELR, model_fr450_fcblelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBGTLR, model_fr450_fcbgtlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBULELR, model_fr450_fcbulelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBULR, model_fr450_fcbulr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_FCBOLR, model_fr450_fcbolr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_JMPL, model_fr450_jmpl, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_CALLL, model_fr450_calll, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_JMPIL, model_fr450_jmpil, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_CALLIL, model_fr450_callil, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_CALL, model_fr450_call, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_RETT, model_fr450_rett, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_REI, model_fr450_rei, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TRA, model_fr450_tra, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TNO, model_fr450_tno, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TEQ, model_fr450_teq, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TNE, model_fr450_tne, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TLE, model_fr450_tle, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TGT, model_fr450_tgt, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TLT, model_fr450_tlt, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TGE, model_fr450_tge, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TLS, model_fr450_tls, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_THI, model_fr450_thi, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TC, model_fr450_tc, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TNC, model_fr450_tnc, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TN, model_fr450_tn, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TP, model_fr450_tp, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TV, model_fr450_tv, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TNV, model_fr450_tnv, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTRA, model_fr450_ftra, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTNO, model_fr450_ftno, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTNE, model_fr450_ftne, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTEQ, model_fr450_fteq, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTLG, model_fr450_ftlg, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTUE, model_fr450_ftue, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTUL, model_fr450_ftul, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTGE, model_fr450_ftge, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTLT, model_fr450_ftlt, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTUGE, model_fr450_ftuge, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTUG, model_fr450_ftug, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTLE, model_fr450_ftle, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTGT, model_fr450_ftgt, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTULE, model_fr450_ftule, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTU, model_fr450_ftu, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTO, model_fr450_fto, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIRA, model_fr450_tira, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TINO, model_fr450_tino, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIEQ, model_fr450_tieq, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TINE, model_fr450_tine, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TILE, model_fr450_tile, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIGT, model_fr450_tigt, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TILT, model_fr450_tilt, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIGE, model_fr450_tige, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TILS, model_fr450_tils, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIHI, model_fr450_tihi, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIC, model_fr450_tic, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TINC, model_fr450_tinc, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIN, model_fr450_tin, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIP, model_fr450_tip, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TIV, model_fr450_tiv, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_TINV, model_fr450_tinv, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIRA, model_fr450_ftira, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FTINO, model_fr450_ftino, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTINE, model_fr450_ftine, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIEQ, model_fr450_ftieq, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTILG, model_fr450_ftilg, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIUE, model_fr450_ftiue, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIUL, model_fr450_ftiul, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIGE, model_fr450_ftige, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTILT, model_fr450_ftilt, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIUGE, model_fr450_ftiuge, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIUG, model_fr450_ftiug, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTILE, model_fr450_ftile, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIGT, model_fr450_ftigt, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIULE, model_fr450_ftiule, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIU, model_fr450_ftiu, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_FTIO, model_fr450_ftio, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } }, + { FRVBF_INSN_BREAK, model_fr450_break, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MTRAP, model_fr450_mtrap, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ANDCR, model_fr450_andcr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ORCR, model_fr450_orcr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_XORCR, model_fr450_xorcr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NANDCR, model_fr450_nandcr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NORCR, model_fr450_norcr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ANDNCR, model_fr450_andncr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ORNCR, model_fr450_orncr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NANDNCR, model_fr450_nandncr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NORNCR, model_fr450_norncr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NOTCR, model_fr450_notcr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CKRA, model_fr450_ckra, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKNO, model_fr450_ckno, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKEQ, model_fr450_ckeq, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKNE, model_fr450_ckne, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKLE, model_fr450_ckle, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKGT, model_fr450_ckgt, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKLT, model_fr450_cklt, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKGE, model_fr450_ckge, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKLS, model_fr450_ckls, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKHI, model_fr450_ckhi, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKC, model_fr450_ckc, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKNC, model_fr450_cknc, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKN, model_fr450_ckn, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKP, model_fr450_ckp, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKV, model_fr450_ckv, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CKNV, model_fr450_cknv, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKRA, model_fr450_fckra, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKNO, model_fr450_fckno, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKNE, model_fr450_fckne, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKEQ, model_fr450_fckeq, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKLG, model_fr450_fcklg, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKUE, model_fr450_fckue, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKUL, model_fr450_fckul, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKGE, model_fr450_fckge, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKLT, model_fr450_fcklt, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKUGE, model_fr450_fckuge, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKUG, model_fr450_fckug, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKLE, model_fr450_fckle, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKGT, model_fr450_fckgt, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKULE, model_fr450_fckule, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKU, model_fr450_fcku, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_FCKO, model_fr450_fcko, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKRA, model_fr450_cckra, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKNO, model_fr450_cckno, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKEQ, model_fr450_cckeq, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKNE, model_fr450_cckne, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKLE, model_fr450_cckle, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKGT, model_fr450_cckgt, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKLT, model_fr450_ccklt, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKGE, model_fr450_cckge, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKLS, model_fr450_cckls, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKHI, model_fr450_cckhi, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKC, model_fr450_cckc, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKNC, model_fr450_ccknc, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKN, model_fr450_cckn, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKP, model_fr450_cckp, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKV, model_fr450_cckv, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CCKNV, model_fr450_ccknv, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKRA, model_fr450_cfckra, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKNO, model_fr450_cfckno, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKNE, model_fr450_cfckne, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKEQ, model_fr450_cfckeq, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKLG, model_fr450_cfcklg, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKUE, model_fr450_cfckue, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKUL, model_fr450_cfckul, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKGE, model_fr450_cfckge, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKLT, model_fr450_cfcklt, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKUGE, model_fr450_cfckuge, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKUG, model_fr450_cfckug, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKLE, model_fr450_cfckle, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKGT, model_fr450_cfckgt, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKULE, model_fr450_cfckule, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKU, model_fr450_cfcku, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CFCKO, model_fr450_cfcko, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } }, + { FRVBF_INSN_CJMPL, model_fr450_cjmpl, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_CCALLL, model_fr450_ccalll, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } }, + { FRVBF_INSN_ICI, model_fr450_ici, { { (int) UNIT_FR450_U_ICI, 1, 1 } } }, + { FRVBF_INSN_DCI, model_fr450_dci, { { (int) UNIT_FR450_U_DCI, 1, 1 } } }, + { FRVBF_INSN_ICEI, model_fr450_icei, { { (int) UNIT_FR450_U_ICI, 1, 1 } } }, + { FRVBF_INSN_DCEI, model_fr450_dcei, { { (int) UNIT_FR450_U_DCI, 1, 1 } } }, + { FRVBF_INSN_DCF, model_fr450_dcf, { { (int) UNIT_FR450_U_DCF, 1, 1 } } }, + { FRVBF_INSN_DCEF, model_fr450_dcef, { { (int) UNIT_FR450_U_DCF, 1, 1 } } }, + { FRVBF_INSN_WITLB, model_fr450_witlb, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_WDTLB, model_fr450_wdtlb, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ITLBI, model_fr450_itlbi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_DTLBI, model_fr450_dtlbi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_ICPL, model_fr450_icpl, { { (int) UNIT_FR450_U_ICPL, 1, 1 } } }, + { FRVBF_INSN_DCPL, model_fr450_dcpl, { { (int) UNIT_FR450_U_DCPL, 1, 1 } } }, + { FRVBF_INSN_ICUL, model_fr450_icul, { { (int) UNIT_FR450_U_ICUL, 1, 1 } } }, + { FRVBF_INSN_DCUL, model_fr450_dcul, { { (int) UNIT_FR450_U_DCUL, 1, 1 } } }, + { FRVBF_INSN_BAR, model_fr450_bar, { { (int) UNIT_FR450_U_BARRIER, 1, 1 } } }, + { FRVBF_INSN_MEMBAR, model_fr450_membar, { { (int) UNIT_FR450_U_MEMBAR, 1, 1 } } }, + { FRVBF_INSN_LRAI, model_fr450_lrai, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LRAD, model_fr450_lrad, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TLBPR, model_fr450_tlbpr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COP1, model_fr450_cop1, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COP2, model_fr450_cop2, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLRGR, model_fr450_clrgr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLRFR, model_fr450_clrfr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLRGA, model_fr450_clrga, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CLRFA, model_fr450_clrfa, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COMMITGR, model_fr450_commitgr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COMMITFR, model_fr450_commitfr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COMMITGA, model_fr450_commitga, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_COMMITFA, model_fr450_commitfa, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FITOS, model_fr450_fitos, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FSTOI, model_fr450_fstoi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FITOD, model_fr450_fitod, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDTOI, model_fr450_fdtoi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDITOS, model_fr450_fditos, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDSTOI, model_fr450_fdstoi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDITOS, model_fr450_nfditos, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDSTOI, model_fr450_nfdstoi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFITOS, model_fr450_cfitos, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFSTOI, model_fr450_cfstoi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFITOS, model_fr450_nfitos, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFSTOI, model_fr450_nfstoi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMOVS, model_fr450_fmovs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMOVD, model_fr450_fmovd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMOVS, model_fr450_fdmovs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMOVS, model_fr450_cfmovs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FNEGS, model_fr450_fnegs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FNEGD, model_fr450_fnegd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDNEGS, model_fr450_fdnegs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFNEGS, model_fr450_cfnegs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FABSS, model_fr450_fabss, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FABSD, model_fr450_fabsd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDABSS, model_fr450_fdabss, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFABSS, model_fr450_cfabss, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FSQRTS, model_fr450_fsqrts, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDSQRTS, model_fr450_fdsqrts, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDSQRTS, model_fr450_nfdsqrts, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FSQRTD, model_fr450_fsqrtd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFSQRTS, model_fr450_cfsqrts, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFSQRTS, model_fr450_nfsqrts, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FADDS, model_fr450_fadds, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FSUBS, model_fr450_fsubs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMULS, model_fr450_fmuls, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDIVS, model_fr450_fdivs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FADDD, model_fr450_faddd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FSUBD, model_fr450_fsubd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMULD, model_fr450_fmuld, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDIVD, model_fr450_fdivd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFADDS, model_fr450_cfadds, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFSUBS, model_fr450_cfsubs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMULS, model_fr450_cfmuls, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFDIVS, model_fr450_cfdivs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFADDS, model_fr450_nfadds, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFSUBS, model_fr450_nfsubs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMULS, model_fr450_nfmuls, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDIVS, model_fr450_nfdivs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCMPS, model_fr450_fcmps, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FCMPD, model_fr450_fcmpd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFCMPS, model_fr450_cfcmps, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDCMPS, model_fr450_fdcmps, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMADDS, model_fr450_fmadds, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMSUBS, model_fr450_fmsubs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMADDD, model_fr450_fmaddd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMSUBD, model_fr450_fmsubd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMADDS, model_fr450_fdmadds, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMADDS, model_fr450_nfdmadds, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMADDS, model_fr450_cfmadds, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMSUBS, model_fr450_cfmsubs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMADDS, model_fr450_nfmadds, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMSUBS, model_fr450_nfmsubs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMAS, model_fr450_fmas, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMSS, model_fr450_fmss, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMAS, model_fr450_fdmas, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMSS, model_fr450_fdmss, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMAS, model_fr450_nfdmas, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMSS, model_fr450_nfdmss, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMAS, model_fr450_cfmas, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CFMSS, model_fr450_cfmss, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMAD, model_fr450_fmad, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FMSD, model_fr450_fmsd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMAS, model_fr450_nfmas, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFMSS, model_fr450_nfmss, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDADDS, model_fr450_fdadds, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDSUBS, model_fr450_fdsubs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMULS, model_fr450_fdmuls, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDDIVS, model_fr450_fddivs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDSADS, model_fr450_fdsads, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FDMULCS, model_fr450_fdmulcs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMULCS, model_fr450_nfdmulcs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDADDS, model_fr450_nfdadds, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDSUBS, model_fr450_nfdsubs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDMULS, model_fr450_nfdmuls, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDDIVS, model_fr450_nfddivs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDSADS, model_fr450_nfdsads, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_NFDCMPS, model_fr450_nfdcmps, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MHSETLOS, model_fr450_mhsetlos, { { (int) UNIT_FR450_U_MEDIA_HILO, 1, 1 } } }, + { FRVBF_INSN_MHSETHIS, model_fr450_mhsethis, { { (int) UNIT_FR450_U_MEDIA_HILO, 1, 1 } } }, + { FRVBF_INSN_MHDSETS, model_fr450_mhdsets, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MHSETLOH, model_fr450_mhsetloh, { { (int) UNIT_FR450_U_MEDIA_HILO, 1, 1 } } }, + { FRVBF_INSN_MHSETHIH, model_fr450_mhsethih, { { (int) UNIT_FR450_U_MEDIA_HILO, 1, 1 } } }, + { FRVBF_INSN_MHDSETH, model_fr450_mhdseth, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MAND, model_fr450_mand, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MOR, model_fr450_mor, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MXOR, model_fr450_mxor, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_CMAND, model_fr450_cmand, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_CMOR, model_fr450_cmor, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_CMXOR, model_fr450_cmxor, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MNOT, model_fr450_mnot, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_CMNOT, model_fr450_cmnot, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MROTLI, model_fr450_mrotli, { { (int) UNIT_FR450_U_MEDIA_3, 1, 1 } } }, + { FRVBF_INSN_MROTRI, model_fr450_mrotri, { { (int) UNIT_FR450_U_MEDIA_3, 1, 1 } } }, + { FRVBF_INSN_MWCUT, model_fr450_mwcut, { { (int) UNIT_FR450_U_MEDIA_3, 1, 1 } } }, + { FRVBF_INSN_MWCUTI, model_fr450_mwcuti, { { (int) UNIT_FR450_U_MEDIA_3, 1, 1 } } }, + { FRVBF_INSN_MCUT, model_fr450_mcut, { { (int) UNIT_FR450_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MCUTI, model_fr450_mcuti, { { (int) UNIT_FR450_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MCUTSS, model_fr450_mcutss, { { (int) UNIT_FR450_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MCUTSSI, model_fr450_mcutssi, { { (int) UNIT_FR450_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MDCUTSSI, model_fr450_mdcutssi, { { (int) UNIT_FR450_U_MEDIA_4_ACC_DUAL, 1, 1 } } }, + { FRVBF_INSN_MAVEH, model_fr450_maveh, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MSLLHI, model_fr450_msllhi, { { (int) UNIT_FR450_U_MEDIA_3, 1, 1 } } }, + { FRVBF_INSN_MSRLHI, model_fr450_msrlhi, { { (int) UNIT_FR450_U_MEDIA_3, 1, 1 } } }, + { FRVBF_INSN_MSRAHI, model_fr450_msrahi, { { (int) UNIT_FR450_U_MEDIA_6, 1, 1 } } }, + { FRVBF_INSN_MDROTLI, model_fr450_mdrotli, { { (int) UNIT_FR450_U_MEDIA_3_QUAD, 1, 1 } } }, + { FRVBF_INSN_MCPLHI, model_fr450_mcplhi, { { (int) UNIT_FR450_U_MEDIA_3_DUAL, 1, 1 } } }, + { FRVBF_INSN_MCPLI, model_fr450_mcpli, { { (int) UNIT_FR450_U_MEDIA_3_DUAL, 1, 1 } } }, + { FRVBF_INSN_MSATHS, model_fr450_msaths, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MQSATHS, model_fr450_mqsaths, { { (int) UNIT_FR450_U_MEDIA_1_QUAD, 1, 1 } } }, + { FRVBF_INSN_MSATHU, model_fr450_msathu, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MCMPSH, model_fr450_mcmpsh, { { (int) UNIT_FR450_U_MEDIA_7, 1, 1 } } }, + { FRVBF_INSN_MCMPUH, model_fr450_mcmpuh, { { (int) UNIT_FR450_U_MEDIA_7, 1, 1 } } }, + { FRVBF_INSN_MABSHS, model_fr450_mabshs, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MADDHSS, model_fr450_maddhss, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MADDHUS, model_fr450_maddhus, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MSUBHSS, model_fr450_msubhss, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MSUBHUS, model_fr450_msubhus, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_CMADDHSS, model_fr450_cmaddhss, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_CMADDHUS, model_fr450_cmaddhus, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_CMSUBHSS, model_fr450_cmsubhss, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_CMSUBHUS, model_fr450_cmsubhus, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } }, + { FRVBF_INSN_MQADDHSS, model_fr450_mqaddhss, { { (int) UNIT_FR450_U_MEDIA_1_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQADDHUS, model_fr450_mqaddhus, { { (int) UNIT_FR450_U_MEDIA_1_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQSUBHSS, model_fr450_mqsubhss, { { (int) UNIT_FR450_U_MEDIA_1_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQSUBHUS, model_fr450_mqsubhus, { { (int) UNIT_FR450_U_MEDIA_1_QUAD, 1, 1 } } }, + { FRVBF_INSN_CMQADDHSS, model_fr450_cmqaddhss, { { (int) UNIT_FR450_U_MEDIA_1_QUAD, 1, 1 } } }, + { FRVBF_INSN_CMQADDHUS, model_fr450_cmqaddhus, { { (int) UNIT_FR450_U_MEDIA_1_QUAD, 1, 1 } } }, + { FRVBF_INSN_CMQSUBHSS, model_fr450_cmqsubhss, { { (int) UNIT_FR450_U_MEDIA_1_QUAD, 1, 1 } } }, + { FRVBF_INSN_CMQSUBHUS, model_fr450_cmqsubhus, { { (int) UNIT_FR450_U_MEDIA_1_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQLCLRHS, model_fr450_mqlclrhs, { { (int) UNIT_FR450_U_MEDIA_1_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQLMTHS, model_fr450_mqlmths, { { (int) UNIT_FR450_U_MEDIA_1_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQSLLHI, model_fr450_mqsllhi, { { (int) UNIT_FR450_U_MEDIA_3_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQSRAHI, model_fr450_mqsrahi, { { (int) UNIT_FR450_U_MEDIA_3_QUAD, 1, 1 } } }, + { FRVBF_INSN_MADDACCS, model_fr450_maddaccs, { { (int) UNIT_FR450_U_MEDIA_2_ACC, 1, 1 } } }, + { FRVBF_INSN_MSUBACCS, model_fr450_msubaccs, { { (int) UNIT_FR450_U_MEDIA_2_ACC, 1, 1 } } }, + { FRVBF_INSN_MDADDACCS, model_fr450_mdaddaccs, { { (int) UNIT_FR450_U_MEDIA_2_ACC_DUAL, 1, 1 } } }, + { FRVBF_INSN_MDSUBACCS, model_fr450_mdsubaccs, { { (int) UNIT_FR450_U_MEDIA_2_ACC_DUAL, 1, 1 } } }, + { FRVBF_INSN_MASACCS, model_fr450_masaccs, { { (int) UNIT_FR450_U_MEDIA_2_ADD_SUB, 1, 1 } } }, + { FRVBF_INSN_MDASACCS, model_fr450_mdasaccs, { { (int) UNIT_FR450_U_MEDIA_2_ADD_SUB_DUAL, 1, 1 } } }, + { FRVBF_INSN_MMULHS, model_fr450_mmulhs, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MMULHU, model_fr450_mmulhu, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MMULXHS, model_fr450_mmulxhs, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MMULXHU, model_fr450_mmulxhu, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_CMMULHS, model_fr450_cmmulhs, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_CMMULHU, model_fr450_cmmulhu, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MQMULHS, model_fr450_mqmulhs, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQMULHU, model_fr450_mqmulhu, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQMULXHS, model_fr450_mqmulxhs, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQMULXHU, model_fr450_mqmulxhu, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_CMQMULHS, model_fr450_cmqmulhs, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_CMQMULHU, model_fr450_cmqmulhu, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MMACHS, model_fr450_mmachs, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MMACHU, model_fr450_mmachu, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MMRDHS, model_fr450_mmrdhs, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MMRDHU, model_fr450_mmrdhu, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_CMMACHS, model_fr450_cmmachs, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_CMMACHU, model_fr450_cmmachu, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MQMACHS, model_fr450_mqmachs, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQMACHU, model_fr450_mqmachu, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_CMQMACHS, model_fr450_cmqmachs, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_CMQMACHU, model_fr450_cmqmachu, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQXMACHS, model_fr450_mqxmachs, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQXMACXHS, model_fr450_mqxmacxhs, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQMACXHS, model_fr450_mqmacxhs, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MCPXRS, model_fr450_mcpxrs, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MCPXRU, model_fr450_mcpxru, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MCPXIS, model_fr450_mcpxis, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MCPXIU, model_fr450_mcpxiu, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_CMCPXRS, model_fr450_cmcpxrs, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_CMCPXRU, model_fr450_cmcpxru, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_CMCPXIS, model_fr450_cmcpxis, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_CMCPXIU, model_fr450_cmcpxiu, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } }, + { FRVBF_INSN_MQCPXRS, model_fr450_mqcpxrs, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQCPXRU, model_fr450_mqcpxru, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQCPXIS, model_fr450_mqcpxis, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MQCPXIU, model_fr450_mqcpxiu, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } }, + { FRVBF_INSN_MEXPDHW, model_fr450_mexpdhw, { { (int) UNIT_FR450_U_MEDIA_3, 1, 1 } } }, + { FRVBF_INSN_CMEXPDHW, model_fr450_cmexpdhw, { { (int) UNIT_FR450_U_MEDIA_3, 1, 1 } } }, + { FRVBF_INSN_MEXPDHD, model_fr450_mexpdhd, { { (int) UNIT_FR450_U_MEDIA_DUAL_EXPAND, 1, 1 } } }, + { FRVBF_INSN_CMEXPDHD, model_fr450_cmexpdhd, { { (int) UNIT_FR450_U_MEDIA_DUAL_EXPAND, 1, 1 } } }, + { FRVBF_INSN_MPACKH, model_fr450_mpackh, { { (int) UNIT_FR450_U_MEDIA_3, 1, 1 } } }, + { FRVBF_INSN_MDPACKH, model_fr450_mdpackh, { { (int) UNIT_FR450_U_MEDIA_3_QUAD, 1, 1 } } }, + { FRVBF_INSN_MUNPACKH, model_fr450_munpackh, { { (int) UNIT_FR450_U_MEDIA_DUAL_EXPAND, 1, 1 } } }, + { FRVBF_INSN_MDUNPACKH, model_fr450_mdunpackh, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MBTOH, model_fr450_mbtoh, { { (int) UNIT_FR450_U_MEDIA_DUAL_EXPAND, 1, 1 } } }, + { FRVBF_INSN_CMBTOH, model_fr450_cmbtoh, { { (int) UNIT_FR450_U_MEDIA_DUAL_EXPAND, 1, 1 } } }, + { FRVBF_INSN_MHTOB, model_fr450_mhtob, { { (int) UNIT_FR450_U_MEDIA_DUAL_HTOB, 1, 1 } } }, + { FRVBF_INSN_CMHTOB, model_fr450_cmhtob, { { (int) UNIT_FR450_U_MEDIA_DUAL_HTOB, 1, 1 } } }, + { FRVBF_INSN_MBTOHE, model_fr450_mbtohe, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_CMBTOHE, model_fr450_cmbtohe, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MNOP, model_fr450_mnop, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCLRACC_0, model_fr450_mclracc_0, { { (int) UNIT_FR450_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MCLRACC_1, model_fr450_mclracc_1, { { (int) UNIT_FR450_U_MEDIA_4_MCLRACCA, 1, 1 } } }, + { FRVBF_INSN_MRDACC, model_fr450_mrdacc, { { (int) UNIT_FR450_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MRDACCG, model_fr450_mrdaccg, { { (int) UNIT_FR450_U_MEDIA_4_ACCG, 1, 1 } } }, + { FRVBF_INSN_MWTACC, model_fr450_mwtacc, { { (int) UNIT_FR450_U_MEDIA_4, 1, 1 } } }, + { FRVBF_INSN_MWTACCG, model_fr450_mwtaccg, { { (int) UNIT_FR450_U_MEDIA_4_ACCG, 1, 1 } } }, + { FRVBF_INSN_MCOP1, model_fr450_mcop1, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MCOP2, model_fr450_mcop2, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_FNOP, model_fr450_fnop, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } }, +}; + /* Model timing data for `simple'. */ static const INSN_TIMING simple_timing[] = { @@ -90346,22 +106735,12 @@ static const INSN_TIMING simple_timing[] = { { FRVBF_INSN_STHF, model_simple_sthf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STF, model_simple_stf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STC, model_simple_stc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTB, model_simple_rstb, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTH, model_simple_rsth, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RST, model_simple_rst, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTBF, model_simple_rstbf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTHF, model_simple_rsthf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTF, model_simple_rstf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STD, model_simple_std, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STDF, model_simple_stdf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STDC, model_simple_stdc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTD, model_simple_rstd, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTDF, model_simple_rstdf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STQ, model_simple_stq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STQF, model_simple_stqf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STQC, model_simple_stqc, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTQ, model_simple_rstq, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, - { FRVBF_INSN_RSTQF, model_simple_rstqf, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STBU, model_simple_stbu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STHU, model_simple_sthu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_STU, model_simple_stu, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, @@ -90701,6 +107080,9 @@ static const INSN_TIMING simple_timing[] = { { FRVBF_INSN_DCUL, model_simple_dcul, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_BAR, model_simple_bar, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MEMBAR, model_simple_membar, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LRAI, model_simple_lrai, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_LRAD, model_simple_lrad, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_TLBPR, model_simple_tlbpr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_COP1, model_simple_cop1, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_COP2, model_simple_cop2, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_CLRGR, model_simple_clrgr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, @@ -90848,6 +107230,10 @@ static const INSN_TIMING simple_timing[] = { { FRVBF_INSN_CMQADDHUS, model_simple_cmqaddhus, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_CMQSUBHSS, model_simple_cmqsubhss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_CMQSUBHUS, model_simple_cmqsubhus, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQLCLRHS, model_simple_mqlclrhs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQLMTHS, model_simple_mqlmths, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQSLLHI, model_simple_mqsllhi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, + { FRVBF_INSN_MQSRAHI, model_simple_mqsrahi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MADDACCS, model_simple_maddaccs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MSUBACCS, model_simple_msubaccs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, { FRVBF_INSN_MDADDACCS, model_simple_mdaddaccs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } }, @@ -90949,6 +107335,12 @@ fr400_model_init (SIM_CPU *cpu) CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_FR400_DATA)); } +static void +fr450_model_init (SIM_CPU *cpu) +{ + CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_FR450_DATA)); +} + static void simple_model_init (SIM_CPU *cpu) { @@ -90991,6 +107383,12 @@ static const MODEL fr400_models[] = { 0 } }; +static const MODEL fr450_models[] = +{ + { "fr450", & fr450_mach, MODEL_FR450, TIMING_DATA (& fr450_timing[0]), fr450_model_init }, + { 0 } +}; + static const MODEL simple_models[] = { { "simple", & simple_mach, MODEL_SIMPLE, TIMING_DATA (& simple_timing[0]), simple_model_init }, @@ -91153,6 +107551,32 @@ const MACH fr400_mach = frvbf_prepare_run }; +static void +fr450_init_cpu (SIM_CPU *cpu) +{ + CPU_REG_FETCH (cpu) = frvbf_fetch_register; + CPU_REG_STORE (cpu) = frvbf_store_register; + CPU_PC_FETCH (cpu) = frvbf_h_pc_get; + CPU_PC_STORE (cpu) = frvbf_h_pc_set; + CPU_GET_IDATA (cpu) = frvbf_get_idata; + CPU_MAX_INSNS (cpu) = FRVBF_INSN__MAX; + CPU_INSN_NAME (cpu) = cgen_insn_name; + CPU_FULL_ENGINE_FN (cpu) = frvbf_engine_run_full; +#if WITH_FAST + CPU_FAST_ENGINE_FN (cpu) = frvbf_engine_run_fast; +#else + CPU_FAST_ENGINE_FN (cpu) = frvbf_engine_run_full; +#endif +} + +const MACH fr450_mach = +{ + "fr450", "fr450", MACH_FR450, + 32, 32, & fr450_models[0], & frvbf_imp_properties, + fr450_init_cpu, + frvbf_prepare_run +}; + static void simple_init_cpu (SIM_CPU *cpu) { diff --git a/sim/frv/profile-fr450.c b/sim/frv/profile-fr450.c new file mode 100644 index 00000000000..27b97558e37 --- /dev/null +++ b/sim/frv/profile-fr450.c @@ -0,0 +1,607 @@ +/* frv simulator fr450 dependent profiling code. + + Copyright (C) 2001, 2004 Free Software Foundation, Inc. + Contributed by Red Hat + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ +#define WANT_CPU +#define WANT_CPU_FRVBF + +#include "sim-main.h" +#include "bfd.h" + +#if WITH_PROFILE_MODEL_P + +#include "profile.h" +#include "profile-fr400.h" + +int +frvbf_model_fr450_u_exec (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced) +{ + return idesc->timing->units[unit_num].done; +} + +int +frvbf_model_fr450_u_integer (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, INT out_GRk, + INT out_ICCi_1) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_integer (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj, out_GRk, out_ICCi_1); +} + +int +frvbf_model_fr450_u_imul (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* Pass 1 is the same as for fr500. */ + return frvbf_model_fr500_u_imul (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + + /* icc0-icc4 are the upper 4 fields of the CCR. */ + if (out_ICCi_1 >= 0) + out_ICCi_1 += 4; + + /* GRk and IACCi_1 have a latency of 1 cycle. */ + cycles = idesc->timing->units[unit_num].done; + update_GRdouble_latency (cpu, out_GRk, cycles + 1); + update_CCR_latency (cpu, out_ICCi_1, cycles + 1); + + return cycles; +} + +int +frvbf_model_fr450_u_idiv (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* Pass 1 is the same as for fr500. */ + return frvbf_model_fr500_u_idiv (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj, out_GRk, out_ICCi_1); + } + + /* icc0-icc4 are the upper 4 fields of the CCR. */ + if (out_ICCi_1 >= 0) + out_ICCi_1 += 4; + + /* GRk, ICCi_1 and the divider have a latency of 18 cycles */ + cycles = idesc->timing->units[unit_num].done; + update_GR_latency (cpu, out_GRk, cycles + 18); + update_CCR_latency (cpu, out_ICCi_1, cycles + 18); + update_idiv_resource_latency (cpu, 0, cycles + 18); + + return cycles; +} + +int +frvbf_model_fr450_u_branch (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, + INT in_ICCi_2, INT in_ICCi_3) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_branch (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj, in_ICCi_2, in_ICCi_3); +} + +int +frvbf_model_fr450_u_trap (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, + INT in_ICCi_2, INT in_FCCi_2) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_trap (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); +} + +int +frvbf_model_fr450_u_check (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_ICCi_3, INT in_FCCi_3) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_check (cpu, idesc, unit_num, referenced, + in_ICCi_3, in_FCCi_3); +} + +int +frvbf_model_fr450_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT out_GRkhi, INT out_GRklo) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_set_hilo (cpu, idesc, unit_num, referenced, + out_GRkhi, out_GRklo); +} + +int +frvbf_model_fr450_u_gr_load (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, + INT out_GRk, INT out_GRdoublek) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* Pass 1 is the same as for fr500. */ + return frvbf_model_fr500_u_fr_load (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj, out_GRk, + out_GRdoublek); + } + + cycles = idesc->timing->units[unit_num].done; + + /* The latency of GRk for a load will depend on how long it takes to retrieve + the the data from the cache or memory. */ + update_GR_latency_for_load (cpu, out_GRk, cycles); + update_GRdouble_latency_for_load (cpu, out_GRdoublek, cycles); + + if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING)) + { + /* GNER has a latency of 2 cycles. */ + update_SPR_latency (cpu, GNER_FOR_GR (out_GRk), cycles + 2); + update_SPR_latency (cpu, GNER_FOR_GR (out_GRdoublek), cycles + 2); + } + + return cycles; +} + +int +frvbf_model_fr450_u_gr_store (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, + INT in_GRk, INT in_GRdoublek) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_gr_store (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj, in_GRk, in_GRdoublek); +} + +int +frvbf_model_fr450_u_fr_load (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, + INT out_FRk, INT out_FRdoublek) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_fr_load (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj, out_FRk, out_FRdoublek); +} + +int +frvbf_model_fr450_u_fr_store (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, + INT in_FRk, INT in_FRdoublek) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_fr_load (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj, in_FRk, in_FRdoublek); +} + +int +frvbf_model_fr450_u_swap (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj, INT out_GRk) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_swap (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj, out_GRk); +} + +int +frvbf_model_fr450_u_fr2gr (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRk, INT out_GRj) +{ + int cycles; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + { + /* Pass 1 is the same as for fr400. */ + return frvbf_model_fr500_u_fr2gr (cpu, idesc, unit_num, referenced, + in_FRk, out_GRj); + } + + /* The latency of GRj is 1 cycle. */ + cycles = idesc->timing->units[unit_num].done; + update_GR_latency (cpu, out_GRj, cycles + 1); + + return cycles; +} + +int +frvbf_model_fr450_u_spr2gr (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_spr, INT out_GRj) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_spr2gr (cpu, idesc, unit_num, referenced, + in_spr, out_GRj); +} + +int +frvbf_model_fr450_u_gr2fr (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRj, INT out_FRk) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_gr2fr (cpu, idesc, unit_num, referenced, + in_GRj, out_FRk); +} + +int +frvbf_model_fr450_u_gr2spr (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRj, INT out_spr) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_gr2spr (cpu, idesc, unit_num, referenced, + in_GRj, out_spr); +} + +int +frvbf_model_fr450_u_media_1 (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, + INT out_FRk) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_media_1 (cpu, idesc, unit_num, referenced, + in_FRi, in_FRj, out_FRk); +} + +int +frvbf_model_fr450_u_media_1_quad (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, + INT out_FRk) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_media_1_quad (cpu, idesc, unit_num, referenced, + in_FRi, in_FRj, out_FRk); +} + +int +frvbf_model_fr450_u_media_hilo (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT out_FRkhi, INT out_FRklo) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_media_hilo (cpu, idesc, unit_num, referenced, + out_FRkhi, out_FRklo); +} + +int +frvbf_model_fr450_u_media_2 (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, + INT out_ACC40Sk, INT out_ACC40Uk) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_media_2 (cpu, idesc, unit_num, referenced, + in_FRi, in_FRj, out_ACC40Sk, + out_ACC40Uk); +} + +int +frvbf_model_fr450_u_media_2_quad (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, + INT out_ACC40Sk, INT out_ACC40Uk) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_media_2_quad (cpu, idesc, unit_num, referenced, + in_FRi, in_FRj, out_ACC40Sk, + out_ACC40Uk); +} + +int +frvbf_model_fr450_u_media_2_acc (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_ACC40Si, INT out_ACC40Sk) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_media_2_acc (cpu, idesc, unit_num, referenced, + in_ACC40Si, out_ACC40Sk); +} + +int +frvbf_model_fr450_u_media_2_acc_dual (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_ACC40Si, INT out_ACC40Sk) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_media_2_acc_dual (cpu, idesc, unit_num, + referenced, in_ACC40Si, + out_ACC40Sk); +} + +int +frvbf_model_fr450_u_media_2_add_sub (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_ACC40Si, INT out_ACC40Sk) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_media_2_add_sub (cpu, idesc, unit_num, + referenced, in_ACC40Si, + out_ACC40Sk); +} + +int +frvbf_model_fr450_u_media_2_add_sub_dual (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_ACC40Si, INT out_ACC40Sk) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_media_2_add_sub_dual (cpu, idesc, unit_num, + referenced, in_ACC40Si, + out_ACC40Sk); +} + +int +frvbf_model_fr450_u_media_3 (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, + INT out_FRk) +{ + /* Modelling is the same as media unit 1. */ + return frvbf_model_fr450_u_media_1 (cpu, idesc, unit_num, referenced, + in_FRi, in_FRj, out_FRk); +} + +int +frvbf_model_fr450_u_media_3_dual (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT out_FRk) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_media_3_dual (cpu, idesc, unit_num, referenced, + in_FRi, out_FRk); +} + +int +frvbf_model_fr450_u_media_3_quad (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT in_FRj, + INT out_FRk) +{ + /* Modelling is the same as media unit 1. */ + return frvbf_model_fr450_u_media_1_quad (cpu, idesc, unit_num, referenced, + in_FRi, in_FRj, out_FRk); +} + +int +frvbf_model_fr450_u_media_4 (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_ACC40Si, INT in_FRj, + INT out_ACC40Sk, INT out_FRk) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_media_4 (cpu, idesc, unit_num, referenced, + in_ACC40Si, in_FRj, + out_ACC40Sk, out_FRk); +} + +int +frvbf_model_fr450_u_media_4_accg (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_ACCGi, INT in_FRinti, + INT out_ACCGk, INT out_FRintk) +{ + /* Modelling is the same as media-4 unit except use accumulator guards + as input instead of accumulators. */ + return frvbf_model_fr450_u_media_4 (cpu, idesc, unit_num, referenced, + in_ACCGi, in_FRinti, + out_ACCGk, out_FRintk); +} + +int +frvbf_model_fr450_u_media_4_acc_dual (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_ACC40Si, INT out_FRk) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_media_4_acc_dual (cpu, idesc, unit_num, + referenced, in_ACC40Si, + out_FRk); +} + +int +frvbf_model_fr450_u_media_4_mclracca (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced) +{ + int cycles; + int acc; + FRV_PROFILE_STATE *ps; + + if (model_insn == FRV_INSN_MODEL_PASS_1) + return 0; + + /* The preprocessing can execute right away. */ + cycles = idesc->timing->units[unit_num].done; + + ps = CPU_PROFILE_STATE (cpu); + + /* The post processing must wait for any pending ACC writes. */ + ps->post_wait = cycles; + for (acc = 0; acc < 4; acc++) + post_wait_for_ACC (cpu, acc); + for (acc = 8; acc < 12; acc++) + post_wait_for_ACC (cpu, acc); + + for (acc = 0; acc < 4; acc++) + { + update_ACC_latency (cpu, acc, ps->post_wait); + update_ACC_ptime (cpu, acc, 2); + } + for (acc = 8; acc < 12; acc++) + { + update_ACC_latency (cpu, acc, ps->post_wait); + update_ACC_ptime (cpu, acc, 2); + } + + return cycles; +} + +int +frvbf_model_fr450_u_media_6 (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, INT out_FRk) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_media_6 (cpu, idesc, unit_num, referenced, + in_FRi, out_FRk); +} + +int +frvbf_model_fr450_u_media_7 (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRinti, INT in_FRintj, + INT out_FCCk) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_media_7 (cpu, idesc, unit_num, referenced, + in_FRinti, in_FRintj, out_FCCk); +} + +int +frvbf_model_fr450_u_media_dual_expand (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRi, + INT out_FRk) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_media_dual_expand (cpu, idesc, unit_num, + referenced, in_FRi, out_FRk); +} + +int +frvbf_model_fr450_u_media_dual_htob (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_FRj, + INT out_FRk) +{ + /* Modelling for this unit is the same as for fr400. */ + return frvbf_model_fr400_u_media_dual_htob (cpu, idesc, unit_num, + referenced, in_FRj, out_FRk); +} + +int +frvbf_model_fr450_u_ici (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_ici (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj); +} + +int +frvbf_model_fr450_u_dci (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_dci (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj); +} + +int +frvbf_model_fr450_u_dcf (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_dcf (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj); +} + +int +frvbf_model_fr450_u_icpl (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_icpl (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj); +} + +int +frvbf_model_fr450_u_dcpl (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_dcpl (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj); +} + +int +frvbf_model_fr450_u_icul (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_icul (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj); +} + +int +frvbf_model_fr450_u_dcul (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced, + INT in_GRi, INT in_GRj) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_dcul (cpu, idesc, unit_num, referenced, + in_GRi, in_GRj); +} + +int +frvbf_model_fr450_u_barrier (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_barrier (cpu, idesc, unit_num, referenced); +} + +int +frvbf_model_fr450_u_membar (SIM_CPU *cpu, const IDESC *idesc, + int unit_num, int referenced) +{ + /* Modelling for this unit is the same as for fr500. */ + return frvbf_model_fr500_u_membar (cpu, idesc, unit_num, referenced); +} + +#endif /* WITH_PROFILE_MODEL_P */ diff --git a/sim/frv/profile.c b/sim/frv/profile.c index 3a3d1aab95a..577826fca9b 100644 --- a/sim/frv/profile.c +++ b/sim/frv/profile.c @@ -37,7 +37,8 @@ static void reset_gr_flags (SIM_CPU *cpu, INT gr) { SIM_DESC sd = CPU_STATE (cpu); - if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400) + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400 + || STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr450) fr400_reset_gr_flags (cpu, gr); /* Other machines have no gr flags right now. */ } @@ -46,7 +47,8 @@ static void reset_fr_flags (SIM_CPU *cpu, INT fr) { SIM_DESC sd = CPU_STATE (cpu); - if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400) + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400 + || STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr450) fr400_reset_fr_flags (cpu, fr); else if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr500) fr500_reset_fr_flags (cpu, fr); @@ -56,7 +58,8 @@ static void reset_acc_flags (SIM_CPU *cpu, INT acc) { SIM_DESC sd = CPU_STATE (cpu); - if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400) + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400 + || STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr450) fr400_reset_acc_flags (cpu, acc); /* Other machines have no acc flags right now. */ } @@ -926,6 +929,7 @@ frvbf_model_insn_before (SIM_CPU *cpu, int first_p) switch (STATE_ARCHITECTURE (sd)->mach) { case bfd_mach_fr400: + case bfd_mach_fr450: fr400_model_insn_before (cpu, first_p); break; case bfd_mach_fr500: @@ -992,6 +996,7 @@ frvbf_model_insn_after (SIM_CPU *cpu, int last_p, int cycles) switch (STATE_ARCHITECTURE (sd)->mach) { case bfd_mach_fr400: + case bfd_mach_fr450: fr400_model_insn_after (cpu, last_p, cycles); break; case bfd_mach_fr500: diff --git a/sim/frv/registers.c b/sim/frv/registers.c index 685e53f7f56..aa65bb29723 100644 --- a/sim/frv/registers.c +++ b/sim/frv/registers.c @@ -5301,6 +5301,1047 @@ static FRV_SPR_CONTROL_INFO fr400_spr[] = RESERVED }; +/* SPR definitions for the fr450 machine. + See the FR451 LSI for implementation details. */ +static FRV_SPR_CONTROL_INFO fr450_spr[] = +{ + {0x200030fe, 0x200030fc, 0xf00030fd, 0xffffff80, IMPL, SUP}, /* PSR */ + {0x00000000, 0x00000000, 0x00000003, 0x00000003, IMPL, SUP}, /* PCSR */ + {0x00000000, 0x00000000, 0xffffffff, 0x00000003, IMPL, SUP}, /* BPCSR */ + {0x00000000, 0x00000000, 0x0000000f, 0x00000fff, IMPL, SUP}, /* TBR */ + {0x00000000, 0x00000000, 0x00000000, 0xffffeffe, IMPL, SUP}, /* BPSR */ + + /* spr registers 5-15 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, + + {0x00000d40, 0x00000d40, 0xcc400fc0, 0x20742ff8, IMPL, SUP}, /* HSR0 */ + + /* spr registers 17-255 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* CCR */ + + /* spr registers 257-262 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffff0000, IMPL, USER}, /* CCCR */ + + /* spr registers 264-271 are reserved */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000003, 0x00000003, IMPL, USER}, /* LR */ + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* LCR */ + + /* spr registers 274-279 and reserved. */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* IACC0H */ + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* IACC0L */ + + /* spr registers 282-287 and reserved. */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + {0x20000021, 0x20000000, 0xa0000000, 0xffffffc2, IMPL, USER}, /* ISR */ + + /* spr registers 289-511 are reserved */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EPCR0 */ + + /* spr registers 513-575 are reserved */ + RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, + + {0x00000100, 0x00000100, 0x00000100, 0xffffffff, IMPL, SUP}, /* ESR0 */ + + /* spr registers 577-589 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESR14 */ + {0x00000800, 0x00000800, 0x00000800, 0xffffffff, IMPL, SUP}, + + /* spr registers 592-672 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESFR1 */ + + /* spr registers 674-831 are reserved */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, SUP}, /* SCR0 */ + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, SUP}, + + /* spr registers 836-1279 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x01c00000, 0x0fff8fc0, IMPL, USER}, /* MSR0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffcd, IMPL, USER}, + + /* spr registers 1282-1407 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + /* Accumulators are read-only by the user except for special insns and + side effect of other insns. ACC0-3 (1408-1411) and ACC8-11 (1416-1419) + are implemented, ACC4-7 are not. */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACC0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + + RESERVED, RESERVED, RESERVED, + RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACC8 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + + /* spr registers 1420-1471 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + /* Accumulator guards (1472-1483). See comments above ACC0. */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACCG0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + + RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACCG8 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, + + /* spr registers 1484-1535 are reserved */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EAR0 */ + + /* spr registers 1537-1550 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EAR15 */ + + /* spr registers 1552-1663 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, /* IAMLR0 */ + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, /* IAMLR7 */ + + /* spr registers 1672-1727 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0x00002902, IMPL, SUP}, /* IAMPR0 */ + {0x00000000, 0x00000000, 0x00000000, 0x00002902, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00002902, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00002902, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00002902, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00002902, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00002902, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00002902, IMPL, SUP}, /* IAMPR7 */ + + /* spr registers 1736-1791 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, /* DAMLR0 */ + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, /* DAMLR11 */ + + /* spr registers 1804-1855 are reserved */ + RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, + + {0x00000000, 0x00000000, 0x00000001, 0x00002000, IMPL, SUP}, /* DAMPR0 */ + {0x00000000, 0x00000000, 0x00000001, 0x00002000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000001, 0x00002000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000001, 0x00002000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000001, 0x00002000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000001, 0x00002000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000001, 0x00002000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000001, 0x00002000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00002000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00002000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00002000, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0x00002000, IMPL, SUP}, /* DAMPR11 */ + + /* spr registers 1868-1919 are reserved */ + RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000808, 0x00000808, 0x00000808, 0xffffffff, IMPL, SUP}, /* AMCR */ + + /* spr registers 1921-1924 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffff00, IMPL, SUP}, /* IAMVR1 */ + RESERVED, + {0x00000000, 0x00000000, 0x00000000, 0xfffff000, IMPL, SUP}, /* DAMVR1 */ + + /* spr registers 1928-1935 are reserved */ + RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xfffff000, IMPL, SUP}, /* CXNR */ + {0x00000000, 0x00000000, 0x00000000, 0x000007fc, IMPL, SUP}, /* TTBR */ + {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, /* TPLR */ + {0x00000000, 0x00000000, 0x00000000, 0x000031f0, IMPL, SUP}, /* TPPR */ + {0x00000000, 0x00000000, 0x00000000, 0x0fffffff, IMPL, SUP}, /* TPXR */ + + /* spr registers 1941-1951 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, SUP}, /* TIMERH */ + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, SUP}, /* TIMERL */ + {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, SUP}, /* TIMERD */ + + /* spr registers 1955-2047 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DCR */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* BRR */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* NMAR */ + + {0x00000000, 0x00000000, 0x00000000, 0x00000ffe, IMPL, SUP}, /* BTBR */ + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* IBAR0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* IBAR3 */ + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBAR0 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBAR2 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR00 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR02 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR10 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* spr registers 2066-2075 are reserved */ + RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR00 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* spr registers 2078 and 2079 are reserved */ + RESERVED, RESERVED, + + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR10 */ + {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, + + /* spr registers 2082-4095 are reserved */ + RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, RESERVED, RESERVED, RESERVED, RESERVED, + RESERVED, +}; + /* Initialize register control for this cpu */ void frv_register_control_init (SIM_CPU *cpu) @@ -5311,6 +6352,8 @@ frv_register_control_init (SIM_CPU *cpu) if (sizeof (fr400_spr) != FRV_MAX_SPR * sizeof (*fr400_spr)) abort (); + if (sizeof (fr450_spr) != FRV_MAX_SPR * sizeof (*fr450_spr)) + abort (); if (sizeof (fr500_spr) != FRV_MAX_SPR * sizeof (*fr500_spr)) abort (); if (sizeof (fr550_spr) != FRV_MAX_SPR * sizeof (*fr550_spr)) @@ -5331,6 +6374,11 @@ frv_register_control_init (SIM_CPU *cpu) control->cpr = 0; control->spr = fr550_spr; return; + case bfd_mach_fr450: + control->fr = 1; + control->cpr = 0; + control->spr = fr450_spr; + return; case bfd_mach_fr400: control->fr = 1; control->cpr = 0; @@ -5449,11 +6497,11 @@ frv_check_spr_read_access (SIM_CPU *current_cpu, UINT spr) switch (STATE_ARCHITECTURE (sd)->mach) { case bfd_mach_fr400: - /* On the fr400: if this is an unimplemented accumulator, then - generate an illegal_instruction_interrupt, otherwise no interrupt. - */ - if (spr >= H_SPR_ACC4 && spr <= H_SPR_ACC63 - || spr >= H_SPR_ACCG4 && spr <= H_SPR_ACCG63) + case bfd_mach_fr450: + /* On the fr4xx series: if this is an unimplemented accumulator, + then generate an illegal_instruction_interrupt, otherwise no + interrupt. */ + if (SPR_IS_ACC (spr)) frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); break; case bfd_mach_fr550: @@ -5542,6 +6590,7 @@ frv_check_register_access ( switch (STATE_ARCHITECTURE (sd)->mach) { case bfd_mach_fr400: + case bfd_mach_fr450: case bfd_mach_fr550: /* On some machines this generates an illegal_instruction interrupt. */ frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); diff --git a/sim/frv/sem.c b/sim/frv/sem.c index 4f2883b1a49..0fb30c31837 100644 --- a/sim/frv/sem.c +++ b/sim/frv/sem.c @@ -5630,138 +5630,6 @@ frvbf_write_mem_SI (current_cpu, pc, ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FL #undef FLD } -/* rstb: rstb$pack $GRk,@($GRi,$GRj) */ - -static SEM_PC -SEM_FN_NAME (frvbf,rstb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = abuf->addr; - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - -{ - SI tmp_address; - tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); -frvbf_write_mem_QI (current_cpu, pc, tmp_address, GET_H_GR (FLD (f_GRk))); -frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_GRk), 1, 0); -} - - return vpc; -#undef FLD -} - -/* rsth: rsth$pack $GRk,@($GRi,$GRj) */ - -static SEM_PC -SEM_FN_NAME (frvbf,rsth) (SIM_CPU *current_cpu, SEM_ARG sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = abuf->addr; - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - -{ - SI tmp_address; - tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); -frvbf_write_mem_HI (current_cpu, pc, tmp_address, GET_H_GR (FLD (f_GRk))); -frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_GRk), 2, 0); -} - - return vpc; -#undef FLD -} - -/* rst: rst$pack $GRk,@($GRi,$GRj) */ - -static SEM_PC -SEM_FN_NAME (frvbf,rst) (SIM_CPU *current_cpu, SEM_ARG sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cswap.f - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = abuf->addr; - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - -{ - SI tmp_address; - tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); -frvbf_write_mem_SI (current_cpu, pc, tmp_address, GET_H_GR (FLD (f_GRk))); -frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_GRk), 4, 0); -} - - return vpc; -#undef FLD -} - -/* rstbf: rstbf$pack $FRintk,@($GRi,$GRj) */ - -static SEM_PC -SEM_FN_NAME (frvbf,rstbf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = abuf->addr; - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - -{ - SI tmp_address; - tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); -frvbf_write_mem_QI (current_cpu, pc, tmp_address, GET_H_FR_INT (FLD (f_FRk))); -frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_FRk), 1, 1); -} - - return vpc; -#undef FLD -} - -/* rsthf: rsthf$pack $FRintk,@($GRi,$GRj) */ - -static SEM_PC -SEM_FN_NAME (frvbf,rsthf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = abuf->addr; - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - -{ - SI tmp_address; - tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); -frvbf_write_mem_HI (current_cpu, pc, tmp_address, GET_H_FR_INT (FLD (f_FRk))); -frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_FRk), 2, 1); -} - - return vpc; -#undef FLD -} - -/* rstf: rstf$pack $FRintk,@($GRi,$GRj) */ - -static SEM_PC -SEM_FN_NAME (frvbf,rstf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstbfu.f - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = abuf->addr; - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - -{ - SI tmp_address; - tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); -frvbf_write_mem_SI (current_cpu, pc, tmp_address, GET_H_FR_INT (FLD (f_FRk))); -frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_FRk), 4, 1); -} - - return vpc; -#undef FLD -} - /* std: std$pack $GRdoublek,@($GRi,$GRj) */ static SEM_PC @@ -5831,54 +5699,6 @@ frvbf_write_mem_DI (current_cpu, pc, tmp_address, GET_H_CPR_DOUBLE (FLD (f_CPRk) #undef FLD } -/* rstd: rstd$pack $GRdoublek,@($GRi,$GRj) */ - -static SEM_PC -SEM_FN_NAME (frvbf,rstd) (SIM_CPU *current_cpu, SEM_ARG sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdu.f - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = abuf->addr; - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - -{ - SI tmp_address; -{ - tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); -frvbf_write_mem_DI (current_cpu, pc, tmp_address, GET_H_GR_DOUBLE (FLD (f_GRk))); -} -frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_GRk), 8, 0); -} - - return vpc; -#undef FLD -} - -/* rstdf: rstdf$pack $FRdoublek,@($GRi,$GRj) */ - -static SEM_PC -SEM_FN_NAME (frvbf,rstdf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdfu.f - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = abuf->addr; - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - -{ - SI tmp_address; -{ - tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); -frvbf_write_mem_DF (current_cpu, pc, tmp_address, GET_H_FR_DOUBLE (FLD (f_FRk))); -} -frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_FRk), 8, 1); -} - - return vpc; -#undef FLD -} - /* stq: stq$pack $GRk,@($GRi,$GRj) */ static SEM_PC @@ -5948,54 +5768,6 @@ frvbf_store_quad_CPR (current_cpu, pc, tmp_address, FLD (f_CPRk)); #undef FLD } -/* rstq: rstq$pack $GRk,@($GRi,$GRj) */ - -static SEM_PC -SEM_FN_NAME (frvbf,rstq) (SIM_CPU *current_cpu, SEM_ARG sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_smulcc.f - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = abuf->addr; - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - -{ - SI tmp_address; -{ - tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); -frvbf_store_quad_GR (current_cpu, pc, tmp_address, FLD (f_GRk)); -} -frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_GRk), 16, 0); -} - - return vpc; -#undef FLD -} - -/* rstqf: rstqf$pack $FRintk,@($GRi,$GRj) */ - -static SEM_PC -SEM_FN_NAME (frvbf,rstqf) (SIM_CPU *current_cpu, SEM_ARG sem_arg) -{ -#define FLD(f) abuf->fields.sfmt_cstdfu.f - ARGBUF *abuf = SEM_ARGBUF (sem_arg); - int UNUSED written = 0; - IADDR UNUSED pc = abuf->addr; - SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); - -{ - SI tmp_address; -{ - tmp_address = ADDSI (GET_H_GR (FLD (f_GRi)), GET_H_GR (FLD (f_GRj))); -frvbf_store_quad_FRint (current_cpu, pc, tmp_address, FLD (f_FRk)); -} -frvbf_check_recovering_store (current_cpu, tmp_address, FLD (f_FRk), 16, 1); -} - - return vpc; -#undef FLD -} - /* stbu: stbu$pack $GRk,@($GRi,$GRj) */ static SEM_PC @@ -16632,6 +16404,57 @@ SEM_FN_NAME (frvbf,membar) (SIM_CPU *current_cpu, SEM_ARG sem_arg) #undef FLD } +/* lrai: lrai$pack $GRi,$GRk,$LRAE,$LRAD,$LRAS */ + +static SEM_PC +SEM_FN_NAME (frvbf,lrai) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* lrad: lrad$pack $GRi,$GRk,$LRAE,$LRAD,$LRAS */ + +static SEM_PC +SEM_FN_NAME (frvbf,lrad) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + +/* tlbpr: tlbpr$pack $GRi,$GRj,$TLBPRopx,$TLBPRL */ + +static SEM_PC +SEM_FN_NAME (frvbf,tlbpr) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.fmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +((void) 0); /*nop*/ + + return vpc; +#undef FLD +} + /* cop1: cop1$pack $s6_1,$CPRi,$CPRj,$CPRk */ static SEM_PC @@ -22836,6 +22659,270 @@ frvbf_media_overflow (current_cpu, 1); #undef FLD } +/* mqlclrhs: mqlclrhs$pack $FRintieven,$FRintjeven,$FRintkeven */ + +static SEM_PC +SEM_FN_NAME (frvbf,mqlclrhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ORIF (ANDSI (FLD (f_FRj), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1))))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + HI tmp_a1; + HI tmp_a2; + HI tmp_a3; + HI tmp_a4; + HI tmp_b1; + HI tmp_b2; + HI tmp_b3; + HI tmp_b4; + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +{ + tmp_a1 = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_a2 = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_b1 = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_b2 = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + tmp_a3 = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_a4 = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_b3 = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_b4 = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} + { + UHI opval = (LEUHI (ABSHI (tmp_a1), ABSHI (tmp_b1))) ? (0) : (LEHI (0, tmp_b1)) ? (tmp_a1) : (EQHI (tmp_a1, -32768)) ? (32767) : (NEGHI (tmp_a1)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 15); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = (LEUHI (ABSHI (tmp_a2), ABSHI (tmp_b2))) ? (0) : (LEHI (0, tmp_b2)) ? (tmp_a2) : (EQHI (tmp_a2, -32768)) ? (32767) : (NEGHI (tmp_a2)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } + { + UHI opval = (LEUHI (ABSHI (tmp_a3), ABSHI (tmp_b3))) ? (0) : (LEHI (0, tmp_b3)) ? (tmp_a3) : (EQHI (tmp_a3, -32768)) ? (32767) : (NEGHI (tmp_a3)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 16); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = (LEUHI (ABSHI (tmp_a4), ABSHI (tmp_b4))) ? (0) : (LEHI (0, tmp_b4)) ? (tmp_a4) : (EQHI (tmp_a4, -32768)) ? (32767) : (NEGHI (tmp_a4)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mqlmths: mqlmths$pack $FRintieven,$FRintjeven,$FRintkeven */ + +static SEM_PC +SEM_FN_NAME (frvbf,mqlmths) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_cmqaddhss.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ORIF (ANDSI (FLD (f_FRj), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1))))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + HI tmp_a1; + HI tmp_a2; + HI tmp_a3; + HI tmp_a4; + HI tmp_b1; + HI tmp_b2; + HI tmp_b3; + HI tmp_b4; + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } +{ + tmp_a1 = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_a2 = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_b1 = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_b2 = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} +{ + tmp_a3 = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_a4 = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0)); + tmp_b3 = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); + tmp_b4 = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0)); +} + { + UHI opval = (ANDIF (GTHI (tmp_b1, -32768), GEHI (tmp_a1, ABSHI (tmp_b1)))) ? (tmp_b1) : (GTHI (tmp_a1, NEGHI (ABSHI (tmp_b1)))) ? (tmp_a1) : (EQHI (tmp_b1, -32768)) ? (32767) : (NEGHI (tmp_b1)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 15); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = (ANDIF (GTHI (tmp_b2, -32768), GEHI (tmp_a2, ABSHI (tmp_b2)))) ? (tmp_b2) : (GTHI (tmp_a2, NEGHI (ABSHI (tmp_b2)))) ? (tmp_a2) : (EQHI (tmp_b2, -32768)) ? (32767) : (NEGHI (tmp_b2)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 17); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } + { + UHI opval = (ANDIF (GTHI (tmp_b3, -32768), GEHI (tmp_a3, ABSHI (tmp_b3)))) ? (tmp_b3) : (GTHI (tmp_a3, NEGHI (ABSHI (tmp_b3)))) ? (tmp_a3) : (EQHI (tmp_b3, -32768)) ? (32767) : (NEGHI (tmp_b3)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 16); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = (ANDIF (GTHI (tmp_b4, -32768), GEHI (tmp_a4, ABSHI (tmp_b4)))) ? (tmp_b4) : (GTHI (tmp_a4, NEGHI (ABSHI (tmp_b4)))) ? (tmp_a4) : (EQHI (tmp_b4, -32768)) ? (32767) : (NEGHI (tmp_b4)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 18); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mqsllhi: mqsllhi$pack $FRintieven,$u6,$FRintkeven */ + +static SEM_PC +SEM_FN_NAME (frvbf,mqsllhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1)))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRi))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRi), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + UHI opval = SLLHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), ANDSI (FLD (f_u6), 15)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = SLLHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), ANDSI (FLD (f_u6), 15)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } + { + UHI opval = SLLHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), ANDSI (FLD (f_u6), 15)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = SLLHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), ANDSI (FLD (f_u6), 15)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + +/* mqsrahi: mqsrahi$pack $FRintieven,$u6,$FRintkeven */ + +static SEM_PC +SEM_FN_NAME (frvbf,mqsrahi) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_mqsllhi.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); + +if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1)))) { +frvbf_media_register_not_aligned (current_cpu); +} else { +{ + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRi))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRi), opval); + written |= (1 << 9); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk))); + sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval); + written |= (1 << 10); + TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval); + } + { + UHI opval = SRAHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), ANDSI (FLD (f_u6), 15)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 11); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = SRAHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), ANDSI (FLD (f_u6), 15)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval); + written |= (1 << 13); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } + { + UHI opval = SRAHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), ANDSI (FLD (f_u6), 15)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 12); + TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval); + } + { + UHI opval = SRAHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), ANDSI (FLD (f_u6), 15)); + sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval); + written |= (1 << 14); + TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval); + } +} +} + + abuf->written = written; + return vpc; +#undef FLD +} + /* maddaccs: maddaccs$pack $ACC40Si,$ACC40Sk */ static SEM_PC @@ -28264,22 +28351,12 @@ static const struct sem_fn_desc sem_fns[] = { { FRVBF_INSN_STHF, SEM_FN_NAME (frvbf,sthf) }, { FRVBF_INSN_STF, SEM_FN_NAME (frvbf,stf) }, { FRVBF_INSN_STC, SEM_FN_NAME (frvbf,stc) }, - { FRVBF_INSN_RSTB, SEM_FN_NAME (frvbf,rstb) }, - { FRVBF_INSN_RSTH, SEM_FN_NAME (frvbf,rsth) }, - { FRVBF_INSN_RST, SEM_FN_NAME (frvbf,rst) }, - { FRVBF_INSN_RSTBF, SEM_FN_NAME (frvbf,rstbf) }, - { FRVBF_INSN_RSTHF, SEM_FN_NAME (frvbf,rsthf) }, - { FRVBF_INSN_RSTF, SEM_FN_NAME (frvbf,rstf) }, { FRVBF_INSN_STD, SEM_FN_NAME (frvbf,std) }, { FRVBF_INSN_STDF, SEM_FN_NAME (frvbf,stdf) }, { FRVBF_INSN_STDC, SEM_FN_NAME (frvbf,stdc) }, - { FRVBF_INSN_RSTD, SEM_FN_NAME (frvbf,rstd) }, - { FRVBF_INSN_RSTDF, SEM_FN_NAME (frvbf,rstdf) }, { FRVBF_INSN_STQ, SEM_FN_NAME (frvbf,stq) }, { FRVBF_INSN_STQF, SEM_FN_NAME (frvbf,stqf) }, { FRVBF_INSN_STQC, SEM_FN_NAME (frvbf,stqc) }, - { FRVBF_INSN_RSTQ, SEM_FN_NAME (frvbf,rstq) }, - { FRVBF_INSN_RSTQF, SEM_FN_NAME (frvbf,rstqf) }, { FRVBF_INSN_STBU, SEM_FN_NAME (frvbf,stbu) }, { FRVBF_INSN_STHU, SEM_FN_NAME (frvbf,sthu) }, { FRVBF_INSN_STU, SEM_FN_NAME (frvbf,stu) }, @@ -28619,6 +28696,9 @@ static const struct sem_fn_desc sem_fns[] = { { FRVBF_INSN_DCUL, SEM_FN_NAME (frvbf,dcul) }, { FRVBF_INSN_BAR, SEM_FN_NAME (frvbf,bar) }, { FRVBF_INSN_MEMBAR, SEM_FN_NAME (frvbf,membar) }, + { FRVBF_INSN_LRAI, SEM_FN_NAME (frvbf,lrai) }, + { FRVBF_INSN_LRAD, SEM_FN_NAME (frvbf,lrad) }, + { FRVBF_INSN_TLBPR, SEM_FN_NAME (frvbf,tlbpr) }, { FRVBF_INSN_COP1, SEM_FN_NAME (frvbf,cop1) }, { FRVBF_INSN_COP2, SEM_FN_NAME (frvbf,cop2) }, { FRVBF_INSN_CLRGR, SEM_FN_NAME (frvbf,clrgr) }, @@ -28766,6 +28846,10 @@ static const struct sem_fn_desc sem_fns[] = { { FRVBF_INSN_CMQADDHUS, SEM_FN_NAME (frvbf,cmqaddhus) }, { FRVBF_INSN_CMQSUBHSS, SEM_FN_NAME (frvbf,cmqsubhss) }, { FRVBF_INSN_CMQSUBHUS, SEM_FN_NAME (frvbf,cmqsubhus) }, + { FRVBF_INSN_MQLCLRHS, SEM_FN_NAME (frvbf,mqlclrhs) }, + { FRVBF_INSN_MQLMTHS, SEM_FN_NAME (frvbf,mqlmths) }, + { FRVBF_INSN_MQSLLHI, SEM_FN_NAME (frvbf,mqsllhi) }, + { FRVBF_INSN_MQSRAHI, SEM_FN_NAME (frvbf,mqsrahi) }, { FRVBF_INSN_MADDACCS, SEM_FN_NAME (frvbf,maddaccs) }, { FRVBF_INSN_MSUBACCS, SEM_FN_NAME (frvbf,msubaccs) }, { FRVBF_INSN_MDADDACCS, SEM_FN_NAME (frvbf,mdaddaccs) }, diff --git a/sim/frv/traps.c b/sim/frv/traps.c index f7b4b746f86..3e9344696fe 100644 --- a/sim/frv/traps.c +++ b/sim/frv/traps.c @@ -50,7 +50,8 @@ frv_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia, { if (sig == sim_core_unaligned_signal) { - if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400) + if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400 + || STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr450) frv_queue_data_access_error_interrupt (current_cpu, addr); else frv_queue_mem_address_not_aligned_interrupt (current_cpu, addr); @@ -591,7 +592,13 @@ frvbf_media_cr_not_aligned (SIM_CPU *current_cpu) /* On some machines this generates an illegal_instruction interrupt. */ switch (STATE_ARCHITECTURE (sd)->mach) { + /* Note: there is a discrepancy between V2.2 of the FR400 + instruction manual and the various FR4xx LSI specs. The former + claims that unaligned registers cause an mp_exception while the + latter say it's an illegal_instruction. The LSI specs appear + to be correct since MTT is fixed at 1. */ case bfd_mach_fr400: + case bfd_mach_fr450: case bfd_mach_fr550: frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); break; @@ -610,7 +617,9 @@ frvbf_media_acc_not_aligned (SIM_CPU *current_cpu) /* On some machines this generates an illegal_instruction interrupt. */ switch (STATE_ARCHITECTURE (sd)->mach) { + /* See comment in frvbf_cr_not_aligned(). */ case bfd_mach_fr400: + case bfd_mach_fr450: case bfd_mach_fr550: frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); break; @@ -629,7 +638,9 @@ frvbf_media_register_not_aligned (SIM_CPU *current_cpu) /* On some machines this generates an illegal_instruction interrupt. */ switch (STATE_ARCHITECTURE (sd)->mach) { + /* See comment in frvbf_cr_not_aligned(). */ case bfd_mach_fr400: + case bfd_mach_fr450: case bfd_mach_fr550: frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION); break; diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog index 4e7b230be8b..a344a6d79a1 100644 --- a/sim/testsuite/ChangeLog +++ b/sim/testsuite/ChangeLog @@ -1,3 +1,31 @@ +2004-03-01 Richard Sandiford + + * sim/frv/allinsn.exp (all_machs): Add fr405 and fr450. + * sim/fr400/allinsn.exp (all_machs): Likewise. + * sim/fr400/addss.cgs (mach): Change to "fr405 fr450". + * sim/fr400/scutss.cgs (mach): Likewise. + * sim/fr400/slass.cgs (mach): Likewise. + * sim/fr400/smass.cgs (mach): Likewise. + * sim/fr400/smsss.cgs (mach): Likewise. + * sim/fr400/smu.cgs (mach): Likewise. + * sim/fr400/subss.cgs (mach): Likewise. + * sim/interrupts/fp_exception.cgs: Replace fmadds with .word. + * sim/interrupts/fp_exception-fr550.cgs: Likewise. + * sim/frv/mqlclrhs.cgs: New test. + * sim/frv/mqlmths.cgs: New test. + * sim/frv/mqsllhi.cgs: New test. + * sim/frv/mqsrahi.cgs: New test. + +2004-03-01 Richard Sandiford + + * sim/frv/fr400/scutss.cgs: Fix tests to account for rounding. + Add some new ones. + +2004-03-01 Richard Sandiford + + * sim/frv/{rstb,rsth,rst,rstd,rstq}.cgs: Delete. + * sim/frv/{rstbf,rsthf,rstf,rstdf,rstqf}.cgs: Delete. + 2004-01-26 Chris Demetriou * sim/mips: New directory. Tests for the MIPS simulator. diff --git a/sim/testsuite/frv-elf/ChangeLog b/sim/testsuite/frv-elf/ChangeLog deleted file mode 100644 index 5d6b82c3211..00000000000 --- a/sim/testsuite/frv-elf/ChangeLog +++ /dev/null @@ -1,34 +0,0 @@ -2000-07-26 Dave Brolley - - * Makefile.in (TESTS): Don't run cache.ok - * cache.s: Use softune syntax for jmpl. - -2000-07-19 Dave Brolley - - * cache.s (pass): Use softune syntax for tira. - * exit47.s (pass): Use softune syntax for tira. - * grloop.s (pass): Use softune syntax for tira. - * hello.s (pass): Use softune syntax for tira. - -Thu Aug 19 18:00:16 1999 Dave Brolley - - * hello.s: Fix sethi, setlo insn usage. - -Mon Jun 21 17:33:37 1999 Dave Brolley - - * Makefile.in (TESTS): Add grloop.ok. - * grloop.s: New testcase. - -Fri Jun 18 17:55:02 1999 Dave Brolley - - * exit47.s: Use proper syscalls interface. - * hello.s: Use proper syscalls interface. - -Mon May 31 12:03:38 1999 Dave Brolley - - * hello.s,loop.s,exit47.s: Convert to frv insn set. - -Thu May 6 16:36:30 1999 Dave Brolley - - * Directory created. - diff --git a/sim/testsuite/frv-elf/Makefile.in b/sim/testsuite/frv-elf/Makefile.in deleted file mode 100644 index 795bdd1aed1..00000000000 --- a/sim/testsuite/frv-elf/Makefile.in +++ /dev/null @@ -1,159 +0,0 @@ -# Makefile for regression testing the frv simulator. -# Copyright (C) 1998 Free Software Foundation, Inc. - -# This file is part of GDB. - -# GDB is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. - -# GDB is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. - -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - -VPATH = @srcdir@ -srcdir = @srcdir@ -srcroot = $(srcdir)/../../.. - -prefix = @prefix@ -exec_prefix = @exec_prefix@ - -host_alias = @host_alias@ -target_alias = @target_alias@ -program_transform_name = @program_transform_name@ -build_canonical = @build@ -host_canonical = @host@ -target_canonical = @target@ -target_cpu = @target_cpu@ - - -SHELL = @SHELL@ -SUBDIRS = @subdirs@ -RPATH_ENVVAR = @RPATH_ENVVAR@ - -EXPECT = `if [ -f ../../../expect/expect ] ; then \ - echo ../../../expect/expect ; \ - else echo expect ; fi` - -RUNTEST = $(RUNTEST_FOR_TARGET) - -RUNTESTFLAGS = - -RUNTEST_FOR_TARGET = `\ - if [ -f $${srcroot}/dejagnu/runtest ]; then \ - echo $${srcroot}/dejagnu/runtest; \ - else \ - if [ "$(host_canonical)" = "$(target_canonical)" ]; then \ - echo runtest; \ - else \ - t='$(program_transform_name)'; echo runtest | sed -e '' $$t; \ - fi; \ - fi` - - -AS_FOR_TARGET = `\ - if [ -x ../../../gas/as-new ]; then \ - echo ../../../gas/as-new ; \ - else \ - echo $(target_alias)-as ; \ - fi` - -LD_FOR_TARGET = `\ - if [ -x ../../../ld/ld-new ]; then \ - echo ../../../ld/ld-new ; \ - else \ - echo $(target_alias)-ld ; \ - fi` - -RUN_FOR_TARGET = `\ - if [ -x ../../../sim/${target_cpu}/run ]; then \ - echo ../../../sim/${target_cpu}/run ; \ - else \ - echo $(target_alias)-run ; \ - fi` - -TESTS = \ - exit47.ko \ - grloop.ok \ - hello.ok - - -check: sanity $(TESTS) -sanity: - @eval echo AS_FOR_TARGET = $(AS_FOR_TARGET) - @eval echo LD_FOR_TARGET = $(LD_FOR_TARGET) - @eval echo RUN_FOR_TARGET = $(RUN_FOR_TARGET) - - - -# Rules for running all the tests, put into three types -# exit success, exit fail, print "Hello World" - -.u.log: - uudecode $*.u - $(RUN_FOR_TARGET) $* > $*.log - - -# Rules for running the tests - -.SUFFIXES: .u .ok .run .hi .ko -.run.ok: - rm -f tmp-$* $*.hi - ulimit -t 5 ; $(RUN_FOR_TARGET) $*.run > tmp-$* - mv tmp-$* $*.ok -.run.hi: - rm -f tmp-$* $*.hi diff-$* - ulimit -t 5 ; $(RUN_FOR_TARGET) $*.run > tmp-$* - echo "Hello World" | diff - tmp-$* > diff-$* - cat tmp-$* diff-$* > $*.hi -.run.ko: - rm -f tmp-$* $*.ko - set +e ; \ - ulimit -t 5 ; $(RUN_FOR_TARGET) $*.run > tmp-$* ; \ - if [ $$? -eq 47 ] ; then \ - exit 0 ; \ - else \ - exit 1 ; \ - fi - mv tmp-$* $*.ko - - -# Rules for building all the tests and packing them into -# uuencoded files. - -uuencode: em-pstr.u em-e0.u em-e47.u em-pchr.u - -.SUFFIXES: .u .s .run -.s.u: - rm -f $*.o $*.run - $(AS_FOR_TARGET) $(srcdir)/$*.s -o $*.o - $(LD_FOR_TARGET) -o $* $*.o - uuencode < $* $* > $*.u - rm -f $*.o $* -.s.run: - rm -f $*.o $*.run - $(AS_FOR_TARGET) $(srcdir)/$*.s -o $*.o - $(LD_FOR_TARGET) -o $*.run $*.o - rm -f $*.o $* - - -clean mostlyclean: - rm -f *~ core *.o a.out - rm -f $(TESTS) - -distclean maintainer-clean realclean: clean - rm -f *~ core - rm -f Makefile config.status *-init.exp - rm -fr *.log summary detail *.plog *.sum *.psum site.* - -Makefile : Makefile.in config.status - $(SHELL) config.status - -config.status: configure - $(SHELL) config.status --recheck diff --git a/sim/testsuite/frv-elf/cache.s b/sim/testsuite/frv-elf/cache.s deleted file mode 100644 index 2ed0e1e35a9..00000000000 --- a/sim/testsuite/frv-elf/cache.s +++ /dev/null @@ -1,164 +0,0 @@ -# run with --memory-region 0xff000000,4 --memory-region 0xfe000000,00404000 -; Exit with return code - .macro exit rc - setlos.p #1,gr7 - setlos \rc,gr8 - tira gr0,#0 - .endm - -; Pass the test case - .macro pass -pass: - setlos.p #5,gr10 - setlos #1,gr8 - setlos #5,gr7 - sethi.p %hi(passmsg),gr9 - setlo %lo(passmsg),gr9 - tira gr0,#0 - exit #0 - .endm - -; Fail the testcase - .macro fail -fail\@: - setlos.p #5,gr10 - setlos #1,gr8 - setlos #5,gr7 - sethi.p %hi(failmsg),gr9 - setlo %lo(failmsg),gr9 - tira gr0,#0 - exit #1 - .endm - - .data -failmsg: - .ascii "fail\n" -passmsg: - .ascii "pass\n" - - .text - .global _start -_start: - movsg hsr0,gr10 ; enable insn and data caches - sethi.p 0xc800,gr11 ; in copy-back mode - setlo 0x0000,gr11 - or gr10,gr11,gr10 - movgs gr10,hsr0 - - sethi.p 0x7,sp - setlo 0x0000,sp - - ; fill the cache - sethi.p %hi(done1),gr10 - setlo %lo(done1),gr10 - movgs gr10,lr - setlos.p 0x1000,gr10 - setlos 0x0,gr11 - movgs gr10,lcr -write1: st.p gr11,@(sp,gr11) - addi.p gr11,4,gr11 - bctrlr.p 1,0 - bra write1 -done1: - ; read it back - sethi.p %hi(done2),gr10 - setlo %lo(done2),gr10 - movgs gr10,lr - setlos.p 0x1000,gr10 - setlos 0x0,gr11 - movgs gr10,lcr -read1: ld @(sp,gr11),gr12 - cmp gr11,gr12,icc0 - bne icc0,1,fail - addi.p gr11,4,gr11 - bctrlr.p 1,0 - bra read1 -done2: - - ; fill the cache twice - sethi.p %hi(done3),gr10 - setlo %lo(done3),gr10 - movgs gr10,lr - setlos.p 0x2000,gr10 - setlos 0x0,gr11 - movgs gr10,lcr -write3: st.p gr11,@(sp,gr11) - addi.p gr11,4,gr11 - bctrlr.p 1,0 - bra write3 -done3: - ; read it back - sethi.p %hi(done4),gr10 - setlo %lo(done4),gr10 - movgs gr10,lr - setlos.p 0x2000,gr10 - setlos 0x0,gr11 - movgs gr10,lcr -read4: ld @(sp,gr11),gr12 - cmp gr11,gr12,icc0 - bne icc0,1,fail - addi.p gr11,4,gr11 - bctrlr.p 1,0 - bra read4 -done4: - ; read it back in reverse - sethi.p %hi(done5),gr10 - setlo %lo(done5),gr10 - movgs gr10,lr - setlos.p 0x2000,gr10 - setlos 0x7ffc,gr11 - movgs gr10,lcr -read5: ld @(sp,gr11),gr12 - cmp gr11,gr12,icc0 - bne icc0,1,fail - subi.p gr11,4,gr11 - bctrlr.p 1,0 - bra read5 -done5: - - ; access data and insns in non-cache areas - sethi.p 0x8038,gr11 ; bctrlr 0,0 - setlo 0x2000,gr11 - - sethi.p 0xff00,gr10 ; documented area - setlo 0x0000,gr10 - sti gr11,@(gr10,0) - jmpl @(gr10,gr0) - - ; enable RAM mode - movsg hsr0,gr10 - sethi.p 0x0040,gr12 - setlo 0x0000,gr12 - or gr10,gr12,gr10 - movgs gr10,hsr0 - - sethi.p 0xfe00,gr10 ; documented area - setlo 0x0400,gr10 - sti gr11,@(gr10,0) - jmpl @(gr10,gr0) - - sethi.p 0xfe40,gr10 ; documented area - setlo 0x0400,gr10 - sti gr11,@(gr10,0) - dcf @(gr10,gr0) - jmpl @(gr10,gr0) - - sethi.p 0x0007,gr10 ; non RAM area - setlo 0x0000,gr10 - sti gr11,@(gr10,0) - jmpl @(gr10,gr0) - - sethi.p 0xfe00,gr10 ; insn RAM area - setlo 0x0000,gr10 - sti gr11,@(gr10,0) - jmpl @(gr10,gr0) - - sethi.p 0xfe40,gr10 ; data RAM area - setlo 0x0000,gr10 - sti gr11,@(gr10,0) - dcf @(gr10,gr0) - jmpl @(gr10,gr0) - - pass -fail: - fail diff --git a/sim/testsuite/frv-elf/configure b/sim/testsuite/frv-elf/configure deleted file mode 100755 index 25c27936dcb..00000000000 --- a/sim/testsuite/frv-elf/configure +++ /dev/null @@ -1,905 +0,0 @@ -#! /bin/sh - -# Guess values for system-dependent variables and create Makefiles. -# Generated automatically using autoconf version 2.13 -# Copyright (C) 1992, 93, 94, 95, 96 Free Software Foundation, Inc. -# -# This configure script is free software; the Free Software Foundation -# gives unlimited permission to copy, distribute and modify it. - -# Defaults: -ac_help= -ac_default_prefix=/usr/local -# Any additions from configure.in: - -# Initialize some variables set by options. -# The variables have the same names as the options, with -# dashes changed to underlines. -build=NONE -cache_file=./config.cache -exec_prefix=NONE -host=NONE -no_create= -nonopt=NONE -no_recursion= -prefix=NONE -program_prefix=NONE -program_suffix=NONE -program_transform_name=s,x,x, -silent= -site= -srcdir= -target=NONE -verbose= -x_includes=NONE -x_libraries=NONE -bindir='${exec_prefix}/bin' -sbindir='${exec_prefix}/sbin' -libexecdir='${exec_prefix}/libexec' -datadir='${prefix}/share' -sysconfdir='${prefix}/etc' -sharedstatedir='${prefix}/com' -localstatedir='${prefix}/var' -libdir='${exec_prefix}/lib' -includedir='${prefix}/include' -oldincludedir='/usr/include' -infodir='${prefix}/info' -mandir='${prefix}/man' - -# Initialize some other variables. -subdirs= -MFLAGS= MAKEFLAGS= -SHELL=${CONFIG_SHELL-/bin/sh} -# Maximum number of lines to put in a shell here document. -ac_max_here_lines=12 - -ac_prev= -for ac_option -do - - # If the previous option needs an argument, assign it. - if test -n "$ac_prev"; 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For more information, check -dnl any existing configure script. - -AC_PREREQ(2.5) -dnl FIXME - think of a truly uniq file to this directory -AC_INIT(Makefile.in) - -CC=${CC-cc} -AC_SUBST(CC) -AC_CONFIG_AUX_DIR(`cd $srcdir;pwd`/../../..) -AC_CANONICAL_SYSTEM - -AC_SUBST(target_cpu) - - -AC_OUTPUT(Makefile) diff --git a/sim/testsuite/frv-elf/exit47.s b/sim/testsuite/frv-elf/exit47.s deleted file mode 100644 index 70e56b3c4ab..00000000000 --- a/sim/testsuite/frv-elf/exit47.s +++ /dev/null @@ -1,5 +0,0 @@ - .global _start -_start: - setlos #47,gr8 - setlos #1,gr7 - tira gr0,#0 diff --git a/sim/testsuite/frv-elf/grloop.s b/sim/testsuite/frv-elf/grloop.s deleted file mode 100644 index 844ad1d2941..00000000000 --- a/sim/testsuite/frv-elf/grloop.s +++ /dev/null @@ -1,10 +0,0 @@ - .global _start -_start: - setlo 0x0400,gr10 -loop: - addicc gr10,-1,gr10,icc0 - bne icc0,0,loop -; exit (0) - setlos #0,gr8 - setlos #1,gr7 - tira gr0,#0 diff --git a/sim/testsuite/frv-elf/hello.s b/sim/testsuite/frv-elf/hello.s deleted file mode 100644 index 0151febc02f..00000000000 --- a/sim/testsuite/frv-elf/hello.s +++ /dev/null @@ -1,16 +0,0 @@ - .global _start -_start: - -; write (hello world) - setlos #14,gr10 - sethi %hi(hello),gr9 - setlo %lo(hello),gr9 - setlos #1,gr8 - setlos #5,gr7 - tira gr0,#0 -; exit (0) - setlos #0,gr8 - setlos #1,gr7 - tira gr0,#0 - -hello: .ascii "Hello World!\r\n" diff --git a/sim/testsuite/frv-elf/loop.s b/sim/testsuite/frv-elf/loop.s deleted file mode 100644 index 8489c13c569..00000000000 --- a/sim/testsuite/frv-elf/loop.s +++ /dev/null @@ -1,2 +0,0 @@ - .global _start -_start: bra icc0,0,_start diff --git a/sim/testsuite/sim/frv/add.cgs b/sim/testsuite/sim/frv/add.cgs deleted file mode 100644 index 54fdfd5daa4..00000000000 --- a/sim/testsuite/sim/frv/add.cgs +++ /dev/null @@ -1,23 +0,0 @@ -# frv testcase for add $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global add -add: - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - add gr7,gr8,gr8 - test_gr_immed 3,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - add gr7,gr8,gr8 - test_gr_limmed 0x8000,0x0000,gr8 - - add gr8,gr8,gr8 - test_gr_immed 0,gr8 - - pass diff --git a/sim/testsuite/sim/frv/add.pcgs b/sim/testsuite/sim/frv/add.pcgs deleted file mode 100644 index cf49976d440..00000000000 --- a/sim/testsuite/sim/frv/add.pcgs +++ /dev/null @@ -1,25 +0,0 @@ -# frv parallel testcase for add $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global add -add: - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - add.p gr7,gr8,gr8 - add gr7,gr8,gr9 - add.p gr7,gr8,gr10 - add gr7,gr8,gr11 - add.p gr7,gr8,gr12 - add gr7,gr8,gr13 - test_gr_immed 3,gr8 - test_gr_immed 3,gr9 - test_gr_immed 4,gr10 - test_gr_immed 4,gr11 - test_gr_immed 4,gr12 - test_gr_immed 4,gr13 - - pass diff --git a/sim/testsuite/sim/frv/addcc.cgs b/sim/testsuite/sim/frv/addcc.cgs deleted file mode 100644 index d2e33d8fa2a..00000000000 --- a/sim/testsuite/sim/frv/addcc.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# frv testcase for addcc $GRi,$GRj,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global addcc -addcc: - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - addcc gr7,gr8,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 3,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - addcc gr7,gr8,gr8,icc0 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_icc 0x08,0 ; Set mask opposite of expected - addcc gr8,gr8,gr8,icc0 - test_icc 0 1 1 1 icc0 - test_gr_immed 0,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - addcc gr8,gr8,gr8,icc0; test zero, carry and overflow bits - test_icc 0 1 1 1 icc0 - test_gr_immed 0,gr8 - - - pass diff --git a/sim/testsuite/sim/frv/addi.cgs b/sim/testsuite/sim/frv/addi.cgs deleted file mode 100644 index 3d60c5d9acf..00000000000 --- a/sim/testsuite/sim/frv/addi.cgs +++ /dev/null @@ -1,25 +0,0 @@ -# frv testcase for addi $GRi,$s12,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global addi -addi: - set_gr_immed 4,gr8 - addi gr8,0,gr8 - test_gr_immed 4,gr8 - addi gr8,1,gr8 - test_gr_immed 5,gr8 - addi gr8,15,gr8 - test_gr_immed 20,gr8 - set_gr_limmed 0x7fff,0xffff,gr8 - addi gr8,1,gr8 - test_gr_limmed 0x8000,0x0000,gr8 - addi gr8,0x7ff,gr8 - test_gr_limmed 0x8000,0x07ff,gr8 - addi gr8,-2048,gr8 - test_gr_limmed 0x7fff,0xffff,gr8 - - pass diff --git a/sim/testsuite/sim/frv/addicc.cgs b/sim/testsuite/sim/frv/addicc.cgs deleted file mode 100644 index 6f2a19760c4..00000000000 --- a/sim/testsuite/sim/frv/addicc.cgs +++ /dev/null @@ -1,30 +0,0 @@ -# frv testcase for addicc $GRi,$s10,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global addicc -addicc: - ; Test add $u4Ri - set_gr_immed 4,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - addicc gr8,0,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 4,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - addicc gr8,1,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 5,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - addicc gr8,15,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 20,gr8 - set_gr_limmed 0x7fff,0xffff,gr8 ; test neg and overflow bits - set_icc 0x05,0 ; Set mask opposite of expected - addicc gr8,1,gr8,icc0 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/addx.cgs b/sim/testsuite/sim/frv/addx.cgs deleted file mode 100644 index 259a694062f..00000000000 --- a/sim/testsuite/sim/frv/addx.cgs +++ /dev/null @@ -1,49 +0,0 @@ -# frv testcase for addx $GRi,$GRj,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global addx -addx: - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0e,0 ; Make sure carry bit is off - addx gr7,gr8,gr8,icc0 - test_icc 1 1 1 0 icc0 - test_gr_immed 3,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - set_icc 0x04,0 ; Make sure carry bit is off - addx gr7,gr8,gr8,icc0 - test_icc 0 1 0 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_icc 0x08,0 ; Make sure carry bit is off - addx gr8,gr8,gr8,icc0 - test_icc 1 0 0 0 icc0 - test_gr_immed 0,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Make sure carry bit is on - addx gr7,gr8,gr8,icc0 - test_icc 1 1 1 1 icc0 - test_gr_immed 4,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 0,gr8 - set_icc 0x05,0 ; Make sure carry bit is on - addx gr7,gr8,gr8,icc0 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_icc 0x0b,0 ; Make sure carry bit is on - addx gr7,gr8,gr8,icc0 - test_icc 1 0 1 1 icc0 - test_gr_immed 0,gr8 - - pass diff --git a/sim/testsuite/sim/frv/addxcc.cgs b/sim/testsuite/sim/frv/addxcc.cgs deleted file mode 100644 index 230c047d688..00000000000 --- a/sim/testsuite/sim/frv/addxcc.cgs +++ /dev/null @@ -1,49 +0,0 @@ -# frv testcase for addxcc $GRi,$GRj,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global addxcc -addxcc: - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0e,0 ; Make sure carry bit is off - addxcc gr7,gr8,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 3,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - set_icc 0x04,0 ; Make sure carry bit is off - addxcc gr7,gr8,gr8,icc0 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_icc 0x08,0 ; Make sure carry bit is off - addxcc gr8,gr8,gr8,icc0 - test_icc 0 1 1 1 icc0 - test_gr_immed 0,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Make sure carry bit is on - addxcc gr7,gr8,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 4,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 0,gr8 - set_icc 0x05,0 ; Make sure carry bit is on - addxcc gr7,gr8,gr8,icc0 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_icc 0x0b,0 ; Make sure carry bit is on - addxcc gr7,gr8,gr8,icc0 - test_icc 0 1 0 1 icc0 - test_gr_immed 0,gr8 - - pass diff --git a/sim/testsuite/sim/frv/addxi.cgs b/sim/testsuite/sim/frv/addxi.cgs deleted file mode 100644 index c36272a14ea..00000000000 --- a/sim/testsuite/sim/frv/addxi.cgs +++ /dev/null @@ -1,46 +0,0 @@ -# frv testcase for addxi $GRi,$s10,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global addxi -addxi: - set_gr_immed 2,gr8 - set_icc 0x0e,0 ; Make sure carry bit is off - addxi gr8,1,gr8,icc0 - test_icc 1 1 1 0 icc0 - test_gr_immed 3,gr8 - - set_gr_limmed 0x7fff,0xffff,gr8 - set_icc 0x04,0 ; Make sure carry bit is off - addxi gr8,1,gr8,icc0 - test_icc 0 1 0 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xffff,0xff00,gr8 - set_icc 0x08,0 ; Make sure carry bit is off - addxi gr8,0x100,gr8,icc0 - test_icc 1 0 0 0 icc0 - test_gr_immed 0,gr8 - - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Make sure carry bit is on - addxi gr8,1,gr8,icc0 - test_icc 1 1 1 1 icc0 - test_gr_immed 4,gr8 - - set_gr_limmed 0x7fff,0xffff,gr8 - set_icc 0x05,0 ; Make sure carry bit is on - addxi gr8,0,gr8,icc0 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xffff,0xfeff,gr8 - set_icc 0x0b,0 ; Make sure carry bit is on - addxi gr8,0x100,gr8,icc0 - test_icc 1 0 1 1 icc0 - test_gr_immed 0,gr8 - - pass diff --git a/sim/testsuite/sim/frv/addxicc.cgs b/sim/testsuite/sim/frv/addxicc.cgs deleted file mode 100644 index 831fec39bdf..00000000000 --- a/sim/testsuite/sim/frv/addxicc.cgs +++ /dev/null @@ -1,46 +0,0 @@ -# frv testcase for addxicc $GRi,$s10,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global addxicc -addxicc: - set_gr_immed 2,gr8 - set_icc 0x0e,0 ; Make sure carry bit is off - addxicc gr8,1,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 3,gr8 - - set_gr_limmed 0x7fff,0xffff,gr8 - set_icc 0x04,0 ; Make sure carry bit is off - addxicc gr8,1,gr8,icc0 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xffff,0xff00,gr8 - set_icc 0x08,0 ; Make sure carry bit is off - addxicc gr8,0x100,gr8,icc0 - test_icc 0 1 0 1 icc0 - test_gr_immed 0,gr8 - - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Make sure carry bit is on - addxicc gr8,1,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 4,gr8 - - set_gr_limmed 0x7fff,0xffff,gr8 - set_icc 0x05,0 ; Make sure carry bit is on - addxicc gr8,0,gr8,icc0 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xffff,0xfeff,gr8 - set_icc 0x0b,0 ; Make sure carry bit is on - addxicc gr8,0x100,gr8,icc0 - test_icc 0 1 0 1 icc0 - test_gr_immed 0,gr8 - - pass diff --git a/sim/testsuite/sim/frv/allinsn.exp b/sim/testsuite/sim/frv/allinsn.exp deleted file mode 100644 index 220550da737..00000000000 --- a/sim/testsuite/sim/frv/allinsn.exp +++ /dev/null @@ -1,19 +0,0 @@ -# FRV simulator testsuite. - -if [istarget frv*-*] { - # load support procs (none yet) - # load_lib cgen.exp - # all machines - set all_machs "frv fr500 fr550 fr400" - set cpu_option -mcpu - - # The .cgs suffix is for "cgen .s". - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/frv/and.cgs b/sim/testsuite/sim/frv/and.cgs deleted file mode 100644 index a1773f1e3de..00000000000 --- a/sim/testsuite/sim/frv/and.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# frv testcase for and $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global and -and: - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - and gr7,gr8,gr8 - test_icc 1 0 1 1 icc0 - test_gr_immed 0,gr8 - - set_gr_limmed 0xffff,0x0000,gr8 - set_icc 0x04,0 ; Set mask opposite of expected - and gr7,gr8,gr8 - test_icc 0 1 0 0 icc0 - test_gr_limmed 0xaaaa,0x0000,gr8 - - set_gr_limmed 0x0000,0xffff,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - and gr7,gr8,gr8 - test_icc 1 1 0 1 icc0 - test_gr_limmed 0x0000,0xaaaa,gr8 - - pass diff --git a/sim/testsuite/sim/frv/andcc.cgs b/sim/testsuite/sim/frv/andcc.cgs deleted file mode 100644 index a2a04d2c0ca..00000000000 --- a/sim/testsuite/sim/frv/andcc.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# frv testcase for andcc $GRi,$GRj,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global andcc -andcc: - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - andcc gr7,gr8,gr8,icc0 - test_icc 0 1 1 1 icc0 - test_gr_immed 0,gr8 - - set_gr_limmed 0xffff,0x0000,gr8 - set_icc 0x04,0 ; Set mask opposite of expected - andcc gr7,gr8,gr8,icc0 - test_icc 1 0 0 0 icc0 - test_gr_limmed 0xaaaa,0x0000,gr8 - - set_gr_limmed 0x0000,0xffff,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - andcc gr7,gr8,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_limmed 0x0000,0xaaaa,gr8 - - pass diff --git a/sim/testsuite/sim/frv/andcr.cgs b/sim/testsuite/sim/frv/andcr.cgs deleted file mode 100644 index 9fbbaffb8b0..00000000000 --- a/sim/testsuite/sim/frv/andcr.cgs +++ /dev/null @@ -1,59 +0,0 @@ -# frv testcase for andcr $CCi,$CCj,$CCk -# mach: all - - .include "testutils.inc" - - start - - .global andcr -andcr: - set_spr_immed 0x1b1b,cccr - andcr cc7,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - andcr cc7,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - andcr cc7,cc5,cc3 - test_spr_immed 0x1b1b,cccr - - andcr cc7,cc4,cc3 - test_spr_immed 0x1b1b,cccr - - andcr cc6,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - andcr cc6,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - andcr cc6,cc5,cc3 - test_spr_immed 0x1b1b,cccr - - andcr cc6,cc4,cc3 - test_spr_immed 0x1b1b,cccr - - andcr cc5,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - andcr cc5,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - andcr cc5,cc5,cc3 - test_spr_immed 0x1b1b,cccr - - andcr cc5,cc4,cc3 - test_spr_immed 0x1b1b,cccr - - andcr cc4,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - andcr cc4,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - andcr cc4,cc5,cc3 - test_spr_immed 0x1b9b,cccr - - andcr cc4,cc4,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/andi.cgs b/sim/testsuite/sim/frv/andi.cgs deleted file mode 100644 index e9fdf75b4d5..00000000000 --- a/sim/testsuite/sim/frv/andi.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for andi $GRi,$s12,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global andi -andi: - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_icc 0x0b,0 ; Set mask opposite of expected - andi gr7,0x555,gr8 - test_icc 1 0 1 1 icc0 - test_gr_immed 0,gr8 - - set_icc 0x04,0 ; Set mask opposite of expected - andi gr7,-2048,gr8 - test_icc 0 1 0 0 icc0 - test_gr_limmed 0xaaaa,0xa800,gr8 - - set_icc 0x0d,0 ; Set mask opposite of expected - andi gr7,-1,gr8 - test_icc 1 1 0 1 icc0 - test_gr_limmed 0xaaaa,0xaaaa,gr8 - - pass diff --git a/sim/testsuite/sim/frv/andicc.cgs b/sim/testsuite/sim/frv/andicc.cgs deleted file mode 100644 index 650805975ad..00000000000 --- a/sim/testsuite/sim/frv/andicc.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for andicc $GRi,$s10,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global andicc -andicc: - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_icc 0x0b,0 ; Set mask opposite of expected - andicc gr7,0x155,gr8,icc0 - test_icc 0 1 1 1 icc0 - test_gr_immed 0,gr8 - - set_icc 0x04,0 ; Set mask opposite of expected - andicc gr7,-512,gr8,icc0 - test_icc 1 0 0 0 icc0 - test_gr_limmed 0xaaaa,0xaa00,gr8 - - set_icc 0x05,0 ; Set mask opposite of expected - andicc gr7,-1,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xaaaa,0xaaaa,gr8 - - pass diff --git a/sim/testsuite/sim/frv/andncr.cgs b/sim/testsuite/sim/frv/andncr.cgs deleted file mode 100644 index 31fd1f78d0d..00000000000 --- a/sim/testsuite/sim/frv/andncr.cgs +++ /dev/null @@ -1,59 +0,0 @@ -# frv testcase for andncr $CCi,$CCj,$CCk -# mach: all - - .include "testutils.inc" - - start - - .global andncr -andncr: - set_spr_immed 0x1b1b,cccr - andncr cc7,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - andncr cc7,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - andncr cc7,cc5,cc3 - test_spr_immed 0x1b1b,cccr - - andncr cc7,cc4,cc3 - test_spr_immed 0x1b1b,cccr - - andncr cc6,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - andncr cc6,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - andncr cc6,cc5,cc3 - test_spr_immed 0x1b1b,cccr - - andncr cc6,cc4,cc3 - test_spr_immed 0x1b1b,cccr - - andncr cc5,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - andncr cc5,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - andncr cc5,cc5,cc3 - test_spr_immed 0x1b9b,cccr - - andncr cc5,cc4,cc3 - test_spr_immed 0x1bdb,cccr - - andncr cc4,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - andncr cc4,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - andncr cc4,cc5,cc3 - test_spr_immed 0x1b1b,cccr - - andncr cc4,cc4,cc3 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/bar.cgs b/sim/testsuite/sim/frv/bar.cgs deleted file mode 100644 index df6a9caf6ec..00000000000 --- a/sim/testsuite/sim/frv/bar.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# frv testcase for bar -# mach: all - - .include "testutils.inc" - - start - - .global bar -bar: - bar - - pass diff --git a/sim/testsuite/sim/frv/bc.cgs b/sim/testsuite/sim/frv/bc.cgs deleted file mode 100644 index a5c612ccc9a..00000000000 --- a/sim/testsuite/sim/frv/bc.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for bc $ICCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global bc -bc: - set_icc 0x0 0 - bc icc0,0,bad - set_icc 0x1 1 - bc icc1,1,ok2 - fail -ok2: - set_icc 0x2 2 - bc icc2,2,bad - set_icc 0x3 3 - bc icc3,3,ok4 - fail -ok4: - set_icc 0x4 0 - bc icc0,0,bad - set_icc 0x5 1 - bc icc1,1,ok6 - fail -ok6: - set_icc 0x6 2 - bc icc2,2,bad - set_icc 0x7 3 - bc icc3,3,ok8 - fail -ok8: - set_icc 0x8 0 - bc icc0,0,bad - set_icc 0x9 1 - bc icc1,1,oka - fail -oka: - set_icc 0xa 2 - bc icc2,2,bad - set_icc 0xb 3 - bc icc3,3,okc - fail -okc: - set_icc 0xc 0 - bc icc0,0,bad - set_icc 0xd 1 - bc icc1,1,oke - fail -oke: - set_icc 0xe 2 - bc icc2,2,bad - set_icc 0xf 3 - bc icc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bcclr.cgs b/sim/testsuite/sim/frv/bcclr.cgs deleted file mode 100644 index 248be13491a..00000000000 --- a/sim/testsuite/sim/frv/bcclr.cgs +++ /dev/null @@ -1,293 +0,0 @@ -# frv testcase for bcclr $ICCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bcclr -bcclr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcclr icc0,0,0 - - set_spr_addr ok2,lr - set_icc 0x1 1 - bcclr icc1,0,1 - fail -ok2: - set_spr_addr bad,lr - set_icc 0x2 2 - bcclr icc2,0,2 - - set_spr_addr ok4,lr - set_icc 0x3 3 - bcclr icc3,0,3 - fail -ok4: - set_spr_addr bad,lr - set_icc 0x4 0 - bcclr icc0,0,0 - - set_spr_addr ok6,lr - set_icc 0x5 1 - bcclr icc1,0,1 - fail -ok6: - set_spr_addr bad,lr - set_icc 0x6 2 - bcclr icc2,0,2 - - set_spr_addr ok8,lr - set_icc 0x7 3 - bcclr icc3,0,3 - fail -ok8: - set_spr_addr bad,lr - set_icc 0x8 0 - bcclr icc0,0,0 - - set_spr_addr oka,lr - set_icc 0x9 1 - bcclr icc1,0,1 - fail -oka: - set_spr_addr bad,lr - set_icc 0xa 2 - bcclr icc2,0,2 - - set_spr_addr okc,lr - set_icc 0xb 3 - bcclr icc3,0,3 - fail -okc: - set_spr_addr bad,lr - set_icc 0xc 0 - bcclr icc0,0,0 - - set_spr_addr oke,lr - set_icc 0xd 1 - bcclr icc1,0,1 - fail -oke: - set_spr_addr bad,lr - set_icc 0xe 2 - bcclr icc2,0,2 - - set_spr_addr okg,lr - set_icc 0xf 3 - bcclr icc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcclr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr oki,lr - set_icc 0x1 1 - bcclr icc1,1,1 - fail -oki: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x2 2 - bcclr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_icc 0x3 3 - bcclr icc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x4 0 - bcclr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_icc 0x5 1 - bcclr icc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x6 2 - bcclr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_icc 0x7 3 - bcclr icc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x8 0 - bcclr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_icc 0x9 1 - bcclr icc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xa 2 - bcclr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_icc 0xb 3 - bcclr icc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xc 0 - bcclr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_icc 0xd 1 - bcclr icc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xe 2 - bcclr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_icc 0xf 3 - bcclr icc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcclr icc0,1,0 - - set_icc 0x1 1 - bcclr icc1,1,1 - - set_icc 0x2 2 - bcclr icc2,1,2 - - set_icc 0x3 3 - bcclr icc3,1,3 - - set_icc 0x4 0 - bcclr icc0,1,0 - - set_icc 0x5 1 - bcclr icc1,1,1 - - set_icc 0x6 2 - bcclr icc2,1,2 - - set_icc 0x7 3 - bcclr icc3,1,3 - - set_icc 0x8 0 - bcclr icc0,1,0 - - set_icc 0x9 1 - bcclr icc1,1,1 - - set_icc 0xa 2 - bcclr icc2,1,2 - - set_icc 0xb 3 - bcclr icc3,1,3 - - set_icc 0xc 0 - bcclr icc0,1,0 - - set_icc 0xd 1 - bcclr icc1,1,1 - - set_icc 0xe 2 - bcclr icc2,1,2 - - set_icc 0xf 3 - bcclr icc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcclr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x1 1 - bcclr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x2 2 - bcclr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x3 3 - bcclr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x4 0 - bcclr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x5 1 - bcclr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x6 2 - bcclr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x7 3 - bcclr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x8 0 - bcclr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x9 1 - bcclr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xa 2 - bcclr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xb 3 - bcclr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0xc 0 - bcclr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0xd 1 - bcclr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xe 2 - bcclr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xf 3 - bcclr icc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bceqlr.cgs b/sim/testsuite/sim/frv/bceqlr.cgs deleted file mode 100644 index bacabf417ec..00000000000 --- a/sim/testsuite/sim/frv/bceqlr.cgs +++ /dev/null @@ -1,293 +0,0 @@ -# frv testcase for bceqlr $ICCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bceqlr -bceqlr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bceqlr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0x1 1 - bceqlr icc1,0,1 - - set_spr_addr bad,lr - set_icc 0x2 2 - bceqlr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0x3 3 - bceqlr icc3,0,3 - - set_spr_addr ok5,lr - set_icc 0x4 0 - bceqlr icc0,0,0 - fail -ok5: - set_spr_addr ok6,lr - set_icc 0x5 1 - bceqlr icc1,0,1 - fail -ok6: - set_spr_addr ok7,lr - set_icc 0x6 2 - bceqlr icc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_icc 0x7 3 - bceqlr icc3,0,3 - fail -ok8: - set_spr_addr bad,lr - set_icc 0x8 0 - bceqlr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0x9 1 - bceqlr icc1,0,1 - - set_spr_addr bad,lr - set_icc 0xa 2 - bceqlr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0xb 3 - bceqlr icc3,0,3 - - set_spr_addr okd,lr - set_icc 0xc 0 - bceqlr icc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_icc 0xd 1 - bceqlr icc1,0,1 - fail -oke: - set_spr_addr okf,lr - set_icc 0xe 2 - bceqlr icc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_icc 0xf 3 - bceqlr icc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bceqlr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x1 1 - bceqlr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x2 2 - bceqlr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x3 3 - bceqlr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okl,lr - set_icc 0x4 0 - bceqlr icc0,1,0 - fail -okl: - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_icc 0x5 1 - bceqlr icc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_icc 0x6 2 - bceqlr icc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_icc 0x7 3 - bceqlr icc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x8 0 - bceqlr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x9 1 - bceqlr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xa 2 - bceqlr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xb 3 - bceqlr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_icc 0xc 0 - bceqlr icc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_icc 0xd 1 - bceqlr icc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_icc 0xe 2 - bceqlr icc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_icc 0xf 3 - bceqlr icc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bceqlr icc0,1,0 - - set_icc 0x1 1 - bceqlr icc1,1,1 - - set_icc 0x2 2 - bceqlr icc2,1,2 - - set_icc 0x3 3 - bceqlr icc3,1,3 - - set_icc 0x4 0 - bceqlr icc0,1,0 - - set_icc 0x5 1 - bceqlr icc1,1,1 - - set_icc 0x6 2 - bceqlr icc2,1,2 - - set_icc 0x7 3 - bceqlr icc3,1,3 - - set_icc 0x8 0 - bceqlr icc0,1,0 - - set_icc 0x9 1 - bceqlr icc1,1,1 - - set_icc 0xa 2 - bceqlr icc2,1,2 - - set_icc 0xb 3 - bceqlr icc3,1,3 - - set_icc 0xc 0 - bceqlr icc0,1,0 - - set_icc 0xd 1 - bceqlr icc1,1,1 - - set_icc 0xe 2 - bceqlr icc2,1,2 - - set_icc 0xf 3 - bceqlr icc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bceqlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x1 1 - bceqlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x2 2 - bceqlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x3 3 - bceqlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x4 0 - bceqlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x5 1 - bceqlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x6 2 - bceqlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x7 3 - bceqlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x8 0 - bceqlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x9 1 - bceqlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xa 2 - bceqlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xb 3 - bceqlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0xc 0 - bceqlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0xd 1 - bceqlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xe 2 - bceqlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xf 3 - bceqlr icc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bcgelr.cgs b/sim/testsuite/sim/frv/bcgelr.cgs deleted file mode 100644 index 72bd37450fd..00000000000 --- a/sim/testsuite/sim/frv/bcgelr.cgs +++ /dev/null @@ -1,293 +0,0 @@ -# frv testcase for bcgelr $ICCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bcgelr -bcgelr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr ok1,lr - set_icc 0x0 0 - bcgelr icc0,0,0 - fail -ok1: - set_spr_addr ok2,lr - set_icc 0x1 1 - bcgelr icc1,0,1 - fail -ok2: - set_spr_addr bad,lr - set_icc 0x2 2 - bcgelr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0x3 3 - bcgelr icc3,0,3 - - set_spr_addr ok5,lr - set_icc 0x4 0 - bcgelr icc0,0,0 - fail -ok5: - set_spr_addr ok6,lr - set_icc 0x5 1 - bcgelr icc1,0,1 - fail -ok6: - set_spr_addr bad,lr - set_icc 0x6 2 - bcgelr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0x7 3 - bcgelr icc3,0,3 - - set_spr_addr bad,lr - set_icc 0x8 0 - bcgelr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0x9 1 - bcgelr icc1,0,1 - - set_spr_addr okb,lr - set_icc 0xa 2 - bcgelr icc2,0,2 - fail -okb: - set_spr_addr okc,lr - set_icc 0xb 3 - bcgelr icc3,0,3 - fail -okc: - set_spr_addr bad,lr - set_icc 0xc 0 - bcgelr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0xd 1 - bcgelr icc1,0,1 - - set_spr_addr okf,lr - set_icc 0xe 2 - bcgelr icc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_icc 0xf 3 - bcgelr icc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr okh,lr - set_icc 0x0 0 - bcgelr icc0,1,0 - fail -okh: - set_spr_immed 1,lcr - set_spr_addr oki,lr - set_icc 0x1 1 - bcgelr icc1,1,1 - fail -oki: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x2 2 - bcgelr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x3 3 - bcgelr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okl,lr - set_icc 0x4 0 - bcgelr icc0,1,0 - fail -okl: - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_icc 0x5 1 - bcgelr icc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x6 2 - bcgelr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x7 3 - bcgelr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x8 0 - bcgelr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x9 1 - bcgelr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_icc 0xa 2 - bcgelr icc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_icc 0xb 3 - bcgelr icc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xc 0 - bcgelr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xd 1 - bcgelr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_icc 0xe 2 - bcgelr icc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_icc 0xf 3 - bcgelr icc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcgelr icc0,1,0 - - set_icc 0x1 1 - bcgelr icc1,1,1 - - set_icc 0x2 2 - bcgelr icc2,1,2 - - set_icc 0x3 3 - bcgelr icc3,1,3 - - set_icc 0x4 0 - bcgelr icc0,1,0 - - set_icc 0x5 1 - bcgelr icc1,1,1 - - set_icc 0x6 2 - bcgelr icc2,1,2 - - set_icc 0x7 3 - bcgelr icc3,1,3 - - set_icc 0x8 0 - bcgelr icc0,1,0 - - set_icc 0x9 1 - bcgelr icc1,1,1 - - set_icc 0xa 2 - bcgelr icc2,1,2 - - set_icc 0xb 3 - bcgelr icc3,1,3 - - set_icc 0xc 0 - bcgelr icc0,1,0 - - set_icc 0xd 1 - bcgelr icc1,1,1 - - set_icc 0xe 2 - bcgelr icc2,1,2 - - set_icc 0xf 3 - bcgelr icc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcgelr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x1 1 - bcgelr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x2 2 - bcgelr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x3 3 - bcgelr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x4 0 - bcgelr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x5 1 - bcgelr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x6 2 - bcgelr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x7 3 - bcgelr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x8 0 - bcgelr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x9 1 - bcgelr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xa 2 - bcgelr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xb 3 - bcgelr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0xc 0 - bcgelr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0xd 1 - bcgelr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xe 2 - bcgelr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xf 3 - bcgelr icc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bcgtlr.cgs b/sim/testsuite/sim/frv/bcgtlr.cgs deleted file mode 100644 index edffed83327..00000000000 --- a/sim/testsuite/sim/frv/bcgtlr.cgs +++ /dev/null @@ -1,284 +0,0 @@ -# frv testcase for bcgtlr $ICCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bcgtlr -bcgtlr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr ok1,lr - set_icc 0x0 0 - bcgtlr icc0,0,0 - fail -ok1: - set_spr_addr ok2,lr - set_icc 0x1 1 - bcgtlr icc1,0,1 - fail -ok2: - set_spr_addr bad,lr - set_icc 0x2 2 - bcgtlr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0x3 3 - bcgtlr icc3,0,3 - - set_spr_addr bad,lr - set_icc 0x4 0 - bcgtlr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0x5 1 - bcgtlr icc1,0,1 - - set_spr_addr bad,lr - set_icc 0x6 2 - bcgtlr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0x7 3 - bcgtlr icc3,0,3 - - set_spr_addr bad,lr - set_icc 0x8 0 - bcgtlr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0x9 1 - bcgtlr icc1,0,1 - - set_spr_addr okb,lr - set_icc 0xa 2 - bcgtlr icc2,0,2 - fail -okb: - set_spr_addr okc,lr - set_icc 0xb 3 - bcgtlr icc3,0,3 - fail -okc: - set_spr_addr bad,lr - set_icc 0xc 0 - bcgtlr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0xd 1 - bcgtlr icc1,0,1 - - set_spr_addr bad,lr - set_icc 0xe 2 - bcgtlr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0xf 3 - bcgtlr icc3,0,3 - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr okh,lr - set_icc 0x0 0 - bcgtlr icc0,1,0 - fail -okh: - set_spr_immed 1,lcr - set_spr_addr oki,lr - set_icc 0x1 1 - bcgtlr icc1,1,1 - fail -oki: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x2 2 - bcgtlr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x3 3 - bcgtlr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x4 0 - bcgtlr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x5 1 - bcgtlr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x6 2 - bcgtlr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x7 3 - bcgtlr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x8 0 - bcgtlr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x9 1 - bcgtlr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_icc 0xa 2 - bcgtlr icc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_icc 0xb 3 - bcgtlr icc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xc 0 - bcgtlr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xd 1 - bcgtlr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xe 2 - bcgtlr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xf 3 - bcgtlr icc3,1,3 - - ; ccond is false - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcgtlr icc0,1,0 - - set_icc 0x1 1 - bcgtlr icc1,1,1 - - set_icc 0x2 2 - bcgtlr icc2,1,2 - - set_icc 0x3 3 - bcgtlr icc3,1,3 - - set_icc 0x4 0 - bcgtlr icc0,1,0 - - set_icc 0x5 1 - bcgtlr icc1,1,1 - - set_icc 0x6 2 - bcgtlr icc2,1,2 - - set_icc 0x7 3 - bcgtlr icc3,1,3 - - set_icc 0x8 0 - bcgtlr icc0,1,0 - - set_icc 0x9 1 - bcgtlr icc1,1,1 - - set_icc 0xa 2 - bcgtlr icc2,1,2 - - set_icc 0xb 3 - bcgtlr icc3,1,3 - - set_icc 0xc 0 - bcgtlr icc0,1,0 - - set_icc 0xd 1 - bcgtlr icc1,1,1 - - set_icc 0xe 2 - bcgtlr icc2,1,2 - - set_icc 0xf 3 - bcgtlr icc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcgtlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x1 1 - bcgtlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x2 2 - bcgtlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x3 3 - bcgtlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x4 0 - bcgtlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x5 1 - bcgtlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x6 2 - bcgtlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x7 3 - bcgtlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x8 0 - bcgtlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x9 1 - bcgtlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xa 2 - bcgtlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xb 3 - bcgtlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0xc 0 - bcgtlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0xd 1 - bcgtlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xe 2 - bcgtlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xf 3 - bcgtlr icc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bchilr.cgs b/sim/testsuite/sim/frv/bchilr.cgs deleted file mode 100644 index ea7e2f4bac5..00000000000 --- a/sim/testsuite/sim/frv/bchilr.cgs +++ /dev/null @@ -1,284 +0,0 @@ -# frv testcase for bchilr $ICCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bchilr -bchilr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr ok1,lr - set_icc 0x0 0 - bchilr icc0,0,0 - fail -ok1: - set_spr_addr bad,lr - set_icc 0x1 1 - bchilr icc1,0,1 - - set_spr_addr ok3,lr - set_icc 0x2 2 - bchilr icc2,0,2 - fail -ok3: - set_spr_addr bad,lr - set_icc 0x3 3 - bchilr icc3,0,3 - - set_spr_addr bad,lr - set_icc 0x4 0 - bchilr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0x5 1 - bchilr icc1,0,1 - - set_spr_addr bad,lr - set_icc 0x6 2 - bchilr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0x7 3 - bchilr icc3,0,3 - - set_spr_addr ok9,lr - set_icc 0x8 0 - bchilr icc0,0,0 - fail -ok9: - set_spr_addr bad,lr - set_icc 0x9 1 - bchilr icc1,0,1 - - set_spr_addr okb,lr - set_icc 0xa 2 - bchilr icc2,0,2 - fail -okb: - set_spr_addr bad,lr - set_icc 0xb 3 - bchilr icc3,0,3 - - set_spr_addr bad,lr - set_icc 0xc 0 - bchilr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0xd 1 - bchilr icc1,0,1 - - set_spr_addr bad,lr - set_icc 0xe 2 - bchilr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0xf 3 - bchilr icc3,0,3 - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr okh,lr - set_icc 0x0 0 - bchilr icc0,1,0 - fail -okh: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x1 1 - bchilr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okj,lr - set_icc 0x2 2 - bchilr icc2,1,2 - fail -okj: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x3 3 - bchilr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x4 0 - bchilr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x5 1 - bchilr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x6 2 - bchilr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x7 3 - bchilr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okp,lr - set_icc 0x8 0 - bchilr icc0,1,0 - fail -okp: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x9 1 - bchilr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_icc 0xa 2 - bchilr icc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xb 3 - bchilr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xc 0 - bchilr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xd 1 - bchilr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xe 2 - bchilr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xf 3 - bchilr icc3,1,3 - - ; ccond is false - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bchilr icc0,1,0 - - set_icc 0x1 1 - bchilr icc1,1,1 - - set_icc 0x2 2 - bchilr icc2,1,2 - - set_icc 0x3 3 - bchilr icc3,1,3 - - set_icc 0x4 0 - bchilr icc0,1,0 - - set_icc 0x5 1 - bchilr icc1,1,1 - - set_icc 0x6 2 - bchilr icc2,1,2 - - set_icc 0x7 3 - bchilr icc3,1,3 - - set_icc 0x8 0 - bchilr icc0,1,0 - - set_icc 0x9 1 - bchilr icc1,1,1 - - set_icc 0xa 2 - bchilr icc2,1,2 - - set_icc 0xb 3 - bchilr icc3,1,3 - - set_icc 0xc 0 - bchilr icc0,1,0 - - set_icc 0xd 1 - bchilr icc1,1,1 - - set_icc 0xe 2 - bchilr icc2,1,2 - - set_icc 0xf 3 - bchilr icc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bchilr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x1 1 - bchilr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x2 2 - bchilr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x3 3 - bchilr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x4 0 - bchilr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x5 1 - bchilr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x6 2 - bchilr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x7 3 - bchilr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x8 0 - bchilr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x9 1 - bchilr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xa 2 - bchilr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xb 3 - bchilr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0xc 0 - bchilr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0xd 1 - bchilr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xe 2 - bchilr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xf 3 - bchilr icc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bclelr.cgs b/sim/testsuite/sim/frv/bclelr.cgs deleted file mode 100644 index 6668c77684b..00000000000 --- a/sim/testsuite/sim/frv/bclelr.cgs +++ /dev/null @@ -1,301 +0,0 @@ -# frv testcase for bclelr $ICCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bclelr -bclelr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bclelr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0x1 1 - bclelr icc1,0,1 - - set_spr_addr ok3,lr - set_icc 0x2 2 - bclelr icc2,0,2 - fail -ok3: - set_spr_addr ok4,lr - set_icc 0x3 3 - bclelr icc3,0,3 - fail -ok4: - set_spr_addr ok5,lr - set_icc 0x4 0 - bclelr icc0,0,0 - fail -ok5: - set_spr_addr ok6,lr - set_icc 0x5 1 - bclelr icc1,0,1 - fail -ok6: - set_spr_addr ok7,lr - set_icc 0x6 2 - bclelr icc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_icc 0x7 3 - bclelr icc3,0,3 - fail -ok8: - set_spr_addr ok9,lr - set_icc 0x8 0 - bclelr icc0,0,0 - fail -ok9: - set_spr_addr oka,lr - set_icc 0x9 1 - bclelr icc1,0,1 - fail -oka: - set_spr_addr bad,lr - set_icc 0xa 2 - bclelr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0xb 3 - bclelr icc3,0,3 - - set_spr_addr okd,lr - set_icc 0xc 0 - bclelr icc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_icc 0xd 1 - bclelr icc1,0,1 - fail -oke: - set_spr_addr okf,lr - set_icc 0xe 2 - bclelr icc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_icc 0xf 3 - bclelr icc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bclelr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x1 1 - bclelr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okj,lr - set_icc 0x2 2 - bclelr icc2,1,2 - fail -okj: - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_icc 0x3 3 - bclelr icc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr okl,lr - set_icc 0x4 0 - bclelr icc0,1,0 - fail -okl: - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_icc 0x5 1 - bclelr icc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_icc 0x6 2 - bclelr icc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_icc 0x7 3 - bclelr icc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr okp,lr - set_icc 0x8 0 - bclelr icc0,1,0 - fail -okp: - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_icc 0x9 1 - bclelr icc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xa 2 - bclelr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xb 3 - bclelr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_icc 0xc 0 - bclelr icc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_icc 0xd 1 - bclelr icc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_icc 0xe 2 - bclelr icc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_icc 0xf 3 - bclelr icc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bclelr icc0,1,0 - - set_icc 0x1 1 - bclelr icc1,1,1 - - set_icc 0x2 2 - bclelr icc2,1,2 - - set_icc 0x3 3 - bclelr icc3,1,3 - - set_icc 0x4 0 - bclelr icc0,1,0 - - set_icc 0x5 1 - bclelr icc1,1,1 - - set_icc 0x6 2 - bclelr icc2,1,2 - - set_icc 0x7 3 - bclelr icc3,1,3 - - set_icc 0x8 0 - bclelr icc0,1,0 - - set_icc 0x9 1 - bclelr icc1,1,1 - - set_icc 0xa 2 - bclelr icc2,1,2 - - set_icc 0xb 3 - bclelr icc3,1,3 - - set_icc 0xc 0 - bclelr icc0,1,0 - - set_icc 0xd 1 - bclelr icc1,1,1 - - set_icc 0xe 2 - bclelr icc2,1,2 - - set_icc 0xf 3 - bclelr icc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bclelr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x1 1 - bclelr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x2 2 - bclelr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x3 3 - bclelr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x4 0 - bclelr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x5 1 - bclelr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x6 2 - bclelr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x7 3 - bclelr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x8 0 - bclelr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x9 1 - bclelr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xa 2 - bclelr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xb 3 - bclelr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0xc 0 - bclelr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0xd 1 - bclelr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xe 2 - bclelr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xf 3 - bclelr icc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bclr.cgs b/sim/testsuite/sim/frv/bclr.cgs deleted file mode 100644 index d36563b618d..00000000000 --- a/sim/testsuite/sim/frv/bclr.cgs +++ /dev/null @@ -1,84 +0,0 @@ -# frv testcase for bclr $ICCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bclr -bclr: - set_spr_addr bad,lr - set_icc 0x0 0 - bclr icc0,0 - - set_spr_addr ok2,lr - set_icc 0x1 1 - bclr icc1,1 - fail -ok2: - set_spr_addr bad,lr - set_icc 0x2 2 - bclr icc2,2 - - set_spr_addr ok4,lr - set_icc 0x3 3 - bclr icc3,3 - fail -ok4: - set_spr_addr bad,lr - set_icc 0x4 0 - bclr icc0,0 - - set_spr_addr ok6,lr - set_icc 0x5 1 - bclr icc1,1 - fail -ok6: - set_spr_addr bad,lr - set_icc 0x6 2 - bclr icc2,2 - - set_spr_addr ok8,lr - set_icc 0x7 3 - bclr icc3,3 - fail -ok8: - set_spr_addr bad,lr - set_icc 0x8 0 - bclr icc0,0 - - set_spr_addr oka,lr - set_icc 0x9 1 - bclr icc1,1 - fail -oka: - set_spr_addr bad,lr - set_icc 0xa 2 - bclr icc2,2 - - set_spr_addr okc,lr - set_icc 0xb 3 - bclr icc3,3 - fail -okc: - set_spr_addr bad,lr - set_icc 0xc 0 - bclr icc0,0 - - set_spr_addr oke,lr - set_icc 0xd 1 - bclr icc1,1 - fail -oke: - set_spr_addr bad,lr - set_icc 0xe 2 - bclr icc2,2 - - set_spr_addr okg,lr - set_icc 0xf 3 - bclr icc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bclslr.cgs b/sim/testsuite/sim/frv/bclslr.cgs deleted file mode 100644 index 37b91bc105d..00000000000 --- a/sim/testsuite/sim/frv/bclslr.cgs +++ /dev/null @@ -1,301 +0,0 @@ -# frv testcase for bclslr $ICCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bclslr -bclslr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bclslr icc0,0,0 - - set_spr_addr ok2,lr - set_icc 0x1 1 - bclslr icc1,0,1 - fail -ok2: - set_spr_addr bad,lr - set_icc 0x2 2 - bclslr icc2,0,2 - - set_spr_addr ok4,lr - set_icc 0x3 3 - bclslr icc3,0,3 - fail -ok4: - set_spr_addr ok5,lr - set_icc 0x4 0 - bclslr icc0,0,0 - fail -ok5: - set_spr_addr ok6,lr - set_icc 0x5 1 - bclslr icc1,0,1 - fail -ok6: - set_spr_addr ok7,lr - set_icc 0x6 2 - bclslr icc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_icc 0x7 3 - bclslr icc3,0,3 - fail -ok8: - set_spr_addr bad,lr - set_icc 0x8 0 - bclslr icc0,0,0 - - set_spr_addr oka,lr - set_icc 0x9 1 - bclslr icc1,0,1 - fail -oka: - set_spr_addr bad,lr - set_icc 0xa 2 - bclslr icc2,0,2 - - set_spr_addr okc,lr - set_icc 0xb 3 - bclslr icc3,0,3 - fail -okc: - set_spr_addr okd,lr - set_icc 0xc 0 - bclslr icc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_icc 0xd 1 - bclslr icc1,0,1 - fail -oke: - set_spr_addr okf,lr - set_icc 0xe 2 - bclslr icc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_icc 0xf 3 - bclslr icc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bclslr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr oki,lr - set_icc 0x1 1 - bclslr icc1,1,1 - fail -oki: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x2 2 - bclslr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_icc 0x3 3 - bclslr icc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr okl,lr - set_icc 0x4 0 - bclslr icc0,1,0 - fail -okl: - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_icc 0x5 1 - bclslr icc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_icc 0x6 2 - bclslr icc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_icc 0x7 3 - bclslr icc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x8 0 - bclslr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_icc 0x9 1 - bclslr icc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xa 2 - bclslr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_icc 0xb 3 - bclslr icc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_icc 0xc 0 - bclslr icc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_icc 0xd 1 - bclslr icc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_icc 0xe 2 - bclslr icc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_icc 0xf 3 - bclslr icc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bclslr icc0,1,0 - - set_icc 0x1 1 - bclslr icc1,1,1 - - set_icc 0x2 2 - bclslr icc2,1,2 - - set_icc 0x3 3 - bclslr icc3,1,3 - - set_icc 0x4 0 - bclslr icc0,1,0 - - set_icc 0x5 1 - bclslr icc1,1,1 - - set_icc 0x6 2 - bclslr icc2,1,2 - - set_icc 0x7 3 - bclslr icc3,1,3 - - set_icc 0x8 0 - bclslr icc0,1,0 - - set_icc 0x9 1 - bclslr icc1,1,1 - - set_icc 0xa 2 - bclslr icc2,1,2 - - set_icc 0xb 3 - bclslr icc3,1,3 - - set_icc 0xc 0 - bclslr icc0,1,0 - - set_icc 0xd 1 - bclslr icc1,1,1 - - set_icc 0xe 2 - bclslr icc2,1,2 - - set_icc 0xf 3 - bclslr icc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bclslr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x1 1 - bclslr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x2 2 - bclslr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x3 3 - bclslr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x4 0 - bclslr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x5 1 - bclslr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x6 2 - bclslr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x7 3 - bclslr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x8 0 - bclslr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x9 1 - bclslr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xa 2 - bclslr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xb 3 - bclslr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0xc 0 - bclslr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0xd 1 - bclslr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xe 2 - bclslr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xf 3 - bclslr icc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bcltlr.cgs b/sim/testsuite/sim/frv/bcltlr.cgs deleted file mode 100644 index 0ba6bfa8aaf..00000000000 --- a/sim/testsuite/sim/frv/bcltlr.cgs +++ /dev/null @@ -1,292 +0,0 @@ -# frv testcase for bcltlr $ICCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bcltlr -bcltlr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcltlr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0x1 1 - bcltlr icc1,0,1 - - set_spr_addr ok3,lr - set_icc 0x2 2 - bcltlr icc2,0,2 - fail -ok3: - set_spr_addr ok4,lr - set_icc 0x3 3 - bcltlr icc3,0,3 - fail -ok4: - set_spr_addr bad,lr - set_icc 0x4 0 - bcltlr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0x5 1 - bcltlr icc1,0,1 - - set_spr_addr ok7,lr - set_icc 0x6 2 - bcltlr icc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_icc 0x7 3 - bcltlr icc3,0,3 - fail -ok8: - set_spr_addr ok9,lr - set_icc 0x8 0 - bcltlr icc0,0,0 - fail -ok9: - set_spr_addr oka,lr - set_icc 0x9 1 - bcltlr icc1,0,1 - fail -oka: - set_spr_addr bad,lr - set_icc 0xa 2 - bcltlr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0xb 3 - bcltlr icc3,0,3 - - set_spr_addr okd,lr - set_icc 0xc 0 - bcltlr icc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_icc 0xd 1 - bcltlr icc1,0,1 - fail -oke: - set_spr_addr bad,lr - set_icc 0xe 2 - bcltlr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0xf 3 - bcltlr icc3,0,3 - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcltlr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x1 1 - bcltlr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okj,lr - set_icc 0x2 2 - bcltlr icc2,1,2 - fail -okj: - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_icc 0x3 3 - bcltlr icc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x4 0 - bcltlr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x5 1 - bcltlr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_icc 0x6 2 - bcltlr icc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_icc 0x7 3 - bcltlr icc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr okp,lr - set_icc 0x8 0 - bcltlr icc0,1,0 - fail -okp: - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_icc 0x9 1 - bcltlr icc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xa 2 - bcltlr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xb 3 - bcltlr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_icc 0xc 0 - bcltlr icc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_icc 0xd 1 - bcltlr icc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xe 2 - bcltlr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xf 3 - bcltlr icc3,1,3 - - ; ccond is false - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcltlr icc0,1,0 - - set_icc 0x1 1 - bcltlr icc1,1,1 - - set_icc 0x2 2 - bcltlr icc2,1,2 - - set_icc 0x3 3 - bcltlr icc3,1,3 - - set_icc 0x4 0 - bcltlr icc0,1,0 - - set_icc 0x5 1 - bcltlr icc1,1,1 - - set_icc 0x6 2 - bcltlr icc2,1,2 - - set_icc 0x7 3 - bcltlr icc3,1,3 - - set_icc 0x8 0 - bcltlr icc0,1,0 - - set_icc 0x9 1 - bcltlr icc1,1,1 - - set_icc 0xa 2 - bcltlr icc2,1,2 - - set_icc 0xb 3 - bcltlr icc3,1,3 - - set_icc 0xc 0 - bcltlr icc0,1,0 - - set_icc 0xd 1 - bcltlr icc1,1,1 - - set_icc 0xe 2 - bcltlr icc2,1,2 - - set_icc 0xf 3 - bcltlr icc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcltlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x1 1 - bcltlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x2 2 - bcltlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x3 3 - bcltlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x4 0 - bcltlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x5 1 - bcltlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x6 2 - bcltlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x7 3 - bcltlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x8 0 - bcltlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x9 1 - bcltlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xa 2 - bcltlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xb 3 - bcltlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0xc 0 - bcltlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0xd 1 - bcltlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xe 2 - bcltlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xf 3 - bcltlr icc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bcnclr.cgs b/sim/testsuite/sim/frv/bcnclr.cgs deleted file mode 100644 index 51824a6295d..00000000000 --- a/sim/testsuite/sim/frv/bcnclr.cgs +++ /dev/null @@ -1,293 +0,0 @@ -# frv testcase for bcnclr $ICCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bcnclr -bcnclr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr ok1,lr - set_icc 0x0 0 - bcnclr icc0,0,0 - fail -ok1: - set_spr_addr bad,lr - set_icc 0x1 1 - bcnclr icc1,0,1 - - set_spr_addr ok3,lr - set_icc 0x2 2 - bcnclr icc2,0,2 - fail -ok3: - set_spr_addr bad,lr - set_icc 0x3 3 - bcnclr icc3,0,3 - - set_spr_addr ok5,lr - set_icc 0x4 0 - bcnclr icc0,0,0 - fail -ok5: - set_spr_addr bad,lr - set_icc 0x5 1 - bcnclr icc1,0,1 - - set_spr_addr ok7,lr - set_icc 0x6 2 - bcnclr icc2,0,2 - fail -ok7: - set_spr_addr bad,lr - set_icc 0x7 3 - bcnclr icc3,0,3 - - set_spr_addr ok9,lr - set_icc 0x8 0 - bcnclr icc0,0,0 - fail -ok9: - set_spr_addr bad,lr - set_icc 0x9 1 - bcnclr icc1,0,1 - - set_spr_addr okb,lr - set_icc 0xa 2 - bcnclr icc2,0,2 - fail -okb: - set_spr_addr bad,lr - set_icc 0xb 3 - bcnclr icc3,0,3 - - set_spr_addr okd,lr - set_icc 0xc 0 - bcnclr icc0,0,0 - fail -okd: - set_spr_addr bad,lr - set_icc 0xd 1 - bcnclr icc1,0,1 - - set_spr_addr okf,lr - set_icc 0xe 2 - bcnclr icc2,0,2 - fail -okf: - set_spr_addr bad,lr - set_icc 0xf 3 - bcnclr icc3,0,3 - - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr okh,lr - set_icc 0x0 0 - bcnclr icc0,1,0 - fail -okh: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x1 1 - bcnclr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okj,lr - set_icc 0x2 2 - bcnclr icc2,1,2 - fail -okj: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x3 3 - bcnclr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okl,lr - set_icc 0x4 0 - bcnclr icc0,1,0 - fail -okl: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x5 1 - bcnclr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_icc 0x6 2 - bcnclr icc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x7 3 - bcnclr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okp,lr - set_icc 0x8 0 - bcnclr icc0,1,0 - fail -okp: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x9 1 - bcnclr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_icc 0xa 2 - bcnclr icc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xb 3 - bcnclr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_icc 0xc 0 - bcnclr icc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xd 1 - bcnclr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_icc 0xe 2 - bcnclr icc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xf 3 - bcnclr icc3,1,3 - - ; ccond is false - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcnclr icc0,1,0 - - set_icc 0x1 1 - bcnclr icc1,1,1 - - set_icc 0x2 2 - bcnclr icc2,1,2 - - set_icc 0x3 3 - bcnclr icc3,1,3 - - set_icc 0x4 0 - bcnclr icc0,1,0 - - set_icc 0x5 1 - bcnclr icc1,1,1 - - set_icc 0x6 2 - bcnclr icc2,1,2 - - set_icc 0x7 3 - bcnclr icc3,1,3 - - set_icc 0x8 0 - bcnclr icc0,1,0 - - set_icc 0x9 1 - bcnclr icc1,1,1 - - set_icc 0xa 2 - bcnclr icc2,1,2 - - set_icc 0xb 3 - bcnclr icc3,1,3 - - set_icc 0xc 0 - bcnclr icc0,1,0 - - set_icc 0xd 1 - bcnclr icc1,1,1 - - set_icc 0xe 2 - bcnclr icc2,1,2 - - set_icc 0xf 3 - bcnclr icc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcnclr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x1 1 - bcnclr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x2 2 - bcnclr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x3 3 - bcnclr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x4 0 - bcnclr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x5 1 - bcnclr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x6 2 - bcnclr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x7 3 - bcnclr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x8 0 - bcnclr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x9 1 - bcnclr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xa 2 - bcnclr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xb 3 - bcnclr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0xc 0 - bcnclr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0xd 1 - bcnclr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xe 2 - bcnclr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xf 3 - bcnclr icc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bcnelr.cgs b/sim/testsuite/sim/frv/bcnelr.cgs deleted file mode 100644 index 55be2d3c156..00000000000 --- a/sim/testsuite/sim/frv/bcnelr.cgs +++ /dev/null @@ -1,292 +0,0 @@ -# frv testcase for bcnelr $ICCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bcnelr -bcnelr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr ok1,lr - set_icc 0x0 0 - bcnelr icc0,0,0 - fail -ok1: - set_spr_addr ok2,lr - set_icc 0x1 1 - bcnelr icc1,0,1 - fail -ok2: - set_spr_addr ok3,lr - set_icc 0x2 2 - bcnelr icc2,0,2 - fail -ok3: - set_spr_addr ok4,lr - set_icc 0x3 3 - bcnelr icc3,0,3 - fail -ok4: - set_spr_addr bad,lr - set_icc 0x4 0 - bcnelr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0x5 1 - bcnelr icc1,0,1 - - set_spr_addr bad,lr - set_icc 0x6 2 - bcnelr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0x7 3 - bcnelr icc3,0,3 - - set_spr_addr ok9,lr - set_icc 0x8 0 - bcnelr icc0,0,0 - fail -ok9: - set_spr_addr oka,lr - set_icc 0x9 1 - bcnelr icc1,0,1 - fail -oka: - set_spr_addr okb,lr - set_icc 0xa 2 - bcnelr icc2,0,2 - fail -okb: - set_spr_addr okc,lr - set_icc 0xb 3 - bcnelr icc3,0,3 - fail -okc: - set_spr_addr bad,lr - set_icc 0xc 0 - bcnelr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0xd 1 - bcnelr icc1,0,1 - - set_spr_addr bad,lr - set_icc 0xe 2 - bcnelr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0xf 3 - bcnelr icc3,0,3 - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr okh,lr - set_icc 0x0 0 - bcnelr icc0,1,0 - fail -okh: - set_spr_immed 1,lcr - set_spr_addr oki,lr - set_icc 0x1 1 - bcnelr icc1,1,1 - fail -oki: - set_spr_immed 1,lcr - set_spr_addr okj,lr - set_icc 0x2 2 - bcnelr icc2,1,2 - fail -okj: - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_icc 0x3 3 - bcnelr icc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x4 0 - bcnelr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x5 1 - bcnelr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x6 2 - bcnelr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x7 3 - bcnelr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okp,lr - set_icc 0x8 0 - bcnelr icc0,1,0 - fail -okp: - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_icc 0x9 1 - bcnelr icc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_icc 0xa 2 - bcnelr icc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_icc 0xb 3 - bcnelr icc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xc 0 - bcnelr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xd 1 - bcnelr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xe 2 - bcnelr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xf 3 - bcnelr icc3,1,3 - - ; ccond is false - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcnelr icc0,1,0 - - set_icc 0x1 1 - bcnelr icc1,1,1 - - set_icc 0x2 2 - bcnelr icc2,1,2 - - set_icc 0x3 3 - bcnelr icc3,1,3 - - set_icc 0x4 0 - bcnelr icc0,1,0 - - set_icc 0x5 1 - bcnelr icc1,1,1 - - set_icc 0x6 2 - bcnelr icc2,1,2 - - set_icc 0x7 3 - bcnelr icc3,1,3 - - set_icc 0x8 0 - bcnelr icc0,1,0 - - set_icc 0x9 1 - bcnelr icc1,1,1 - - set_icc 0xa 2 - bcnelr icc2,1,2 - - set_icc 0xb 3 - bcnelr icc3,1,3 - - set_icc 0xc 0 - bcnelr icc0,1,0 - - set_icc 0xd 1 - bcnelr icc1,1,1 - - set_icc 0xe 2 - bcnelr icc2,1,2 - - set_icc 0xf 3 - bcnelr icc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcnelr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x1 1 - bcnelr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x2 2 - bcnelr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x3 3 - bcnelr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x4 0 - bcnelr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x5 1 - bcnelr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x6 2 - bcnelr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x7 3 - bcnelr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x8 0 - bcnelr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x9 1 - bcnelr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xa 2 - bcnelr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xb 3 - bcnelr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0xc 0 - bcnelr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0xd 1 - bcnelr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xe 2 - bcnelr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xf 3 - bcnelr icc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bcnlr.cgs b/sim/testsuite/sim/frv/bcnlr.cgs deleted file mode 100644 index 8ddfcaa33d0..00000000000 --- a/sim/testsuite/sim/frv/bcnlr.cgs +++ /dev/null @@ -1,293 +0,0 @@ -# frv testcase for bcnlr $ICCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bcnlr -bcnlr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcnlr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0x1 1 - bcnlr icc1,0,1 - - set_spr_addr bad,lr - set_icc 0x2 2 - bcnlr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0x3 3 - bcnlr icc3,0,3 - - set_spr_addr bad,lr - set_icc 0x4 0 - bcnlr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0x5 1 - bcnlr icc1,0,1 - - set_spr_addr bad,lr - set_icc 0x6 2 - bcnlr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0x7 3 - bcnlr icc3,0,3 - - set_spr_addr ok9,lr - set_icc 0x8 0 - bcnlr icc0,0,0 - fail -ok9: - set_spr_addr oka,lr - set_icc 0x9 1 - bcnlr icc1,0,1 - fail -oka: - set_spr_addr okb,lr - set_icc 0xa 2 - bcnlr icc2,0,2 - fail -okb: - set_spr_addr okc,lr - set_icc 0xb 3 - bcnlr icc3,0,3 - fail -okc: - set_spr_addr okd,lr - set_icc 0xc 0 - bcnlr icc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_icc 0xd 1 - bcnlr icc1,0,1 - fail -oke: - set_spr_addr okf,lr - set_icc 0xe 2 - bcnlr icc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_icc 0xf 3 - bcnlr icc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcnlr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x1 1 - bcnlr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x2 2 - bcnlr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x3 3 - bcnlr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x4 0 - bcnlr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x5 1 - bcnlr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x6 2 - bcnlr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x7 3 - bcnlr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okp,lr - set_icc 0x8 0 - bcnlr icc0,1,0 - fail -okp: - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_icc 0x9 1 - bcnlr icc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_icc 0xa 2 - bcnlr icc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_icc 0xb 3 - bcnlr icc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_icc 0xc 0 - bcnlr icc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_icc 0xd 1 - bcnlr icc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_icc 0xe 2 - bcnlr icc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_icc 0xf 3 - bcnlr icc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcnlr icc0,1,0 - - set_icc 0x1 1 - bcnlr icc1,1,1 - - set_icc 0x2 2 - bcnlr icc2,1,2 - - set_icc 0x3 3 - bcnlr icc3,1,3 - - set_icc 0x4 0 - bcnlr icc0,1,0 - - set_icc 0x5 1 - bcnlr icc1,1,1 - - set_icc 0x6 2 - bcnlr icc2,1,2 - - set_icc 0x7 3 - bcnlr icc3,1,3 - - set_icc 0x8 0 - bcnlr icc0,1,0 - - set_icc 0x9 1 - bcnlr icc1,1,1 - - set_icc 0xa 2 - bcnlr icc2,1,2 - - set_icc 0xb 3 - bcnlr icc3,1,3 - - set_icc 0xc 0 - bcnlr icc0,1,0 - - set_icc 0xd 1 - bcnlr icc1,1,1 - - set_icc 0xe 2 - bcnlr icc2,1,2 - - set_icc 0xf 3 - bcnlr icc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcnlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x1 1 - bcnlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x2 2 - bcnlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x3 3 - bcnlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x4 0 - bcnlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x5 1 - bcnlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x6 2 - bcnlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x7 3 - bcnlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x8 0 - bcnlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x9 1 - bcnlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xa 2 - bcnlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xb 3 - bcnlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0xc 0 - bcnlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0xd 1 - bcnlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xe 2 - bcnlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xf 3 - bcnlr icc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bcnolr.cgs b/sim/testsuite/sim/frv/bcnolr.cgs deleted file mode 100644 index 04f0b8dbd84..00000000000 --- a/sim/testsuite/sim/frv/bcnolr.cgs +++ /dev/null @@ -1,246 +0,0 @@ -# frv testcase for bcnolr -# mach: all - - .include "testutils.inc" - - start - - .global bcnolr -bcnolr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcnolr - - set_icc 0x1 1 - bcnolr - - set_icc 0x2 2 - bcnolr - - set_icc 0x3 3 - bcnolr - - set_icc 0x4 0 - bcnolr - - set_icc 0x5 1 - bcnolr - - set_icc 0x6 2 - bcnolr - - set_icc 0x7 3 - bcnolr - - set_icc 0x8 0 - bcnolr - - set_icc 0x9 1 - bcnolr - - set_icc 0xa 2 - bcnolr - - set_icc 0xb 3 - bcnolr - - set_icc 0xc 0 - bcnolr - - set_icc 0xd 1 - bcnolr - - set_icc 0xe 2 - bcnolr - - set_icc 0xf 3 - bcnolr - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x1 1 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x2 2 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x3 3 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x4 0 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x5 1 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x6 2 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x7 3 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x8 0 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x9 1 - bcnolr - - set_spr_immed 1,lcr - set_icc 0xa 2 - bcnolr - - set_spr_immed 1,lcr - set_icc 0xb 3 - bcnolr - - set_spr_immed 1,lcr - set_icc 0xc 0 - bcnolr - - set_spr_immed 1,lcr - set_icc 0xd 1 - bcnolr - - set_spr_immed 1,lcr - set_icc 0xe 2 - bcnolr - - set_spr_immed 1,lcr - set_icc 0xf 3 - bcnolr - - ; ccond is false - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcnolr - - set_icc 0x1 1 - bcnolr - - set_icc 0x2 2 - bcnolr - - set_icc 0x3 3 - bcnolr - - set_icc 0x4 0 - bcnolr - - set_icc 0x5 1 - bcnolr - - set_icc 0x6 2 - bcnolr - - set_icc 0x7 3 - bcnolr - - set_icc 0x8 0 - bcnolr - - set_icc 0x9 1 - bcnolr - - set_icc 0xa 2 - bcnolr - - set_icc 0xb 3 - bcnolr - - set_icc 0xc 0 - bcnolr - - set_icc 0xd 1 - bcnolr - - set_icc 0xe 2 - bcnolr - - set_icc 0xf 3 - bcnolr - - ; ccond is false - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x1 1 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x2 2 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x3 3 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x4 0 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x5 1 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x6 2 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x7 3 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x8 0 - bcnolr - - set_spr_immed 1,lcr - set_icc 0x9 1 - bcnolr - - set_spr_immed 1,lcr - set_icc 0xa 2 - bcnolr - - set_spr_immed 1,lcr - set_icc 0xb 3 - bcnolr - - set_spr_immed 1,lcr - set_icc 0xc 0 - bcnolr - - set_spr_immed 1,lcr - set_icc 0xd 1 - bcnolr - - set_spr_immed 1,lcr - set_icc 0xe 2 - bcnolr - - set_spr_immed 1,lcr - set_icc 0xf 3 - bcnolr - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bcnvlr.cgs b/sim/testsuite/sim/frv/bcnvlr.cgs deleted file mode 100644 index 24515575ee5..00000000000 --- a/sim/testsuite/sim/frv/bcnvlr.cgs +++ /dev/null @@ -1,292 +0,0 @@ -# frv testcase for bcnvlr $ICCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bcnvlr -bcnvlr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr ok1,lr - set_icc 0x0 0 - bcnvlr icc0,0,0 - fail -ok1: - set_spr_addr ok2,lr - set_icc 0x1 1 - bcnvlr icc1,0,1 - fail -ok2: - set_spr_addr bad,lr - set_icc 0x2 2 - bcnvlr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0x3 3 - bcnvlr icc3,0,3 - - set_spr_addr ok5,lr - set_icc 0x4 0 - bcnvlr icc0,0,0 - fail -ok5: - set_spr_addr ok6,lr - set_icc 0x5 1 - bcnvlr icc1,0,1 - fail -ok6: - set_spr_addr bad,lr - set_icc 0x6 2 - bcnvlr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0x7 3 - bcnvlr icc3,0,3 - - set_spr_addr ok9,lr - set_icc 0x8 0 - bcnvlr icc0,0,0 - fail -ok9: - set_spr_addr oka,lr - set_icc 0x9 1 - bcnvlr icc1,0,1 - fail -oka: - set_spr_addr bad,lr - set_icc 0xa 2 - bcnvlr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0xb 3 - bcnvlr icc3,0,3 - - set_spr_addr okd,lr - set_icc 0xc 0 - bcnvlr icc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_icc 0xd 1 - bcnvlr icc1,0,1 - fail -oke: - set_spr_addr bad,lr - set_icc 0xe 2 - bcnvlr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0xf 3 - bcnvlr icc3,0,3 - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr okh,lr - set_icc 0x0 0 - bcnvlr icc0,1,0 - fail -okh: - set_spr_immed 1,lcr - set_spr_addr oki,lr - set_icc 0x1 1 - bcnvlr icc1,1,1 - fail -oki: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x2 2 - bcnvlr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x3 3 - bcnvlr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okl,lr - set_icc 0x4 0 - bcnvlr icc0,1,0 - fail -okl: - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_icc 0x5 1 - bcnvlr icc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x6 2 - bcnvlr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x7 3 - bcnvlr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okp,lr - set_icc 0x8 0 - bcnvlr icc0,1,0 - fail -okp: - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_icc 0x9 1 - bcnvlr icc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xa 2 - bcnvlr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xb 3 - bcnvlr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_icc 0xc 0 - bcnvlr icc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_icc 0xd 1 - bcnvlr icc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xe 2 - bcnvlr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xf 3 - bcnvlr icc3,1,3 - - ; ccond is false - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcnvlr icc0,1,0 - - set_icc 0x1 1 - bcnvlr icc1,1,1 - - set_icc 0x2 2 - bcnvlr icc2,1,2 - - set_icc 0x3 3 - bcnvlr icc3,1,3 - - set_icc 0x4 0 - bcnvlr icc0,1,0 - - set_icc 0x5 1 - bcnvlr icc1,1,1 - - set_icc 0x6 2 - bcnvlr icc2,1,2 - - set_icc 0x7 3 - bcnvlr icc3,1,3 - - set_icc 0x8 0 - bcnvlr icc0,1,0 - - set_icc 0x9 1 - bcnvlr icc1,1,1 - - set_icc 0xa 2 - bcnvlr icc2,1,2 - - set_icc 0xb 3 - bcnvlr icc3,1,3 - - set_icc 0xc 0 - bcnvlr icc0,1,0 - - set_icc 0xd 1 - bcnvlr icc1,1,1 - - set_icc 0xe 2 - bcnvlr icc2,1,2 - - set_icc 0xf 3 - bcnvlr icc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcnvlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x1 1 - bcnvlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x2 2 - bcnvlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x3 3 - bcnvlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x4 0 - bcnvlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x5 1 - bcnvlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x6 2 - bcnvlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x7 3 - bcnvlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x8 0 - bcnvlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x9 1 - bcnvlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xa 2 - bcnvlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xb 3 - bcnvlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0xc 0 - bcnvlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0xd 1 - bcnvlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xe 2 - bcnvlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xf 3 - bcnvlr icc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bcplr.cgs b/sim/testsuite/sim/frv/bcplr.cgs deleted file mode 100644 index fef3ccbadbe..00000000000 --- a/sim/testsuite/sim/frv/bcplr.cgs +++ /dev/null @@ -1,292 +0,0 @@ -# frv testcase for bcplr $ICCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bcplr -bcplr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr ok1,lr - set_icc 0x0 0 - bcplr icc0,0,0 - fail -ok1: - set_spr_addr ok2,lr - set_icc 0x1 1 - bcplr icc1,0,1 - fail -ok2: - set_spr_addr ok3,lr - set_icc 0x2 2 - bcplr icc2,0,2 - fail -ok3: - set_spr_addr ok4,lr - set_icc 0x3 3 - bcplr icc3,0,3 - fail -ok4: - set_spr_addr ok5,lr - set_icc 0x4 0 - bcplr icc0,0,0 - fail -ok5: - set_spr_addr ok6,lr - set_icc 0x5 1 - bcplr icc1,0,1 - fail -ok6: - set_spr_addr ok7,lr - set_icc 0x6 2 - bcplr icc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_icc 0x7 3 - bcplr icc3,0,3 - fail -ok8: - set_spr_addr bad,lr - set_icc 0x8 0 - bcplr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0x9 1 - bcplr icc1,0,1 - - set_spr_addr bad,lr - set_icc 0xa 2 - bcplr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0xb 3 - bcplr icc3,0,3 - - set_spr_addr bad,lr - set_icc 0xc 0 - bcplr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0xd 1 - bcplr icc1,0,1 - - set_spr_addr bad,lr - set_icc 0xe 2 - bcplr icc2,0,2 - - set_spr_addr bad,lr - set_icc 0xf 3 - bcplr icc3,0,3 - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr okh,lr - set_icc 0x0 0 - bcplr icc0,1,0 - fail -okh: - set_spr_immed 1,lcr - set_spr_addr oki,lr - set_icc 0x1 1 - bcplr icc1,1,1 - fail -oki: - set_spr_immed 1,lcr - set_spr_addr okj,lr - set_icc 0x2 2 - bcplr icc2,1,2 - fail -okj: - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_icc 0x3 3 - bcplr icc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr okl,lr - set_icc 0x4 0 - bcplr icc0,1,0 - fail -okl: - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_icc 0x5 1 - bcplr icc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_icc 0x6 2 - bcplr icc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_icc 0x7 3 - bcplr icc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x8 0 - bcplr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x9 1 - bcplr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xa 2 - bcplr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xb 3 - bcplr icc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xc 0 - bcplr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xd 1 - bcplr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xe 2 - bcplr icc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xf 3 - bcplr icc3,1,3 - - ; ccond is false - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcplr icc0,1,0 - - set_icc 0x1 1 - bcplr icc1,1,1 - - set_icc 0x2 2 - bcplr icc2,1,2 - - set_icc 0x3 3 - bcplr icc3,1,3 - - set_icc 0x4 0 - bcplr icc0,1,0 - - set_icc 0x5 1 - bcplr icc1,1,1 - - set_icc 0x6 2 - bcplr icc2,1,2 - - set_icc 0x7 3 - bcplr icc3,1,3 - - set_icc 0x8 0 - bcplr icc0,1,0 - - set_icc 0x9 1 - bcplr icc1,1,1 - - set_icc 0xa 2 - bcplr icc2,1,2 - - set_icc 0xb 3 - bcplr icc3,1,3 - - set_icc 0xc 0 - bcplr icc0,1,0 - - set_icc 0xd 1 - bcplr icc1,1,1 - - set_icc 0xe 2 - bcplr icc2,1,2 - - set_icc 0xf 3 - bcplr icc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcplr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x1 1 - bcplr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x2 2 - bcplr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x3 3 - bcplr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x4 0 - bcplr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x5 1 - bcplr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x6 2 - bcplr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x7 3 - bcplr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x8 0 - bcplr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x9 1 - bcplr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xa 2 - bcplr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xb 3 - bcplr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0xc 0 - bcplr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0xd 1 - bcplr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xe 2 - bcplr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xf 3 - bcplr icc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bcralr.cgs b/sim/testsuite/sim/frv/bcralr.cgs deleted file mode 100644 index 612363d62a7..00000000000 --- a/sim/testsuite/sim/frv/bcralr.cgs +++ /dev/null @@ -1,309 +0,0 @@ -# frv testcase for bcralr $ccond -# mach: all - - .include "testutils.inc" - - start - - .global bcralr -bcralr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr ok1,lr - set_icc 0x0 0 - bcralr 0 - fail -ok1: - set_spr_addr ok2,lr - set_icc 0x1 1 - bcralr 0 - fail -ok2: - set_spr_addr ok3,lr - set_icc 0x2 2 - bcralr 0 - fail -ok3: - set_spr_addr ok4,lr - set_icc 0x3 3 - bcralr 0 - fail -ok4: - set_spr_addr ok5,lr - set_icc 0x4 0 - bcralr 0 - fail -ok5: - set_spr_addr ok6,lr - set_icc 0x5 1 - bcralr 0 - fail -ok6: - set_spr_addr ok7,lr - set_icc 0x6 2 - bcralr 0 - fail -ok7: - set_spr_addr ok8,lr - set_icc 0x7 3 - bcralr 0 - fail -ok8: - set_spr_addr ok9,lr - set_icc 0x8 0 - bcralr 0 - fail -ok9: - set_spr_addr oka,lr - set_icc 0x9 1 - bcralr 0 - fail -oka: - set_spr_addr okb,lr - set_icc 0xa 2 - bcralr 0 - fail -okb: - set_spr_addr okc,lr - set_icc 0xb 3 - bcralr 0 - fail -okc: - set_spr_addr okd,lr - set_icc 0xc 0 - bcralr 0 - fail -okd: - set_spr_addr oke,lr - set_icc 0xd 1 - bcralr 0 - fail -oke: - set_spr_addr okf,lr - set_icc 0xe 2 - bcralr 0 - fail -okf: - set_spr_addr okg,lr - set_icc 0xf 3 - bcralr 0 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr okh,lr - set_icc 0x0 0 - bcralr 1 - fail -okh: - set_spr_immed 1,lcr - set_spr_addr oki,lr - set_icc 0x1 1 - bcralr 1 - fail -oki: - set_spr_immed 1,lcr - set_spr_addr okj,lr - set_icc 0x2 2 - bcralr 1 - fail -okj: - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_icc 0x3 3 - bcralr 1 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr okl,lr - set_icc 0x4 0 - bcralr 1 - fail -okl: - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_icc 0x5 1 - bcralr 1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_icc 0x6 2 - bcralr 1 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_icc 0x7 3 - bcralr 1 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr okp,lr - set_icc 0x8 0 - bcralr 1 - fail -okp: - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_icc 0x9 1 - bcralr 1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_icc 0xa 2 - bcralr 1 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_icc 0xb 3 - bcralr 1 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_icc 0xc 0 - bcralr 1 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_icc 0xd 1 - bcralr 1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_icc 0xe 2 - bcralr 1 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_icc 0xf 3 - bcralr 1 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcralr 1 - - set_icc 0x1 1 - bcralr 1 - - set_icc 0x2 2 - bcralr 1 - - set_icc 0x3 3 - bcralr 1 - - set_icc 0x4 0 - bcralr 1 - - set_icc 0x5 1 - bcralr 1 - - set_icc 0x6 2 - bcralr 1 - - set_icc 0x7 3 - bcralr 1 - - set_icc 0x8 0 - bcralr 1 - - set_icc 0x9 1 - bcralr 1 - - set_icc 0xa 2 - bcralr 1 - - set_icc 0xb 3 - bcralr 1 - - set_icc 0xc 0 - bcralr 1 - - set_icc 0xd 1 - bcralr 1 - - set_icc 0xe 2 - bcralr 1 - - set_icc 0xf 3 - bcralr 1 - - ; ccond is false - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcralr 0 - - set_spr_immed 1,lcr - set_icc 0x1 1 - bcralr 0 - - set_spr_immed 1,lcr - set_icc 0x2 2 - bcralr 0 - - set_spr_immed 1,lcr - set_icc 0x3 3 - bcralr 0 - - set_spr_immed 1,lcr - set_icc 0x4 0 - bcralr 0 - - set_spr_immed 1,lcr - set_icc 0x5 1 - bcralr 0 - - set_spr_immed 1,lcr - set_icc 0x6 2 - bcralr 0 - - set_spr_immed 1,lcr - set_icc 0x7 3 - bcralr 0 - - set_spr_immed 1,lcr - set_icc 0x8 0 - bcralr 0 - - set_spr_immed 1,lcr - set_icc 0x9 1 - bcralr 0 - - set_spr_immed 1,lcr - set_icc 0xa 2 - bcralr 0 - - set_spr_immed 1,lcr - set_icc 0xb 3 - bcralr 0 - - set_spr_immed 1,lcr - set_icc 0xc 0 - bcralr 0 - - set_spr_immed 1,lcr - set_icc 0xd 1 - bcralr 0 - - set_spr_immed 1,lcr - set_icc 0xe 2 - bcralr 0 - - set_spr_immed 1,lcr - set_icc 0xf 3 - bcralr 0 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bctrlr.cgs b/sim/testsuite/sim/frv/bctrlr.cgs deleted file mode 100644 index b00cb97aaf8..00000000000 --- a/sim/testsuite/sim/frv/bctrlr.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# frv testcase for bctrlr $ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bctrlr -bctrlr: - set_spr_addr bad,lr - set_spr_immed 1,lcr - bctrlr 0,0 - - set_spr_addr ok1,lr - set_spr_immed 2,lcr - bctrlr 0,0 - fail -ok1: - set_spr_addr bad,lr - set_spr_immed 2,lcr - bctrlr 1,0 - - set_spr_addr ok2,lr - bctrlr 1,0 - fail -ok2: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bcvlr.cgs b/sim/testsuite/sim/frv/bcvlr.cgs deleted file mode 100644 index b25d646092d..00000000000 --- a/sim/testsuite/sim/frv/bcvlr.cgs +++ /dev/null @@ -1,293 +0,0 @@ -# frv testcase for bcvlr $ICCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bcvlr -bcvlr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcvlr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0x1 1 - bcvlr icc1,0,1 - - set_spr_addr ok3,lr - set_icc 0x2 2 - bcvlr icc2,0,2 - fail -ok3: - set_spr_addr ok4,lr - set_icc 0x3 3 - bcvlr icc3,0,3 - fail -ok4: - set_spr_addr bad,lr - set_icc 0x4 0 - bcvlr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0x5 1 - bcvlr icc1,0,1 - - set_spr_addr ok7,lr - set_icc 0x6 2 - bcvlr icc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_icc 0x7 3 - bcvlr icc3,0,3 - fail -ok8: - set_spr_addr bad,lr - set_icc 0x8 0 - bcvlr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0x9 1 - bcvlr icc1,0,1 - - set_spr_addr okb,lr - set_icc 0xa 2 - bcvlr icc2,0,2 - fail -okb: - set_spr_addr okc,lr - set_icc 0xb 3 - bcvlr icc3,0,3 - fail -okc: - set_spr_addr bad,lr - set_icc 0xc 0 - bcvlr icc0,0,0 - - set_spr_addr bad,lr - set_icc 0xd 1 - bcvlr icc1,0,1 - - set_spr_addr okf,lr - set_icc 0xe 2 - bcvlr icc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_icc 0xf 3 - bcvlr icc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcvlr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x1 1 - bcvlr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okj,lr - set_icc 0x2 2 - bcvlr icc2,1,2 - fail -okj: - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_icc 0x3 3 - bcvlr icc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x4 0 - bcvlr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x5 1 - bcvlr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_icc 0x6 2 - bcvlr icc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_icc 0x7 3 - bcvlr icc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x8 0 - bcvlr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x9 1 - bcvlr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_icc 0xa 2 - bcvlr icc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_icc 0xb 3 - bcvlr icc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xc 0 - bcvlr icc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0xd 1 - bcvlr icc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_icc 0xe 2 - bcvlr icc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_icc 0xf 3 - bcvlr icc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcvlr icc0,1,0 - - set_icc 0x1 1 - bcvlr icc1,1,1 - - set_icc 0x2 2 - bcvlr icc2,1,2 - - set_icc 0x3 3 - bcvlr icc3,1,3 - - set_icc 0x4 0 - bcvlr icc0,1,0 - - set_icc 0x5 1 - bcvlr icc1,1,1 - - set_icc 0x6 2 - bcvlr icc2,1,2 - - set_icc 0x7 3 - bcvlr icc3,1,3 - - set_icc 0x8 0 - bcvlr icc0,1,0 - - set_icc 0x9 1 - bcvlr icc1,1,1 - - set_icc 0xa 2 - bcvlr icc2,1,2 - - set_icc 0xb 3 - bcvlr icc3,1,3 - - set_icc 0xc 0 - bcvlr icc0,1,0 - - set_icc 0xd 1 - bcvlr icc1,1,1 - - set_icc 0xe 2 - bcvlr icc2,1,2 - - set_icc 0xf 3 - bcvlr icc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_icc 0x0 0 - bcvlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x1 1 - bcvlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x2 2 - bcvlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x3 3 - bcvlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x4 0 - bcvlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x5 1 - bcvlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0x6 2 - bcvlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0x7 3 - bcvlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0x8 0 - bcvlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0x9 1 - bcvlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xa 2 - bcvlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xb 3 - bcvlr icc3,0,3 - - set_spr_immed 1,lcr - set_icc 0xc 0 - bcvlr icc0,0,0 - - set_spr_immed 1,lcr - set_icc 0xd 1 - bcvlr icc1,0,1 - - set_spr_immed 1,lcr - set_icc 0xe 2 - bcvlr icc2,0,2 - - set_spr_immed 1,lcr - set_icc 0xf 3 - bcvlr icc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/beq.cgs b/sim/testsuite/sim/frv/beq.cgs deleted file mode 100644 index b3706dc09e0..00000000000 --- a/sim/testsuite/sim/frv/beq.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for beq $ICCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global beq -beq: - set_icc 0x0 0 - beq icc0,0,bad - set_icc 0x1 1 - beq icc1,1,bad - set_icc 0x2 2 - beq icc2,2,bad - set_icc 0x3 3 - beq icc3,3,bad - set_icc 0x4 0 - beq icc0,0,ok1 - fail -ok1: - set_icc 0x5 1 - beq icc1,1,ok2 - fail -ok2: - set_icc 0x6 2 - beq icc2,2,ok3 - fail -ok3: - set_icc 0x7 3 - beq icc3,3,ok4 - fail -ok4: - set_icc 0x8 0 - beq icc0,0,bad - set_icc 0x9 1 - beq icc1,1,bad - set_icc 0xa 2 - beq icc2,2,bad - set_icc 0xb 3 - beq icc3,3,bad - set_icc 0xc 0 - beq icc0,0,ok5 - fail -ok5: - set_icc 0xd 1 - beq icc1,1,ok6 - fail -ok6: - set_icc 0xe 2 - beq icc2,2,ok7 - fail -ok7: - set_icc 0xf 3 - beq icc3,3,ok8 - fail -ok8: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/beqlr.cgs b/sim/testsuite/sim/frv/beqlr.cgs deleted file mode 100644 index 772b9faf197..00000000000 --- a/sim/testsuite/sim/frv/beqlr.cgs +++ /dev/null @@ -1,71 +0,0 @@ -# frv testcase for beqlr $ICCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global beqlr -beqlr: - set_spr_addr bad,lr - set_icc 0x0 0 - beqlr icc0,0 - set_icc 0x1 1 - beqlr icc1,1 - set_icc 0x2 2 - beqlr icc2,2 - set_icc 0x3 3 - beqlr icc3,3 - set_spr_addr ok1,lr - set_icc 0x4 0 - beqlr icc0,0 - fail -ok1: - set_spr_addr ok2,lr - set_icc 0x5 1 - beqlr icc1,1 - fail -ok2: - set_spr_addr ok3,lr - set_icc 0x6 2 - beqlr icc2,2 - fail -ok3: - set_spr_addr ok4,lr - set_icc 0x7 3 - beqlr icc3,3 - fail -ok4: - set_spr_addr bad,lr - set_icc 0x8 0 - beqlr icc0,0 - set_icc 0x9 1 - beqlr icc1,1 - set_icc 0xa 2 - beqlr icc2,2 - set_icc 0xb 3 - beqlr icc3,3 - set_spr_addr ok5,lr - set_icc 0xc 0 - beqlr icc0,0 - fail -ok5: - set_spr_addr ok6,lr - set_icc 0xd 1 - beqlr icc1,1 - fail -ok6: - set_spr_addr ok7,lr - set_icc 0xe 2 - beqlr icc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_icc 0xf 3 - beqlr icc3,3 - fail -ok8: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bge.cgs b/sim/testsuite/sim/frv/bge.cgs deleted file mode 100644 index 7ebead7e5ee..00000000000 --- a/sim/testsuite/sim/frv/bge.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for bge $ICCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global bge -bge: - set_icc 0x0 0 - bge icc0,0,ok1 - fail -ok1: - set_icc 0x1 1 - bge icc1,1,ok2 - fail -ok2: - set_icc 0x2 2 - bge icc2,2,bad - set_icc 0x3 3 - bge icc3,3,bad - set_icc 0x4 0 - bge icc0,0,ok5 - fail -ok5: - set_icc 0x5 1 - bge icc1,1,ok6 - fail -ok6: - set_icc 0x6 2 - bge icc2,2,bad - set_icc 0x7 3 - bge icc3,3,bad - set_icc 0x8 0 - bge icc0,0,bad - set_icc 0x9 1 - bge icc1,1,bad - set_icc 0xa 2 - bge icc2,2,okb - fail -okb: - set_icc 0xb 3 - bge icc3,3,okc - fail -okc: - set_icc 0xc 0 - bge icc0,0,bad - set_icc 0xd 1 - bge icc1,1,bad - set_icc 0xe 2 - bge icc2,2,okf - fail -okf: - set_icc 0xf 3 - bge icc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bgelr.cgs b/sim/testsuite/sim/frv/bgelr.cgs deleted file mode 100644 index 806770a2c27..00000000000 --- a/sim/testsuite/sim/frv/bgelr.cgs +++ /dev/null @@ -1,84 +0,0 @@ -# frv testcase for bgelr $ICCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bgelr -bgelr: - set_spr_addr ok1,lr - set_icc 0x0 0 - bgelr icc0,0 - fail -ok1: - set_spr_addr ok2,lr - set_icc 0x1 1 - bgelr icc1,1 - fail -ok2: - set_spr_addr bad,lr - set_icc 0x2 2 - bgelr icc2,2 - - set_spr_addr bad,lr - set_icc 0x3 3 - bgelr icc3,3 - - set_spr_addr ok5,lr - set_icc 0x4 0 - bgelr icc0,0 - fail -ok5: - set_spr_addr ok6,lr - set_icc 0x5 1 - bgelr icc1,1 - fail -ok6: - set_spr_addr bad,lr - set_icc 0x6 2 - bgelr icc2,2 - - set_spr_addr bad,lr - set_icc 0x7 3 - bgelr icc3,3 - - set_spr_addr bad,lr - set_icc 0x8 0 - bgelr icc0,0 - - set_spr_addr bad,lr - set_icc 0x9 1 - bgelr icc1,1 - - set_spr_addr okb,lr - set_icc 0xa 2 - bgelr icc2,2 - fail -okb: - set_spr_addr okc,lr - set_icc 0xb 3 - bgelr icc3,3 - fail -okc: - set_spr_addr bad,lr - set_icc 0xc 0 - bgelr icc0,0 - - set_spr_addr bad,lr - set_icc 0xd 1 - bgelr icc1,1 - - set_spr_addr okf,lr - set_icc 0xe 2 - bgelr icc2,2 - fail -okf: - set_spr_addr okg,lr - set_icc 0xf 3 - bgelr icc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bgt.cgs b/sim/testsuite/sim/frv/bgt.cgs deleted file mode 100644 index 98b1b17fadb..00000000000 --- a/sim/testsuite/sim/frv/bgt.cgs +++ /dev/null @@ -1,53 +0,0 @@ -# frv testcase for bgt $ICCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global bgt -bgt: - set_icc 0x0 0 - bgt icc0,0,ok1 - fail -ok1: - set_icc 0x1 1 - bgt icc1,1,ok2 - fail -ok2: - set_icc 0x2 2 - bgt icc2,2,bad - set_icc 0x3 3 - bgt icc3,3,bad - set_icc 0x4 0 - bgt icc0,0,bad - set_icc 0x5 1 - bgt icc1,1,bad - set_icc 0x6 2 - bgt icc2,2,bad - set_icc 0x7 3 - bgt icc3,3,bad - set_icc 0x8 0 - bgt icc0,0,bad - set_icc 0x9 1 - bgt icc1,1,bad - set_icc 0xa 2 - bgt icc2,2,okb - fail -okb: - set_icc 0xb 3 - bgt icc3,3,okc - fail -okc: - set_icc 0xc 0 - bgt icc0,0,bad - set_icc 0xd 1 - bgt icc1,1,bad - set_icc 0xe 2 - bgt icc2,2,bad - set_icc 0xf 3 - bgt icc3,3,bad - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bgtlr.cgs b/sim/testsuite/sim/frv/bgtlr.cgs deleted file mode 100644 index ad44a2ce2b1..00000000000 --- a/sim/testsuite/sim/frv/bgtlr.cgs +++ /dev/null @@ -1,80 +0,0 @@ -# frv testcase for bgtlr $ICCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bgtlr -bgtlr: - set_spr_addr ok1,lr - set_icc 0x0 0 - bgtlr icc0,0 - fail -ok1: - set_spr_addr ok2,lr - set_icc 0x1 1 - bgtlr icc1,1 - fail -ok2: - set_spr_addr bad,lr - set_icc 0x2 2 - bgtlr icc2,2 - - set_spr_addr bad,lr - set_icc 0x3 3 - bgtlr icc3,3 - - set_spr_addr bad,lr - set_icc 0x4 0 - bgtlr icc0,0 - - set_spr_addr bad,lr - set_icc 0x5 1 - bgtlr icc1,1 - - set_spr_addr bad,lr - set_icc 0x6 2 - bgtlr icc2,2 - - set_spr_addr bad,lr - set_icc 0x7 3 - bgtlr icc3,3 - - set_spr_addr bad,lr - set_icc 0x8 0 - bgtlr icc0,0 - - set_spr_addr bad,lr - set_icc 0x9 1 - bgtlr icc1,1 - - set_spr_addr okb,lr - set_icc 0xa 2 - bgtlr icc2,2 - fail -okb: - set_spr_addr okc,lr - set_icc 0xb 3 - bgtlr icc3,3 - fail -okc: - set_spr_addr bad,lr - set_icc 0xc 0 - bgtlr icc0,0 - - set_spr_addr bad,lr - set_icc 0xd 1 - bgtlr icc1,1 - - set_spr_addr bad,lr - set_icc 0xe 2 - bgtlr icc2,2 - - set_spr_addr bad,lr - set_icc 0xf 3 - bgtlr icc3,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bhi.cgs b/sim/testsuite/sim/frv/bhi.cgs deleted file mode 100644 index a92c0c0b307..00000000000 --- a/sim/testsuite/sim/frv/bhi.cgs +++ /dev/null @@ -1,53 +0,0 @@ -# frv testcase for bhi $ICCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global bhi -bhi: - set_icc 0x0 0 - bhi icc0,0,ok1 - fail -ok1: - set_icc 0x1 1 - bhi icc1,1,bad - set_icc 0x2 2 - bhi icc2,2,ok3 - fail -ok3: - set_icc 0x3 3 - bhi icc3,3,bad - set_icc 0x4 0 - bhi icc0,0,bad - set_icc 0x5 1 - bhi icc1,1,bad - set_icc 0x6 2 - bhi icc2,2,bad - set_icc 0x7 3 - bhi icc3,3,bad - set_icc 0x8 0 - bhi icc0,0,ok9 - fail -ok9: - set_icc 0x9 1 - bhi icc1,1,bad - set_icc 0xa 2 - bhi icc2,2,okb - fail -okb: - set_icc 0xb 3 - bhi icc3,3,bad - set_icc 0xc 0 - bhi icc0,0,bad - set_icc 0xd 1 - bhi icc1,1,bad - set_icc 0xe 2 - bhi icc2,2,bad - set_icc 0xf 3 - bhi icc3,3,bad - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bhilr.cgs b/sim/testsuite/sim/frv/bhilr.cgs deleted file mode 100644 index 927643b2170..00000000000 --- a/sim/testsuite/sim/frv/bhilr.cgs +++ /dev/null @@ -1,80 +0,0 @@ -# frv testcase for bhilr $ICCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bhilr -bhilr: - set_spr_addr ok1,lr - set_icc 0x0 0 - bhilr icc0,0 - fail -ok1: - set_spr_addr bad,lr - set_icc 0x1 1 - bhilr icc1,1 - - set_spr_addr ok3,lr - set_icc 0x2 2 - bhilr icc2,2 - fail -ok3: - set_spr_addr bad,lr - set_icc 0x3 3 - bhilr icc3,3 - - set_spr_addr bad,lr - set_icc 0x4 0 - bhilr icc0,0 - - set_spr_addr bad,lr - set_icc 0x5 1 - bhilr icc1,1 - - set_spr_addr bad,lr - set_icc 0x6 2 - bhilr icc2,2 - - set_spr_addr bad,lr - set_icc 0x7 3 - bhilr icc3,3 - - set_spr_addr ok9,lr - set_icc 0x8 0 - bhilr icc0,0 - fail -ok9: - set_spr_addr bad,lr - set_icc 0x9 1 - bhilr icc1,1 - - set_spr_addr okb,lr - set_icc 0xa 2 - bhilr icc2,2 - fail -okb: - set_spr_addr bad,lr - set_icc 0xb 3 - bhilr icc3,3 - - set_spr_addr bad,lr - set_icc 0xc 0 - bhilr icc0,0 - - set_spr_addr bad,lr - set_icc 0xd 1 - bhilr icc1,1 - - set_spr_addr bad,lr - set_icc 0xe 2 - bhilr icc2,2 - - set_spr_addr bad,lr - set_icc 0xf 3 - bhilr icc3,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ble.cgs b/sim/testsuite/sim/frv/ble.cgs deleted file mode 100644 index c3587663606..00000000000 --- a/sim/testsuite/sim/frv/ble.cgs +++ /dev/null @@ -1,69 +0,0 @@ -# frv testcase for ble $ICCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global ble -ble: - set_icc 0x0 0 - ble icc0,0,bad - set_icc 0x1 1 - ble icc1,1,bad - set_icc 0x2 2 - ble icc2,2,ok3 - fail -ok3: - set_icc 0x3 3 - ble icc3,3,ok4 - fail -ok4: - set_icc 0x4 0 - ble icc0,0,ok5 - fail -ok5: - set_icc 0x5 1 - ble icc1,1,ok6 - fail -ok6: - set_icc 0x6 2 - ble icc2,2,ok7 - fail -ok7: - set_icc 0x7 3 - ble icc3,3,ok8 - fail -ok8: - set_icc 0x8 0 - ble icc0,0,ok9 - fail -ok9: - set_icc 0x9 1 - ble icc1,1,oka - fail -oka: - set_icc 0xa 2 - ble icc2,2,bad - set_icc 0xb 3 - ble icc3,3,bad - set_icc 0xc 0 - ble icc0,0,okd - fail -okd: - set_icc 0xd 1 - ble icc1,1,oke - fail -oke: - set_icc 0xe 2 - ble icc2,2,okf - fail -okf: - set_icc 0xf 3 - ble icc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/blelr.cgs b/sim/testsuite/sim/frv/blelr.cgs deleted file mode 100644 index dbb8e84539a..00000000000 --- a/sim/testsuite/sim/frv/blelr.cgs +++ /dev/null @@ -1,88 +0,0 @@ -# frv testcase for blelr $ICCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global blelr -blelr: - set_spr_addr bad,lr - set_icc 0x0 0 - blelr icc0,0 - - set_spr_addr bad,lr - set_icc 0x1 1 - blelr icc1,1 - - set_spr_addr ok3,lr - set_icc 0x2 2 - blelr icc2,2 - fail -ok3: - set_spr_addr ok4,lr - set_icc 0x3 3 - blelr icc3,3 - fail -ok4: - set_spr_addr ok5,lr - set_icc 0x4 0 - blelr icc0,0 - fail -ok5: - set_spr_addr ok6,lr - set_icc 0x5 1 - blelr icc1,1 - fail -ok6: - set_spr_addr ok7,lr - set_icc 0x6 2 - blelr icc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_icc 0x7 3 - blelr icc3,3 - fail -ok8: - set_spr_addr ok9,lr - set_icc 0x8 0 - blelr icc0,0 - fail -ok9: - set_spr_addr oka,lr - set_icc 0x9 1 - blelr icc1,1 - fail -oka: - set_spr_addr bad,lr - set_icc 0xa 2 - blelr icc2,2 - - set_spr_addr bad,lr - set_icc 0xb 3 - blelr icc3,3 - - set_spr_addr okd,lr - set_icc 0xc 0 - blelr icc0,0 - fail -okd: - set_spr_addr oke,lr - set_icc 0xd 1 - blelr icc1,1 - fail -oke: - set_spr_addr okf,lr - set_icc 0xe 2 - blelr icc2,2 - fail -okf: - set_spr_addr okg,lr - set_icc 0xf 3 - blelr icc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bls.cgs b/sim/testsuite/sim/frv/bls.cgs deleted file mode 100644 index e868de62af3..00000000000 --- a/sim/testsuite/sim/frv/bls.cgs +++ /dev/null @@ -1,69 +0,0 @@ -# frv testcase for bls $ICCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global bls -bls: - set_icc 0x0 0 - bls icc0,0,bad - set_icc 0x1 1 - bls icc1,1,ok2 - fail -ok2: - set_icc 0x2 2 - bls icc2,2,bad - set_icc 0x3 3 - bls icc3,3,ok4 - fail -ok4: - set_icc 0x4 0 - bls icc0,0,ok5 - fail -ok5: - set_icc 0x5 1 - bls icc1,1,ok6 - fail -ok6: - set_icc 0x6 2 - bls icc2,2,ok7 - fail -ok7: - set_icc 0x7 3 - bls icc3,3,ok8 - fail -ok8: - set_icc 0x8 0 - bls icc0,0,bad - set_icc 0x9 1 - bls icc1,1,oka - fail -oka: - set_icc 0xa 2 - bls icc2,2,bad - set_icc 0xb 3 - bls icc3,3,okc - fail -okc: - set_icc 0xc 0 - bls icc0,0,okd - fail -okd: - set_icc 0xd 1 - bls icc1,1,oke - fail -oke: - set_icc 0xe 2 - bls icc2,2,okf - fail -okf: - set_icc 0xf 3 - bls icc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/blslr.cgs b/sim/testsuite/sim/frv/blslr.cgs deleted file mode 100644 index 5166c52a54c..00000000000 --- a/sim/testsuite/sim/frv/blslr.cgs +++ /dev/null @@ -1,88 +0,0 @@ -# frv testcase for blslr $ICCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global blslr -blslr: - set_spr_addr bad,lr - set_icc 0x0 0 - blslr icc0,0 - - set_spr_addr ok2,lr - set_icc 0x1 1 - blslr icc1,1 - fail -ok2: - set_spr_addr bad,lr - set_icc 0x2 2 - blslr icc2,2 - - set_spr_addr ok4,lr - set_icc 0x3 3 - blslr icc3,3 - fail -ok4: - set_spr_addr ok5,lr - set_icc 0x4 0 - blslr icc0,0 - fail -ok5: - set_spr_addr ok6,lr - set_icc 0x5 1 - blslr icc1,1 - fail -ok6: - set_spr_addr ok7,lr - set_icc 0x6 2 - blslr icc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_icc 0x7 3 - blslr icc3,3 - fail -ok8: - set_spr_addr bad,lr - set_icc 0x8 0 - blslr icc0,0 - - set_spr_addr oka,lr - set_icc 0x9 1 - blslr icc1,1 - fail -oka: - set_spr_addr bad,lr - set_icc 0xa 2 - blslr icc2,2 - - set_spr_addr okc,lr - set_icc 0xb 3 - blslr icc3,3 - fail -okc: - set_spr_addr okd,lr - set_icc 0xc 0 - blslr icc0,0 - fail -okd: - set_spr_addr oke,lr - set_icc 0xd 1 - blslr icc1,1 - fail -oke: - set_spr_addr okf,lr - set_icc 0xe 2 - blslr icc2,2 - fail -okf: - set_spr_addr okg,lr - set_icc 0xf 3 - blslr icc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/blt.cgs b/sim/testsuite/sim/frv/blt.cgs deleted file mode 100644 index 639f9710a43..00000000000 --- a/sim/testsuite/sim/frv/blt.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for blt $ICCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global blt -blt: - set_icc 0x0 0 - blt icc0,0,bad - set_icc 0x1 1 - blt icc1,1,bad - set_icc 0x2 2 - blt icc2,2,ok3 - fail -ok3: - set_icc 0x3 3 - blt icc3,3,ok4 - fail -ok4: - set_icc 0x4 0 - blt icc0,0,bad - set_icc 0x5 1 - blt icc1,1,bad - set_icc 0x6 2 - blt icc2,2,ok7 - fail -ok7: - set_icc 0x7 3 - blt icc3,3,ok8 - fail -ok8: - set_icc 0x8 0 - blt icc0,0,ok9 - fail -ok9: - set_icc 0x9 1 - blt icc1,1,oka - fail -oka: - set_icc 0xa 2 - blt icc2,2,bad - set_icc 0xb 3 - blt icc3,3,bad - set_icc 0xc 0 - blt icc0,0,okd - fail -okd: - set_icc 0xd 1 - blt icc1,1,oke - fail -oke: - set_icc 0xe 2 - blt icc2,2,bad - set_icc 0xf 3 - blt icc3,3,bad - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bltlr.cgs b/sim/testsuite/sim/frv/bltlr.cgs deleted file mode 100644 index fcf04b5db7a..00000000000 --- a/sim/testsuite/sim/frv/bltlr.cgs +++ /dev/null @@ -1,84 +0,0 @@ -# frv testcase for bltlr $ICCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bltlr -bltlr: - set_spr_addr bad,lr - set_icc 0x0 0 - bltlr icc0,0 - - set_spr_addr bad,lr - set_icc 0x1 1 - bltlr icc1,1 - - set_spr_addr ok3,lr - set_icc 0x2 2 - bltlr icc2,2 - fail -ok3: - set_spr_addr ok4,lr - set_icc 0x3 3 - bltlr icc3,3 - fail -ok4: - set_spr_addr bad,lr - set_icc 0x4 0 - bltlr icc0,0 - - set_spr_addr bad,lr - set_icc 0x5 1 - bltlr icc1,1 - - set_spr_addr ok7,lr - set_icc 0x6 2 - bltlr icc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_icc 0x7 3 - bltlr icc3,3 - fail -ok8: - set_spr_addr ok9,lr - set_icc 0x8 0 - bltlr icc0,0 - fail -ok9: - set_spr_addr oka,lr - set_icc 0x9 1 - bltlr icc1,1 - fail -oka: - set_spr_addr bad,lr - set_icc 0xa 2 - bltlr icc2,2 - - set_spr_addr bad,lr - set_icc 0xb 3 - bltlr icc3,3 - - set_spr_addr okd,lr - set_icc 0xc 0 - bltlr icc0,0 - fail -okd: - set_spr_addr oke,lr - set_icc 0xd 1 - bltlr icc1,1 - fail -oke: - set_spr_addr bad,lr - set_icc 0xe 2 - bltlr icc2,2 - - set_spr_addr bad,lr - set_icc 0xf 3 - bltlr icc3,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bn.cgs b/sim/testsuite/sim/frv/bn.cgs deleted file mode 100644 index e5ff3977bb4..00000000000 --- a/sim/testsuite/sim/frv/bn.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for bn $ICCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global bn -bn: - set_icc 0x0 0 - bn icc0,0,bad - set_icc 0x1 1 - bn icc1,1,bad - set_icc 0x2 2 - bn icc2,2,bad - set_icc 0x3 3 - bn icc3,3,bad - set_icc 0x4 0 - bn icc0,0,bad - set_icc 0x5 1 - bn icc1,1,bad - set_icc 0x6 2 - bn icc2,2,bad - set_icc 0x7 3 - bn icc3,3,bad - set_icc 0x8 0 - bn icc0,0,ok9 - fail -ok9: - set_icc 0x9 1 - bn icc1,1,oka - fail -oka: - set_icc 0xa 2 - bn icc2,2,okb - fail -okb: - set_icc 0xb 3 - bn icc3,3,okc - fail -okc: - set_icc 0xc 0 - bn icc0,0,okd - fail -okd: - set_icc 0xd 1 - bn icc1,1,oke - fail -oke: - set_icc 0xe 2 - bn icc2,2,okf - fail -okf: - set_icc 0xf 3 - bn icc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bnc.cgs b/sim/testsuite/sim/frv/bnc.cgs deleted file mode 100644 index 6f14e6cd550..00000000000 --- a/sim/testsuite/sim/frv/bnc.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for bnc $ICCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global bnc -bnc: - set_icc 0x0 0 - bnc icc0,0,ok1 - fail -ok1: - set_icc 0x1 1 - bnc icc1,1,bad - set_icc 0x2 2 - bnc icc2,2,ok3 - fail -ok3: - set_icc 0x3 3 - bnc icc3,3,bad - set_icc 0x4 0 - bnc icc0,0,ok5 - fail -ok5: - set_icc 0x5 1 - bnc icc1,1,bad - set_icc 0x6 2 - bnc icc2,2,ok7 - fail -ok7: - set_icc 0x7 3 - bnc icc3,3,bad - set_icc 0x8 0 - bnc icc0,0,ok9 - fail -ok9: - set_icc 0x9 1 - bnc icc1,1,bad - set_icc 0xa 2 - bnc icc2,2,okb - fail -okb: - set_icc 0xb 3 - bnc icc3,3,bad - set_icc 0xc 0 - bnc icc0,0,okd - fail -okd: - set_icc 0xd 1 - bnc icc1,1,bad - set_icc 0xe 2 - bnc icc2,2,okf - fail -okf: - set_icc 0xf 3 - bnc icc3,3,bad - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bnclr.cgs b/sim/testsuite/sim/frv/bnclr.cgs deleted file mode 100644 index d24f8eb5463..00000000000 --- a/sim/testsuite/sim/frv/bnclr.cgs +++ /dev/null @@ -1,84 +0,0 @@ -# frv testcase for bnclr $ICCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bnclr -bnclr: - set_spr_addr ok1,lr - set_icc 0x0 0 - bnclr icc0,0 - fail -ok1: - set_spr_addr bad,lr - set_icc 0x1 1 - bnclr icc1,1 - - set_spr_addr ok3,lr - set_icc 0x2 2 - bnclr icc2,2 - fail -ok3: - set_spr_addr bad,lr - set_icc 0x3 3 - bnclr icc3,3 - - set_spr_addr ok5,lr - set_icc 0x4 0 - bnclr icc0,0 - fail -ok5: - set_spr_addr bad,lr - set_icc 0x5 1 - bnclr icc1,1 - - set_spr_addr ok7,lr - set_icc 0x6 2 - bnclr icc2,2 - fail -ok7: - set_spr_addr bad,lr - set_icc 0x7 3 - bnclr icc3,3 - - set_spr_addr ok9,lr - set_icc 0x8 0 - bnclr icc0,0 - fail -ok9: - set_spr_addr bad,lr - set_icc 0x9 1 - bnclr icc1,1 - - set_spr_addr okb,lr - set_icc 0xa 2 - bnclr icc2,2 - fail -okb: - set_spr_addr bad,lr - set_icc 0xb 3 - bnclr icc3,3 - - set_spr_addr okd,lr - set_icc 0xc 0 - bnclr icc0,0 - fail -okd: - set_spr_addr bad,lr - set_icc 0xd 1 - bnclr icc1,1 - - set_spr_addr okf,lr - set_icc 0xe 2 - bnclr icc2,2 - fail -okf: - set_spr_addr bad,lr - set_icc 0xf 3 - bnclr icc3,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bne.cgs b/sim/testsuite/sim/frv/bne.cgs deleted file mode 100644 index f0f08945358..00000000000 --- a/sim/testsuite/sim/frv/bne.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for bne $ICCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global bne -bne: - set_icc 0x0 0 - bne icc0,0,ok1 - fail -ok1: - set_icc 0x1 1 - bne icc1,1,ok2 - fail -ok2: - set_icc 0x2 2 - bne icc2,2,ok3 - fail -ok3: - set_icc 0x3 3 - bne icc3,3,ok4 - fail -ok4: - set_icc 0x4 0 - bne icc0,0,bad - set_icc 0x5 1 - bne icc1,1,bad - set_icc 0x6 2 - bne icc2,2,bad - set_icc 0x7 3 - bne icc3,3,bad - set_icc 0x8 0 - bne icc0,0,ok9 - fail -ok9: - set_icc 0x9 1 - bne icc1,1,oka - fail -oka: - set_icc 0xa 2 - bne icc2,2,okb - fail -okb: - set_icc 0xb 3 - bne icc3,3,okc - fail -okc: - set_icc 0xc 0 - bne icc0,0,bad - set_icc 0xd 1 - bne icc1,1,bad - set_icc 0xe 2 - bne icc2,2,bad - set_icc 0xf 3 - bne icc3,3,bad - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bnelr.cgs b/sim/testsuite/sim/frv/bnelr.cgs deleted file mode 100644 index 7a477b844e6..00000000000 --- a/sim/testsuite/sim/frv/bnelr.cgs +++ /dev/null @@ -1,84 +0,0 @@ -# frv testcase for bnelr $ICCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bnelr -bnelr: - set_spr_addr ok1,lr - set_icc 0x0 0 - bnelr icc0,0 - fail -ok1: - set_spr_addr ok2,lr - set_icc 0x1 1 - bnelr icc1,1 - fail -ok2: - set_spr_addr ok3,lr - set_icc 0x2 2 - bnelr icc2,2 - fail -ok3: - set_spr_addr ok4,lr - set_icc 0x3 3 - bnelr icc3,3 - fail -ok4: - set_spr_addr bad,lr - set_icc 0x4 0 - bnelr icc0,0 - - set_spr_addr bad,lr - set_icc 0x5 1 - bnelr icc1,1 - - set_spr_addr bad,lr - set_icc 0x6 2 - bnelr icc2,2 - - set_spr_addr bad,lr - set_icc 0x7 3 - bnelr icc3,3 - - set_spr_addr ok9,lr - set_icc 0x8 0 - bnelr icc0,0 - fail -ok9: - set_spr_addr oka,lr - set_icc 0x9 1 - bnelr icc1,1 - fail -oka: - set_spr_addr okb,lr - set_icc 0xa 2 - bnelr icc2,2 - fail -okb: - set_spr_addr okc,lr - set_icc 0xb 3 - bnelr icc3,3 - fail -okc: - set_spr_addr bad,lr - set_icc 0xc 0 - bnelr icc0,0 - - set_spr_addr bad,lr - set_icc 0xd 1 - bnelr icc1,1 - - set_spr_addr bad,lr - set_icc 0xe 2 - bnelr icc2,2 - - set_spr_addr bad,lr - set_icc 0xf 3 - bnelr icc3,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bnlr.cgs b/sim/testsuite/sim/frv/bnlr.cgs deleted file mode 100644 index de32b051694..00000000000 --- a/sim/testsuite/sim/frv/bnlr.cgs +++ /dev/null @@ -1,84 +0,0 @@ -# frv testcase for bnlr $ICCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bnlr -bnlr: - set_spr_addr bad,lr - set_icc 0x0 0 - bnlr icc0,0 - - set_spr_addr bad,lr - set_icc 0x1 1 - bnlr icc1,1 - - set_spr_addr bad,lr - set_icc 0x2 2 - bnlr icc2,2 - - set_spr_addr bad,lr - set_icc 0x3 3 - bnlr icc3,3 - - set_spr_addr bad,lr - set_icc 0x4 0 - bnlr icc0,0 - - set_spr_addr bad,lr - set_icc 0x5 1 - bnlr icc1,1 - - set_spr_addr bad,lr - set_icc 0x6 2 - bnlr icc2,2 - - set_spr_addr bad,lr - set_icc 0x7 3 - bnlr icc3,3 - - set_spr_addr ok9,lr - set_icc 0x8 0 - bnlr icc0,0 - fail -ok9: - set_spr_addr oka,lr - set_icc 0x9 1 - bnlr icc1,1 - fail -oka: - set_spr_addr okb,lr - set_icc 0xa 2 - bnlr icc2,2 - fail -okb: - set_spr_addr okc,lr - set_icc 0xb 3 - bnlr icc3,3 - fail -okc: - set_spr_addr okd,lr - set_icc 0xc 0 - bnlr icc0,0 - fail -okd: - set_spr_addr oke,lr - set_icc 0xd 1 - bnlr icc1,1 - fail -oke: - set_spr_addr okf,lr - set_icc 0xe 2 - bnlr icc2,2 - fail -okf: - set_spr_addr okg,lr - set_icc 0xf 3 - bnlr icc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bno.cgs b/sim/testsuite/sim/frv/bno.cgs deleted file mode 100644 index 005e4224437..00000000000 --- a/sim/testsuite/sim/frv/bno.cgs +++ /dev/null @@ -1,45 +0,0 @@ -# frv testcase for bno $ICCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global bno -bno: - set_icc 0x0 0 - bno - set_icc 0x1 1 - bno - set_icc 0x2 2 - bno - set_icc 0x3 3 - bno - set_icc 0x4 0 - bno - set_icc 0x5 1 - bno - set_icc 0x6 2 - bno - set_icc 0x7 3 - bno - set_icc 0x8 0 - bno - set_icc 0x9 1 - bno - set_icc 0xa 2 - bno - set_icc 0xb 3 - bno - set_icc 0xc 0 - bno - set_icc 0xd 1 - bno - set_icc 0xe 2 - bno - set_icc 0xf 3 - bno - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bnolr.cgs b/sim/testsuite/sim/frv/bnolr.cgs deleted file mode 100644 index ae69f6fa495..00000000000 --- a/sim/testsuite/sim/frv/bnolr.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for bnolr -# mach: all - - .include "testutils.inc" - - start - - .global bnolr -bnolr: - set_spr_addr bad,lr - set_icc 0x0 0 - bnolr - - set_icc 0x1 1 - bnolr - - set_icc 0x2 2 - bnolr - - set_icc 0x3 3 - bnolr - - set_icc 0x4 0 - bnolr - - set_icc 0x5 1 - bnolr - - set_icc 0x6 2 - bnolr - - set_icc 0x7 3 - bnolr - - set_icc 0x8 0 - bnolr - - set_icc 0x9 1 - bnolr - - set_icc 0xa 2 - bnolr - - set_icc 0xb 3 - bnolr - - set_icc 0xc 0 - bnolr - - set_icc 0xd 1 - bnolr - - set_icc 0xe 2 - bnolr - - set_icc 0xf 3 - bnolr - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bnv.cgs b/sim/testsuite/sim/frv/bnv.cgs deleted file mode 100644 index 29ec57a1ded..00000000000 --- a/sim/testsuite/sim/frv/bnv.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for bnv $ICCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global bnv -bnv: - set_icc 0x0 0 - bnv icc0,0,ok1 - fail -ok1: - set_icc 0x1 1 - bnv icc1,1,ok2 - fail -ok2: - set_icc 0x2 2 - bnv icc2,2,bad - set_icc 0x3 3 - bnv icc3,3,bad - set_icc 0x4 0 - bnv icc0,0,ok5 - fail -ok5: - set_icc 0x5 1 - bnv icc1,1,ok6 - fail -ok6: - set_icc 0x6 2 - bnv icc2,2,bad - set_icc 0x7 3 - bnv icc3,3,bad - set_icc 0x8 0 - bnv icc0,0,ok9 - fail -ok9: - set_icc 0x9 1 - bnv icc1,1,oka - fail -oka: - set_icc 0xa 2 - bnv icc2,2,bad - set_icc 0xb 3 - bnv icc3,3,bad - set_icc 0xc 0 - bnv icc0,0,okd - fail -okd: - set_icc 0xd 1 - bnv icc1,1,oke - fail -oke: - set_icc 0xe 2 - bnv icc2,2,bad - set_icc 0xf 3 - bnv icc3,3,bad - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bnvlr.cgs b/sim/testsuite/sim/frv/bnvlr.cgs deleted file mode 100644 index de40f9cf5fb..00000000000 --- a/sim/testsuite/sim/frv/bnvlr.cgs +++ /dev/null @@ -1,84 +0,0 @@ -# frv testcase for bnvlr $ICCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bnvlr -bnvlr: - set_spr_addr ok1,lr - set_icc 0x0 0 - bnvlr icc0,0 - fail -ok1: - set_spr_addr ok2,lr - set_icc 0x1 1 - bnvlr icc1,1 - fail -ok2: - set_spr_addr bad,lr - set_icc 0x2 2 - bnvlr icc2,2 - - set_spr_addr bad,lr - set_icc 0x3 3 - bnvlr icc3,3 - - set_spr_addr ok5,lr - set_icc 0x4 0 - bnvlr icc0,0 - fail -ok5: - set_spr_addr ok6,lr - set_icc 0x5 1 - bnvlr icc1,1 - fail -ok6: - set_spr_addr bad,lr - set_icc 0x6 2 - bnvlr icc2,2 - - set_spr_addr bad,lr - set_icc 0x7 3 - bnvlr icc3,3 - - set_spr_addr ok9,lr - set_icc 0x8 0 - bnvlr icc0,0 - fail -ok9: - set_spr_addr oka,lr - set_icc 0x9 1 - bnvlr icc1,1 - fail -oka: - set_spr_addr bad,lr - set_icc 0xa 2 - bnvlr icc2,2 - - set_spr_addr bad,lr - set_icc 0xb 3 - bnvlr icc3,3 - - set_spr_addr okd,lr - set_icc 0xc 0 - bnvlr icc0,0 - fail -okd: - set_spr_addr oke,lr - set_icc 0xd 1 - bnvlr icc1,1 - fail -oke: - set_spr_addr bad,lr - set_icc 0xe 2 - bnvlr icc2,2 - - set_spr_addr bad,lr - set_icc 0xf 3 - bnvlr icc3,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bp.cgs b/sim/testsuite/sim/frv/bp.cgs deleted file mode 100644 index 0bc1e7fb8b9..00000000000 --- a/sim/testsuite/sim/frv/bp.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for bp $ICCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global bp -bp: - set_icc 0x0 0 - bp icc0,0,ok1 - fail -ok1: - set_icc 0x1 1 - bp icc1,1,ok2 - fail -ok2: - set_icc 0x2 2 - bp icc2,2,ok3 - fail -ok3: - set_icc 0x3 3 - bp icc3,3,ok4 - fail -ok4: - set_icc 0x4 0 - bp icc0,0,ok5 - fail -ok5: - set_icc 0x5 1 - bp icc1,1,ok6 - fail -ok6: - set_icc 0x6 2 - bp icc2,2,ok7 - fail -ok7: - set_icc 0x7 3 - bp icc3,3,ok8 - fail -ok8: - set_icc 0x8 0 - bp icc0,0,bad - set_icc 0x9 1 - bp icc1,1,bad - set_icc 0xa 2 - bp icc2,2,bad - set_icc 0xb 3 - bp icc3,3,bad - set_icc 0xc 0 - bp icc0,0,bad - set_icc 0xd 1 - bp icc1,1,bad - set_icc 0xe 2 - bp icc2,2,bad - set_icc 0xf 3 - bp icc3,3,bad - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bplr.cgs b/sim/testsuite/sim/frv/bplr.cgs deleted file mode 100644 index 2bd9bb6ec67..00000000000 --- a/sim/testsuite/sim/frv/bplr.cgs +++ /dev/null @@ -1,84 +0,0 @@ -# frv testcase for bplr $ICCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bplr -bplr: - set_spr_addr ok1,lr - set_icc 0x0 0 - bplr icc0,0 - fail -ok1: - set_spr_addr ok2,lr - set_icc 0x1 1 - bplr icc1,1 - fail -ok2: - set_spr_addr ok3,lr - set_icc 0x2 2 - bplr icc2,2 - fail -ok3: - set_spr_addr ok4,lr - set_icc 0x3 3 - bplr icc3,3 - fail -ok4: - set_spr_addr ok5,lr - set_icc 0x4 0 - bplr icc0,0 - fail -ok5: - set_spr_addr ok6,lr - set_icc 0x5 1 - bplr icc1,1 - fail -ok6: - set_spr_addr ok7,lr - set_icc 0x6 2 - bplr icc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_icc 0x7 3 - bplr icc3,3 - fail -ok8: - set_spr_addr bad,lr - set_icc 0x8 0 - bplr icc0,0 - - set_spr_addr bad,lr - set_icc 0x9 1 - bplr icc1,1 - - set_spr_addr bad,lr - set_icc 0xa 2 - bplr icc2,2 - - set_spr_addr bad,lr - set_icc 0xb 3 - bplr icc3,3 - - set_spr_addr bad,lr - set_icc 0xc 0 - bplr icc0,0 - - set_spr_addr bad,lr - set_icc 0xd 1 - bplr icc1,1 - - set_spr_addr bad,lr - set_icc 0xe 2 - bplr icc2,2 - - set_spr_addr bad,lr - set_icc 0xf 3 - bplr icc3,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bra.cgs b/sim/testsuite/sim/frv/bra.cgs deleted file mode 100644 index e6b312b1372..00000000000 --- a/sim/testsuite/sim/frv/bra.cgs +++ /dev/null @@ -1,75 +0,0 @@ -# frv testcase for bra $ICCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global bra -bra: - set_icc 0x0 0 - bra ok1 - fail -ok1: - set_icc 0x1 1 - bra ok2 - fail -ok2: - set_icc 0x2 2 - bra ok3 - fail -ok3: - set_icc 0x3 3 - bra ok4 - fail -ok4: - set_icc 0x4 0 - bra ok5 - fail -ok5: - set_icc 0x5 1 - bra ok6 - fail -ok6: - set_icc 0x6 2 - bra ok7 - fail -ok7: - set_icc 0x7 3 - bra ok8 - fail -ok8: - set_icc 0x8 0 - bra ok9 - fail -ok9: - set_icc 0x9 1 - bra oka - fail -oka: - set_icc 0xa 2 - bra okb - fail -okb: - set_icc 0xb 3 - bra okc - fail -okc: - set_icc 0xc 0 - bra okd - fail -okd: - set_icc 0xd 1 - bra oke - fail -oke: - set_icc 0xe 2 - bra okf - fail -okf: - set_icc 0xf 3 - bra okg - fail -okg: - - pass diff --git a/sim/testsuite/sim/frv/bralr.cgs b/sim/testsuite/sim/frv/bralr.cgs deleted file mode 100644 index 39282099947..00000000000 --- a/sim/testsuite/sim/frv/bralr.cgs +++ /dev/null @@ -1,91 +0,0 @@ -# frv testcase for bralr -# mach: all - - .include "testutils.inc" - - start - - .global bralr -bralr: - set_spr_addr ok1,lr - set_icc 0x0 0 - bralr - fail -ok1: - set_spr_addr ok2,lr - set_icc 0x1 1 - bralr - fail -ok2: - set_spr_addr ok3,lr - set_icc 0x2 2 - bralr - fail -ok3: - set_spr_addr ok4,lr - set_icc 0x3 3 - bralr - fail -ok4: - set_spr_addr ok5,lr - set_icc 0x4 0 - bralr - fail -ok5: - set_spr_addr ok6,lr - set_icc 0x5 1 - bralr - fail -ok6: - set_spr_addr ok7,lr - set_icc 0x6 2 - bralr - fail -ok7: - set_spr_addr ok8,lr - set_icc 0x7 3 - bralr - fail -ok8: - set_spr_addr ok9,lr - set_icc 0x8 0 - bralr - fail -ok9: - set_spr_addr oka,lr - set_icc 0x9 1 - bralr - fail -oka: - set_spr_addr okb,lr - set_icc 0xa 2 - bralr - fail -okb: - set_spr_addr okc,lr - set_icc 0xb 3 - bralr - fail -okc: - set_spr_addr okd,lr - set_icc 0xc 0 - bralr - fail -okd: - set_spr_addr oke,lr - set_icc 0xd 1 - bralr - fail -oke: - set_spr_addr okf,lr - set_icc 0xe 2 - bralr - fail -okf: - set_spr_addr okg,lr - set_icc 0xf 3 - bralr - fail -okg: - - pass diff --git a/sim/testsuite/sim/frv/branch.pcgs b/sim/testsuite/sim/frv/branch.pcgs deleted file mode 100644 index 013b0badad2..00000000000 --- a/sim/testsuite/sim/frv/branch.pcgs +++ /dev/null @@ -1,63 +0,0 @@ -# frv parallel testcase for branching -# mach: fr500 fr550 frv - - .include "testutils.inc" - - start - - .global branch -branch: ; All insns in VLIW execute - setlos.p 1,gr1 - setlos 0,gr2 - setlos.p 0,gr3 - bra ok1 - setlos.p 2,gr2 - setlos 3,gr3 - fail -ok1: - test_gr_immed 1,gr1 - test_gr_immed 0,gr2 - test_gr_immed 0,gr3 - - ; 1st branch is taken - bra.p ok5 - bra ok4 - bra.p ok3 - bra ok2 - fail -ok2: - fail -ok3: - fail -ok4: - fail -ok5: - ; 1st true branch is taken - set_icc 0x4 1 - bne.p icc1,1,ok6 - blt icc1,1,ok7 - beq.p icc1,1,ok9 - ble icc1,1,ok8 - fail -ok6: - fail -ok7: - fail -ok8: - fail -ok9: - ; combination of the above - set_icc 0x4 1 - setlos.p 4,gr4 - setlos.p 0,gr5 - bne.p icc1,1,oka - beq icc1,1,okb - setlos 5,gr5 - fail -oka: - fail -okb: - test_gr_immed 4,gr4 - test_gr_immed 0,gr5 - - pass diff --git a/sim/testsuite/sim/frv/break.cgs b/sim/testsuite/sim/frv/break.cgs deleted file mode 100644 index b2a61a05be0..00000000000 --- a/sim/testsuite/sim/frv/break.cgs +++ /dev/null @@ -1,58 +0,0 @@ -# FRV testcase for break -# mach: all - - .include "testutils.inc" - - start - - .global tra -tra: - ; Can't test break anymore in the user environment because it is the - ; debugger's breakpoint insn. Just pass this test for now. - pass - - - - - - set_gr_spr tbr,gr7 - and_gr_immed -4081,gr7 ; clear tbr.tt - inc_gr_immed 0xff0,gr7 ; break handler - set_bctrlr_0_0 gr7 - set_spr_immed 128,lcr - - test_spr_bits 0x4,2,0x1,psr ; psr.s is set - test_spr_bits 0x1,0,0x0,psr ; psr.et is clear - set_spr_addr ok1,lr - break -ret: - or_spr_immed 0x00000001,psr ; turn on psr.et - and_spr_immed 0xfffffffb,psr ; turn off psr.s - test_spr_bits 0x4,2,0x0,psr ; psr.s is clear - test_spr_bits 0x1,0,0x1,psr ; psr.et is set - set_spr_addr ok0,lr - break -ret1: - test_spr_bits 0x4,2,0x0,psr ; psr.s is clear - test_spr_bits 0x1,0,0x1,psr ; psr.et is set - pass - - ; check interrupt for second break -ok0: test_spr_addr ret1,bpcsr - test_spr_bits 0x1000,12,0x0,bpsr ; bpsr.bs is clear - test_spr_bits 0x0001,0,0x1,bpsr ; bpsr.et is set - test_spr_bits 0x4,2,0x1,psr ; psr.s is set - test_spr_bits 0x1,0,0x0,psr ; psr.et is clear - rett 0 ; nop - rett 1 - - ; check interrupt for first break -ok1: test_spr_addr ret,bpcsr - test_spr_bits 0x1000,12,0x1,bpsr ; bpsr.bs is set - test_spr_bits 0x0001,0,0x0,bpsr ; bpsr.et is clear - test_spr_bits 0x4,2,0x1,psr ; psr.s is set - test_spr_bits 0x1,0,0x0,psr ; psr.et is clear - rett 0 ; nop - rett 1 - - diff --git a/sim/testsuite/sim/frv/bv.cgs b/sim/testsuite/sim/frv/bv.cgs deleted file mode 100644 index e2f8174063f..00000000000 --- a/sim/testsuite/sim/frv/bv.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for bv $ICCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global bv -bv: - set_icc 0x0 0 - bv icc0,0,bad - set_icc 0x1 1 - bv icc1,1,bad - set_icc 0x2 2 - bv icc2,2,ok3 - fail -ok3: - set_icc 0x3 3 - bv icc3,3,ok4 - fail -ok4: - set_icc 0x4 0 - bv icc0,0,bad - set_icc 0x5 1 - bv icc1,1,bad - set_icc 0x6 2 - bv icc2,2,ok7 - fail -ok7: - set_icc 0x7 3 - bv icc3,3,ok8 - fail -ok8: - set_icc 0x8 0 - bv icc0,0,bad - set_icc 0x9 1 - bv icc1,1,bad - set_icc 0xa 2 - bv icc2,2,okb - fail -okb: - set_icc 0xb 3 - bv icc3,3,okc - fail -okc: - set_icc 0xc 0 - bv icc0,0,bad - set_icc 0xd 1 - bv icc1,1,bad - set_icc 0xe 2 - bv icc2,2,okf - fail -okf: - set_icc 0xf 3 - bv icc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/bvlr.cgs b/sim/testsuite/sim/frv/bvlr.cgs deleted file mode 100644 index b7ba9d88ac5..00000000000 --- a/sim/testsuite/sim/frv/bvlr.cgs +++ /dev/null @@ -1,84 +0,0 @@ -# frv testcase for bvlr $ICCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global bvlr -bvlr: - set_spr_addr bad,lr - set_icc 0x0 0 - bvlr icc0,0 - - set_spr_addr bad,lr - set_icc 0x1 1 - bvlr icc1,1 - - set_spr_addr ok3,lr - set_icc 0x2 2 - bvlr icc2,2 - fail -ok3: - set_spr_addr ok4,lr - set_icc 0x3 3 - bvlr icc3,3 - fail -ok4: - set_spr_addr bad,lr - set_icc 0x4 0 - bvlr icc0,0 - - set_spr_addr bad,lr - set_icc 0x5 1 - bvlr icc1,1 - - set_spr_addr ok7,lr - set_icc 0x6 2 - bvlr icc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_icc 0x7 3 - bvlr icc3,3 - fail -ok8: - set_spr_addr bad,lr - set_icc 0x8 0 - bvlr icc0,0 - - set_spr_addr bad,lr - set_icc 0x9 1 - bvlr icc1,1 - - set_spr_addr okb,lr - set_icc 0xa 2 - bvlr icc2,2 - fail -okb: - set_spr_addr okc,lr - set_icc 0xb 3 - bvlr icc3,3 - fail -okc: - set_spr_addr bad,lr - set_icc 0xc 0 - bvlr icc0,0 - - set_spr_addr bad,lr - set_icc 0xd 1 - bvlr icc1,1 - - set_spr_addr okf,lr - set_icc 0xe 2 - bvlr icc2,2 - fail -okf: - set_spr_addr okg,lr - set_icc 0xf 3 - bvlr icc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/cadd.cgs b/sim/testsuite/sim/frv/cadd.cgs deleted file mode 100644 index 291b8fb6675..00000000000 --- a/sim/testsuite/sim/frv/cadd.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for cadd $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cadd -cadd: - set_spr_immed 0x1b1b,cccr - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - cadd gr7,gr8,gr8,cc4,1 - test_gr_immed 3,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - cadd gr7,gr8,gr8,cc4,1 - test_gr_limmed 0x8000,0x0000,gr8 - - cadd gr8,gr8,gr8,cc4,1 - test_gr_immed 0,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - cadd gr7,gr8,gr8,cc4,0 - test_gr_immed 2,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - cadd gr7,gr8,gr8,cc4,0 - test_gr_immed 1,gr8 - - cadd gr8,gr8,gr8,cc4,0 - test_gr_immed 1,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - cadd gr7,gr8,gr8,cc5,0 - test_gr_immed 3,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - cadd gr7,gr8,gr8,cc5,0 - test_gr_limmed 0x8000,0x0000,gr8 - - cadd gr8,gr8,gr8,cc5,0 - test_gr_immed 0,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - cadd gr7,gr8,gr8,cc5,1 - test_gr_immed 2,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - cadd gr7,gr8,gr8,cc5,1 - test_gr_immed 1,gr8 - - cadd gr8,gr8,gr8,cc5,1 - test_gr_immed 1,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - cadd gr7,gr8,gr8,cc6,1 - test_gr_immed 2,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - cadd gr7,gr8,gr8,cc6,0 - test_gr_immed 1,gr8 - - cadd gr8,gr8,gr8,cc6,1 - test_gr_immed 1,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - cadd gr7,gr8,gr8,cc7,0 - test_gr_immed 2,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - cadd gr7,gr8,gr8,cc7,1 - test_gr_immed 1,gr8 - - cadd gr8,gr8,gr8,cc7,0 - test_gr_immed 1,gr8 - - pass diff --git a/sim/testsuite/sim/frv/caddcc.cgs b/sim/testsuite/sim/frv/caddcc.cgs deleted file mode 100644 index ddfd41e359b..00000000000 --- a/sim/testsuite/sim/frv/caddcc.cgs +++ /dev/null @@ -1,163 +0,0 @@ -# frv testcase for caddcc $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global caddcc -caddcc: - set_spr_immed 0x1b1b,cccr - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc0,1 - test_icc 0 0 0 0 icc0 - test_gr_immed 3,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc0,1 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_icc 0x08,0 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc4,1 - test_icc 0 1 1 1 icc0 - test_gr_immed 0,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc4,1; test zero, carry and overflow bits - test_icc 0 1 1 1 icc0 - test_gr_immed 0,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc0,0 - test_icc 1 1 1 1 icc0 - test_gr_immed 2,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc0,0 - test_icc 0 1 0 1 icc0 - test_gr_immed 1,gr8 - - set_icc 0x08,0 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc4,0 - test_icc 1 0 0 0 icc0 - test_gr_immed 1,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc4,0; test zero, carry and overflow bits - test_icc 1 0 0 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc1,0 - test_icc 0 0 0 0 icc1 - test_gr_immed 3,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc1,0 - test_icc 1 0 1 0 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_icc 0x08,1 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc5,0 - test_icc 0 1 1 1 icc1 - test_gr_immed 0,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x08,1 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc5,0; test zero, carry and overflow bits - test_icc 0 1 1 1 icc1 - test_gr_immed 0,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc1,1 - test_icc 1 1 1 1 icc1 - test_gr_immed 2,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc1,1 - test_icc 0 1 0 1 icc1 - test_gr_immed 1,gr8 - - set_icc 0x08,1 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc5,1 - test_icc 1 0 0 0 icc1 - test_gr_immed 1,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x08,1 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc5,1; test zero, carry and overflow bits - test_icc 1 0 0 0 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,2 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc2,0 - test_icc 1 1 1 1 icc2 - test_gr_immed 2,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - set_icc 0x05,2 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc2,0 - test_icc 0 1 0 1 icc2 - test_gr_immed 1,gr8 - - set_icc 0x08,2 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc6,1 - test_icc 1 0 0 0 icc2 - test_gr_immed 1,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x08,2 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc6,1; test zero, carry and overflow bits - test_icc 1 0 0 0 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,3 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc3,0 - test_icc 1 1 1 1 icc3 - test_gr_immed 2,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - set_icc 0x05,3 ; Set mask opposite of expected - caddcc gr7,gr8,gr8,cc3,0 - test_icc 0 1 0 1 icc3 - test_gr_immed 1,gr8 - - set_icc 0x08,3 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc7,1 - test_icc 1 0 0 0 icc3 - test_gr_immed 1,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x08,3 ; Set mask opposite of expected - caddcc gr8,gr8,gr8,cc7,1; test zero, carry and overflow bits - test_icc 1 0 0 0 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - - - pass diff --git a/sim/testsuite/sim/frv/call.cgs b/sim/testsuite/sim/frv/call.cgs deleted file mode 100644 index 5f0d7677bcc..00000000000 --- a/sim/testsuite/sim/frv/call.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# frv testcase for call $label24 -# mach: all - - .include "testutils.inc" - - start - - .global call -call: - set_spr_immed 0,lr - call ok1 -bad1: - fail -ok1: - test_spr_addr bad1,lr - - pass diff --git a/sim/testsuite/sim/frv/call.pcgs b/sim/testsuite/sim/frv/call.pcgs deleted file mode 100644 index 7f452c664f6..00000000000 --- a/sim/testsuite/sim/frv/call.pcgs +++ /dev/null @@ -1,30 +0,0 @@ -# frv parallel testcase for call $label24 -# mach: fr500 fr550 frv - - .include "testutils.inc" - - start - - .global call -call: - set_spr_immed 0,lr - call ok1 -bad1: - fail -ok1: - test_spr_addr bad1,lr - - set_spr_immed 0,lr - setlos.p 0,gr5 - call.p ok2 - bra bad3 -bad2: - setlos 5,gr5 - fail -bad3: - fail -ok2: - test_spr_addr bad2,lr - test_gr_immed 0,gr5 - - pass diff --git a/sim/testsuite/sim/frv/callil.cgs b/sim/testsuite/sim/frv/callil.cgs deleted file mode 100644 index eac63e86a49..00000000000 --- a/sim/testsuite/sim/frv/callil.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for callil @($GRi,$d12),$LI -# mach: all - - .include "testutils.inc" - - start - - .global callil -callil: - set_gr_addr ok2,gr8 - inc_gr_immed -2047,gr8 - callil @(gr8,0x7ff) -bad2: - fail -ok2: - test_spr_addr bad2,lr - - set_gr_addr ok3,gr8 - inc_gr_immed 2048,gr8 - callil @(gr8,-2048) -bad3: - fail -ok3: - test_spr_addr bad3,lr - - pass diff --git a/sim/testsuite/sim/frv/calll.cgs b/sim/testsuite/sim/frv/calll.cgs deleted file mode 100644 index eee73bc2a97..00000000000 --- a/sim/testsuite/sim/frv/calll.cgs +++ /dev/null @@ -1,28 +0,0 @@ -# frv testcase for calll @($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global calll -calll: - set_gr_addr ok2,gr8 - inc_gr_immed -4,gr8 - inc_gr_immed 4,gr9 - calll @(gr8,gr9) -bad2: - fail -ok2: - test_spr_addr bad2,lr - - set_gr_addr ok3,gr8 - inc_gr_immed 4,gr8 - set_gr_immed -4,gr9 - calll @(gr8,gr9) -bad3: - fail -ok3: - test_spr_addr bad3,lr - - pass diff --git a/sim/testsuite/sim/frv/cand.cgs b/sim/testsuite/sim/frv/cand.cgs deleted file mode 100644 index 6113593c24f..00000000000 --- a/sim/testsuite/sim/frv/cand.cgs +++ /dev/null @@ -1,126 +0,0 @@ -# frv testcase for cand $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global cand -cand: - set_spr_immed 0x1b1b,cccr - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc0,1 - test_icc 1 0 1 1 icc0 - test_gr_immed 0,gr8 - - set_gr_limmed 0xffff,0x0000,gr8 - set_icc 0x04,0 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc0,1 - test_icc 0 1 0 0 icc0 - test_gr_limmed 0xaaaa,0x0000,gr8 - - set_gr_limmed 0x0000,0xffff,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc4,1 - test_icc 1 1 0 1 icc0 - test_gr_limmed 0x0000,0xaaaa,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc0,0 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0xffff,0x0000,gr8 - set_icc 0x04,0 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc0,0 - test_icc 0 1 0 0 icc0 - test_gr_limmed 0xffff,0x0000,gr8 - - set_gr_limmed 0x0000,0xffff,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc4,0 - test_icc 1 1 0 1 icc0 - test_gr_limmed 0x0000,0xffff,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x0b,1 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc1,0 - test_icc 1 0 1 1 icc1 - test_gr_immed 0,gr8 - - set_gr_limmed 0xffff,0x0000,gr8 - set_icc 0x04,1 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc1,0 - test_icc 0 1 0 0 icc1 - test_gr_limmed 0xaaaa,0x0000,gr8 - - set_gr_limmed 0x0000,0xffff,gr8 - set_icc 0x0d,1 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc5,0 - test_icc 1 1 0 1 icc1 - test_gr_limmed 0x0000,0xaaaa,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x0b,1 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc1,1 - test_icc 1 0 1 1 icc1 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0xffff,0x0000,gr8 - set_icc 0x04,1 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc1,1 - test_icc 0 1 0 0 icc1 - test_gr_limmed 0xffff,0x0000,gr8 - - set_gr_limmed 0x0000,0xffff,gr8 - set_icc 0x0d,1 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc5,1 - test_icc 1 1 0 1 icc1 - test_gr_limmed 0x0000,0xffff,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x0b,2 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc2,0 - test_icc 1 0 1 1 icc2 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0xffff,0x0000,gr8 - set_icc 0x04,2 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc2,0 - test_icc 0 1 0 0 icc2 - test_gr_limmed 0xffff,0x0000,gr8 - - set_gr_limmed 0x0000,0xffff,gr8 - set_icc 0x0d,2 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc6,1 - test_icc 1 1 0 1 icc2 - test_gr_limmed 0x0000,0xffff,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x0b,3 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc3,0 - test_icc 1 0 1 1 icc3 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0xffff,0x0000,gr8 - set_icc 0x04,3 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc3,0 - test_icc 0 1 0 0 icc3 - test_gr_limmed 0xffff,0x0000,gr8 - - set_gr_limmed 0x0000,0xffff,gr8 - set_icc 0x0d,3 ; Set mask opposite of expected - cand gr7,gr8,gr8,cc7,1 - test_icc 1 1 0 1 icc3 - test_gr_limmed 0x0000,0xffff,gr8 - - pass diff --git a/sim/testsuite/sim/frv/candcc.cgs b/sim/testsuite/sim/frv/candcc.cgs deleted file mode 100644 index c16df73ec29..00000000000 --- a/sim/testsuite/sim/frv/candcc.cgs +++ /dev/null @@ -1,126 +0,0 @@ -# frv testcase for candcc $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global candcc -candcc: - set_spr_immed 0x1b1b,cccr - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc0,1 - test_icc 0 1 1 1 icc0 - test_gr_immed 0,gr8 - - set_gr_limmed 0xffff,0x0000,gr8 - set_icc 0x04,0 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc0,1 - test_icc 1 0 0 0 icc0 - test_gr_limmed 0xaaaa,0x0000,gr8 - - set_gr_limmed 0x0000,0xffff,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc4,1 - test_icc 0 0 0 1 icc0 - test_gr_limmed 0x0000,0xaaaa,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc0,0 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0xffff,0x0000,gr8 - set_icc 0x04,0 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc0,0 - test_icc 0 1 0 0 icc0 - test_gr_limmed 0xffff,0x0000,gr8 - - set_gr_limmed 0x0000,0xffff,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc4,0 - test_icc 1 1 0 1 icc0 - test_gr_limmed 0x0000,0xffff,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x0b,1 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc1,0 - test_icc 0 1 1 1 icc1 - test_gr_immed 0,gr8 - - set_gr_limmed 0xffff,0x0000,gr8 - set_icc 0x04,1 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc1,0 - test_icc 1 0 0 0 icc1 - test_gr_limmed 0xaaaa,0x0000,gr8 - - set_gr_limmed 0x0000,0xffff,gr8 - set_icc 0x0d,1 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc5,0 - test_icc 0 0 0 1 icc1 - test_gr_limmed 0x0000,0xaaaa,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x0b,1 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc1,1 - test_icc 1 0 1 1 icc1 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0xffff,0x0000,gr8 - set_icc 0x04,1 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc1,1 - test_icc 0 1 0 0 icc1 - test_gr_limmed 0xffff,0x0000,gr8 - - set_gr_limmed 0x0000,0xffff,gr8 - set_icc 0x0d,1 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc5,1 - test_icc 1 1 0 1 icc1 - test_gr_limmed 0x0000,0xffff,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x0b,2 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc2,0 - test_icc 1 0 1 1 icc2 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0xffff,0x0000,gr8 - set_icc 0x04,2 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc2,0 - test_icc 0 1 0 0 icc2 - test_gr_limmed 0xffff,0x0000,gr8 - - set_gr_limmed 0x0000,0xffff,gr8 - set_icc 0x0d,2 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc6,1 - test_icc 1 1 0 1 icc2 - test_gr_limmed 0x0000,0xffff,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x0b,3 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc3,0 - test_icc 1 0 1 1 icc3 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0xffff,0x0000,gr8 - set_icc 0x04,3 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc3,0 - test_icc 0 1 0 0 icc3 - test_gr_limmed 0xffff,0x0000,gr8 - - set_gr_limmed 0x0000,0xffff,gr8 - set_icc 0x0d,3 ; Set mask opposite of expected - candcc gr7,gr8,gr8,cc7,1 - test_icc 1 1 0 1 icc3 - test_gr_limmed 0x0000,0xffff,gr8 - - pass diff --git a/sim/testsuite/sim/frv/ccalll.cgs b/sim/testsuite/sim/frv/ccalll.cgs deleted file mode 100644 index dcfd300079c..00000000000 --- a/sim/testsuite/sim/frv/ccalll.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for ccalll @($GRi,$GRj),$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global ccalll -ccalll: - set_spr_immed 0x1b1b,cccr - - set_gr_addr ok2,gr8 - inc_gr_immed -4,gr8 - inc_gr_immed 4,gr9 - ccalll @(gr8,gr9),cc0,1 -bad2: - fail -ok2: - test_spr_addr bad2,lr - - set_gr_addr ok3,gr8 - inc_gr_immed 4,gr8 - set_gr_immed -4,gr9 - ccalll @(gr8,gr9),cc4,1 -bad3: - fail -ok3: - test_spr_addr bad3,lr - - set_spr_immed 0,lr - set_gr_addr bad,gr8 - inc_gr_immed -4,gr8 - set_gr_immed 4,gr9 - ccalll @(gr8,gr9),cc0,0 - test_spr_addr 0,lr - - set_gr_addr bad,gr8 - inc_gr_immed 4,gr8 - set_gr_immed -4,gr9 - ccalll @(gr8,gr9),cc4,0 - test_spr_addr 0,lr - - set_gr_addr ok5,gr8 - inc_gr_immed -4,gr8 - set_gr_immed 4,gr9 - ccalll @(gr8,gr9),cc1,0 -bad5: - fail -ok5: - test_spr_addr bad5,lr - - set_gr_addr ok6,gr8 - inc_gr_immed 4,gr8 - set_gr_immed -4,gr9 - ccalll @(gr8,gr9),cc5,0 -bad6: - fail -ok6: - test_spr_addr bad6,lr - - set_spr_immed 0,lr - set_gr_addr bad,gr8 - inc_gr_immed -4,gr8 - set_gr_immed 4,gr9 - ccalll @(gr8,gr9),cc1,1 - test_spr_addr 0,lr - - set_gr_addr bad,gr8 - inc_gr_immed 4,gr8 - set_gr_immed -4,gr9 - ccalll @(gr8,gr9),cc5,1 - test_spr_addr 0,lr - - set_gr_addr bad,gr8 - inc_gr_immed -4,gr8 - set_gr_immed 4,gr9 - ccalll @(gr8,gr9),cc2,1 - test_spr_addr 0,lr - - set_gr_addr bad,gr8 - inc_gr_immed 4,gr8 - set_gr_immed -4,gr9 - ccalll @(gr8,gr9),cc6,0 - test_spr_addr 0,lr - - set_gr_addr bad,gr8 - inc_gr_immed -4,gr8 - set_gr_immed 4,gr9 - ccalll @(gr8,gr9),cc3,0 - test_spr_addr 0,lr - - set_gr_addr bad,gr8 - inc_gr_immed 4,gr8 - set_gr_immed -4,gr9 - ccalll @(gr8,gr9),cc7,1 - test_spr_addr 0,lr - - pass -bad: - fail - diff --git a/sim/testsuite/sim/frv/cckc.cgs b/sim/testsuite/sim/frv/cckc.cgs deleted file mode 100644 index 70eabee5ce9..00000000000 --- a/sim/testsuite/sim/frv/cckc.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cckc $ICCi,$CCj_int,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cckc -cckc: - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckc icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckc icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckc icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckc icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckc icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckc icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckc icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckc icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckc icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckc icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckc icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckc icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckc icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckc icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckc icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckc icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckc icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckc icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckc icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckc icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckc icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckc icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckc icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckc icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckc icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckc icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckc icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckc icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckc icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckc icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckc icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckc icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckc icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckc icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckc icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckc icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckc icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckc icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckc icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckc icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckc icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckc icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckc icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckc icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckc icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckc icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckc icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckc icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckc icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckc icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckc icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckc icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckc icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckc icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckc icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckc icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckc icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckc icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckc icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckc icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckc icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckc icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckc icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckc icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckc icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckc icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckc icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckc icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckc icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckc icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckc icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckc icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckc icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckc icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckc icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckc icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckc icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckc icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckc icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckc icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckc icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckc icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckc icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckc icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckc icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckc icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckc icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckc icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckc icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckc icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckc icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckc icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckc icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckc icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckc icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckc icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cckeq.cgs b/sim/testsuite/sim/frv/cckeq.cgs deleted file mode 100644 index 2c86f1858d5..00000000000 --- a/sim/testsuite/sim/frv/cckeq.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cckeq $ICCi,$CCj_int,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cckeq -cckeq: - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckeq icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckeq icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckeq icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckeq icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckeq icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckeq icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckeq icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckeq icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckeq icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckeq icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckeq icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckeq icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckeq icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckeq icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckeq icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckeq icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckeq icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckeq icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckeq icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckeq icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckeq icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckeq icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckeq icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckeq icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckeq icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckeq icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckeq icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckeq icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckeq icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckeq icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckeq icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckeq icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckeq icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckeq icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckeq icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckeq icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckeq icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckeq icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckeq icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckeq icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckeq icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckeq icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckeq icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckeq icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckeq icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckeq icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckeq icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckeq icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckeq icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckeq icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckeq icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckeq icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckeq icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckeq icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckeq icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckeq icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckeq icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckeq icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckeq icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckeq icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckeq icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckeq icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckeq icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckeq icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckeq icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckeq icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckeq icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckeq icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckeq icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckeq icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckeq icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckeq icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckeq icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckeq icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckeq icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckeq icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckeq icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckeq icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckeq icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckeq icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckeq icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckeq icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckeq icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckeq icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckeq icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckeq icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckeq icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckeq icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckeq icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckeq icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckeq icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckeq icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckeq icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckeq icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckeq icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckeq icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cckge.cgs b/sim/testsuite/sim/frv/cckge.cgs deleted file mode 100644 index 6938f1e8e67..00000000000 --- a/sim/testsuite/sim/frv/cckge.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cckge $ICCi,$CCj_int,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cckge -cckge: - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckge icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckge icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckge icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckge icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckge icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckge icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckge icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckge icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckge icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckge icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckge icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckge icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckge icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckge icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckge icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckge icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckge icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckge icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckge icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckge icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckge icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckge icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckge icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckge icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckge icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckge icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckge icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckge icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckge icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckge icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckge icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckge icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckge icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckge icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckge icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckge icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckge icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckge icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckge icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckge icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckge icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckge icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckge icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckge icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckge icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckge icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckge icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckge icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckge icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckge icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckge icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckge icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckge icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckge icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckge icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckge icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckge icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckge icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckge icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckge icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckge icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckge icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckge icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckge icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckge icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckge icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckge icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckge icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckge icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckge icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckge icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckge icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckge icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckge icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckge icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckge icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckge icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckge icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckge icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckge icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckge icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckge icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckge icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckge icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckge icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckge icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckge icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckge icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckge icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckge icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckge icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckge icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckge icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckge icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckge icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckge icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cckgt.cgs b/sim/testsuite/sim/frv/cckgt.cgs deleted file mode 100644 index e0745dd4433..00000000000 --- a/sim/testsuite/sim/frv/cckgt.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cckgt $ICCi,$CCj_int,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cckgt -cckgt: - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckgt icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckgt icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckgt icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckgt icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckgt icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckgt icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckgt icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckgt icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckgt icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckgt icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckgt icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckgt icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckgt icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckgt icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckgt icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckgt icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckgt icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckgt icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckgt icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckgt icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckgt icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckgt icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckgt icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckgt icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckgt icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckgt icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckgt icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckgt icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckgt icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckgt icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckgt icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckgt icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckgt icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckgt icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckgt icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckgt icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckgt icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckgt icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckgt icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckgt icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckgt icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckgt icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckgt icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckgt icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckgt icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckgt icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckgt icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckgt icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckgt icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckgt icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckgt icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckgt icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckgt icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckgt icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckgt icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckgt icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckgt icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckgt icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckgt icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckgt icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckgt icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckgt icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckgt icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckgt icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckgt icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckgt icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckgt icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckgt icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckgt icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckgt icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckgt icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckgt icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckgt icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckgt icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckgt icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckgt icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckgt icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckgt icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckgt icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckgt icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckgt icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckgt icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckgt icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckgt icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckgt icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckgt icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckgt icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckgt icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckgt icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckgt icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckgt icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckgt icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckgt icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckgt icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckgt icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckgt icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cckhi.cgs b/sim/testsuite/sim/frv/cckhi.cgs deleted file mode 100644 index 4741f5ac3a4..00000000000 --- a/sim/testsuite/sim/frv/cckhi.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cckhi $ICCi,$CCj_int,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cckhi -cckhi: - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckhi icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckhi icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckhi icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckhi icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckhi icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckhi icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckhi icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckhi icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckhi icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckhi icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckhi icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckhi icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckhi icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckhi icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckhi icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckhi icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckhi icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckhi icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckhi icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckhi icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckhi icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckhi icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckhi icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckhi icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckhi icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckhi icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckhi icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckhi icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckhi icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckhi icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckhi icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckhi icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckhi icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckhi icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckhi icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckhi icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckhi icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckhi icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckhi icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckhi icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckhi icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckhi icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckhi icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckhi icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckhi icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckhi icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckhi icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckhi icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckhi icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckhi icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckhi icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckhi icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckhi icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckhi icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckhi icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckhi icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckhi icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckhi icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckhi icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckhi icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckhi icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckhi icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckhi icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckhi icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckhi icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckhi icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckhi icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckhi icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckhi icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckhi icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckhi icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckhi icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckhi icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckhi icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckhi icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckhi icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckhi icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckhi icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckhi icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckhi icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckhi icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckhi icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckhi icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckhi icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckhi icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckhi icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckhi icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckhi icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckhi icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckhi icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckhi icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckhi icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckhi icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckhi icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckhi icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckhi icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cckle.cgs b/sim/testsuite/sim/frv/cckle.cgs deleted file mode 100644 index 9d8821414f7..00000000000 --- a/sim/testsuite/sim/frv/cckle.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cckle $ICCi,$CCj_int,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cckle -cckle: - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckle icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckle icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckle icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckle icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckle icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckle icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckle icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckle icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckle icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckle icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckle icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckle icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckle icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckle icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckle icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckle icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckle icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckle icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckle icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckle icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckle icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckle icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckle icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckle icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckle icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckle icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckle icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckle icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckle icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckle icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckle icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckle icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckle icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckle icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckle icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckle icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckle icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckle icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckle icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckle icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckle icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckle icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckle icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckle icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckle icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckle icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckle icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckle icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckle icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckle icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckle icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckle icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckle icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckle icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckle icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckle icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckle icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckle icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckle icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckle icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckle icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckle icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckle icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckle icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckle icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckle icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckle icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckle icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckle icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckle icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckle icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckle icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckle icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckle icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckle icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckle icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckle icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckle icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckle icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckle icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckle icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckle icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckle icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckle icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckle icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckle icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckle icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckle icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckle icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckle icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckle icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckle icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckle icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckle icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckle icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckle icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cckls.cgs b/sim/testsuite/sim/frv/cckls.cgs deleted file mode 100644 index a78b7799add..00000000000 --- a/sim/testsuite/sim/frv/cckls.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cckls $ICCi,$CCj_int,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cckls -cckls: - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckls icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckls icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckls icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckls icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckls icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckls icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckls icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckls icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckls icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckls icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckls icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckls icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckls icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckls icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckls icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckls icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckls icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckls icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckls icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckls icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckls icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckls icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckls icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckls icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckls icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckls icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckls icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckls icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckls icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckls icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckls icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckls icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckls icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckls icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckls icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckls icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckls icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckls icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckls icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckls icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckls icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckls icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckls icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckls icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckls icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckls icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckls icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckls icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckls icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckls icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckls icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckls icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckls icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckls icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckls icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckls icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckls icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckls icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckls icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckls icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckls icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckls icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckls icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckls icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckls icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckls icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckls icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckls icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckls icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckls icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckls icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckls icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckls icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckls icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckls icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckls icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckls icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckls icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckls icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckls icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckls icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckls icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckls icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckls icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckls icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckls icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckls icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckls icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckls icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckls icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckls icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckls icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckls icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckls icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckls icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckls icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/ccklt.cgs b/sim/testsuite/sim/frv/ccklt.cgs deleted file mode 100644 index c14c6328694..00000000000 --- a/sim/testsuite/sim/frv/ccklt.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for ccklt $ICCi,$CCj_int,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global ccklt -ccklt: - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccklt icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccklt icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccklt icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccklt icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccklt icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccklt icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccklt icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccklt icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccklt icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccklt icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccklt icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccklt icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccklt icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccklt icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccklt icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccklt icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccklt icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccklt icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccklt icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccklt icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccklt icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccklt icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccklt icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccklt icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccklt icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccklt icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccklt icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccklt icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccklt icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccklt icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccklt icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccklt icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccklt icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccklt icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccklt icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccklt icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccklt icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccklt icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccklt icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccklt icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccklt icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccklt icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccklt icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccklt icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccklt icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccklt icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccklt icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccklt icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccklt icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccklt icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccklt icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccklt icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccklt icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccklt icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccklt icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccklt icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccklt icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccklt icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccklt icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccklt icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccklt icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccklt icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccklt icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccklt icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccklt icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccklt icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccklt icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccklt icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccklt icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccklt icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccklt icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccklt icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccklt icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccklt icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccklt icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccklt icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccklt icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccklt icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccklt icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccklt icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccklt icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccklt icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccklt icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccklt icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccklt icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccklt icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccklt icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccklt icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccklt icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccklt icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccklt icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccklt icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccklt icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccklt icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccklt icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccklt icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cckn.cgs b/sim/testsuite/sim/frv/cckn.cgs deleted file mode 100644 index d4231246d8d..00000000000 --- a/sim/testsuite/sim/frv/cckn.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cckn $ICCi,$CCj_int,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cckn -cckn: - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckn icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckn icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckn icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckn icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckn icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckn icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckn icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckn icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckn icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckn icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckn icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckn icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckn icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckn icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckn icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckn icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckn icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckn icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckn icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckn icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckn icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckn icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckn icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckn icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckn icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckn icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckn icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckn icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckn icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckn icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckn icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckn icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckn icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckn icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckn icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckn icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckn icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckn icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckn icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckn icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckn icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckn icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckn icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckn icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckn icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckn icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckn icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckn icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckn icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckn icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckn icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckn icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckn icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckn icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckn icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckn icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckn icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckn icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckn icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckn icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckn icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckn icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckn icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckn icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckn icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckn icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckn icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckn icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckn icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckn icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckn icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckn icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckn icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckn icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckn icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckn icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckn icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckn icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckn icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckn icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckn icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckn icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckn icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckn icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckn icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckn icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckn icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckn icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckn icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckn icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckn icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckn icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckn icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckn icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckn icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckn icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/ccknc.cgs b/sim/testsuite/sim/frv/ccknc.cgs deleted file mode 100644 index 0478f271ec5..00000000000 --- a/sim/testsuite/sim/frv/ccknc.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for ccknc $ICCi,$CCj_int,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global ccknc -ccknc: - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccknc icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccknc icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccknc icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccknc icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccknc icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccknc icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccknc icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccknc icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccknc icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccknc icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccknc icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccknc icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccknc icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccknc icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccknc icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccknc icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccknc icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccknc icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccknc icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccknc icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccknc icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccknc icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccknc icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccknc icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccknc icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccknc icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccknc icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccknc icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccknc icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccknc icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccknc icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccknc icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccknc icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccknc icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccknc icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccknc icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccknc icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccknc icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccknc icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccknc icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccknc icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccknc icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccknc icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccknc icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccknc icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccknc icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccknc icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccknc icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccknc icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccknc icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccknc icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccknc icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccknc icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccknc icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccknc icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccknc icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccknc icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccknc icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccknc icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccknc icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccknc icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccknc icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccknc icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccknc icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccknc icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccknc icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccknc icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccknc icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccknc icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccknc icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccknc icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccknc icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccknc icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccknc icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccknc icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccknc icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccknc icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccknc icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccknc icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccknc icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccknc icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccknc icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccknc icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccknc icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccknc icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccknc icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccknc icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccknc icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccknc icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccknc icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccknc icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccknc icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccknc icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccknc icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccknc icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccknc icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cckne.cgs b/sim/testsuite/sim/frv/cckne.cgs deleted file mode 100644 index d8af1e34cf6..00000000000 --- a/sim/testsuite/sim/frv/cckne.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cckne $ICCi,$CCj_int,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cckne -cckne: - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckne icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckne icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckne icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckne icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckne icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckne icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckne icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckne icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckne icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckne icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckne icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckne icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckne icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckne icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckne icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckne icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckne icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckne icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckne icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckne icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckne icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckne icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckne icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckne icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckne icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckne icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckne icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckne icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckne icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckne icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckne icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckne icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckne icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckne icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckne icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckne icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckne icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckne icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckne icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckne icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckne icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckne icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckne icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckne icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckne icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckne icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckne icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckne icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckne icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckne icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckne icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckne icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckne icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckne icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckne icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckne icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckne icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckne icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckne icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckne icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckne icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckne icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckne icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckne icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckne icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckne icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckne icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckne icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckne icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckne icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckne icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckne icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckne icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckne icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckne icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckne icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckne icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckne icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckne icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckne icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckne icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckne icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckne icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckne icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckne icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckne icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckne icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckne icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckne icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckne icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckne icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckne icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckne icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckne icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckne icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckne icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cckno.cgs b/sim/testsuite/sim/frv/cckno.cgs deleted file mode 100644 index 8c3c9274183..00000000000 --- a/sim/testsuite/sim/frv/cckno.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cckno $CCj_int,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cckno -cckno: - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckno cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckno cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckno cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckno cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckno cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckno cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckno cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckno cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckno cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckno cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckno cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckno cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckno cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckno cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckno cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckno cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckno cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckno cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckno cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckno cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckno cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckno cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckno cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckno cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckno cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckno cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckno cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckno cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckno cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckno cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckno cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckno cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckno cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckno cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckno cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckno cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckno cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckno cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckno cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckno cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckno cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckno cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckno cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckno cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckno cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckno cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckno cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckno cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckno cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckno cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckno cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckno cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckno cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckno cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckno cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckno cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckno cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckno cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckno cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckno cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckno cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckno cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckno cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckno cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckno cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckno cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckno cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckno cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckno cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckno cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckno cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckno cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckno cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckno cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckno cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckno cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckno cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckno cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckno cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckno cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckno cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckno cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckno cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckno cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckno cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckno cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckno cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckno cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckno cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckno cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckno cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckno cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckno cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckno cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckno cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckno cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/ccknv.cgs b/sim/testsuite/sim/frv/ccknv.cgs deleted file mode 100644 index 333edca9d83..00000000000 --- a/sim/testsuite/sim/frv/ccknv.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for ccknv $ICCi,$CCj_int,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global ccknv -ccknv: - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccknv icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccknv icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccknv icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccknv icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccknv icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccknv icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccknv icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccknv icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccknv icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccknv icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccknv icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccknv icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccknv icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccknv icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccknv icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccknv icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccknv icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccknv icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccknv icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccknv icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccknv icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccknv icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccknv icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccknv icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccknv icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccknv icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccknv icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccknv icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccknv icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccknv icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccknv icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccknv icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccknv icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccknv icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccknv icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccknv icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccknv icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccknv icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccknv icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccknv icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccknv icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccknv icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccknv icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccknv icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccknv icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccknv icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccknv icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccknv icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccknv icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccknv icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccknv icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccknv icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccknv icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccknv icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccknv icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccknv icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccknv icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccknv icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccknv icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccknv icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccknv icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccknv icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccknv icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccknv icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccknv icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccknv icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccknv icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccknv icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccknv icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccknv icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccknv icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccknv icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccknv icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccknv icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccknv icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccknv icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccknv icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccknv icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccknv icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccknv icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - ccknv icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - ccknv icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - ccknv icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - ccknv icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - ccknv icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - ccknv icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - ccknv icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - ccknv icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - ccknv icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - ccknv icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - ccknv icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - ccknv icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - ccknv icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - ccknv icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - ccknv icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - ccknv icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cckp.cgs b/sim/testsuite/sim/frv/cckp.cgs deleted file mode 100644 index 53570d98905..00000000000 --- a/sim/testsuite/sim/frv/cckp.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cckp $ICCi,$CCj_int,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cckp -cckp: - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckp icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckp icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckp icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckp icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckp icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckp icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckp icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckp icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckp icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckp icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckp icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckp icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckp icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckp icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckp icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckp icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckp icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckp icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckp icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckp icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckp icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckp icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckp icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckp icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckp icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckp icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckp icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckp icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckp icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckp icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckp icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckp icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckp icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckp icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckp icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckp icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckp icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckp icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckp icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckp icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckp icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckp icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckp icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckp icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckp icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckp icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckp icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckp icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckp icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckp icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckp icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckp icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckp icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckp icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckp icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckp icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckp icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckp icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckp icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckp icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckp icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckp icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckp icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckp icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckp icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckp icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckp icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckp icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckp icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckp icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckp icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckp icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckp icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckp icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckp icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckp icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckp icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckp icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckp icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckp icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckp icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckp icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckp icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckp icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckp icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckp icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckp icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckp icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckp icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckp icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckp icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckp icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckp icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckp icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckp icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckp icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cckra.cgs b/sim/testsuite/sim/frv/cckra.cgs deleted file mode 100644 index c0b27fca15b..00000000000 --- a/sim/testsuite/sim/frv/cckra.cgs +++ /dev/null @@ -1,480 +0,0 @@ -# frv testcase for cckra $CCj_int,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cckra -cckra: - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckra cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckra cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckra cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckra cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckra cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckra cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckra cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckra cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckra cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckra cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckra cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckra cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckra cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckra cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckra cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckra cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckra cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckra cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckra cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckra cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckra cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckra cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckra cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckra cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckra cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckra cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckra cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckra cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckra cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckra cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckra cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckra cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckra cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckra cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckra cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckra cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckra cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckra cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckra cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckra cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckra cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckra cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckra cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckra cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckra cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckra cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckra cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckra cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckra cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckra cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckra cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckra cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckra cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckra cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckra cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckra cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckra cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckra cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckra cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckra cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckra cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckra cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckra cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckra cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckra cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckra cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckra cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckra cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckra cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckra cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckra cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckra cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckra cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckra cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckra cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckra cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckra cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckra cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckra cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckra cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckra cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckra cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckra cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckra cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckra cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckra cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckra cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckra cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckra cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckra cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckra cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckra cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckra cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckra cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cckv.cgs b/sim/testsuite/sim/frv/cckv.cgs deleted file mode 100644 index 9ebb6e353a4..00000000000 --- a/sim/testsuite/sim/frv/cckv.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cckv $ICCi,$CCj_int,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cckv -cckv: - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckv icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckv icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckv icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckv icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckv icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckv icc0,cc7,cc0,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckv icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckv icc0,cc7,cc0,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckv icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckv icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckv icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckv icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckv icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckv icc0,cc7,cc4,1 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckv icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckv icc0,cc7,cc4,1 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckv icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckv icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckv icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckv icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckv icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckv icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckv icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckv icc0,cc7,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckv icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckv icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckv icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckv icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckv icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckv icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckv icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckv icc0,cc7,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckv icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckv icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckv icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckv icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckv icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckv icc0,cc7,cc1,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckv icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckv icc0,cc7,cc1,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckv icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckv icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckv icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckv icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckv icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckv icc0,cc7,cc5,0 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckv icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckv icc0,cc7,cc5,0 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckv icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckv icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckv icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckv icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckv icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckv icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckv icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckv icc0,cc7,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckv icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckv icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckv icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckv icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckv icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckv icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckv icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckv icc0,cc7,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckv icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckv icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckv icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckv icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckv icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckv icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckv icc0,cc7,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckv icc0,cc7,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckv icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckv icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckv icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckv icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckv icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckv icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckv icc0,cc7,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckv icc0,cc7,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x0 0 - cckv icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x1 0 - cckv icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x2 0 - cckv icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x3 0 - cckv icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x4 0 - cckv icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x5 0 - cckv icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x6 0 - cckv icc0,cc7,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x7 0 - cckv icc0,cc7,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x8 0 - cckv icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0x9 0 - cckv icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xa 0 - cckv icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xb 0 - cckv icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xc 0 - cckv icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xd 0 - cckv icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xe 0 - cckv icc0,cc7,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x5b1b,cccr - set_icc 0xf 0 - cckv icc0,cc7,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/ccmp.cgs b/sim/testsuite/sim/frv/ccmp.cgs deleted file mode 100644 index 52d5310499e..00000000000 --- a/sim/testsuite/sim/frv/ccmp.cgs +++ /dev/null @@ -1,134 +0,0 @@ -# frv testcase for ccmp $GRi,$GRj,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global ccmp -ccmp: - set_spr_immed 0x1b1b,cccr - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - ccmp gr8,gr7,cc0,1 - test_icc 0 0 0 0 icc0 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - ccmp gr8,gr7,cc0,1 - test_icc 0 0 1 0 icc0 - - set_icc 0x0b,0 ; Set mask opposite of expected - ccmp gr8,gr8,cc4,1 - test_icc 0 1 0 0 icc0 - - set_gr_immed 0,gr8 - set_icc 0x06,0 ; Set mask opposite of expected - ccmp gr8,gr7,cc4,1 - test_icc 1 0 0 1 icc0 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - ccmp gr8,gr7,cc0,0 - test_icc 1 1 1 1 icc0 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - ccmp gr8,gr7,cc0,0 - test_icc 1 1 0 1 icc0 - - set_icc 0x0b,0 ; Set mask opposite of expected - ccmp gr8,gr8,cc4,0 - test_icc 1 0 1 1 icc0 - - set_icc 0x06,0 ; Set mask opposite of expected - ccmp gr8,gr7,cc4,0 - test_icc 0 1 1 0 icc0 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - ccmp gr8,gr7,cc1,0 - test_icc 0 0 0 0 icc1 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,1 ; Set mask opposite of expected - ccmp gr8,gr7,cc1,0 - test_icc 0 0 1 0 icc1 - - set_icc 0x0b,1 ; Set mask opposite of expected - ccmp gr8,gr8,cc5,0 - test_icc 0 1 0 0 icc1 - - set_gr_immed 0,gr8 - set_icc 0x06,1 ; Set mask opposite of expected - ccmp gr8,gr7,cc5,0 - test_icc 1 0 0 1 icc1 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - ccmp gr8,gr7,cc1,1 - test_icc 1 1 1 1 icc1 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,1 ; Set mask opposite of expected - ccmp gr8,gr7,cc1,1 - test_icc 1 1 0 1 icc1 - - set_icc 0x0b,1 ; Set mask opposite of expected - ccmp gr8,gr8,cc5,1 - test_icc 1 0 1 1 icc1 - - set_icc 0x06,1 ; Set mask opposite of expected - ccmp gr8,gr7,cc5,1 - test_icc 0 1 1 0 icc1 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,2 ; Set mask opposite of expected - ccmp gr8,gr7,cc2,0 - test_icc 1 1 1 1 icc2 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,2 ; Set mask opposite of expected - ccmp gr8,gr7,cc2,0 - test_icc 1 1 0 1 icc2 - - set_icc 0x0b,2 ; Set mask opposite of expected - ccmp gr8,gr8,cc6,1 - test_icc 1 0 1 1 icc2 - - set_icc 0x06,2 ; Set mask opposite of expected - ccmp gr8,gr7,cc6,1 - test_icc 0 1 1 0 icc2 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,3 ; Set mask opposite of expected - ccmp gr8,gr7,cc3,0 - test_icc 1 1 1 1 icc3 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,3 ; Set mask opposite of expected - ccmp gr8,gr7,cc3,0 - test_icc 1 1 0 1 icc3 - - set_icc 0x0b,3 ; Set mask opposite of expected - ccmp gr8,gr8,cc7,1 - test_icc 1 0 1 1 icc3 - - set_icc 0x06,3 ; Set mask opposite of expected - ccmp gr8,gr7,cc7,1 - test_icc 0 1 1 0 icc3 - - pass diff --git a/sim/testsuite/sim/frv/cfabss.cgs b/sim/testsuite/sim/frv/cfabss.cgs deleted file mode 100644 index 752a40bdbf2..00000000000 --- a/sim/testsuite/sim/frv/cfabss.cgs +++ /dev/null @@ -1,96 +0,0 @@ -# frv testcase for cfabss $FRj,$FRk,$CCi,$cond -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global cfabss -cfabss: - set_spr_immed 0x1b1b,cccr - - cfabss fr0,fr1,cc0,1 - test_fr_fr fr1,fr52 - cfabss fr8,fr1,cc0,1 - test_fr_fr fr1,fr28 - cfabss fr12,fr1,cc0,1 - test_fr_fr fr1,fr24 - cfabss fr24,fr1,cc4,1 - test_fr_fr fr1,fr24 - cfabss fr28,fr1,cc4,1 - test_fr_fr fr1,fr28 - cfabss fr52,fr1,cc4,1 - test_fr_fr fr1,fr52 - - cfabss fr0,fr1,cc1,0 - test_fr_fr fr1,fr52 - cfabss fr8,fr1,cc1,0 - test_fr_fr fr1,fr28 - cfabss fr12,fr1,cc1,0 - test_fr_fr fr1,fr24 - cfabss fr24,fr1,cc5,0 - test_fr_fr fr1,fr24 - cfabss fr28,fr1,cc5,0 - test_fr_fr fr1,fr28 - cfabss fr52,fr1,cc5,0 - test_fr_fr fr1,fr52 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfabss fr0,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr8,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr12,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr24,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr28,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr52,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfabss fr0,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr8,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr12,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr24,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr28,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr52,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfabss fr0,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr8,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr12,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr24,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr28,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr52,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfabss fr0,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr8,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr12,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr24,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr28,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfabss fr52,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - - pass diff --git a/sim/testsuite/sim/frv/cfadds.cgs b/sim/testsuite/sim/frv/cfadds.cgs deleted file mode 100644 index 158ac930455..00000000000 --- a/sim/testsuite/sim/frv/cfadds.cgs +++ /dev/null @@ -1,456 +0,0 @@ -# frv testcase for cfadds $FRi,$FRj,$FRk,$CCi,$cond -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global cfadds -cfadds: - set_spr_immed 0x1b1b,cccr - - cfadds fr16,fr0,fr1,cc0,1 - test_fr_fr fr1,fr0 - cfadds fr16,fr4,fr1,cc0,1 - test_fr_fr fr1,fr4 - cfadds fr16,fr8,fr1,cc0,1 - test_fr_fr fr1,fr8 - cfadds fr16,fr12,fr1,cc0,1 - test_fr_fr fr1,fr12 - cfadds fr16,fr16,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfadds fr16,fr20,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfadds fr16,fr24,fr1,cc0,1 - test_fr_fr fr1,fr24 - cfadds fr16,fr28,fr1,cc0,1 - test_fr_fr fr1,fr28 - cfadds fr16,fr32,fr1,cc0,1 - test_fr_fr fr1,fr32 - cfadds fr16,fr36,fr1,cc0,1 - test_fr_fr fr1,fr36 - cfadds fr16,fr40,fr1,cc0,1 - test_fr_fr fr1,fr40 - cfadds fr16,fr44,fr1,cc0,1 - test_fr_fr fr1,fr44 - cfadds fr16,fr48,fr1,cc0,1 - test_fr_fr fr1,fr48 - cfadds fr16,fr52,fr1,cc0,1 - test_fr_fr fr1,fr52 - - cfadds fr20,fr0,fr1,cc0,1 - test_fr_fr fr1,fr0 - cfadds fr20,fr4,fr1,cc0,1 - test_fr_fr fr1,fr4 - cfadds fr20,fr8,fr1,cc4,1 - test_fr_fr fr1,fr8 - cfadds fr20,fr12,fr1,cc4,1 - test_fr_fr fr1,fr12 - cfadds fr20,fr16,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfadds fr20,fr20,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfadds fr20,fr24,fr1,cc4,1 - test_fr_fr fr1,fr24 - cfadds fr20,fr28,fr1,cc4,1 - test_fr_fr fr1,fr28 - cfadds fr20,fr32,fr1,cc4,1 - test_fr_fr fr1,fr32 - cfadds fr20,fr36,fr1,cc4,1 - test_fr_fr fr1,fr36 - cfadds fr20,fr40,fr1,cc4,1 - test_fr_fr fr1,fr40 - cfadds fr20,fr44,fr1,cc4,1 - test_fr_fr fr1,fr44 - cfadds fr20,fr48,fr1,cc4,1 - test_fr_fr fr1,fr48 - cfadds fr20,fr52,fr1,cc4,1 - test_fr_fr fr1,fr52 - - cfadds fr8,fr28,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfadds fr12,fr24,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfadds fr24,fr12,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfadds fr28,fr8,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - cfadds fr36,fr40,fr1,cc4,1 - test_fr_fr fr1,fr44 - - cfadds fr16,fr0,fr1,cc1,0 - test_fr_fr fr1,fr0 - cfadds fr16,fr4,fr1,cc1,0 - test_fr_fr fr1,fr4 - cfadds fr16,fr8,fr1,cc1,0 - test_fr_fr fr1,fr8 - cfadds fr16,fr12,fr1,cc1,0 - test_fr_fr fr1,fr12 - cfadds fr16,fr16,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfadds fr16,fr20,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfadds fr16,fr24,fr1,cc1,0 - test_fr_fr fr1,fr24 - cfadds fr16,fr28,fr1,cc1,0 - test_fr_fr fr1,fr28 - cfadds fr16,fr32,fr1,cc1,0 - test_fr_fr fr1,fr32 - cfadds fr16,fr36,fr1,cc1,0 - test_fr_fr fr1,fr36 - cfadds fr16,fr40,fr1,cc1,0 - test_fr_fr fr1,fr40 - cfadds fr16,fr44,fr1,cc1,0 - test_fr_fr fr1,fr44 - cfadds fr16,fr48,fr1,cc1,0 - test_fr_fr fr1,fr48 - cfadds fr16,fr52,fr1,cc1,0 - test_fr_fr fr1,fr52 - - cfadds fr20,fr0,fr1,cc1,0 - test_fr_fr fr1,fr0 - cfadds fr20,fr4,fr1,cc1,0 - test_fr_fr fr1,fr4 - cfadds fr20,fr8,fr1,cc5,0 - test_fr_fr fr1,fr8 - cfadds fr20,fr12,fr1,cc5,0 - test_fr_fr fr1,fr12 - cfadds fr20,fr16,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfadds fr20,fr20,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfadds fr20,fr24,fr1,cc5,0 - test_fr_fr fr1,fr24 - cfadds fr20,fr28,fr1,cc5,0 - test_fr_fr fr1,fr28 - cfadds fr20,fr32,fr1,cc5,0 - test_fr_fr fr1,fr32 - cfadds fr20,fr36,fr1,cc5,0 - test_fr_fr fr1,fr36 - cfadds fr20,fr40,fr1,cc5,0 - test_fr_fr fr1,fr40 - cfadds fr20,fr44,fr1,cc5,0 - test_fr_fr fr1,fr44 - cfadds fr20,fr48,fr1,cc5,0 - test_fr_fr fr1,fr48 - cfadds fr20,fr52,fr1,cc5,0 - test_fr_fr fr1,fr52 - - cfadds fr8,fr28,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfadds fr12,fr24,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfadds fr24,fr12,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfadds fr28,fr8,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - cfadds fr36,fr40,fr1,cc5,0 - test_fr_fr fr1,fr44 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfadds fr16,fr0,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr4,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr8,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr12,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr20,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr24,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr32,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr36,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr40,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr44,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr48,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr52,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfadds fr20,fr0,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr4,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr8,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr12,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr16,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr20,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr24,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr28,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr32,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr36,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr40,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr44,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr48,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr52,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfadds fr8,fr28,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr12,fr24,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr24,fr12,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr28,fr8,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfadds fr36,fr40,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfadds fr16,fr0,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr4,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr8,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr12,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr20,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr24,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr32,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr36,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr40,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr44,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr48,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr52,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfadds fr20,fr0,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr4,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr8,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr12,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr16,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr20,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr24,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr28,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr32,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr36,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr40,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr44,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr48,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr52,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfadds fr8,fr28,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr12,fr24,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr24,fr12,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr28,fr8,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfadds fr36,fr40,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfadds fr16,fr0,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr4,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr8,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr12,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr16,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr20,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr24,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr28,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr32,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr36,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr40,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr44,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr48,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr52,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfadds fr20,fr0,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr4,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr8,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr12,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr16,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr20,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr24,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr28,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr32,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr36,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr40,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr44,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr48,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr52,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfadds fr8,fr28,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr12,fr24,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr24,fr12,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr28,fr8,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfadds fr36,fr40,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 -; - set_fr_iimmed 0xdead,0xbeef,fr1 - cfadds fr16,fr0,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr4,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr8,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr12,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr16,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr20,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr24,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr28,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr32,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr36,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr40,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr44,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr48,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr16,fr52,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfadds fr20,fr0,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr4,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr8,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr12,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr16,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr20,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr24,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr28,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr32,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr36,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr40,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr44,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr48,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr20,fr52,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfadds fr8,fr28,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr12,fr24,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr24,fr12,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfadds fr28,fr8,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfadds fr36,fr40,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - - pass - - diff --git a/sim/testsuite/sim/frv/cfckeq.cgs b/sim/testsuite/sim/frv/cfckeq.cgs deleted file mode 100644 index 467568af55e..00000000000 --- a/sim/testsuite/sim/frv/cfckeq.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cfckeq $FCCi,$CCj_float,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cfckeq -cfckeq: - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckeq fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckeq fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckeq fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckeq fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckeq fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckeq fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckeq fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckeq fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckeq fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckeq fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckeq fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckeq fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckeq fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckeq fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckeq fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckeq fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckeq fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckeq fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckeq fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckeq fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckeq fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckeq fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckeq fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckeq fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckeq fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckeq fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckeq fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckeq fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckeq fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckeq fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckeq fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckeq fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckeq fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckeq fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckeq fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckeq fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckeq fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckeq fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckeq fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckeq fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckeq fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckeq fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckeq fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckeq fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckeq fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckeq fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckeq fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckeq fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckeq fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckeq fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckeq fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckeq fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckeq fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckeq fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckeq fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckeq fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckeq fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckeq fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckeq fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckeq fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckeq fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckeq fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckeq fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckeq fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckeq fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckeq fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckeq fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckeq fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckeq fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckeq fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckeq fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckeq fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckeq fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckeq fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckeq fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckeq fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckeq fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckeq fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckeq fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckeq fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckeq fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckeq fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckeq fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckeq fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckeq fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckeq fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckeq fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckeq fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckeq fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckeq fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckeq fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckeq fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckeq fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckeq fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckeq fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckeq fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cfckge.cgs b/sim/testsuite/sim/frv/cfckge.cgs deleted file mode 100644 index ba2de9510e7..00000000000 --- a/sim/testsuite/sim/frv/cfckge.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cfckge $FCCi,$CCj_float,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cfckge -cfckge: - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckge fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckge fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckge fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckge fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckge fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckge fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckge fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckge fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckge fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckge fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckge fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckge fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckge fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckge fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckge fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckge fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckge fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckge fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckge fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckge fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckge fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckge fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckge fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckge fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckge fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckge fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckge fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckge fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckge fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckge fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckge fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckge fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckge fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckge fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckge fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckge fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckge fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckge fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckge fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckge fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckge fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckge fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckge fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckge fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckge fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckge fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckge fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckge fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckge fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckge fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckge fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckge fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckge fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckge fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckge fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckge fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckge fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckge fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckge fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckge fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckge fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckge fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckge fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckge fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckge fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckge fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckge fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckge fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckge fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckge fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckge fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckge fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckge fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckge fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckge fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckge fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckge fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckge fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckge fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckge fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckge fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckge fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckge fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckge fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckge fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckge fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckge fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckge fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckge fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckge fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckge fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckge fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckge fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckge fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckge fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckge fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cfckgt.cgs b/sim/testsuite/sim/frv/cfckgt.cgs deleted file mode 100644 index 7858c1772a6..00000000000 --- a/sim/testsuite/sim/frv/cfckgt.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cfckgt $FCCi,$CCj_float,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cfckgt -cfckgt: - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckgt fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckgt fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckgt fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckgt fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckgt fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckgt fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckgt fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckgt fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckgt fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckgt fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckgt fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckgt fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckgt fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckgt fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckgt fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckgt fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckgt fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckgt fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckgt fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckgt fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckgt fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckgt fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckgt fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckgt fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckgt fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckgt fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckgt fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckgt fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckgt fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckgt fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckgt fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckgt fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckgt fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckgt fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckgt fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckgt fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckgt fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckgt fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckgt fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckgt fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckgt fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckgt fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckgt fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckgt fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckgt fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckgt fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckgt fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckgt fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckgt fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckgt fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckgt fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckgt fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckgt fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckgt fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckgt fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckgt fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckgt fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckgt fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckgt fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckgt fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckgt fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckgt fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckgt fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckgt fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckgt fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckgt fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckgt fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckgt fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckgt fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckgt fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckgt fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckgt fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckgt fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckgt fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckgt fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckgt fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckgt fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckgt fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckgt fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckgt fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckgt fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckgt fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckgt fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckgt fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckgt fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckgt fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckgt fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckgt fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckgt fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckgt fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckgt fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckgt fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckgt fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckgt fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckgt fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckgt fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cfckle.cgs b/sim/testsuite/sim/frv/cfckle.cgs deleted file mode 100644 index fb2b1b85e13..00000000000 --- a/sim/testsuite/sim/frv/cfckle.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cfckle $FCCi,$CCj_float$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cfckle -cfckle: - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckle fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckle fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckle fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckle fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckle fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckle fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckle fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckle fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckle fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckle fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckle fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckle fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckle fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckle fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckle fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckle fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckle fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckle fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckle fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckle fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckle fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckle fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckle fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckle fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckle fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckle fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckle fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckle fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckle fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckle fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckle fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckle fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckle fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckle fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckle fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckle fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckle fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckle fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckle fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckle fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckle fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckle fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckle fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckle fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckle fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckle fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckle fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckle fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckle fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckle fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckle fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckle fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckle fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckle fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckle fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckle fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckle fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckle fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckle fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckle fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckle fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckle fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckle fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckle fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckle fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckle fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckle fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckle fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckle fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckle fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckle fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckle fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckle fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckle fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckle fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckle fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckle fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckle fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckle fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckle fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckle fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckle fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckle fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckle fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckle fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckle fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckle fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckle fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckle fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckle fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckle fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckle fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckle fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckle fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckle fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckle fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cfcklg.cgs b/sim/testsuite/sim/frv/cfcklg.cgs deleted file mode 100644 index 22deb52f38d..00000000000 --- a/sim/testsuite/sim/frv/cfcklg.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cfcklg $FCCi,$CCj_float$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cfcklg -cfcklg: - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcklg fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcklg fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcklg fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcklg fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcklg fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcklg fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcklg fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcklg fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcklg fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcklg fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcklg fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcklg fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcklg fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcklg fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcklg fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcklg fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcklg fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcklg fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcklg fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcklg fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcklg fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcklg fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcklg fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcklg fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcklg fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcklg fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcklg fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcklg fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcklg fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcklg fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcklg fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcklg fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcklg fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcklg fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcklg fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcklg fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcklg fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcklg fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcklg fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcklg fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcklg fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcklg fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcklg fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcklg fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcklg fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcklg fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcklg fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcklg fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcklg fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcklg fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcklg fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcklg fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcklg fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcklg fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcklg fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcklg fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcklg fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcklg fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcklg fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcklg fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcklg fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcklg fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcklg fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcklg fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcklg fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcklg fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcklg fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcklg fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcklg fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcklg fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcklg fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcklg fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcklg fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcklg fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcklg fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcklg fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcklg fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcklg fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcklg fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcklg fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcklg fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcklg fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcklg fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcklg fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcklg fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcklg fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcklg fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcklg fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcklg fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcklg fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcklg fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcklg fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcklg fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcklg fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcklg fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcklg fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cfcklt.cgs b/sim/testsuite/sim/frv/cfcklt.cgs deleted file mode 100644 index ffabcd2628b..00000000000 --- a/sim/testsuite/sim/frv/cfcklt.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cfcklt $FCCi,$CCj_float,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cfcklt -cfcklt: - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcklt fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcklt fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcklt fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcklt fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcklt fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcklt fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcklt fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcklt fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcklt fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcklt fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcklt fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcklt fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcklt fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcklt fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcklt fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcklt fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcklt fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcklt fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcklt fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcklt fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcklt fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcklt fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcklt fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcklt fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcklt fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcklt fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcklt fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcklt fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcklt fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcklt fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcklt fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcklt fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcklt fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcklt fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcklt fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcklt fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcklt fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcklt fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcklt fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcklt fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcklt fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcklt fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcklt fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcklt fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcklt fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcklt fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcklt fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcklt fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcklt fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcklt fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcklt fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcklt fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcklt fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcklt fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcklt fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcklt fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcklt fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcklt fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcklt fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcklt fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcklt fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcklt fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcklt fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcklt fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcklt fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcklt fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcklt fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcklt fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcklt fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcklt fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcklt fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcklt fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcklt fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcklt fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcklt fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcklt fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcklt fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcklt fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcklt fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcklt fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcklt fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcklt fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcklt fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcklt fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcklt fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcklt fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcklt fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcklt fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcklt fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcklt fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcklt fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcklt fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcklt fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcklt fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcklt fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcklt fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cfckne.cgs b/sim/testsuite/sim/frv/cfckne.cgs deleted file mode 100644 index da6846fa30e..00000000000 --- a/sim/testsuite/sim/frv/cfckne.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cfckne $FCCi,$CCj_float,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cfckne -cfckne: - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckne fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckne fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckne fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckne fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckne fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckne fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckne fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckne fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckne fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckne fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckne fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckne fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckne fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckne fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckne fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckne fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckne fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckne fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckne fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckne fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckne fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckne fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckne fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckne fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckne fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckne fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckne fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckne fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckne fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckne fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckne fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckne fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckne fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckne fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckne fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckne fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckne fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckne fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckne fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckne fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckne fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckne fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckne fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckne fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckne fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckne fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckne fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckne fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckne fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckne fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckne fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckne fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckne fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckne fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckne fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckne fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckne fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckne fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckne fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckne fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckne fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckne fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckne fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckne fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckne fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckne fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckne fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckne fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckne fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckne fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckne fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckne fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckne fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckne fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckne fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckne fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckne fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckne fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckne fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckne fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckne fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckne fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckne fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckne fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckne fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckne fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckne fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckne fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckne fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckne fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckne fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckne fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckne fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckne fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckne fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckne fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cfckno.cgs b/sim/testsuite/sim/frv/cfckno.cgs deleted file mode 100644 index 56819604070..00000000000 --- a/sim/testsuite/sim/frv/cfckno.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cfckno $CCj_float,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cfckno -cfckno: - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckno cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckno cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckno cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckno cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckno cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckno cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckno cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckno cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckno cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckno cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckno cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckno cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckno cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckno cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckno cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckno cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckno cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckno cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckno cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckno cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckno cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckno cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckno cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckno cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckno cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckno cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckno cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckno cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckno cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckno cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckno cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckno cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckno cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckno cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckno cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckno cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckno cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckno cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckno cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckno cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckno cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckno cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckno cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckno cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckno cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckno cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckno cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckno cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckno cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckno cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckno cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckno cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckno cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckno cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckno cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckno cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckno cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckno cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckno cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckno cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckno cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckno cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckno cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckno cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckno cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckno cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckno cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckno cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckno cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckno cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckno cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckno cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckno cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckno cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckno cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckno cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckno cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckno cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckno cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckno cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckno cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckno cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckno cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckno cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckno cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckno cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckno cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckno cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckno cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckno cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckno cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckno cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckno cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckno cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckno cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckno cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cfcko.cgs b/sim/testsuite/sim/frv/cfcko.cgs deleted file mode 100644 index ac55fc3e7ac..00000000000 --- a/sim/testsuite/sim/frv/cfcko.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cfcko $FCCi,$CCj_float,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cfcko -cfcko: - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcko fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcko fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcko fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcko fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcko fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcko fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcko fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcko fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcko fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcko fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcko fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcko fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcko fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcko fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcko fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcko fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcko fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcko fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcko fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcko fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcko fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcko fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcko fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcko fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcko fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcko fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcko fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcko fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcko fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcko fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcko fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcko fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcko fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcko fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcko fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcko fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcko fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcko fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcko fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcko fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcko fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcko fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcko fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcko fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcko fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcko fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcko fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcko fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcko fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcko fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcko fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcko fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcko fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcko fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcko fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcko fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcko fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcko fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcko fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcko fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcko fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcko fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcko fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcko fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcko fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcko fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcko fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcko fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcko fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcko fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcko fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcko fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcko fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcko fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcko fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcko fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcko fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcko fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcko fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcko fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcko fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcko fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcko fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcko fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcko fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcko fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcko fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcko fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcko fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcko fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcko fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcko fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcko fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcko fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcko fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcko fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cfckra.cgs b/sim/testsuite/sim/frv/cfckra.cgs deleted file mode 100644 index 0cabd8f47c1..00000000000 --- a/sim/testsuite/sim/frv/cfckra.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cfckra $CCj_float,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cfckra -cfckra: - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckra cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckra cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckra cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckra cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckra cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckra cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckra cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckra cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckra cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckra cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckra cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckra cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckra cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckra cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckra cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckra cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckra cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckra cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckra cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckra cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckra cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckra cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckra cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckra cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckra cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckra cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckra cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckra cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckra cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckra cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckra cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckra cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckra cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckra cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckra cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckra cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckra cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckra cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckra cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckra cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckra cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckra cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckra cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckra cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckra cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckra cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckra cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckra cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckra cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckra cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckra cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckra cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckra cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckra cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckra cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckra cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckra cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckra cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckra cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckra cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckra cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckra cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckra cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckra cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckra cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckra cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckra cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckra cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckra cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckra cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckra cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckra cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckra cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckra cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckra cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckra cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckra cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckra cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckra cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckra cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckra cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckra cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckra cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckra cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckra cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckra cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckra cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckra cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckra cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckra cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckra cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckra cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckra cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckra cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckra cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckra cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cfcku.cgs b/sim/testsuite/sim/frv/cfcku.cgs deleted file mode 100644 index 0f56e7e74c6..00000000000 --- a/sim/testsuite/sim/frv/cfcku.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cfcku $FCCi,$CCj_float,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cfcku -cfcku: - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcku fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcku fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcku fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcku fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcku fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcku fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcku fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcku fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcku fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcku fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcku fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcku fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcku fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcku fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcku fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcku fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcku fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcku fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcku fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcku fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcku fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcku fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcku fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcku fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcku fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcku fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcku fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcku fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcku fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcku fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcku fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcku fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcku fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcku fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcku fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcku fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcku fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcku fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcku fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcku fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcku fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcku fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcku fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcku fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcku fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcku fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcku fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcku fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcku fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcku fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcku fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcku fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcku fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcku fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcku fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcku fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcku fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcku fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcku fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcku fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcku fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcku fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcku fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcku fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcku fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcku fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcku fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcku fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcku fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcku fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcku fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcku fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcku fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcku fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcku fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcku fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcku fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcku fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcku fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcku fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfcku fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfcku fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfcku fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfcku fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfcku fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfcku fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfcku fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfcku fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfcku fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfcku fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfcku fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfcku fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfcku fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfcku fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfcku fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfcku fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cfckue.cgs b/sim/testsuite/sim/frv/cfckue.cgs deleted file mode 100644 index 447c2bac3ed..00000000000 --- a/sim/testsuite/sim/frv/cfckue.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cfckue $FCCi,$CCj_float,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cfckue -cfckue: - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckue fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckue fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckue fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckue fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckue fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckue fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckue fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckue fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckue fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckue fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckue fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckue fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckue fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckue fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckue fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckue fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckue fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckue fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckue fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckue fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckue fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckue fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckue fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckue fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckue fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckue fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckue fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckue fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckue fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckue fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckue fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckue fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckue fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckue fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckue fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckue fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckue fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckue fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckue fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckue fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckue fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckue fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckue fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckue fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckue fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckue fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckue fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckue fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckue fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckue fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckue fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckue fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckue fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckue fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckue fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckue fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckue fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckue fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckue fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckue fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckue fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckue fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckue fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckue fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckue fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckue fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckue fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckue fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckue fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckue fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckue fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckue fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckue fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckue fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckue fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckue fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckue fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckue fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckue fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckue fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckue fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckue fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckue fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckue fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckue fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckue fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckue fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckue fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckue fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckue fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckue fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckue fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckue fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckue fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckue fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckue fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cfckug.cgs b/sim/testsuite/sim/frv/cfckug.cgs deleted file mode 100644 index 7442f84a457..00000000000 --- a/sim/testsuite/sim/frv/cfckug.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cfckug $FCCi,$CCj_float,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cfckug -cfckug: - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckug fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckug fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckug fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckug fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckug fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckug fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckug fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckug fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckug fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckug fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckug fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckug fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckug fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckug fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckug fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckug fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckug fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckug fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckug fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckug fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckug fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckug fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckug fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckug fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckug fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckug fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckug fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckug fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckug fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckug fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckug fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckug fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckug fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckug fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckug fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckug fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckug fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckug fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckug fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckug fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckug fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckug fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckug fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckug fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckug fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckug fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckug fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckug fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckug fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckug fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckug fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckug fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckug fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckug fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckug fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckug fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckug fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckug fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckug fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckug fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckug fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckug fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckug fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckug fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckug fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckug fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckug fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckug fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckug fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckug fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckug fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckug fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckug fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckug fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckug fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckug fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckug fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckug fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckug fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckug fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckug fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckug fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckug fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckug fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckug fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckug fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckug fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckug fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckug fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckug fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckug fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckug fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckug fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckug fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckug fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckug fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cfckuge.cgs b/sim/testsuite/sim/frv/cfckuge.cgs deleted file mode 100644 index 8eaf92fd406..00000000000 --- a/sim/testsuite/sim/frv/cfckuge.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cfckuge $FCCi,$CCj_float,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cfckuge -cfckuge: - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckuge fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckuge fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckuge fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckuge fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckuge fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckuge fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckuge fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckuge fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckuge fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckuge fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckuge fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckuge fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckuge fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckuge fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckuge fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckuge fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckuge fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckuge fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckuge fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckuge fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckuge fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckuge fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckuge fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckuge fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckuge fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckuge fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckuge fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckuge fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckuge fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckuge fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckuge fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckuge fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckuge fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckuge fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckuge fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckuge fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckuge fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckuge fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckuge fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckuge fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckuge fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckuge fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckuge fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckuge fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckuge fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckuge fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckuge fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckuge fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckuge fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckuge fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckuge fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckuge fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckuge fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckuge fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckuge fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckuge fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckuge fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckuge fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckuge fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckuge fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckuge fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckuge fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckuge fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckuge fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckuge fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckuge fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckuge fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckuge fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckuge fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckuge fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckuge fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckuge fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckuge fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckuge fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckuge fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckuge fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckuge fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckuge fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckuge fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckuge fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckuge fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckuge fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckuge fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckuge fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckuge fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckuge fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckuge fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckuge fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckuge fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckuge fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckuge fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckuge fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckuge fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckuge fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckuge fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckuge fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cfckul.cgs b/sim/testsuite/sim/frv/cfckul.cgs deleted file mode 100644 index 5945a8a7ce0..00000000000 --- a/sim/testsuite/sim/frv/cfckul.cgs +++ /dev/null @@ -1,410 +0,0 @@ -# frv testcase for cfckul $FCCi,$CCj_float,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cfckul -cfckul: - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckul fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckul fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckul fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckul fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckul fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckul fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckul fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckul fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckul fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckul fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckul fcc0,cc3,cc4,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckul fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckul fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckul fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckul fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckul fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckul fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckul fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckul fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckul fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckul fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckul fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckul fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckul fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckul fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckul fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckul fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckul fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckul fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckul fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckul fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckul fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckul fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckul fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckul fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckul fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckul fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckul fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckul fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckul fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckul fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckul fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckul fcc0,cc3,cc5,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckul fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckul fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckul fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckul fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckul fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckul fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckul fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckul fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckul fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckul fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckul fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckul fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckul fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckul fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckul fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckul fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckul fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckul fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckul fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckul fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckul fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckul fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckul fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckul fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckul fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckul fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckul fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckul fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckul fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckul fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckul fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckul fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckul fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckul fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckul fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckul fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckul fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cfckule.cgs b/sim/testsuite/sim/frv/cfckule.cgs deleted file mode 100644 index aaf655e8430..00000000000 --- a/sim/testsuite/sim/frv/cfckule.cgs +++ /dev/null @@ -1,490 +0,0 @@ -# frv testcase for cfckule $FCCi,$CCj_float,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cfckule -cfckule: - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckule fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckule fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckule fcc0,cc3,cc0,1 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckule fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckule fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckule fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckule fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckule fcc0,cc3,cc0,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckule fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckule fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckule fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckule fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckule fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckule fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckule fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckule fcc0,cc3,cc4,1 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckule fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckule fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckule fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckule fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckule fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckule fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckule fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckule fcc0,cc3,cc0,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckule fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckule fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckule fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckule fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckule fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckule fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckule fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckule fcc0,cc3,cc4,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckule fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckule fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckule fcc0,cc3,cc1,0 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckule fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckule fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckule fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckule fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckule fcc0,cc3,cc1,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckule fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckule fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckule fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckule fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckule fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckule fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckule fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckule fcc0,cc3,cc5,0 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckule fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckule fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckule fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckule fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckule fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckule fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckule fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckule fcc0,cc3,cc1,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckule fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckule fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckule fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckule fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckule fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckule fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckule fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckule fcc0,cc3,cc5,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckule fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckule fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckule fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckule fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckule fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckule fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckule fcc0,cc3,cc2,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckule fcc0,cc3,cc2,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckule fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckule fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckule fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckule fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckule fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckule fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckule fcc0,cc3,cc6,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckule fcc0,cc3,cc6,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x0 0 - cfckule fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x1 0 - cfckule fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x2 0 - cfckule fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x3 0 - cfckule fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x4 0 - cfckule fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x5 0 - cfckule fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x6 0 - cfckule fcc0,cc3,cc3,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x7 0 - cfckule fcc0,cc3,cc3,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x8 0 - cfckule fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0x9 0 - cfckule fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xa 0 - cfckule fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xb 0 - cfckule fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xc 0 - cfckule fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xd 0 - cfckule fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xe 0 - cfckule fcc0,cc3,cc7,0 - test_spr_immed 0x1b1b,cccr - - set_spr_immed 0x1b5b,cccr - set_fcc 0xf 0 - cfckule fcc0,cc3,cc7,1 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cfcmps.cgs b/sim/testsuite/sim/frv/cfcmps.cgs deleted file mode 100644 index 168e618853b..00000000000 --- a/sim/testsuite/sim/frv/cfcmps.cgs +++ /dev/null @@ -1,3542 +0,0 @@ -# frv testcase for cfcmps $FRi,$FRj,$FCCi,$CCi,$cond_2 -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global cfcmps -cfcmps: - set_spr_immed 0x1b1b,cccr - - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr0,fr0,fcc0,cc0,1 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr4,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr8,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr12,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr16,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr20,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr24,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr28,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr32,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr36,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr40,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr44,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr48,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr52,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr0,fr56,fcc0,cc0,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr0,fr60,fcc0,cc0,1 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr4,fr0,fcc0,cc0,1 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr4,fr4,fcc0,cc0,1 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr8,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr12,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr16,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr20,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr24,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr28,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr32,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr36,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr40,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr44,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr48,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr52,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr4,fr56,fcc0,cc0,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr4,fr60,fcc0,cc0,1 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr8,fr0,fcc0,cc0,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr8,fr4,fcc0,cc0,1 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr8,fr8,fcc0,cc0,1 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr12,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr16,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr20,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr24,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr28,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr32,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr36,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr40,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr44,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr48,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr52,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr8,fr56,fcc0,cc0,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr8,fr60,fcc0,cc0,1 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr0,fcc0,cc0,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr4,fcc0,cc0,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr8,fcc0,cc0,1 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr12,fr12,fcc0,cc0,1 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr16,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr20,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr24,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr28,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr32,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr36,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr40,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr44,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr48,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr52,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr12,fr56,fcc0,cc0,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr12,fr60,fcc0,cc0,1 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr0,fcc0,cc0,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr4,fcc0,cc0,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr8,fcc0,cc0,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr12,fcc0,cc0,1 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr16,fr16,fcc0,cc0,1 - test_fcc 0x8,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr16,fr20,fcc0,cc0,1 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr24,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr28,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr32,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr36,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr40,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr44,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr48,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr52,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr16,fr56,fcc0,cc0,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr16,fr60,fcc0,cc0,1 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr0,fcc0,cc0,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr4,fcc0,cc0,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr8,fcc0,cc0,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr12,fcc0,cc0,1 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr20,fr16,fcc0,cc0,1 - test_fcc 0x8,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr20,fr20,fcc0,cc0,1 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr24,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr28,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr32,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr36,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr40,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr44,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr48,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr52,fcc0,cc0,1 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr20,fr56,fcc0,cc0,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr20,fr60,fcc0,cc0,1 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr0,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr4,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr8,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr12,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr16,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr20,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr24,fr24,fcc0,cc4,1 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr28,fcc0,cc4,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr32,fcc0,cc4,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr36,fcc0,cc4,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr40,fcc0,cc4,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr44,fcc0,cc4,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr48,fcc0,cc4,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr52,fcc0,cc4,1 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr24,fr56,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr24,fr60,fcc0,cc4,1 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr0,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr4,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr8,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr12,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr16,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr20,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr24,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr28,fr28,fcc0,cc4,1 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr32,fcc0,cc4,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr36,fcc0,cc4,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr40,fcc0,cc4,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr44,fcc0,cc4,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr48,fcc0,cc4,1 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr52,fcc0,cc4,1 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr28,fr56,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr28,fr60,fcc0,cc4,1 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr0,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr4,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr8,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr12,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr16,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr20,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr24,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr28,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr32,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr36,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr40,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr44,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr48,fr48,fcc0,cc4,1 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr48,fr52,fcc0,cc4,1 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr48,fr56,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr48,fr60,fcc0,cc4,1 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr0,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr4,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr8,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr12,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr16,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr20,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr24,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr28,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr32,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr36,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr40,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr44,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr48,fcc0,cc4,1 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr52,fr52,fcc0,cc4,1 - test_fcc 0x8,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr52,fr56,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr52,fr60,fcc0,cc4,1 - test_fcc 0x1,0 - - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr0,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr4,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr8,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr12,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr16,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr20,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr24,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr28,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr32,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr36,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr40,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr44,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr48,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr52,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr56,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr60,fcc0,cc4,1 - test_fcc 0x1,0 - - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr0,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr4,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr8,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr12,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr16,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr20,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr24,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr28,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr32,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr36,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr40,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr44,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr48,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr52,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr56,fcc0,cc4,1 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr60,fcc0,cc4,1 - test_fcc 0x1,0 -; - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr0,fr0,fcc0,cc1,0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr4,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr8,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr12,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr16,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr20,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr24,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr28,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr32,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr36,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr40,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr44,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr48,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr52,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr0,fr56,fcc0,cc1,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr0,fr60,fcc0,cc1,0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr4,fr0,fcc0,cc1,0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr4,fr4,fcc0,cc1,0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr8,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr12,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr16,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr20,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr24,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr28,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr32,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr36,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr40,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr44,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr48,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr52,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr4,fr56,fcc0,cc1,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr4,fr60,fcc0,cc1,0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr8,fr0,fcc0,cc1,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr8,fr4,fcc0,cc1,0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr8,fr8,fcc0,cc1,0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr12,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr16,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr20,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr24,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr28,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr32,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr36,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr40,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr44,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr48,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr52,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr8,fr56,fcc0,cc1,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr8,fr60,fcc0,cc1,0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr0,fcc0,cc1,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr4,fcc0,cc1,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr8,fcc0,cc1,0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr12,fr12,fcc0,cc1,0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr16,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr20,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr24,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr28,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr32,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr36,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr40,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr44,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr48,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr52,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr12,fr56,fcc0,cc1,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr12,fr60,fcc0,cc1,0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr0,fcc0,cc1,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr4,fcc0,cc1,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr8,fcc0,cc1,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr12,fcc0,cc1,0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr16,fr16,fcc0,cc1,0 - test_fcc 0x8,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr16,fr20,fcc0,cc1,0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr24,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr28,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr32,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr36,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr40,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr44,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr48,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr52,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr16,fr56,fcc0,cc1,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr16,fr60,fcc0,cc1,0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr0,fcc0,cc1,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr4,fcc0,cc1,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr8,fcc0,cc1,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr12,fcc0,cc1,0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr20,fr16,fcc0,cc1,0 - test_fcc 0x8,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr20,fr20,fcc0,cc1,0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr24,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr28,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr32,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr36,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr40,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr44,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr48,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr52,fcc0,cc1,0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr20,fr56,fcc0,cc1,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr20,fr60,fcc0,cc1,0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr0,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr4,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr8,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr12,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr16,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr20,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr24,fr24,fcc0,cc5,0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr28,fcc0,cc5,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr32,fcc0,cc5,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr36,fcc0,cc5,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr40,fcc0,cc5,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr44,fcc0,cc5,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr48,fcc0,cc5,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr52,fcc0,cc5,0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr24,fr56,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr24,fr60,fcc0,cc5,0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr0,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr4,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr8,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr12,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr16,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr20,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr24,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr28,fr28,fcc0,cc5,0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr32,fcc0,cc5,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr36,fcc0,cc5,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr40,fcc0,cc5,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr44,fcc0,cc5,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr48,fcc0,cc5,0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr52,fcc0,cc5,0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr28,fr56,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr28,fr60,fcc0,cc5,0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr0,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr4,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr8,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr12,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr16,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr20,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr24,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr28,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr32,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr36,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr40,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr44,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr48,fr48,fcc0,cc5,0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr48,fr52,fcc0,cc5,0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr48,fr56,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr48,fr60,fcc0,cc5,0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr0,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr4,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr8,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr12,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr16,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr20,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr24,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr28,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr32,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr36,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr40,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr44,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr48,fcc0,cc5,0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr52,fr52,fcc0,cc5,0 - test_fcc 0x8,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr52,fr56,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr52,fr60,fcc0,cc5,0 - test_fcc 0x1,0 - - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr0,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr4,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr8,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr12,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr16,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr20,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr24,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr28,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr32,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr36,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr40,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr44,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr48,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr52,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr56,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr60,fcc0,cc5,0 - test_fcc 0x1,0 - - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr0,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr4,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr8,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr12,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr16,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr20,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr24,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr28,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr32,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr36,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr40,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr44,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr48,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr52,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr56,fcc0,cc5,0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr60,fcc0,cc5,0 - test_fcc 0x1,0 -; - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr0,fr0,fcc0,cc0,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr4,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr8,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr12,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr16,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr20,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr24,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr28,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr32,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr36,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr40,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr44,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr48,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr52,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr0,fr56,fcc0,cc0,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr0,fr60,fcc0,cc0,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr4,fr0,fcc0,cc0,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr4,fr4,fcc0,cc0,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr8,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr12,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr16,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr20,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr24,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr28,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr32,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr36,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr40,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr44,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr48,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr52,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr4,fr56,fcc0,cc0,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr4,fr60,fcc0,cc0,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr8,fr0,fcc0,cc0,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr8,fr4,fcc0,cc0,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr8,fr8,fcc0,cc0,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr12,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr16,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr20,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr24,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr28,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr32,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr36,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr40,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr44,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr48,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr52,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr8,fr56,fcc0,cc0,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr8,fr60,fcc0,cc0,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr0,fcc0,cc0,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr4,fcc0,cc0,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr8,fcc0,cc0,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr12,fr12,fcc0,cc0,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr16,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr20,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr24,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr28,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr32,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr36,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr40,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr44,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr48,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr52,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr12,fr56,fcc0,cc0,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr12,fr60,fcc0,cc0,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr0,fcc0,cc0,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr4,fcc0,cc0,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr8,fcc0,cc0,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr12,fcc0,cc0,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr16,fr16,fcc0,cc0,0 - test_fcc 0x7,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr16,fr20,fcc0,cc0,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr24,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr28,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr32,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr36,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr40,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr44,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr48,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr52,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr16,fr56,fcc0,cc0,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr16,fr60,fcc0,cc0,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr0,fcc0,cc0,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr4,fcc0,cc0,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr8,fcc0,cc0,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr12,fcc0,cc0,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr20,fr16,fcc0,cc0,0 - test_fcc 0x7,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr20,fr20,fcc0,cc0,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr24,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr28,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr32,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr36,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr40,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr44,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr48,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr52,fcc0,cc0,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr20,fr56,fcc0,cc0,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr20,fr60,fcc0,cc0,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr0,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr4,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr8,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr12,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr16,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr20,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr24,fr24,fcc0,cc4,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr28,fcc0,cc4,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr32,fcc0,cc4,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr36,fcc0,cc4,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr40,fcc0,cc4,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr44,fcc0,cc4,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr48,fcc0,cc4,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr52,fcc0,cc4,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr24,fr56,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr24,fr60,fcc0,cc4,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr0,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr4,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr8,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr12,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr16,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr20,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr24,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr28,fr28,fcc0,cc4,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr32,fcc0,cc4,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr36,fcc0,cc4,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr40,fcc0,cc4,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr44,fcc0,cc4,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr48,fcc0,cc4,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr52,fcc0,cc4,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr28,fr56,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr28,fr60,fcc0,cc4,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr0,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr4,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr8,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr12,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr16,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr20,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr24,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr28,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr32,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr36,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr40,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr44,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr48,fr48,fcc0,cc4,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr48,fr52,fcc0,cc4,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr48,fr56,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr48,fr60,fcc0,cc4,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr0,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr4,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr8,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr12,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr16,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr20,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr24,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr28,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr32,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr36,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr40,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr44,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr48,fcc0,cc4,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr52,fr52,fcc0,cc4,0 - test_fcc 0x7,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr52,fr56,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr52,fr60,fcc0,cc4,0 - test_fcc 0xe,0 - - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr0,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr4,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr8,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr12,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr16,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr20,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr24,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr28,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr32,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr36,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr40,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr44,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr48,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr52,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr56,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr60,fcc0,cc4,0 - test_fcc 0xe,0 - - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr0,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr4,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr8,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr12,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr16,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr20,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr24,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr28,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr32,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr36,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr40,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr44,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr48,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr52,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr56,fcc0,cc4,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr60,fcc0,cc4,0 - test_fcc 0xe,0 -; - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr0,fr0,fcc0,cc1,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr4,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr8,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr12,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr16,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr20,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr24,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr28,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr32,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr36,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr40,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr44,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr48,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr52,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr0,fr56,fcc0,cc1,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr0,fr60,fcc0,cc1,1 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr4,fr0,fcc0,cc1,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr4,fr4,fcc0,cc1,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr8,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr12,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr16,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr20,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr24,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr28,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr32,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr36,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr40,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr44,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr48,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr52,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr4,fr56,fcc0,cc1,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr4,fr60,fcc0,cc1,1 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr8,fr0,fcc0,cc1,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr8,fr4,fcc0,cc1,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr8,fr8,fcc0,cc1,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr12,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr16,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr20,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr24,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr28,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr32,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr36,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr40,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr44,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr48,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr52,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr8,fr56,fcc0,cc1,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr8,fr60,fcc0,cc1,1 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr0,fcc0,cc1,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr4,fcc0,cc1,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr8,fcc0,cc1,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr12,fr12,fcc0,cc1,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr16,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr20,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr24,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr28,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr32,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr36,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr40,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr44,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr48,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr52,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr12,fr56,fcc0,cc1,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr12,fr60,fcc0,cc1,1 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr0,fcc0,cc1,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr4,fcc0,cc1,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr8,fcc0,cc1,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr12,fcc0,cc1,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr16,fr16,fcc0,cc1,1 - test_fcc 0x7,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr16,fr20,fcc0,cc1,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr24,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr28,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr32,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr36,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr40,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr44,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr48,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr52,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr16,fr56,fcc0,cc1,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr16,fr60,fcc0,cc1,1 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr0,fcc0,cc1,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr4,fcc0,cc1,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr8,fcc0,cc1,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr12,fcc0,cc1,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr20,fr16,fcc0,cc1,1 - test_fcc 0x7,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr20,fr20,fcc0,cc1,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr24,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr28,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr32,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr36,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr40,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr44,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr48,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr52,fcc0,cc1,1 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr20,fr56,fcc0,cc1,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr20,fr60,fcc0,cc1,1 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr0,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr4,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr8,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr12,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr16,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr20,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr24,fr24,fcc0,cc5,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr28,fcc0,cc5,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr32,fcc0,cc5,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr36,fcc0,cc5,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr40,fcc0,cc5,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr44,fcc0,cc5,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr48,fcc0,cc5,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr52,fcc0,cc5,1 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr24,fr56,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr24,fr60,fcc0,cc5,1 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr0,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr4,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr8,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr12,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr16,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr20,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr24,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr28,fr28,fcc0,cc5,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr32,fcc0,cc5,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr36,fcc0,cc5,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr40,fcc0,cc5,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr44,fcc0,cc5,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr48,fcc0,cc5,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr52,fcc0,cc5,1 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr28,fr56,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr28,fr60,fcc0,cc5,1 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr0,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr4,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr8,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr12,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr16,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr20,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr24,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr28,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr32,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr36,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr40,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr44,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr48,fr48,fcc0,cc5,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr48,fr52,fcc0,cc5,1 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr48,fr56,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr48,fr60,fcc0,cc5,1 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr0,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr4,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr8,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr12,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr16,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr20,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr24,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr28,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr32,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr36,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr40,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr44,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr48,fcc0,cc5,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr52,fr52,fcc0,cc5,1 - test_fcc 0x7,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr52,fr56,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr52,fr60,fcc0,cc5,1 - test_fcc 0xe,0 - - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr0,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr4,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr8,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr12,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr16,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr20,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr24,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr28,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr32,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr36,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr40,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr44,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr48,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr52,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr56,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr60,fcc0,cc5,1 - test_fcc 0xe,0 - - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr0,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr4,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr8,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr12,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr16,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr20,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr24,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr28,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr32,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr36,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr40,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr44,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr48,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr52,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr56,fcc0,cc5,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr60,fcc0,cc5,1 - test_fcc 0xe,0 -; - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr0,fr0,fcc0,cc2,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr4,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr8,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr12,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr16,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr20,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr24,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr28,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr32,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr36,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr40,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr44,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr48,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr52,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr0,fr56,fcc0,cc2,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr0,fr60,fcc0,cc2,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr4,fr0,fcc0,cc2,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr4,fr4,fcc0,cc2,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr8,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr12,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr16,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr20,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr24,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr28,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr32,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr36,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr40,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr44,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr48,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr52,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr4,fr56,fcc0,cc2,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr4,fr60,fcc0,cc2,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr8,fr0,fcc0,cc2,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr8,fr4,fcc0,cc2,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr8,fr8,fcc0,cc2,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr12,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr16,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr20,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr24,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr28,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr32,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr36,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr40,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr44,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr48,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr52,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr8,fr56,fcc0,cc2,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr8,fr60,fcc0,cc2,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr0,fcc0,cc2,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr4,fcc0,cc2,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr8,fcc0,cc2,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr12,fr12,fcc0,cc2,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr16,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr20,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr24,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr28,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr32,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr36,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr40,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr44,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr48,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr52,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr12,fr56,fcc0,cc2,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr12,fr60,fcc0,cc2,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr0,fcc0,cc2,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr4,fcc0,cc2,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr8,fcc0,cc2,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr12,fcc0,cc2,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr16,fr16,fcc0,cc2,1 - test_fcc 0x7,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr16,fr20,fcc0,cc2,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr24,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr28,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr32,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr36,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr40,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr44,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr48,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr52,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr16,fr56,fcc0,cc2,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr16,fr60,fcc0,cc2,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr0,fcc0,cc2,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr4,fcc0,cc2,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr8,fcc0,cc2,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr12,fcc0,cc2,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr20,fr16,fcc0,cc2,1 - test_fcc 0x7,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr20,fr20,fcc0,cc2,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr24,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr28,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr32,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr36,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr40,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr44,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr48,fcc0,cc2,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr52,fcc0,cc2,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr20,fr56,fcc0,cc2,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr20,fr60,fcc0,cc2,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr0,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr4,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr8,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr12,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr16,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr20,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr24,fr24,fcc0,cc6,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr28,fcc0,cc6,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr32,fcc0,cc6,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr36,fcc0,cc6,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr40,fcc0,cc6,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr44,fcc0,cc6,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr48,fcc0,cc6,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr52,fcc0,cc6,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr24,fr56,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr24,fr60,fcc0,cc6,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr0,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr4,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr8,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr12,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr16,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr20,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr24,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr28,fr28,fcc0,cc6,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr32,fcc0,cc6,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr36,fcc0,cc6,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr40,fcc0,cc6,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr44,fcc0,cc6,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr48,fcc0,cc6,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr52,fcc0,cc6,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr28,fr56,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr28,fr60,fcc0,cc6,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr0,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr4,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr8,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr12,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr16,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr20,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr24,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr28,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr32,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr36,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr40,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr44,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr48,fr48,fcc0,cc6,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr48,fr52,fcc0,cc6,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr48,fr56,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr48,fr60,fcc0,cc6,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr0,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr4,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr8,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr12,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr16,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr20,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr24,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr28,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr32,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr36,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr40,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr44,fcc0,cc6,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr48,fcc0,cc6,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr52,fr52,fcc0,cc6,0 - test_fcc 0x7,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr52,fr56,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr52,fr60,fcc0,cc6,0 - test_fcc 0xe,0 - - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr0,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr4,fcc0,cc6,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr8,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr12,fcc0,cc6,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr16,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr20,fcc0,cc6,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr24,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr28,fcc0,cc6,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr32,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr36,fcc0,cc6,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr40,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr44,fcc0,cc6,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr48,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr52,fcc0,cc6,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr56,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr60,fcc0,cc6,0 - test_fcc 0xe,0 - - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr0,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr4,fcc0,cc6,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr8,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr12,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr16,fcc0,cc6,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr20,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr24,fcc0,cc6,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr28,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr32,fcc0,cc6,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr36,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr40,fcc0,cc6,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr44,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr48,fcc0,cc6,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr52,fcc0,cc6,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr56,fcc0,cc6,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr60,fcc0,cc6,1 - test_fcc 0xe,0 - - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr0,fr0,fcc0,cc3,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr4,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr8,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr12,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr16,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr20,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr24,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr28,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr32,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr36,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr40,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr44,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr48,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr0,fr52,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr0,fr56,fcc0,cc3,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr0,fr60,fcc0,cc3,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr4,fr0,fcc0,cc3,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr4,fr4,fcc0,cc3,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr8,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr12,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr16,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr20,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr24,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr28,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr32,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr36,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr40,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr44,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr48,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr4,fr52,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr4,fr56,fcc0,cc3,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr4,fr60,fcc0,cc3,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr8,fr0,fcc0,cc3,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr8,fr4,fcc0,cc3,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr8,fr8,fcc0,cc3,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr12,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr16,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr20,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr24,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr28,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr32,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr36,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr40,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr44,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr48,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr8,fr52,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr8,fr56,fcc0,cc3,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr8,fr60,fcc0,cc3,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr0,fcc0,cc3,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr4,fcc0,cc3,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr12,fr8,fcc0,cc3,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr12,fr12,fcc0,cc3,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr16,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr20,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr24,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr28,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr32,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr36,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr40,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr44,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr48,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr12,fr52,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr12,fr56,fcc0,cc3,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr12,fr60,fcc0,cc3,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr0,fcc0,cc3,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr4,fcc0,cc3,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr8,fcc0,cc3,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr16,fr12,fcc0,cc3,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr16,fr16,fcc0,cc3,1 - test_fcc 0x7,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr16,fr20,fcc0,cc3,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr24,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr28,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr32,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr36,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr40,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr44,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr48,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr16,fr52,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr16,fr56,fcc0,cc3,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr16,fr60,fcc0,cc3,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr0,fcc0,cc3,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr4,fcc0,cc3,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr8,fcc0,cc3,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr20,fr12,fcc0,cc3,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr20,fr16,fcc0,cc3,1 - test_fcc 0x7,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr20,fr20,fcc0,cc3,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr24,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr28,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr32,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr36,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr40,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr44,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr48,fcc0,cc3,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr20,fr52,fcc0,cc3,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr20,fr56,fcc0,cc3,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr20,fr60,fcc0,cc3,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr0,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr4,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr8,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr12,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr16,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr24,fr20,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr24,fr24,fcc0,cc7,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr28,fcc0,cc7,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr32,fcc0,cc7,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr36,fcc0,cc7,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr40,fcc0,cc7,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr44,fcc0,cc7,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr48,fcc0,cc7,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr24,fr52,fcc0,cc7,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr24,fr56,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr24,fr60,fcc0,cc7,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr0,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr4,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr8,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr12,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr16,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr20,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr28,fr24,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr28,fr28,fcc0,cc7,0 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr32,fcc0,cc7,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr36,fcc0,cc7,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr40,fcc0,cc7,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr44,fcc0,cc7,0 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr48,fcc0,cc7,1 - test_fcc 0xb,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr28,fr52,fcc0,cc7,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr28,fr56,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr28,fr60,fcc0,cc7,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr0,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr4,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr8,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr12,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr16,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr20,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr24,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr28,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr32,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr36,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr40,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr48,fr44,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr48,fr48,fcc0,cc7,1 - test_fcc 0x7,0 - set_fcc 0xb,0 ; Set mask opposite of expected - cfcmps fr48,fr52,fcc0,cc7,0 - test_fcc 0xb,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr48,fr56,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr48,fr60,fcc0,cc7,0 - test_fcc 0xe,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr0,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr4,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr8,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr12,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr16,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr20,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr24,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr28,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr32,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr36,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr40,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr44,fcc0,cc7,0 - test_fcc 0xd,0 - set_fcc 0xd,0 ; Set mask opposite of expected - cfcmps fr52,fr48,fcc0,cc7,1 - test_fcc 0xd,0 - set_fcc 0x7,0 ; Set mask opposite of expected - cfcmps fr52,fr52,fcc0,cc7,0 - test_fcc 0x7,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr52,fr56,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr52,fr60,fcc0,cc7,0 - test_fcc 0xe,0 - - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr0,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr4,fcc0,cc7,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr8,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr12,fcc0,cc7,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr16,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr20,fcc0,cc7,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr24,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr28,fcc0,cc7,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr32,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr36,fcc0,cc7,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr40,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr44,fcc0,cc7,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr48,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr52,fcc0,cc7,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr56,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr56,fr60,fcc0,cc7,0 - test_fcc 0xe,0 - - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr0,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr4,fcc0,cc7,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr8,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr12,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr16,fcc0,cc7,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr20,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr24,fcc0,cc7,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr28,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr32,fcc0,cc7,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr36,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr40,fcc0,cc7,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr44,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr48,fcc0,cc7,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr52,fcc0,cc7,1 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr56,fcc0,cc7,0 - test_fcc 0xe,0 - set_fcc 0xe,0 ; Set mask opposite of expected - cfcmps fr60,fr60,fcc0,cc7,1 - test_fcc 0xe,0 - - pass diff --git a/sim/testsuite/sim/frv/cfdivs.cgs b/sim/testsuite/sim/frv/cfdivs.cgs deleted file mode 100644 index e776f800ec3..00000000000 --- a/sim/testsuite/sim/frv/cfdivs.cgs +++ /dev/null @@ -1,696 +0,0 @@ -# frv testcase for cfdivs $FRi,$FRj,$FRk,$CCi,$cond -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global cfdivs -cfdivs: - set_spr_immed 0x1b1b,cccr - - cfdivs fr0,fr28,fr1,cc0,1 - test_fr_fr fr1,fr0 - cfdivs fr4,fr28,fr1,cc0,1 - test_fr_fr fr1,fr4 - cfdivs fr8,fr28,fr1,cc0,1 - test_fr_fr fr1,fr8 - cfdivs fr12,fr28,fr1,cc0,1 - test_fr_fr fr1,fr12 - cfdivs fr16,fr28,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr28,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr24,fr28,fr1,cc0,1 - test_fr_fr fr1,fr24 - cfdivs fr28,fr28,fr1,cc0,1 - test_fr_fr fr1,fr28 - cfdivs fr32,fr28,fr1,cc0,1 - test_fr_fr fr1,fr32 - cfdivs fr36,fr28,fr1,cc0,1 - test_fr_fr fr1,fr36 - cfdivs fr40,fr28,fr1,cc0,1 - test_fr_fr fr1,fr40 - cfdivs fr44,fr28,fr1,cc0,1 - test_fr_fr fr1,fr44 - cfdivs fr48,fr28,fr1,cc0,1 - test_fr_fr fr1,fr48 - cfdivs fr52,fr28,fr1,cc0,1 - test_fr_fr fr1,fr52 - - cfdivs fr16,fr0,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr4,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr8,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr12,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr24,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr28,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr32,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr36,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr40,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr44,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr48,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr52,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - cfdivs fr20,fr0,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr4,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr8,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr12,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr24,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr28,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr32,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr36,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr40,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr44,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr48,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr52,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - cfdivs fr8,fr28,fr1,cc4,1 - test_fr_fr fr1,fr8 - cfdivs fr28,fr8,fr1,cc4,1 - test_fr_fr fr1,fr8 - - cfdivs fr40,fr32,fr1,cc4,1 - test_fr_fr fr1,fr36 -; - cfdivs fr0,fr28,fr1,cc1,0 - test_fr_fr fr1,fr0 - cfdivs fr4,fr28,fr1,cc1,0 - test_fr_fr fr1,fr4 - cfdivs fr8,fr28,fr1,cc1,0 - test_fr_fr fr1,fr8 - cfdivs fr12,fr28,fr1,cc1,0 - test_fr_fr fr1,fr12 - cfdivs fr16,fr28,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr28,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr24,fr28,fr1,cc1,0 - test_fr_fr fr1,fr24 - cfdivs fr28,fr28,fr1,cc1,0 - test_fr_fr fr1,fr28 - cfdivs fr32,fr28,fr1,cc1,0 - test_fr_fr fr1,fr32 - cfdivs fr36,fr28,fr1,cc1,0 - test_fr_fr fr1,fr36 - cfdivs fr40,fr28,fr1,cc1,0 - test_fr_fr fr1,fr40 - cfdivs fr44,fr28,fr1,cc1,0 - test_fr_fr fr1,fr44 - cfdivs fr48,fr28,fr1,cc1,0 - test_fr_fr fr1,fr48 - cfdivs fr52,fr28,fr1,cc1,0 - test_fr_fr fr1,fr52 - - cfdivs fr16,fr0,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr4,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr8,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr12,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr24,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr28,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr32,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr36,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr40,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr44,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr48,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr16,fr52,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - cfdivs fr20,fr0,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr4,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr8,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr12,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr24,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr28,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr32,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr36,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr40,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr44,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr48,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfdivs fr20,fr52,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - cfdivs fr8,fr28,fr1,cc5,0 - test_fr_fr fr1,fr8 - cfdivs fr28,fr8,fr1,cc5,0 - test_fr_fr fr1,fr8 - - cfdivs fr40,fr32,fr1,cc5,0 - test_fr_fr fr1,fr36 -; - set_fr_iimmed 0xdead,0xbeef,fr1 - cfdivs fr0,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr4,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr8,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr12,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr24,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr28,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr32,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr36,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr40,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr44,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr48,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr52,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfdivs fr16,fr0,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr4,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr8,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr12,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr24,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr32,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr36,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr40,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr44,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr48,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr52,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfdivs fr20,fr0,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr4,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr8,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr12,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr24,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr28,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr32,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr36,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr40,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr44,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr48,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr52,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfdivs fr8,fr28,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr28,fr8,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfdivs fr40,fr32,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 -; - set_fr_iimmed 0xdead,0xbeef,fr1 - cfdivs fr0,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr4,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr8,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr12,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr24,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr28,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr32,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr36,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr40,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr44,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr48,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr52,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfdivs fr16,fr0,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr4,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr8,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr12,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr24,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr32,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr36,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr40,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr44,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr48,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr52,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfdivs fr20,fr0,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr4,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr8,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr12,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr24,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr28,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr32,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr36,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr40,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr44,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr48,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr52,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfdivs fr8,fr28,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr28,fr8,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfdivs fr40,fr32,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 -; - set_fr_iimmed 0xdead,0xbeef,fr1 - cfdivs fr0,fr28,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr4,fr28,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr8,fr28,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr12,fr28,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr28,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr28,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr24,fr28,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr28,fr28,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr32,fr28,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr36,fr28,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr40,fr28,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr44,fr28,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr48,fr28,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr52,fr28,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfdivs fr16,fr0,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr4,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr8,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr12,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr24,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr28,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr32,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr36,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr40,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr44,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr48,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr52,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfdivs fr20,fr0,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr4,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr8,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr12,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr24,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr28,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr32,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr36,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr40,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr44,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr48,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr52,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfdivs fr8,fr28,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr28,fr8,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfdivs fr40,fr32,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 -; - set_fr_iimmed 0xdead,0xbeef,fr1 - cfdivs fr0,fr28,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr4,fr28,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr8,fr28,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr12,fr28,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr28,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr28,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr24,fr28,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr28,fr28,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr32,fr28,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr36,fr28,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr40,fr28,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr44,fr28,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr48,fr28,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr52,fr28,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfdivs fr16,fr0,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr4,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr8,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr12,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr24,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr28,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr32,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr36,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr40,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr44,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr48,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr16,fr52,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfdivs fr20,fr0,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr4,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr8,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr12,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr24,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr28,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr32,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr36,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr40,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr44,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr48,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr20,fr52,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfdivs fr8,fr28,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfdivs fr28,fr8,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfdivs fr40,fr32,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - - pass diff --git a/sim/testsuite/sim/frv/cfitos.cgs b/sim/testsuite/sim/frv/cfitos.cgs deleted file mode 100644 index b24184e65c0..00000000000 --- a/sim/testsuite/sim/frv/cfitos.cgs +++ /dev/null @@ -1,88 +0,0 @@ -# frv testcase for cfitos $FRj,$FRk,$CCi,$cond -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global cfitos -cfitos: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0,0,fr1 - cfitos fr1,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - set_fr_iimmed 0x0000,0x0002,fr1 - cfitos fr1,fr1,cc0,1 - test_fr_fr fr1,fr32 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfitos fr1,fr1,cc4,1 - test_fr_iimmed 0xce054904,fr1 - - set_fr_iimmed 0,0,fr1 - cfitos fr1,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - set_fr_iimmed 0x0000,0x0002,fr1 - cfitos fr1,fr1,cc1,0 - test_fr_fr fr1,fr32 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfitos fr1,fr1,cc5,0 - test_fr_iimmed 0xce054904,fr1 - - set_fr_iimmed 0,0,fr1 - cfitos fr1,fr1,cc0,0 - test_fr_iimmed 0,fr1 - - set_fr_iimmed 0x0000,0x0002,fr1 - cfitos fr1,fr1,cc0,0 - test_fr_iimmed 0x00000002,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfitos fr1,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - - set_fr_iimmed 0,0,fr1 - cfitos fr1,fr1,cc1,1 - test_fr_iimmed 0,fr1 - - set_fr_iimmed 0x0000,0x0002,fr1 - cfitos fr1,fr1,cc1,1 - test_fr_iimmed 0x00000002,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfitos fr1,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - - set_fr_iimmed 0,0,fr1 - cfitos fr1,fr1,cc2,1 - test_fr_iimmed 0,fr1 - - set_fr_iimmed 0x0000,0x0002,fr1 - cfitos fr1,fr1,cc2,0 - test_fr_iimmed 0x00000002,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfitos fr1,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - - set_fr_iimmed 0,0,fr1 - cfitos fr1,fr1,cc3,0 - test_fr_iimmed 0,fr1 - - set_fr_iimmed 0x0000,0x0002,fr1 - cfitos fr1,fr1,cc3,1 - test_fr_iimmed 0x00000002,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfitos fr1,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - - pass diff --git a/sim/testsuite/sim/frv/cfmadds.cgs b/sim/testsuite/sim/frv/cfmadds.cgs deleted file mode 100644 index a30f7bfd87d..00000000000 --- a/sim/testsuite/sim/frv/cfmadds.cgs +++ /dev/null @@ -1,627 +0,0 @@ -# frv testcase for cfmadds $GRi,$GRj,$GRk,$CCi,$cond -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global cfmadds -cfmadds: - set_spr_immed 0x1b1b,cccr - - set_fr_fr fr16,fr1 - cfmadds fr16,fr4,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr8,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr12,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr16,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr20,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr24,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr28,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr32,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr36,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr40,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr44,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr48,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - cfmadds fr20,fr4,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr8,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr12,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr16,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr20,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr24,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr28,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr32,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr36,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr40,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr44,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr48,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - set_fr_fr fr16,fr1 - cfmadds fr28,fr0,fr1,cc4,1 - test_fr_fr fr1,fr0 - set_fr_fr fr16,fr1 - cfmadds fr28,fr4,fr1,cc4,1 - test_fr_fr fr1,fr4 - set_fr_fr fr16,fr1 - cfmadds fr28,fr8,fr1,cc4,1 - test_fr_fr fr1,fr8 - set_fr_fr fr16,fr1 - cfmadds fr28,fr12,fr1,cc4,1 - test_fr_fr fr1,fr12 - set_fr_fr fr16,fr1 - cfmadds fr28,fr16,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - set_fr_fr fr16,fr1 - cfmadds fr28,fr20,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - set_fr_fr fr16,fr1 - cfmadds fr28,fr24,fr1,cc4,1 - test_fr_fr fr1,fr24 - set_fr_fr fr16,fr1 - cfmadds fr28,fr28,fr1,cc4,1 - test_fr_fr fr1,fr28 - set_fr_fr fr16,fr1 - cfmadds fr28,fr32,fr1,cc4,1 - test_fr_fr fr1,fr32 - set_fr_fr fr16,fr1 - cfmadds fr28,fr36,fr1,cc4,1 - test_fr_fr fr1,fr36 - set_fr_fr fr16,fr1 - cfmadds fr28,fr40,fr1,cc4,1 - test_fr_fr fr1,fr40 - set_fr_fr fr16,fr1 - cfmadds fr28,fr44,fr1,cc4,1 - test_fr_fr fr1,fr44 - set_fr_fr fr16,fr1 - cfmadds fr28,fr48,fr1,cc4,1 - test_fr_fr fr1,fr48 - set_fr_fr fr16,fr1 - cfmadds fr28,fr52,fr1,cc4,1 - test_fr_fr fr1,fr52 - - set_fr_fr fr36,fr1 - cfmadds fr28,fr8,fr1,cc4,1 - test_fr_fr fr1,fr32 - cfmadds fr8,fr28,fr1,cc4,1 - test_fr_fr fr1,fr28 - - set_fr_fr fr36,fr1 - cfmadds fr32,fr36,fr1,cc4,1 - test_fr_fr fr1,fr44 -; - set_fr_fr fr16,fr1 - cfmadds fr16,fr4,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr8,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr12,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr16,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr20,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr24,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr28,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr32,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr36,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr40,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr44,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr16,fr48,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - cfmadds fr20,fr4,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr8,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr12,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr16,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr20,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr24,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr28,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr32,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr36,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr40,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr44,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmadds fr20,fr48,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - set_fr_fr fr16,fr1 - cfmadds fr28,fr0,fr1,cc5,0 - test_fr_fr fr1,fr0 - set_fr_fr fr16,fr1 - cfmadds fr28,fr4,fr1,cc5,0 - test_fr_fr fr1,fr4 - set_fr_fr fr16,fr1 - cfmadds fr28,fr8,fr1,cc5,0 - test_fr_fr fr1,fr8 - set_fr_fr fr16,fr1 - cfmadds fr28,fr12,fr1,cc5,0 - test_fr_fr fr1,fr12 - set_fr_fr fr16,fr1 - cfmadds fr28,fr16,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - set_fr_fr fr16,fr1 - cfmadds fr28,fr20,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - set_fr_fr fr16,fr1 - cfmadds fr28,fr24,fr1,cc5,0 - test_fr_fr fr1,fr24 - set_fr_fr fr16,fr1 - cfmadds fr28,fr28,fr1,cc5,0 - test_fr_fr fr1,fr28 - set_fr_fr fr16,fr1 - cfmadds fr28,fr32,fr1,cc5,0 - test_fr_fr fr1,fr32 - set_fr_fr fr16,fr1 - cfmadds fr28,fr36,fr1,cc5,0 - test_fr_fr fr1,fr36 - set_fr_fr fr16,fr1 - cfmadds fr28,fr40,fr1,cc5,0 - test_fr_fr fr1,fr40 - set_fr_fr fr16,fr1 - cfmadds fr28,fr44,fr1,cc5,0 - test_fr_fr fr1,fr44 - set_fr_fr fr16,fr1 - cfmadds fr28,fr48,fr1,cc5,0 - test_fr_fr fr1,fr48 - set_fr_fr fr16,fr1 - cfmadds fr28,fr52,fr1,cc5,0 - test_fr_fr fr1,fr52 - - set_fr_fr fr36,fr1 - cfmadds fr28,fr8,fr1,cc5,0 - test_fr_fr fr1,fr32 - cfmadds fr8,fr28,fr1,cc5,0 - test_fr_fr fr1,fr28 - - set_fr_fr fr36,fr1 - cfmadds fr32,fr36,fr1,cc5,0 - test_fr_fr fr1,fr44 -; - set_fr_fr fr48,fr1 - cfmadds fr16,fr4,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr8,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr12,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr16,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr20,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr24,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr28,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr32,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr36,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr40,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr44,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr48,fr1,cc0,0 - test_fr_fr fr1,fr48 - - cfmadds fr20,fr4,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr8,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr12,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr16,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr20,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr24,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr28,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr32,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr36,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr40,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr44,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr48,fr1,cc4,0 - test_fr_fr fr1,fr48 - - cfmadds fr28,fr0,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr4,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr8,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr12,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr16,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr20,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr24,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr28,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr32,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr36,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr40,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr44,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr48,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr52,fr1,cc4,0 - test_fr_fr fr1,fr48 - - cfmadds fr28,fr8,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmadds fr8,fr28,fr1,cc4,0 - test_fr_fr fr1,fr48 - - cfmadds fr32,fr36,fr1,cc4,0 - test_fr_fr fr1,fr48 -; - set_fr_fr fr48,fr1 - cfmadds fr16,fr4,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr8,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr12,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr16,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr20,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr24,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr28,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr32,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr36,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr40,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr44,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr48,fr1,cc1,1 - test_fr_fr fr1,fr48 - - cfmadds fr20,fr4,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr8,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr12,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr16,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr20,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr24,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr28,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr32,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr36,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr40,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr44,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr48,fr1,cc5,1 - test_fr_fr fr1,fr48 - - cfmadds fr28,fr0,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr4,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr8,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr12,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr16,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr20,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr24,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr28,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr32,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr36,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr40,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr44,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr48,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr52,fr1,cc5,1 - test_fr_fr fr1,fr48 - - cfmadds fr28,fr8,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmadds fr8,fr28,fr1,cc5,1 - test_fr_fr fr1,fr48 - - cfmadds fr32,fr36,fr1,cc5,1 - test_fr_fr fr1,fr48 -; - set_fr_fr fr48,fr1 - cfmadds fr16,fr4,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr8,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr12,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr16,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr20,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr24,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr28,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr32,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr36,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr40,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr44,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr48,fr1,cc2,0 - test_fr_fr fr1,fr48 - - cfmadds fr20,fr4,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr8,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr12,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr16,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr20,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr24,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr28,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr32,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr36,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr40,fr1,cc6,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr44,fr1,cc6,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr48,fr1,cc6,0 - test_fr_fr fr1,fr48 - - cfmadds fr28,fr0,fr1,cc6,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr4,fr1,cc6,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr8,fr1,cc6,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr12,fr1,cc6,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr16,fr1,cc6,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr20,fr1,cc6,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr24,fr1,cc6,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr28,fr1,cc6,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr32,fr1,cc6,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr36,fr1,cc6,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr40,fr1,cc6,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr44,fr1,cc6,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr48,fr1,cc6,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr52,fr1,cc6,0 - test_fr_fr fr1,fr48 - - cfmadds fr28,fr8,fr1,cc6,1 - test_fr_fr fr1,fr48 - cfmadds fr8,fr28,fr1,cc6,0 - test_fr_fr fr1,fr48 - - cfmadds fr32,fr36,fr1,cc6,1 - test_fr_fr fr1,fr48 -; - set_fr_fr fr48,fr1 - cfmadds fr16,fr4,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr8,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr12,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr16,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr20,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr24,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr28,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr32,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr36,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr40,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmadds fr16,fr44,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmadds fr16,fr48,fr1,cc3,0 - test_fr_fr fr1,fr48 - - cfmadds fr20,fr4,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr8,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr12,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr16,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr20,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr24,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr28,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr32,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr36,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr40,fr1,cc7,0 - test_fr_fr fr1,fr48 - cfmadds fr20,fr44,fr1,cc7,1 - test_fr_fr fr1,fr48 - cfmadds fr20,fr48,fr1,cc7,0 - test_fr_fr fr1,fr48 - - cfmadds fr28,fr0,fr1,cc7,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr4,fr1,cc7,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr8,fr1,cc7,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr12,fr1,cc7,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr16,fr1,cc7,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr20,fr1,cc7,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr24,fr1,cc7,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr28,fr1,cc7,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr32,fr1,cc7,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr36,fr1,cc7,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr40,fr1,cc7,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr44,fr1,cc7,0 - test_fr_fr fr1,fr48 - cfmadds fr28,fr48,fr1,cc7,1 - test_fr_fr fr1,fr48 - cfmadds fr28,fr52,fr1,cc7,0 - test_fr_fr fr1,fr48 - - cfmadds fr28,fr8,fr1,cc7,1 - test_fr_fr fr1,fr48 - cfmadds fr8,fr28,fr1,cc7,0 - test_fr_fr fr1,fr48 - - cfmadds fr32,fr36,fr1,cc7,1 - test_fr_fr fr1,fr48 -; - pass diff --git a/sim/testsuite/sim/frv/cfmas.cgs b/sim/testsuite/sim/frv/cfmas.cgs deleted file mode 100644 index 8c0dc05f65d..00000000000 --- a/sim/testsuite/sim/frv/cfmas.cgs +++ /dev/null @@ -1,775 +0,0 @@ -# frv testcase for cfmas $FRi,$FRj,$FRk,$CCi,$cond -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global cfmas -cfmas: - set_spr_immed 0x1b1b,cccr - - cfmas fr16,fr4,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr4 - cfmas fr16,fr8,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - cfmas fr16,fr12,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr12 - cfmas fr16,fr16,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmas fr16,fr20,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmas fr16,fr24,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr24 - cfmas fr16,fr28,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - cfmas fr16,fr32,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr32 - cfmas fr16,fr36,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr36 - cfmas fr16,fr40,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr40 - cfmas fr16,fr44,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr44 - cfmas fr16,fr48,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr48 - - cfmas fr20,fr4,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr4 - cfmas fr20,fr8,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - cfmas fr20,fr12,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr12 - cfmas fr20,fr16,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmas fr20,fr20,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmas fr20,fr24,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr24 - cfmas fr20,fr28,fr2,cc4,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - cfmas fr20,fr32,fr2,cc4,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr32 - cfmas fr20,fr36,fr2,cc4,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr36 - cfmas fr20,fr40,fr2,cc4,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr40 - cfmas fr20,fr44,fr2,cc4,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr44 - cfmas fr20,fr48,fr2,cc4,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr48 - - cfmas fr28,fr0,fr2,cc4,1 - test_fr_fr fr2,fr0 - cfmas fr28,fr4,fr2,cc4,1 - test_fr_fr fr2,fr4 - cfmas fr28,fr8,fr2,cc4,1 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmas fr28,fr12,fr2,cc4,1 - test_fr_fr fr2,fr12 - cfmas fr28,fr16,fr2,cc4,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmas fr28,fr20,fr2,cc4,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmas fr28,fr24,fr2,cc4,1 - test_fr_fr fr2,fr24 - cfmas fr28,fr28,fr2,cc4,1 - test_fr_fr fr2,fr28 - cfmas fr28,fr32,fr2,cc4,1 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr36 - cfmas fr28,fr36,fr2,cc4,1 - test_fr_fr fr2,fr36 - cfmas fr28,fr40,fr2,cc4,1 - test_fr_fr fr2,fr40 - cfmas fr28,fr44,fr2,cc4,1 - test_fr_fr fr2,fr44 - cfmas fr28,fr48,fr2,cc4,1 - test_fr_fr fr2,fr48 - cfmas fr28,fr52,fr2,cc4,1 - test_fr_fr fr2,fr52 - - cfmas fr28,fr8,fr2,cc4,1 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmas fr8,fr28,fr2,cc4,1 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - - cfmas fr32,fr36,fr2,cc4,1 - test_fr_fr fr2,fr40 -; - cfmas fr16,fr4,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr4 - cfmas fr16,fr8,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - cfmas fr16,fr12,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr12 - cfmas fr16,fr16,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmas fr16,fr20,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmas fr16,fr24,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr24 - cfmas fr16,fr28,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - cfmas fr16,fr32,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr32 - cfmas fr16,fr36,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr36 - cfmas fr16,fr40,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr40 - cfmas fr16,fr44,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr44 - cfmas fr16,fr48,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr48 - - cfmas fr20,fr4,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr4 - cfmas fr20,fr8,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - cfmas fr20,fr12,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr12 - cfmas fr20,fr16,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmas fr20,fr20,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmas fr20,fr24,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr24 - cfmas fr20,fr28,fr2,cc5,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - cfmas fr20,fr32,fr2,cc5,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr32 - cfmas fr20,fr36,fr2,cc5,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr36 - cfmas fr20,fr40,fr2,cc5,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr40 - cfmas fr20,fr44,fr2,cc5,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr44 - cfmas fr20,fr48,fr2,cc5,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr48 - - cfmas fr28,fr0,fr2,cc5,0 - test_fr_fr fr2,fr0 - cfmas fr28,fr4,fr2,cc5,0 - test_fr_fr fr2,fr4 - cfmas fr28,fr8,fr2,cc5,0 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmas fr28,fr12,fr2,cc5,0 - test_fr_fr fr2,fr12 - cfmas fr28,fr16,fr2,cc5,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmas fr28,fr20,fr2,cc5,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmas fr28,fr24,fr2,cc5,0 - test_fr_fr fr2,fr24 - cfmas fr28,fr28,fr2,cc5,0 - test_fr_fr fr2,fr28 - cfmas fr28,fr32,fr2,cc5,0 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr36 - cfmas fr28,fr36,fr2,cc5,0 - test_fr_fr fr2,fr36 - cfmas fr28,fr40,fr2,cc5,0 - test_fr_fr fr2,fr40 - cfmas fr28,fr44,fr2,cc5,0 - test_fr_fr fr2,fr44 - cfmas fr28,fr48,fr2,cc5,0 - test_fr_fr fr2,fr48 - cfmas fr28,fr52,fr2,cc5,0 - test_fr_fr fr2,fr52 - - cfmas fr28,fr8,fr2,cc5,0 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmas fr8,fr28,fr2,cc5,0 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - - cfmas fr32,fr36,fr2,cc5,0 - test_fr_fr fr2,fr40 -; - set_fr_iimmed 0x1111,0x1111,fr2 - set_fr_iimmed 0x2222,0x2222,fr3 - cfmas fr16,fr4,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr8,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr12,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr16,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr20,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr24,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr28,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr32,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr36,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr40,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr44,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr48,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - - cfmas fr20,fr4,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr8,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr12,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr16,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr20,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr24,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr20,fr28,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr32,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr36,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr40,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr44,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr48,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - - cfmas fr28,fr0,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr4,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr8,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr28,fr12,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr16,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr20,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr24,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr28,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr32,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr28,fr36,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr40,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr44,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr48,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr52,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - - cfmas fr28,fr8,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr8,fr28,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - - cfmas fr32,fr36,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 -; - set_fr_iimmed 0x1111,0x1111,fr2 - set_fr_iimmed 0x2222,0x2222,fr3 - cfmas fr16,fr4,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr8,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr12,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr16,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr20,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr24,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr28,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr32,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr36,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr40,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr44,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr48,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - - cfmas fr20,fr4,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr8,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr12,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr16,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr20,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr24,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr20,fr28,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr32,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr36,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr40,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr44,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr48,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - - cfmas fr28,fr0,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr4,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr8,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr28,fr12,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr16,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr20,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr24,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr28,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr32,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr28,fr36,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr40,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr44,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr48,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr52,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - - cfmas fr28,fr8,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr8,fr28,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - - cfmas fr32,fr36,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 -; - set_fr_iimmed 0x1111,0x1111,fr2 - set_fr_iimmed 0x2222,0x2222,fr3 - cfmas fr16,fr4,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr8,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr12,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr16,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr20,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr24,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr28,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr32,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr36,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr40,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr44,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr48,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - - cfmas fr20,fr4,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr8,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr12,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr16,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr20,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr24,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr20,fr28,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr32,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr36,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr40,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr44,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr48,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - - cfmas fr28,fr0,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr4,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr8,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr28,fr12,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr16,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr20,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr24,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr28,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr32,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr28,fr36,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr40,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr44,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr48,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr52,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - - cfmas fr28,fr8,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr8,fr28,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - - cfmas fr32,fr36,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 -; - set_fr_iimmed 0x1111,0x1111,fr2 - set_fr_iimmed 0x2222,0x2222,fr3 - cfmas fr16,fr4,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr8,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr12,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr16,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr20,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr24,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr28,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr32,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr36,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr40,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr44,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr16,fr48,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - - cfmas fr20,fr4,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr8,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr12,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr16,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr20,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr24,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr20,fr28,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr32,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr36,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr40,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr44,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr20,fr48,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - - cfmas fr28,fr0,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr4,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr8,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr28,fr12,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr16,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr20,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr24,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr28,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr32,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr28,fr36,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr40,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr44,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr48,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - cfmas fr28,fr52,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - - cfmas fr28,fr8,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmas fr8,fr28,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - - cfmas fr32,fr36,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - - pass diff --git a/sim/testsuite/sim/frv/cfmovs.cgs b/sim/testsuite/sim/frv/cfmovs.cgs deleted file mode 100644 index 310bac36541..00000000000 --- a/sim/testsuite/sim/frv/cfmovs.cgs +++ /dev/null @@ -1,216 +0,0 @@ -# frv testcase for cfmovs $FRj,$FRk,$CCi,$cond -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global cfmovs -cfmovs: - set_spr_immed 0x1b1b,cccr - - cfmovs fr0,fr1,cc0,1 - test_fr_fr fr0,fr1 - cfmovs fr4,fr1,cc0,1 - test_fr_fr fr4,fr1 - cfmovs fr8,fr1,cc0,1 - test_fr_fr fr8,fr1 - cfmovs fr12,fr1,cc0,1 - test_fr_fr fr12,fr1 - cfmovs fr16,fr1,cc0,1 - test_fr_fr fr16,fr1 - cfmovs fr20,fr1,cc0,1 - test_fr_fr fr20,fr1 - cfmovs fr24,fr1,cc0,1 - test_fr_fr fr24,fr1 - cfmovs fr28,fr1,cc0,1 - test_fr_fr fr28,fr1 - cfmovs fr32,fr1,cc4,1 - test_fr_fr fr32,fr1 - cfmovs fr36,fr1,cc4,1 - test_fr_fr fr36,fr1 - cfmovs fr40,fr1,cc4,1 - test_fr_fr fr40,fr1 - cfmovs fr44,fr1,cc4,1 - test_fr_fr fr44,fr1 - cfmovs fr48,fr1,cc4,1 - test_fr_fr fr48,fr1 - cfmovs fr52,fr1,cc4,1 - test_fr_fr fr52,fr1 - cfmovs fr56,fr1,cc4,1 - test_fr_iimmed 0x7fc00000,fr1 - cfmovs fr60,fr1,cc4,1 - test_fr_iimmed 0x7f800001,fr1 - - cfmovs fr0,fr1,cc1,0 - test_fr_fr fr0,fr1 - cfmovs fr4,fr1,cc1,0 - test_fr_fr fr4,fr1 - cfmovs fr8,fr1,cc1,0 - test_fr_fr fr8,fr1 - cfmovs fr12,fr1,cc1,0 - test_fr_fr fr12,fr1 - cfmovs fr16,fr1,cc1,0 - test_fr_fr fr16,fr1 - cfmovs fr20,fr1,cc1,0 - test_fr_fr fr20,fr1 - cfmovs fr24,fr1,cc1,0 - test_fr_fr fr24,fr1 - cfmovs fr28,fr1,cc1,0 - test_fr_fr fr28,fr1 - cfmovs fr32,fr1,cc5,0 - test_fr_fr fr32,fr1 - cfmovs fr36,fr1,cc5,0 - test_fr_fr fr36,fr1 - cfmovs fr40,fr1,cc5,0 - test_fr_fr fr40,fr1 - cfmovs fr44,fr1,cc5,0 - test_fr_fr fr44,fr1 - cfmovs fr48,fr1,cc5,0 - test_fr_fr fr48,fr1 - cfmovs fr52,fr1,cc5,0 - test_fr_fr fr52,fr1 - cfmovs fr56,fr1,cc5,0 - test_fr_iimmed 0x7fc00000,fr1 - cfmovs fr60,fr1,cc5,0 - test_fr_iimmed 0x7f800001,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfmovs fr0,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr4,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr8,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr12,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr20,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr24,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr32,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr36,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr40,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr44,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr48,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr52,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr56,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr60,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfmovs fr0,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr4,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr8,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr12,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr20,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr24,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr32,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr36,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr40,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr44,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr48,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr52,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr56,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr60,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfmovs fr0,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr4,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr8,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr12,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr16,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr20,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr24,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr28,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr32,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr36,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr40,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr44,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr48,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr52,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr56,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr60,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfmovs fr0,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr4,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr8,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr12,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr16,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr20,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr24,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr28,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr32,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr36,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr40,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr44,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr48,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr52,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr56,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmovs fr60,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - - pass diff --git a/sim/testsuite/sim/frv/cfmss.cgs b/sim/testsuite/sim/frv/cfmss.cgs deleted file mode 100644 index c31fba3bfba..00000000000 --- a/sim/testsuite/sim/frv/cfmss.cgs +++ /dev/null @@ -1,697 +0,0 @@ -# frv testcase for cfmss $FRi,$FRj,$FRk,$CCi,$cond -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global cfmss -cfmss: - set_spr_immed 0x1b1b,cccr - - cfmss fr16,fr4,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr16,fr8,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - cfmss fr16,fr12,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr16,fr16,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmss fr16,fr20,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmss fr16,fr24,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr16,fr28,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - cfmss fr16,fr32,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr16,fr36,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr16,fr40,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr16,fr44,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr16,fr48,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - - cfmss fr20,fr4,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr20,fr8,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - cfmss fr20,fr12,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr20,fr16,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmss fr20,fr20,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmss fr20,fr24,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr20,fr28,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - cfmss fr20,fr32,fr2,cc0,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr20,fr36,fr2,cc4,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr20,fr40,fr2,cc4,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr20,fr44,fr2,cc4,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr20,fr48,fr2,cc4,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - - cfmss fr28,fr0,fr2,cc4,1 - test_fr_fr fr2,fr0 - cfmss fr28,fr4,fr2,cc4,1 - test_fr_fr fr2,fr4 - cfmss fr28,fr8,fr2,cc4,1 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr32 - cfmss fr28,fr12,fr2,cc4,1 - test_fr_fr fr2,fr12 - cfmss fr28,fr16,fr2,cc4,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - cfmss fr28,fr20,fr2,cc4,1 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - cfmss fr28,fr24,fr2,cc4,1 - test_fr_fr fr2,fr24 - cfmss fr28,fr28,fr2,cc4,1 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr20 - test_fr_fr fr3,fr16 - cfmss fr28,fr32,fr2,cc4,1 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr8 - cfmss fr28,fr36,fr2,cc4,1 - test_fr_fr fr2,fr36 - cfmss fr28,fr40,fr2,cc4,1 - test_fr_fr fr2,fr40 - cfmss fr28,fr44,fr2,cc4,1 - test_fr_fr fr2,fr44 - cfmss fr28,fr48,fr2,cc4,1 - test_fr_fr fr2,fr48 - cfmss fr28,fr52,fr2,cc4,1 - test_fr_fr fr2,fr52 - - cfmss fr28,fr8,fr2,cc4,1 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr32 - cfmss fr8,fr28,fr2,cc4,1 - test_fr_fr fr2,fr8 - - cfmss fr32,fr36,fr2,cc4,1 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr8 -; - cfmss fr16,fr4,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr16,fr8,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - cfmss fr16,fr12,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr16,fr16,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmss fr16,fr20,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmss fr16,fr24,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr16,fr28,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - cfmss fr16,fr32,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr16,fr36,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr16,fr40,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr16,fr44,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr16,fr48,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - - cfmss fr20,fr4,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr20,fr8,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - cfmss fr20,fr12,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr20,fr16,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmss fr20,fr20,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - cfmss fr20,fr24,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr20,fr28,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - cfmss fr20,fr32,fr2,cc1,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr20,fr36,fr2,cc5,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr20,fr40,fr2,cc5,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr20,fr44,fr2,cc5,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - cfmss fr20,fr48,fr2,cc5,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - - cfmss fr28,fr0,fr2,cc5,0 - test_fr_fr fr2,fr0 - cfmss fr28,fr4,fr2,cc5,0 - test_fr_fr fr2,fr4 - cfmss fr28,fr8,fr2,cc5,0 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr32 - cfmss fr28,fr12,fr2,cc5,0 - test_fr_fr fr2,fr12 - cfmss fr28,fr16,fr2,cc5,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - cfmss fr28,fr20,fr2,cc5,0 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - cfmss fr28,fr24,fr2,cc5,0 - test_fr_fr fr2,fr24 - cfmss fr28,fr28,fr2,cc5,0 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr20 - test_fr_fr fr3,fr16 - cfmss fr28,fr32,fr2,cc5,0 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr8 - cfmss fr28,fr36,fr2,cc5,0 - test_fr_fr fr2,fr36 - cfmss fr28,fr40,fr2,cc5,0 - test_fr_fr fr2,fr40 - cfmss fr28,fr44,fr2,cc5,0 - test_fr_fr fr2,fr44 - cfmss fr28,fr48,fr2,cc5,0 - test_fr_fr fr2,fr48 - cfmss fr28,fr52,fr2,cc5,0 - test_fr_fr fr2,fr52 - - cfmss fr28,fr8,fr2,cc5,0 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr32 - cfmss fr8,fr28,fr2,cc5,0 - test_fr_fr fr2,fr8 - - cfmss fr32,fr36,fr2,cc5,0 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr8 -; - set_fr_iimmed 0x1111,0x1111,fr2 - set_fr_iimmed 0x2222,0x2222,fr3 - cfmss fr16,fr4,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr8,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr16,fr12,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr16,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr16,fr20,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr16,fr24,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr28,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr16,fr32,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr36,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr40,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr44,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr48,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - - cfmss fr20,fr4,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr8,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr20,fr12,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr16,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr20,fr20,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr20,fr24,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr28,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr20,fr32,fr2,cc0,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr36,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr40,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr44,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr48,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - - cfmss fr28,fr0,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr4,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr8,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr12,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr16,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr20,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr24,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr28,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr32,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr36,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr40,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr44,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr48,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr52,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - - cfmss fr28,fr8,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr8,fr28,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - - cfmss fr32,fr36,fr2,cc4,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 -; - set_fr_iimmed 0x1111,0x1111,fr2 - set_fr_iimmed 0x2222,0x2222,fr3 - cfmss fr16,fr4,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr8,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr16,fr12,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr16,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr16,fr20,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr16,fr24,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr28,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr16,fr32,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr36,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr40,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr44,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr48,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - - cfmss fr20,fr4,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr8,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr20,fr12,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr16,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr20,fr20,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr20,fr24,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr28,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr20,fr32,fr2,cc1,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr36,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr40,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr44,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr48,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - - cfmss fr28,fr0,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr4,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr8,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr12,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr16,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr20,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr24,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr28,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr32,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr36,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr40,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr44,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr48,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr52,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - - cfmss fr28,fr8,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr8,fr28,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - - cfmss fr32,fr36,fr2,cc5,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 -; - set_fr_iimmed 0x1111,0x1111,fr2 - set_fr_iimmed 0x2222,0x2222,fr3 - cfmss fr16,fr4,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr8,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr16,fr12,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr16,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr16,fr20,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr16,fr24,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr28,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr16,fr32,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr36,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr40,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr44,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr48,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - - cfmss fr20,fr4,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr8,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr20,fr12,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr16,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr20,fr20,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr20,fr24,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr28,fr2,cc2,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr20,fr32,fr2,cc2,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr36,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr40,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr44,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr48,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - - cfmss fr28,fr0,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr4,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr8,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr12,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr16,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr20,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr24,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr28,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr32,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr36,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr40,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr44,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr48,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr52,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - - cfmss fr28,fr8,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr8,fr28,fr2,cc6,0 - test_fr_iimmed 0x11111111,fr2 - - cfmss fr32,fr36,fr2,cc6,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 -; - set_fr_iimmed 0x1111,0x1111,fr2 - set_fr_iimmed 0x2222,0x2222,fr3 - cfmss fr16,fr4,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr8,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr16,fr12,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr16,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr16,fr20,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr16,fr24,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr28,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr16,fr32,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr36,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr40,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr44,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr16,fr48,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - - cfmss fr20,fr4,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr8,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr20,fr12,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr16,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr20,fr20,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr20,fr24,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr28,fr2,cc3,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr20,fr32,fr2,cc3,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr36,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr40,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr44,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr20,fr48,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - - cfmss fr28,fr0,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr4,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr8,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr12,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr16,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr20,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr24,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr28,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr32,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr28,fr36,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr40,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr44,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr48,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - cfmss fr28,fr52,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - - cfmss fr28,fr8,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - cfmss fr8,fr28,fr2,cc7,0 - test_fr_iimmed 0x11111111,fr2 - - cfmss fr32,fr36,fr2,cc7,1 - test_fr_iimmed 0x11111111,fr2 - test_fr_iimmed 0x22222222,fr3 - - pass diff --git a/sim/testsuite/sim/frv/cfmsubs.cgs b/sim/testsuite/sim/frv/cfmsubs.cgs deleted file mode 100644 index bc74da41b03..00000000000 --- a/sim/testsuite/sim/frv/cfmsubs.cgs +++ /dev/null @@ -1,629 +0,0 @@ -# frv testcase for cfmsubs $GRi,$GRj,$GRk,$CCi,$cond -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global cfmsubs -cfmsubs: - set_spr_immed 0x1b1b,cccr - - set_fr_fr fr16,fr1 - cfmsubs fr16,fr4,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr8,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr12,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr16,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr20,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr24,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr28,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr32,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr36,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr40,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr44,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr48,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - cfmsubs fr20,fr4,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr8,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr12,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr16,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr20,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr24,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr28,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr32,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr36,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr40,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr44,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr48,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - set_fr_fr fr16,fr1 - cfmsubs fr28,fr0,fr1,cc4,1 - test_fr_fr fr1,fr0 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr4,fr1,cc4,1 - test_fr_fr fr1,fr4 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr8,fr1,cc4,1 - test_fr_fr fr1,fr8 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr12,fr1,cc4,1 - test_fr_fr fr1,fr12 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr16,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr20,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr24,fr1,cc4,1 - test_fr_fr fr1,fr24 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr28,fr1,cc4,1 - test_fr_fr fr1,fr28 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr32,fr1,cc4,1 - test_fr_fr fr1,fr32 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr36,fr1,cc4,1 - test_fr_fr fr1,fr36 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr40,fr1,cc4,1 - test_fr_fr fr1,fr40 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr44,fr1,cc4,1 - test_fr_fr fr1,fr44 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr48,fr1,cc4,1 - test_fr_fr fr1,fr48 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr52,fr1,cc4,1 - test_fr_fr fr1,fr52 - - set_fr_fr fr32,fr1 - cfmsubs fr8,fr8,fr1,cc4,1 - test_fr_fr fr1,fr8 - set_fr_fr fr36,fr1 - cfmsubs fr36,fr36,fr1,cc4,1 - test_fr_fr fr1,fr40 - - cfmsubs fr32,fr36,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 -; - set_fr_fr fr16,fr1 - cfmsubs fr16,fr4,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr8,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr12,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr16,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr20,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr24,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr28,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr32,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr36,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr40,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr44,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr16,fr48,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - cfmsubs fr20,fr4,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr8,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr12,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr16,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr20,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr24,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr28,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr32,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr36,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr40,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr44,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmsubs fr20,fr48,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - set_fr_fr fr16,fr1 - cfmsubs fr28,fr0,fr1,cc5,0 - test_fr_fr fr1,fr0 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr4,fr1,cc5,0 - test_fr_fr fr1,fr4 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr8,fr1,cc5,0 - test_fr_fr fr1,fr8 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr12,fr1,cc5,0 - test_fr_fr fr1,fr12 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr16,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr20,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr24,fr1,cc5,0 - test_fr_fr fr1,fr24 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr28,fr1,cc5,0 - test_fr_fr fr1,fr28 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr32,fr1,cc5,0 - test_fr_fr fr1,fr32 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr36,fr1,cc5,0 - test_fr_fr fr1,fr36 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr40,fr1,cc5,0 - test_fr_fr fr1,fr40 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr44,fr1,cc5,0 - test_fr_fr fr1,fr44 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr48,fr1,cc5,0 - test_fr_fr fr1,fr48 - set_fr_fr fr16,fr1 - cfmsubs fr28,fr52,fr1,cc5,0 - test_fr_fr fr1,fr52 - - set_fr_fr fr32,fr1 - cfmsubs fr8,fr8,fr1,cc5,0 - test_fr_fr fr1,fr8 - set_fr_fr fr36,fr1 - cfmsubs fr36,fr36,fr1,cc5,0 - test_fr_fr fr1,fr40 - - cfmsubs fr32,fr36,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 -; - set_fr_fr fr48,fr1 - cfmsubs fr16,fr4,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr8,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr12,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr16,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr20,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr24,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr28,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr32,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr36,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr40,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr44,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr48,fr1,cc0,0 - test_fr_fr fr1,fr48 - - cfmsubs fr20,fr4,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr8,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr12,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr16,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr20,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr24,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr28,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr32,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr36,fr1,cc0,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr40,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr44,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr48,fr1,cc4,0 - test_fr_fr fr1,fr48 - - cfmsubs fr28,fr0,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr4,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr8,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr12,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr16,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr20,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr24,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr28,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr32,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr36,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr40,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr44,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr48,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr52,fr1,cc4,0 - test_fr_fr fr1,fr48 - - cfmsubs fr8,fr8,fr1,cc4,0 - test_fr_fr fr1,fr48 - cfmsubs fr36,fr36,fr1,cc4,0 - test_fr_fr fr1,fr48 - - cfmsubs fr32,fr36,fr1,cc4,0 - test_fr_fr fr1,fr48 -; - set_fr_fr fr48,fr1 - cfmsubs fr16,fr4,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr8,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr12,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr16,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr20,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr24,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr28,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr32,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr36,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr40,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr44,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr48,fr1,cc1,1 - test_fr_fr fr1,fr48 - - cfmsubs fr20,fr4,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr8,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr12,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr16,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr20,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr24,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr28,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr32,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr36,fr1,cc1,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr40,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr44,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr48,fr1,cc5,1 - test_fr_fr fr1,fr48 - - cfmsubs fr28,fr0,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr4,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr8,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr12,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr16,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr20,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr24,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr28,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr32,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr36,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr40,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr44,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr48,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr52,fr1,cc5,1 - test_fr_fr fr1,fr48 - - cfmsubs fr8,fr8,fr1,cc5,1 - test_fr_fr fr1,fr48 - cfmsubs fr36,fr36,fr1,cc5,1 - test_fr_fr fr1,fr48 - - cfmsubs fr32,fr36,fr1,cc5,1 - test_fr_fr fr1,fr48 -; - set_fr_fr fr48,fr1 - cfmsubs fr16,fr4,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr8,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr12,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr16,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr20,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr24,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr28,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr32,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr36,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr40,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr44,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr48,fr1,cc2,1 - test_fr_fr fr1,fr48 - - cfmsubs fr20,fr4,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr8,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr12,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr16,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr20,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr24,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr28,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr32,fr1,cc2,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr36,fr1,cc2,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr40,fr1,cc6,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr44,fr1,cc6,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr48,fr1,cc6,1 - test_fr_fr fr1,fr48 - - cfmsubs fr28,fr0,fr1,cc6,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr4,fr1,cc6,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr8,fr1,cc6,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr12,fr1,cc6,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr16,fr1,cc6,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr20,fr1,cc6,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr24,fr1,cc6,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr28,fr1,cc6,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr32,fr1,cc6,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr36,fr1,cc6,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr40,fr1,cc6,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr44,fr1,cc6,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr48,fr1,cc6,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr52,fr1,cc6,1 - test_fr_fr fr1,fr48 - - cfmsubs fr8,fr8,fr1,cc6,0 - test_fr_fr fr1,fr48 - cfmsubs fr36,fr36,fr1,cc6,1 - test_fr_fr fr1,fr48 - - cfmsubs fr32,fr36,fr1,cc6,0 - test_fr_fr fr1,fr48 -; - set_fr_fr fr48,fr1 - cfmsubs fr16,fr4,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr8,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr12,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr16,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr20,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr24,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr28,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr32,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr36,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr40,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr44,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmsubs fr16,fr48,fr1,cc3,1 - test_fr_fr fr1,fr48 - - cfmsubs fr20,fr4,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr8,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr12,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr16,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr20,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr24,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr28,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr32,fr1,cc3,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr36,fr1,cc3,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr40,fr1,cc7,1 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr44,fr1,cc7,0 - test_fr_fr fr1,fr48 - cfmsubs fr20,fr48,fr1,cc7,1 - test_fr_fr fr1,fr48 - - cfmsubs fr28,fr0,fr1,cc7,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr4,fr1,cc7,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr8,fr1,cc7,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr12,fr1,cc7,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr16,fr1,cc7,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr20,fr1,cc7,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr24,fr1,cc7,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr28,fr1,cc7,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr32,fr1,cc7,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr36,fr1,cc7,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr40,fr1,cc7,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr44,fr1,cc7,1 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr48,fr1,cc7,0 - test_fr_fr fr1,fr48 - cfmsubs fr28,fr52,fr1,cc7,1 - test_fr_fr fr1,fr48 - - cfmsubs fr8,fr8,fr1,cc7,0 - test_fr_fr fr1,fr48 - cfmsubs fr36,fr36,fr1,cc7,1 - test_fr_fr fr1,fr48 - - cfmsubs fr32,fr36,fr1,cc7,0 - test_fr_fr fr1,fr48 -; - pass diff --git a/sim/testsuite/sim/frv/cfmuls.cgs b/sim/testsuite/sim/frv/cfmuls.cgs deleted file mode 100644 index 773c95a60e7..00000000000 --- a/sim/testsuite/sim/frv/cfmuls.cgs +++ /dev/null @@ -1,696 +0,0 @@ -# frv testcase for cfmuls $FRi,$FRj,$FRk,$CCi,$cond -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global cfmuls -cfmuls: - set_spr_immed 0x1b1b,cccr - - cfmuls fr16,fr4,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr8,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr12,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr16,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr20,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr24,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr28,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr32,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr36,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr40,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr44,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr48,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - cfmuls fr20,fr4,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr8,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr12,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr16,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr20,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr24,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr28,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr32,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr36,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr40,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr44,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr48,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - cfmuls fr28,fr0,fr1,cc4,1 - test_fr_fr fr1,fr0 - cfmuls fr28,fr4,fr1,cc4,1 - test_fr_fr fr1,fr4 - cfmuls fr28,fr8,fr1,cc4,1 - test_fr_fr fr1,fr8 - cfmuls fr28,fr12,fr1,cc4,1 - test_fr_fr fr1,fr12 - cfmuls fr28,fr16,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr28,fr20,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr28,fr24,fr1,cc4,1 - test_fr_fr fr1,fr24 - cfmuls fr28,fr28,fr1,cc4,1 - test_fr_fr fr1,fr28 - cfmuls fr28,fr32,fr1,cc4,1 - test_fr_fr fr1,fr32 - cfmuls fr28,fr36,fr1,cc4,1 - test_fr_fr fr1,fr36 - cfmuls fr28,fr40,fr1,cc4,1 - test_fr_fr fr1,fr40 - cfmuls fr28,fr44,fr1,cc4,1 - test_fr_fr fr1,fr44 - cfmuls fr28,fr48,fr1,cc4,1 - test_fr_fr fr1,fr48 - cfmuls fr28,fr52,fr1,cc4,1 - test_fr_fr fr1,fr52 - - cfmuls fr28,fr8,fr1,cc4,1 - test_fr_fr fr1,fr8 - cfmuls fr8,fr28,fr1,cc4,1 - test_fr_fr fr1,fr8 - - cfmuls fr32,fr36,fr1,cc4,1 - test_fr_fr fr1,fr40 -; - cfmuls fr16,fr4,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr8,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr12,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr16,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr20,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr24,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr28,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr32,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr36,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr40,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr44,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr16,fr48,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - cfmuls fr20,fr4,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr8,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr12,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr16,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr20,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr24,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr28,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr32,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr36,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr40,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr44,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr20,fr48,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - cfmuls fr28,fr0,fr1,cc5,0 - test_fr_fr fr1,fr0 - cfmuls fr28,fr4,fr1,cc5,0 - test_fr_fr fr1,fr4 - cfmuls fr28,fr8,fr1,cc5,0 - test_fr_fr fr1,fr8 - cfmuls fr28,fr12,fr1,cc5,0 - test_fr_fr fr1,fr12 - cfmuls fr28,fr16,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr28,fr20,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfmuls fr28,fr24,fr1,cc5,0 - test_fr_fr fr1,fr24 - cfmuls fr28,fr28,fr1,cc5,0 - test_fr_fr fr1,fr28 - cfmuls fr28,fr32,fr1,cc5,0 - test_fr_fr fr1,fr32 - cfmuls fr28,fr36,fr1,cc5,0 - test_fr_fr fr1,fr36 - cfmuls fr28,fr40,fr1,cc5,0 - test_fr_fr fr1,fr40 - cfmuls fr28,fr44,fr1,cc5,0 - test_fr_fr fr1,fr44 - cfmuls fr28,fr48,fr1,cc5,0 - test_fr_fr fr1,fr48 - cfmuls fr28,fr52,fr1,cc5,0 - test_fr_fr fr1,fr52 - - cfmuls fr28,fr8,fr1,cc5,0 - test_fr_fr fr1,fr8 - cfmuls fr8,fr28,fr1,cc5,0 - test_fr_fr fr1,fr8 - - cfmuls fr32,fr36,fr1,cc5,0 - test_fr_fr fr1,fr40 -; - set_fr_iimmed 0xdead,0xbeef,fr1 - cfmuls fr16,fr4,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr8,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr12,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr20,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr24,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr32,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr36,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr40,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr44,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr48,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfmuls fr20,fr4,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr8,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr12,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr20,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr24,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr28,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr32,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr36,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr40,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr44,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr48,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfmuls fr28,fr0,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr4,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr8,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr12,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr16,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr20,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr24,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr28,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr32,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr36,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr40,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr44,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr48,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr52,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfmuls fr28,fr8,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr8,fr28,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfmuls fr32,fr36,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 -; - set_fr_iimmed 0xdead,0xbeef,fr1 - cfmuls fr16,fr4,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr8,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr12,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr20,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr24,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr32,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr36,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr40,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr44,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr48,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfmuls fr20,fr4,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr8,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr12,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr20,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr24,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr28,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr32,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr36,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr40,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr44,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr48,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfmuls fr28,fr0,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr4,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr8,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr12,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr16,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr20,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr24,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr28,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr32,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr36,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr40,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr44,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr48,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr52,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfmuls fr28,fr8,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr8,fr28,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfmuls fr32,fr36,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 -; - set_fr_iimmed 0xdead,0xbeef,fr1 - cfmuls fr16,fr4,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr8,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr12,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr16,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr20,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr24,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr28,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr32,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr36,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr40,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr44,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr48,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfmuls fr20,fr4,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr8,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr12,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr16,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr20,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr24,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr28,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr32,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr36,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr40,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr44,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr48,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfmuls fr28,fr0,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr4,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr8,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr12,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr16,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr20,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr24,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr28,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr32,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr36,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr40,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr44,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr48,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr52,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfmuls fr28,fr8,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr8,fr28,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfmuls fr32,fr36,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 -; - set_fr_iimmed 0xdead,0xbeef,fr1 - cfmuls fr16,fr4,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr8,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr12,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr16,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr20,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr24,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr28,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr32,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr36,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr40,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr44,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr16,fr48,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfmuls fr20,fr4,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr8,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr12,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr16,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr20,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr24,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr28,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr32,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr36,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr40,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr44,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr20,fr48,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfmuls fr28,fr0,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr4,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr8,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr12,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr16,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr20,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr24,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr28,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr32,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr36,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr40,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr44,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr48,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr28,fr52,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfmuls fr28,fr8,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfmuls fr8,fr28,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfmuls fr32,fr36,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - - pass diff --git a/sim/testsuite/sim/frv/cfnegs.cgs b/sim/testsuite/sim/frv/cfnegs.cgs deleted file mode 100644 index c1f2b256897..00000000000 --- a/sim/testsuite/sim/frv/cfnegs.cgs +++ /dev/null @@ -1,96 +0,0 @@ -# frv testcase for cfnegs $FRj,$FRk,$CCi,$cond -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global cfnegs -cfnegs: - set_spr_immed 0x1b1b,cccr - - cfnegs fr0,fr1,cc0,1 - test_fr_fr fr1,fr52 - cfnegs fr8,fr1,cc0,1 - test_fr_fr fr1,fr28 - cfnegs fr12,fr1,cc0,1 - test_fr_fr fr1,fr24 - cfnegs fr24,fr1,cc4,1 - test_fr_fr fr1,fr12 - cfnegs fr28,fr1,cc4,1 - test_fr_fr fr1,fr8 - cfnegs fr52,fr1,cc4,1 - test_fr_fr fr1,fr0 - - cfnegs fr0,fr1,cc1,0 - test_fr_fr fr1,fr52 - cfnegs fr8,fr1,cc1,0 - test_fr_fr fr1,fr28 - cfnegs fr12,fr1,cc1,0 - test_fr_fr fr1,fr24 - cfnegs fr24,fr1,cc5,0 - test_fr_fr fr1,fr12 - cfnegs fr28,fr1,cc5,0 - test_fr_fr fr1,fr8 - cfnegs fr52,fr1,cc5,0 - test_fr_fr fr1,fr0 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfnegs fr0,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr8,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr12,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr24,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr28,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr52,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfnegs fr0,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr8,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr12,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr24,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr28,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr52,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfnegs fr0,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr8,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr12,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr24,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr28,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr52,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfnegs fr0,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr8,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr12,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr24,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr28,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfnegs fr52,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - - pass diff --git a/sim/testsuite/sim/frv/cfsqrts.cgs b/sim/testsuite/sim/frv/cfsqrts.cgs deleted file mode 100644 index ee7a9a56297..00000000000 --- a/sim/testsuite/sim/frv/cfsqrts.cgs +++ /dev/null @@ -1,60 +0,0 @@ -# frv testcase for cfsqrts $FRj,$FRk,$CCi,$cond -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global cfsqrts -cfsqrts: - set_spr_immed 0x1b1b,cccr - - cfsqrts fr44,fr1,cc0,1 ; 9.0 - test_fr_fr fr1,fr36 ; 3.0 - - set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 - cfsqrts fr10,fr10,cc4,1 - test_fr_iimmed 0x3fe2dfc5,fr10 ; 1.7724539 - - cfsqrts fr44,fr1,cc1,0 ; 9.0 - test_fr_fr fr1,fr36 ; 3.0 - - set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 - cfsqrts fr10,fr10,cc5,0 - test_fr_iimmed 0x3fe2dfc5,fr10 ; 1.7724539 - - set_fr_fr fr0,fr1 - cfsqrts fr44,fr1,cc0,0 ; 9.0 - test_fr_fr fr1,fr0 - - set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 - cfsqrts fr10,fr10,cc4,0 - test_fr_iimmed 0x40490fdb,fr10 - - set_fr_fr fr0,fr1 - cfsqrts fr44,fr1,cc1,1 ; 9.0 - test_fr_fr fr1,fr0 - - set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 - cfsqrts fr10,fr10,cc5,1 - test_fr_iimmed 0x40490fdb,fr10 - - set_fr_fr fr0,fr1 - cfsqrts fr44,fr1,cc2,0 ; 9.0 - test_fr_fr fr1,fr0 - - set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 - cfsqrts fr10,fr10,cc6,1 - test_fr_iimmed 0x40490fdb,fr10 - - set_fr_fr fr0,fr1 - cfsqrts fr44,fr1,cc3,1 ; 9.0 - test_fr_fr fr1,fr0 - - set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 - cfsqrts fr10,fr10,cc7,0 - test_fr_iimmed 0x40490fdb,fr10 - - pass diff --git a/sim/testsuite/sim/frv/cfstoi.cgs b/sim/testsuite/sim/frv/cfstoi.cgs deleted file mode 100644 index 9ba8d126fe1..00000000000 --- a/sim/testsuite/sim/frv/cfstoi.cgs +++ /dev/null @@ -1,83 +0,0 @@ -# frv testcase for cfstoi $FRj,$FRk,$CCi,$cond -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global cfstoi -cfstoi: - set_spr_immed 0x1b1b,cccr - - cfstoi fr16,fr1,cc0,1 - test_fr_iimmed 0,fr1 - cfstoi fr20,fr1,cc0,1 - test_fr_iimmed 0,fr1 - - cfstoi fr32,fr1,cc4,1 - test_fr_iimmed 0x00000002,fr1 - - set_fr_iimmed 0xce05,0x4904,fr1 - cfstoi fr1,fr1,cc4,1 - test_fr_iimmed 0xdeadbf00,fr1 - - cfstoi fr16,fr1,cc1,0 - test_fr_iimmed 0,fr1 - cfstoi fr20,fr1,cc1,0 - test_fr_iimmed 0,fr1 - - cfstoi fr32,fr1,cc5,0 - test_fr_iimmed 0x00000002,fr1 - - set_fr_iimmed 0xce05,0x4904,fr1 - cfstoi fr1,fr1,cc5,0 - test_fr_iimmed 0xdeadbf00,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfstoi fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfstoi fr20,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfstoi fr32,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfstoi fr1,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfstoi fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfstoi fr20,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfstoi fr32,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfstoi fr1,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfstoi fr16,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfstoi fr20,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfstoi fr32,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfstoi fr1,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfstoi fr16,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfstoi fr20,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfstoi fr32,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfstoi fr1,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - - pass diff --git a/sim/testsuite/sim/frv/cfsubs.cgs b/sim/testsuite/sim/frv/cfsubs.cgs deleted file mode 100644 index 3bc7db1ea68..00000000000 --- a/sim/testsuite/sim/frv/cfsubs.cgs +++ /dev/null @@ -1,412 +0,0 @@ -# frv testcase for cfsubs $FRi,$FRj,$FRk,$CCi,$cond -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global cfsubs -cfsubs: - set_spr_immed 0x1b1b,cccr - - cfsubs fr0,fr16,fr1,cc0,1 - test_fr_fr fr1,fr0 - cfsubs fr4,fr16,fr1,cc0,1 - test_fr_fr fr1,fr4 - cfsubs fr8,fr16,fr1,cc0,1 - test_fr_fr fr1,fr8 - cfsubs fr12,fr16,fr1,cc0,1 - test_fr_fr fr1,fr12 - cfsubs fr16,fr16,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfsubs fr20,fr16,fr1,cc0,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfsubs fr24,fr16,fr1,cc0,1 - test_fr_fr fr1,fr24 - cfsubs fr28,fr16,fr1,cc0,1 - test_fr_fr fr1,fr28 - cfsubs fr32,fr16,fr1,cc0,1 - test_fr_fr fr1,fr32 - cfsubs fr36,fr16,fr1,cc0,1 - test_fr_fr fr1,fr36 - cfsubs fr40,fr16,fr1,cc0,1 - test_fr_fr fr1,fr40 - cfsubs fr44,fr16,fr1,cc0,1 - test_fr_fr fr1,fr44 - cfsubs fr48,fr16,fr1,cc0,1 - test_fr_fr fr1,fr48 - cfsubs fr52,fr16,fr1,cc0,1 - test_fr_fr fr1,fr52 - - cfsubs fr0,fr20,fr1,cc0,1 - test_fr_fr fr1,fr0 - cfsubs fr4,fr20,fr1,cc4,1 - test_fr_fr fr1,fr4 - cfsubs fr8,fr20,fr1,cc4,1 - test_fr_fr fr1,fr8 - cfsubs fr12,fr20,fr1,cc4,1 - test_fr_fr fr1,fr12 - cfsubs fr16,fr20,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfsubs fr20,fr20,fr1,cc4,1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfsubs fr24,fr20,fr1,cc4,1 - test_fr_fr fr1,fr24 - cfsubs fr28,fr20,fr1,cc4,1 - test_fr_fr fr1,fr28 - cfsubs fr32,fr20,fr1,cc4,1 - test_fr_fr fr1,fr32 - cfsubs fr36,fr20,fr1,cc4,1 - test_fr_fr fr1,fr36 - cfsubs fr40,fr20,fr1,cc4,1 - test_fr_fr fr1,fr40 - cfsubs fr44,fr20,fr1,cc4,1 - test_fr_fr fr1,fr44 - cfsubs fr48,fr20,fr1,cc4,1 - test_fr_fr fr1,fr48 - cfsubs fr52,fr20,fr1,cc4,1 - test_fr_fr fr1,fr52 - - cfsubs fr32,fr36,fr1,cc4,1 - test_fr_fr fr1,fr8 - - cfsubs fr44,fr40,fr1,cc4,1 - test_fr_fr fr1,fr36 -; - cfsubs fr0,fr16,fr1,cc1,0 - test_fr_fr fr1,fr0 - cfsubs fr4,fr16,fr1,cc1,0 - test_fr_fr fr1,fr4 - cfsubs fr8,fr16,fr1,cc1,0 - test_fr_fr fr1,fr8 - cfsubs fr12,fr16,fr1,cc1,0 - test_fr_fr fr1,fr12 - cfsubs fr16,fr16,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfsubs fr20,fr16,fr1,cc1,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfsubs fr24,fr16,fr1,cc1,0 - test_fr_fr fr1,fr24 - cfsubs fr28,fr16,fr1,cc1,0 - test_fr_fr fr1,fr28 - cfsubs fr32,fr16,fr1,cc1,0 - test_fr_fr fr1,fr32 - cfsubs fr36,fr16,fr1,cc1,0 - test_fr_fr fr1,fr36 - cfsubs fr40,fr16,fr1,cc1,0 - test_fr_fr fr1,fr40 - cfsubs fr44,fr16,fr1,cc1,0 - test_fr_fr fr1,fr44 - cfsubs fr48,fr16,fr1,cc1,0 - test_fr_fr fr1,fr48 - cfsubs fr52,fr16,fr1,cc1,0 - test_fr_fr fr1,fr52 - - cfsubs fr0,fr20,fr1,cc1,0 - test_fr_fr fr1,fr0 - cfsubs fr4,fr20,fr1,cc5,0 - test_fr_fr fr1,fr4 - cfsubs fr8,fr20,fr1,cc5,0 - test_fr_fr fr1,fr8 - cfsubs fr12,fr20,fr1,cc5,0 - test_fr_fr fr1,fr12 - cfsubs fr16,fr20,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfsubs fr20,fr20,fr1,cc5,0 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - cfsubs fr24,fr20,fr1,cc5,0 - test_fr_fr fr1,fr24 - cfsubs fr28,fr20,fr1,cc5,0 - test_fr_fr fr1,fr28 - cfsubs fr32,fr20,fr1,cc5,0 - test_fr_fr fr1,fr32 - cfsubs fr36,fr20,fr1,cc5,0 - test_fr_fr fr1,fr36 - cfsubs fr40,fr20,fr1,cc5,0 - test_fr_fr fr1,fr40 - cfsubs fr44,fr20,fr1,cc5,0 - test_fr_fr fr1,fr44 - cfsubs fr48,fr20,fr1,cc5,0 - test_fr_fr fr1,fr48 - cfsubs fr52,fr20,fr1,cc5,0 - test_fr_fr fr1,fr52 - - cfsubs fr32,fr36,fr1,cc5,0 - test_fr_fr fr1,fr8 - - cfsubs fr44,fr40,fr1,cc5,0 - test_fr_fr fr1,fr36 - - set_fr_iimmed 0xdead,0xbeef,fr1 - cfsubs fr0,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr4,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr8,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr12,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr16,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr20,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr24,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr28,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr32,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr36,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr40,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr44,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr48,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr52,fr16,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfsubs fr0,fr20,fr1,cc0,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr4,fr20,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr8,fr20,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr12,fr20,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr16,fr20,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr20,fr20,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr24,fr20,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr28,fr20,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr32,fr20,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr36,fr20,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr40,fr20,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr44,fr20,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr48,fr20,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr52,fr20,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfsubs fr32,fr36,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfsubs fr44,fr40,fr1,cc4,0 - test_fr_iimmed 0xdeadbeef,fr1 -; - set_fr_iimmed 0xdead,0xbeef,fr1 - cfsubs fr0,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr4,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr8,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr12,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr16,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr20,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr24,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr28,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr32,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr36,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr40,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr44,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr48,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr52,fr16,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfsubs fr0,fr20,fr1,cc1,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr4,fr20,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr8,fr20,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr12,fr20,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr16,fr20,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr20,fr20,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr24,fr20,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr28,fr20,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr32,fr20,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr36,fr20,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr40,fr20,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr44,fr20,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr48,fr20,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr52,fr20,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfsubs fr32,fr36,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfsubs fr44,fr40,fr1,cc5,1 - test_fr_iimmed 0xdeadbeef,fr1 -; - set_fr_iimmed 0xdead,0xbeef,fr1 - cfsubs fr0,fr16,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr4,fr16,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr8,fr16,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr12,fr16,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr16,fr16,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr20,fr16,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr24,fr16,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr28,fr16,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr32,fr16,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr36,fr16,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr40,fr16,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr44,fr16,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr48,fr16,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr52,fr16,fr1,cc2,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfsubs fr0,fr20,fr1,cc2,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr4,fr20,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr8,fr20,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr12,fr20,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr16,fr20,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr20,fr20,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr24,fr20,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr28,fr20,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr32,fr20,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr36,fr20,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr40,fr20,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr44,fr20,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr48,fr20,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr52,fr20,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfsubs fr32,fr36,fr1,cc6,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfsubs fr44,fr40,fr1,cc6,1 - test_fr_iimmed 0xdeadbeef,fr1 -; - set_fr_iimmed 0xdead,0xbeef,fr1 - cfsubs fr0,fr16,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr4,fr16,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr8,fr16,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr12,fr16,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr16,fr16,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr20,fr16,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr24,fr16,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr28,fr16,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr32,fr16,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr36,fr16,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr40,fr16,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr44,fr16,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr48,fr16,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr52,fr16,fr1,cc3,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfsubs fr0,fr20,fr1,cc3,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr4,fr20,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr8,fr20,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr12,fr20,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr16,fr20,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr20,fr20,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr24,fr20,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr28,fr20,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr32,fr20,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr36,fr20,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr40,fr20,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr44,fr20,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr48,fr20,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - cfsubs fr52,fr20,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - - cfsubs fr32,fr36,fr1,cc7,0 - test_fr_iimmed 0xdeadbeef,fr1 - - cfsubs fr44,fr40,fr1,cc7,1 - test_fr_iimmed 0xdeadbeef,fr1 - - pass - - diff --git a/sim/testsuite/sim/frv/cjmpl.cgs b/sim/testsuite/sim/frv/cjmpl.cgs deleted file mode 100644 index df7be86ac14..00000000000 --- a/sim/testsuite/sim/frv/cjmpl.cgs +++ /dev/null @@ -1,55 +0,0 @@ -# frv testcase for cjmpl @($GRi,$GRj),$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cjmpl -cjmpl: - set_spr_immed 0x1b1b,cccr - - set_spr_immed 0,lr - set_gr_addr ok1,gr8 - set_gr_immed 0,gr9 - cjmpl @(gr8,gr9),cc0,1 - fail -ok1: - test_spr_immed 0,lr - - set_spr_immed 0,lr - set_gr_addr bad,gr8 - set_gr_immed 0,gr9 - cjmpl @(gr8,gr9),cc0,0 - test_spr_immed 0,lr - - set_spr_immed 0,lr - set_gr_addr ok4,gr8 - set_gr_immed 3,gr9 ; target gets aligned down - cjmpl @(gr8,gr9),cc1,0 - fail -ok4: - test_spr_immed 0,lr - - set_spr_immed 0,lr - set_gr_addr bad,gr8 - set_gr_immed 0,gr9 - cjmpl @(gr8,gr9),cc1,1 - test_spr_immed 0,lr - - set_spr_immed 0,lr - set_gr_addr bad,gr8 - set_gr_immed 0,gr9 - cjmpl @(gr8,gr9),cc2,0 - test_spr_immed 0,lr - - set_spr_immed 0,lr - set_gr_addr bad,gr8 - set_gr_immed 0,gr9 - cjmpl @(gr8,gr9),cc3,1 - test_spr_immed 0,lr - - pass -bad: - fail - diff --git a/sim/testsuite/sim/frv/ckc.cgs b/sim/testsuite/sim/frv/ckc.cgs deleted file mode 100644 index a849dd48376..00000000000 --- a/sim/testsuite/sim/frv/ckc.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for ckc $ICCi,$CCj_int -# mach: all - - .include "testutils.inc" - - start - - .global ckc -ckc: - set_spr_immed 0x1b1b,cccr - set_icc 0x0 0 - ckc icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x1 0 - ckc icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x2 0 - ckc icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x3 0 - ckc icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x4 0 - ckc icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x5 0 - ckc icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x6 0 - ckc icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x7 0 - ckc icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x8 0 - ckc icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x9 0 - ckc icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xa 0 - ckc icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xb 0 - ckc icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xc 0 - ckc icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xd 0 - ckc icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xe 0 - ckc icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xf 0 - ckc icc0,cc7 - test_spr_immed 0xdb1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/ckeq.cgs b/sim/testsuite/sim/frv/ckeq.cgs deleted file mode 100644 index 241dc9d0c3c..00000000000 --- a/sim/testsuite/sim/frv/ckeq.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for ckeq $ICCi,$CCj_int -# mach: all - - .include "testutils.inc" - - start - - .global ckeq -ckeq: - set_spr_immed 0x1b1b,cccr - set_icc 0x0 0 - ckeq icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x1 0 - ckeq icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x2 0 - ckeq icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x3 0 - ckeq icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x4 0 - ckeq icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x5 0 - ckeq icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x6 0 - ckeq icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x7 0 - ckeq icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x8 0 - ckeq icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x9 0 - ckeq icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xa 0 - ckeq icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xb 0 - ckeq icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xc 0 - ckeq icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xd 0 - ckeq icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xe 0 - ckeq icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xf 0 - ckeq icc0,cc7 - test_spr_immed 0xdb1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/ckge.cgs b/sim/testsuite/sim/frv/ckge.cgs deleted file mode 100644 index 58eefd33845..00000000000 --- a/sim/testsuite/sim/frv/ckge.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for ckge $ICCi,$CCj_int -# mach: all - - .include "testutils.inc" - - start - - .global ckge -ckge: - set_spr_immed 0x1b1b,cccr - set_icc 0x0 0 - ckge icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x1 0 - ckge icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x2 0 - ckge icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x3 0 - ckge icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x4 0 - ckge icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x5 0 - ckge icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x6 0 - ckge icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x7 0 - ckge icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x8 0 - ckge icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x9 0 - ckge icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xa 0 - ckge icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xb 0 - ckge icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xc 0 - ckge icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xd 0 - ckge icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xe 0 - ckge icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xf 0 - ckge icc0,cc7 - test_spr_immed 0xdb1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/ckgt.cgs b/sim/testsuite/sim/frv/ckgt.cgs deleted file mode 100644 index 7d4b6a88e19..00000000000 --- a/sim/testsuite/sim/frv/ckgt.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for ckgt $ICCi,$CCj_int -# mach: all - - .include "testutils.inc" - - start - - .global ckgt -ckgt: - set_spr_immed 0x1b1b,cccr - set_icc 0x0 0 - ckgt icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x1 0 - ckgt icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x2 0 - ckgt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x3 0 - ckgt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x4 0 - ckgt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x5 0 - ckgt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x6 0 - ckgt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x7 0 - ckgt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x8 0 - ckgt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x9 0 - ckgt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xa 0 - ckgt icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xb 0 - ckgt icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xc 0 - ckgt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xd 0 - ckgt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xe 0 - ckgt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xf 0 - ckgt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/ckhi.cgs b/sim/testsuite/sim/frv/ckhi.cgs deleted file mode 100644 index 5c55937f6ab..00000000000 --- a/sim/testsuite/sim/frv/ckhi.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for ckhi $ICCi,$CCj_int -# mach: all - - .include "testutils.inc" - - start - - .global ckhi -ckhi: - set_spr_immed 0x1b1b,cccr - set_icc 0x0 0 - ckhi icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x1 0 - ckhi icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x2 0 - ckhi icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x3 0 - ckhi icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x4 0 - ckhi icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x5 0 - ckhi icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x6 0 - ckhi icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x7 0 - ckhi icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x8 0 - ckhi icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x9 0 - ckhi icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xa 0 - ckhi icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xb 0 - ckhi icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xc 0 - ckhi icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xd 0 - ckhi icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xe 0 - ckhi icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xf 0 - ckhi icc0,cc7 - test_spr_immed 0x9b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/ckle.cgs b/sim/testsuite/sim/frv/ckle.cgs deleted file mode 100644 index 8a6f445beaa..00000000000 --- a/sim/testsuite/sim/frv/ckle.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for ckle $ICCi,$CCj_int -# mach: all - - .include "testutils.inc" - - start - - .global ckle -ckle: - set_spr_immed 0x1b1b,cccr - set_icc 0x0 0 - ckle icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x1 0 - ckle icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x2 0 - ckle icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x3 0 - ckle icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x4 0 - ckle icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x5 0 - ckle icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x6 0 - ckle icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x7 0 - ckle icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x8 0 - ckle icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x9 0 - ckle icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xa 0 - ckle icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xb 0 - ckle icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xc 0 - ckle icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xd 0 - ckle icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xe 0 - ckle icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xf 0 - ckle icc0,cc7 - test_spr_immed 0xdb1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/ckls.cgs b/sim/testsuite/sim/frv/ckls.cgs deleted file mode 100644 index ca5822f283f..00000000000 --- a/sim/testsuite/sim/frv/ckls.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for ckls $ICCi,$CCj_int -# mach: all - - .include "testutils.inc" - - start - - .global ckls -ckls: - set_spr_immed 0x1b1b,cccr - set_icc 0x0 0 - ckls icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x1 0 - ckls icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x2 0 - ckls icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x3 0 - ckls icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x4 0 - ckls icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x5 0 - ckls icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x6 0 - ckls icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x7 0 - ckls icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x8 0 - ckls icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x9 0 - ckls icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xa 0 - ckls icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xb 0 - ckls icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xc 0 - ckls icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xd 0 - ckls icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xe 0 - ckls icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xf 0 - ckls icc0,cc7 - test_spr_immed 0xdb1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cklt.cgs b/sim/testsuite/sim/frv/cklt.cgs deleted file mode 100644 index f5848af490d..00000000000 --- a/sim/testsuite/sim/frv/cklt.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for cklt $ICCi,$CCj_int -# mach: all - - .include "testutils.inc" - - start - - .global cklt -cklt: - set_spr_immed 0x1b1b,cccr - set_icc 0x0 0 - cklt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x1 0 - cklt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x2 0 - cklt icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x3 0 - cklt icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x4 0 - cklt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x5 0 - cklt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x6 0 - cklt icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x7 0 - cklt icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x8 0 - cklt icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x9 0 - cklt icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xa 0 - cklt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xb 0 - cklt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xc 0 - cklt icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xd 0 - cklt icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xe 0 - cklt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xf 0 - cklt icc0,cc7 - test_spr_immed 0x9b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/ckn.cgs b/sim/testsuite/sim/frv/ckn.cgs deleted file mode 100644 index 073a2f1137d..00000000000 --- a/sim/testsuite/sim/frv/ckn.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for ckn $ICCi,$CCj_int -# mach: all - - .include "testutils.inc" - - start - - .global ckn -ckn: - set_spr_immed 0x1b1b,cccr - set_icc 0x0 0 - ckn icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x1 0 - ckn icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x2 0 - ckn icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x3 0 - ckn icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x4 0 - ckn icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x5 0 - ckn icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x6 0 - ckn icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x7 0 - ckn icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x8 0 - ckn icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x9 0 - ckn icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xa 0 - ckn icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xb 0 - ckn icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xc 0 - ckn icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xd 0 - ckn icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xe 0 - ckn icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xf 0 - ckn icc0,cc7 - test_spr_immed 0xdb1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cknc.cgs b/sim/testsuite/sim/frv/cknc.cgs deleted file mode 100644 index a1359a983ad..00000000000 --- a/sim/testsuite/sim/frv/cknc.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for cknc $ICCi,$CCj_int -# mach: all - - .include "testutils.inc" - - start - - .global cknc -cknc: - set_spr_immed 0x1b1b,cccr - set_icc 0x0 0 - cknc icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x1 0 - cknc icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x2 0 - cknc icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x3 0 - cknc icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x4 0 - cknc icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x5 0 - cknc icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x6 0 - cknc icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x7 0 - cknc icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x8 0 - cknc icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x9 0 - cknc icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xa 0 - cknc icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xb 0 - cknc icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xc 0 - cknc icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xd 0 - cknc icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xe 0 - cknc icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xf 0 - cknc icc0,cc7 - test_spr_immed 0x9b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/ckne.cgs b/sim/testsuite/sim/frv/ckne.cgs deleted file mode 100644 index b9c293519b7..00000000000 --- a/sim/testsuite/sim/frv/ckne.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for ckne $ICCi,$CCj_int -# mach: all - - .include "testutils.inc" - - start - - .global ckne -ckne: - set_spr_immed 0x1b1b,cccr - set_icc 0x0 0 - ckne icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x1 0 - ckne icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x2 0 - ckne icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x3 0 - ckne icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x4 0 - ckne icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x5 0 - ckne icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x6 0 - ckne icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x7 0 - ckne icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x8 0 - ckne icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x9 0 - ckne icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xa 0 - ckne icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xb 0 - ckne icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xc 0 - ckne icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xd 0 - ckne icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xe 0 - ckne icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xf 0 - ckne icc0,cc7 - test_spr_immed 0x9b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/ckno.cgs b/sim/testsuite/sim/frv/ckno.cgs deleted file mode 100644 index e387b46beac..00000000000 --- a/sim/testsuite/sim/frv/ckno.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for ckno $CCj_int -# mach: all - - .include "testutils.inc" - - start - - .global ckno -ckno: - set_spr_immed 0x1b1b,cccr - set_icc 0x0 0 - ckno cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x1 0 - ckno cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x2 0 - ckno cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x3 0 - ckno cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x4 0 - ckno cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x5 0 - ckno cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x6 0 - ckno cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x7 0 - ckno cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x8 0 - ckno cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x9 0 - ckno cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xa 0 - ckno cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xb 0 - ckno cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xc 0 - ckno cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xd 0 - ckno cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xe 0 - ckno cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xf 0 - ckno cc7 - test_spr_immed 0x9b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cknv.cgs b/sim/testsuite/sim/frv/cknv.cgs deleted file mode 100644 index 039eb7d8dbf..00000000000 --- a/sim/testsuite/sim/frv/cknv.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for cknv $ICCi,$CCj_int -# mach: all - - .include "testutils.inc" - - start - - .global cknv -cknv: - set_spr_immed 0x1b1b,cccr - set_icc 0x0 0 - cknv icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x1 0 - cknv icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x2 0 - cknv icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x3 0 - cknv icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x4 0 - cknv icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x5 0 - cknv icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x6 0 - cknv icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x7 0 - cknv icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x8 0 - cknv icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x9 0 - cknv icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xa 0 - cknv icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xb 0 - cknv icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xc 0 - cknv icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xd 0 - cknv icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xe 0 - cknv icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xf 0 - cknv icc0,cc7 - test_spr_immed 0x9b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/ckp.cgs b/sim/testsuite/sim/frv/ckp.cgs deleted file mode 100644 index 49129ec9bb9..00000000000 --- a/sim/testsuite/sim/frv/ckp.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for ckp $ICCi,$CCj_int -# mach: all - - .include "testutils.inc" - - start - - .global ckp -ckp: - set_spr_immed 0x1b1b,cccr - set_icc 0x0 0 - ckp icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x1 0 - ckp icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x2 0 - ckp icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x3 0 - ckp icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x4 0 - ckp icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x5 0 - ckp icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x6 0 - ckp icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x7 0 - ckp icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x8 0 - ckp icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x9 0 - ckp icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xa 0 - ckp icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xb 0 - ckp icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xc 0 - ckp icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xd 0 - ckp icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xe 0 - ckp icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xf 0 - ckp icc0,cc7 - test_spr_immed 0x9b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/ckra.cgs b/sim/testsuite/sim/frv/ckra.cgs deleted file mode 100644 index b542b10b9ed..00000000000 --- a/sim/testsuite/sim/frv/ckra.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for ckra $CCj_int -# mach: all - - .include "testutils.inc" - - start - - .global ckra -ckra: - set_spr_immed 0x1b1b,cccr - set_icc 0x0 0 - ckra cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x1 0 - ckra cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x2 0 - ckra cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x3 0 - ckra cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x4 0 - ckra cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x5 0 - ckra cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x6 0 - ckra cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x7 0 - ckra cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x8 0 - ckra cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x9 0 - ckra cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xa 0 - ckra cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xb 0 - ckra cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xc 0 - ckra cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xd 0 - ckra cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xe 0 - ckra cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xf 0 - ckra cc7 - test_spr_immed 0xdb1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/ckv.cgs b/sim/testsuite/sim/frv/ckv.cgs deleted file mode 100644 index 338c2861ed8..00000000000 --- a/sim/testsuite/sim/frv/ckv.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for ckv $ICCi,$CCj_int -# mach: all - - .include "testutils.inc" - - start - - .global ckv -ckv: - set_spr_immed 0x1b1b,cccr - set_icc 0x0 0 - ckv icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x1 0 - ckv icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x2 0 - ckv icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x3 0 - ckv icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x4 0 - ckv icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x5 0 - ckv icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x6 0 - ckv icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x7 0 - ckv icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x8 0 - ckv icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0x9 0 - ckv icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xa 0 - ckv icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xb 0 - ckv icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xc 0 - ckv icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xd 0 - ckv icc0,cc7 - test_spr_immed 0x9b1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xe 0 - ckv icc0,cc7 - test_spr_immed 0xdb1b,cccr - - set_spr_immed 0x1b1b,cccr - set_icc 0xf 0 - ckv icc0,cc7 - test_spr_immed 0xdb1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/cld.cgs b/sim/testsuite/sim/frv/cld.cgs deleted file mode 100644 index 62e1324a22b..00000000000 --- a/sim/testsuite/sim/frv/cld.cgs +++ /dev/null @@ -1,126 +0,0 @@ -# frv testcase for cld @($GRi,$GRj),$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cld -cld: - set_spr_immed 0x1b1b,cccr - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cld @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cld @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cld @(sp,gr7),gr8,cc4,1 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cld @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cld @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cld @(sp,gr7),gr8,cc4,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cld @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cld @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cld @(sp,gr7),gr8,cc5,0 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cld @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cld @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cld @(sp,gr7),gr8,cc5,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cld @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cld @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cld @(sp,gr7),gr8,cc6,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cld @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cld @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cld @(sp,gr7),gr8,cc7,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - pass diff --git a/sim/testsuite/sim/frv/cldbf.cgs b/sim/testsuite/sim/frv/cldbf.cgs deleted file mode 100644 index 46d65ea6939..00000000000 --- a/sim/testsuite/sim/frv/cldbf.cgs +++ /dev/null @@ -1,114 +0,0 @@ -# frv testcase for cldbf @($GRi,$GRj),$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cldbf -cldbf: - set_spr_immed 0x1b1b,cccr - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldbf @(sp,gr7),fr8,cc0,1 - test_fr_limmed 0x0000,0x00de,fr8 - - set_gr_immed 1,gr7 - cldbf @(sp,gr7),fr8,cc0,1 - test_fr_limmed 0x0000,0x00ad,fr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldbf @(sp,gr7),fr8,cc4,1 - test_fr_limmed 0x0000,0x0000,fr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldbf @(sp,gr7),fr8,cc0,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_gr_immed 1,gr7 - cldbf @(sp,gr7),fr8,cc0,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldbf @(sp,gr7),fr8,cc4,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldbf @(sp,gr7),fr8,cc1,0 - test_fr_limmed 0x0000,0x00de,fr8 - - set_gr_immed 1,gr7 - cldbf @(sp,gr7),fr8,cc1,0 - test_fr_limmed 0x0000,0x00ad,fr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldbf @(sp,gr7),fr8,cc5,0 - test_fr_limmed 0x0000,0x0000,fr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldbf @(sp,gr7),fr8,cc1,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_gr_immed 1,gr7 - cldbf @(sp,gr7),fr8,cc1,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldbf @(sp,gr7),fr8,cc5,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldbf @(sp,gr7),fr8,cc2,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_gr_immed 1,gr7 - cldbf @(sp,gr7),fr8,cc2,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldbf @(sp,gr7),fr8,cc6,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldbf @(sp,gr7),fr8,cc3,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_gr_immed 1,gr7 - cldbf @(sp,gr7),fr8,cc3,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldbf @(sp,gr7),fr8,cc7,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - pass diff --git a/sim/testsuite/sim/frv/cldbfu.cgs b/sim/testsuite/sim/frv/cldbfu.cgs deleted file mode 100644 index bde4ff16db6..00000000000 --- a/sim/testsuite/sim/frv/cldbfu.cgs +++ /dev/null @@ -1,154 +0,0 @@ -# frv testcase for cldbfu @($GRi,$GRj),$FRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cldbfu -cldbfu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr21 - - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldbfu @(sp,gr7),fr8,cc0,1 - test_fr_limmed 0x0000,0x00de,fr8 - test_gr_gr sp,gr20 - - inc_gr_immed 1,gr20 - set_gr_immed 1,gr7 - cldbfu @(sp,gr7),fr8,cc0,1 - test_fr_limmed 0x0000,0x00ad,fr8 - test_gr_gr sp,gr20 - - inc_gr_immed 2,gr20 - inc_gr_immed -1,sp - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldbfu @(sp,gr7),fr8,cc4,1 - test_fr_limmed 0x0000,0x0000,fr8 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldbfu @(sp,gr7),fr8,cc0,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_immed 1,gr7 - cldbfu @(sp,gr7),fr8,cc0,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,gr20 - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldbfu @(sp,gr7),fr8,cc4,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldbfu @(sp,gr7),fr8,cc1,0 - test_fr_limmed 0x0000,0x00de,fr8 - test_gr_gr sp,gr20 - - inc_gr_immed 1,gr20 - set_gr_immed 1,gr7 - cldbfu @(sp,gr7),fr8,cc1,0 - test_fr_limmed 0x0000,0x00ad,fr8 - test_gr_gr sp,gr20 - - inc_gr_immed 2,gr20 - inc_gr_immed -1,sp - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldbfu @(sp,gr7),fr8,cc5,0 - test_fr_limmed 0x0000,0x0000,fr8 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldbfu @(sp,gr7),fr8,cc1,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_immed 1,gr7 - cldbfu @(sp,gr7),fr8,cc1,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,gr20 - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldbfu @(sp,gr7),fr8,cc5,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldbfu @(sp,gr7),fr8,cc2,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_immed 1,gr7 - cldbfu @(sp,gr7),fr8,cc2,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,gr20 - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldbfu @(sp,gr7),fr8,cc6,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldbfu @(sp,gr7),fr8,cc3,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_immed 1,gr7 - cldbfu @(sp,gr7),fr8,cc3,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,gr20 - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldbfu @(sp,gr7),fr8,cc7,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - pass diff --git a/sim/testsuite/sim/frv/cldd.cgs b/sim/testsuite/sim/frv/cldd.cgs deleted file mode 100644 index 709eba19ae7..00000000000 --- a/sim/testsuite/sim/frv/cldd.cgs +++ /dev/null @@ -1,168 +0,0 @@ -# frv testcase for cldd @($GRi,$GRj),$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cldd -cldd: - set_spr_immed 0x1b1b,cccr - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_immed 0,gr7 - cldd @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - cldd @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - cldd @(sp,gr7),gr8,cc4,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_immed 0,gr7 - cldd @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - cldd @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - cldd @(sp,gr7),gr8,cc4,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_immed 0,gr7 - cldd @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - cldd @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - cldd @(sp,gr7),gr8,cc5,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_immed 0,gr7 - cldd @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - cldd @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - cldd @(sp,gr7),gr8,cc5,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_immed 0,gr7 - cldd @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - cldd @(sp,gr7),gr8,cc2,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - cldd @(sp,gr7),gr8,cc6,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_immed 0,gr7 - cldd @(sp,gr7),gr8,cc3,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - cldd @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - cldd @(sp,gr7),gr8,cc7,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - - pass diff --git a/sim/testsuite/sim/frv/clddf.cgs b/sim/testsuite/sim/frv/clddf.cgs deleted file mode 100644 index c5416ed4c37..00000000000 --- a/sim/testsuite/sim/frv/clddf.cgs +++ /dev/null @@ -1,174 +0,0 @@ -# frv testcase for clddf @($GRi,$GRj),$FRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global clddf -clddf: - set_spr_immed 0x1b1b,cccr - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_immed 0,gr7 - clddf @(sp,gr7),fr8,cc0,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddf @(sp,gr7),fr8,cc0,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - clddf @(sp,gr7),fr8,cc4,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_immed 0,gr7 - clddf @(sp,gr7),fr8,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddf @(sp,gr7),fr8,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - clddf @(sp,gr7),fr8,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_immed 0,gr7 - clddf @(sp,gr7),fr8,cc1,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddf @(sp,gr7),fr8,cc1,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - clddf @(sp,gr7),fr8,cc5,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_immed 0,gr7 - clddf @(sp,gr7),fr8,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddf @(sp,gr7),fr8,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - clddf @(sp,gr7),fr8,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_immed 0,gr7 - clddf @(sp,gr7),fr8,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddf @(sp,gr7),fr8,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - clddf @(sp,gr7),fr8,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_immed 0,gr7 - clddf @(sp,gr7),fr8,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddf @(sp,gr7),fr8,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - clddf @(sp,gr7),fr8,cc7,1 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - pass diff --git a/sim/testsuite/sim/frv/clddfu.cgs b/sim/testsuite/sim/frv/clddfu.cgs deleted file mode 100644 index ab981aa1389..00000000000 --- a/sim/testsuite/sim/frv/clddfu.cgs +++ /dev/null @@ -1,212 +0,0 @@ -# frv testcase for clddfu @($GRi,$GRj),$FRk,$CCi,$ccond -# mach: all - - .include "testutils.inc" - - start - - .global clddfu -clddfu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr21 - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_immed 0,gr7 - clddfu @(sp,gr7),fr8,cc0,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddfu @(sp,gr7),fr8,cc0,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 8,sp - set_gr_immed -8,gr7 - clddfu @(sp,gr7),fr8,cc4,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_gr_gr sp,gr20 - - set_gr_gr sp,gr21 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_immed 0,gr7 - clddfu @(sp,gr7),fr8,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,gr20 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddfu @(sp,gr7),fr8,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 16,gr20 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - clddfu @(sp,gr7),fr8,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - test_gr_gr sp,gr20 - - set_gr_gr sp,gr21 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_immed 0,gr7 - clddfu @(sp,gr7),fr8,cc1,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddfu @(sp,gr7),fr8,cc1,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 8,sp - set_gr_immed -8,gr7 - clddfu @(sp,gr7),fr8,cc5,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_gr_gr sp,gr20 - - set_gr_gr sp,gr21 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_immed 0,gr7 - clddfu @(sp,gr7),fr8,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,gr20 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddfu @(sp,gr7),fr8,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 16,gr20 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - clddfu @(sp,gr7),fr8,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - test_gr_gr sp,gr20 - - set_gr_gr sp,gr21 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_immed 0,gr7 - clddfu @(sp,gr7),fr8,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,gr20 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddfu @(sp,gr7),fr8,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 16,gr20 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - clddfu @(sp,gr7),fr8,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - test_gr_gr sp,gr20 - - set_gr_gr sp,gr21 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_immed 0,gr7 - clddfu @(sp,gr7),fr8,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,gr20 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddfu @(sp,gr7),fr8,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 16,gr20 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - clddfu @(sp,gr7),fr8,cc7,1 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - test_gr_gr sp,gr20 - - pass diff --git a/sim/testsuite/sim/frv/clddu.cgs b/sim/testsuite/sim/frv/clddu.cgs deleted file mode 100644 index 91df6d8f43e..00000000000 --- a/sim/testsuite/sim/frv/clddu.cgs +++ /dev/null @@ -1,219 +0,0 @@ -# frv testcase for clddu @($GRi,$GRj),$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global clddu -clddu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr21 - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_immed 0,gr7 - clddu @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddu @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 8,sp - set_gr_immed -8,gr7 - clddu @(sp,gr7),gr8,cc4,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_immed 0,gr7 - clddu @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,gr20 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddu @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 16,gr20 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - clddu @(sp,gr7),gr8,cc4,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_immed 0,gr7 - clddu @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddu @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 8,sp - set_gr_immed -8,gr7 - clddu @(sp,gr7),gr8,cc5,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_immed 0,gr7 - clddu @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,gr20 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddu @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 16,gr20 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - clddu @(sp,gr7),gr8,cc5,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_immed 0,gr7 - clddu @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,gr20 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddu @(sp,gr7),gr8,cc2,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 16,gr20 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - clddu @(sp,gr7),gr8,cc6,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_immed 0,gr7 - clddu @(sp,gr7),gr8,cc3,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,gr20 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - clddu @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 16,gr20 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - clddu @(sp,gr7),gr8,cc7,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_gr sp,gr20 - - set_gr_gr gr21,gr8 - inc_gr_immed -12,gr8 - set_gr_immed 8,gr7 - clddu @(gr8,gr7),gr8,cc0,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - - pass diff --git a/sim/testsuite/sim/frv/cldf.cgs b/sim/testsuite/sim/frv/cldf.cgs deleted file mode 100644 index 011a02a3e85..00000000000 --- a/sim/testsuite/sim/frv/cldf.cgs +++ /dev/null @@ -1,126 +0,0 @@ -# frv testcase for cldf @($GRi,$GRj),$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cldf -cldf: - set_spr_immed 0x1b1b,cccr - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldf @(sp,gr7),fr8,cc0,1 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldf @(sp,gr7),fr8,cc0,1 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cldf @(sp,gr7),fr8,cc4,1 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldf @(sp,gr7),fr8,cc0,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldf @(sp,gr7),fr8,cc0,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cldf @(sp,gr7),fr8,cc4,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldf @(sp,gr7),fr8,cc1,0 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldf @(sp,gr7),fr8,cc1,0 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cldf @(sp,gr7),fr8,cc5,0 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldf @(sp,gr7),fr8,cc1,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldf @(sp,gr7),fr8,cc1,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cldf @(sp,gr7),fr8,cc5,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldf @(sp,gr7),fr8,cc2,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldf @(sp,gr7),fr8,cc2,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cldf @(sp,gr7),fr8,cc6,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldf @(sp,gr7),fr8,cc3,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldf @(sp,gr7),fr8,cc3,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cldf @(sp,gr7),fr8,cc7,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - pass diff --git a/sim/testsuite/sim/frv/cldfu.cgs b/sim/testsuite/sim/frv/cldfu.cgs deleted file mode 100644 index d4abef00c96..00000000000 --- a/sim/testsuite/sim/frv/cldfu.cgs +++ /dev/null @@ -1,164 +0,0 @@ -# frv testcase for cldfu @($GRi,$GRj),$FRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cldfu -cldfu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr21 - - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldfu @(sp,gr7),fr8,cc0,1 - test_fr_limmed 0xdead,0xbeef,fr8 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldfu @(sp,gr7),fr8,cc0,1 - test_fr_limmed 0xdead,0xbeef,fr8 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 4,sp - set_gr_immed -4,gr7 - cldfu @(sp,gr7),fr8,cc4,1 - test_fr_limmed 0xdead,0xbeef,fr8 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldfu @(sp,gr7),fr8,cc0,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,gr20 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldfu @(sp,gr7),fr8,cc0,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 8,gr20 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cldfu @(sp,gr7),fr8,cc4,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldfu @(sp,gr7),fr8,cc1,0 - test_fr_limmed 0xdead,0xbeef,fr8 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldfu @(sp,gr7),fr8,cc1,0 - test_fr_limmed 0xdead,0xbeef,fr8 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 4,sp - set_gr_immed -4,gr7 - cldfu @(sp,gr7),fr8,cc5,0 - test_fr_limmed 0xdead,0xbeef,fr8 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldfu @(sp,gr7),fr8,cc1,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,gr20 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldfu @(sp,gr7),fr8,cc1,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 8,gr20 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cldfu @(sp,gr7),fr8,cc5,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldfu @(sp,gr7),fr8,cc2,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,gr20 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldfu @(sp,gr7),fr8,cc2,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 8,gr20 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cldfu @(sp,gr7),fr8,cc6,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldfu @(sp,gr7),fr8,cc3,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,gr20 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldfu @(sp,gr7),fr8,cc3,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 8,gr20 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cldfu @(sp,gr7),fr8,cc7,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - pass diff --git a/sim/testsuite/sim/frv/cldhf.cgs b/sim/testsuite/sim/frv/cldhf.cgs deleted file mode 100644 index 26972ed000d..00000000000 --- a/sim/testsuite/sim/frv/cldhf.cgs +++ /dev/null @@ -1,114 +0,0 @@ -# frv testcase for cldhf @($GRi,$GRj),$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cldhf -cldhf: - set_spr_immed 0x1b1b,cccr - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldhf @(sp,gr7),fr8,cc0,1 - test_fr_limmed 0x0000,0xdead,fr8 - - set_gr_immed 2,gr7 - cldhf @(sp,gr7),fr8,cc0,1 - test_fr_limmed 0x0000,0xbeef,fr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldhf @(sp,gr7),fr8,cc4,1 - test_fr_limmed 0x0000,0x0000,fr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldhf @(sp,gr7),fr8,cc0,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_gr_immed 2,gr7 - cldhf @(sp,gr7),fr8,cc0,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldhf @(sp,gr7),fr8,cc4,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldhf @(sp,gr7),fr8,cc1,0 - test_fr_limmed 0x0000,0xdead,fr8 - - set_gr_immed 2,gr7 - cldhf @(sp,gr7),fr8,cc1,0 - test_fr_limmed 0x0000,0xbeef,fr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldhf @(sp,gr7),fr8,cc5,0 - test_fr_limmed 0x0000,0x0000,fr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldhf @(sp,gr7),fr8,cc1,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_gr_immed 2,gr7 - cldhf @(sp,gr7),fr8,cc1,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldhf @(sp,gr7),fr8,cc5,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldhf @(sp,gr7),fr8,cc2,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_gr_immed 2,gr7 - cldhf @(sp,gr7),fr8,cc2,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldhf @(sp,gr7),fr8,cc6,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldhf @(sp,gr7),fr8,cc3,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_gr_immed 2,gr7 - cldhf @(sp,gr7),fr8,cc3,0 - test_fr_limmed 0xbeef,0xdead,fr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldhf @(sp,gr7),fr8,cc7,1 - test_fr_limmed 0xbeef,0xdead,fr8 - - pass diff --git a/sim/testsuite/sim/frv/cldhfu.cgs b/sim/testsuite/sim/frv/cldhfu.cgs deleted file mode 100644 index 062e3984a92..00000000000 --- a/sim/testsuite/sim/frv/cldhfu.cgs +++ /dev/null @@ -1,152 +0,0 @@ -# frv testcase for cldhfu @($GRi,$GRj),$FRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cldhfu -cldhfu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr21 - - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldhfu @(sp,gr7),fr8,cc0,1 - test_fr_limmed 0x0000,0xdead,fr8 - test_gr_gr sp,gr20 - - inc_gr_immed 2,gr20 - set_gr_immed 2,gr7 - cldhfu @(sp,gr7),fr8,cc0,1 - test_fr_limmed 0x0000,0xbeef,fr8 - test_gr_gr sp,gr20 - - inc_gr_immed -2,sp - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldhfu @(sp,gr7),fr8,cc4,1 - test_fr_limmed 0x0000,0x0000,fr8 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldhfu @(sp,gr7),fr8,cc0,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_immed 2,gr7 - cldhfu @(sp,gr7),fr8,cc0,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - inc_gr_immed 4,gr20 - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldhfu @(sp,gr7),fr8,cc4,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldhfu @(sp,gr7),fr8,cc1,0 - test_fr_limmed 0x0000,0xdead,fr8 - test_gr_gr sp,gr20 - - inc_gr_immed 2,gr20 - set_gr_immed 2,gr7 - cldhfu @(sp,gr7),fr8,cc1,0 - test_fr_limmed 0x0000,0xbeef,fr8 - test_gr_gr sp,gr20 - - inc_gr_immed -2,sp - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldhfu @(sp,gr7),fr8,cc5,0 - test_fr_limmed 0x0000,0x0000,fr8 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldhfu @(sp,gr7),fr8,cc1,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_immed 2,gr7 - cldhfu @(sp,gr7),fr8,cc1,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - inc_gr_immed 4,gr20 - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldhfu @(sp,gr7),fr8,cc5,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldhfu @(sp,gr7),fr8,cc2,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_immed 2,gr7 - cldhfu @(sp,gr7),fr8,cc2,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - inc_gr_immed 4,gr20 - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldhfu @(sp,gr7),fr8,cc6,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - cldhfu @(sp,gr7),fr8,cc3,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - set_gr_immed 2,gr7 - cldhfu @(sp,gr7),fr8,cc3,0 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - inc_gr_immed 4,gr20 - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldhfu @(sp,gr7),fr8,cc7,1 - test_fr_limmed 0xbeef,0xdead,fr8 - test_gr_gr sp,gr20 - - pass diff --git a/sim/testsuite/sim/frv/cldq.cgs b/sim/testsuite/sim/frv/cldq.cgs deleted file mode 100644 index bfb433b5e31..00000000000 --- a/sim/testsuite/sim/frv/cldq.cgs +++ /dev/null @@ -1,276 +0,0 @@ -# frv testcase for cldq @($GRi,$GRj),$GRk,$CCi,$cond -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global cldq -cldq: - set_spr_immed 0x1b1b,cccr - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_immed 0,gr7 - cldq @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - cldq @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - cldq @(sp,gr7),gr8,cc4,1 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_immed 0,gr7 - cldq @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - cldq @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - cldq @(sp,gr7),gr8,cc4,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_immed 0,gr7 - cldq @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - cldq @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - cldq @(sp,gr7),gr8,cc5,0 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_immed 0,gr7 - cldq @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - cldq @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - cldq @(sp,gr7),gr8,cc5,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_immed 0,gr7 - cldq @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - cldq @(sp,gr7),gr8,cc2,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - cldq @(sp,gr7),gr8,cc6,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_immed 0,gr7 - cldq @(sp,gr7),gr8,cc3,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - cldq @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - cldq @(sp,gr7),gr8,cc7,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - - pass diff --git a/sim/testsuite/sim/frv/cldqu.cgs b/sim/testsuite/sim/frv/cldqu.cgs deleted file mode 100644 index fa0949a876e..00000000000 --- a/sim/testsuite/sim/frv/cldqu.cgs +++ /dev/null @@ -1,318 +0,0 @@ -# frv testcase for cldqu @($GRi,$GRj),$GRk,$CCi,$cond -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global cldqu -cldqu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr21 - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_gr sp,gr20 - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_immed 0,gr7 - cldqu @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - cldqu @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 16,sp - set_gr_immed -16,gr7 - cldqu @(sp,gr7),gr8,cc4,1 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_gr sp,gr20 - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_immed 0,gr7 - cldqu @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,gr20 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - cldqu @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 32,gr20 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - cldqu @(sp,gr7),gr8,cc4,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_gr sp,gr20 - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_immed 0,gr7 - cldqu @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - cldqu @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 16,sp - set_gr_immed -16,gr7 - cldqu @(sp,gr7),gr8,cc5,0 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_gr sp,gr20 - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_immed 0,gr7 - cldqu @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,gr20 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - cldqu @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 32,gr20 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - cldqu @(sp,gr7),gr8,cc5,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_gr sp,gr20 - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_immed 0,gr7 - cldqu @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,gr20 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - cldqu @(sp,gr7),gr8,cc2,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 32,gr20 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - cldqu @(sp,gr7),gr8,cc6,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_gr sp,gr20 - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_immed 0,gr7 - cldqu @(sp,gr7),gr8,cc3,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,gr20 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - cldqu @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 32,gr20 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - cldqu @(sp,gr7),gr8,cc7,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - test_gr_gr sp,gr20 - - set_gr_gr gr21,gr8 - inc_gr_immed -28,gr8 - set_gr_immed 16,gr7 - cldqu @(gr8,gr7),gr8,cc0,1 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - - pass diff --git a/sim/testsuite/sim/frv/cldsb.cgs b/sim/testsuite/sim/frv/cldsb.cgs deleted file mode 100644 index ea8dd943ba3..00000000000 --- a/sim/testsuite/sim/frv/cldsb.cgs +++ /dev/null @@ -1,114 +0,0 @@ -# frv testcase for cldsb @($GRi,$GRj),$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cldsb -cldsb: - set_spr_immed 0x1b1b,cccr - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldsb @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xffff,0xffde,gr8 - - set_gr_immed 1,gr7 - cldsb @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xffff,0xffad,gr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldsb @(sp,gr7),gr8,cc4,1 - test_gr_immed 0,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldsb @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 1,gr7 - cldsb @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldsb @(sp,gr7),gr8,cc4,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldsb @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xffff,0xffde,gr8 - - set_gr_immed 1,gr7 - cldsb @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xffff,0xffad,gr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldsb @(sp,gr7),gr8,cc5,0 - test_gr_immed 0,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldsb @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 1,gr7 - cldsb @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldsb @(sp,gr7),gr8,cc5,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldsb @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 1,gr7 - cldsb @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldsb @(sp,gr7),gr8,cc6,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldsb @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 1,gr7 - cldsb @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldsb @(sp,gr7),gr8,cc7,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - pass diff --git a/sim/testsuite/sim/frv/cldsbu.cgs b/sim/testsuite/sim/frv/cldsbu.cgs deleted file mode 100644 index a4057f15696..00000000000 --- a/sim/testsuite/sim/frv/cldsbu.cgs +++ /dev/null @@ -1,162 +0,0 @@ -# frv testcase for cldsbu @($GRi,$GRj),$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cldsbu -cldsbu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr20 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldsbu @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xffff,0xffde,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 1,gr9 - set_gr_immed 1,gr7 - cldsbu @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xffff,0xffad,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 2,gr9 - inc_gr_immed -1,sp - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldsbu @(sp,gr7),gr8,cc4,1 - test_gr_immed 0,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldsbu @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_immed 1,gr7 - cldsbu @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - inc_gr_immed 4,gr9 - set_gr_immed -1,gr7 - cldsbu @(sp,gr7),gr8,cc4,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldsbu @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xffff,0xffde,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 1,gr9 - set_gr_immed 1,gr7 - cldsbu @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xffff,0xffad,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 2,gr9 - inc_gr_immed -1,sp - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldsbu @(sp,gr7),gr8,cc5,0 - test_gr_immed 0,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldsbu @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_immed 1,gr7 - cldsbu @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - inc_gr_immed 4,gr9 - set_gr_immed -1,gr7 - cldsbu @(sp,gr7),gr8,cc5,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldsbu @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_immed 1,gr7 - cldsbu @(sp,gr7),gr8,cc2,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - inc_gr_immed 4,gr9 - set_gr_immed -1,gr7 - cldsbu @(sp,gr7),gr8,cc6,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldsbu @(sp,gr7),gr8,cc3,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_immed 1,gr7 - cldsbu @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - inc_gr_immed 4,gr9 - set_gr_immed -1,gr7 - cldsbu @(sp,gr7),gr8,cc7,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr8 - set_gr_immed 1,gr7 - cldsbu @(gr8,gr7),gr8,cc0,1 - test_gr_limmed 0xffff,0xffad,gr8 - - pass - diff --git a/sim/testsuite/sim/frv/cldsh.cgs b/sim/testsuite/sim/frv/cldsh.cgs deleted file mode 100644 index 091d72036af..00000000000 --- a/sim/testsuite/sim/frv/cldsh.cgs +++ /dev/null @@ -1,114 +0,0 @@ -# frv testcase for cldsh @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global cldsh -cldsh: - set_spr_immed 0x1b1b,cccr - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldsh @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xffff,0xdead,gr8 - - set_gr_immed 2,gr7 - cldsh @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xffff,0xbeef,gr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldsh @(sp,gr7),gr8,cc4,1 - test_gr_immed 0,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldsh @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 2,gr7 - cldsh @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldsh @(sp,gr7),gr8,cc4,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldsh @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xffff,0xdead,gr8 - - set_gr_immed 2,gr7 - cldsh @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xffff,0xbeef,gr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldsh @(sp,gr7),gr8,cc5,0 - test_gr_immed 0,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldsh @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 2,gr7 - cldsh @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldsh @(sp,gr7),gr8,cc5,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldsh @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 2,gr7 - cldsh @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldsh @(sp,gr7),gr8,cc6,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldsh @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 2,gr7 - cldsh @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldsh @(sp,gr7),gr8,cc7,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - pass diff --git a/sim/testsuite/sim/frv/cldshu.cgs b/sim/testsuite/sim/frv/cldshu.cgs deleted file mode 100644 index 491352eb58b..00000000000 --- a/sim/testsuite/sim/frv/cldshu.cgs +++ /dev/null @@ -1,159 +0,0 @@ -# frv testcase for cldshu @($GRi,$GRj),$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cldshu -cldshu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr20 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldshu @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xffff,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 2,gr9 - set_gr_immed 2,gr7 - cldshu @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xffff,0xbeef,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed -2,sp - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldshu @(sp,gr7),gr8,cc4,1 - test_gr_immed 0,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldshu @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_immed 2,gr7 - cldshu @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 4,gr9 - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldshu @(sp,gr7),gr8,cc4,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldshu @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xffff,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 2,gr9 - set_gr_immed 2,gr7 - cldshu @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xffff,0xbeef,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed -2,sp - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldshu @(sp,gr7),gr8,cc5,0 - test_gr_immed 0,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldshu @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_immed 2,gr7 - cldshu @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 4,gr9 - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldshu @(sp,gr7),gr8,cc5,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldshu @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_immed 2,gr7 - cldshu @(sp,gr7),gr8,cc2,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 4,gr9 - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldshu @(sp,gr7),gr8,cc6,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldshu @(sp,gr7),gr8,cc3,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_immed 2,gr7 - cldshu @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 4,gr9 - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - cldshu @(sp,gr7),gr8,cc7,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr8 - set_gr_immed 2,gr7 - cldshu @(gr8,gr7),gr8,cc0,1 - test_gr_limmed 0xffff,0xbeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/cldu.cgs b/sim/testsuite/sim/frv/cldu.cgs deleted file mode 100644 index 61cf606132a..00000000000 --- a/sim/testsuite/sim/frv/cldu.cgs +++ /dev/null @@ -1,172 +0,0 @@ -# frv testcase for cldu @($GRi,$GRj),$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cldu -cldu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr20 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldu @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_gr sp,gr9 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldu @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_gr sp,gr9 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 4,sp - set_gr_immed -4,gr7 - cldu @(sp,gr7),gr8,cc4,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_gr sp,gr9 - - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldu @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,gr9 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldu @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 8,gr9 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cldu @(sp,gr7),gr8,cc4,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldu @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_gr sp,gr9 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldu @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_gr sp,gr9 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 4,sp - set_gr_immed -4,gr7 - cldu @(sp,gr7),gr8,cc5,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_gr sp,gr9 - - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldu @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,gr9 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldu @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 8,gr9 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cldu @(sp,gr7),gr8,cc5,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldu @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,gr9 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldu @(sp,gr7),gr8,cc2,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 8,gr9 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cldu @(sp,gr7),gr8,cc6,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldu @(sp,gr7),gr8,cc3,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,gr9 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - cldu @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 8,gr9 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - cldu @(sp,gr7),gr8,cc7,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr8 - inc_gr_immed -4,gr8 - set_gr_immed 4,gr7 - cldu @(gr8,gr7),gr8,cc0,1 - test_gr_limmed 0xdead,0xbeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/cldub.cgs b/sim/testsuite/sim/frv/cldub.cgs deleted file mode 100644 index b1f07766ddd..00000000000 --- a/sim/testsuite/sim/frv/cldub.cgs +++ /dev/null @@ -1,114 +0,0 @@ -# frv testcase for cldub @($GRi,$GRj),$GRk,$cci,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cldub -cldub: - set_spr_immed 0x1b1b,cccr - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldub @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0x0000,0x00de,gr8 - - set_gr_immed 1,gr7 - cldub @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0x0000,0x00ad,gr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldub @(sp,gr7),gr8,cc4,1 - test_gr_limmed 0x0000,0x0000,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldub @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 1,gr7 - cldub @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldub @(sp,gr7),gr8,cc4,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldub @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0x0000,0x00de,gr8 - - set_gr_immed 1,gr7 - cldub @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0x0000,0x00ad,gr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldub @(sp,gr7),gr8,cc5,0 - test_gr_limmed 0x0000,0x0000,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldub @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 1,gr7 - cldub @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldub @(sp,gr7),gr8,cc5,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldub @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 1,gr7 - cldub @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldub @(sp,gr7),gr8,cc6,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - cldub @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 1,gr7 - cldub @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldub @(sp,gr7),gr8,cc7,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - pass diff --git a/sim/testsuite/sim/frv/cldubu.cgs b/sim/testsuite/sim/frv/cldubu.cgs deleted file mode 100644 index c9f9579da9d..00000000000 --- a/sim/testsuite/sim/frv/cldubu.cgs +++ /dev/null @@ -1,155 +0,0 @@ -# frv testcase for cldubu @($GRi,$GRj),$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cldubu -cldubu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr20 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldubu @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0x0000,0x00de,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 1,gr9 - set_gr_immed 1,gr7 - cldubu @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0x0000,0x00ad,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 2,gr9 - inc_gr_immed -1,sp - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldubu @(sp,gr7),gr8,cc4,1 - test_gr_limmed 0x0000,0x0000,gr8 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldubu @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_immed 1,gr7 - cldubu @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 4,gr9 - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldubu @(sp,gr7),gr8,cc4,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldubu @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0x0000,0x00de,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 1,gr9 - set_gr_immed 1,gr7 - cldubu @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0x0000,0x00ad,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 2,gr9 - inc_gr_immed -1,sp - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldubu @(sp,gr7),gr8,cc5,0 - test_gr_limmed 0x0000,0x0000,gr8 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldubu @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_immed 1,gr7 - cldubu @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 4,gr9 - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldubu @(sp,gr7),gr8,cc5,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldubu @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_immed 1,gr7 - cldubu @(sp,gr7),gr8,cc2,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 4,gr9 - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldubu @(sp,gr7),gr8,cc6,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - cldubu @(sp,gr7),gr8,cc3,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_immed 1,gr7 - cldubu @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 4,gr9 - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - cldubu @(sp,gr7),gr8,cc7,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr8 - set_gr_immed 1,gr7 - cldubu @(gr8,gr7),gr8,cc0,1 - test_gr_limmed 0x0000,0x00ad,gr8 - - pass diff --git a/sim/testsuite/sim/frv/clduh.cgs b/sim/testsuite/sim/frv/clduh.cgs deleted file mode 100644 index a9e505c0727..00000000000 --- a/sim/testsuite/sim/frv/clduh.cgs +++ /dev/null @@ -1,114 +0,0 @@ -# frv testcase for clduh @($GRi,$GRj),$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global clduh -clduh: - set_spr_immed 0x1b1b,cccr - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - clduh @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0x0000,0xdead,gr8 - - set_gr_immed 2,gr7 - clduh @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0x0000,0xbeef,gr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - clduh @(sp,gr7),gr8,cc4,1 - test_gr_limmed 0x0000,0x0000,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - clduh @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 2,gr7 - clduh @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - clduh @(sp,gr7),gr8,cc4,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - clduh @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0x0000,0xdead,gr8 - - set_gr_immed 2,gr7 - clduh @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0x0000,0xbeef,gr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - clduh @(sp,gr7),gr8,cc5,0 - test_gr_limmed 0x0000,0x0000,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - clduh @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 2,gr7 - clduh @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - clduh @(sp,gr7),gr8,cc5,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - clduh @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 2,gr7 - clduh @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - clduh @(sp,gr7),gr8,cc6,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - clduh @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 2,gr7 - clduh @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - clduh @(sp,gr7),gr8,cc7,1 - test_gr_limmed 0xbeef,0xdead,gr8 - - pass diff --git a/sim/testsuite/sim/frv/clduhu.cgs b/sim/testsuite/sim/frv/clduhu.cgs deleted file mode 100644 index 80eb381c384..00000000000 --- a/sim/testsuite/sim/frv/clduhu.cgs +++ /dev/null @@ -1,159 +0,0 @@ -# frv testcase for clduhu @($GRi,$GRj),$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global clduhu -clduhu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr20 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - clduhu @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0x0000,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 2,gr9 - set_gr_immed 2,gr7 - clduhu @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0x0000,0xbeef,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed -2,sp - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - clduhu @(sp,gr7),gr8,cc4,1 - test_gr_limmed 0x0000,0x0000,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - clduhu @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_immed 2,gr7 - clduhu @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 4,gr9 - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - clduhu @(sp,gr7),gr8,cc4,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - clduhu @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0x0000,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 2,gr9 - set_gr_immed 2,gr7 - clduhu @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0x0000,0xbeef,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed -2,sp - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - clduhu @(sp,gr7),gr8,cc5,0 - test_gr_limmed 0x0000,0x0000,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - clduhu @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_immed 2,gr7 - clduhu @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 4,gr9 - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - clduhu @(sp,gr7),gr8,cc5,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - clduhu @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_immed 2,gr7 - clduhu @(sp,gr7),gr8,cc2,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 4,gr9 - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - clduhu @(sp,gr7),gr8,cc6,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - clduhu @(sp,gr7),gr8,cc3,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_immed 2,gr7 - clduhu @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 4,gr9 - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - clduhu @(sp,gr7),gr8,cc7,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_gr sp,gr9 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr8 - set_gr_immed 2,gr7 - clduhu @(gr8,gr7),gr8,cc0,1 - test_gr_limmed 0x0000,0xbeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/clrfa.cgs b/sim/testsuite/sim/frv/clrfa.cgs deleted file mode 100644 index 8bba605e8df..00000000000 --- a/sim/testsuite/sim/frv/clrfa.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# frv testcase for clrfa -# mach: frv - - .include "testutils.inc" - - start - - .global clrfa -clrfa: - nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 - or_spr_immed 0x00100000,fner1 - nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 - or_spr_immed 0x00200000,fner1 - nldfi @(sp,0),fr52 ; Activate fr52 with nesr.fr==1 - or_spr_immed 0x00100000,fner0 - - clrfa - test_spr_immed 0x00000000,fner1 - test_spr_immed 0x00000000,fner0 - test_spr_immed 0,nesr0 - test_spr_immed 0,neear0 - test_spr_immed 0x94800401,nesr1 - test_spr_gr neear1,sp - test_spr_immed 0,nesr2 - test_spr_immed 0,neear2 - - pass diff --git a/sim/testsuite/sim/frv/clrfr.cgs b/sim/testsuite/sim/frv/clrfr.cgs deleted file mode 100644 index 9112815236b..00000000000 --- a/sim/testsuite/sim/frv/clrfr.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# frv testcase for clrfr $FRk -# mach: frv - - .include "testutils.inc" - - start - - .global clrfr -clrfr: - nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 - or_spr_immed 0x00100000,fner1 - nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 - or_spr_immed 0x00200000,fner1 - nldfi @(sp,0),fr52 ; Activate fr52 with nesr.fr==1 - or_spr_immed 0x00100000,fner0 - - clrfr fr20 - test_spr_immed 0x00200000,fner1 - test_spr_immed 0x00100000,fner0 - test_spr_immed 0,nesr0 - test_spr_immed 0,neear0 - test_spr_immed 0x94800401,nesr1 - test_spr_gr neear1,sp - test_spr_immed 0xf4800801,nesr2 - test_spr_gr neear2,sp - - pass diff --git a/sim/testsuite/sim/frv/clrga.cgs b/sim/testsuite/sim/frv/clrga.cgs deleted file mode 100644 index 9e9a9a9f1c8..00000000000 --- a/sim/testsuite/sim/frv/clrga.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# frv testcase for clrga -# mach: frv - - .include "testutils.inc" - - start - - .global clrga -clrga: - nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 - or_spr_immed 0x00100000,gner1 - nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 - or_spr_immed 0x00200000,gner1 - nldi @(sp,0),gr52 ; Activate gr52 with nesr.fr==0 - or_spr_immed 0x00100000,gner0 - - clrga - test_spr_immed 0x00000000,gner1 - test_spr_immed 0x00000000,gner0 - test_spr_immed 0,nesr0 - test_spr_immed 0,neear0 - test_spr_immed 0xd4800401,nesr1 - test_spr_gr neear1,sp - test_spr_immed 0,nesr2 - test_spr_immed 0,neear2 - - pass diff --git a/sim/testsuite/sim/frv/clrgr.cgs b/sim/testsuite/sim/frv/clrgr.cgs deleted file mode 100644 index 049b9e371e7..00000000000 --- a/sim/testsuite/sim/frv/clrgr.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# frv testcase for clrgr $GRk -# mach: frv - - .include "testutils.inc" - - start - - .global clrgr -clrgr: - nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 - or_spr_immed 0x00100000,gner1 - nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 - or_spr_immed 0x00200000,gner1 - nldi @(sp,0),gr52 ; Activate gr52 with nesr.fr==0 - or_spr_immed 0x00100000,gner0 - - clrgr gr20 - test_spr_immed 0x00200000,gner1 - test_spr_immed 0x00100000,gner0 - test_spr_immed 0,nesr0 - test_spr_immed 0,neear0 - test_spr_immed 0xd4800401,nesr1 - test_spr_gr neear1,sp - test_spr_immed 0xb4800801,nesr2 - test_spr_gr neear2,sp - - pass diff --git a/sim/testsuite/sim/frv/cmaddhss.cgs b/sim/testsuite/sim/frv/cmaddhss.cgs deleted file mode 100644 index 1f04e678eca..00000000000 --- a/sim/testsuite/sim/frv/cmaddhss.cgs +++ /dev/null @@ -1,562 +0,0 @@ -# frv testcase for cmaddhss $FRi,$FRj,$FRj,$CCi,$cond -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global maddhss -maddhss: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmaddhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0xbeef,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x2345,0x6789,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmaddhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x1233,0x5677,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhss fr10,fr11,fr12,cc4,1 - test_fr_limmed 0x7fff,0x7fff,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc4,1 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc4,1 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmaddhss.p fr10,fr10,fr12,cc4,1 - cmaddhss fr11,fr11,fr13,cc4,1 - test_fr_limmed 0x0002,0x0002,fr12 - test_fr_limmed 0x7fff,0x7fff,fr13 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmaddhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0xbeef,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x2345,0x6789,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmaddhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x1233,0x5677,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhss fr10,fr11,fr12,cc5,0 - test_fr_limmed 0x7fff,0x7fff,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc5,0 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc5,0 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmaddhss.p fr10,fr10,fr12,cc5,0 - cmaddhss fr11,fr11,fr13,cc5,0 - test_fr_limmed 0x0002,0x0002,fr12 - test_fr_limmed 0x7fff,0x7fff,fr13 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmaddhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmaddhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhss fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmaddhss.p fr10,fr10,fr12,cc4,0 - cmaddhss fr11,fr11,fr13,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmaddhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmaddhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhss fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmaddhss.p fr10,fr10,fr12,cc5,1 - cmaddhss fr11,fr11,fr13,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmaddhss fr10,fr11,fr12,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhss fr10,fr11,fr12,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmaddhss fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhss fr10,fr11,fr12,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc6,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmaddhss.p fr10,fr10,fr12,cc6,1 - cmaddhss fr11,fr11,fr13,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set -; - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmaddhss fr10,fr11,fr12,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhss fr10,fr11,fr12,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmaddhss fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhss fr10,fr11,fr12,cc7,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc7,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc7,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmaddhss.p fr10,fr10,fr12,cc7,1 - cmaddhss fr11,fr11,fr13,cc7,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - pass diff --git a/sim/testsuite/sim/frv/cmaddhus.cgs b/sim/testsuite/sim/frv/cmaddhus.cgs deleted file mode 100644 index 76da81d5548..00000000000 --- a/sim/testsuite/sim/frv/cmaddhus.cgs +++ /dev/null @@ -1,496 +0,0 @@ -# frv testcase for cmaddhus $FRi,$FRj,$FRj,$CCi,$cond -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global cmaddhus -cmaddhus: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmaddhus fr10,fr11,fr12,cc0,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc0,1 - test_fr_limmed 0xbeef,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhus fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x2345,0x6789,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhus fr10,fr11,fr12,cc4,1 - test_fr_limmed 0x8000,0x7fff,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xfffe,0xfffe,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmaddhus fr10,fr11,fr12,cc4,1 - test_fr_limmed 0xffff,0xffff,fr12 - test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhus fr10,fr11,fr12,cc4,1 - test_fr_limmed 0xffff,0xffff,fr12 - test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmaddhus.p fr10,fr10,fr12,cc4,1 - cmaddhus fr11,fr11,fr13,cc4,1 - test_fr_limmed 0x0002,0x0002,fr12 - test_fr_limmed 0xffff,0xffff,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmaddhus fr10,fr11,fr12,cc1,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc1,0 - test_fr_limmed 0xbeef,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhus fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x2345,0x6789,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhus fr10,fr11,fr12,cc5,0 - test_fr_limmed 0x8000,0x7fff,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xfffe,0xfffe,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmaddhus fr10,fr11,fr12,cc5,0 - test_fr_limmed 0xffff,0xffff,fr12 - test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhus fr10,fr11,fr12,cc5,0 - test_fr_limmed 0xffff,0xffff,fr12 - test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmaddhus.p fr10,fr10,fr12,cc5,0 - cmaddhus fr11,fr11,fr13,cc5,0 - test_fr_limmed 0x0002,0x0002,fr12 - test_fr_limmed 0xffff,0xffff,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0x0000,fr10 - set_fr_iimmed 0x0000,0xdead,fr11 - cmaddhus fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhus fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhus fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xfffe,0xfffe,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmaddhus fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhus fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmaddhus.p fr10,fr10,fr12,cc4,0 - cmaddhus fr11,fr11,fr13,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0x0000,fr10 - set_fr_iimmed 0x0000,0xdead,fr11 - cmaddhus fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhus fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhus fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xfffe,0xfffe,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmaddhus fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhus fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmaddhus.p fr10,fr10,fr12,cc5,1 - cmaddhus fr11,fr11,fr13,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0x0000,fr10 - set_fr_iimmed 0x0000,0xdead,fr11 - cmaddhus fr10,fr11,fr12,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhus fr10,fr11,fr12,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhus fr10,fr11,fr12,cc6,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xfffe,0xfffe,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmaddhus fr10,fr11,fr12,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhus fr10,fr11,fr12,cc6,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmaddhus.p fr10,fr10,fr12,cc6,0 - cmaddhus fr11,fr11,fr13,cc6,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0x0000,fr10 - set_fr_iimmed 0x0000,0xdead,fr11 - cmaddhus fr10,fr11,fr12,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhus fr10,fr11,fr12,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhus fr10,fr11,fr12,cc7,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xfffe,0xfffe,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmaddhus fr10,fr11,fr12,cc7,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhus fr10,fr11,fr12,cc7,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmaddhus.p fr10,fr10,fr12,cc7,0 - cmaddhus fr11,fr11,fr13,cc7,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - pass diff --git a/sim/testsuite/sim/frv/cmand.cgs b/sim/testsuite/sim/frv/cmand.cgs deleted file mode 100644 index 7ed9e4da33e..00000000000 --- a/sim/testsuite/sim/frv/cmand.cgs +++ /dev/null @@ -1,89 +0,0 @@ -# frv testcase for cmand $FRinti,$FRintj,$FRintk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmand -cmand: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmand fr7,fr8,fr8,cc0,1 - test_fr_iimmed 0,fr8 - - set_fr_iimmed 0xffff,0x0000,fr8 - cmand fr7,fr8,fr8,cc0,1 - test_fr_iimmed 0xaaaa0000,fr8 - - set_fr_iimmed 0x0000,0xffff,fr8 - cmand fr7,fr8,fr8,cc4,1 - test_fr_iimmed 0x0000aaaa,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmand fr7,fr8,fr8,cc1,0 - test_fr_iimmed 0,fr8 - - set_fr_iimmed 0xffff,0x0000,fr8 - cmand fr7,fr8,fr8,cc1,0 - test_fr_iimmed 0xaaaa0000,fr8 - - set_fr_iimmed 0x0000,0xffff,fr8 - cmand fr7,fr8,fr8,cc5,0 - test_fr_iimmed 0x0000aaaa,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmand fr7,fr8,fr8,cc0,0 - test_fr_iimmed 0x55555555,fr8 - - set_fr_iimmed 0xffff,0x0000,fr8 - cmand fr7,fr8,fr8,cc0,0 - test_fr_iimmed 0xffff0000,fr8 - - set_fr_iimmed 0x0000,0xffff,fr8 - cmand fr7,fr8,fr8,cc4,0 - test_fr_iimmed 0x0000ffff,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmand fr7,fr8,fr8,cc1,1 - test_fr_iimmed 0x55555555,fr8 - - set_fr_iimmed 0xffff,0x0000,fr8 - cmand fr7,fr8,fr8,cc1,1 - test_fr_iimmed 0xffff0000,fr8 - - set_fr_iimmed 0x0000,0xffff,fr8 - cmand fr7,fr8,fr8,cc5,1 - test_fr_iimmed 0x0000ffff,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmand fr7,fr8,fr8,cc2,0 - test_fr_iimmed 0x55555555,fr8 - - set_fr_iimmed 0xffff,0x0000,fr8 - cmand fr7,fr8,fr8,cc2,1 - test_fr_iimmed 0xffff0000,fr8 - - set_fr_iimmed 0x0000,0xffff,fr8 - cmand fr7,fr8,fr8,cc6,0 - test_fr_iimmed 0x0000ffff,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmand fr7,fr8,fr8,cc3,1 - test_fr_iimmed 0x55555555,fr8 - - set_fr_iimmed 0xffff,0x0000,fr8 - cmand fr7,fr8,fr8,cc3,0 - test_fr_iimmed 0xffff0000,fr8 - - set_fr_iimmed 0x0000,0xffff,fr8 - cmand fr7,fr8,fr8,cc7,1 - test_fr_iimmed 0x0000ffff,fr8 - pass diff --git a/sim/testsuite/sim/frv/cmbtoh.cgs b/sim/testsuite/sim/frv/cmbtoh.cgs deleted file mode 100644 index 5e7c91ae669..00000000000 --- a/sim/testsuite/sim/frv/cmbtoh.cgs +++ /dev/null @@ -1,74 +0,0 @@ -# frv testcase for cmbtoh $FRj,$FRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmbtoh -cmbtoh: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmbtoh fr10,fr12,cc0,1 - test_fr_limmed 0x00de,0x00ad,fr12 - test_fr_limmed 0x00be,0x00ef,fr13 - - set_fr_iimmed 0x1234,0x5678,fr10 - cmbtoh fr10,fr12,cc4,1 - test_fr_limmed 0x0012,0x0034,fr12 - test_fr_limmed 0x0056,0x0078,fr13 - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmbtoh fr10,fr12,cc1,0 - test_fr_limmed 0x00de,0x00ad,fr12 - test_fr_limmed 0x00be,0x00ef,fr13 - - set_fr_iimmed 0x1234,0x5678,fr10 - cmbtoh fr10,fr12,cc5,0 - test_fr_limmed 0x0012,0x0034,fr12 - test_fr_limmed 0x0056,0x0078,fr13 - - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x2222,0x2222,fr13 - set_fr_iimmed 0xdead,0xbeef,fr10 - cmbtoh fr10,fr12,cc0,0 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - set_fr_iimmed 0x1234,0x5678,fr10 - cmbtoh fr10,fr12,cc4,0 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmbtoh fr10,fr12,cc1,1 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - set_fr_iimmed 0x1234,0x5678,fr10 - cmbtoh fr10,fr12,cc5,1 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmbtoh fr10,fr12,cc2,1 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - set_fr_iimmed 0x1234,0x5678,fr10 - cmbtoh fr10,fr12,cc6,0 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmbtoh fr10,fr12,cc3,1 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - set_fr_iimmed 0x1234,0x5678,fr10 - cmbtoh fr10,fr12,cc7,0 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - pass diff --git a/sim/testsuite/sim/frv/cmbtohe.cgs b/sim/testsuite/sim/frv/cmbtohe.cgs deleted file mode 100644 index eb6b51492ee..00000000000 --- a/sim/testsuite/sim/frv/cmbtohe.cgs +++ /dev/null @@ -1,100 +0,0 @@ -# frv testcase for cmbtohe $FRj,$FRk -# mach: frv - - .include "testutils.inc" - - start - - .global cmbtohe -cmbtohe: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmbtohe fr10,fr12,cc0,1 - test_fr_limmed 0x00de,0x00de,fr12 - test_fr_limmed 0x00ad,0x00ad,fr13 - test_fr_limmed 0x00be,0x00be,fr14 - test_fr_limmed 0x00ef,0x00ef,fr15 - - set_fr_iimmed 0x1234,0x5678,fr10 - cmbtohe fr10,fr12,cc4,1 - test_fr_limmed 0x0012,0x0012,fr12 - test_fr_limmed 0x0034,0x0034,fr13 - test_fr_limmed 0x0056,0x0056,fr14 - test_fr_limmed 0x0078,0x0078,fr15 - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmbtohe fr10,fr12,cc1,0 - test_fr_limmed 0x00de,0x00de,fr12 - test_fr_limmed 0x00ad,0x00ad,fr13 - test_fr_limmed 0x00be,0x00be,fr14 - test_fr_limmed 0x00ef,0x00ef,fr15 - - set_fr_iimmed 0x1234,0x5678,fr10 - cmbtohe fr10,fr12,cc5,0 - test_fr_limmed 0x0012,0x0012,fr12 - test_fr_limmed 0x0034,0x0034,fr13 - test_fr_limmed 0x0056,0x0056,fr14 - test_fr_limmed 0x0078,0x0078,fr15 - - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x2222,0x2222,fr13 - set_fr_iimmed 0x3333,0x3333,fr14 - set_fr_iimmed 0x4444,0x4444,fr15 - set_fr_iimmed 0xdead,0xbeef,fr10 - cmbtohe fr10,fr12,cc0,0 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - test_fr_limmed 0x3333,0x3333,fr14 - test_fr_limmed 0x4444,0x4444,fr15 - - set_fr_iimmed 0x1234,0x5678,fr10 - cmbtohe fr10,fr12,cc4,0 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - test_fr_limmed 0x3333,0x3333,fr14 - test_fr_limmed 0x4444,0x4444,fr15 - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmbtohe fr10,fr12,cc1,1 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - test_fr_limmed 0x3333,0x3333,fr14 - test_fr_limmed 0x4444,0x4444,fr15 - - set_fr_iimmed 0x1234,0x5678,fr10 - cmbtohe fr10,fr12,cc5,1 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - test_fr_limmed 0x3333,0x3333,fr14 - test_fr_limmed 0x4444,0x4444,fr15 - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmbtohe fr10,fr12,cc2,1 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - test_fr_limmed 0x3333,0x3333,fr14 - test_fr_limmed 0x4444,0x4444,fr15 - - set_fr_iimmed 0x1234,0x5678,fr10 - cmbtohe fr10,fr12,cc6,0 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - test_fr_limmed 0x3333,0x3333,fr14 - test_fr_limmed 0x4444,0x4444,fr15 - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmbtohe fr10,fr12,cc3,0 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - test_fr_limmed 0x3333,0x3333,fr14 - test_fr_limmed 0x4444,0x4444,fr15 - - set_fr_iimmed 0x1234,0x5678,fr10 - cmbtohe fr10,fr12,cc7,1 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - test_fr_limmed 0x3333,0x3333,fr14 - test_fr_limmed 0x4444,0x4444,fr15 - - pass diff --git a/sim/testsuite/sim/frv/cmcpxis.cgs b/sim/testsuite/sim/frv/cmcpxis.cgs deleted file mode 100644 index ded030078d4..00000000000 --- a/sim/testsuite/sim/frv/cmcpxis.cgs +++ /dev/null @@ -1,971 +0,0 @@ -# frv testcase for cmcpxis $GRi,$GRj,$ACCk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmcpxis -cmcpxis: - set_spr_immed 0x1b1b,cccr - - ; Positive operands - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxis fr7,fr8,acc0,cc0,1 - test_accg_immed 0x00,accg0 - test_acc_immed 26,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxis fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - cmcpxis fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 3,acc0 - - set_fr_iimmed 0x3ff8,2,fr7 ; 15 bit result - set_fr_iimmed 0x0007,2,fr8 - cmcpxis fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0,0x7ffe,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 0x2000,2,fr8 - cmcpxis fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0xc000,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x0001,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 1,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc0,1 - test_accg_immed 0xff,accg0 - test_acc_immed -9,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc0,1 - test_accg_immed 0xff,accg0 - test_acc_immed -6,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc0,1 - test_accg_immed 0xff,accg0 - test_acc_immed -2,acc0 - - set_fr_iimmed 0x2001,0xffff,fr7 ; 15 bit result - set_fr_iimmed 0xffff,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc4,1 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbfff,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0x0003,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc4,1 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x7ffa,acc0 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc4,1 - test_accg_immed 0xff,accg0 - test_acc_limmed 0x8001,0x0000,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x8000,0x0000,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffb,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc4,1 - test_accg_immed 0x00,accg0 - test_acc_immed 26,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 3,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 0x40000000,acc0 - - ; Positive operands - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxis fr7,fr8,acc0,cc1,0 - test_accg_immed 0x00,accg0 - test_acc_immed 26,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxis fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - cmcpxis fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 3,acc0 - - set_fr_iimmed 0x3ff8,2,fr7 ; 15 bit result - set_fr_iimmed 0x0007,2,fr8 - cmcpxis fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0,0x7ffe,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 0x2000,2,fr8 - cmcpxis fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0xc000,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x0001,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 1,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc1,0 - test_accg_immed 0xff,accg0 - test_acc_immed -9,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc1,0 - test_accg_immed 0xff,accg0 - test_acc_immed -6,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc1,0 - test_accg_immed 0xff,accg0 - test_acc_immed -2,acc0 - - set_fr_iimmed 0x2001,0xffff,fr7 ; 15 bit result - set_fr_iimmed 0xffff,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc5,0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbfff,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0x0003,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc5,0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x7ffa,acc0 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc5,0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0x8001,0x0000,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x8000,0x0000,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffb,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc5,0 - test_accg_immed 0x00,accg0 - test_acc_immed 26,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 3,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 0x40000000,acc0 - - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxis fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxis fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - cmcpxis fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 0x0007,2,fr8 - cmcpxis fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 0x2000,2,fr8 - cmcpxis fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 1,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfff9,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0x0003,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffb,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxis fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxis fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - cmcpxis fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 0x0007,2,fr8 - cmcpxis fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 0x2000,2,fr8 - cmcpxis fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 1,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfff9,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0x0003,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffb,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxis fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxis fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - cmcpxis fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 0x0007,2,fr8 - cmcpxis fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 0x2000,2,fr8 - cmcpxis fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 1,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfff9,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0x0003,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffb,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxis fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxis fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - cmcpxis fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 0x0007,2,fr8 - cmcpxis fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 0x2000,2,fr8 - cmcpxis fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 1,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfff9,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0x0003,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffb,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxis fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxis fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - cmcpxis fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 0x0007,2,fr8 - cmcpxis fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 0x2000,2,fr8 - cmcpxis fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 1,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfff9,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0x0003,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffb,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 -; - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxis fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxis fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - cmcpxis fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 0x0007,2,fr8 - cmcpxis fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 0x2000,2,fr8 - cmcpxis fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 1,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfff9,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0x0003,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffb,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxis fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxis fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - cmcpxis fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 0x0007,2,fr8 - cmcpxis fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 0x2000,2,fr8 - cmcpxis fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 1,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0xfffe,1,fr8 - cmcpxis fr7,fr8,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfff9,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0x0003,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffb,0xfffd,fr8 - cmcpxis fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr8 - cmcpxis fr7,fr8,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x7fff,fr8 - cmcpxis fr7,fr8,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxis fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - pass diff --git a/sim/testsuite/sim/frv/cmcpxiu.cgs b/sim/testsuite/sim/frv/cmcpxiu.cgs deleted file mode 100644 index 90a92bc0ce9..00000000000 --- a/sim/testsuite/sim/frv/cmcpxiu.cgs +++ /dev/null @@ -1,508 +0,0 @@ -# frv testcase for cmcpxiu $GRi,$GRj,$GRk,$CCi,$cond -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global cmcpxiu -cmcpxiu: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxiu fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 26,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 1,3,fr8 - cmcpxiu fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 5,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxiu fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 0x0001,2,fr8 - cmcpxiu fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x7fff,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 0x0001,2,fr8 - cmcpxiu fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8001,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 17 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 0x00010001,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x0000,0x8000,fr8 - cmcpxiu fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0000,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; almost max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,1 - test_accg_immed 1,accg0 - test_acc_immed 0xfffb0003,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,1 - test_accg_immed 1,accg0 - test_acc_immed 0xfffc0002,acc0 - - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxiu fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 26,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 1,3,fr8 - cmcpxiu fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 5,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxiu fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 0x0001,2,fr8 - cmcpxiu fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x7fff,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 0x0001,2,fr8 - cmcpxiu fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8001,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 17 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 0x00010001,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x0000,0x8000,fr8 - cmcpxiu fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0000,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; almost max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,0 - test_accg_immed 1,accg0 - test_acc_immed 0xfffb0003,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,0 - test_accg_immed 1,accg0 - test_acc_immed 0xfffc0002,acc0 - - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxiu fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 1,3,fr8 - cmcpxiu fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxiu fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 0x0001,2,fr8 - cmcpxiu fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x0000,0x8000,fr8 - cmcpxiu fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0x0001,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxiu fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 1,3,fr8 - cmcpxiu fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxiu fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 0x0001,2,fr8 - cmcpxiu fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x0000,0x8000,fr8 - cmcpxiu fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0x0001,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxiu fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 1,3,fr8 - cmcpxiu fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxiu fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 0x0001,2,fr8 - cmcpxiu fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxiu fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x0000,0x8000,fr8 - cmcpxiu fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0x0001,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc6,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc6,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxiu fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 1,3,fr8 - cmcpxiu fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxiu fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 0x0001,2,fr8 - cmcpxiu fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxiu fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x0000,0x8000,fr8 - cmcpxiu fr7,fr8,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0x0001,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc7,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc7,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - pass diff --git a/sim/testsuite/sim/frv/cmcpxrs.cgs b/sim/testsuite/sim/frv/cmcpxrs.cgs deleted file mode 100644 index ea1242c1cdb..00000000000 --- a/sim/testsuite/sim/frv/cmcpxrs.cgs +++ /dev/null @@ -1,649 +0,0 @@ -# frv testcase for cmcpxrs $GRi,$GRj,$ACCk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmcpxrs -cmcpxrs: - set_spr_immed 0x1b1b,cccr - - ; Positive operands - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxrs fr7,fr8,acc0,cc0,1 - test_accg_immed 0xff,accg0 - test_acc_immed -14,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxrs fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - cmcpxrs fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 1,acc0 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x0007,fr8 - cmcpxrs fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0,0x7ff0,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x2000,fr8 - cmcpxrs fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x4000,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxrs fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x0001,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,1,fr8 - cmcpxrs fr7,fr8,acc0,cc0,1 - test_accg_immed 0xff,accg0 - test_acc_immed -3,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmcpxrs fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 1,0xfffe,fr8 - cmcpxrs fr7,fr8,acc0,cc4,1 - test_accg_immed 0xff,accg0 - test_acc_immed -2,acc0 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0xfff9,fr8 - cmcpxrs fr7,fr8,acc0,cc4,1 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbff0,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x0003,fr8 - cmcpxrs fr7,fr8,acc0,cc4,1 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x8006,acc0 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc4,1 - test_accg_immed 0xff,accg0 - test_acc_limmed 0x8000,0x8000,acc0 - - set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x7fff,0x8000,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffb,fr8 - cmcpxrs fr7,fr8,acc0,cc4,1 - test_accg_immed 0xff,accg0 - test_acc_immed -14,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmcpxrs fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 1,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x7fff,0x8001,fr8 - cmcpxrs fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 0x40000000,acc0 - - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxrs fr7,fr8,acc0,cc1,0 - test_accg_immed 0xff,accg0 - test_acc_immed -14,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxrs fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - cmcpxrs fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 1,acc0 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x0007,fr8 - cmcpxrs fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0,0x7ff0,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x2000,fr8 - cmcpxrs fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x4000,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxrs fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x0001,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,1,fr8 - cmcpxrs fr7,fr8,acc0,cc1,0 - test_accg_immed 0xff,accg0 - test_acc_immed -3,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmcpxrs fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 1,0xfffe,fr8 - cmcpxrs fr7,fr8,acc0,cc5,0 - test_accg_immed 0xff,accg0 - test_acc_immed -2,acc0 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0xfff9,fr8 - cmcpxrs fr7,fr8,acc0,cc5,0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbff0,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x0003,fr8 - cmcpxrs fr7,fr8,acc0,cc5,0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x8006,acc0 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc5,0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0x8000,0x8000,acc0 - - set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x7fff,0x8000,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffb,fr8 - cmcpxrs fr7,fr8,acc0,cc5,0 - test_accg_immed 0xff,accg0 - test_acc_immed -14,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmcpxrs fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 1,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x7fff,0x8001,fr8 - cmcpxrs fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 0x40000000,acc0 - - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxrs fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxrs fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - cmcpxrs fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x0007,fr8 - cmcpxrs fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x2000,fr8 - cmcpxrs fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxrs fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,1,fr8 - cmcpxrs fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmcpxrs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 1,0xfffe,fr8 - cmcpxrs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0xfff9,fr8 - cmcpxrs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x0003,fr8 - cmcpxrs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffb,fr8 - cmcpxrs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmcpxrs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x7fff,0x8001,fr8 - cmcpxrs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxrs fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxrs fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - cmcpxrs fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x0007,fr8 - cmcpxrs fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x2000,fr8 - cmcpxrs fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxrs fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,1,fr8 - cmcpxrs fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmcpxrs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 1,0xfffe,fr8 - cmcpxrs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0xfff9,fr8 - cmcpxrs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x0003,fr8 - cmcpxrs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffb,fr8 - cmcpxrs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmcpxrs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x7fff,0x8001,fr8 - cmcpxrs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxrs fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxrs fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - cmcpxrs fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x0007,fr8 - cmcpxrs fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x2000,fr8 - cmcpxrs fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxrs fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,1,fr8 - cmcpxrs fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmcpxrs fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 1,0xfffe,fr8 - cmcpxrs fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0xfff9,fr8 - cmcpxrs fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x0003,fr8 - cmcpxrs fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffb,fr8 - cmcpxrs fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmcpxrs fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x7fff,0x8001,fr8 - cmcpxrs fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 -; - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxrs fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxrs fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - cmcpxrs fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x0007,fr8 - cmcpxrs fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x2000,fr8 - cmcpxrs fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxrs fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,1,fr8 - cmcpxrs fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmcpxrs fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 1,0xfffe,fr8 - cmcpxrs fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0xfff9,fr8 - cmcpxrs fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x0003,fr8 - cmcpxrs fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffb,fr8 - cmcpxrs fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmcpxrs fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x7fff,0x8001,fr8 - cmcpxrs fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmcpxrs fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - pass diff --git a/sim/testsuite/sim/frv/cmcpxru.cgs b/sim/testsuite/sim/frv/cmcpxru.cgs deleted file mode 100644 index f9217b68121..00000000000 --- a/sim/testsuite/sim/frv/cmcpxru.cgs +++ /dev/null @@ -1,544 +0,0 @@ -# frv testcase for cmcpxru $GRi,$GRj,$GRk,$CCi,$cond -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global cmcpxru -cmcpxru: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxru fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 14,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 3,1,fr8 - cmcpxru fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 1,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxru fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 2,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x7ffd,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0xffff,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 0x0001ffff,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxru fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x0000,fr8 - cmcpxru fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0000,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0xffff,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxru fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 14,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 3,1,fr8 - cmcpxru fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 1,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxru fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 2,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x7ffd,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0xffff,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 0x0001ffff,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxru fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x0000,fr8 - cmcpxru fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0000,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0xffff,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxru fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 3,1,fr8 - cmcpxru fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxru fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 2,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxru fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x0000,fr8 - cmcpxru fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0xffff,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxru fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 3,1,fr8 - cmcpxru fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxru fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 2,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxru fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x0000,fr8 - cmcpxru fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0xffff,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxru fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 3,1,fr8 - cmcpxru fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxru fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 2,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxru fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x0000,fr8 - cmcpxru fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0xffff,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 -; - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxru fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 3,1,fr8 - cmcpxru fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxru fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 2,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxru fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x0000,fr8 - cmcpxru fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0xffff,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 2,1,0,msr1 ; msr1.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - pass diff --git a/sim/testsuite/sim/frv/cmexpdhd.cgs b/sim/testsuite/sim/frv/cmexpdhd.cgs deleted file mode 100644 index 33a3c009375..00000000000 --- a/sim/testsuite/sim/frv/cmexpdhd.cgs +++ /dev/null @@ -1,116 +0,0 @@ -# frv testcase for cmexpdhd $FRi,$s6,$FRj,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmexpdhd -cmexpdhd: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmexpdhd fr10,0,fr12,cc0,1 - test_fr_limmed 0xdead,0xdead,fr12 - test_fr_limmed 0xdead,0xdead,fr13 - - cmexpdhd fr10,1,fr12,cc0,1 - test_fr_limmed 0xbeef,0xbeef,fr12 - test_fr_limmed 0xbeef,0xbeef,fr13 - - cmexpdhd fr10,62,fr12,cc4,1 - test_fr_limmed 0xdead,0xdead,fr12 - test_fr_limmed 0xdead,0xdead,fr13 - - cmexpdhd fr10,63,fr12,cc4,1 - test_fr_limmed 0xbeef,0xbeef,fr12 - test_fr_limmed 0xbeef,0xbeef,fr13 - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmexpdhd fr10,0,fr12,cc1,0 - test_fr_limmed 0xdead,0xdead,fr12 - test_fr_limmed 0xdead,0xdead,fr13 - - cmexpdhd fr10,1,fr12,cc1,0 - test_fr_limmed 0xbeef,0xbeef,fr12 - test_fr_limmed 0xbeef,0xbeef,fr13 - - cmexpdhd fr10,62,fr12,cc5,0 - test_fr_limmed 0xdead,0xdead,fr12 - test_fr_limmed 0xdead,0xdead,fr13 - - cmexpdhd fr10,63,fr12,cc5,0 - test_fr_limmed 0xbeef,0xbeef,fr12 - test_fr_limmed 0xbeef,0xbeef,fr13 - - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x2222,0x2222,fr13 - set_fr_iimmed 0xdead,0xbeef,fr10 - cmexpdhd fr10,0,fr12,cc0,0 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - cmexpdhd fr10,1,fr12,cc0,0 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - cmexpdhd fr10,62,fr12,cc4,0 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - cmexpdhd fr10,63,fr12,cc4,0 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmexpdhd fr10,0,fr12,cc1,1 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - cmexpdhd fr10,1,fr12,cc1,1 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - cmexpdhd fr10,62,fr12,cc5,1 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - cmexpdhd fr10,63,fr12,cc5,1 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmexpdhd fr10,0,fr12,cc2,1 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - cmexpdhd fr10,1,fr12,cc2,0 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - cmexpdhd fr10,62,fr12,cc6,1 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - cmexpdhd fr10,63,fr12,cc6,0 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmexpdhd fr10,0,fr12,cc3,1 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - cmexpdhd fr10,1,fr12,cc3,0 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - cmexpdhd fr10,62,fr12,cc7,1 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - cmexpdhd fr10,63,fr12,cc7,0 - test_fr_limmed 0x1111,0x1111,fr12 - test_fr_limmed 0x2222,0x2222,fr13 - - pass diff --git a/sim/testsuite/sim/frv/cmexpdhw.cgs b/sim/testsuite/sim/frv/cmexpdhw.cgs deleted file mode 100644 index 330d404562b..00000000000 --- a/sim/testsuite/sim/frv/cmexpdhw.cgs +++ /dev/null @@ -1,91 +0,0 @@ -# frv testcase for cmexpdhw $FRi,$s6,$FRj,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmexpdhw -cmexpdhw: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmexpdhw fr10,0,fr12,cc0,1 - test_fr_limmed 0xdead,0xdead,fr12 - - cmexpdhw fr10,1,fr12,cc0,1 - test_fr_limmed 0xbeef,0xbeef,fr12 - - cmexpdhw fr10,62,fr12,cc4,1 - test_fr_limmed 0xdead,0xdead,fr12 - - cmexpdhw fr10,63,fr12,cc4,1 - test_fr_limmed 0xbeef,0xbeef,fr12 - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmexpdhw fr10,0,fr12,cc1,0 - test_fr_limmed 0xdead,0xdead,fr12 - - cmexpdhw fr10,1,fr12,cc1,0 - test_fr_limmed 0xbeef,0xbeef,fr12 - - cmexpdhw fr10,62,fr12,cc5,0 - test_fr_limmed 0xdead,0xdead,fr12 - - cmexpdhw fr10,63,fr12,cc5,0 - test_fr_limmed 0xbeef,0xbeef,fr12 - - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0xdead,0xbeef,fr10 - cmexpdhw fr10,0,fr12,cc0,0 - test_fr_limmed 0x1111,0x1111,fr12 - - cmexpdhw fr10,1,fr12,cc0,0 - test_fr_limmed 0x1111,0x1111,fr12 - - cmexpdhw fr10,62,fr12,cc4,0 - test_fr_limmed 0x1111,0x1111,fr12 - - cmexpdhw fr10,63,fr12,cc4,0 - test_fr_limmed 0x1111,0x1111,fr12 - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmexpdhw fr10,0,fr12,cc1,1 - test_fr_limmed 0x1111,0x1111,fr12 - - cmexpdhw fr10,1,fr12,cc1,1 - test_fr_limmed 0x1111,0x1111,fr12 - - cmexpdhw fr10,62,fr12,cc5,1 - test_fr_limmed 0x1111,0x1111,fr12 - - cmexpdhw fr10,63,fr12,cc5,1 - test_fr_limmed 0x1111,0x1111,fr12 - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmexpdhw fr10,0,fr12,cc2,1 - test_fr_limmed 0x1111,0x1111,fr12 - - cmexpdhw fr10,1,fr12,cc2,0 - test_fr_limmed 0x1111,0x1111,fr12 - - cmexpdhw fr10,62,fr12,cc6,1 - test_fr_limmed 0x1111,0x1111,fr12 - - cmexpdhw fr10,63,fr12,cc6,0 - test_fr_limmed 0x1111,0x1111,fr12 - - set_fr_iimmed 0xdead,0xbeef,fr10 - cmexpdhw fr10,0,fr12,cc3,1 - test_fr_limmed 0x1111,0x1111,fr12 - - cmexpdhw fr10,1,fr12,cc3,0 - test_fr_limmed 0x1111,0x1111,fr12 - - cmexpdhw fr10,62,fr12,cc7,1 - test_fr_limmed 0x1111,0x1111,fr12 - - cmexpdhw fr10,63,fr12,cc7,0 - test_fr_limmed 0x1111,0x1111,fr12 - - pass diff --git a/sim/testsuite/sim/frv/cmhtob.cgs b/sim/testsuite/sim/frv/cmhtob.cgs deleted file mode 100644 index a3f00c52cef..00000000000 --- a/sim/testsuite/sim/frv/cmhtob.cgs +++ /dev/null @@ -1,103 +0,0 @@ -# frv testcase for cmhtob $FRj,$FRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmhtob -cmhtob: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x00ad,0x00ef,fr10 - set_fr_iimmed 0x0034,0x0078,fr11 - cmhtob fr10,fr12,cc0,1 - test_fr_limmed 0xadef,0x3478,fr12 - - set_fr_iimmed 0xdead,0xbeef,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - cmhtob fr10,fr12,cc0,1 - test_fr_limmed 0xffff,0xffff,fr12 - - set_fr_iimmed 0x0134,0x0878,fr10 - set_fr_iimmed 0x10ad,0x80ef,fr11 - cmhtob fr10,fr12,cc4,1 - test_fr_limmed 0xffff,0xffff,fr12 - - set_fr_iimmed 0x00ad,0x00ef,fr10 - set_fr_iimmed 0x0034,0x0078,fr11 - cmhtob fr10,fr12,cc1,0 - test_fr_limmed 0xadef,0x3478,fr12 - - set_fr_iimmed 0xdead,0xbeef,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - cmhtob fr10,fr12,cc1,0 - test_fr_limmed 0xffff,0xffff,fr12 - - set_fr_iimmed 0x0134,0x0878,fr10 - set_fr_iimmed 0x10ad,0x80ef,fr11 - cmhtob fr10,fr12,cc5,0 - test_fr_limmed 0xffff,0xffff,fr12 - - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x00ad,0x00ef,fr10 - set_fr_iimmed 0x0034,0x0078,fr11 - cmhtob fr10,fr12,cc0,0 - test_fr_limmed 0x1111,0x1111,fr12 - - set_fr_iimmed 0xdead,0xbeef,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - cmhtob fr10,fr12,cc0,0 - test_fr_limmed 0x1111,0x1111,fr12 - - set_fr_iimmed 0x0134,0x0878,fr10 - set_fr_iimmed 0x10ad,0x80ef,fr11 - cmhtob fr10,fr12,cc4,0 - test_fr_limmed 0x1111,0x1111,fr12 - - set_fr_iimmed 0x00ad,0x00ef,fr10 - set_fr_iimmed 0x0034,0x0078,fr11 - cmhtob fr10,fr12,cc1,1 - test_fr_limmed 0x1111,0x1111,fr12 - - set_fr_iimmed 0xdead,0xbeef,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - cmhtob fr10,fr12,cc1,1 - test_fr_limmed 0x1111,0x1111,fr12 - - set_fr_iimmed 0x0134,0x0878,fr10 - set_fr_iimmed 0x10ad,0x80ef,fr11 - cmhtob fr10,fr12,cc5,1 - test_fr_limmed 0x1111,0x1111,fr12 - - set_fr_iimmed 0x00ad,0x00ef,fr10 - set_fr_iimmed 0x0034,0x0078,fr11 - cmhtob fr10,fr12,cc2,1 - test_fr_limmed 0x1111,0x1111,fr12 - - set_fr_iimmed 0xdead,0xbeef,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - cmhtob fr10,fr12,cc2,0 - test_fr_limmed 0x1111,0x1111,fr12 - - set_fr_iimmed 0x0134,0x0878,fr10 - set_fr_iimmed 0x10ad,0x80ef,fr11 - cmhtob fr10,fr12,cc6,1 - test_fr_limmed 0x1111,0x1111,fr12 - - set_fr_iimmed 0x00ad,0x00ef,fr10 - set_fr_iimmed 0x0034,0x0078,fr11 - cmhtob fr10,fr12,cc3,1 - test_fr_limmed 0x1111,0x1111,fr12 - - set_fr_iimmed 0xdead,0xbeef,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - cmhtob fr10,fr12,cc7,0 - test_fr_limmed 0x1111,0x1111,fr12 - - set_fr_iimmed 0x0134,0x0878,fr10 - set_fr_iimmed 0x10ad,0x80ef,fr11 - cmhtob fr10,fr12,cc7,1 - test_fr_limmed 0x1111,0x1111,fr12 - - pass diff --git a/sim/testsuite/sim/frv/cmmachs.cgs b/sim/testsuite/sim/frv/cmmachs.cgs deleted file mode 100644 index 2131b7e456d..00000000000 --- a/sim/testsuite/sim/frv/cmmachs.cgs +++ /dev/null @@ -1,1631 +0,0 @@ -# frv testcase for cmmachs $GRi,$GRj,$ACCk,$CCi,$cond -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global cmmachs -cmmachs: - set_spr_immed 0x1b1b,cccr - - ; Positive operands - set_spr_immed 0x0,msr0 - set_spr_immed 0x0,msr1 - set_accg_immed 0x0,accg0 - set_acc_immed 0x0,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x0,acc1 - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0,0x8006,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0001,0x0006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0001,0x0006,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0007,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0007,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0001,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xffff,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xffff,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xffff,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xffff,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xbffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xbffd,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x3ffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x3ffd,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffd,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffd,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xc003,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xc003,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xc005,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xc005,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x3ffec006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3ffec006,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x7ffec006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x7ffec006,acc1 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachs fr7,fr8,acc0,cc4,1 -;;;;;;;;;;;; - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_accg_immed -128,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed -128,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr7 - set_fr_iimmed 1,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0x8000,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - ; Positive operands - set_spr_immed 0x0,msr0 - set_spr_immed 0x0,msr1 - set_accg_immed 0x0,accg0 ; saturation - set_acc_immed 0x0,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x0,acc1 - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0,0x8006,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0001,0x0006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0001,0x0006,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0007,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0007,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0001,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xffff,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xffff,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xffff,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xffff,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xbffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xbffd,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x3ffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x3ffd,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffd,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffd,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xc003,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xc003,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xc005,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xc005,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x3ffec006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3ffec006,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x7ffec006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x7ffec006,acc1 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr7 - set_fr_iimmed 1,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0x8000,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - ; Positive operands - set_spr_immed 0x0,msr0 - set_spr_immed 0x0,msr1 - set_accg_immed 0x0,accg0 - set_acc_immed 0x0,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x0,acc1 - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr7 - set_fr_iimmed 1,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0x8000,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - ; Positive operands - set_spr_immed 0x0,msr0 - set_spr_immed 0x0,msr1 - set_accg_immed 0x0,accg0 - set_acc_immed 0x0,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x0,acc1 - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr7 - set_fr_iimmed 1,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0x8000,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - ; Positive operands - set_spr_immed 0x0,msr0 - set_spr_immed 0x0,msr1 - set_accg_immed 0x0,accg0 - set_acc_immed 0x0,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x0,acc1 - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmachs fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachs fr7,fr8,acc0,cc2,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmachs fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachs fr7,fr8,acc0,cc2,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc2,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmachs fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc2,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmachs fr7,fr8,acc0,cc2,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc6,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc6,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmachs fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachs fr7,fr8,acc0,cc6,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachs fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc6,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr7 - set_fr_iimmed 1,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0x8000,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc6,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 -; - ; Positive operands - set_spr_immed 0x0,msr0 - set_spr_immed 0x0,msr1 - set_accg_immed 0x0,accg0 - set_acc_immed 0x0,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x0,acc1 - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmachs fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachs fr7,fr8,acc0,cc3,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmachs fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachs fr7,fr8,acc0,cc3,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc3,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmachs fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc3,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmachs fr7,fr8,acc0,cc3,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc7,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc7,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmachs fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachs fr7,fr8,acc0,cc7,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachs fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc7,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr7 - set_fr_iimmed 1,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0x8000,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc7,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - pass diff --git a/sim/testsuite/sim/frv/cmmachu.cgs b/sim/testsuite/sim/frv/cmmachu.cgs deleted file mode 100644 index 8948f15c4a5..00000000000 --- a/sim/testsuite/sim/frv/cmmachu.cgs +++ /dev/null @@ -1,864 +0,0 @@ -# frv testcase for cmmachu $GRi,$GRj,$GRk,$CCi,$cond -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global cmmachu -cmmachu: - set_spr_immed 0x1b1b,cccr - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0,accg0 - set_acc_immed 0,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmachu fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmachu fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachu fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachu fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8006,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachu fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0001,0x0006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0001,0x0006,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x00020006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x00020006,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachu fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x40010007,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x40010007,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x8001,0x0007,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x8001,0x0007,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 1,accg0 - test_acc_limmed 0x7fff,0x0008,acc0 - test_accg_immed 1,accg1 - test_acc_limmed 0x7fff,0x0008,acc1 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachu fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_fr_iimmed 0xffff,0x0000,fr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0,accg0 - set_acc_immed 0,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmachu fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmachu fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachu fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachu fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8006,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachu fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0001,0x0006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0001,0x0006,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x00020006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x00020006,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachu fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x40010007,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x40010007,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x8001,0x0007,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x8001,0x0007,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 1,accg0 - test_acc_limmed 0x7fff,0x0008,acc0 - test_accg_immed 1,accg1 - test_acc_limmed 0x7fff,0x0008,acc1 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachu fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_fr_iimmed 0xffff,0x0000,fr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmachu fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmachu fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachu fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachu fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachu fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - - set_fr_iimmed 0xffff,0x0000,fr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmachu fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmachu fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachu fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachu fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachu fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - - set_fr_iimmed 0xffff,0x0000,fr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmachu fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmachu fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachu fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachu fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachu fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachu fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachu fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - - set_fr_iimmed 0xffff,0x0000,fr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 -; - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmachu fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmachu fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachu fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachu fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachu fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachu fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachu fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - - set_fr_iimmed 0xffff,0x0000,fr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - - pass diff --git a/sim/testsuite/sim/frv/cmmulhs.cgs b/sim/testsuite/sim/frv/cmmulhs.cgs deleted file mode 100644 index 01ee59822e4..00000000000 --- a/sim/testsuite/sim/frv/cmmulhs.cgs +++ /dev/null @@ -1,814 +0,0 @@ -# frv testcase for cmmulhs $GRi,$GRj,$ACCk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmmulhs -cmmulhs: - set_spr_immed 0x1b1b,cccr - - ; Positive operands - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmulhs fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmulhs fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmulhs fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmulhs fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0,0x7ffe,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0,0x7ffe,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmulhs fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8000,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmulhs fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x0001,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmulhs fr7,fr8,acc0,cc0,1 - test_accg_immed 0xff,accg0 - test_acc_immed -6,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -6,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc0,1 - test_accg_immed 0xff,accg0 - test_acc_immed -2,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -2,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmulhs fr7,fr8,acc0,cc4,1 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffe,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffe,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmulhs fr7,fr8,acc0,cc4,1 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x8000,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0x8000,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmulhs fr7,fr8,acc0,cc4,1 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xc000,0x8000,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xc000,0x8000,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmulhs fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmulhs fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmulhs fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 0x40000000,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x40000000,acc1 - - ; Positive operands - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmulhs fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmulhs fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmulhs fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmulhs fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0,0x7ffe,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0,0x7ffe,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmulhs fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8000,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmulhs fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x0001,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmulhs fr7,fr8,acc0,cc1,0 - test_accg_immed 0xff,accg0 - test_acc_immed -6,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -6,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc1,0 - test_accg_immed 0xff,accg0 - test_acc_immed -2,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -2,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmulhs fr7,fr8,acc0,cc5,0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffe,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffe,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmulhs fr7,fr8,acc0,cc5,0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x8000,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0x8000,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmulhs fr7,fr8,acc0,cc5,0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xc000,0x8000,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xc000,0x8000,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmulhs fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmulhs fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmulhs fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 0x40000000,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x40000000,acc1 - - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmulhs fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmulhs fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmulhs fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmulhs fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmulhs fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmulhs fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmulhs fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmulhs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmulhs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmulhs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmulhs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmulhs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmulhs fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmulhs fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmulhs fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmulhs fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmulhs fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmulhs fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmulhs fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmulhs fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmulhs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmulhs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmulhs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmulhs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmulhs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmulhs fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmulhs fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmulhs fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmulhs fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmulhs fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmulhs fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmulhs fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmulhs fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmulhs fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmulhs fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmulhs fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmulhs fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmulhs fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmulhs fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmulhs fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmulhs fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmulhs fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmulhs fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmulhs fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmulhs fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmulhs fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmulhs fr7,fr8,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmulhs fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmulhs fr7,fr8,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmulhs fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmulhs fr7,fr8,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmulhs fr7,fr8,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmulhs fr7,fr8,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - pass diff --git a/sim/testsuite/sim/frv/cmmulhu.cgs b/sim/testsuite/sim/frv/cmmulhu.cgs deleted file mode 100644 index 9e8fbb881cc..00000000000 --- a/sim/testsuite/sim/frv/cmmulhu.cgs +++ /dev/null @@ -1,460 +0,0 @@ -# frv testcase for cmmulhu $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmmulhu -cmmulhu: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmulhu fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmulhu fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmulhu fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmulhu fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x7ffe,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x7ffe,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmulhu fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8000,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmulhu fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 0x00010000,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x00010000,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmulhu fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmulhu fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0000,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmulhu fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0xfffe,0x0001,acc1 - - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmulhu fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmulhu fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmulhu fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmulhu fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x7ffe,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x7ffe,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmulhu fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8000,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmulhu fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 0x00010000,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x00010000,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmulhu fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmulhu fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0000,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmulhu fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0xfffe,0x0001,acc1 - - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmulhu fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmulhu fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmulhu fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmulhu fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmulhu fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmulhu fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmulhu fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmulhu fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmulhu fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmulhu fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmulhu fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmulhu fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmulhu fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmulhu fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmulhu fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmulhu fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmulhu fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmulhu fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmulhu fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmulhu fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmulhu fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmulhu fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmulhu fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmulhu fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmulhu fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmulhu fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmulhu fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmulhu fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmulhu fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmulhu fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmulhu fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmulhu fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmulhu fr7,fr8,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmulhu fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmulhu fr7,fr8,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmulhu fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - pass diff --git a/sim/testsuite/sim/frv/cmnot.cgs b/sim/testsuite/sim/frv/cmnot.cgs deleted file mode 100644 index cc93c016e20..00000000000 --- a/sim/testsuite/sim/frv/cmnot.cgs +++ /dev/null @@ -1,60 +0,0 @@ -# frv testcase for cmnot $FRintj,$FRintk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmnot -cmnot: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - cmnot fr7,fr7,cc0,1 - test_fr_iimmed 0x55555555,fr7 - - set_fr_iimmed 0xdead,0xbeef,fr7 - cmnot fr7,fr7,cc4,1 - test_fr_iimmed 0x21524110,fr7 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - cmnot fr7,fr7,cc1,0 - test_fr_iimmed 0x55555555,fr7 - - set_fr_iimmed 0xdead,0xbeef,fr7 - cmnot fr7,fr7,cc5,0 - test_fr_iimmed 0x21524110,fr7 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - cmnot fr7,fr7,cc0,0 - test_fr_iimmed 0xaaaaaaaa,fr7 - - set_fr_iimmed 0xdead,0xbeef,fr7 - cmnot fr7,fr7,cc4,0 - test_fr_iimmed 0xdeadbeef,fr7 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - cmnot fr7,fr7,cc1,1 - test_fr_iimmed 0xaaaaaaaa,fr7 - - set_fr_iimmed 0xdead,0xbeef,fr7 - cmnot fr7,fr7,cc5,1 - test_fr_iimmed 0xdeadbeef,fr7 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - cmnot fr7,fr7,cc2,0 - test_fr_iimmed 0xaaaaaaaa,fr7 - - set_fr_iimmed 0xdead,0xbeef,fr7 - cmnot fr7,fr7,cc6,1 - test_fr_iimmed 0xdeadbeef,fr7 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - cmnot fr7,fr7,cc3,0 - test_fr_iimmed 0xaaaaaaaa,fr7 - - set_fr_iimmed 0xdead,0xbeef,fr7 - cmnot fr7,fr7,cc7,1 - test_fr_iimmed 0xdeadbeef,fr7 - - pass diff --git a/sim/testsuite/sim/frv/cmor.cgs b/sim/testsuite/sim/frv/cmor.cgs deleted file mode 100644 index ebdc5f2a313..00000000000 --- a/sim/testsuite/sim/frv/cmor.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for cmor $FRinti,$FRintj,$FRintk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmor -cmor: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmor fr7,fr8,fr8,cc0,1 - test_fr_iimmed 0xffffffff,fr8 - - set_fr_iimmed 0x0000,0x0000,fr7 - set_fr_iimmed 0x0000,0x0000,fr8 - cmor fr7,fr8,fr8,cc0,1 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xdead,0x0000,fr7 - set_fr_iimmed 0x0000,0xbeef,fr8 - cmor fr7,fr8,fr8,cc4,1 - test_fr_iimmed 0xdeadbeef,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmor fr7,fr8,fr8,cc1,0 - test_fr_iimmed 0xffffffff,fr8 - - set_fr_iimmed 0x0000,0x0000,fr7 - set_fr_iimmed 0x0000,0x0000,fr8 - cmor fr7,fr8,fr8,cc1,0 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xdead,0x0000,fr7 - set_fr_iimmed 0x0000,0xbeef,fr8 - cmor fr7,fr8,fr8,cc5,0 - test_fr_iimmed 0xdeadbeef,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmor fr7,fr8,fr8,cc0,0 - test_fr_iimmed 0x55555555,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr7 - set_fr_iimmed 0x0000,0x0000,fr8 - cmor fr7,fr8,fr8,cc0,0 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xdead,0x0000,fr7 - set_fr_iimmed 0x0000,0xbeef,fr8 - cmor fr7,fr8,fr8,cc4,0 - test_fr_iimmed 0x0000beef,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmor fr7,fr8,fr8,cc1,1 - test_fr_iimmed 0x55555555,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr7 - set_fr_iimmed 0x0000,0x0000,fr8 - cmor fr7,fr8,fr8,cc1,1 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xdead,0x0000,fr7 - set_fr_iimmed 0x0000,0xbeef,fr8 - cmor fr7,fr8,fr8,cc5,1 - test_fr_iimmed 0x0000beef,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmor fr7,fr8,fr8,cc2,0 - test_fr_iimmed 0x55555555,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr7 - set_fr_iimmed 0x0000,0x0000,fr8 - cmor fr7,fr8,fr8,cc2,1 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xdead,0x0000,fr7 - set_fr_iimmed 0x0000,0xbeef,fr8 - cmor fr7,fr8,fr8,cc6,0 - test_fr_iimmed 0x0000beef,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmor fr7,fr8,fr8,cc3,1 - test_fr_iimmed 0x55555555,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr7 - set_fr_iimmed 0x0000,0x0000,fr8 - cmor fr7,fr8,fr8,cc3,0 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xdead,0x0000,fr7 - set_fr_iimmed 0x0000,0xbeef,fr8 - cmor fr7,fr8,fr8,cc7,1 - test_fr_iimmed 0x0000beef,fr8 - pass diff --git a/sim/testsuite/sim/frv/cmov.cgs b/sim/testsuite/sim/frv/cmov.cgs deleted file mode 100644 index 236bb20f086..00000000000 --- a/sim/testsuite/sim/frv/cmov.cgs +++ /dev/null @@ -1,54 +0,0 @@ -# frv testcase for cmov $GRi,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmov -cmov: - set_spr_immed 0x1b1b,cccr - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0xdeadbeef,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - cmov gr7,gr8,cc0,0 - test_icc 1 0 0 0 icc0 - test_gr_immed 0xdeadbeef,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0xdeadbeef,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - cmov gr7,gr8,cc0,1 - test_icc 1 0 0 0 icc0 - test_gr_immed 0x00007fff,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0xdeadbeef,gr8 - set_icc 0x08,1 ; Set mask opposite of expected - cmov gr7,gr8,cc1,0 - test_icc 1 0 0 0 icc1 - test_gr_immed 0x00007fff,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0xdeadbeef,gr8 - set_icc 0x08,1 ; Set mask opposite of expected - cmov gr7,gr8,cc1,1 - test_icc 1 0 0 0 icc1 - test_gr_immed 0xdeadbeef,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0xdeadbeef,gr8 - set_icc 0x08,2 ; Set mask opposite of expected - cmov gr7,gr8,cc2,0 - test_icc 1 0 0 0 icc2 - test_gr_immed 0xdeadbeef,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0xdeadbeef,gr8 - set_icc 0x08,3 ; Set mask opposite of expected - cmov gr7,gr8,cc3,0 - test_icc 1 0 0 0 icc3 - test_gr_immed 0xdeadbeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/cmovfg.cgs b/sim/testsuite/sim/frv/cmovfg.cgs deleted file mode 100644 index 4109842cfa4..00000000000 --- a/sim/testsuite/sim/frv/cmovfg.cgs +++ /dev/null @@ -1,84 +0,0 @@ -# frv testcase for cmovfg $FRk,$GRj,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmovfg -cmovfg: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_gr_limmed 0,0,gr8 - cmovfg fr8,gr8,cc0,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_gr_limmed 0,0,gr8 - cmovfg fr8,gr8,cc4,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_gr_limmed 0,0,gr8 - cmovfg fr8,gr8,cc0,0 - test_gr_limmed 0,0,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_gr_limmed 0,0,gr8 - cmovfg fr8,gr8,cc4,0 - test_gr_limmed 0,0,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_gr_limmed 0,0,gr8 - cmovfg fr8,gr8,cc1,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_gr_limmed 0,0,gr8 - cmovfg fr8,gr8,cc5,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_gr_limmed 0,0,gr8 - cmovfg fr8,gr8,cc1,1 - test_gr_limmed 0,0,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_gr_limmed 0,0,gr8 - cmovfg fr8,gr8,cc5,1 - test_gr_limmed 0,0,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_gr_limmed 0,0,gr8 - cmovfg fr8,gr8,cc2,0 - test_gr_limmed 0,0,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_gr_limmed 0,0,gr8 - cmovfg fr8,gr8,cc2,1 - test_gr_limmed 0,0,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_gr_limmed 0,0,gr8 - cmovfg fr8,gr8,cc3,1 - test_gr_limmed 0,0,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_gr_limmed 0,0,gr8 - cmovfg fr8,gr8,cc7,0 - test_gr_limmed 0,0,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - pass diff --git a/sim/testsuite/sim/frv/cmovfgd.cgs b/sim/testsuite/sim/frv/cmovfgd.cgs deleted file mode 100644 index 5d1757d1f38..00000000000 --- a/sim/testsuite/sim/frv/cmovfgd.cgs +++ /dev/null @@ -1,132 +0,0 @@ -# frv testcase for cmovfgd $FRk,$GRj,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmovfgd -cmovfgd: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_gr_limmed 0,0,gr8 - set_gr_limmed 0,0,gr9 - cmovfgd fr8,gr8,cc0,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_gr_limmed 0,0,gr8 - set_gr_limmed 0,0,gr9 - cmovfgd fr8,gr8,cc4,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_gr_limmed 0,0,gr8 - set_gr_limmed 0,0,gr9 - cmovfgd fr8,gr8,cc0,0 - test_gr_limmed 0,0,gr8 - test_gr_limmed 0,0,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_gr_limmed 0,0,gr8 - set_gr_limmed 0,0,gr9 - cmovfgd fr8,gr8,cc4,0 - test_gr_limmed 0,0,gr8 - test_gr_limmed 0,0,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_gr_limmed 0,0,gr8 - set_gr_limmed 0,0,gr9 - cmovfgd fr8,gr8,cc1,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_gr_limmed 0,0,gr8 - set_gr_limmed 0,0,gr9 - cmovfgd fr8,gr8,cc5,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_gr_limmed 0,0,gr8 - set_gr_limmed 0,0,gr9 - cmovfgd fr8,gr8,cc1,1 - test_gr_limmed 0,0,gr8 - test_gr_limmed 0,0,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_gr_limmed 0,0,gr8 - set_gr_limmed 0,0,gr9 - cmovfgd fr8,gr8,cc5,1 - test_gr_limmed 0,0,gr8 - test_gr_limmed 0,0,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_gr_limmed 0,0,gr8 - set_gr_limmed 0,0,gr9 - cmovfgd fr8,gr8,cc2,0 - test_gr_limmed 0,0,gr8 - test_gr_limmed 0,0,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_gr_limmed 0,0,gr8 - set_gr_limmed 0,0,gr9 - cmovfgd fr8,gr8,cc6,1 - test_gr_limmed 0,0,gr8 - test_gr_limmed 0,0,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_gr_limmed 0,0,gr8 - set_gr_limmed 0,0,gr9 - cmovfgd fr8,gr8,cc3,1 - test_gr_limmed 0,0,gr8 - test_gr_limmed 0,0,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_gr_limmed 0,0,gr8 - set_gr_limmed 0,0,gr9 - cmovfgd fr8,gr8,cc7,0 - test_gr_limmed 0,0,gr8 - test_gr_limmed 0,0,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - pass diff --git a/sim/testsuite/sim/frv/cmovgf.cgs b/sim/testsuite/sim/frv/cmovgf.cgs deleted file mode 100644 index 58ed1d85356..00000000000 --- a/sim/testsuite/sim/frv/cmovgf.cgs +++ /dev/null @@ -1,84 +0,0 @@ -# frv testcase for cmovgf $GRj,$FRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmovgf -cmovgf: - set_spr_immed 0x1b1b,cccr - - set_gr_limmed 0xdead,0xbeef,gr8 - set_fr_iimmed 0,0,fr8 - cmovgf gr8,fr8,cc0,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_fr_iimmed 0,0,fr8 - cmovgf gr8,fr8,cc4,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_fr_iimmed 0,0,fr8 - cmovgf gr8,fr8,cc0,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0,0,fr8 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_fr_iimmed 0,0,fr8 - cmovgf gr8,fr8,cc4,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0,0,fr8 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_fr_iimmed 0,0,fr8 - cmovgf gr8,fr8,cc1,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_fr_iimmed 0,0,fr8 - cmovgf gr8,fr8,cc5,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_fr_iimmed 0,0,fr8 - cmovgf gr8,fr8,cc1,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0,0,fr8 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_fr_iimmed 0,0,fr8 - cmovgf gr8,fr8,cc5,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0,0,fr8 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_fr_iimmed 0,0,fr8 - cmovgf gr8,fr8,cc2,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0,0,fr8 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_fr_iimmed 0,0,fr8 - cmovgf gr8,fr8,cc6,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0,0,fr8 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_fr_iimmed 0,0,fr8 - cmovgf gr8,fr8,cc3,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0,0,fr8 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_fr_iimmed 0,0,fr8 - cmovgf gr8,fr8,cc7,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0,0,fr8 - - pass diff --git a/sim/testsuite/sim/frv/cmovgfd.cgs b/sim/testsuite/sim/frv/cmovgfd.cgs deleted file mode 100644 index 67bb2728508..00000000000 --- a/sim/testsuite/sim/frv/cmovgfd.cgs +++ /dev/null @@ -1,132 +0,0 @@ -# frv testcase for cmovgfd $GRj,$FRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmovgfd -cmovgfd: - set_spr_immed 0x1b1b,cccr - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_fr_iimmed 0,0,fr8 - set_fr_iimmed 0,0,fr9 - cmovgfd gr8,fr8,cc0,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_fr_iimmed 0,0,fr8 - set_fr_iimmed 0,0,fr9 - cmovgfd gr8,fr8,cc4,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_fr_iimmed 0,0,fr8 - set_fr_iimmed 0,0,fr9 - cmovgfd gr8,fr8,cc0,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0,0,fr8 - test_fr_limmed 0,0,fr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_fr_iimmed 0,0,fr8 - set_fr_iimmed 0,0,fr9 - cmovgfd gr8,fr8,cc4,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0,0,fr8 - test_fr_limmed 0,0,fr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_fr_iimmed 0,0,fr8 - set_fr_iimmed 0,0,fr9 - cmovgfd gr8,fr8,cc1,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_fr_iimmed 0,0,fr8 - set_fr_iimmed 0,0,fr9 - cmovgfd gr8,fr8,cc5,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_fr_iimmed 0,0,fr8 - set_fr_iimmed 0,0,fr9 - cmovgfd gr8,fr8,cc1,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0,0,fr8 - test_fr_limmed 0,0,fr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_fr_iimmed 0,0,fr8 - set_fr_iimmed 0,0,fr9 - cmovgfd gr8,fr8,cc5,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0,0,fr8 - test_fr_limmed 0,0,fr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_fr_iimmed 0,0,fr8 - set_fr_iimmed 0,0,fr9 - cmovgfd gr8,fr8,cc2,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0,0,fr8 - test_fr_limmed 0,0,fr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_fr_iimmed 0,0,fr8 - set_fr_iimmed 0,0,fr9 - cmovgfd gr8,fr8,cc6,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0,0,fr8 - test_fr_limmed 0,0,fr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_fr_iimmed 0,0,fr8 - set_fr_iimmed 0,0,fr9 - cmovgfd gr8,fr8,cc3,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0,0,fr8 - test_fr_limmed 0,0,fr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_fr_iimmed 0,0,fr8 - set_fr_iimmed 0,0,fr9 - cmovgfd gr8,fr8,cc7,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0,0,fr8 - test_fr_limmed 0,0,fr9 - - pass diff --git a/sim/testsuite/sim/frv/cmp.cgs b/sim/testsuite/sim/frv/cmp.cgs deleted file mode 100644 index e6694c14a7c..00000000000 --- a/sim/testsuite/sim/frv/cmp.cgs +++ /dev/null @@ -1,31 +0,0 @@ -# frv testcase for cmp $GRi,$GRj,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global cmp -cmp: - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - cmp gr8,gr7,icc0 - test_icc 0 0 0 0 icc0 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - cmp gr8,gr7,icc0 - test_icc 0 0 1 0 icc0 - - set_icc 0x0b,0 ; Set mask opposite of expected - cmp gr8,gr8,icc0 - test_icc 0 1 0 0 icc0 - - set_gr_immed 0,gr8 - set_icc 0x06,0 ; Set mask opposite of expected - cmp gr8,gr7,icc0 - test_icc 1 0 0 1 icc0 - - pass diff --git a/sim/testsuite/sim/frv/cmpb.cgs b/sim/testsuite/sim/frv/cmpb.cgs deleted file mode 100644 index 94b98366069..00000000000 --- a/sim/testsuite/sim/frv/cmpb.cgs +++ /dev/null @@ -1,41 +0,0 @@ -# frv testcase for cmpb $GRi,$GRj,$ICCi_1 -# mach: fr400 fr550 - - .include "testutils.inc" - - start - - .global cmpb -cmpb: - set_gr_limmed 0xdead,0xbeef,gr7 - set_gr_limmed 0xdead,0xbeef,gr8 - set_icc 0x00,0 ; Set mask opposite of expected - cmpb gr7,gr8,icc0 - test_icc 1 1 1 1 icc0 - - set_gr_limmed 0x21ad,0xbeef,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - cmpb gr7,gr8,icc0 - test_icc 0 1 1 1 icc0 - - set_gr_limmed 0xde52,0xbeef,gr8 - set_icc 0x04,0 ; Set mask opposite of expected - cmpb gr7,gr8,icc0 - test_icc 1 0 1 1 icc0 - - set_gr_limmed 0xdead,0x41ef,gr8 - set_icc 0x02,0 ; Set mask opposite of expected - cmpb gr7,gr8,icc0 - test_icc 1 1 0 1 icc0 - - set_gr_limmed 0xdead,0xbe10,gr8 - set_icc 0x01,0 ; Set mask opposite of expected - cmpb gr7,gr8,icc0 - test_icc 1 1 1 0 icc0 - - set_gr_limmed 0xbeef,0xdead,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - cmpb gr7,gr8,icc0 - test_icc 0 0 0 0 icc0 - - pass diff --git a/sim/testsuite/sim/frv/cmpba.cgs b/sim/testsuite/sim/frv/cmpba.cgs deleted file mode 100644 index 160b9ef2cb9..00000000000 --- a/sim/testsuite/sim/frv/cmpba.cgs +++ /dev/null @@ -1,41 +0,0 @@ -# frv testcase for cmpba $GRi,$GRj,$ICCi_1 -# mach: fr400 fr550 - - .include "testutils.inc" - - start - - .global cmpba -cmpba: - set_gr_limmed 0xdead,0xbeef,gr7 - set_gr_limmed 0xdead,0xbeef,gr8 - set_icc 0x0e,0 ; Set mask opposite of expected - cmpba gr7,gr8,icc0 - test_icc 0 0 0 1 icc0 - - set_gr_limmed 0x21ad,0xbeef,gr8 - set_icc 0x0e,0 ; Set mask opposite of expected - cmpba gr7,gr8,icc0 - test_icc 0 0 0 1 icc0 - - set_gr_limmed 0xde52,0xbeef,gr8 - set_icc 0x0e,0 ; Set mask opposite of expected - cmpba gr7,gr8,icc0 - test_icc 0 0 0 1 icc0 - - set_gr_limmed 0xdead,0x41ef,gr8 - set_icc 0x0e,0 ; Set mask opposite of expected - cmpba gr7,gr8,icc0 - test_icc 0 0 0 1 icc0 - - set_gr_limmed 0xdead,0xbe10,gr8 - set_icc 0x03,0 ; Set mask opposite of expected - cmpba gr7,gr8,icc0 - test_icc 0 0 0 1 icc0 - - set_gr_limmed 0xbeef,0xdead,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - cmpba gr7,gr8,icc0 - test_icc 0 0 0 0 icc0 - - pass diff --git a/sim/testsuite/sim/frv/cmpi.cgs b/sim/testsuite/sim/frv/cmpi.cgs deleted file mode 100644 index a8324db5531..00000000000 --- a/sim/testsuite/sim/frv/cmpi.cgs +++ /dev/null @@ -1,50 +0,0 @@ -# frv testcase for cmpi $GRi,$s12,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global cmpi -cmpi: - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - cmpi gr8,1,icc0 - test_icc 0 0 0 0 icc0 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - cmpi gr8,1,icc0 - test_icc 0 0 1 0 icc0 - - set_gr_immed 0x1ff,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - cmpi gr8,0x1ff,icc0 - test_icc 0 1 0 0 icc0 - - set_gr_immed 0,gr8 - set_icc 0x06,0 ; Set mask opposite of expected - cmpi gr8,1,icc0 - test_icc 1 0 0 1 icc0 - - set_gr_immed 2,gr8 - set_icc 0x0e,0 ; Set mask opposite of expected - cmpi gr8,-1,icc0 - test_icc 0 0 0 1 icc0 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x06,0 ; Set mask opposite of expected - cmpi gr8,-1,icc0 - test_icc 1 0 0 1 icc0 - - set_gr_immed -512,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - cmpi gr8,-512,icc0 - test_icc 0 1 0 0 icc0 - - set_gr_immed 0,gr8 - set_icc 0x0e,0 ; Set mask opposite of expected - cmpi gr8,-1,icc0 - test_icc 0 0 0 1 icc0 - - pass diff --git a/sim/testsuite/sim/frv/cmqmachs.cgs b/sim/testsuite/sim/frv/cmqmachs.cgs deleted file mode 100644 index 4acd62a73af..00000000000 --- a/sim/testsuite/sim/frv/cmqmachs.cgs +++ /dev/null @@ -1,1268 +0,0 @@ -# frv testcase for cmqmachs $GRi,$GRj,$ACCk,$CCi,$cond -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global cmqmachs -cmqmachs: - set_spr_immed 0x1b1b,cccr - - ; Positive operands - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0,accg0 - set_acc_immed 0,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmachs fr8,fr10,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachs fr8,fr10,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0,0x7ffe,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0,0x7ffe,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8008,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8008,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x7fff,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x7fff,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmachs fr8,fr10,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8002,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x7ffd,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x7ffd,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmachs fr8,fr10,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8002,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x3ffb,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x3ffb,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0002,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffb,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffb,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmachs fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0008,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0008,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffd,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffd,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachs fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0009,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0009,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x3fffbffd,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x3fffbffd,acc3 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 1,0xffff,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0x80,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - - ; Positive operands - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0,accg0 - set_acc_immed 0,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmachs fr8,fr10,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachs fr8,fr10,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0,0x7ffe,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0,0x7ffe,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8008,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8008,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x7fff,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x7fff,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmachs fr8,fr10,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8002,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x7ffd,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x7ffd,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmachs fr8,fr10,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8002,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x3ffb,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x3ffb,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0002,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffb,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffb,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmachs fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0008,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0008,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffd,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffd,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachs fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0009,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0009,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x3fffbffd,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x3fffbffd,acc3 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 1,0xffff,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0x80,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - - ; Positive operands - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmachs fr8,fr10,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachs fr8,fr10,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmachs fr8,fr10,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmachs fr8,fr10,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmachs fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachs fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0x7f,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_immed 0xffffffff,acc3 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 1,0xffff,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0x80,accg2 ; saturation - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - - ; Positive operands - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmachs fr8,fr10,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachs fr8,fr10,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmachs fr8,fr10,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmachs fr8,fr10,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmachs fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachs fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0x7f,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_immed 0xffffffff,acc3 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 1,0xffff,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0x80,accg2 ; saturation - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - - ; Positive operands - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmachs fr8,fr10,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachs fr8,fr10,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmachs fr8,fr10,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmachs fr8,fr10,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmachs fr8,fr10,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachs fr8,fr10,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0x7f,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_immed 0xffffffff,acc3 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 1,0xffff,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0x80,accg2 ; saturation - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 -; - ; Positive operands - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmachs fr8,fr10,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachs fr8,fr10,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmachs fr8,fr10,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmachs fr8,fr10,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmachs fr8,fr10,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachs fr8,fr10,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0x7f,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_immed 0xffffffff,acc3 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 1,0xffff,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0x80,accg2 ; saturation - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - - pass - - diff --git a/sim/testsuite/sim/frv/cmqmachu.cgs b/sim/testsuite/sim/frv/cmqmachu.cgs deleted file mode 100644 index 1be138952f0..00000000000 --- a/sim/testsuite/sim/frv/cmqmachu.cgs +++ /dev/null @@ -1,876 +0,0 @@ -# frv testcase for cmqmachu $GRi,$GRj,$GRk,$CCi,$cond -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global cmqmachu -cmqmachu: - set_spr_immed 0x1b1b,cccr - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0,accg0 - set_acc_immed 0,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmachu fr8,fr10,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 2,acc2 - test_accg_immed 0,accg3 - test_acc_immed 2,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachu fr8,fr10,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8000,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8006,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x00018000,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x00018000,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x3fff8007,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff8007,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x4001,0x8000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x4001,0x8000,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 1,accg0 - test_acc_limmed 0x3ffd,0x8008,acc0 - test_accg_immed 1,accg1 - test_acc_limmed 0x3ffd,0x8008,acc1 - test_accg_immed 1,accg2 - test_acc_limmed 0x3fff,0x8001,acc2 - test_accg_immed 1,accg3 - test_acc_limmed 0x3fff,0x8001,acc3 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0xff,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 1,1,fr9 - set_fr_iimmed 1,1,fr11 - cmqmachu fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_fr_iimmed 0xffff,0x0000,fr8 - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0x0000,0xffff,fr9 - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0,accg0 - set_acc_immed 0,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmachu fr8,fr10,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 2,acc2 - test_accg_immed 0,accg3 - test_acc_immed 2,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachu fr8,fr10,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8000,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8006,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x00018000,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x00018000,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x3fff8007,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff8007,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x4001,0x8000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x4001,0x8000,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 1,accg0 - test_acc_limmed 0x3ffd,0x8008,acc0 - test_accg_immed 1,accg1 - test_acc_limmed 0x3ffd,0x8008,acc1 - test_accg_immed 1,accg2 - test_acc_limmed 0x3fff,0x8001,acc2 - test_accg_immed 1,accg3 - test_acc_limmed 0x3fff,0x8001,acc3 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0xff,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 1,1,fr9 - set_fr_iimmed 1,1,fr11 - cmqmachu fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_fr_iimmed 0xffff,0x0000,fr8 - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0x0000,0xffff,fr9 - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmachu fr8,fr10,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachu fr8,fr10,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0xff,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 1,1,fr9 - set_fr_iimmed 1,1,fr11 - cmqmachu fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0xff,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed 0xffffffff,acc3 - - set_fr_iimmed 0xffff,0x0000,fr8 - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0x0000,0xffff,fr9 - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0xff,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed 0xffffffff,acc3 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmachu fr8,fr10,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachu fr8,fr10,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0xff,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 1,1,fr9 - set_fr_iimmed 1,1,fr11 - cmqmachu fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0xff,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed 0xffffffff,acc3 - - set_fr_iimmed 0xffff,0x0000,fr8 - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0x0000,0xffff,fr9 - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0xff,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed 0xffffffff,acc3 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmachu fr8,fr10,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachu fr8,fr10,acc0,cc2,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc6,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0xff,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 1,1,fr9 - set_fr_iimmed 1,1,fr11 - cmqmachu fr8,fr10,acc0,cc6,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0xff,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed 0xffffffff,acc3 - - set_fr_iimmed 0xffff,0x0000,fr8 - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0x0000,0xffff,fr9 - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0xff,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed 0xffffffff,acc3 -; - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmachu fr8,fr10,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachu fr8,fr10,acc0,cc3,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc7,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0xff,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 1,1,fr9 - set_fr_iimmed 1,1,fr11 - cmqmachu fr8,fr10,acc0,cc7,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0xff,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed 0xffffffff,acc3 - - set_fr_iimmed 0xffff,0x0000,fr8 - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0x0000,0xffff,fr9 - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0xff,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed 0xffffffff,acc3 - - pass diff --git a/sim/testsuite/sim/frv/cmqmulhs.cgs b/sim/testsuite/sim/frv/cmqmulhs.cgs deleted file mode 100644 index b3157373bfc..00000000000 --- a/sim/testsuite/sim/frv/cmqmulhs.cgs +++ /dev/null @@ -1,734 +0,0 @@ -# frv testcase for cmqmulhs $GRi,$GRj,$ACCk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmqmulhs -cmqmulhs: - set_spr_immed 0x1b1b,cccr - - ; Positive operands - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmulhs fr8,fr10,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmulhs fr8,fr10,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0,0x7ffe,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0,0x7ffe,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmulhs fr8,fr10,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8000,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x0001,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x0001,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmulhs fr8,fr10,acc0,cc0,1 - test_accg_immed 0xff,accg0 - test_acc_immed -6,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -6,acc1 - test_accg_immed 0xff,accg2 - test_acc_immed -2,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed -2,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmulhs fr8,fr10,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffe,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffe,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmulhs fr8,fr10,acc0,cc4,1 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x8000,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0x8000,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xc000,0x8000,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xc000,0x8000,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmulhs fr8,fr10,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 2,acc2 - test_accg_immed 0,accg3 - test_acc_immed 2,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmulhs fr8,fr10,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x40000000,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x40000000,acc3 - - ; Positive operands - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmulhs fr8,fr10,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmulhs fr8,fr10,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0,0x7ffe,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0,0x7ffe,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmulhs fr8,fr10,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8000,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x0001,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x0001,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmulhs fr8,fr10,acc0,cc1,0 - test_accg_immed 0xff,accg0 - test_acc_immed -6,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -6,acc1 - test_accg_immed 0xff,accg2 - test_acc_immed -2,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed -2,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmulhs fr8,fr10,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffe,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffe,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmulhs fr8,fr10,acc0,cc5,0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x8000,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0x8000,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xc000,0x8000,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xc000,0x8000,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmulhs fr8,fr10,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 2,acc2 - test_accg_immed 0,accg3 - test_acc_immed 2,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmulhs fr8,fr10,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x40000000,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x40000000,acc3 - - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmulhs fr8,fr10,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmulhs fr8,fr10,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmulhs fr8,fr10,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmulhs fr8,fr10,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmulhs fr8,fr10,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmulhs fr8,fr10,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmulhs fr8,fr10,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmulhs fr8,fr10,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmulhs fr8,fr10,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmulhs fr8,fr10,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmulhs fr8,fr10,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmulhs fr8,fr10,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmulhs fr8,fr10,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmulhs fr8,fr10,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmulhs fr8,fr10,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmulhs fr8,fr10,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmulhs fr8,fr10,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmulhs fr8,fr10,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmulhs fr8,fr10,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmulhs fr8,fr10,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmulhs fr8,fr10,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmulhs fr8,fr10,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmulhs fr8,fr10,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmulhs fr8,fr10,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 -; - ; Positive operands - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmulhs fr8,fr10,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmulhs fr8,fr10,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmulhs fr8,fr10,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmulhs fr8,fr10,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmulhs fr8,fr10,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmulhs fr8,fr10,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmulhs fr8,fr10,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmulhs fr8,fr10,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - pass diff --git a/sim/testsuite/sim/frv/cmqmulhu.cgs b/sim/testsuite/sim/frv/cmqmulhu.cgs deleted file mode 100644 index 36f0c2f45b1..00000000000 --- a/sim/testsuite/sim/frv/cmqmulhu.cgs +++ /dev/null @@ -1,464 +0,0 @@ -# frv testcase for cmqmulhu $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmqmulhu -cmqmulhu: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmulhu fr8,fr10,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 2,acc2 - test_accg_immed 0,accg3 - test_acc_immed 2,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmulhu fr8,fr10,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x7ffe,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x7ffe,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmulhu fr8,fr10,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8000,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x00010000,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x00010000,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmulhu fr8,fr10,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x4000,0x0000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x4000,0x0000,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmulhu fr8,fr10,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0xfffe,0x0001,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0xfffe,0x0001,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0xfffe,0x0001,acc3 - - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmulhu fr8,fr10,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 2,acc2 - test_accg_immed 0,accg3 - test_acc_immed 2,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmulhu fr8,fr10,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x7ffe,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x7ffe,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmulhu fr8,fr10,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8000,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x00010000,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x00010000,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmulhu fr8,fr10,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x4000,0x0000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x4000,0x0000,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmulhu fr8,fr10,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0xfffe,0x0001,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0xfffe,0x0001,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0xfffe,0x0001,acc3 - - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmulhu fr8,fr10,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmulhu fr8,fr10,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmulhu fr8,fr10,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmulhu fr8,fr10,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmulhu fr8,fr10,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmulhu fr8,fr10,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmulhu fr8,fr10,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmulhu fr8,fr10,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmulhu fr8,fr10,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmulhu fr8,fr10,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmulhu fr8,fr10,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmulhu fr8,fr10,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmulhu fr8,fr10,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmulhu fr8,fr10,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmulhu fr8,fr10,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 -; - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmulhu fr8,fr10,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmulhu fr8,fr10,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmulhu fr8,fr10,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmulhu fr8,fr10,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmulhu fr8,fr10,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - pass diff --git a/sim/testsuite/sim/frv/cmsubhss.cgs b/sim/testsuite/sim/frv/cmsubhss.cgs deleted file mode 100644 index 386b27d1a14..00000000000 --- a/sim/testsuite/sim/frv/cmsubhss.cgs +++ /dev/null @@ -1,562 +0,0 @@ -# frv testcase for cmsubhss $FRi,$FRj,$FRj,$CCi,$cond -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global cmsubhss -cmsubhss: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmsubhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0xdead,0x4111,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x4111,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x0123,0x4567,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x1235,0x5679,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc4,1 - test_fr_limmed 0x7fff,0x7fff,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhss fr10,fr11,fr12,cc4,1 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhss fr10,fr11,fr12,cc4,1 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmsubhss.p fr10,fr10,fr12,cc4,1 - cmsubhss fr11,fr10,fr13,cc4,1 - test_fr_limmed 0x0000,0x0000,fr12 - test_fr_limmed 0x8000,0x8000,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmsubhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0xdead,0x4111,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x4111,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x0123,0x4567,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x1235,0x5679,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc5,0 - test_fr_limmed 0x7fff,0x7fff,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhss fr10,fr11,fr12,cc5,0 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhss fr10,fr11,fr12,cc5,0 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmsubhss.p fr10,fr10,fr12,cc5,0 - cmsubhss fr11,fr10,fr13,cc5,0 - test_fr_limmed 0x0000,0x0000,fr12 - test_fr_limmed 0x8000,0x8000,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmsubhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhss fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhss fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmsubhss.p fr10,fr10,fr12,cc4,0 - cmsubhss fr11,fr10,fr13,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmsubhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhss fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhss fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmsubhss.p fr10,fr10,fr12,cc5,1 - cmsubhss fr11,fr10,fr13,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmsubhss fr10,fr11,fr12,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhss fr10,fr11,fr12,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhss fr10,fr11,fr12,cc6,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhss fr10,fr11,fr12,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmsubhss.p fr10,fr10,fr12,cc6,1 - cmsubhss fr11,fr10,fr13,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set -; - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmsubhss fr10,fr11,fr12,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhss fr10,fr11,fr12,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc7,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhss fr10,fr11,fr12,cc7,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhss fr10,fr11,fr12,cc7,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmsubhss.p fr10,fr10,fr12,cc7,1 - cmsubhss fr11,fr10,fr13,cc7,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - pass diff --git a/sim/testsuite/sim/frv/cmsubhus.cgs b/sim/testsuite/sim/frv/cmsubhus.cgs deleted file mode 100644 index 2a8f3434c78..00000000000 --- a/sim/testsuite/sim/frv/cmsubhus.cgs +++ /dev/null @@ -1,442 +0,0 @@ -# frv testcase for cmsubhus $FRi,$FRj,$FRj,$CCi,$cond -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global cmsubhus -cmsubhus: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0xbeef,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc0,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhus fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x0123,0x4567,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x7ffc,0x7ffd,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhus fr10,fr11,fr12,cc4,1 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc4,1 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - cmsubhus.p fr10,fr10,fr12,cc4,1 - cmsubhus fr10,fr11,fr13,cc4,1 - test_fr_limmed 0x0000,0x0000,fr12 - test_fr_limmed 0x0000,0x0000,fr13 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0xbeef,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc1,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhus fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x0123,0x4567,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x7ffc,0x7ffd,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhus fr10,fr11,fr12,cc5,0 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc5,0 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - cmsubhus.p fr10,fr10,fr12,cc5,0 - cmsubhus fr10,fr11,fr13,cc5,0 - test_fr_limmed 0x0000,0x0000,fr12 - test_fr_limmed 0x0000,0x0000,fr13 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhus fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhus fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - cmsubhus.p fr10,fr10,fr12,cc4,0 - cmsubhus fr10,fr11,fr13,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhus fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhus fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - cmsubhus.p fr10,fr10,fr12,cc5,1 - cmsubhus fr10,fr11,fr13,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhus fr10,fr11,fr12,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhus fr10,fr11,fr12,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc6,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - cmsubhus.p fr10,fr10,fr12,cc6,0 - cmsubhus fr10,fr11,fr13,cc6,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set -; - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhus fr10,fr11,fr12,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhus fr10,fr11,fr12,cc7,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc7,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - cmsubhus.p fr10,fr10,fr12,cc7,0 - cmsubhus fr10,fr11,fr13,cc7,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - pass diff --git a/sim/testsuite/sim/frv/cmxor.cgs b/sim/testsuite/sim/frv/cmxor.cgs deleted file mode 100644 index 236e2fed0e4..00000000000 --- a/sim/testsuite/sim/frv/cmxor.cgs +++ /dev/null @@ -1,132 +0,0 @@ -# frv testcase for cmxor $FRinti,$FRintj,$FRintk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cmxor -cmxor: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmxor fr7,fr8,fr8,cc0,1 - test_fr_iimmed 0xffffffff,fr8 - - set_fr_iimmed 0x0000,0x0000,fr7 - set_fr_iimmed 0x0000,0x0000,fr8 - cmxor fr7,fr8,fr8,cc0,1 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - cmxor fr7,fr8,fr8,cc4,1 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xdead,0x0000,fr7 - set_fr_iimmed 0x0000,0xbeef,fr8 - cmxor fr7,fr8,fr8,cc4,1 - test_fr_iimmed 0xdeadbeef,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmxor fr7,fr8,fr8,cc1,0 - test_fr_iimmed 0xffffffff,fr8 - - set_fr_iimmed 0x0000,0x0000,fr7 - set_fr_iimmed 0x0000,0x0000,fr8 - cmxor fr7,fr8,fr8,cc1,0 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - cmxor fr7,fr8,fr8,cc5,0 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xdead,0x0000,fr7 - set_fr_iimmed 0x0000,0xbeef,fr8 - cmxor fr7,fr8,fr8,cc5,0 - test_fr_iimmed 0xdeadbeef,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmxor fr7,fr8,fr8,cc0,0 - test_fr_iimmed 0x55555555,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr7 - set_fr_iimmed 0x0000,0x0000,fr8 - cmxor fr7,fr8,fr8,cc0,0 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - cmxor fr7,fr8,fr8,cc4,0 - test_fr_iimmed 0xaaaaaaaa,fr8 - - set_fr_iimmed 0xdead,0x0000,fr7 - set_fr_iimmed 0x0000,0xbeef,fr8 - cmxor fr7,fr8,fr8,cc4,0 - test_fr_iimmed 0x0000beef,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmxor fr7,fr8,fr8,cc1,1 - test_fr_iimmed 0x55555555,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr7 - set_fr_iimmed 0x0000,0x0000,fr8 - cmxor fr7,fr8,fr8,cc1,1 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - cmxor fr7,fr8,fr8,cc5,1 - test_fr_iimmed 0xaaaaaaaa,fr8 - - set_fr_iimmed 0xdead,0x0000,fr7 - set_fr_iimmed 0x0000,0xbeef,fr8 - cmxor fr7,fr8,fr8,cc5,1 - test_fr_iimmed 0x0000beef,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmxor fr7,fr8,fr8,cc2,0 - test_fr_iimmed 0x55555555,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr7 - set_fr_iimmed 0x0000,0x0000,fr8 - cmxor fr7,fr8,fr8,cc2,1 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - cmxor fr7,fr8,fr8,cc6,0 - test_fr_iimmed 0xaaaaaaaa,fr8 - - set_fr_iimmed 0xdead,0x0000,fr7 - set_fr_iimmed 0x0000,0xbeef,fr8 - cmxor fr7,fr8,fr8,cc6,1 - test_fr_iimmed 0x0000beef,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - cmxor fr7,fr8,fr8,cc3,0 - test_fr_iimmed 0x55555555,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr7 - set_fr_iimmed 0x0000,0x0000,fr8 - cmxor fr7,fr8,fr8,cc3,1 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - cmxor fr7,fr8,fr8,cc7,0 - test_fr_iimmed 0xaaaaaaaa,fr8 - - set_fr_iimmed 0xdead,0x0000,fr7 - set_fr_iimmed 0x0000,0xbeef,fr8 - cmxor fr7,fr8,fr8,cc7,1 - test_fr_iimmed 0x0000beef,fr8 - - pass diff --git a/sim/testsuite/sim/frv/cnot.cgs b/sim/testsuite/sim/frv/cnot.cgs deleted file mode 100644 index 3169887914d..00000000000 --- a/sim/testsuite/sim/frv/cnot.cgs +++ /dev/null @@ -1,60 +0,0 @@ -# frv testcase for cnot $GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global cnot -cnot: - set_spr_immed 0x1b1b,cccr - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - cnot gr7,gr7,cc0,1 - test_gr_limmed 0x5555,0x5555,gr7 - - set_gr_limmed 0xdead,0xbeef,gr7 - cnot gr7,gr7,cc4,1 - test_gr_limmed 0x2152,0x4110,gr7 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - cnot gr7,gr7,cc0,0 - test_gr_limmed 0xaaaa,0xaaaa,gr7 - - set_gr_limmed 0xdead,0xbeef,gr7 - cnot gr7,gr7,cc4,0 - test_gr_limmed 0xdead,0xbeef,gr7 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - cnot gr7,gr7,cc1,0 - test_gr_limmed 0x5555,0x5555,gr7 - - set_gr_limmed 0xdead,0xbeef,gr7 - cnot gr7,gr7,cc5,0 - test_gr_limmed 0x2152,0x4110,gr7 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - cnot gr7,gr7,cc1,1 - test_gr_limmed 0xaaaa,0xaaaa,gr7 - - set_gr_limmed 0xdead,0xbeef,gr7 - cnot gr7,gr7,cc5,1 - test_gr_limmed 0xdead,0xbeef,gr7 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - cnot gr7,gr7,cc2,0 - test_gr_limmed 0xaaaa,0xaaaa,gr7 - - set_gr_limmed 0xdead,0xbeef,gr7 - cnot gr7,gr7,cc6,1 - test_gr_limmed 0xdead,0xbeef,gr7 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - cnot gr7,gr7,cc3,0 - test_gr_limmed 0xaaaa,0xaaaa,gr7 - - set_gr_limmed 0xdead,0xbeef,gr7 - cnot gr7,gr7,cc7,1 - test_gr_limmed 0xdead,0xbeef,gr7 - - pass diff --git a/sim/testsuite/sim/frv/commitfa.cgs b/sim/testsuite/sim/frv/commitfa.cgs deleted file mode 100644 index 8208cab5226..00000000000 --- a/sim/testsuite/sim/frv/commitfa.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for commitfa -# mach: frv - - .include "testutils.inc" - - start - - .global commitfa -commitfa: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x190,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_psr_et 1 - set_gr_immed 0,gr15 - - nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 - nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 - nldfi @(sp,0),fr52 ; Activate fr52 with nesr.fr==1 - set_spr_immed 0x00000000,fner1 - set_spr_immed 0x00000000,fner0 - set_spr_addr bad,lr - commitfa ; should be nop - test_spr_immed 0x00000000,fner1 - test_spr_immed 0x00000000,fner0 - test_spr_immed 0xd4800001,nesr0 - test_spr_gr neear0,sp - test_spr_immed 0x94800401,nesr1 - test_spr_gr neear1,sp - test_spr_immed 0xf4800801,nesr2 - test_spr_gr neear2,sp - - or_spr_immed 0x00100000,fner1 - or_spr_immed 0x00200000,fner1 - or_spr_immed 0x00100000,fner0 - set_spr_addr ok,lr - set_gr_addr com1,gr16 -com1: commitfa - test_gr_immed 1,gr15 - - pass - -ok: test_spr_immed 0x1,esfr1 ; esr0 is active - test_spr_gr epcr0,gr16 - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x14,esr0 ; esr0.ec is set - test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is clear - test_spr_bits 0x01000,12,0x0,esr0 ; esr0.edv is clear - test_spr_immed 0x00000000,fner1 - test_spr_immed 0x00000000,fner0 - test_spr_immed 0,nesr0 - test_spr_immed 0,neear0 - test_spr_immed 0x94800401,nesr1 - test_spr_gr neear1,sp - test_spr_immed 0,nesr2 - test_spr_immed 0,neear2 - inc_gr_immed 1,gr15 - rett 0 - -bad: fail diff --git a/sim/testsuite/sim/frv/commitfr.cgs b/sim/testsuite/sim/frv/commitfr.cgs deleted file mode 100644 index 97491dc38f2..00000000000 --- a/sim/testsuite/sim/frv/commitfr.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for commitfr $FRk -# mach: frv - - .include "testutils.inc" - - start - - .global commitfr -commitfr: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x190,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_psr_et 1 - set_gr_immed 0,gr15 - - nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 - nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 - nldfi @(sp,0),fr52 ; Activate fr52 with nesr.fr==1 - set_spr_immed 0x00000000,fner1 - set_spr_immed 0x00000000,fner0 - set_spr_addr bad,lr - commitfr fr20 ; should be nop - test_spr_immed 0x00000000,fner1 - test_spr_immed 0x00000000,fner0 - test_spr_immed 0xd4800001,nesr0 - test_spr_gr neear0,sp - test_spr_immed 0x94800401,nesr1 - test_spr_gr neear1,sp - test_spr_immed 0xf4800801,nesr2 - test_spr_gr neear2,sp - - or_spr_immed 0x00100000,fner1 - or_spr_immed 0x00200000,fner1 - or_spr_immed 0x00100000,fner0 - set_spr_addr ok,lr - set_gr_addr com1,gr16 -com1: commitfr fr20 - test_gr_immed 1,gr15 - - pass - -ok: test_spr_immed 0x1,esfr1 ; esr0 is active - test_spr_gr epcr0,gr16 - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x14,esr0 ; esr0.ec is set - test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is clear - test_spr_bits 0x01000,12,0x0,esr0 ; esr0.edv is clear - test_spr_immed 0x00200000,fner1 - test_spr_immed 0x00100000,fner0 - test_spr_immed 0,nesr0 - test_spr_immed 0,neear0 - test_spr_immed 0x94800401,nesr1 - test_spr_gr neear1,sp - test_spr_immed 0xf4800801,nesr2 - test_spr_gr neear2,sp - inc_gr_immed 1,gr15 - rett 0 - -bad: fail diff --git a/sim/testsuite/sim/frv/commitga.cgs b/sim/testsuite/sim/frv/commitga.cgs deleted file mode 100644 index 57100b82284..00000000000 --- a/sim/testsuite/sim/frv/commitga.cgs +++ /dev/null @@ -1,62 +0,0 @@ -# frv testcase for commitga -# mach: frv - - .include "testutils.inc" - - start - - .global commitga -commitga: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x190,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_psr_et 1 - set_gr_immed 0,gr15 - - nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 - nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 - nldi @(sp,0),gr52 ; Activate gr52 with nesr.fr==0 - set_spr_immed 0x00000000,gner1 - set_spr_immed 0x00000000,gner0 - set_spr_addr bad,lr - commitga ; should be a nop - test_gr_immed 0,gr15 - test_spr_immed 0x00000000,gner1 - test_spr_immed 0x00000000,gner0 - test_spr_immed 0x94800001,nesr0 - test_spr_gr neear0,sp - test_spr_immed 0xd4800401,nesr1 - test_spr_gr neear1,sp - test_spr_immed 0xb4800801,nesr2 - test_spr_gr neear2,sp - - or_spr_immed 0x00100000,gner1 - or_spr_immed 0x00200000,gner1 - or_spr_immed 0x00100000,gner0 - set_spr_addr ok,lr - set_gr_addr com1,gr16 -com1: commitga - test_gr_immed 1,gr15 - - pass - -ok: test_spr_immed 0x1,esfr1 ; esr0 is active - test_spr_gr epcr0,gr16 - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x14,esr0 ; esr0.ec is set - test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is clear - test_spr_bits 0x01000,12,0x0,esr0 ; esr0.edv is clear - test_spr_immed 0x00000000,gner1 - test_spr_immed 0x00000000,gner0 - test_spr_immed 0,nesr0 - test_spr_immed 0,neear0 - test_spr_immed 0xd4800401,nesr1 - test_spr_gr neear1,sp - test_spr_immed 0,nesr2 - test_spr_immed 0,neear0 - inc_gr_immed 1,gr15 - rett 0 - -bad: fail diff --git a/sim/testsuite/sim/frv/commitgr.cgs b/sim/testsuite/sim/frv/commitgr.cgs deleted file mode 100644 index 45553da052e..00000000000 --- a/sim/testsuite/sim/frv/commitgr.cgs +++ /dev/null @@ -1,62 +0,0 @@ -# frv testcase for commitgr $GRk -# mach: frv - - .include "testutils.inc" - - start - - .global commitgr -commitgr: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x190,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_psr_et 1 - set_gr_immed 0,gr15 - - nldi @(sp,0),gr20 ; Activate gr20 with nesr.fr==0 - nldfi @(sp,0),fr20 ; Activate fr20 with nesr.fr==1 - nldi @(sp,0),gr52 ; Activate gr52 with nesr.fr==0 - set_spr_immed 0x00000000,gner1 - set_spr_immed 0x00000000,gner0 - set_spr_addr bad,lr - commitgr gr20 ; should only clear ne flags - test_gr_immed 0,gr15 - test_spr_immed 0x00000000,gner1 - test_spr_immed 0x00000000,gner0 - test_spr_immed 0x94800001,nesr0 - test_spr_gr neear0,sp - test_spr_immed 0xd4800401,nesr1 - test_spr_gr neear1,sp - test_spr_immed 0xb4800801,nesr2 - test_spr_gr neear2,sp - - or_spr_immed 0x00100000,gner1 - or_spr_immed 0x00200000,gner1 - or_spr_immed 0x00100000,gner0 - set_spr_addr ok,lr - set_gr_addr com1,gr16 -com1: commitgr gr20 - test_gr_immed 1,gr15 - - pass - -ok: test_spr_immed 0x1,esfr1 ; esr0 is active - test_spr_gr epcr0,gr16 - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x14,esr0 ; esr0.ec is set - test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is clear - test_spr_bits 0x01000,12,0x0,esr0 ; esr0.edv is clear - test_spr_immed 0x00200000,gner1 - test_spr_immed 0x00100000,gner0 - test_spr_immed 0,nesr0 - test_spr_immed 0,neear0 - test_spr_immed 0xd4800401,nesr1 - test_spr_gr neear1,sp - test_spr_immed 0xb4800801,nesr2 - test_spr_gr neear2,sp - inc_gr_immed 1,gr15 - rett 0 - -bad: fail diff --git a/sim/testsuite/sim/frv/cop1.cgs b/sim/testsuite/sim/frv/cop1.cgs deleted file mode 100644 index 652e3550e0e..00000000000 --- a/sim/testsuite/sim/frv/cop1.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# frv testcase for cop1 $s6_1,$CPRi,$CPRj,$CPRk -# mach: frv - - .include "testutils.inc" - - start - - .global cop1 -cop1: - cop1 0,cpr0,cpr15,cpr31 - cop1 31,cpr32,cpr45,cpr63 - cop1 -32,cpr32,cpr45,cpr63 - - pass diff --git a/sim/testsuite/sim/frv/cop2.cgs b/sim/testsuite/sim/frv/cop2.cgs deleted file mode 100644 index 858ed2b4ce2..00000000000 --- a/sim/testsuite/sim/frv/cop2.cgs +++ /dev/null @@ -1,14 +0,0 @@ -# frv testcase for cop2 $s6_1,$CPRi,$CPRj,$CPRk -# mach: frv - - .include "testutils.inc" - - start - - .global cop2 -cop2: - cop2 0,cpr0,cpr15,cpr31 - cop2 31,cpr32,cpr45,cpr63 - cop2 -32,cpr32,cpr45,cpr63 - - pass diff --git a/sim/testsuite/sim/frv/cor.cgs b/sim/testsuite/sim/frv/cor.cgs deleted file mode 100644 index ef19985b672..00000000000 --- a/sim/testsuite/sim/frv/cor.cgs +++ /dev/null @@ -1,138 +0,0 @@ -# frv testcase for cor $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cor -cor: - set_spr_immed 0x1b1b,cccr - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc0,1 - test_icc 0 1 1 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 0x00000000,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc0,1 - test_icc 1 0 0 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc4,1 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc0,0 - test_icc 0 1 1 1 icc0 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc0,0 - test_icc 1 0 0 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc4,0 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x0000,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,1 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc1,0 - test_icc 0 1 1 1 icc1 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 0x00000000,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,1 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc1,0 - test_icc 1 0 0 0 icc1 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc5,0 - test_icc 0 1 0 1 icc1 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,1 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc1,1 - test_icc 0 1 1 1 icc1 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,1 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc1,1 - test_icc 1 0 0 0 icc1 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc5,1 - test_icc 0 1 0 1 icc1 - test_gr_limmed 0x0000,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,2 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc2,0 - test_icc 0 1 1 1 icc2 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,2 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc2,0 - test_icc 1 0 0 0 icc2 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,2 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc6,1 - test_icc 0 1 0 1 icc2 - test_gr_limmed 0x0000,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,3 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc3,0 - test_icc 0 1 1 1 icc3 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,3 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc3,0 - test_icc 1 0 0 0 icc3 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,3 ; Set mask opposite of expected - cor gr7,gr8,gr8,cc7,1 - test_icc 0 1 0 1 icc3 - test_gr_limmed 0x0000,0xbeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/corcc.cgs b/sim/testsuite/sim/frv/corcc.cgs deleted file mode 100644 index 527665802e6..00000000000 --- a/sim/testsuite/sim/frv/corcc.cgs +++ /dev/null @@ -1,138 +0,0 @@ -# frv testcase for corcc $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global corcc -corcc: - set_spr_immed 0x1b1b,cccr - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc0,1 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 0x00000000,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc0,1 - test_icc 0 1 0 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc4,1 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc0,0 - test_icc 0 1 1 1 icc0 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc0,0 - test_icc 1 0 0 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc4,0 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x0000,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,1 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc1,0 - test_icc 1 0 1 1 icc1 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 0x00000000,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,1 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc1,0 - test_icc 0 1 0 0 icc1 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc5,0 - test_icc 1 0 0 1 icc1 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,1 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc1,1 - test_icc 0 1 1 1 icc1 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,1 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc1,1 - test_icc 1 0 0 0 icc1 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc5,1 - test_icc 0 1 0 1 icc1 - test_gr_limmed 0x0000,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,2 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc2,0 - test_icc 0 1 1 1 icc2 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,2 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc2,0 - test_icc 1 0 0 0 icc2 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,2 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc6,1 - test_icc 0 1 0 1 icc2 - test_gr_limmed 0x0000,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,3 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc3,0 - test_icc 0 1 1 1 icc3 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,3 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc3,0 - test_icc 1 0 0 0 icc3 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,3 ; Set mask opposite of expected - corcc gr7,gr8,gr8,cc7,1 - test_icc 0 1 0 1 icc3 - test_gr_limmed 0x0000,0xbeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/cscan.cgs b/sim/testsuite/sim/frv/cscan.cgs deleted file mode 100644 index 505bb5a384e..00000000000 --- a/sim/testsuite/sim/frv/cscan.cgs +++ /dev/null @@ -1,394 +0,0 @@ -# frv testcase for cscan $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cscan -cscan: - set_spr_immed 0x1b1b,cccr - - set_gr_limmed 0x2aaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0x5555,gr8 - cscan gr7,gr8,gr9,cc0,1 - test_gr_immed 0,gr9 - test_gr_limmed 0x2aaa,0xaaaa,gr7 - test_gr_limmed 0xaaaa,0x5555,gr8 - - set_gr_limmed 0x2aaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaab,gr8 - cscan gr7,gr8,gr9,cc0,1 - test_gr_immed 0,gr9 - test_gr_limmed 0x2aaa,0xaaaa,gr7 - test_gr_limmed 0xaaaa,0xaaab,gr8 - - set_gr_limmed 0xd555,0x5555,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - cscan gr7,gr8,gr9,cc0,1 - test_gr_immed 63,gr9 - test_gr_limmed 0xd555,0x5555,gr7 - test_gr_limmed 0xaaaa,0xaaaa,gr8 - - set_gr_limmed 0xd555,0x5555,gr7 - set_gr_limmed 0xaaaa,0xaaab,gr8 - cscan gr7,gr8,gr9,cc0,1 - test_gr_immed 63,gr9 - test_gr_limmed 0xd555,0x5555,gr7 - test_gr_limmed 0xaaaa,0xaaab,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0x7fff,0xffff,gr8 - cscan gr7,gr8,gr9,cc0,1 - test_gr_immed 0,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xbfff,0xffff,gr8 - cscan gr7,gr8,gr9,cc4,1 - test_gr_immed 2,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xbfff,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xfffe,0xffff,gr8 - cscan gr7,gr8,gr9,cc4,1 - test_gr_immed 16,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xfffe,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xffff,0xfffd,gr8 - cscan gr7,gr8,gr9,cc4,1 - test_gr_immed 31,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xffff,0xfffd,gr8 - - set_gr_limmed 0xdead,0xbeef,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - cscan gr7,gr8,gr9,cc4,1 - test_gr_immed 7,gr9 - test_gr_limmed 0xdead,0xbeef,gr7 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0x7fff,gr9 - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - cscan gr7,gr8,gr9,cc0,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xaaaa,0xaaaa,gr7 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0xaaaa,0xaaab,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - cscan gr7,gr8,gr9,cc0,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xaaaa,0xaaab,gr7 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0x5555,0x5555,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - cscan gr7,gr8,gr9,cc0,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0x5555,0x5555,gr7 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0x5555,0x5555,gr7 - set_gr_limmed 0x5555,0x5554,gr8 - cscan gr7,gr8,gr9,cc0,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0x5555,0x5555,gr7 - test_gr_limmed 0x5555,0x5554,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0x7fff,0xffff,gr8 - cscan gr7,gr8,gr9,cc0,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xbfff,0xffff,gr8 - cscan gr7,gr8,gr9,cc4,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xbfff,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xfffe,0xffff,gr8 - cscan gr7,gr8,gr9,cc4,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xfffe,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xffff,0xfffd,gr8 - cscan gr7,gr8,gr9,cc4,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xffff,0xfffd,gr8 - - set_gr_limmed 0xdead,0xbeef,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - cscan gr7,gr8,gr9,cc4,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xdead,0xbeef,gr7 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_limmed 0x2aaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - cscan gr7,gr8,gr9,cc1,0 - test_gr_immed 0,gr9 - test_gr_limmed 0x2aaa,0xaaaa,gr7 - test_gr_limmed 0xaaaa,0xaaaa,gr8 - - set_gr_limmed 0x2aaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaab,gr8 - cscan gr7,gr8,gr9,cc1,0 - test_gr_immed 0,gr9 - test_gr_limmed 0x2aaa,0xaaaa,gr7 - test_gr_limmed 0xaaaa,0xaaab,gr8 - - set_gr_limmed 0xd555,0x5555,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - cscan gr7,gr8,gr9,cc1,0 - test_gr_immed 63,gr9 - test_gr_limmed 0xd555,0x5555,gr7 - test_gr_limmed 0xaaaa,0xaaaa,gr8 - - set_gr_limmed 0xd555,0x5555,gr7 - set_gr_limmed 0xaaaa,0xaaab,gr8 - cscan gr7,gr8,gr9,cc1,0 - test_gr_immed 63,gr9 - test_gr_limmed 0xd555,0x5555,gr7 - test_gr_limmed 0xaaaa,0xaaab,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0x7fff,0xffff,gr8 - cscan gr7,gr8,gr9,cc1,0 - test_gr_immed 0,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xbfff,0xffff,gr8 - cscan gr7,gr8,gr9,cc5,0 - test_gr_immed 2,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xbfff,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xfffe,0xffff,gr8 - cscan gr7,gr8,gr9,cc5,0 - test_gr_immed 16,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xfffe,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xffff,0xfffd,gr8 - cscan gr7,gr8,gr9,cc5,0 - test_gr_immed 31,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xffff,0xfffd,gr8 - - set_gr_limmed 0xdead,0xbeef,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - cscan gr7,gr8,gr9,cc5,0 - test_gr_immed 7,gr9 - test_gr_limmed 0xdead,0xbeef,gr7 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0x7fff,gr9 - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - cscan gr7,gr8,gr9,cc1,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xaaaa,0xaaaa,gr7 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0xaaaa,0xaaab,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - cscan gr7,gr8,gr9,cc1,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xaaaa,0xaaab,gr7 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0x5555,0x5555,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - cscan gr7,gr8,gr9,cc1,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0x5555,0x5555,gr7 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0x5555,0x5555,gr7 - set_gr_limmed 0x5555,0x5554,gr8 - cscan gr7,gr8,gr9,cc1,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0x5555,0x5555,gr7 - test_gr_limmed 0x5555,0x5554,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0x7fff,0xffff,gr8 - cscan gr7,gr8,gr9,cc1,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xbfff,0xffff,gr8 - cscan gr7,gr8,gr9,cc5,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xbfff,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xfffe,0xffff,gr8 - cscan gr7,gr8,gr9,cc5,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xfffe,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xffff,0xfffd,gr8 - cscan gr7,gr8,gr9,cc5,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xffff,0xfffd,gr8 - - set_gr_limmed 0xdead,0xbeef,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - cscan gr7,gr8,gr9,cc5,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xdead,0xbeef,gr7 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0x7fff,gr9 - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - cscan gr7,gr8,gr9,cc2,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xaaaa,0xaaaa,gr7 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0xaaaa,0xaaab,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - cscan gr7,gr8,gr9,cc2,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xaaaa,0xaaab,gr7 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0x5555,0x5555,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - cscan gr7,gr8,gr9,cc2,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0x5555,0x5555,gr7 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0x5555,0x5555,gr7 - set_gr_limmed 0x5555,0x5554,gr8 - cscan gr7,gr8,gr9,cc2,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0x5555,0x5555,gr7 - test_gr_limmed 0x5555,0x5554,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0x7fff,0xffff,gr8 - cscan gr7,gr8,gr9,cc2,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xbfff,0xffff,gr8 - cscan gr7,gr8,gr9,cc6,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xbfff,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xfffe,0xffff,gr8 - cscan gr7,gr8,gr9,cc6,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xfffe,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xffff,0xfffd,gr8 - cscan gr7,gr8,gr9,cc6,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xffff,0xfffd,gr8 - - set_gr_limmed 0xdead,0xbeef,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - cscan gr7,gr8,gr9,cc6,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xdead,0xbeef,gr7 - test_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0x7fff,gr9 - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - cscan gr7,gr8,gr9,cc3,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xaaaa,0xaaaa,gr7 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0xaaaa,0xaaab,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - cscan gr7,gr8,gr9,cc3,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xaaaa,0xaaab,gr7 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0x5555,0x5555,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - cscan gr7,gr8,gr9,cc3,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0x5555,0x5555,gr7 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_limmed 0x5555,0x5555,gr7 - set_gr_limmed 0x5555,0x5554,gr8 - cscan gr7,gr8,gr9,cc3,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0x5555,0x5555,gr7 - test_gr_limmed 0x5555,0x5554,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0x7fff,0xffff,gr8 - cscan gr7,gr8,gr9,cc3,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xbfff,0xffff,gr8 - cscan gr7,gr8,gr9,cc7,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xbfff,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xfffe,0xffff,gr8 - cscan gr7,gr8,gr9,cc7,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xfffe,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xffff,0xfffd,gr8 - cscan gr7,gr8,gr9,cc7,0 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xffff,0xfffd,gr8 - - set_gr_limmed 0xdead,0xbeef,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - cscan gr7,gr8,gr9,cc7,1 - test_gr_immed 0x7fff,gr9 - test_gr_limmed 0xdead,0xbeef,gr7 - test_gr_limmed 0xbeef,0xdead,gr8 - - pass diff --git a/sim/testsuite/sim/frv/csdiv.cgs b/sim/testsuite/sim/frv/csdiv.cgs deleted file mode 100644 index c6bfb976967..00000000000 --- a/sim/testsuite/sim/frv/csdiv.cgs +++ /dev/null @@ -1,190 +0,0 @@ -# frv testcase for csdiv $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global csdiv -csdiv: - set_spr_immed 0x1b1b,cccr - - ; simple division 12 / 3 - set_gr_immed 3,gr3 - set_gr_immed 12,gr1 - csdiv gr1,gr3,gr2,cc4,1 - test_gr_immed 4,gr2 - - ; Random example - set_gr_limmed 0x0123,0x4567,gr3 - set_gr_limmed 0xfedc,0xba98,gr1 - csdiv gr1,gr3,gr2,cc4,1 - test_gr_immed -1,gr2 - - ; Special case from the Arch Spec Vol 2 - and_spr_immed -33,isr ; turn off isr.edem - ; set up exception handler - set_psr_et 1 - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x170,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_gr_immed 0,gr15 - - ; divide will cause overflow - set_spr_addr ok1,lr - set_gr_addr e1,gr17 - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 -e1: csdiv gr1,gr3,gr2,cc4,1 - test_gr_immed 1,gr15 - test_gr_limmed 0x8000,0x0000,gr2 - - ; Special case from the Arch Spec Vol 2 - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc4,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; simple division 12 / 3 - set_gr_immed 3,gr3 - set_gr_immed 12,gr1 - csdiv gr1,gr3,gr2,cc4,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; Random example - set_gr_limmed 0x0123,0x4567,gr3 - set_gr_limmed 0xfedc,0xba98,gr1 - csdiv gr1,gr3,gr2,cc4,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; Special case from the Arch Spec Vol 2 - and_spr_immed -33,isr ; turn off isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc4,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc4,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; simple division 12 / 3 - set_gr_immed 3,gr3 - set_gr_immed 12,gr1 - csdiv gr1,gr3,gr2,cc5,0 - test_gr_immed 4,gr2 - - ; Random example - set_gr_limmed 0x0123,0x4567,gr3 - set_gr_limmed 0xfedc,0xba98,gr1 - csdiv gr1,gr3,gr2,cc5,0 - test_gr_immed -1,gr2 - - ; Special case from the Arch Spec Vol 2 - and_spr_immed -33,isr ; turn off isr.edem - ; divide will cause overflow - set_spr_addr ok1,lr - set_gr_addr e2,gr17 - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 -e2: csdiv gr1,gr3,gr2,cc5,0 - test_gr_immed 2,gr15 - test_gr_limmed 0x8000,0x0000,gr2 - - ; Special case from the Arch Spec Vol 2 - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc5,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; simple division 12 / 3 - set_gr_immed 3,gr3 - set_gr_immed 12,gr1 - csdiv gr1,gr3,gr2,cc5,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; Random example - set_gr_limmed 0x0123,0x4567,gr3 - set_gr_limmed 0xfedc,0xba98,gr1 - csdiv gr1,gr3,gr2,cc5,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; Special case from the Arch Spec Vol 2 - and_spr_immed -33,isr ; turn off isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc5,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc5,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; simple division 12 / 3 - set_gr_immed 3,gr3 - set_gr_immed 12,gr1 - csdiv gr1,gr3,gr2,cc6,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; Random example - set_gr_limmed 0x0123,0x4567,gr3 - set_gr_limmed 0xfedc,0xba98,gr1 - csdiv gr1,gr3,gr2,cc6,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; Special case from the Arch Spec Vol 2 - and_spr_immed -33,isr ; turn off isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc6,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc6,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; simple division 12 / 3 - set_gr_immed 3,gr3 - set_gr_immed 12,gr1 - csdiv gr1,gr3,gr2,cc7,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; Random example - set_gr_limmed 0x0123,0x4567,gr3 - set_gr_limmed 0xfedc,0xba98,gr1 - csdiv gr1,gr3,gr2,cc7,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; Special case from the Arch Spec Vol 2 - and_spr_immed -33,isr ; turn off isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc7,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc7,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - pass - -ok1: ; exception handler for overflow - test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set - test_spr_gr epcr0,gr17 ; return address set - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/csll.cgs b/sim/testsuite/sim/frv/csll.cgs deleted file mode 100644 index 0186756fed6..00000000000 --- a/sim/testsuite/sim/frv/csll.cgs +++ /dev/null @@ -1,180 +0,0 @@ -# frv testcase for csll $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global csll -csll: - set_spr_immed 0x1b1b,cccr - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_immed 2,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc0,1 - test_icc 1 1 0 1 icc0 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc0,1 - test_icc 1 1 1 1 icc0 - test_gr_immed 4,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_immed 1,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc4,1 - test_icc 0 1 1 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_immed 2,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc4,1 - test_icc 1 0 1 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_immed 2,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc0,0 - test_icc 1 1 0 1 icc0 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc0,0 - test_icc 1 1 1 1 icc0 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_immed 1,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc4,0 - test_icc 0 1 1 1 icc0 - test_gr_immed 1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_immed 2,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc4,0 - test_icc 1 0 1 0 icc0 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_immed 2,gr8 - set_icc 0x0d,1 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc1,0 - test_icc 1 1 0 1 icc1 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_immed 2,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc1,0 - test_icc 1 1 1 1 icc1 - test_gr_immed 4,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_immed 1,gr8 - set_icc 0x07,1 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc5,0 - test_icc 0 1 1 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_immed 2,gr8 - set_icc 0x0a,1 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc5,0 - test_icc 1 0 1 0 icc1 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_immed 2,gr8 - set_icc 0x0d,1 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc1,1 - test_icc 1 1 0 1 icc1 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_immed 2,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc1,1 - test_icc 1 1 1 1 icc1 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_immed 1,gr8 - set_icc 0x07,1 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc5,1 - test_icc 0 1 1 1 icc1 - test_gr_immed 1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_immed 2,gr8 - set_icc 0x0a,1 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc5,1 - test_icc 1 0 1 0 icc1 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_immed 2,gr8 - set_icc 0x0d,2 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc2,0 - test_icc 1 1 0 1 icc2 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_immed 2,gr8 - set_icc 0x0f,2 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc2,0 - test_icc 1 1 1 1 icc2 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_immed 1,gr8 - set_icc 0x07,2 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc6,1 - test_icc 0 1 1 1 icc2 - test_gr_immed 1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_immed 2,gr8 - set_icc 0x0a,2 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc6,1 - test_icc 1 0 1 0 icc2 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_immed 2,gr8 - set_icc 0x0d,3 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc3,0 - test_icc 1 1 0 1 icc3 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_immed 2,gr8 - set_icc 0x0f,3 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc3,0 - test_icc 1 1 1 1 icc3 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_immed 1,gr8 - set_icc 0x07,3 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc7,1 - test_icc 0 1 1 1 icc3 - test_gr_immed 1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_immed 2,gr8 - set_icc 0x0a,3 ; Set mask opposite of expected - csll gr8,gr7,gr8,cc7,1 - test_icc 1 0 1 0 icc3 - test_gr_immed 2,gr8 - - pass diff --git a/sim/testsuite/sim/frv/csllcc.cgs b/sim/testsuite/sim/frv/csllcc.cgs deleted file mode 100644 index 0c5b9af8ae4..00000000000 --- a/sim/testsuite/sim/frv/csllcc.cgs +++ /dev/null @@ -1,180 +0,0 @@ -# frv testcase for csllcc $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global csllcc -csllcc: - set_spr_immed 0x1b1b,cccr - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc0,1 - test_icc 0 0 0 1 icc0 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc0,1 - test_icc 0 0 0 1 icc0 - test_gr_immed 4,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_immed 1,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc4,1 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_immed 2,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc4,1 - test_icc 0 1 1 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_immed 2,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc0,0 - test_icc 1 1 0 1 icc0 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc0,0 - test_icc 1 1 1 1 icc0 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_immed 1,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc4,0 - test_icc 0 1 1 1 icc0 - test_gr_immed 1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_immed 2,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc4,0 - test_icc 1 0 1 0 icc0 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_immed 2,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc1,0 - test_icc 0 0 0 1 icc1 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_immed 2,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc1,0 - test_icc 0 0 0 1 icc1 - test_gr_immed 4,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_immed 1,gr8 - set_icc 0x07,1 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc5,0 - test_icc 1 0 0 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_immed 2,gr8 - set_icc 0x08,1 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc5,0 - test_icc 0 1 1 0 icc1 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_immed 2,gr8 - set_icc 0x0d,1 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc1,1 - test_icc 1 1 0 1 icc1 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_immed 2,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc1,1 - test_icc 1 1 1 1 icc1 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_immed 1,gr8 - set_icc 0x07,1 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc5,1 - test_icc 0 1 1 1 icc1 - test_gr_immed 1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_immed 2,gr8 - set_icc 0x0a,1 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc5,1 - test_icc 1 0 1 0 icc1 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_immed 2,gr8 - set_icc 0x0d,2 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc2,0 - test_icc 1 1 0 1 icc2 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_immed 2,gr8 - set_icc 0x0f,2 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc2,0 - test_icc 1 1 1 1 icc2 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_immed 1,gr8 - set_icc 0x07,2 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc6,1 - test_icc 0 1 1 1 icc2 - test_gr_immed 1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_immed 2,gr8 - set_icc 0x0a,2 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc6,1 - test_icc 1 0 1 0 icc2 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_immed 2,gr8 - set_icc 0x0d,3 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc3,0 - test_icc 1 1 0 1 icc3 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_immed 2,gr8 - set_icc 0x0f,3 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc3,0 - test_icc 1 1 1 1 icc3 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_immed 1,gr8 - set_icc 0x07,3 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc7,1 - test_icc 0 1 1 1 icc3 - test_gr_immed 1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_immed 2,gr8 - set_icc 0x0a,3 ; Set mask opposite of expected - csllcc gr8,gr7,gr8,cc7,1 - test_icc 1 0 1 0 icc3 - test_gr_immed 2,gr8 - - pass diff --git a/sim/testsuite/sim/frv/csmul.cgs b/sim/testsuite/sim/frv/csmul.cgs deleted file mode 100644 index 25346e7d18f..00000000000 --- a/sim/testsuite/sim/frv/csmul.cgs +++ /dev/null @@ -1,1044 +0,0 @@ -# frv testcase for csmul $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global csmul -csmul: - set_spr_immed 0x1b1b,cccr - - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed 1,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_limmed 0x3fff,0xffff,gr8 - test_gr_immed 0x00000001,gr9 - - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed -1,gr8 - test_gr_immed -6,gr9 - - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed -1,gr8 - test_gr_immed -6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed -1,gr8 - test_gr_immed -2,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed -1,gr8 - test_gr_immed -2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0xbfff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x8000,0x0000,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_limmed 0xc000,0x0000,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_immed 1,gr8 - test_gr_immed 0x00000000,gr9 - - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_gr_limmed 0x8000,0x0001,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_limmed 0x3fff,0xffff,gr8 - test_gr_immed 0x00000001,gr9 - - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - csmul gr7,gr8,gr8,cc4,1 - test_gr_limmed 0x4000,0x0000,gr8 - test_gr_immed 0x00000000,gr9 - - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed 1,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_limmed 0x3fff,0xffff,gr8 - test_gr_immed 0x00000001,gr9 - - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed -1,gr8 - test_gr_immed -6,gr9 - - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed -1,gr8 - test_gr_immed -6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed -1,gr8 - test_gr_immed -2,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed -1,gr8 - test_gr_immed -2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0xbfff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x8000,0x0000,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_limmed 0xc000,0x0000,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_immed 1,gr8 - test_gr_immed 0x00000000,gr9 - - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_gr_limmed 0x8000,0x0001,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_limmed 0x3fff,0xffff,gr8 - test_gr_immed 0x00000001,gr9 - - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - csmul gr7,gr8,gr8,cc5,0 - test_gr_limmed 0x4000,0x0000,gr8 - test_gr_immed 0x00000000,gr9 - - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed 1,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed 4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_immed 0,gr9 - - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed 1,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed -4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x8000,0x0000,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_immed 0,gr9 - - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed -1,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_immed -4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_gr_limmed 0x8000,0x0001,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_limmed 0x8000,0x0001,gr8 - test_gr_immed 0,gr9 - - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - csmul gr7,gr8,gr8,cc4,0 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_immed 0,gr9 - - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed 1,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed 4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_immed 0,gr9 - - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed 1,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed -4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x8000,0x0000,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_immed 0,gr9 - - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed -1,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_immed -4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_gr_limmed 0x8000,0x0001,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_limmed 0x8000,0x0001,gr8 - test_gr_immed 0,gr9 - - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - csmul gr7,gr8,gr8,cc5,1 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_immed 0,gr9 - - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed 1,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed 4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_immed 0,gr9 - - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed 1,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed -4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x8000,0x0000,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_immed 0,gr9 - - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed -1,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_immed -4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_gr_limmed 0x8000,0x0001,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_limmed 0x8000,0x0001,gr8 - test_gr_immed 0,gr9 - - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - csmul gr7,gr8,gr8,cc6,0 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_immed 0,gr9 - - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed 1,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed 4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_immed 0,gr9 - - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed 1,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed -4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x8000,0x0000,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_immed 0,gr9 - - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed -1,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_immed -4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_gr_limmed 0x8000,0x0001,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_limmed 0x8000,0x0001,gr8 - test_gr_immed 0,gr9 - - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - csmul gr7,gr8,gr8,cc7,1 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_immed 0,gr9 - - pass diff --git a/sim/testsuite/sim/frv/csmulcc.cgs b/sim/testsuite/sim/frv/csmulcc.cgs deleted file mode 100644 index 26c7e66e136..00000000000 --- a/sim/testsuite/sim/frv/csmulcc.cgs +++ /dev/null @@ -1,1380 +0,0 @@ -# frv testcase for csmulcc $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global csmulcc -csmulcc: - set_spr_immed 0x1b1b,cccr - - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_icc 0xc,0 - csmulcc gr7,gr8,gr8,cc0,1 - test_icc 0 0 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - set_icc 0xd,0 - csmulcc gr7,gr8,gr8,cc0,1 - test_icc 0 0 0 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_icc 0xe,0 - csmulcc gr7,gr8,gr8,cc4,1 - test_icc 0 0 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - set_icc 0xb,0 - csmulcc gr7,gr8,gr8,cc4,1 - test_icc 0 1 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_icc 0x8,0 - csmulcc gr7,gr8,gr8,cc0,1 - test_icc 0 1 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - set_icc 0xd,0 - csmulcc gr7,gr8,gr8,cc0,1 - test_icc 0 0 0 1 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - set_icc 0xe,0 - csmulcc gr7,gr8,gr8,cc4,1 - test_icc 0 0 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - set_icc 0xf,0 - csmulcc gr7,gr8,gr8,cc4,1 - test_icc 0 0 1 1 icc0 - test_gr_immed 1,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - set_icc 0xc,0 - csmulcc gr7,gr8,gr8,cc0,1 - test_icc 0 0 0 0 icc0 - test_gr_limmed 0x3fff,0xffff,gr8 - test_gr_immed 0x00000001,gr9 - - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_icc 0x5,0 - csmulcc gr7,gr8,gr8,cc0,1 - test_icc 1 0 0 1 icc0 - test_gr_immed -1,gr8 - test_gr_immed -6,gr9 - - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_icc 0x6,0 - csmulcc gr7,gr8,gr8,cc4,1 - test_icc 1 0 1 0 icc0 - test_gr_immed -1,gr8 - test_gr_immed -6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_icc 0x7,0 - csmulcc gr7,gr8,gr8,cc4,1 - test_icc 1 0 1 1 icc0 - test_gr_immed -1,gr8 - test_gr_immed -2,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_icc 0x4,0 - csmulcc gr7,gr8,gr8,cc0,1 - test_icc 1 0 0 0 icc0 - test_gr_immed -1,gr8 - test_gr_immed -2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - set_icc 0x9,0 - csmulcc gr7,gr8,gr8,cc0,1 - test_icc 0 1 0 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_icc 0xa,0 - csmulcc gr7,gr8,gr8,cc4,1 - test_icc 0 1 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_icc 0x7,0 - csmulcc gr7,gr8,gr8,cc4,1 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0xbfff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x4,0 - csmulcc gr7,gr8,gr8,cc0,1 - test_icc 1 0 0 0 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x5,0 - csmulcc gr7,gr8,gr8,cc0,1 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_icc 0x6,0 - csmulcc gr7,gr8,gr8,cc4,1 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x7,0 - csmulcc gr7,gr8,gr8,cc4,1 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0xc000,0x0000,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_icc 0xc,0 - csmulcc gr7,gr8,gr8,cc0,1 - test_icc 0 0 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_icc 0xd,0 - csmulcc gr7,gr8,gr8,cc0,1 - test_icc 0 0 0 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - set_icc 0xe,0 - csmulcc gr7,gr8,gr8,cc4,1 - test_icc 0 0 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_icc 0xf,0 - csmulcc gr7,gr8,gr8,cc4,1 - test_icc 0 0 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0xc,0 - csmulcc gr7,gr8,gr8,cc0,1 - test_icc 0 0 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_icc 0xd,0 - csmulcc gr7,gr8,gr8,cc0,1 - test_icc 0 0 0 1 icc0 - test_gr_immed 1,gr8 - test_gr_immed 0x00000000,gr9 - - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_gr_limmed 0x8000,0x0001,gr8 - set_icc 0xe,0 - csmulcc gr7,gr8,gr8,cc4,1 - test_icc 0 0 1 0 icc0 - test_gr_limmed 0x3fff,0xffff,gr8 - test_gr_immed 0x00000001,gr9 - - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0xf,0 - csmulcc gr7,gr8,gr8,cc4,1 - test_icc 0 0 1 1 icc0 - test_gr_limmed 0x4000,0x0000,gr8 - test_gr_immed 0x00000000,gr9 - - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_icc 0x0,0 - csmulcc gr7,gr8,gr8,cc0,0 - test_icc 0 0 0 0 icc0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - set_icc 0x1,0 - csmulcc gr7,gr8,gr8,cc0,0 - test_icc 0 0 0 1 icc0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_icc 0x2,0 - csmulcc gr7,gr8,gr8,cc4,0 - test_icc 0 0 1 0 icc0 - test_gr_immed 1,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - set_icc 0x3,0 - csmulcc gr7,gr8,gr8,cc4,0 - test_icc 0 0 1 1 icc0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_icc 0x4,0 - csmulcc gr7,gr8,gr8,cc0,0 - test_icc 0 1 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - set_icc 0x5,0 - csmulcc gr7,gr8,gr8,cc0,0 - test_icc 0 1 0 1 icc0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - set_icc 0x6,0 - csmulcc gr7,gr8,gr8,cc4,0 - test_icc 0 1 1 0 icc0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - set_icc 0x7,0 - csmulcc gr7,gr8,gr8,cc4,0 - test_icc 0 1 1 1 icc0 - test_gr_immed 4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - set_icc 0x8,0 - csmulcc gr7,gr8,gr8,cc0,0 - test_icc 1 0 0 0 icc0 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_immed 0,gr9 - - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_icc 0x9,0 - csmulcc gr7,gr8,gr8,cc0,0 - test_icc 1 0 0 1 icc0 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_icc 0xa,0 - csmulcc gr7,gr8,gr8,cc4,0 - test_icc 1 0 1 0 icc0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_icc 0xb,0 - csmulcc gr7,gr8,gr8,cc4,0 - test_icc 1 0 1 1 icc0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_icc 0xc,0 - csmulcc gr7,gr8,gr8,cc0,0 - test_icc 1 1 0 0 icc0 - test_gr_immed 1,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - set_icc 0xd,0 - csmulcc gr7,gr8,gr8,cc0,0 - test_icc 1 1 0 1 icc0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_icc 0xe,0 - csmulcc gr7,gr8,gr8,cc4,0 - test_icc 1 1 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_icc 0xf,0 - csmulcc gr7,gr8,gr8,cc4,0 - test_icc 1 1 1 1 icc0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x0,0 - csmulcc gr7,gr8,gr8,cc0,0 - test_icc 0 0 0 0 icc0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x1,0 - csmulcc gr7,gr8,gr8,cc0,0 - test_icc 0 0 0 1 icc0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_icc 0x2,0 - csmulcc gr7,gr8,gr8,cc4,0 - test_icc 0 0 1 0 icc0 - test_gr_immed -4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x3,0 - csmulcc gr7,gr8,gr8,cc4,0 - test_icc 0 0 1 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_immed 0,gr9 - - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_icc 0x4,0 - csmulcc gr7,gr8,gr8,cc0,0 - test_icc 0 1 0 0 icc0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_icc 0x5,0 - csmulcc gr7,gr8,gr8,cc0,0 - test_icc 0 1 0 1 icc0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - set_icc 0x6,0 - csmulcc gr7,gr8,gr8,cc4,0 - test_icc 0 1 1 0 icc0 - test_gr_immed -1,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_icc 0x7,0 - csmulcc gr7,gr8,gr8,cc4,0 - test_icc 0 1 1 1 icc0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x8,0 - csmulcc gr7,gr8,gr8,cc0,0 - test_icc 1 0 0 0 icc0 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_icc 0x9,0 - csmulcc gr7,gr8,gr8,cc0,0 - test_icc 1 0 0 1 icc0 - test_gr_immed -4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_gr_limmed 0x8000,0x0001,gr8 - set_icc 0xa,0 - csmulcc gr7,gr8,gr8,cc4,0 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0x8000,0x0001,gr8 - test_gr_immed 0,gr9 - - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0xb,0 - csmulcc gr7,gr8,gr8,cc4,0 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_immed 0,gr9 - - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_icc 0xc,1 - csmulcc gr7,gr8,gr8,cc1,0 - test_icc 0 0 0 0 icc1 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - set_icc 0xd,1 - csmulcc gr7,gr8,gr8,cc1,0 - test_icc 0 0 0 1 icc1 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_icc 0xe,1 - csmulcc gr7,gr8,gr8,cc5,0 - test_icc 0 0 1 0 icc1 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - set_icc 0xb,1 - csmulcc gr7,gr8,gr8,cc5,0 - test_icc 0 1 1 1 icc1 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_icc 0x8,1 - csmulcc gr7,gr8,gr8,cc1,0 - test_icc 0 1 0 0 icc1 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - set_icc 0xd,1 - csmulcc gr7,gr8,gr8,cc1,0 - test_icc 0 0 0 1 icc1 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - set_icc 0xe,1 - csmulcc gr7,gr8,gr8,cc5,0 - test_icc 0 0 1 0 icc1 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - set_icc 0xf,1 - csmulcc gr7,gr8,gr8,cc5,0 - test_icc 0 0 1 1 icc1 - test_gr_immed 1,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - set_icc 0xc,1 - csmulcc gr7,gr8,gr8,cc1,0 - test_icc 0 0 0 0 icc1 - test_gr_limmed 0x3fff,0xffff,gr8 - test_gr_immed 0x00000001,gr9 - - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_icc 0x5,1 - csmulcc gr7,gr8,gr8,cc1,0 - test_icc 1 0 0 1 icc1 - test_gr_immed -1,gr8 - test_gr_immed -6,gr9 - - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_icc 0x6,1 - csmulcc gr7,gr8,gr8,cc5,0 - test_icc 1 0 1 0 icc1 - test_gr_immed -1,gr8 - test_gr_immed -6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_icc 0x7,1 - csmulcc gr7,gr8,gr8,cc5,0 - test_icc 1 0 1 1 icc1 - test_gr_immed -1,gr8 - test_gr_immed -2,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_icc 0x4,1 - csmulcc gr7,gr8,gr8,cc1,0 - test_icc 1 0 0 0 icc1 - test_gr_immed -1,gr8 - test_gr_immed -2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - set_icc 0x9,1 - csmulcc gr7,gr8,gr8,cc1,0 - test_icc 0 1 0 1 icc1 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_icc 0xa,1 - csmulcc gr7,gr8,gr8,cc5,0 - test_icc 0 1 1 0 icc1 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_icc 0x7,1 - csmulcc gr7,gr8,gr8,cc5,0 - test_icc 1 0 1 1 icc1 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0xbfff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x4,1 - csmulcc gr7,gr8,gr8,cc1,0 - test_icc 1 0 0 0 icc1 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x5,1 - csmulcc gr7,gr8,gr8,cc1,0 - test_icc 1 0 0 1 icc1 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_icc 0x6,1 - csmulcc gr7,gr8,gr8,cc5,0 - test_icc 1 0 1 0 icc1 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x7,1 - csmulcc gr7,gr8,gr8,cc5,0 - test_icc 1 0 1 1 icc1 - test_gr_limmed 0xc000,0x0000,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_icc 0xc,1 - csmulcc gr7,gr8,gr8,cc1,0 - test_icc 0 0 0 0 icc1 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_icc 0xd,1 - csmulcc gr7,gr8,gr8,cc1,0 - test_icc 0 0 0 1 icc1 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - set_icc 0xe,1 - csmulcc gr7,gr8,gr8,cc5,0 - test_icc 0 0 1 0 icc1 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_icc 0xf,1 - csmulcc gr7,gr8,gr8,cc5,0 - test_icc 0 0 1 1 icc1 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0xc,1 - csmulcc gr7,gr8,gr8,cc1,0 - test_icc 0 0 0 0 icc1 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_icc 0xd,1 - csmulcc gr7,gr8,gr8,cc1,0 - test_icc 0 0 0 1 icc1 - test_gr_immed 1,gr8 - test_gr_immed 0x00000000,gr9 - - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_gr_limmed 0x8000,0x0001,gr8 - set_icc 0xe,1 - csmulcc gr7,gr8,gr8,cc5,0 - test_icc 0 0 1 0 icc1 - test_gr_limmed 0x3fff,0xffff,gr8 - test_gr_immed 0x00000001,gr9 - - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0xf,1 - csmulcc gr7,gr8,gr8,cc5,0 - test_icc 0 0 1 1 icc1 - test_gr_limmed 0x4000,0x0000,gr8 - test_gr_immed 0x00000000,gr9 - - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_icc 0x0,1 - csmulcc gr7,gr8,gr8,cc1,1 - test_icc 0 0 0 0 icc1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - set_icc 0x1,1 - csmulcc gr7,gr8,gr8,cc1,1 - test_icc 0 0 0 1 icc1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_icc 0x2,1 - csmulcc gr7,gr8,gr8,cc5,1 - test_icc 0 0 1 0 icc1 - test_gr_immed 1,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - set_icc 0x3,1 - csmulcc gr7,gr8,gr8,cc5,1 - test_icc 0 0 1 1 icc1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_icc 0x4,1 - csmulcc gr7,gr8,gr8,cc1,1 - test_icc 0 1 0 0 icc1 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - set_icc 0x5,1 - csmulcc gr7,gr8,gr8,cc1,1 - test_icc 0 1 0 1 icc1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - set_icc 0x6,1 - csmulcc gr7,gr8,gr8,cc5,1 - test_icc 0 1 1 0 icc1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - set_icc 0x7,1 - csmulcc gr7,gr8,gr8,cc5,1 - test_icc 0 1 1 1 icc1 - test_gr_immed 4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - set_icc 0x8,1 - csmulcc gr7,gr8,gr8,cc1,1 - test_icc 1 0 0 0 icc1 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_immed 0,gr9 - - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_icc 0x9,1 - csmulcc gr7,gr8,gr8,cc1,1 - test_icc 1 0 0 1 icc1 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_icc 0xa,1 - csmulcc gr7,gr8,gr8,cc5,1 - test_icc 1 0 1 0 icc1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_icc 0xb,1 - csmulcc gr7,gr8,gr8,cc5,1 - test_icc 1 0 1 1 icc1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_icc 0xc,1 - csmulcc gr7,gr8,gr8,cc1,1 - test_icc 1 1 0 0 icc1 - test_gr_immed 1,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - set_icc 0xd,1 - csmulcc gr7,gr8,gr8,cc1,1 - test_icc 1 1 0 1 icc1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_icc 0xe,1 - csmulcc gr7,gr8,gr8,cc5,1 - test_icc 1 1 1 0 icc1 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_icc 0xf,1 - csmulcc gr7,gr8,gr8,cc5,1 - test_icc 1 1 1 1 icc1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x0,1 - csmulcc gr7,gr8,gr8,cc1,1 - test_icc 0 0 0 0 icc1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x1,1 - csmulcc gr7,gr8,gr8,cc1,1 - test_icc 0 0 0 1 icc1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_icc 0x2,1 - csmulcc gr7,gr8,gr8,cc5,1 - test_icc 0 0 1 0 icc1 - test_gr_immed -4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x3,1 - csmulcc gr7,gr8,gr8,cc5,1 - test_icc 0 0 1 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_immed 0,gr9 - - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_icc 0x4,1 - csmulcc gr7,gr8,gr8,cc1,1 - test_icc 0 1 0 0 icc1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_icc 0x5,1 - csmulcc gr7,gr8,gr8,cc1,1 - test_icc 0 1 0 1 icc1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - set_icc 0x6,1 - csmulcc gr7,gr8,gr8,cc5,1 - test_icc 0 1 1 0 icc1 - test_gr_immed -1,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_icc 0x7,1 - csmulcc gr7,gr8,gr8,cc5,1 - test_icc 0 1 1 1 icc1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x8,1 - csmulcc gr7,gr8,gr8,cc1,1 - test_icc 1 0 0 0 icc1 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_icc 0x9,1 - csmulcc gr7,gr8,gr8,cc1,1 - test_icc 1 0 0 1 icc1 - test_gr_immed -4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_gr_limmed 0x8000,0x0001,gr8 - set_icc 0xa,1 - csmulcc gr7,gr8,gr8,cc5,1 - test_icc 1 0 1 0 icc1 - test_gr_limmed 0x8000,0x0001,gr8 - test_gr_immed 0,gr9 - - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0xb,1 - csmulcc gr7,gr8,gr8,cc5,1 - test_icc 1 0 1 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_immed 0,gr9 - - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_icc 0x0,2 - csmulcc gr7,gr8,gr8,cc2,0 - test_icc 0 0 0 0 icc2 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - set_icc 0x1,2 - csmulcc gr7,gr8,gr8,cc2,1 - test_icc 0 0 0 1 icc2 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_icc 0x2,2 - csmulcc gr7,gr8,gr8,cc6,0 - test_icc 0 0 1 0 icc2 - test_gr_immed 1,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - set_icc 0x3,2 - csmulcc gr7,gr8,gr8,cc6,1 - test_icc 0 0 1 1 icc2 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_icc 0x4,2 - csmulcc gr7,gr8,gr8,cc2,0 - test_icc 0 1 0 0 icc2 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - set_icc 0x5,2 - csmulcc gr7,gr8,gr8,cc2,1 - test_icc 0 1 0 1 icc2 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - set_icc 0x6,2 - csmulcc gr7,gr8,gr8,cc6,1 - test_icc 0 1 1 0 icc2 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - set_icc 0x7,2 - csmulcc gr7,gr8,gr8,cc6,0 - test_icc 0 1 1 1 icc2 - test_gr_immed 4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - set_icc 0x8,2 - csmulcc gr7,gr8,gr8,cc2,1 - test_icc 1 0 0 0 icc2 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_immed 0,gr9 - - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_icc 0x9,2 - csmulcc gr7,gr8,gr8,cc2,0 - test_icc 1 0 0 1 icc2 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_icc 0xa,2 - csmulcc gr7,gr8,gr8,cc6,1 - test_icc 1 0 1 0 icc2 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_icc 0xb,2 - csmulcc gr7,gr8,gr8,cc6,0 - test_icc 1 0 1 1 icc2 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_icc 0xc,2 - csmulcc gr7,gr8,gr8,cc2,1 - test_icc 1 1 0 0 icc2 - test_gr_immed 1,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - set_icc 0xd,2 - csmulcc gr7,gr8,gr8,cc2,0 - test_icc 1 1 0 1 icc2 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_icc 0xe,2 - csmulcc gr7,gr8,gr8,cc6,1 - test_icc 1 1 1 0 icc2 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_icc 0xf,2 - csmulcc gr7,gr8,gr8,cc6,0 - test_icc 1 1 1 1 icc2 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x0,2 - csmulcc gr7,gr8,gr8,cc2,1 - test_icc 0 0 0 0 icc2 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x1,2 - csmulcc gr7,gr8,gr8,cc2,0 - test_icc 0 0 0 1 icc2 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_icc 0x2,2 - csmulcc gr7,gr8,gr8,cc6,1 - test_icc 0 0 1 0 icc2 - test_gr_immed -4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x3,2 - csmulcc gr7,gr8,gr8,cc6,0 - test_icc 0 0 1 1 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_immed 0,gr9 - - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_icc 0x4,2 - csmulcc gr7,gr8,gr8,cc2,1 - test_icc 0 1 0 0 icc2 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_icc 0x5,2 - csmulcc gr7,gr8,gr8,cc2,0 - test_icc 0 1 0 1 icc2 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - set_icc 0x6,2 - csmulcc gr7,gr8,gr8,cc6,1 - test_icc 0 1 1 0 icc2 - test_gr_immed -1,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_icc 0x7,2 - csmulcc gr7,gr8,gr8,cc6,0 - test_icc 0 1 1 1 icc2 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x8,2 - csmulcc gr7,gr8,gr8,cc2,1 - test_icc 1 0 0 0 icc2 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_icc 0x9,2 - csmulcc gr7,gr8,gr8,cc2,0 - test_icc 1 0 0 1 icc2 - test_gr_immed -4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_gr_limmed 0x8000,0x0001,gr8 - set_icc 0xa,2 - csmulcc gr7,gr8,gr8,cc6,1 - test_icc 1 0 1 0 icc2 - test_gr_limmed 0x8000,0x0001,gr8 - test_gr_immed 0,gr9 - - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0xb,2 - csmulcc gr7,gr8,gr8,cc6,0 - test_icc 1 0 1 1 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_immed 0,gr9 - - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_icc 0x0,3 - csmulcc gr7,gr8,gr8,cc3,0 - test_icc 0 0 0 0 icc3 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - set_icc 0x1,3 - csmulcc gr7,gr8,gr8,cc3,1 - test_icc 0 0 0 1 icc3 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_icc 0x2,3 - csmulcc gr7,gr8,gr8,cc7,0 - test_icc 0 0 1 0 icc3 - test_gr_immed 1,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - set_icc 0x3,3 - csmulcc gr7,gr8,gr8,cc7,1 - test_icc 0 0 1 1 icc3 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_icc 0x4,3 - csmulcc gr7,gr8,gr8,cc3,0 - test_icc 0 1 0 0 icc3 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - set_icc 0x5,3 - csmulcc gr7,gr8,gr8,cc3,1 - test_icc 0 1 0 1 icc3 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - set_icc 0x6,3 - csmulcc gr7,gr8,gr8,cc7,1 - test_icc 0 1 1 0 icc3 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - set_icc 0x7,3 - csmulcc gr7,gr8,gr8,cc7,0 - test_icc 0 1 1 1 icc3 - test_gr_immed 4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - set_icc 0x8,3 - csmulcc gr7,gr8,gr8,cc3,1 - test_icc 1 0 0 0 icc3 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_immed 0,gr9 - - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_icc 0x9,3 - csmulcc gr7,gr8,gr8,cc3,0 - test_icc 1 0 0 1 icc3 - test_gr_immed 2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_icc 0xa,3 - csmulcc gr7,gr8,gr8,cc7,1 - test_icc 1 0 1 0 icc3 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_icc 0xb,3 - csmulcc gr7,gr8,gr8,cc7,0 - test_icc 1 0 1 1 icc3 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_icc 0xc,3 - csmulcc gr7,gr8,gr8,cc3,1 - test_icc 1 1 0 0 icc3 - test_gr_immed 1,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - set_icc 0xd,3 - csmulcc gr7,gr8,gr8,cc3,0 - test_icc 1 1 0 1 icc3 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_icc 0xe,3 - csmulcc gr7,gr8,gr8,cc7,1 - test_icc 1 1 1 0 icc3 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_icc 0xf,3 - csmulcc gr7,gr8,gr8,cc7,0 - test_icc 1 1 1 1 icc3 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x0,3 - csmulcc gr7,gr8,gr8,cc3,1 - test_icc 0 0 0 0 icc3 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x1,3 - csmulcc gr7,gr8,gr8,cc3,0 - test_icc 0 0 0 1 icc3 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_icc 0x2,3 - csmulcc gr7,gr8,gr8,cc7,1 - test_icc 0 0 1 0 icc3 - test_gr_immed -4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x3,3 - csmulcc gr7,gr8,gr8,cc7,0 - test_icc 0 0 1 1 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_immed 0,gr9 - - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_icc 0x4,3 - csmulcc gr7,gr8,gr8,cc3,1 - test_icc 0 1 0 0 icc3 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_icc 0x5,3 - csmulcc gr7,gr8,gr8,cc3,0 - test_icc 0 1 0 1 icc3 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - set_icc 0x6,3 - csmulcc gr7,gr8,gr8,cc7,1 - test_icc 0 1 1 0 icc3 - test_gr_immed -1,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_icc 0x7,3 - csmulcc gr7,gr8,gr8,cc7,0 - test_icc 0 1 1 1 icc3 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x8,3 - csmulcc gr7,gr8,gr8,cc3,1 - test_icc 1 0 0 0 icc3 - test_gr_immed -2,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_icc 0x9,3 - csmulcc gr7,gr8,gr8,cc3,0 - test_icc 1 0 0 1 icc3 - test_gr_immed -4,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_gr_limmed 0x8000,0x0001,gr8 - set_icc 0xa,3 - csmulcc gr7,gr8,gr8,cc7,1 - test_icc 1 0 1 0 icc3 - test_gr_limmed 0x8000,0x0001,gr8 - test_gr_immed 0,gr9 - - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0xb,3 - csmulcc gr7,gr8,gr8,cc7,0 - test_icc 1 0 1 1 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_immed 0,gr9 - - pass diff --git a/sim/testsuite/sim/frv/csra.cgs b/sim/testsuite/sim/frv/csra.cgs deleted file mode 100644 index f59de057d68..00000000000 --- a/sim/testsuite/sim/frv/csra.cgs +++ /dev/null @@ -1,180 +0,0 @@ -# frv testcase for csra $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global csra -csra: - set_spr_immed 0x1b1b,cccr - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc0,1 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc0,1 - test_icc 1 1 1 1 icc0 - test_gr_limmed 0xc000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc4,1 - test_icc 1 1 1 1 icc0 - test_gr_immed -1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc4,1 - test_icc 1 0 1 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc0,0 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc0,0 - test_icc 1 1 1 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc4,0 - test_icc 1 1 1 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc4,0 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc1,0 - test_icc 0 1 0 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc1,0 - test_icc 1 1 1 1 icc1 - test_gr_limmed 0xc000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc5,0 - test_icc 1 1 1 1 icc1 - test_gr_immed -1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,1 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc5,0 - test_icc 1 0 1 0 icc1 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc1,1 - test_icc 0 1 0 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc1,1 - test_icc 1 1 1 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc5,1 - test_icc 1 1 1 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,1 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc5,1 - test_icc 1 0 1 0 icc1 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,2 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc2,0 - test_icc 0 1 0 1 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,2 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc2,0 - test_icc 1 1 1 1 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,2 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc6,1 - test_icc 1 1 1 1 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,2 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc6,1 - test_icc 1 0 1 0 icc2 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,3 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc3,0 - test_icc 0 1 0 1 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,3 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc3,0 - test_icc 1 1 1 1 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,3 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc7,1 - test_icc 1 1 1 1 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,3 ; Set mask opposite of expected - csra gr8,gr7,gr8,cc7,1 - test_icc 1 0 1 0 icc3 - test_gr_limmed 0x4000,0x0000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/csracc.cgs b/sim/testsuite/sim/frv/csracc.cgs deleted file mode 100644 index 64d4cbfb56a..00000000000 --- a/sim/testsuite/sim/frv/csracc.cgs +++ /dev/null @@ -1,180 +0,0 @@ -# frv testcase for csracc $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global csracc -csracc: - set_spr_immed 0x1b1b,cccr - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc0,1 - test_icc 1 0 0 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc0,1 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0xc000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc4,1 - test_icc 1 0 1 0 icc0 - test_gr_immed -1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc4,1 - test_icc 0 1 1 1 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc0,0 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc0,0 - test_icc 1 1 1 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc4,0 - test_icc 1 1 1 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc4,0 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc1,0 - test_icc 1 0 0 0 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x07,1 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc1,0 - test_icc 1 0 1 0 icc1 - test_gr_limmed 0xc000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x07,1 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc5,0 - test_icc 1 0 1 0 icc1 - test_gr_immed -1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,1 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc5,0 - test_icc 0 1 1 1 icc1 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc1,1 - test_icc 0 1 0 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc1,1 - test_icc 1 1 1 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc5,1 - test_icc 1 1 1 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,1 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc5,1 - test_icc 1 0 1 0 icc1 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,2 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc2,0 - test_icc 0 1 0 1 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,2 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc2,0 - test_icc 1 1 1 1 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,2 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc6,1 - test_icc 1 1 1 1 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,2 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc6,1 - test_icc 1 0 1 0 icc2 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,3 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc3,0 - test_icc 0 1 0 1 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,3 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc3,0 - test_icc 1 1 1 1 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,3 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc7,1 - test_icc 1 1 1 1 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,3 ; Set mask opposite of expected - csracc gr8,gr7,gr8,cc7,1 - test_icc 1 0 1 0 icc3 - test_gr_limmed 0x4000,0x0000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/csrl.cgs b/sim/testsuite/sim/frv/csrl.cgs deleted file mode 100644 index 7a71db4bddb..00000000000 --- a/sim/testsuite/sim/frv/csrl.cgs +++ /dev/null @@ -1,180 +0,0 @@ -# frv testcase for csrl $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global csrl -csrl: - set_spr_immed 0x1b1b,cccr - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc0,1 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc0,1 - test_icc 1 1 1 1 icc0 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc4,1 - test_icc 1 1 1 1 icc0 - test_gr_immed 1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc4,1 - test_icc 1 0 1 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc0,0 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc0,0 - test_icc 1 1 1 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc4,0 - test_icc 1 1 1 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc4,0 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc1,0 - test_icc 0 1 0 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc1,0 - test_icc 1 1 1 1 icc1 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc5,0 - test_icc 1 1 1 1 icc1 - test_gr_immed 1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,1 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc5,0 - test_icc 1 0 1 0 icc1 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc1,1 - test_icc 0 1 0 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc1,1 - test_icc 1 1 1 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc5,1 - test_icc 1 1 1 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,1 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc5,1 - test_icc 1 0 1 0 icc1 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,2 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc2,0 - test_icc 0 1 0 1 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,2 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc2,0 - test_icc 1 1 1 1 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,2 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc6,1 - test_icc 1 1 1 1 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,2 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc6,1 - test_icc 1 0 1 0 icc2 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,3 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc3,0 - test_icc 0 1 0 1 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,3 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc3,0 - test_icc 1 1 1 1 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,3 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc7,1 - test_icc 1 1 1 1 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,3 ; Set mask opposite of expected - csrl gr8,gr7,gr8,cc7,1 - test_icc 1 0 1 0 icc3 - test_gr_limmed 0x4000,0x0000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/csrlcc.cgs b/sim/testsuite/sim/frv/csrlcc.cgs deleted file mode 100644 index fb89456f5a5..00000000000 --- a/sim/testsuite/sim/frv/csrlcc.cgs +++ /dev/null @@ -1,180 +0,0 @@ -# frv testcase for csrlcc $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global csrlcc -csrlcc: - set_spr_immed 0x1b1b,cccr - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc0,1 - test_icc 1 0 0 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc0,1 - test_icc 0 0 1 0 icc0 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc4,1 - test_icc 0 0 1 0 icc0 - test_gr_immed 1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc4,1 - test_icc 0 1 1 1 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc0,0 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc0,0 - test_icc 1 1 1 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc4,0 - test_icc 1 1 1 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc4,0 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc1,0 - test_icc 1 0 0 0 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc1,0 - test_icc 0 0 1 0 icc1 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc5,0 - test_icc 0 0 1 0 icc1 - test_gr_immed 1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,1 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc5,0 - test_icc 0 1 1 1 icc1 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc1,1 - test_icc 0 1 0 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc1,1 - test_icc 1 1 1 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc5,1 - test_icc 1 1 1 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,1 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc5,1 - test_icc 1 0 1 0 icc1 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,2 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc2,0 - test_icc 0 1 0 1 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,2 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc2,0 - test_icc 1 1 1 1 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,2 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc6,1 - test_icc 1 1 1 1 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,2 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc6,1 - test_icc 1 0 1 0 icc2 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,3 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc3,0 - test_icc 0 1 0 1 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,3 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc3,0 - test_icc 1 1 1 1 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,3 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc7,1 - test_icc 1 1 1 1 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,3 ; Set mask opposite of expected - csrlcc gr8,gr7,gr8,cc7,1 - test_icc 1 0 1 0 icc3 - test_gr_limmed 0x4000,0x0000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/cst.cgs b/sim/testsuite/sim/frv/cst.cgs deleted file mode 100644 index 8244edf0d27..00000000000 --- a/sim/testsuite/sim/frv/cst.cgs +++ /dev/null @@ -1,126 +0,0 @@ -# frv testcase for cst $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global cst -cst: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr21 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cst gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffff,0xffff,gr21 - - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_gr_limmed 0xeeee,0xffff,gr8 - cst gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xeeee,0xffff,gr21 - - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - set_gr_limmed 0xcccc,0xdddd,gr8 - cst gr8,@(sp,gr7),cc4,1 - test_mem_limmed 0xcccc,0xdddd,gr21 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cst gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr21 - - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_gr_limmed 0xeeee,0xffff,gr8 - cst gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr21 - - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - set_gr_limmed 0xcccc,0xdddd,gr8 - cst gr8,@(sp,gr7),cc4,0 - test_mem_limmed 0xdead,0xbeef,gr21 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cst gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffff,0xffff,gr21 - - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_gr_limmed 0xeeee,0xffff,gr8 - cst gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xeeee,0xffff,gr21 - - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - set_gr_limmed 0xcccc,0xdddd,gr8 - cst gr8,@(sp,gr7),cc5,0 - test_mem_limmed 0xcccc,0xdddd,gr21 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cst gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr21 - - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_gr_limmed 0xeeee,0xffff,gr8 - cst gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr21 - - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - set_gr_limmed 0xcccc,0xdddd,gr8 - cst gr8,@(sp,gr7),cc5,1 - test_mem_limmed 0xdead,0xbeef,gr21 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cst gr8,@(sp,gr7),cc2,0 - test_mem_limmed 0xdead,0xbeef,gr21 - - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_gr_limmed 0xeeee,0xffff,gr8 - cst gr8,@(sp,gr7),cc2,1 - test_mem_limmed 0xdead,0xbeef,gr21 - - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - set_gr_limmed 0xcccc,0xdddd,gr8 - cst gr8,@(sp,gr7),cc6,0 - test_mem_limmed 0xdead,0xbeef,gr21 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cst gr8,@(sp,gr7),cc3,1 - test_mem_limmed 0xdead,0xbeef,gr21 - - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_gr_limmed 0xeeee,0xffff,gr8 - cst gr8,@(sp,gr7),cc3,0 - test_mem_limmed 0xdead,0xbeef,gr21 - - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - set_gr_limmed 0xcccc,0xdddd,gr8 - cst gr8,@(sp,gr7),cc7,1 - test_mem_limmed 0xdead,0xbeef,gr21 - - pass diff --git a/sim/testsuite/sim/frv/cstb.cgs b/sim/testsuite/sim/frv/cstb.cgs deleted file mode 100644 index 7b62558d83c..00000000000 --- a/sim/testsuite/sim/frv/cstb.cgs +++ /dev/null @@ -1,120 +0,0 @@ -# frv testcase for cstb $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global add -add: - set_spr_immed 0x1b1b,cccr - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstb gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffad,0xbeef,sp - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xffee,gr8 - cstb gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffad,0xeeef,sp - - set_gr_immed -1,gr7 - inc_gr_immed 4,sp - set_gr_limmed 0xffff,0xff00,gr8 - cstb gr8,@(sp,gr7),cc4,1 - inc_gr_immed -4,sp - test_mem_limmed 0xffad,0xee00,sp - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstb gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,sp - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xffee,gr8 - cstb gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,sp - - set_gr_immed -1,gr7 - inc_gr_immed 4,sp - set_gr_limmed 0xffff,0xff00,gr8 - cstb gr8,@(sp,gr7),cc4,0 - inc_gr_immed -4,sp - test_mem_limmed 0xdead,0xbeef,sp - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstb gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffad,0xbeef,sp - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xffee,gr8 - cstb gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffad,0xeeef,sp - - set_gr_immed -1,gr7 - inc_gr_immed 4,sp - set_gr_limmed 0xffff,0xff00,gr8 - cstb gr8,@(sp,gr7),cc5,0 - inc_gr_immed -4,sp - test_mem_limmed 0xffad,0xee00,sp - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstb gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,sp - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xffee,gr8 - cstb gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,sp - - set_gr_immed -1,gr7 - inc_gr_immed 4,sp - set_gr_limmed 0xffff,0xff00,gr8 - cstb gr8,@(sp,gr7),cc5,1 - inc_gr_immed -4,sp - test_mem_limmed 0xdead,0xbeef,sp - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstb gr8,@(sp,gr7),cc2,0 - test_mem_limmed 0xdead,0xbeef,sp - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xffee,gr8 - cstb gr8,@(sp,gr7),cc2,1 - test_mem_limmed 0xdead,0xbeef,sp - - set_gr_immed -1,gr7 - inc_gr_immed 4,sp - set_gr_limmed 0xffff,0xff00,gr8 - cstb gr8,@(sp,gr7),cc6,0 - inc_gr_immed -4,sp - test_mem_limmed 0xdead,0xbeef,sp - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstb gr8,@(sp,gr7),cc3,1 - test_mem_limmed 0xdead,0xbeef,sp - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xffee,gr8 - cstb gr8,@(sp,gr7),cc3,0 - test_mem_limmed 0xdead,0xbeef,sp - - set_gr_immed -1,gr7 - inc_gr_immed 4,sp - set_gr_limmed 0xffff,0xff00,gr8 - cstb gr8,@(sp,gr7),cc7,1 - inc_gr_immed -4,sp - test_mem_limmed 0xdead,0xbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/cstbf.cgs b/sim/testsuite/sim/frv/cstbf.cgs deleted file mode 100644 index 23e1ae432de..00000000000 --- a/sim/testsuite/sim/frv/cstbf.cgs +++ /dev/null @@ -1,120 +0,0 @@ -# frv testcase for cstbf $FRk,@($GRi,$GRj),$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cstbf -cstbf: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr20 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstbf fr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffad,0xbeef,gr20 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xffaa,fr8 - cstbf fr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffad,0xaaef,gr20 - - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - set_fr_iimmed 0xffff,0xffbb,fr8 - cstbf fr8,@(sp,gr7),cc4,1 - test_mem_limmed 0xffad,0xaabb,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstbf fr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xffaa,fr8 - cstbf fr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - set_fr_iimmed 0xffff,0xffbb,fr8 - cstbf fr8,@(sp,gr7),cc4,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstbf fr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffad,0xbeef,gr20 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xffaa,fr8 - cstbf fr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffad,0xaaef,gr20 - - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - set_fr_iimmed 0xffff,0xffbb,fr8 - cstbf fr8,@(sp,gr7),cc5,0 - test_mem_limmed 0xffad,0xaabb,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstbf fr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xffaa,fr8 - cstbf fr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - set_fr_iimmed 0xffff,0xffbb,fr8 - cstbf fr8,@(sp,gr7),cc5,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstbf fr8,@(sp,gr7),cc2,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xffaa,fr8 - cstbf fr8,@(sp,gr7),cc2,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - set_fr_iimmed 0xffff,0xffbb,fr8 - cstbf fr8,@(sp,gr7),cc6,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstbf fr8,@(sp,gr7),cc3,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xffaa,fr8 - cstbf fr8,@(sp,gr7),cc3,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - set_fr_iimmed 0xffff,0xffbb,fr8 - cstbf fr8,@(sp,gr7),cc7,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - pass diff --git a/sim/testsuite/sim/frv/cstbfu.cgs b/sim/testsuite/sim/frv/cstbfu.cgs deleted file mode 100644 index 01943be1e88..00000000000 --- a/sim/testsuite/sim/frv/cstbfu.cgs +++ /dev/null @@ -1,152 +0,0 @@ -# frv testcase for cstbfu $FRk,@($GRi,$GRj),$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cstbfu -cstbfu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr20 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstbfu fr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffad,0xbeef,gr20 - test_gr_gr sp,gr21 - - inc_gr_immed 2,gr21 - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xffaa,fr8 - cstbfu fr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffad,0xaaef,gr20 - test_gr_gr sp,gr21 - - inc_gr_immed 1,gr21 - inc_gr_immed 2,sp - set_gr_immed -1,gr7 - set_fr_iimmed 0xffff,0xffbb,fr8 - cstbfu fr8,@(sp,gr7),cc4,1 - test_mem_limmed 0xffad,0xaabb,gr20 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_gr_gr sp,gr21 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstbfu fr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xffaa,fr8 - cstbfu fr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - inc_gr_immed 4,gr21 - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - set_fr_iimmed 0xffff,0xffbb,fr8 - cstbfu fr8,@(sp,gr7),cc4,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstbfu fr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffad,0xbeef,gr20 - test_gr_gr sp,gr21 - - inc_gr_immed 2,gr21 - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xffaa,fr8 - cstbfu fr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffad,0xaaef,gr20 - test_gr_gr sp,gr21 - - inc_gr_immed 1,gr21 - inc_gr_immed 2,sp - set_gr_immed -1,gr7 - set_fr_iimmed 0xffff,0xffbb,fr8 - cstbfu fr8,@(sp,gr7),cc5,0 - test_mem_limmed 0xffad,0xaabb,gr20 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_gr_gr sp,gr21 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstbfu fr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xffaa,fr8 - cstbfu fr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - inc_gr_immed 4,gr21 - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - set_fr_iimmed 0xffff,0xffbb,fr8 - cstbfu fr8,@(sp,gr7),cc5,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_gr_gr sp,gr21 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstbfu fr8,@(sp,gr7),cc2,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xffaa,fr8 - cstbfu fr8,@(sp,gr7),cc2,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - inc_gr_immed 4,gr21 - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - set_fr_iimmed 0xffff,0xffbb,fr8 - cstbfu fr8,@(sp,gr7),cc6,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_gr_gr sp,gr21 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstbfu fr8,@(sp,gr7),cc3,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xffaa,fr8 - cstbfu fr8,@(sp,gr7),cc3,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - inc_gr_immed 4,gr21 - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - set_fr_iimmed 0xffff,0xffbb,fr8 - cstbfu fr8,@(sp,gr7),cc7,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - pass diff --git a/sim/testsuite/sim/frv/cstbu.cgs b/sim/testsuite/sim/frv/cstbu.cgs deleted file mode 100644 index f8a9d0f1b70..00000000000 --- a/sim/testsuite/sim/frv/cstbu.cgs +++ /dev/null @@ -1,152 +0,0 @@ -# frv testcase for cstbu $GRk,@($GRi,$GRj),$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cstbu -cstbu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr21 - - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstbu gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffad,0xbeef,sp - test_gr_gr sp,gr20 - - inc_gr_immed 2,gr20 - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xffee,gr8 - cstbu gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffad,0xeeef,gr21 - test_gr_gr sp,gr20 - - inc_gr_immed 1,gr20 - set_gr_immed -1,gr7 - inc_gr_immed 2,sp - set_gr_limmed 0xffff,0xff00,gr8 - cstbu gr8,@(sp,gr7),cc4,1 - inc_gr_immed -4,sp - test_mem_limmed 0xffad,0xee00,gr21 - - set_gr_gr gr21,sp - set_gr_gr gr21,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstbu gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xffee,gr8 - cstbu gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_immed -1,gr7 - inc_gr_immed 4,gr20 - inc_gr_immed 4,sp - set_gr_limmed 0xffff,0xff00,gr8 - cstbu gr8,@(sp,gr7),cc4,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstbu gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffad,0xbeef,sp - test_gr_gr sp,gr20 - - inc_gr_immed 2,gr20 - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xffee,gr8 - cstbu gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffad,0xeeef,gr21 - test_gr_gr sp,gr20 - - inc_gr_immed 1,gr20 - set_gr_immed -1,gr7 - inc_gr_immed 2,sp - set_gr_limmed 0xffff,0xff00,gr8 - cstbu gr8,@(sp,gr7),cc5,0 - inc_gr_immed -4,sp - test_mem_limmed 0xffad,0xee00,gr21 - - set_gr_gr gr21,sp - set_gr_gr gr21,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstbu gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xffee,gr8 - cstbu gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_immed -1,gr7 - inc_gr_immed 4,gr20 - inc_gr_immed 4,sp - set_gr_limmed 0xffff,0xff00,gr8 - cstbu gr8,@(sp,gr7),cc5,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr gr21,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstbu gr8,@(sp,gr7),cc2,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xffee,gr8 - cstbu gr8,@(sp,gr7),cc2,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_immed -1,gr7 - inc_gr_immed 4,gr20 - inc_gr_immed 4,sp - set_gr_limmed 0xffff,0xff00,gr8 - cstbu gr8,@(sp,gr7),cc6,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr gr21,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstbu gr8,@(sp,gr7),cc3,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xffee,gr8 - cstbu gr8,@(sp,gr7),cc3,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_immed -1,gr7 - inc_gr_immed 4,gr20 - inc_gr_immed 4,sp - set_gr_limmed 0xffff,0xff00,gr8 - cstbu gr8,@(sp,gr7),cc7,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - pass diff --git a/sim/testsuite/sim/frv/cstd.cgs b/sim/testsuite/sim/frv/cstd.cgs deleted file mode 100644 index 6904414a73f..00000000000 --- a/sim/testsuite/sim/frv/cstd.cgs +++ /dev/null @@ -1,221 +0,0 @@ -# frv testcase for cstd $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global cstd -cstd: - set_spr_immed 0x1b1b,cccr - - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr20 - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - cstd gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xbeef,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - cstd gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xaaaa,0xaaaa,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbbbb,0xbbbb,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - set_gr_limmed 0xcccc,0xcccc,gr8 - set_gr_limmed 0xdddd,0xdddd,gr9 - cstd gr8,@(sp,gr7),cc4,1 - test_mem_limmed 0xcccc,0xcccc,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdddd,0xdddd,gr21 - - set_gr_gr gr20,gr21 - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - cstd gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - cstd gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - set_gr_limmed 0xcccc,0xcccc,gr8 - set_gr_limmed 0xdddd,0xdddd,gr9 - cstd gr8,@(sp,gr7),cc4,0 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - cstd gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xbeef,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - cstd gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xaaaa,0xaaaa,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbbbb,0xbbbb,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - set_gr_limmed 0xcccc,0xcccc,gr8 - set_gr_limmed 0xdddd,0xdddd,gr9 - cstd gr8,@(sp,gr7),cc5,0 - test_mem_limmed 0xcccc,0xcccc,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdddd,0xdddd,gr21 - - set_gr_gr gr20,gr21 - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - cstd gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - cstd gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - set_gr_limmed 0xcccc,0xcccc,gr8 - set_gr_limmed 0xdddd,0xdddd,gr9 - cstd gr8,@(sp,gr7),cc5,1 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - cstd gr8,@(sp,gr7),cc2,0 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - cstd gr8,@(sp,gr7),cc2,1 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - set_gr_limmed 0xcccc,0xcccc,gr8 - set_gr_limmed 0xdddd,0xdddd,gr9 - cstd gr8,@(sp,gr7),cc6,0 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - cstd gr8,@(sp,gr7),cc3,1 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - cstd gr8,@(sp,gr7),cc3,0 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - set_gr_limmed 0xcccc,0xcccc,gr8 - set_gr_limmed 0xdddd,0xdddd,gr9 - cstd gr8,@(sp,gr7),cc7,1 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - pass diff --git a/sim/testsuite/sim/frv/cstdf.cgs b/sim/testsuite/sim/frv/cstdf.cgs deleted file mode 100644 index fabbe93f3b6..00000000000 --- a/sim/testsuite/sim/frv/cstdf.cgs +++ /dev/null @@ -1,222 +0,0 @@ -# frv testcase for cstdf $GRk,@($GRi,$GRj),$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cstdf -cstdf: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr20 - - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - cstdf fr8,@(sp,gr7),cc0,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - set_fr_iimmed 0xbbbb,0xbbbb,fr9 - cstdf fr8,@(sp,gr7),cc0,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xaaaa,0xaaaa,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbbbb,0xbbbb,gr22 - - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - set_fr_iimmed 0xcccc,0xcccc,fr8 - set_fr_iimmed 0xdddd,0xdddd,fr9 - cstdf fr8,@(sp,gr7),cc4,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xcccc,0xcccc,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xdddd,0xdddd,gr22 - - set_gr_gr gr20,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - cstdf fr8,@(sp,gr7),cc0,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - set_fr_iimmed 0xbbbb,0xbbbb,fr9 - cstdf fr8,@(sp,gr7),cc0,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - set_fr_iimmed 0xcccc,0xcccc,fr8 - set_fr_iimmed 0xdddd,0xdddd,fr9 - cstdf fr8,@(sp,gr7),cc4,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - - set_gr_gr gr20,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - cstdf fr8,@(sp,gr7),cc1,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - set_fr_iimmed 0xbbbb,0xbbbb,fr9 - cstdf fr8,@(sp,gr7),cc1,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xaaaa,0xaaaa,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbbbb,0xbbbb,gr22 - - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - set_fr_iimmed 0xcccc,0xcccc,fr8 - set_fr_iimmed 0xdddd,0xdddd,fr9 - cstdf fr8,@(sp,gr7),cc5,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xcccc,0xcccc,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xdddd,0xdddd,gr22 - - set_gr_gr gr20,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - cstdf fr8,@(sp,gr7),cc1,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - set_fr_iimmed 0xbbbb,0xbbbb,fr9 - cstdf fr8,@(sp,gr7),cc1,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - set_fr_iimmed 0xcccc,0xcccc,fr8 - set_fr_iimmed 0xdddd,0xdddd,fr9 - cstdf fr8,@(sp,gr7),cc5,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - - set_gr_gr gr20,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - cstdf fr8,@(sp,gr7),cc2,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - set_fr_iimmed 0xbbbb,0xbbbb,fr9 - cstdf fr8,@(sp,gr7),cc2,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - set_fr_iimmed 0xcccc,0xcccc,fr8 - set_fr_iimmed 0xdddd,0xdddd,fr9 - cstdf fr8,@(sp,gr7),cc6,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - - set_gr_gr gr20,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - cstdf fr8,@(sp,gr7),cc3,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - set_fr_iimmed 0xbbbb,0xbbbb,fr9 - cstdf fr8,@(sp,gr7),cc3,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - set_fr_iimmed 0xcccc,0xcccc,fr8 - set_fr_iimmed 0xdddd,0xdddd,fr9 - cstdf fr8,@(sp,gr7),cc7,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - - pass diff --git a/sim/testsuite/sim/frv/cstdfu.cgs b/sim/testsuite/sim/frv/cstdfu.cgs deleted file mode 100644 index b489bc900c6..00000000000 --- a/sim/testsuite/sim/frv/cstdfu.cgs +++ /dev/null @@ -1,248 +0,0 @@ -# frv testcase for cstdfu $GRk,@($GRi,$GRj),$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cstdfu -cstdfu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr20 - - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - cstdfu fr8,@(sp,gr7),cc0,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - test_gr_gr sp,gr21 - - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - set_fr_iimmed 0xbbbb,0xbbbb,fr9 - cstdfu fr8,@(sp,gr7),cc0,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xaaaa,0xaaaa,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbbbb,0xbbbb,gr22 - test_gr_gr sp,gr21 - - inc_gr_immed 8,sp - set_gr_immed -8,gr7 - set_fr_iimmed 0xcccc,0xcccc,fr8 - set_fr_iimmed 0xdddd,0xdddd,fr9 - cstdfu fr8,@(sp,gr7),cc4,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xcccc,0xcccc,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xdddd,0xdddd,gr22 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - cstdfu fr8,@(sp,gr7),cc0,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - test_gr_gr sp,gr21 - - inc_gr_immed -8,sp - set_gr_gr sp,gr23 - set_gr_immed 8,gr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - set_fr_iimmed 0xbbbb,0xbbbb,fr9 - cstdfu fr8,@(sp,gr7),cc0,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - test_gr_gr sp,gr23 - - inc_gr_immed 16,sp - set_gr_gr sp,gr23 - set_gr_immed -8,gr7 - set_fr_iimmed 0xcccc,0xcccc,fr8 - set_fr_iimmed 0xdddd,0xdddd,fr9 - cstdfu fr8,@(sp,gr7),cc4,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - test_gr_gr sp,gr23 - - set_gr_gr gr20,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - cstdfu fr8,@(sp,gr7),cc1,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - test_gr_gr sp,gr21 - - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - set_fr_iimmed 0xbbbb,0xbbbb,fr9 - cstdfu fr8,@(sp,gr7),cc1,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xaaaa,0xaaaa,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbbbb,0xbbbb,gr22 - test_gr_gr sp,gr21 - - inc_gr_immed 8,sp - set_gr_immed -8,gr7 - set_fr_iimmed 0xcccc,0xcccc,fr8 - set_fr_iimmed 0xdddd,0xdddd,fr9 - cstdfu fr8,@(sp,gr7),cc5,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xcccc,0xcccc,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xdddd,0xdddd,gr22 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - cstdfu fr8,@(sp,gr7),cc1,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - test_gr_gr sp,gr21 - - inc_gr_immed -8,sp - set_gr_gr sp,gr23 - set_gr_immed 8,gr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - set_fr_iimmed 0xbbbb,0xbbbb,fr9 - cstdfu fr8,@(sp,gr7),cc1,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - test_gr_gr sp,gr23 - - inc_gr_immed 16,sp - set_gr_gr sp,gr23 - set_gr_immed -8,gr7 - set_fr_iimmed 0xcccc,0xcccc,fr8 - set_fr_iimmed 0xdddd,0xdddd,fr9 - cstdfu fr8,@(sp,gr7),cc5,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - test_gr_gr sp,gr23 - - set_gr_gr gr20,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - cstdfu fr8,@(sp,gr7),cc2,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - test_gr_gr sp,gr21 - - inc_gr_immed -8,sp - set_gr_gr sp,gr23 - set_gr_immed 8,gr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - set_fr_iimmed 0xbbbb,0xbbbb,fr9 - cstdfu fr8,@(sp,gr7),cc2,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - test_gr_gr sp,gr23 - - inc_gr_immed 16,sp - set_gr_gr sp,gr23 - set_gr_immed -8,gr7 - set_fr_iimmed 0xcccc,0xcccc,fr8 - set_fr_iimmed 0xdddd,0xdddd,fr9 - cstdfu fr8,@(sp,gr7),cc6,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - test_gr_gr sp,gr23 - - set_gr_gr gr20,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - cstdfu fr8,@(sp,gr7),cc3,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - test_gr_gr sp,gr21 - - inc_gr_immed -8,sp - set_gr_gr sp,gr23 - set_gr_immed 8,gr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - set_fr_iimmed 0xbbbb,0xbbbb,fr9 - cstdfu fr8,@(sp,gr7),cc3,0 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - test_gr_gr sp,gr23 - - inc_gr_immed 16,sp - set_gr_gr sp,gr23 - set_gr_immed -8,gr7 - set_fr_iimmed 0xcccc,0xcccc,fr8 - set_fr_iimmed 0xdddd,0xdddd,fr9 - cstdfu fr8,@(sp,gr7),cc7,1 - set_gr_gr gr21,gr22 - test_mem_limmed 0xdead,0xbeef,gr22 - inc_gr_immed 4,gr22 - test_mem_limmed 0xbeef,0xdead,gr22 - test_gr_gr sp,gr23 - - pass diff --git a/sim/testsuite/sim/frv/cstdu.cgs b/sim/testsuite/sim/frv/cstdu.cgs deleted file mode 100644 index a996ef6d1b7..00000000000 --- a/sim/testsuite/sim/frv/cstdu.cgs +++ /dev/null @@ -1,251 +0,0 @@ -# frv testcase for cstdu $GRk,@($GRi,$GRj),$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cstdu -cstdu: - set_spr_immed 0x1b1b,cccr - - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr20 - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - cstdu gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xbeef,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr20,gr21 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - cstdu gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xaaaa,0xaaaa,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbbbb,0xbbbb,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr20,gr21 - inc_gr_immed 8,sp - set_gr_immed -8,gr7 - set_gr_limmed 0xcccc,0xcccc,gr8 - set_gr_limmed 0xdddd,0xdddd,gr9 - cstdu gr8,@(sp,gr7),cc4,1 - test_mem_limmed 0xcccc,0xcccc,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdddd,0xdddd,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr20,gr21 - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - - set_gr_gr sp,gr22 - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - cstdu gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - test_gr_gr sp,gr22 - - set_gr_gr gr20,gr21 - inc_gr_immed -8,sp - set_gr_gr sp,gr22 - set_gr_immed 8,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - cstdu gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - test_gr_gr sp,gr22 - - set_gr_gr gr20,gr21 - inc_gr_immed 16,sp - set_gr_gr sp,gr22 - set_gr_immed -8,gr7 - set_gr_limmed 0xcccc,0xcccc,gr8 - set_gr_limmed 0xdddd,0xdddd,gr9 - cstdu gr8,@(sp,gr7),cc4,0 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - test_gr_gr sp,gr22 - - set_gr_gr gr20,gr21 - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - cstdu gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xbeef,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr20,gr21 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - cstdu gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xaaaa,0xaaaa,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbbbb,0xbbbb,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr20,gr21 - inc_gr_immed 8,sp - set_gr_immed -8,gr7 - set_gr_limmed 0xcccc,0xcccc,gr8 - set_gr_limmed 0xdddd,0xdddd,gr9 - cstdu gr8,@(sp,gr7),cc5,0 - test_mem_limmed 0xcccc,0xcccc,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdddd,0xdddd,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr20,gr21 - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - - set_gr_gr sp,gr22 - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - cstdu gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - test_gr_gr sp,gr22 - - set_gr_gr gr20,gr21 - inc_gr_immed -8,sp - set_gr_gr sp,gr22 - set_gr_immed 8,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - cstdu gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - test_gr_gr sp,gr22 - - set_gr_gr gr20,gr21 - inc_gr_immed 16,sp - set_gr_gr sp,gr22 - set_gr_immed -8,gr7 - set_gr_limmed 0xcccc,0xcccc,gr8 - set_gr_limmed 0xdddd,0xdddd,gr9 - cstdu gr8,@(sp,gr7),cc5,1 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - test_gr_gr sp,gr22 - - set_gr_gr gr20,gr21 - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - - set_gr_gr sp,gr22 - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - cstdu gr8,@(sp,gr7),cc2,0 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - test_gr_gr sp,gr22 - - set_gr_gr gr20,gr21 - inc_gr_immed -8,sp - set_gr_gr sp,gr22 - set_gr_immed 8,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - cstdu gr8,@(sp,gr7),cc2,1 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - test_gr_gr sp,gr22 - - set_gr_gr gr20,gr21 - inc_gr_immed 16,sp - set_gr_gr sp,gr22 - set_gr_immed -8,gr7 - set_gr_limmed 0xcccc,0xcccc,gr8 - set_gr_limmed 0xdddd,0xdddd,gr9 - cstdu gr8,@(sp,gr7),cc6,0 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - test_gr_gr sp,gr22 - - set_gr_gr gr20,gr21 - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - - set_gr_gr sp,gr22 - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - cstdu gr8,@(sp,gr7),cc3,1 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - test_gr_gr sp,gr22 - - set_gr_gr gr20,gr21 - inc_gr_immed -8,sp - set_gr_gr sp,gr22 - set_gr_immed 8,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - cstdu gr8,@(sp,gr7),cc3,0 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - test_gr_gr sp,gr22 - - set_gr_gr gr20,gr21 - inc_gr_immed 16,sp - set_gr_gr sp,gr22 - set_gr_immed -8,gr7 - set_gr_limmed 0xcccc,0xcccc,gr8 - set_gr_limmed 0xdddd,0xdddd,gr9 - cstdu gr8,@(sp,gr7),cc7,1 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - test_gr_gr sp,gr22 - - pass diff --git a/sim/testsuite/sim/frv/cstf.cgs b/sim/testsuite/sim/frv/cstf.cgs deleted file mode 100644 index 94c0f052e56..00000000000 --- a/sim/testsuite/sim/frv/cstf.cgs +++ /dev/null @@ -1,126 +0,0 @@ -# frv testcase for cstf $FRk,@($GRi,$GRj),$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cstf -cstf: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr20 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstf fr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffff,0xffff,gr20 - - set_gr_immed 4,gr7 - inc_gr_immed -4,sp - set_fr_iimmed 0xeeee,0xeeee,fr8 - cstf fr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xeeee,0xeeee,gr20 - - set_gr_immed -4,gr7 - inc_gr_immed 8,sp - set_fr_iimmed 0xdddd,0xdddd,fr8 - cstf fr8,@(sp,gr7),cc4,1 - test_mem_limmed 0xdddd,0xdddd,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstf fr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 4,gr7 - inc_gr_immed -4,sp - set_fr_iimmed 0xeeee,0xeeee,fr8 - cstf fr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed -4,gr7 - inc_gr_immed 8,sp - set_fr_iimmed 0xdddd,0xdddd,fr8 - cstf fr8,@(sp,gr7),cc4,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstf fr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffff,0xffff,gr20 - - set_gr_immed 4,gr7 - inc_gr_immed -4,sp - set_fr_iimmed 0xeeee,0xeeee,fr8 - cstf fr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xeeee,0xeeee,gr20 - - set_gr_immed -4,gr7 - inc_gr_immed 8,sp - set_fr_iimmed 0xdddd,0xdddd,fr8 - cstf fr8,@(sp,gr7),cc5,0 - test_mem_limmed 0xdddd,0xdddd,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstf fr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 4,gr7 - inc_gr_immed -4,sp - set_fr_iimmed 0xeeee,0xeeee,fr8 - cstf fr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed -4,gr7 - inc_gr_immed 8,sp - set_fr_iimmed 0xdddd,0xdddd,fr8 - cstf fr8,@(sp,gr7),cc5,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstf fr8,@(sp,gr7),cc2,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 4,gr7 - inc_gr_immed -4,sp - set_fr_iimmed 0xeeee,0xeeee,fr8 - cstf fr8,@(sp,gr7),cc2,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed -4,gr7 - inc_gr_immed 8,sp - set_fr_iimmed 0xdddd,0xdddd,fr8 - cstf fr8,@(sp,gr7),cc6,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstf fr8,@(sp,gr7),cc3,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 4,gr7 - inc_gr_immed -4,sp - set_fr_iimmed 0xeeee,0xeeee,fr8 - cstf fr8,@(sp,gr7),cc3,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed -4,gr7 - inc_gr_immed 8,sp - set_fr_iimmed 0xdddd,0xdddd,fr8 - cstf fr8,@(sp,gr7),cc7,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - pass diff --git a/sim/testsuite/sim/frv/cstfu.cgs b/sim/testsuite/sim/frv/cstfu.cgs deleted file mode 100644 index ee450c84334..00000000000 --- a/sim/testsuite/sim/frv/cstfu.cgs +++ /dev/null @@ -1,158 +0,0 @@ -# frv testcase for cstfu $FRk,@($GRi,$GRj),$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cstfu -cstfu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr20 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstfu fr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffff,0xffff,gr20 - test_gr_gr sp,gr21 - - set_gr_immed 4,gr7 - inc_gr_immed -4,sp - set_fr_iimmed 0xeeee,0xeeee,fr8 - cstfu fr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xeeee,0xeeee,gr20 - test_gr_gr sp,gr21 - - set_gr_immed -4,gr7 - inc_gr_immed 4,sp - set_fr_iimmed 0xdddd,0xdddd,fr8 - cstfu fr8,@(sp,gr7),cc4,1 - test_mem_limmed 0xdddd,0xdddd,gr20 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstfu fr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_immed 4,gr7 - inc_gr_immed -4,sp - inc_gr_immed -4,gr21 - set_fr_iimmed 0xeeee,0xeeee,fr8 - cstfu fr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_immed -4,gr7 - inc_gr_immed 8,sp - inc_gr_immed 8,gr21 - set_fr_iimmed 0xdddd,0xdddd,fr8 - cstfu fr8,@(sp,gr7),cc4,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstfu fr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffff,0xffff,gr20 - test_gr_gr sp,gr21 - - set_gr_immed 4,gr7 - inc_gr_immed -4,sp - set_fr_iimmed 0xeeee,0xeeee,fr8 - cstfu fr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xeeee,0xeeee,gr20 - test_gr_gr sp,gr21 - - set_gr_immed -4,gr7 - inc_gr_immed 4,sp - set_fr_iimmed 0xdddd,0xdddd,fr8 - cstfu fr8,@(sp,gr7),cc5,0 - test_mem_limmed 0xdddd,0xdddd,gr20 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstfu fr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_immed 4,gr7 - inc_gr_immed -4,sp - inc_gr_immed -4,gr21 - set_fr_iimmed 0xeeee,0xeeee,fr8 - cstfu fr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_immed -4,gr7 - inc_gr_immed 8,sp - inc_gr_immed 8,gr21 - set_fr_iimmed 0xdddd,0xdddd,fr8 - cstfu fr8,@(sp,gr7),cc5,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstfu fr8,@(sp,gr7),cc2,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_immed 4,gr7 - inc_gr_immed -4,sp - inc_gr_immed -4,gr21 - set_fr_iimmed 0xeeee,0xeeee,fr8 - cstfu fr8,@(sp,gr7),cc2,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_immed -4,gr7 - inc_gr_immed 8,sp - inc_gr_immed 8,gr21 - set_fr_iimmed 0xdddd,0xdddd,fr8 - cstfu fr8,@(sp,gr7),cc6,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cstfu fr8,@(sp,gr7),cc3,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_immed 4,gr7 - inc_gr_immed -4,sp - inc_gr_immed -4,gr21 - set_fr_iimmed 0xeeee,0xeeee,fr8 - cstfu fr8,@(sp,gr7),cc3,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_immed -4,gr7 - inc_gr_immed 8,sp - inc_gr_immed 8,gr21 - set_fr_iimmed 0xdddd,0xdddd,fr8 - cstfu fr8,@(sp,gr7),cc7,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - pass diff --git a/sim/testsuite/sim/frv/csth.cgs b/sim/testsuite/sim/frv/csth.cgs deleted file mode 100644 index b9f743cbd71..00000000000 --- a/sim/testsuite/sim/frv/csth.cgs +++ /dev/null @@ -1,120 +0,0 @@ -# frv testcase for csth $GRk,@($GRi,$GRj),$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global csth -csth: - set_spr_immed 0x1b1b,cccr - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - csth gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffff,0xbeef,sp - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xeeee,gr8 - csth gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffff,0xeeee,sp - - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_gr_limmed 0xffff,0xdddd,gr8 - csth gr8,@(sp,gr7),cc4,1 - inc_gr_immed -4,sp - test_mem_limmed 0xffff,0xdddd,sp - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - csth gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,sp - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xeeee,gr8 - csth gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,sp - - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_gr_limmed 0xffff,0xdddd,gr8 - csth gr8,@(sp,gr7),cc4,0 - inc_gr_immed -4,sp - test_mem_limmed 0xdead,0xbeef,sp - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - csth gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffff,0xbeef,sp - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xeeee,gr8 - csth gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffff,0xeeee,sp - - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_gr_limmed 0xffff,0xdddd,gr8 - csth gr8,@(sp,gr7),cc5,0 - inc_gr_immed -4,sp - test_mem_limmed 0xffff,0xdddd,sp - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - csth gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,sp - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xeeee,gr8 - csth gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,sp - - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_gr_limmed 0xffff,0xdddd,gr8 - csth gr8,@(sp,gr7),cc5,1 - inc_gr_immed -4,sp - test_mem_limmed 0xdead,0xbeef,sp - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - csth gr8,@(sp,gr7),cc2,0 - test_mem_limmed 0xdead,0xbeef,sp - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xeeee,gr8 - csth gr8,@(sp,gr7),cc2,1 - test_mem_limmed 0xdead,0xbeef,sp - - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_gr_limmed 0xffff,0xdddd,gr8 - csth gr8,@(sp,gr7),cc6,0 - inc_gr_immed -4,sp - test_mem_limmed 0xdead,0xbeef,sp - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - csth gr8,@(sp,gr7),cc3,1 - test_mem_limmed 0xdead,0xbeef,sp - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xeeee,gr8 - csth gr8,@(sp,gr7),cc3,0 - test_mem_limmed 0xdead,0xbeef,sp - - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_gr_limmed 0xffff,0xdddd,gr8 - csth gr8,@(sp,gr7),cc7,1 - inc_gr_immed -4,sp - test_mem_limmed 0xdead,0xbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/csthf.cgs b/sim/testsuite/sim/frv/csthf.cgs deleted file mode 100644 index 21a64c8ae53..00000000000 --- a/sim/testsuite/sim/frv/csthf.cgs +++ /dev/null @@ -1,120 +0,0 @@ -# frv testcase for csthf $FRk,@($GRi,$GRj),$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global csthf -csthf: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr20 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0x1111,0xffff,fr8 - csthf fr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffff,0xbeef,gr20 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xaaaa,fr8 - csthf fr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffff,0xaaaa,gr20 - - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_fr_iimmed 0x2222,0xbbbb,fr8 - csthf fr8,@(sp,gr7),cc4,1 - test_mem_limmed 0xffff,0xbbbb,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0x1111,0xffff,fr8 - csthf fr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xaaaa,fr8 - csthf fr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_fr_iimmed 0x2222,0xbbbb,fr8 - csthf fr8,@(sp,gr7),cc4,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0x1111,0xffff,fr8 - csthf fr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffff,0xbeef,gr20 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xaaaa,fr8 - csthf fr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffff,0xaaaa,gr20 - - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_fr_iimmed 0x2222,0xbbbb,fr8 - csthf fr8,@(sp,gr7),cc5,0 - test_mem_limmed 0xffff,0xbbbb,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0x1111,0xffff,fr8 - csthf fr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xaaaa,fr8 - csthf fr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_fr_iimmed 0x2222,0xbbbb,fr8 - csthf fr8,@(sp,gr7),cc5,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0x1111,0xffff,fr8 - csthf fr8,@(sp,gr7),cc2,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xaaaa,fr8 - csthf fr8,@(sp,gr7),cc2,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_fr_iimmed 0x2222,0xbbbb,fr8 - csthf fr8,@(sp,gr7),cc6,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0x1111,0xffff,fr8 - csthf fr8,@(sp,gr7),cc3,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xaaaa,fr8 - csthf fr8,@(sp,gr7),cc3,0 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_fr_iimmed 0x2222,0xbbbb,fr8 - csthf fr8,@(sp,gr7),cc7,1 - test_mem_limmed 0xdead,0xbeef,gr20 - - pass diff --git a/sim/testsuite/sim/frv/csthfu.cgs b/sim/testsuite/sim/frv/csthfu.cgs deleted file mode 100644 index 252ae7da0a2..00000000000 --- a/sim/testsuite/sim/frv/csthfu.cgs +++ /dev/null @@ -1,150 +0,0 @@ -# frv testcase for csthfu $FRk,@($GRi,$GRj),$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global csthfu -csthfu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr20 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - set_gr_immed 0,gr7 - set_fr_iimmed 0x1111,0xffff,fr8 - csthfu fr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffff,0xbeef,gr20 - test_gr_gr sp,gr21 - - inc_gr_immed 2,gr21 - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xaaaa,fr8 - csthfu fr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffff,0xaaaa,gr20 - test_gr_gr sp,gr21 - - inc_gr_immed 2,sp - set_gr_immed -2,gr7 - set_fr_iimmed 0x2222,0xbbbb,fr8 - csthfu fr8,@(sp,gr7),cc4,1 - test_mem_limmed 0xffff,0xbbbb,gr20 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - set_gr_immed 0,gr7 - set_fr_iimmed 0x1111,0xffff,fr8 - csthfu fr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xaaaa,fr8 - csthfu fr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - inc_gr_immed 4,gr21 - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_fr_iimmed 0x2222,0xbbbb,fr8 - csthfu fr8,@(sp,gr7),cc4,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - set_gr_immed 0,gr7 - set_fr_iimmed 0x1111,0xffff,fr8 - csthfu fr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffff,0xbeef,gr20 - test_gr_gr sp,gr21 - - inc_gr_immed 2,gr21 - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xaaaa,fr8 - csthfu fr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffff,0xaaaa,gr20 - test_gr_gr sp,gr21 - - inc_gr_immed 2,sp - set_gr_immed -2,gr7 - set_fr_iimmed 0x2222,0xbbbb,fr8 - csthfu fr8,@(sp,gr7),cc5,0 - test_mem_limmed 0xffff,0xbbbb,gr20 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - set_gr_immed 0,gr7 - set_fr_iimmed 0x1111,0xffff,fr8 - csthfu fr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xaaaa,fr8 - csthfu fr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - inc_gr_immed 4,gr21 - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_fr_iimmed 0x2222,0xbbbb,fr8 - csthfu fr8,@(sp,gr7),cc5,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - set_gr_immed 0,gr7 - set_fr_iimmed 0x1111,0xffff,fr8 - csthfu fr8,@(sp,gr7),cc2,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xaaaa,fr8 - csthfu fr8,@(sp,gr7),cc2,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - inc_gr_immed 4,gr21 - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_fr_iimmed 0x2222,0xbbbb,fr8 - csthfu fr8,@(sp,gr7),cc6,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr21 - set_gr_immed 0,gr7 - set_fr_iimmed 0x1111,0xffff,fr8 - csthfu fr8,@(sp,gr7),cc3,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - set_gr_immed 2,gr7 - set_fr_iimmed 0xffff,0xaaaa,fr8 - csthfu fr8,@(sp,gr7),cc3,0 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - inc_gr_immed 4,gr21 - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_fr_iimmed 0x2222,0xbbbb,fr8 - csthfu fr8,@(sp,gr7),cc7,1 - test_mem_limmed 0xdead,0xbeef,gr20 - test_gr_gr sp,gr21 - - pass diff --git a/sim/testsuite/sim/frv/csthu.cgs b/sim/testsuite/sim/frv/csthu.cgs deleted file mode 100644 index c7e2255ccaa..00000000000 --- a/sim/testsuite/sim/frv/csthu.cgs +++ /dev/null @@ -1,150 +0,0 @@ -# frv testcase for csthu $GRk,@($GRi,$GRj),$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global csthu -csthu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr20 - set_gr_gr sp,gr21 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - csthu gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffff,0xbeef,gr21 - test_gr_gr sp,gr20 - - inc_gr_immed 2,gr20 - set_gr_immed 2,gr7 - set_gr_limmed 0xdead,0xeeee,gr8 - csthu gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffff,0xeeee,gr21 - test_gr_gr sp,gr20 - - inc_gr_immed 2,sp - set_gr_immed -2,gr7 - set_gr_limmed 0xffff,0xdddd,gr8 - csthu gr8,@(sp,gr7),cc4,1 - test_mem_limmed 0xffff,0xdddd,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr gr21,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - csthu gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xeeee,gr8 - csthu gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - inc_gr_immed 4,gr20 - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_gr_limmed 0xffff,0xdddd,gr8 - csthu gr8,@(sp,gr7),cc4,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr21,gr20 - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - csthu gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffff,0xbeef,gr21 - test_gr_gr sp,gr20 - - inc_gr_immed 2,gr20 - set_gr_immed 2,gr7 - set_gr_limmed 0xdead,0xeeee,gr8 - csthu gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffff,0xeeee,gr21 - test_gr_gr sp,gr20 - - inc_gr_immed 2,sp - set_gr_immed -2,gr7 - set_gr_limmed 0xffff,0xdddd,gr8 - csthu gr8,@(sp,gr7),cc5,0 - test_mem_limmed 0xffff,0xdddd,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr gr21,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - csthu gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xeeee,gr8 - csthu gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - inc_gr_immed 4,gr20 - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_gr_limmed 0xffff,0xdddd,gr8 - csthu gr8,@(sp,gr7),cc5,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr gr21,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - csthu gr8,@(sp,gr7),cc2,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xeeee,gr8 - csthu gr8,@(sp,gr7),cc2,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - inc_gr_immed 4,gr20 - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_gr_limmed 0xffff,0xdddd,gr8 - csthu gr8,@(sp,gr7),cc6,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_gr_gr gr21,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - csthu gr8,@(sp,gr7),cc3,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_immed 2,gr7 - set_gr_limmed 0xffff,0xeeee,gr8 - csthu gr8,@(sp,gr7),cc3,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - inc_gr_immed 4,gr20 - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - set_gr_limmed 0xffff,0xdddd,gr8 - csthu gr8,@(sp,gr7),cc7,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - pass diff --git a/sim/testsuite/sim/frv/cstq.cgs b/sim/testsuite/sim/frv/cstq.cgs deleted file mode 100644 index 6f183322cd7..00000000000 --- a/sim/testsuite/sim/frv/cstq.cgs +++ /dev/null @@ -1,355 +0,0 @@ -# frv testcase for cstq $GRk,@($GRi,$GRj),$CCi,$cond -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global cstq -cstq: - set_spr_immed 0x1b1b,cccr - - set_gr_gr sp,gr22 - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_gr sp,gr20 - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - set_gr_limmed 0xdead,0xdead,gr10 - set_gr_limmed 0xbeef,0xbeef,gr11 - cstq gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xbeef,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xbeef,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - set_gr_limmed 0xcccc,0xcccc,gr10 - set_gr_limmed 0xdddd,0xdddd,gr11 - cstq gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xaaaa,0xaaaa,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbbbb,0xbbbb,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xcccc,0xcccc,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdddd,0xdddd,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - set_gr_limmed 0x1111,0x1111,gr8 - set_gr_limmed 0x2222,0x2222,gr9 - set_gr_limmed 0x3333,0x3333,gr10 - set_gr_limmed 0x4444,0x4444,gr11 - cstq gr8,@(sp,gr7),cc4,1 - test_mem_limmed 0x1111,0x1111,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0x2222,0x2222,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0x3333,0x3333,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0x4444,0x4444,gr21 - - set_gr_gr gr22,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_gr sp,gr20 - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - set_gr_limmed 0xdead,0xdead,gr10 - set_gr_limmed 0xbeef,0xbeef,gr11 - cstq gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xbeef,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - set_gr_limmed 0xcccc,0xcccc,gr10 - set_gr_limmed 0xdddd,0xdddd,gr11 - cstq gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xbeef,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - set_gr_limmed 0x1111,0x1111,gr8 - set_gr_limmed 0x2222,0x2222,gr9 - set_gr_limmed 0x3333,0x3333,gr10 - set_gr_limmed 0x4444,0x4444,gr11 - cstq gr8,@(sp,gr7),cc4,0 - test_mem_limmed 0xbeef,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr22,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_gr sp,gr20 - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - set_gr_limmed 0xdead,0xdead,gr10 - set_gr_limmed 0xbeef,0xbeef,gr11 - cstq gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xbeef,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xbeef,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - set_gr_limmed 0xcccc,0xcccc,gr10 - set_gr_limmed 0xdddd,0xdddd,gr11 - cstq gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xaaaa,0xaaaa,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbbbb,0xbbbb,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xcccc,0xcccc,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdddd,0xdddd,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - set_gr_limmed 0x1111,0x1111,gr8 - set_gr_limmed 0x2222,0x2222,gr9 - set_gr_limmed 0x3333,0x3333,gr10 - set_gr_limmed 0x4444,0x4444,gr11 - cstq gr8,@(sp,gr7),cc5,0 - test_mem_limmed 0x1111,0x1111,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0x2222,0x2222,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0x3333,0x3333,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0x4444,0x4444,gr21 - - set_gr_gr gr22,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_gr sp,gr20 - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - set_gr_limmed 0xdead,0xdead,gr10 - set_gr_limmed 0xbeef,0xbeef,gr11 - cstq gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xbeef,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - set_gr_limmed 0xcccc,0xcccc,gr10 - set_gr_limmed 0xdddd,0xdddd,gr11 - cstq gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xbeef,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - set_gr_limmed 0x1111,0x1111,gr8 - set_gr_limmed 0x2222,0x2222,gr9 - set_gr_limmed 0x3333,0x3333,gr10 - set_gr_limmed 0x4444,0x4444,gr11 - cstq gr8,@(sp,gr7),cc5,1 - test_mem_limmed 0xbeef,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr22,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_gr sp,gr20 - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - set_gr_limmed 0xdead,0xdead,gr10 - set_gr_limmed 0xbeef,0xbeef,gr11 - cstq gr8,@(sp,gr7),cc2,0 - test_mem_limmed 0xbeef,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - set_gr_limmed 0xcccc,0xcccc,gr10 - set_gr_limmed 0xdddd,0xdddd,gr11 - cstq gr8,@(sp,gr7),cc2,1 - test_mem_limmed 0xbeef,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - set_gr_limmed 0x1111,0x1111,gr8 - set_gr_limmed 0x2222,0x2222,gr9 - set_gr_limmed 0x3333,0x3333,gr10 - set_gr_limmed 0x4444,0x4444,gr11 - cstq gr8,@(sp,gr7),cc6,0 - test_mem_limmed 0xbeef,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr22,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_gr sp,gr20 - set_gr_gr sp,gr21 - - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - set_gr_limmed 0xdead,0xdead,gr10 - set_gr_limmed 0xbeef,0xbeef,gr11 - cstq gr8,@(sp,gr7),cc3,1 - test_mem_limmed 0xbeef,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_gr_limmed 0xbbbb,0xbbbb,gr9 - set_gr_limmed 0xcccc,0xcccc,gr10 - set_gr_limmed 0xdddd,0xdddd,gr11 - cstq gr8,@(sp,gr7),cc3,0 - test_mem_limmed 0xbeef,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - set_gr_gr gr20,gr21 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - set_gr_limmed 0x1111,0x1111,gr8 - set_gr_limmed 0x2222,0x2222,gr9 - set_gr_limmed 0x3333,0x3333,gr10 - set_gr_limmed 0x4444,0x4444,gr11 - cstq gr8,@(sp,gr7),cc7,1 - test_mem_limmed 0xbeef,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xdead,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xdead,0xbeef,gr21 - inc_gr_immed 4,gr21 - test_mem_limmed 0xbeef,0xdead,gr21 - - pass diff --git a/sim/testsuite/sim/frv/cstu.cgs b/sim/testsuite/sim/frv/cstu.cgs deleted file mode 100644 index 81a5b82496c..00000000000 --- a/sim/testsuite/sim/frv/cstu.cgs +++ /dev/null @@ -1,152 +0,0 @@ -# frv testcase for cstu $GRk,@($GRi,$GRj),$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cstu -cstu: - set_spr_immed 0x1b1b,cccr - set_gr_gr sp,gr21 - - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstu gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xffff,0xffff,gr21 - test_gr_gr sp,gr21 - - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_gr_limmed 0xeeee,0xffff,gr8 - cstu gr8,@(sp,gr7),cc0,1 - test_mem_limmed 0xeeee,0xffff,gr21 - test_gr_gr sp,gr21 - - inc_gr_immed 4,sp - set_gr_immed -4,gr7 - set_gr_limmed 0xcccc,0xdddd,gr8 - cstu gr8,@(sp,gr7),cc4,1 - test_mem_limmed 0xcccc,0xdddd,gr21 - test_gr_gr sp,gr21 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstu gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr21 - - inc_gr_immed -4,sp - set_gr_gr sp,gr20 - set_gr_immed 4,gr7 - set_gr_limmed 0xeeee,0xffff,gr8 - cstu gr8,@(sp,gr7),cc0,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - inc_gr_immed 8,sp - set_gr_gr sp,gr20 - set_gr_immed -4,gr7 - set_gr_limmed 0xcccc,0xdddd,gr8 - cstu gr8,@(sp,gr7),cc4,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstu gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xffff,0xffff,gr21 - test_gr_gr sp,gr21 - - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_gr_limmed 0xeeee,0xffff,gr8 - cstu gr8,@(sp,gr7),cc1,0 - test_mem_limmed 0xeeee,0xffff,gr21 - test_gr_gr sp,gr21 - - inc_gr_immed 4,sp - set_gr_immed -4,gr7 - set_gr_limmed 0xcccc,0xdddd,gr8 - cstu gr8,@(sp,gr7),cc5,0 - test_mem_limmed 0xcccc,0xdddd,gr21 - test_gr_gr sp,gr21 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstu gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr21 - - inc_gr_immed -4,sp - set_gr_gr sp,gr20 - set_gr_immed 4,gr7 - set_gr_limmed 0xeeee,0xffff,gr8 - cstu gr8,@(sp,gr7),cc1,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - inc_gr_immed 8,sp - set_gr_gr sp,gr20 - set_gr_immed -4,gr7 - set_gr_limmed 0xcccc,0xdddd,gr8 - cstu gr8,@(sp,gr7),cc5,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstu gr8,@(sp,gr7),cc2,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr21 - - inc_gr_immed -4,sp - set_gr_gr sp,gr20 - set_gr_immed 4,gr7 - set_gr_limmed 0xeeee,0xffff,gr8 - cstu gr8,@(sp,gr7),cc2,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - inc_gr_immed 8,sp - set_gr_gr sp,gr20 - set_gr_immed -4,gr7 - set_gr_limmed 0xcccc,0xdddd,gr8 - cstu gr8,@(sp,gr7),cc6,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - set_gr_gr gr21,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - cstu gr8,@(sp,gr7),cc3,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr21 - - inc_gr_immed -4,sp - set_gr_gr sp,gr20 - set_gr_immed 4,gr7 - set_gr_limmed 0xeeee,0xffff,gr8 - cstu gr8,@(sp,gr7),cc3,0 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - inc_gr_immed 8,sp - set_gr_gr sp,gr20 - set_gr_immed -4,gr7 - set_gr_limmed 0xcccc,0xdddd,gr8 - cstu gr8,@(sp,gr7),cc7,1 - test_mem_limmed 0xdead,0xbeef,gr21 - test_gr_gr sp,gr20 - - pass diff --git a/sim/testsuite/sim/frv/csub.cgs b/sim/testsuite/sim/frv/csub.cgs deleted file mode 100644 index 7d07c147327..00000000000 --- a/sim/testsuite/sim/frv/csub.cgs +++ /dev/null @@ -1,108 +0,0 @@ -# frv testcase for csub $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global csub -csub: - set_spr_immed 0x1b1b,cccr - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - csub gr8,gr7,gr8,cc4,1 - test_gr_immed 1,gr8 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - csub gr8,gr7,gr8,cc4,1 - test_gr_limmed 0x7fff,0xffff,gr8 - - csub gr8,gr8,gr8,cc4,1 - test_gr_immed 0,gr8 - - csub gr8,gr7,gr8,cc4,1 - test_gr_immed -1,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - csub gr8,gr7,gr8,cc4,0 - test_gr_immed 2,gr8 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - csub gr8,gr7,gr8,cc4,0 - test_gr_limmed 0x8000,0x0000,gr8 - - csub gr8,gr8,gr8,cc4,0 - test_gr_limmed 0x8000,0x0000,gr8 - - csub gr8,gr7,gr8,cc4,0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - csub gr8,gr7,gr8,cc5,0 - test_gr_immed 1,gr8 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - csub gr8,gr7,gr8,cc5,0 - test_gr_limmed 0x7fff,0xffff,gr8 - - csub gr8,gr8,gr8,cc5,0 - test_gr_immed 0,gr8 - - csub gr8,gr7,gr8,cc5,0 - test_gr_immed -1,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - csub gr8,gr7,gr8,cc5,1 - test_gr_immed 2,gr8 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - csub gr8,gr7,gr8,cc5,1 - test_gr_limmed 0x8000,0x0000,gr8 - - csub gr8,gr8,gr8,cc5,1 - test_gr_limmed 0x8000,0x0000,gr8 - - csub gr8,gr7,gr8,cc5,1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - csub gr8,gr7,gr8,cc6,1 - test_gr_immed 2,gr8 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - csub gr8,gr7,gr8,cc6,0 - test_gr_limmed 0x8000,0x0000,gr8 - - csub gr8,gr8,gr8,cc6,1 - test_gr_limmed 0x8000,0x0000,gr8 - - csub gr8,gr7,gr8,cc6,0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - csub gr8,gr7,gr8,cc7,0 - test_gr_immed 2,gr8 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - csub gr8,gr7,gr8,cc7,1 - test_gr_limmed 0x8000,0x0000,gr8 - - csub gr8,gr8,gr8,cc7,0 - test_gr_limmed 0x8000,0x0000,gr8 - - csub gr8,gr7,gr8,cc7,1 - test_gr_limmed 0x8000,0x0000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/csubcc.cgs b/sim/testsuite/sim/frv/csubcc.cgs deleted file mode 100644 index 64cd93b16f5..00000000000 --- a/sim/testsuite/sim/frv/csubcc.cgs +++ /dev/null @@ -1,156 +0,0 @@ -# frv testcase for csubcc $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global csubcc -csubcc: - set_spr_immed 0x1b1b,cccr - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc0,1 - test_icc 0 0 0 0 icc0 - test_gr_immed 1,gr8 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc0,1 - test_icc 0 0 1 0 icc0 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_icc 0x0b,0 ; Set mask opposite of expected - csubcc gr8,gr8,gr8,cc4,1 - test_icc 0 1 0 0 icc0 - test_gr_immed 0,gr8 - - set_icc 0x06,0 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc4,1 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc0,0 - test_icc 1 1 1 1 icc0 - test_gr_immed 2,gr8 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc0,0 - test_icc 1 1 0 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_icc 0x0b,0 ; Set mask opposite of expected - csubcc gr8,gr8,gr8,cc4,0 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_icc 0x06,0 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc4,0 - test_icc 0 1 1 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc1,0 - test_icc 0 0 0 0 icc1 - test_gr_immed 1,gr8 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,1 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc1,0 - test_icc 0 0 1 0 icc1 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_icc 0x0b,1 ; Set mask opposite of expected - csubcc gr8,gr8,gr8,cc5,0 - test_icc 0 1 0 0 icc1 - test_gr_immed 0,gr8 - - set_icc 0x06,1 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc5,0 - test_icc 1 0 0 1 icc1 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,1 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc1,1 - test_icc 1 1 1 1 icc1 - test_gr_immed 2,gr8 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,1 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc1,1 - test_icc 1 1 0 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_icc 0x0b,1 ; Set mask opposite of expected - csubcc gr8,gr8,gr8,cc5,1 - test_icc 1 0 1 1 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_icc 0x06,1 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc5,1 - test_icc 0 1 1 0 icc1 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,2 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc2,0 - test_icc 1 1 1 1 icc2 - test_gr_immed 2,gr8 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,2 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc2,0 - test_icc 1 1 0 1 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - - set_icc 0x0b,2 ; Set mask opposite of expected - csubcc gr8,gr8,gr8,cc6,1 - test_icc 1 0 1 1 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - - set_icc 0x06,2 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc6,1 - test_icc 0 1 1 0 icc2 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,3 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc3,0 - test_icc 1 1 1 1 icc3 - test_gr_immed 2,gr8 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,3 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc3,0 - test_icc 1 1 0 1 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - - set_icc 0x0b,3 ; Set mask opposite of expected - csubcc gr8,gr8,gr8,cc7,1 - test_icc 1 0 1 1 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - - set_icc 0x06,3 ; Set mask opposite of expected - csubcc gr8,gr7,gr8,cc7,1 - test_icc 0 1 1 0 icc3 - test_gr_limmed 0x8000,0x0000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/cswap.cgs b/sim/testsuite/sim/frv/cswap.cgs deleted file mode 100644 index 19a51d5481d..00000000000 --- a/sim/testsuite/sim/frv/cswap.cgs +++ /dev/null @@ -1,212 +0,0 @@ -# frv testcase for cswap @($GRi,$GRj),$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cswap -cswap: - set_spr_immed 0x1b1b,cccr - - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_gr_gr sp,gr21 - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_gr_gr sp,gr22 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_immed -4,gr7 - cswap @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_mem_limmed 0xbeef,0xdead,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 0,gr7 - cswap @(sp,gr7),gr8,cc0,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_mem_limmed 0xbeef,0xdead,gr22 - test_mem_limmed 0xdead,0xbeef,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 4,gr7 - cswap @(sp,gr7),gr8,cc4,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_mem_limmed 0xbeef,0xdead,gr22 - test_mem_limmed 0xdead,0xbeef,gr21 - test_mem_limmed 0xbeef,0xdead,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_gr_gr sp,gr21 - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_gr_gr sp,gr22 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_immed -4,gr7 - cswap @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_mem_limmed 0xdead,0xbeef,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_immed 0,gr7 - cswap @(sp,gr7),gr8,cc0,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_mem_limmed 0xdead,0xbeef,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_immed 4,gr7 - cswap @(sp,gr7),gr8,cc4,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_mem_limmed 0xdead,0xbeef,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_gr_gr sp,gr21 - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_gr_gr sp,gr22 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_immed -4,gr7 - cswap @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_mem_limmed 0xbeef,0xdead,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 0,gr7 - cswap @(sp,gr7),gr8,cc1,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_mem_limmed 0xbeef,0xdead,gr22 - test_mem_limmed 0xdead,0xbeef,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 4,gr7 - cswap @(sp,gr7),gr8,cc5,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_mem_limmed 0xbeef,0xdead,gr22 - test_mem_limmed 0xdead,0xbeef,gr21 - test_mem_limmed 0xbeef,0xdead,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_gr_gr sp,gr21 - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_gr_gr sp,gr22 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_immed -4,gr7 - cswap @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_mem_limmed 0xdead,0xbeef,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_immed 0,gr7 - cswap @(sp,gr7),gr8,cc1,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_mem_limmed 0xdead,0xbeef,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_immed 4,gr7 - cswap @(sp,gr7),gr8,cc5,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_mem_limmed 0xdead,0xbeef,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_gr_gr sp,gr21 - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_gr_gr sp,gr22 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_immed -4,gr7 - cswap @(sp,gr7),gr8,cc2,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_mem_limmed 0xdead,0xbeef,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_immed 0,gr7 - cswap @(sp,gr7),gr8,cc2,1 - test_gr_limmed 0xdead,0xbeef,gr8 - test_mem_limmed 0xdead,0xbeef,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_immed 4,gr7 - cswap @(sp,gr7),gr8,cc6,0 - test_gr_limmed 0xbeef,0xdead,gr8 - test_mem_limmed 0xdead,0xbeef,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_gr gr20,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_gr_gr sp,gr21 - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_gr_gr sp,gr22 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_immed -4,gr7 - cswap @(sp,gr7),gr8,cc3,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_mem_limmed 0xdead,0xbeef,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_immed 0,gr7 - cswap @(sp,gr7),gr8,cc3,0 - test_gr_limmed 0xdead,0xbeef,gr8 - test_mem_limmed 0xdead,0xbeef,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_immed 4,gr7 - cswap @(sp,gr7),gr8,cc7,1 - test_gr_limmed 0xbeef,0xdead,gr8 - test_mem_limmed 0xdead,0xbeef,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - pass diff --git a/sim/testsuite/sim/frv/cudiv.cgs b/sim/testsuite/sim/frv/cudiv.cgs deleted file mode 100644 index 78f44ae8407..00000000000 --- a/sim/testsuite/sim/frv/cudiv.cgs +++ /dev/null @@ -1,96 +0,0 @@ -# frv testcase for cudiv $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cudiv -cudiv: - set_spr_immed 0x1b1b,cccr - - ; simple division 12 / 3 - set_gr_immed 0x00000003,gr2 - set_gr_immed 0x0000000c,gr3 - cudiv gr3,gr2,gr3,cc0,1 - test_gr_immed 0x00000003,gr2 - test_gr_immed 0x00000004,gr3 - - ; example 1 from division in the fr30 manual - set_gr_limmed 0x0123,0x4567,gr2 - set_gr_limmed 0xfedc,0xba98,gr3 - cudiv gr3,gr2,gr3,cc4,1 - test_gr_limmed 0x0123,0x4567,gr2 - test_gr_immed 0x000000e0,gr3 - - ; simple division 12 / 3 - set_gr_immed 0x00000003,gr2 - set_gr_immed 0x0000000c,gr3 - cudiv gr3,gr2,gr3,cc0,0 - test_gr_immed 0x00000003,gr2 - test_gr_immed 0x0000000c,gr3 - - ; example 1 from division in the fr30 manual - set_gr_limmed 0x0123,0x4567,gr2 - set_gr_limmed 0xfedc,0xba98,gr3 - cudiv gr3,gr2,gr3,cc4,0 - test_gr_limmed 0x0123,0x4567,gr2 - test_gr_limmed 0xfedc,0xba98,gr3 - - ; simple division 12 / 3 - set_gr_immed 0x00000003,gr2 - set_gr_immed 0x0000000c,gr3 - cudiv gr3,gr2,gr3,cc1,0 - test_gr_immed 0x00000003,gr2 - test_gr_immed 0x00000004,gr3 - - ; example 1 from division in the fr30 manual - set_gr_limmed 0x0123,0x4567,gr2 - set_gr_limmed 0xfedc,0xba98,gr3 - cudiv gr3,gr2,gr3,cc5,0 - test_gr_limmed 0x0123,0x4567,gr2 - test_gr_immed 0x000000e0,gr3 - - ; simple division 12 / 3 - set_gr_immed 0x00000003,gr2 - set_gr_immed 0x0000000c,gr3 - cudiv gr3,gr2,gr3,cc1,1 - test_gr_immed 0x00000003,gr2 - test_gr_immed 0x0000000c,gr3 - - ; example 1 from division in the fr30 manual - set_gr_limmed 0x0123,0x4567,gr2 - set_gr_limmed 0xfedc,0xba98,gr3 - cudiv gr3,gr2,gr3,cc5,1 - test_gr_limmed 0x0123,0x4567,gr2 - test_gr_limmed 0xfedc,0xba98,gr3 - - ; simple division 12 / 3 - set_gr_immed 0x00000003,gr2 - set_gr_immed 0x0000000c,gr3 - cudiv gr3,gr2,gr3,cc2,0 - test_gr_immed 0x00000003,gr2 - test_gr_immed 0x0000000c,gr3 - - ; example 1 from division in the fr30 manual - set_gr_limmed 0x0123,0x4567,gr2 - set_gr_limmed 0xfedc,0xba98,gr3 - cudiv gr3,gr2,gr3,cc6,1 - test_gr_limmed 0x0123,0x4567,gr2 - test_gr_limmed 0xfedc,0xba98,gr3 - - ; simple division 12 / 3 - set_gr_immed 0x00000003,gr2 - set_gr_immed 0x0000000c,gr3 - cudiv gr3,gr2,gr3,cc3,0 - test_gr_immed 0x00000003,gr2 - test_gr_immed 0x0000000c,gr3 - - ; example 1 from division in the fr30 manual - set_gr_limmed 0x0123,0x4567,gr2 - set_gr_limmed 0xfedc,0xba98,gr3 - cudiv gr3,gr2,gr3,cc7,1 - test_gr_limmed 0x0123,0x4567,gr2 - test_gr_limmed 0xfedc,0xba98,gr3 - - pass diff --git a/sim/testsuite/sim/frv/cxor.cgs b/sim/testsuite/sim/frv/cxor.cgs deleted file mode 100644 index 54a672dfe70..00000000000 --- a/sim/testsuite/sim/frv/cxor.cgs +++ /dev/null @@ -1,180 +0,0 @@ -# frv testcase for cxor $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cxor -cxor: - set_spr_immed 0x1b1b,cccr - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc0,1 - test_icc 0 1 1 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 0x00000000,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc0,1 - test_icc 1 0 0 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc4,1 - test_icc 1 0 1 1 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc4,1 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc0,0 - test_icc 0 1 1 1 icc0 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc0,0 - test_icc 1 0 0 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc4,0 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0xaaaa,0xaaaa,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc4,0 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x0000,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,1 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc1,0 - test_icc 0 1 1 1 icc1 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 0x00000000,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,1 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc1,0 - test_icc 1 0 0 0 icc1 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_icc 0x0b,1 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc5,0 - test_icc 1 0 1 1 icc1 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc5,0 - test_icc 0 1 0 1 icc1 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,1 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc1,1 - test_icc 0 1 1 1 icc1 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,1 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc1,1 - test_icc 1 0 0 0 icc1 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_icc 0x0b,1 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc5,1 - test_icc 1 0 1 1 icc1 - test_gr_limmed 0xaaaa,0xaaaa,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc5,1 - test_icc 0 1 0 1 icc1 - test_gr_limmed 0x0000,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,2 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc2,0 - test_icc 0 1 1 1 icc2 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,2 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc2,0 - test_icc 1 0 0 0 icc2 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_icc 0x0b,2 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc6,1 - test_icc 1 0 1 1 icc2 - test_gr_limmed 0xaaaa,0xaaaa,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,2 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc6,1 - test_icc 0 1 0 1 icc2 - test_gr_limmed 0x0000,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,3 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc3,0 - test_icc 0 1 1 1 icc3 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,3 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc3,0 - test_icc 1 0 0 0 icc3 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_icc 0x0b,3 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc7,1 - test_icc 1 0 1 1 icc3 - test_gr_limmed 0xaaaa,0xaaaa,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,3 ; Set mask opposite of expected - cxor gr7,gr8,gr8,cc7,1 - test_icc 0 1 0 1 icc3 - test_gr_limmed 0x0000,0xbeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/cxorcc.cgs b/sim/testsuite/sim/frv/cxorcc.cgs deleted file mode 100644 index 86d917d288c..00000000000 --- a/sim/testsuite/sim/frv/cxorcc.cgs +++ /dev/null @@ -1,180 +0,0 @@ -# frv testcase for cxorcc $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "testutils.inc" - - start - - .global cxorcc -cxorcc: - set_spr_immed 0x1b1b,cccr - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc0,1 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 0x00000000,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc0,1 - test_icc 0 1 0 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc4,1 - test_icc 0 1 1 1 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc4,1 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc0,0 - test_icc 0 1 1 1 icc0 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc0,0 - test_icc 1 0 0 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc4,0 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0xaaaa,0xaaaa,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc4,0 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x0000,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,1 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc1,0 - test_icc 1 0 1 1 icc1 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 0x00000000,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,1 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc1,0 - test_icc 0 1 0 0 icc1 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_icc 0x0b,1 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc5,0 - test_icc 0 1 1 1 icc1 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc5,0 - test_icc 1 0 0 1 icc1 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,1 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc1,1 - test_icc 0 1 1 1 icc1 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,1 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc1,1 - test_icc 1 0 0 0 icc1 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_icc 0x0b,1 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc5,1 - test_icc 1 0 1 1 icc1 - test_gr_limmed 0xaaaa,0xaaaa,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,1 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc5,1 - test_icc 0 1 0 1 icc1 - test_gr_limmed 0x0000,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,2 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc2,0 - test_icc 0 1 1 1 icc2 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,2 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc2,0 - test_icc 1 0 0 0 icc2 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_icc 0x0b,2 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc6,1 - test_icc 1 0 1 1 icc2 - test_gr_limmed 0xaaaa,0xaaaa,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,2 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc6,1 - test_icc 0 1 0 1 icc2 - test_gr_limmed 0x0000,0xbeef,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,3 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc3,0 - test_icc 0 1 1 1 icc3 - test_gr_limmed 0x5555,0x5555,gr8 - - set_gr_immed 0x00007fff,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,3 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc3,0 - test_icc 1 0 0 0 icc3 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_icc 0x0b,3 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc7,1 - test_icc 1 0 1 1 icc3 - test_gr_limmed 0xaaaa,0xaaaa,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,3 ; Set mask opposite of expected - cxorcc gr7,gr8,gr8,cc7,1 - test_icc 0 1 0 1 icc3 - test_gr_limmed 0x0000,0xbeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/dcef.cgs b/sim/testsuite/sim/frv/dcef.cgs deleted file mode 100644 index 74475ef0b22..00000000000 --- a/sim/testsuite/sim/frv/dcef.cgs +++ /dev/null @@ -1,50 +0,0 @@ -# frv testcase for dcef @(GRi,GRj),a -# mach: fr400 fr550 - - .include "testutils.inc" - - start - - .global dcef -dcef: - and_spr_immed 0x7fffffff,hsr0 ; data cache only: copy-back mode - set_gr_addr doit,gr10 - set_gr_immed 0,gr11 - set_gr_immed 1,gr12 - set_gr_immed 2,gr13 - set_gr_immed 3,gr14 - - set_spr_addr ok1,lr - bra doit -ok1: test_gr_immed 1,gr11 - - set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11 in cache - set_spr_addr ok2,lr - bra doit -ok2: test_gr_immed 2,gr11 ; still only added 1 - - set_gr_addr doit1,gr10 - set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11 in cache - dcef @(gr10,gr0),1 ; flush data cache - set_spr_addr ok3,lr - bra doit1 -ok3: test_gr_immed 4,gr11 ; added 2 this time - - set_gr_addr doit2,gr10 - set_mem_immed 0x9600b00e,gr10 ; change to add gr11,gr14,gr11 in cache - dcef @(gr0,gr0),1 ; flush data cache - set_spr_addr ok4,lr - bra doit2 -ok4: test_gr_immed 7,gr11 ; added 3 this time - - pass - -doit: add gr11,gr12,gr11 - bralr - -doit1: add gr11,gr12,gr11 - bralr - -doit2: add gr11,gr12,gr11 - bralr - diff --git a/sim/testsuite/sim/frv/dcei.cgs b/sim/testsuite/sim/frv/dcei.cgs deleted file mode 100644 index 6254c06b183..00000000000 --- a/sim/testsuite/sim/frv/dcei.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# frv testcase for dcei @(GRi,GRj),a -# mach: fr400 fr550 - - .include "testutils.inc" - - start - - .global dcei -dcei: - or_spr_immed 0x08000000,hsr0 ; data cache: copy-back mode - - set_mem_immed 0xdeadbeef,sp - test_mem_immed 0xdeadbeef,sp - - flush_data_cache sp - set_mem_immed 0xbeefdead,sp - test_mem_immed 0xbeefdead,sp - - dcei @(sp,gr0),1 - test_mem_immed 0xdeadbeef,sp - - set_mem_immed 0xbeefdead,sp - test_mem_immed 0xbeefdead,sp - dcei @(gr0,gr0),1 - test_mem_immed 0xdeadbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/dcf.cgs b/sim/testsuite/sim/frv/dcf.cgs deleted file mode 100644 index f6e670e7b43..00000000000 --- a/sim/testsuite/sim/frv/dcf.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# FRV testcase for dcf @(GRi,GRj) -# mach: all - - .include "testutils.inc" - - start - - .global dcf -dcf: - and_spr_immed 0x7fffffff,hsr0 ; data cache only: copy-back mode - set_gr_addr doit,gr10 - set_gr_immed 0,gr11 - set_gr_immed 1,gr12 - set_gr_immed 2,gr13 - - set_spr_addr ok1,lr - bra doit -ok1: test_gr_immed 1,gr11 - - set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11 in cache - set_spr_addr ok2,lr - bra doit -ok2: test_gr_immed 2,gr11 ; still only added 1 - - set_gr_addr doit1,gr10 - set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11 in cache - dcf @(gr10,gr0) ; flush data cache - set_spr_addr ok3,lr - bra doit1 -ok3: test_gr_immed 4,gr11 ; added 2 this time - - pass - -doit: add gr11,gr12,gr11 - bralr - -doit1: add gr11,gr12,gr11 - bralr - diff --git a/sim/testsuite/sim/frv/dci.cgs b/sim/testsuite/sim/frv/dci.cgs deleted file mode 100644 index de481c363c4..00000000000 --- a/sim/testsuite/sim/frv/dci.cgs +++ /dev/null @@ -1,22 +0,0 @@ -# FRV testcase for dci @(GRi,GRj) -# mach: all - - .include "testutils.inc" - - start - - .global dci -dci: - or_spr_immed 0x08000000,hsr0 ; data cache: copy-back mode - - set_mem_immed 0xdeadbeef,sp - test_mem_immed 0xdeadbeef,sp - - flush_data_cache sp - set_mem_immed 0xbeefdead,sp - test_mem_immed 0xbeefdead,sp - - dci @(sp,gr0) - test_mem_immed 0xdeadbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/fabsd.cgs b/sim/testsuite/sim/frv/fabsd.cgs deleted file mode 100644 index 41a485e19eb..00000000000 --- a/sim/testsuite/sim/frv/fabsd.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for fabsd $FRj,$FRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - double_constants - start - load_double_constants - - .global fabsd -fabsd: - fabsd fr0,fr2 - test_dfr_dfr fr2,fr52 - fabsd fr8,fr2 - test_dfr_dfr fr2,fr28 - fabsd fr12,fr2 - test_dfr_dfr fr2,fr24 - fabsd fr24,fr2 - test_dfr_dfr fr2,fr24 - fabsd fr28,fr2 - test_dfr_dfr fr2,fr28 - fabsd fr52,fr2 - test_dfr_dfr fr2,fr52 - - pass diff --git a/sim/testsuite/sim/frv/fabss.cgs b/sim/testsuite/sim/frv/fabss.cgs deleted file mode 100644 index f48514a13e1..00000000000 --- a/sim/testsuite/sim/frv/fabss.cgs +++ /dev/null @@ -1,25 +0,0 @@ -# frv testcase for fabss $FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fabss -fabss: - fabss fr0,fr1 - test_fr_fr fr1,fr52 - fabss fr8,fr1 - test_fr_fr fr1,fr28 - fabss fr12,fr1 - test_fr_fr fr1,fr24 - fabss fr24,fr1 - test_fr_fr fr1,fr24 - fabss fr28,fr1 - test_fr_fr fr1,fr28 - fabss fr52,fr1 - test_fr_fr fr1,fr52 - - pass diff --git a/sim/testsuite/sim/frv/faddd.cgs b/sim/testsuite/sim/frv/faddd.cgs deleted file mode 100644 index dbb6373bb4d..00000000000 --- a/sim/testsuite/sim/frv/faddd.cgs +++ /dev/null @@ -1,93 +0,0 @@ -# frv testcase for faddd $GRi,$GRj,$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - double_constants - start - load_double_constants - - .global faddd -faddd: - faddd fr16,fr0,fr2 - test_dfr_dfr fr2,fr0 - faddd fr16,fr4,fr2 - test_dfr_dfr fr2,fr4 - faddd fr16,fr8,fr2 - test_dfr_dfr fr2,fr8 - faddd fr16,fr12,fr2 - test_dfr_dfr fr2,fr12 - faddd fr16,fr16,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - faddd fr16,fr20,fr2 - test_dfr_dfr fr2,fr26 - test_dfr_dfr fr2,fr20 - faddd fr16,fr24,fr2 - test_dfr_dfr fr2,fr24 - faddd fr16,fr28,fr2 - test_dfr_dfr fr2,fr28 - faddd fr16,fr32,fr2 - test_dfr_dfr fr2,fr32 - faddd fr16,fr36,fr2 - test_dfr_dfr fr2,fr36 - faddd fr16,fr40,fr2 - test_dfr_dfr fr2,fr40 - faddd fr16,fr44,fr2 - test_dfr_dfr fr2,fr44 - faddd fr16,fr48,fr2 - test_dfr_dfr fr2,fr48 - faddd fr16,fr52,fr2 - test_dfr_dfr fr2,fr52 - - faddd fr20,fr0,fr2 - test_dfr_dfr fr2,fr0 - faddd fr20,fr4,fr2 - test_dfr_dfr fr2,fr4 - faddd fr20,fr8,fr2 - test_dfr_dfr fr2,fr8 - faddd fr20,fr12,fr2 - test_dfr_dfr fr2,fr12 - faddd fr20,fr16,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - faddd fr20,fr20,fr2 - test_dfr_dfr fr2,fr26 - test_dfr_dfr fr2,fr20 - faddd fr20,fr24,fr2 - test_dfr_dfr fr2,fr24 - faddd fr20,fr28,fr2 - test_dfr_dfr fr2,fr28 - faddd fr20,fr32,fr2 - test_dfr_dfr fr2,fr32 - faddd fr20,fr36,fr2 - test_dfr_dfr fr2,fr36 - faddd fr20,fr40,fr2 - test_dfr_dfr fr2,fr40 - faddd fr20,fr44,fr2 - test_dfr_dfr fr2,fr44 - faddd fr20,fr48,fr2 - test_dfr_dfr fr2,fr48 - faddd fr20,fr52,fr2 - test_dfr_dfr fr2,fr52 - - faddd fr8,fr28,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - faddd fr12,fr24,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - faddd fr24,fr12,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - faddd fr28,fr8,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - - faddd fr36,fr40,fr2 - test_dfr_dfr fr2,fr44 - - pass - - diff --git a/sim/testsuite/sim/frv/fadds.cgs b/sim/testsuite/sim/frv/fadds.cgs deleted file mode 100644 index d741ac92239..00000000000 --- a/sim/testsuite/sim/frv/fadds.cgs +++ /dev/null @@ -1,92 +0,0 @@ -# frv testcase for fadds $GRi,$GRj,$GRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fadds -fadds: - fadds fr16,fr0,fr1 - test_fr_fr fr1,fr0 - fadds fr16,fr4,fr1 - test_fr_fr fr1,fr4 - fadds fr16,fr8,fr1 - test_fr_fr fr1,fr8 - fadds fr16,fr12,fr1 - test_fr_fr fr1,fr12 - fadds fr16,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fadds fr16,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fadds fr16,fr24,fr1 - test_fr_fr fr1,fr24 - fadds fr16,fr28,fr1 - test_fr_fr fr1,fr28 - fadds fr16,fr32,fr1 - test_fr_fr fr1,fr32 - fadds fr16,fr36,fr1 - test_fr_fr fr1,fr36 - fadds fr16,fr40,fr1 - test_fr_fr fr1,fr40 - fadds fr16,fr44,fr1 - test_fr_fr fr1,fr44 - fadds fr16,fr48,fr1 - test_fr_fr fr1,fr48 - fadds fr16,fr52,fr1 - test_fr_fr fr1,fr52 - - fadds fr20,fr0,fr1 - test_fr_fr fr1,fr0 - fadds fr20,fr4,fr1 - test_fr_fr fr1,fr4 - fadds fr20,fr8,fr1 - test_fr_fr fr1,fr8 - fadds fr20,fr12,fr1 - test_fr_fr fr1,fr12 - fadds fr20,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fadds fr20,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fadds fr20,fr24,fr1 - test_fr_fr fr1,fr24 - fadds fr20,fr28,fr1 - test_fr_fr fr1,fr28 - fadds fr20,fr32,fr1 - test_fr_fr fr1,fr32 - fadds fr20,fr36,fr1 - test_fr_fr fr1,fr36 - fadds fr20,fr40,fr1 - test_fr_fr fr1,fr40 - fadds fr20,fr44,fr1 - test_fr_fr fr1,fr44 - fadds fr20,fr48,fr1 - test_fr_fr fr1,fr48 - fadds fr20,fr52,fr1 - test_fr_fr fr1,fr52 - - fadds fr8,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fadds fr12,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fadds fr24,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fadds fr28,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - fadds fr36,fr40,fr1 - test_fr_fr fr1,fr44 - - pass - - diff --git a/sim/testsuite/sim/frv/fbeq.cgs b/sim/testsuite/sim/frv/fbeq.cgs deleted file mode 100644 index e51b2c96dcc..00000000000 --- a/sim/testsuite/sim/frv/fbeq.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for fbeq $FCCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global fbeq -fbeq: - set_fcc 0x0 0 - fbeq fcc0,0,bad - set_fcc 0x1 1 - fbeq fcc1,1,bad - set_fcc 0x2 2 - fbeq fcc2,2,bad - set_fcc 0x3 3 - fbeq fcc3,3,bad - set_fcc 0x4 0 - fbeq fcc0,0,bad - set_fcc 0x5 1 - fbeq fcc1,1,bad - set_fcc 0x6 2 - fbeq fcc2,2,bad - set_fcc 0x7 3 - fbeq fcc3,3,bad - set_fcc 0x8 0 - fbeq fcc0,0,ok9 - fail -ok9: - set_fcc 0x9 1 - fbeq fcc1,1,oka - fail -oka: - set_fcc 0xa 2 - fbeq fcc2,2,okb - fail -okb: - set_fcc 0xb 3 - fbeq fcc3,3,okc - fail -okc: - set_fcc 0xc 0 - fbeq fcc0,0,okd - fail -okd: - set_fcc 0xd 1 - fbeq fcc1,1,oke - fail -oke: - set_fcc 0xe 2 - fbeq fcc2,2,okf - fail -okf: - set_fcc 0xf 3 - fbeq fcc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbeqlr.cgs b/sim/testsuite/sim/frv/fbeqlr.cgs deleted file mode 100644 index af29cb909c4..00000000000 --- a/sim/testsuite/sim/frv/fbeqlr.cgs +++ /dev/null @@ -1,84 +0,0 @@ -# frv testcase for fbeqlr $FCCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fbeqlr -fbeqlr: - set_spr_addr bad,lr - set_fcc 0x0 0 - fbeqlr fcc0,0 - - set_spr_addr bad,lr - set_fcc 0x1 1 - fbeqlr fcc1,1 - - set_spr_addr bad,lr - set_fcc 0x2 2 - fbeqlr fcc2,2 - - set_spr_addr bad,lr - set_fcc 0x3 3 - fbeqlr fcc3,3 - - set_spr_addr bad,lr - set_fcc 0x4 0 - fbeqlr fcc0,0 - - set_spr_addr bad,lr - set_fcc 0x5 1 - fbeqlr fcc1,1 - - set_spr_addr bad,lr - set_fcc 0x6 2 - fbeqlr fcc2,2 - - set_spr_addr bad,lr - set_fcc 0x7 3 - fbeqlr fcc3,3 - - set_spr_addr ok9,lr - set_fcc 0x8 0 - fbeqlr fcc0,0 - fail -ok9: - set_spr_addr oka,lr - set_fcc 0x9 1 - fbeqlr fcc1,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fbeqlr fcc2,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fbeqlr fcc3,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fbeqlr fcc0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fbeqlr fcc1,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fbeqlr fcc2,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fbeqlr fcc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbge.cgs b/sim/testsuite/sim/frv/fbge.cgs deleted file mode 100644 index a20029e6613..00000000000 --- a/sim/testsuite/sim/frv/fbge.cgs +++ /dev/null @@ -1,69 +0,0 @@ -# frv testcase for fbge $FCCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global fbge -fbge: - set_fcc 0x0 0 - fbge fcc0,0,bad - set_fcc 0x1 1 - fbge fcc1,1,bad - set_fcc 0x2 2 - fbge fcc2,2,ok3 - fail -ok3: - set_fcc 0x3 3 - fbge fcc3,3,ok4 - fail -ok4: - set_fcc 0x4 0 - fbge fcc0,0,bad - set_fcc 0x5 1 - fbge fcc1,1,bad - set_fcc 0x6 2 - fbge fcc2,2,ok7 - fail -ok7: - set_fcc 0x7 3 - fbge fcc3,3,ok8 - fail -ok8: - set_fcc 0x8 0 - fbge fcc0,0,ok9 - fail -ok9: - set_fcc 0x9 1 - fbge fcc1,1,oka - fail -oka: - set_fcc 0xa 2 - fbge fcc2,2,okb - fail -okb: - set_fcc 0xb 3 - fbge fcc3,3,okc - fail -okc: - set_fcc 0xc 0 - fbge fcc0,0,okd - fail -okd: - set_fcc 0xd 1 - fbge fcc1,1,oke - fail -oke: - set_fcc 0xe 2 - fbge fcc2,2,okf - fail -okf: - set_fcc 0xf 3 - fbge fcc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbgelr.cgs b/sim/testsuite/sim/frv/fbgelr.cgs deleted file mode 100644 index 59e941084ba..00000000000 --- a/sim/testsuite/sim/frv/fbgelr.cgs +++ /dev/null @@ -1,88 +0,0 @@ -# frv testcase for fbgelr $FCCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fbgelr -fbgelr: - set_spr_addr bad,lr - set_fcc 0x0 0 - fbgelr fcc0,0 - - set_spr_addr bad,lr - set_fcc 0x1 1 - fbgelr fcc1,1 - - set_spr_addr ok3,lr - set_fcc 0x2 2 - fbgelr fcc2,2 - fail -ok3: - set_spr_addr ok4,lr - set_fcc 0x3 3 - fbgelr fcc3,3 - fail -ok4: - set_spr_addr bad,lr - set_fcc 0x4 0 - fbgelr fcc0,0 - - set_spr_addr bad,lr - set_fcc 0x5 1 - fbgelr fcc1,1 - - set_spr_addr ok7,lr - set_fcc 0x6 2 - fbgelr fcc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fbgelr fcc3,3 - fail -ok8: - set_spr_addr ok9,lr - set_fcc 0x8 0 - fbgelr fcc0,0 - fail -ok9: - set_spr_addr oka,lr - set_fcc 0x9 1 - fbgelr fcc1,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fbgelr fcc2,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fbgelr fcc3,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fbgelr fcc0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fbgelr fcc1,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fbgelr fcc2,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fbgelr fcc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbgt.cgs b/sim/testsuite/sim/frv/fbgt.cgs deleted file mode 100644 index 7cc4ea7ab4b..00000000000 --- a/sim/testsuite/sim/frv/fbgt.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for fbgt $FCCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global fbgt -fbgt: - set_fcc 0x0 0 - fbgt fcc0,0,bad - set_fcc 0x1 1 - fbgt fcc1,1,bad - set_fcc 0x2 2 - fbgt fcc2,2,ok3 - fail -ok3: - set_fcc 0x3 3 - fbgt fcc3,3,ok4 - fail -ok4: - set_fcc 0x4 0 - fbgt fcc0,0,bad - set_fcc 0x5 1 - fbgt fcc1,1,bad - set_fcc 0x6 2 - fbgt fcc2,2,ok7 - fail -ok7: - set_fcc 0x7 3 - fbgt fcc3,3,ok8 - fail -ok8: - set_fcc 0x8 0 - fbgt fcc0,0,bad - set_fcc 0x9 1 - fbgt fcc1,1,bad - set_fcc 0xa 2 - fbgt fcc2,2,okb - fail -okb: - set_fcc 0xb 3 - fbgt fcc3,3,okc - fail -okc: - set_fcc 0xc 0 - fbgt fcc0,0,bad - set_fcc 0xd 1 - fbgt fcc1,1,bad - set_fcc 0xe 2 - fbgt fcc2,2,okf - fail -okf: - set_fcc 0xf 3 - fbgt fcc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbgtlr.cgs b/sim/testsuite/sim/frv/fbgtlr.cgs deleted file mode 100644 index 7e4a7a51275..00000000000 --- a/sim/testsuite/sim/frv/fbgtlr.cgs +++ /dev/null @@ -1,84 +0,0 @@ -# frv testcase for fbgtlr $FCCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fbgtlr -fbgtlr: - set_spr_addr bad,lr - set_fcc 0x0 0 - fbgtlr fcc0,0 - - set_spr_addr bad,lr - set_fcc 0x1 1 - fbgtlr fcc1,1 - - set_spr_addr ok3,lr - set_fcc 0x2 2 - fbgtlr fcc2,2 - fail -ok3: - set_spr_addr ok4,lr - set_fcc 0x3 3 - fbgtlr fcc3,3 - fail -ok4: - set_spr_addr bad,lr - set_fcc 0x4 0 - fbgtlr fcc0,0 - - set_spr_addr bad,lr - set_fcc 0x5 1 - fbgtlr fcc1,1 - - set_spr_addr ok7,lr - set_fcc 0x6 2 - fbgtlr fcc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fbgtlr fcc3,3 - fail -ok8: - set_spr_addr bad,lr - set_fcc 0x8 0 - fbgtlr fcc0,0 - - set_spr_addr bad,lr - set_fcc 0x9 1 - fbgtlr fcc1,1 - - set_spr_addr okb,lr - set_fcc 0xa 2 - fbgtlr fcc2,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fbgtlr fcc3,3 - fail -okc: - set_spr_addr bad,lr - set_fcc 0xc 0 - fbgtlr fcc0,0 - - set_spr_addr bad,lr - set_fcc 0xd 1 - fbgtlr fcc1,1 - - set_spr_addr okf,lr - set_fcc 0xe 2 - fbgtlr fcc2,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fbgtlr fcc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fble.cgs b/sim/testsuite/sim/frv/fble.cgs deleted file mode 100644 index e52936a776b..00000000000 --- a/sim/testsuite/sim/frv/fble.cgs +++ /dev/null @@ -1,69 +0,0 @@ -# frv testcase for fble $FCCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global fble -fble: - set_fcc 0x0 0 - fble fcc0,0,bad - set_fcc 0x1 1 - fble fcc1,1,bad - set_fcc 0x2 2 - fble fcc2,2,bad - set_fcc 0x3 3 - fble fcc3,3,bad - set_fcc 0x4 0 - fble fcc0,0,ok5 - fail -ok5: - set_fcc 0x5 1 - fble fcc1,1,ok6 - fail -ok6: - set_fcc 0x6 2 - fble fcc2,2,ok7 - fail -ok7: - set_fcc 0x7 3 - fble fcc3,3,ok8 - fail -ok8: - set_fcc 0x8 0 - fble fcc0,0,ok9 - fail -ok9: - set_fcc 0x9 1 - fble fcc1,1,oka - fail -oka: - set_fcc 0xa 2 - fble fcc2,2,okb - fail -okb: - set_fcc 0xb 3 - fble fcc3,3,okc - fail -okc: - set_fcc 0xc 0 - fble fcc0,0,okd - fail -okd: - set_fcc 0xd 1 - fble fcc1,1,oke - fail -oke: - set_fcc 0xe 2 - fble fcc2,2,okf - fail -okf: - set_fcc 0xf 3 - fble fcc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fblelr.cgs b/sim/testsuite/sim/frv/fblelr.cgs deleted file mode 100644 index 92a47bc970f..00000000000 --- a/sim/testsuite/sim/frv/fblelr.cgs +++ /dev/null @@ -1,89 +0,0 @@ -# frv testcase for fblelr $FCCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fblelr -fblelr: - set_spr_addr bad,lr - set_fcc 0x0 0 - fblelr fcc0,0 - - set_spr_addr bad,lr - set_fcc 0x1 1 - fblelr fcc1,1 - - set_spr_addr bad,lr - set_fcc 0x2 2 - fblelr fcc2,2 - - set_spr_addr bad,lr - set_fcc 0x3 3 - fblelr fcc3,3 - - set_spr_addr ok5,lr - set_fcc 0x4 0 - fblelr fcc0,0 - fail -ok5: - set_spr_addr ok6,lr - set_fcc 0x5 1 - fblelr fcc1,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fblelr fcc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fblelr fcc3,3 - fail -ok8: - set_spr_addr ok9,lr - set_fcc 0x8 0 - fblelr fcc0,0 - fail -ok9: - set_spr_addr oka,lr - set_fcc 0x9 1 - fblelr fcc1,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fblelr fcc2,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fblelr fcc3,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fblelr fcc0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fblelr fcc1,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fblelr fcc2,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fblelr fcc3,3 - fail -okg: - pass -bad: - fail - diff --git a/sim/testsuite/sim/frv/fblg.cgs b/sim/testsuite/sim/frv/fblg.cgs deleted file mode 100644 index a16f80289f5..00000000000 --- a/sim/testsuite/sim/frv/fblg.cgs +++ /dev/null @@ -1,69 +0,0 @@ -# frv testcase for fblg $FCCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global fblg -fblg: - set_fcc 0x0 0 - fblg fcc0,0,bad - set_fcc 0x1 1 - fblg fcc1,1,bad - set_fcc 0x2 2 - fblg fcc2,2,ok3 - fail -ok3: - set_fcc 0x3 3 - fblg fcc3,3,ok4 - fail -ok4: - set_fcc 0x4 0 - fblg fcc0,0,ok5 - fail -ok5: - set_fcc 0x5 1 - fblg fcc1,1,ok6 - fail -ok6: - set_fcc 0x6 2 - fblg fcc2,2,ok7 - fail -ok7: - set_fcc 0x7 3 - fblg fcc3,3,ok8 - fail -ok8: - set_fcc 0x8 0 - fblg fcc0,0,bad - set_fcc 0x9 1 - fblg fcc1,1,bad - set_fcc 0xa 2 - fblg fcc2,2,okb - fail -okb: - set_fcc 0xb 3 - fblg fcc3,3,okc - fail -okc: - set_fcc 0xc 0 - fblg fcc0,0,okd - fail -okd: - set_fcc 0xd 1 - fblg fcc1,1,oke - fail -oke: - set_fcc 0xe 2 - fblg fcc2,2,okf - fail -okf: - set_fcc 0xf 3 - fblg fcc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fblglr.cgs b/sim/testsuite/sim/frv/fblglr.cgs deleted file mode 100644 index e7a32b04ce7..00000000000 --- a/sim/testsuite/sim/frv/fblglr.cgs +++ /dev/null @@ -1,88 +0,0 @@ -# frv testcase for fblglr $FCCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fblglr -fblglr: - set_spr_addr bad,lr - set_fcc 0x0 0 - fblglr fcc0,0 - - set_spr_addr bad,lr - set_fcc 0x1 1 - fblglr fcc1,1 - - set_spr_addr ok3,lr - set_fcc 0x2 2 - fblglr fcc2,2 - fail -ok3: - set_spr_addr ok4,lr - set_fcc 0x3 3 - fblglr fcc3,3 - fail -ok4: - set_spr_addr ok5,lr - set_fcc 0x4 0 - fblglr fcc0,0 - fail -ok5: - set_spr_addr ok6,lr - set_fcc 0x5 1 - fblglr fcc1,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fblglr fcc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fblglr fcc3,3 - fail -ok8: - set_spr_addr bad,lr - set_fcc 0x8 0 - fblglr fcc0,0 - - set_spr_addr bad,lr - set_fcc 0x9 1 - fblglr fcc1,1 - - set_spr_addr okb,lr - set_fcc 0xa 2 - fblglr fcc2,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fblglr fcc3,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fblglr fcc0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fblglr fcc1,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fblglr fcc2,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fblglr fcc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fblt.cgs b/sim/testsuite/sim/frv/fblt.cgs deleted file mode 100644 index ef7e5c78c45..00000000000 --- a/sim/testsuite/sim/frv/fblt.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for fblt $FCCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global fblt -fblt: - set_fcc 0x0 0 - fblt fcc0,0,bad - set_fcc 0x1 1 - fblt fcc1,1,bad - set_fcc 0x2 2 - fblt fcc2,2,bad - set_fcc 0x3 3 - fblt fcc3,3,bad - set_fcc 0x4 0 - fblt fcc0,0,ok5 - fail -ok5: - set_fcc 0x5 1 - fblt fcc1,1,ok6 - fail -ok6: - set_fcc 0x6 2 - fblt fcc2,2,ok7 - fail -ok7: - set_fcc 0x7 3 - fblt fcc3,3,ok8 - fail -ok8: - set_fcc 0x8 0 - fblt fcc0,0,bad - set_fcc 0x9 1 - fblt fcc1,1,bad - set_fcc 0xa 2 - fblt fcc2,2,bad - set_fcc 0xb 3 - fblt fcc3,3,bad - set_fcc 0xc 0 - fblt fcc0,0,okd - fail -okd: - set_fcc 0xd 1 - fblt fcc1,1,oke - fail -oke: - set_fcc 0xe 2 - fblt fcc2,2,okf - fail -okf: - set_fcc 0xf 3 - fblt fcc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbltlr.cgs b/sim/testsuite/sim/frv/fbltlr.cgs deleted file mode 100644 index 0a2c43696d3..00000000000 --- a/sim/testsuite/sim/frv/fbltlr.cgs +++ /dev/null @@ -1,84 +0,0 @@ -# frv testcase for fbltlr $FCCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fbltlr -fbltlr: - set_spr_addr bad,lr - set_fcc 0x0 0 - fbltlr fcc0,0 - - set_spr_addr bad,lr - set_fcc 0x1 1 - fbltlr fcc1,1 - - set_spr_addr bad,lr - set_fcc 0x2 2 - fbltlr fcc2,2 - - set_spr_addr bad,lr - set_fcc 0x3 3 - fbltlr fcc3,3 - - set_spr_addr ok5,lr - set_fcc 0x4 0 - fbltlr fcc0,0 - fail -ok5: - set_spr_addr ok6,lr - set_fcc 0x5 1 - fbltlr fcc1,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fbltlr fcc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fbltlr fcc3,3 - fail -ok8: - set_spr_addr bad,lr - set_fcc 0x8 0 - fbltlr fcc0,0 - - set_spr_addr bad,lr - set_fcc 0x9 1 - fbltlr fcc1,1 - - set_spr_addr bad,lr - set_fcc 0xa 2 - fbltlr fcc2,2 - - set_spr_addr bad,lr - set_fcc 0xb 3 - fbltlr fcc3,3 - - set_spr_addr okd,lr - set_fcc 0xc 0 - fbltlr fcc0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fbltlr fcc1,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fbltlr fcc2,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fbltlr fcc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbne.cgs b/sim/testsuite/sim/frv/fbne.cgs deleted file mode 100644 index f376eeaeac0..00000000000 --- a/sim/testsuite/sim/frv/fbne.cgs +++ /dev/null @@ -1,73 +0,0 @@ -# frv testcase for fbne $FCCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global fbne -fbne: - set_fcc 0x0 0 - fbne fcc0,0,bad - set_fcc 0x1 1 - fbne fcc1,1,ok2 - fail -ok2: - set_fcc 0x2 2 - fbne fcc2,2,ok3 - fail -ok3: - set_fcc 0x3 3 - fbne fcc3,3,ok4 - fail -ok4: - set_fcc 0x4 0 - fbne fcc0,0,ok5 - fail -ok5: - set_fcc 0x5 1 - fbne fcc1,1,ok6 - fail -ok6: - set_fcc 0x6 2 - fbne fcc2,2,ok7 - fail -ok7: - set_fcc 0x7 3 - fbne fcc3,3,ok8 - fail -ok8: - set_fcc 0x8 0 - fbne fcc0,0,bad - set_fcc 0x9 1 - fbne fcc1,1,oka - fail -oka: - set_fcc 0xa 2 - fbne fcc2,2,okb - fail -okb: - set_fcc 0xb 3 - fbne fcc3,3,okc - fail -okc: - set_fcc 0xc 0 - fbne fcc0,0,okd - fail -okd: - set_fcc 0xd 1 - fbne fcc1,1,oke - fail -oke: - set_fcc 0xe 2 - fbne fcc2,2,okf - fail -okf: - set_fcc 0xf 3 - fbne fcc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbnelr.cgs b/sim/testsuite/sim/frv/fbnelr.cgs deleted file mode 100644 index 334d185a4d4..00000000000 --- a/sim/testsuite/sim/frv/fbnelr.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fbnelr $FCCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fbnelr -fbnelr: - set_spr_addr bad,lr - set_fcc 0x0 0 - fbnelr fcc0,0 - - set_spr_addr ok2,lr - set_fcc 0x1 1 - fbnelr fcc1,1 - fail -ok2: - set_spr_addr ok3,lr - set_fcc 0x2 2 - fbnelr fcc2,2 - fail -ok3: - set_spr_addr ok4,lr - set_fcc 0x3 3 - fbnelr fcc3,3 - fail -ok4: - set_spr_addr ok5,lr - set_fcc 0x4 0 - fbnelr fcc0,0 - fail -ok5: - set_spr_addr ok6,lr - set_fcc 0x5 1 - fbnelr fcc1,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fbnelr fcc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fbnelr fcc3,3 - fail -ok8: - set_spr_addr bad,lr - set_fcc 0x8 0 - fbnelr fcc0,0 - - set_spr_addr oka,lr - set_fcc 0x9 1 - fbnelr fcc1,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fbnelr fcc2,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fbnelr fcc3,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fbnelr fcc0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fbnelr fcc1,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fbnelr fcc2,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fbnelr fcc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbno.cgs b/sim/testsuite/sim/frv/fbno.cgs deleted file mode 100644 index a3dc5877f47..00000000000 --- a/sim/testsuite/sim/frv/fbno.cgs +++ /dev/null @@ -1,45 +0,0 @@ -# frv testcase for fbno $FCCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global fbno -fbno: - set_fcc 0x0 0 - fbno - set_fcc 0x1 1 - fbno - set_fcc 0x2 2 - fbno - set_fcc 0x3 3 - fbno - set_fcc 0x4 0 - fbno - set_fcc 0x5 1 - fbno - set_fcc 0x6 2 - fbno - set_fcc 0x7 3 - fbno - set_fcc 0x8 0 - fbno - set_fcc 0x9 1 - fbno - set_fcc 0xa 2 - fbno - set_fcc 0xb 3 - fbno - set_fcc 0xc 0 - fbno - set_fcc 0xd 1 - fbno - set_fcc 0xe 2 - fbno - set_fcc 0xf 3 - fbno - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbnolr.cgs b/sim/testsuite/sim/frv/fbnolr.cgs deleted file mode 100644 index be5a0ef9a6c..00000000000 --- a/sim/testsuite/sim/frv/fbnolr.cgs +++ /dev/null @@ -1,47 +0,0 @@ -# frv testcase for fbnolr -# mach: all - - .include "testutils.inc" - - start - - .global fbnolr -fbnolr: - set_spr_addr bad,lr - - set_fcc 0x0 0 - fbnolr - set_fcc 0x1 1 - fbnolr - set_fcc 0x2 2 - fbnolr - set_fcc 0x3 3 - fbnolr - set_fcc 0x4 0 - fbnolr - set_fcc 0x5 1 - fbnolr - set_fcc 0x6 2 - fbnolr - set_fcc 0x7 3 - fbnolr - set_fcc 0x8 0 - fbnolr - set_fcc 0x9 1 - fbnolr - set_fcc 0xa 2 - fbnolr - set_fcc 0xb 3 - fbnolr - set_fcc 0xc 0 - fbnolr - set_fcc 0xd 1 - fbnolr - set_fcc 0xe 2 - fbnolr - set_fcc 0xf 3 - fbnolr - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbo.cgs b/sim/testsuite/sim/frv/fbo.cgs deleted file mode 100644 index 42062c93f0f..00000000000 --- a/sim/testsuite/sim/frv/fbo.cgs +++ /dev/null @@ -1,73 +0,0 @@ -# frv testcase for fbo $FCCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global fbo -fbo: - set_fcc 0x0 0 - fbo fcc0,0,bad - set_fcc 0x1 1 - fbo fcc1,1,bad - set_fcc 0x2 2 - fbo fcc2,2,ok3 - fail -ok3: - set_fcc 0x3 3 - fbo fcc3,3,ok4 - fail -ok4: - set_fcc 0x4 0 - fbo fcc0,0,ok5 - fail -ok5: - set_fcc 0x5 1 - fbo fcc1,1,ok6 - fail -ok6: - set_fcc 0x6 2 - fbo fcc2,2,ok7 - fail -ok7: - set_fcc 0x7 3 - fbo fcc3,3,ok8 - fail -ok8: - set_fcc 0x8 0 - fbo fcc0,0,ok9 - fail -ok9: - set_fcc 0x9 1 - fbo fcc1,1,oka - fail -oka: - set_fcc 0xa 2 - fbo fcc2,2,okb - fail -okb: - set_fcc 0xb 3 - fbo fcc3,3,okc - fail -okc: - set_fcc 0xc 0 - fbo fcc0,0,okd - fail -okd: - set_fcc 0xd 1 - fbo fcc1,1,oke - fail -oke: - set_fcc 0xe 2 - fbo fcc2,2,okf - fail -okf: - set_fcc 0xf 3 - fbo fcc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbolr.cgs b/sim/testsuite/sim/frv/fbolr.cgs deleted file mode 100644 index 2f9bfb34bf3..00000000000 --- a/sim/testsuite/sim/frv/fbolr.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fbolr $FCCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fbolr -fbolr: - set_spr_addr bad,lr - set_fcc 0x0 0 - fbolr fcc0,0 - - set_spr_addr bad,lr - set_fcc 0x1 1 - fbolr fcc1,1 - - set_spr_addr ok3,lr - set_fcc 0x2 2 - fbolr fcc2,2 - fail -ok3: - set_spr_addr ok4,lr - set_fcc 0x3 3 - fbolr fcc3,3 - fail -ok4: - set_spr_addr ok5,lr - set_fcc 0x4 0 - fbolr fcc0,0 - fail -ok5: - set_spr_addr ok6,lr - set_fcc 0x5 1 - fbolr fcc1,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fbolr fcc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fbolr fcc3,3 - fail -ok8: - set_spr_addr ok9,lr - set_fcc 0x8 0 - fbolr fcc0,0 - fail -ok9: - set_spr_addr oka,lr - set_fcc 0x9 1 - fbolr fcc1,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fbolr fcc2,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fbolr fcc3,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fbolr fcc0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fbolr fcc1,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fbolr fcc2,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fbolr fcc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbra.cgs b/sim/testsuite/sim/frv/fbra.cgs deleted file mode 100644 index 2f293081ff0..00000000000 --- a/sim/testsuite/sim/frv/fbra.cgs +++ /dev/null @@ -1,75 +0,0 @@ -# frv testcase for fbra $FCCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global fbra -fbra: - set_fcc 0x0 0 - fbra ok1 - fail -ok1: - set_fcc 0x1 1 - fbra ok2 - fail -ok2: - set_fcc 0x2 2 - fbra ok3 - fail -ok3: - set_fcc 0x3 3 - fbra ok4 - fail -ok4: - set_fcc 0x4 0 - fbra ok5 - fail -ok5: - set_fcc 0x5 1 - fbra ok6 - fail -ok6: - set_fcc 0x6 2 - fbra ok7 - fail -ok7: - set_fcc 0x7 3 - fbra ok8 - fail -ok8: - set_fcc 0x8 0 - fbra ok9 - fail -ok9: - set_fcc 0x9 1 - fbra oka - fail -oka: - set_fcc 0xa 2 - fbra okb - fail -okb: - set_fcc 0xb 3 - fbra okc - fail -okc: - set_fcc 0xc 0 - fbra okd - fail -okd: - set_fcc 0xd 1 - fbra oke - fail -oke: - set_fcc 0xe 2 - fbra okf - fail -okf: - set_fcc 0xf 3 - fbra okg - fail -okg: - - pass diff --git a/sim/testsuite/sim/frv/fbralr.cgs b/sim/testsuite/sim/frv/fbralr.cgs deleted file mode 100644 index d57afc9e68a..00000000000 --- a/sim/testsuite/sim/frv/fbralr.cgs +++ /dev/null @@ -1,91 +0,0 @@ -# frv testcase for fbralr -# mach: all - - .include "testutils.inc" - - start - - .global fbralr -fbralr: - set_spr_addr ok1,lr - set_fcc 0x0 0 - fbralr - fail -ok1: - set_spr_addr ok2,lr - set_fcc 0x1 1 - fbralr - fail -ok2: - set_spr_addr ok3,lr - set_fcc 0x2 2 - fbralr - fail -ok3: - set_spr_addr ok4,lr - set_fcc 0x3 3 - fbralr - fail -ok4: - set_spr_addr ok5,lr - set_fcc 0x4 0 - fbralr - fail -ok5: - set_spr_addr ok6,lr - set_fcc 0x5 1 - fbralr - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fbralr - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fbralr - fail -ok8: - set_spr_addr ok9,lr - set_fcc 0x8 0 - fbralr - fail -ok9: - set_spr_addr oka,lr - set_fcc 0x9 1 - fbralr - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fbralr - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fbralr - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fbralr - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fbralr - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fbralr - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fbralr - fail -okg: - - pass diff --git a/sim/testsuite/sim/frv/fbu.cgs b/sim/testsuite/sim/frv/fbu.cgs deleted file mode 100644 index f3970012a17..00000000000 --- a/sim/testsuite/sim/frv/fbu.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for fbu $FCCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global fbu -fbu: - set_fcc 0x0 0 - fbu fcc0,0,bad - set_fcc 0x1 1 - fbu fcc1,1,ok2 - fail -ok2: - set_fcc 0x2 2 - fbu fcc2,2,bad - set_fcc 0x3 3 - fbu fcc3,3,ok4 - fail -ok4: - set_fcc 0x4 0 - fbu fcc0,0,bad - set_fcc 0x5 1 - fbu fcc1,1,ok6 - fail -ok6: - set_fcc 0x6 2 - fbu fcc2,2,bad - set_fcc 0x7 3 - fbu fcc3,3,ok8 - fail -ok8: - set_fcc 0x8 0 - fbu fcc0,0,bad - set_fcc 0x9 1 - fbu fcc1,1,oka - fail -oka: - set_fcc 0xa 2 - fbu fcc2,2,bad - set_fcc 0xb 3 - fbu fcc3,3,okc - fail -okc: - set_fcc 0xc 0 - fbu fcc0,0,bad - set_fcc 0xd 1 - fbu fcc1,1,oke - fail -oke: - set_fcc 0xe 2 - fbu fcc2,2,bad - set_fcc 0xf 3 - fbu fcc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbue.cgs b/sim/testsuite/sim/frv/fbue.cgs deleted file mode 100644 index dd1d636a18e..00000000000 --- a/sim/testsuite/sim/frv/fbue.cgs +++ /dev/null @@ -1,69 +0,0 @@ -# frv testcase for fbue $FCCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global fbue -fbue: - set_fcc 0x0 0 - fbue fcc0,0,bad - set_fcc 0x1 1 - fbue fcc1,1,ok2 - fail -ok2: - set_fcc 0x2 2 - fbue fcc2,2,bad - set_fcc 0x3 3 - fbue fcc3,3,ok4 - fail -ok4: - set_fcc 0x4 0 - fbue fcc0,0,bad - set_fcc 0x5 1 - fbue fcc1,1,ok6 - fail -ok6: - set_fcc 0x6 2 - fbue fcc2,2,bad - set_fcc 0x7 3 - fbue fcc3,3,ok8 - fail -ok8: - set_fcc 0x8 0 - fbue fcc0,0,ok9 - fail -ok9: - set_fcc 0x9 1 - fbue fcc1,1,oka - fail -oka: - set_fcc 0xa 2 - fbue fcc2,2,okb - fail -okb: - set_fcc 0xb 3 - fbue fcc3,3,okc - fail -okc: - set_fcc 0xc 0 - fbue fcc0,0,okd - fail -okd: - set_fcc 0xd 1 - fbue fcc1,1,oke - fail -oke: - set_fcc 0xe 2 - fbue fcc2,2,okf - fail -okf: - set_fcc 0xf 3 - fbue fcc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbuelr.cgs b/sim/testsuite/sim/frv/fbuelr.cgs deleted file mode 100644 index 62ca6aa7063..00000000000 --- a/sim/testsuite/sim/frv/fbuelr.cgs +++ /dev/null @@ -1,88 +0,0 @@ -# frv testcase for fbuelr $FCCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fbuelr -fbuelr: - set_spr_addr bad,lr - set_fcc 0x0 0 - fbuelr fcc0,0 - - set_spr_addr ok2,lr - set_fcc 0x1 1 - fbuelr fcc1,1 - fail -ok2: - set_spr_addr bad,lr - set_fcc 0x2 2 - fbuelr fcc2,2 - - set_spr_addr ok4,lr - set_fcc 0x3 3 - fbuelr fcc3,3 - fail -ok4: - set_spr_addr bad,lr - set_fcc 0x4 0 - fbuelr fcc0,0 - - set_spr_addr ok6,lr - set_fcc 0x5 1 - fbuelr fcc1,1 - fail -ok6: - set_spr_addr bad,lr - set_fcc 0x6 2 - fbuelr fcc2,2 - - set_spr_addr ok8,lr - set_fcc 0x7 3 - fbuelr fcc3,3 - fail -ok8: - set_spr_addr ok9,lr - set_fcc 0x8 0 - fbuelr fcc0,0 - fail -ok9: - set_spr_addr oka,lr - set_fcc 0x9 1 - fbuelr fcc1,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fbuelr fcc2,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fbuelr fcc3,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fbuelr fcc0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fbuelr fcc1,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fbuelr fcc2,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fbuelr fcc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbug.cgs b/sim/testsuite/sim/frv/fbug.cgs deleted file mode 100644 index 3a5ee01aa3f..00000000000 --- a/sim/testsuite/sim/frv/fbug.cgs +++ /dev/null @@ -1,69 +0,0 @@ -# frv testcase for fbug $FCCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global fbug -fbug: - set_fcc 0x0 0 - fbug fcc0,0,bad - set_fcc 0x1 1 - fbug fcc1,1,ok2 - fail -ok2: - set_fcc 0x2 2 - fbug fcc2,2,ok3 - fail -ok3: - set_fcc 0x3 3 - fbug fcc3,3,ok4 - fail -ok4: - set_fcc 0x4 0 - fbug fcc0,0,bad - set_fcc 0x5 1 - fbug fcc1,1,ok6 - fail -ok6: - set_fcc 0x6 2 - fbug fcc2,2,ok7 - fail -ok7: - set_fcc 0x7 3 - fbug fcc3,3,ok8 - fail -ok8: - set_fcc 0x8 0 - fbug fcc0,0,bad - set_fcc 0x9 1 - fbug fcc1,1,oka - fail -oka: - set_fcc 0xa 2 - fbug fcc2,2,okb - fail -okb: - set_fcc 0xb 3 - fbug fcc3,3,okc - fail -okc: - set_fcc 0xc 0 - fbug fcc0,0,bad - set_fcc 0xd 1 - fbug fcc1,1,oke - fail -oke: - set_fcc 0xe 2 - fbug fcc2,2,okf - fail -okf: - set_fcc 0xf 3 - fbug fcc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbuge.cgs b/sim/testsuite/sim/frv/fbuge.cgs deleted file mode 100644 index edbf7f83461..00000000000 --- a/sim/testsuite/sim/frv/fbuge.cgs +++ /dev/null @@ -1,73 +0,0 @@ -# frv testcase for fbuge $FCCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global fbuge -fbuge: - set_fcc 0x0 0 - fbuge fcc0,0,bad - set_fcc 0x1 1 - fbuge fcc1,1,ok2 - fail -ok2: - set_fcc 0x2 2 - fbuge fcc2,2,ok3 - fail -ok3: - set_fcc 0x3 3 - fbuge fcc3,3,ok4 - fail -ok4: - set_fcc 0x4 0 - fbuge fcc0,0,bad - set_fcc 0x5 1 - fbuge fcc1,1,ok6 - fail -ok6: - set_fcc 0x6 2 - fbuge fcc2,2,ok7 - fail -ok7: - set_fcc 0x7 3 - fbuge fcc3,3,ok8 - fail -ok8: - set_fcc 0x8 0 - fbuge fcc0,0,ok9 - fail -ok9: - set_fcc 0x9 1 - fbuge fcc1,1,oka - fail -oka: - set_fcc 0xa 2 - fbuge fcc2,2,okb - fail -okb: - set_fcc 0xb 3 - fbuge fcc3,3,okc - fail -okc: - set_fcc 0xc 0 - fbuge fcc0,0,okd - fail -okd: - set_fcc 0xd 1 - fbuge fcc1,1,oke - fail -oke: - set_fcc 0xe 2 - fbuge fcc2,2,okf - fail -okf: - set_fcc 0xf 3 - fbuge fcc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbugelr.cgs b/sim/testsuite/sim/frv/fbugelr.cgs deleted file mode 100644 index b1799c56918..00000000000 --- a/sim/testsuite/sim/frv/fbugelr.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fbugelr $FCCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fbugelr -fbugelr: - set_spr_addr bad,lr - set_fcc 0x0 0 - fbugelr fcc0,0 - - set_spr_addr ok2,lr - set_fcc 0x1 1 - fbugelr fcc1,1 - fail -ok2: - set_spr_addr ok3,lr - set_fcc 0x2 2 - fbugelr fcc2,2 - fail -ok3: - set_spr_addr ok4,lr - set_fcc 0x3 3 - fbugelr fcc3,3 - fail -ok4: - set_spr_addr bad,lr - set_fcc 0x4 0 - fbugelr fcc0,0 - - set_spr_addr ok6,lr - set_fcc 0x5 1 - fbugelr fcc1,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fbugelr fcc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fbugelr fcc3,3 - fail -ok8: - set_spr_addr ok9,lr - set_fcc 0x8 0 - fbugelr fcc0,0 - fail -ok9: - set_spr_addr oka,lr - set_fcc 0x9 1 - fbugelr fcc1,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fbugelr fcc2,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fbugelr fcc3,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fbugelr fcc0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fbugelr fcc1,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fbugelr fcc2,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fbugelr fcc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbuglr.cgs b/sim/testsuite/sim/frv/fbuglr.cgs deleted file mode 100644 index d660a95d810..00000000000 --- a/sim/testsuite/sim/frv/fbuglr.cgs +++ /dev/null @@ -1,88 +0,0 @@ -# frv testcase for fbuglr $FCCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fbuglr -fbuglr: - set_spr_addr bad,lr - set_fcc 0x0 0 - fbuglr fcc0,0 - - set_spr_addr ok2,lr - set_fcc 0x1 1 - fbuglr fcc1,1 - fail -ok2: - set_spr_addr ok3,lr - set_fcc 0x2 2 - fbuglr fcc2,2 - fail -ok3: - set_spr_addr ok4,lr - set_fcc 0x3 3 - fbuglr fcc3,3 - fail -ok4: - set_spr_addr bad,lr - set_fcc 0x4 0 - fbuglr fcc0,0 - - set_spr_addr ok6,lr - set_fcc 0x5 1 - fbuglr fcc1,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fbuglr fcc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fbuglr fcc3,3 - fail -ok8: - set_spr_addr bad,lr - set_fcc 0x8 0 - fbuglr fcc0,0 - - set_spr_addr oka,lr - set_fcc 0x9 1 - fbuglr fcc1,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fbuglr fcc2,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fbuglr fcc3,3 - fail -okc: - set_spr_addr bad,lr - set_fcc 0xc 0 - fbuglr fcc0,0 - - set_spr_addr oke,lr - set_fcc 0xd 1 - fbuglr fcc1,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fbuglr fcc2,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fbuglr fcc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbul.cgs b/sim/testsuite/sim/frv/fbul.cgs deleted file mode 100644 index 47b689d6ea5..00000000000 --- a/sim/testsuite/sim/frv/fbul.cgs +++ /dev/null @@ -1,69 +0,0 @@ -# frv testcase for fbul $FCCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global fbul -fbul: - set_fcc 0x0 0 - fbul fcc0,0,bad - set_fcc 0x1 1 - fbul fcc1,1,ok2 - fail -ok2: - set_fcc 0x2 2 - fbul fcc2,2,bad - set_fcc 0x3 3 - fbul fcc3,3,ok4 - fail -ok4: - set_fcc 0x4 0 - fbul fcc0,0,ok5 - fail -ok5: - set_fcc 0x5 1 - fbul fcc1,1,ok6 - fail -ok6: - set_fcc 0x6 2 - fbul fcc2,2,ok7 - fail -ok7: - set_fcc 0x7 3 - fbul fcc3,3,ok8 - fail -ok8: - set_fcc 0x8 0 - fbul fcc0,0,bad - set_fcc 0x9 1 - fbul fcc1,1,oka - fail -oka: - set_fcc 0xa 2 - fbul fcc2,2,bad - set_fcc 0xb 3 - fbul fcc3,3,okc - fail -okc: - set_fcc 0xc 0 - fbul fcc0,0,okd - fail -okd: - set_fcc 0xd 1 - fbul fcc1,1,oke - fail -oke: - set_fcc 0xe 2 - fbul fcc2,2,okf - fail -okf: - set_fcc 0xf 3 - fbul fcc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbule.cgs b/sim/testsuite/sim/frv/fbule.cgs deleted file mode 100644 index ad5f4e9b173..00000000000 --- a/sim/testsuite/sim/frv/fbule.cgs +++ /dev/null @@ -1,73 +0,0 @@ -# frv testcase for fbule $FCCi,$hint,$label16 -# mach: all - - .include "testutils.inc" - - start - - .global fbule -fbule: - set_fcc 0x0 0 - fbule fcc0,0,bad - set_fcc 0x1 1 - fbule fcc1,1,ok2 - fail -ok2: - set_fcc 0x2 2 - fbule fcc2,2,bad - set_fcc 0x3 3 - fbule fcc3,3,ok4 - fail -ok4: - set_fcc 0x4 0 - fbule fcc0,0,ok5 - fail -ok5: - set_fcc 0x5 1 - fbule fcc1,1,ok6 - fail -ok6: - set_fcc 0x6 2 - fbule fcc2,2,ok7 - fail -ok7: - set_fcc 0x7 3 - fbule fcc3,3,ok8 - fail -ok8: - set_fcc 0x8 0 - fbule fcc0,0,ok9 - fail -ok9: - set_fcc 0x9 1 - fbule fcc1,1,oka - fail -oka: - set_fcc 0xa 2 - fbule fcc2,2,okb - fail -okb: - set_fcc 0xb 3 - fbule fcc3,3,okc - fail -okc: - set_fcc 0xc 0 - fbule fcc0,0,okd - fail -okd: - set_fcc 0xd 1 - fbule fcc1,1,oke - fail -oke: - set_fcc 0xe 2 - fbule fcc2,2,okf - fail -okf: - set_fcc 0xf 3 - fbule fcc3,3,okg - fail -okg: - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbulelr.cgs b/sim/testsuite/sim/frv/fbulelr.cgs deleted file mode 100644 index f34d58cfc6e..00000000000 --- a/sim/testsuite/sim/frv/fbulelr.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fbulelr $FCCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fbulelr -fbulelr: - set_spr_addr bad,lr - set_fcc 0x0 0 - fbulelr fcc0,0 - - set_spr_addr ok2,lr - set_fcc 0x1 1 - fbulelr fcc1,1 - fail -ok2: - set_spr_addr bad,lr - set_fcc 0x2 2 - fbulelr fcc2,2 - - set_spr_addr ok4,lr - set_fcc 0x3 3 - fbulelr fcc3,3 - fail -ok4: - set_spr_addr ok5,lr - set_fcc 0x4 0 - fbulelr fcc0,0 - fail -ok5: - set_spr_addr ok6,lr - set_fcc 0x5 1 - fbulelr fcc1,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fbulelr fcc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fbulelr fcc3,3 - fail -ok8: - set_spr_addr ok9,lr - set_fcc 0x8 0 - fbulelr fcc0,0 - fail -ok9: - set_spr_addr oka,lr - set_fcc 0x9 1 - fbulelr fcc1,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fbulelr fcc2,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fbulelr fcc3,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fbulelr fcc0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fbulelr fcc1,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fbulelr fcc2,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fbulelr fcc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbullr.cgs b/sim/testsuite/sim/frv/fbullr.cgs deleted file mode 100644 index 2d5b251ce00..00000000000 --- a/sim/testsuite/sim/frv/fbullr.cgs +++ /dev/null @@ -1,88 +0,0 @@ -# frv testcase for fbullr $FCCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fbullr -fbullr: - set_spr_addr bad,lr - set_fcc 0x0 0 - fbullr fcc0,0 - - set_spr_addr ok2,lr - set_fcc 0x1 1 - fbullr fcc1,1 - fail -ok2: - set_spr_addr bad,lr - set_fcc 0x2 2 - fbullr fcc2,2 - - set_spr_addr ok4,lr - set_fcc 0x3 3 - fbullr fcc3,3 - fail -ok4: - set_spr_addr ok5,lr - set_fcc 0x4 0 - fbullr fcc0,0 - fail -ok5: - set_spr_addr ok6,lr - set_fcc 0x5 1 - fbullr fcc1,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fbullr fcc2,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fbullr fcc3,3 - fail -ok8: - set_spr_addr bad,lr - set_fcc 0x8 0 - fbullr fcc0,0 - - set_spr_addr oka,lr - set_fcc 0x9 1 - fbullr fcc1,1 - fail -oka: - set_spr_addr bad,lr - set_fcc 0xa 2 - fbullr fcc2,2 - - set_spr_addr okc,lr - set_fcc 0xb 3 - fbullr fcc3,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fbullr fcc0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fbullr fcc1,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fbullr fcc2,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fbullr fcc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fbulr.cgs b/sim/testsuite/sim/frv/fbulr.cgs deleted file mode 100644 index d8594bc3b91..00000000000 --- a/sim/testsuite/sim/frv/fbulr.cgs +++ /dev/null @@ -1,84 +0,0 @@ -# frv testcase for fbulr $FCCi,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fbulr -fbulr: - set_spr_addr bad,lr - set_fcc 0x0 0 - fbulr fcc0,0 - - set_spr_addr ok2,lr - set_fcc 0x1 1 - fbulr fcc1,1 - fail -ok2: - set_spr_addr bad,lr - set_fcc 0x2 2 - fbulr fcc2,2 - - set_spr_addr ok4,lr - set_fcc 0x3 3 - fbulr fcc3,3 - fail -ok4: - set_spr_addr bad,lr - set_fcc 0x4 0 - fbulr fcc0,0 - - set_spr_addr ok6,lr - set_fcc 0x5 1 - fbulr fcc1,1 - fail -ok6: - set_spr_addr bad,lr - set_fcc 0x6 2 - fbulr fcc2,2 - - set_spr_addr ok8,lr - set_fcc 0x7 3 - fbulr fcc3,3 - fail -ok8: - set_spr_addr bad,lr - set_fcc 0x8 0 - fbulr fcc0,0 - - set_spr_addr oka,lr - set_fcc 0x9 1 - fbulr fcc1,1 - fail -oka: - set_spr_addr bad,lr - set_fcc 0xa 2 - fbulr fcc2,2 - - set_spr_addr okc,lr - set_fcc 0xb 3 - fbulr fcc3,3 - fail -okc: - set_spr_addr bad,lr - set_fcc 0xc 0 - fbulr fcc0,0 - - set_spr_addr oke,lr - set_fcc 0xd 1 - fbulr fcc1,1 - fail -oke: - set_spr_addr bad,lr - set_fcc 0xe 2 - fbulr fcc2,2 - - set_spr_addr okg,lr - set_fcc 0xf 3 - fbulr fcc3,3 - fail -okg: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fcbeqlr.cgs b/sim/testsuite/sim/frv/fcbeqlr.cgs deleted file mode 100644 index b87e77f34a4..00000000000 --- a/sim/testsuite/sim/frv/fcbeqlr.cgs +++ /dev/null @@ -1,262 +0,0 @@ -# frv testcase for fcbeqlr $FCCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fcbeqlr -fcbeqlr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbeqlr fcc0,0,0 - - set_spr_addr bad,lr - set_fcc 0x1 1 - fcbeqlr fcc1,0,1 - - set_spr_addr bad,lr - set_fcc 0x2 2 - fcbeqlr fcc2,0,2 - - set_spr_addr bad,lr - set_fcc 0x3 3 - fcbeqlr fcc3,0,3 - - set_spr_addr bad,lr - set_fcc 0x4 0 - fcbeqlr fcc0,0,0 - - set_spr_addr bad,lr - set_fcc 0x5 1 - fcbeqlr fcc1,0,1 - - set_spr_addr bad,lr - set_fcc 0x6 2 - fcbeqlr fcc2,0,2 - - set_spr_addr bad,lr - set_fcc 0x7 3 - fcbeqlr fcc3,0,3 - - set_spr_addr ok9,lr - set_fcc 0x8 0 - fcbeqlr fcc0,0,0 - fail -ok9: - set_spr_addr oka,lr - set_fcc 0x9 1 - fcbeqlr fcc1,0,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fcbeqlr fcc2,0,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fcbeqlr fcc3,0,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fcbeqlr fcc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fcbeqlr fcc1,0,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fcbeqlr fcc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fcbeqlr fcc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbeqlr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x1 1 - fcbeqlr fcc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x2 2 - fcbeqlr fcc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x3 3 - fcbeqlr fcc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x4 0 - fcbeqlr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x5 1 - fcbeqlr fcc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x6 2 - fcbeqlr fcc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x7 3 - fcbeqlr fcc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okp,lr - set_fcc 0x8 0 - fcbeqlr fcc0,1,0 - fail -okp: - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_fcc 0x9 1 - fcbeqlr fcc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_fcc 0xa 2 - fcbeqlr fcc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_fcc 0xb 3 - fcbeqlr fcc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_fcc 0xc 0 - fcbeqlr fcc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_fcc 0xd 1 - fcbeqlr fcc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_fcc 0xe 2 - fcbeqlr fcc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_fcc 0xf 3 - fcbeqlr fcc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - - set_fcc 0x0 0 - fcbeqlr fcc0,1,0 - set_fcc 0x1 1 - fcbeqlr fcc1,1,1 - set_fcc 0x2 2 - fcbeqlr fcc2,1,2 - set_fcc 0x3 3 - fcbeqlr fcc3,1,3 - set_fcc 0x4 0 - fcbeqlr fcc0,1,0 - set_fcc 0x5 1 - fcbeqlr fcc1,1,1 - set_fcc 0x6 2 - fcbeqlr fcc2,1,2 - set_fcc 0x7 3 - fcbeqlr fcc3,1,3 - set_fcc 0x8 0 - fcbeqlr fcc0,1,0 - set_fcc 0x9 1 - fcbeqlr fcc1,1,1 - set_fcc 0xa 2 - fcbeqlr fcc2,1,2 - set_fcc 0xb 3 - fcbeqlr fcc3,1,3 - set_fcc 0xc 0 - fcbeqlr fcc0,1,0 - set_fcc 0xd 1 - fcbeqlr fcc1,1,1 - set_fcc 0xe 2 - fcbeqlr fcc2,1,2 - set_fcc 0xf 3 - fcbeqlr fcc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcbeqlr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcbeqlr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcbeqlr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcbeqlr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcbeqlr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcbeqlr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcbeqlr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcbeqlr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcbeqlr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcbeqlr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcbeqlr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcbeqlr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcbeqlr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcbeqlr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcbeqlr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcbeqlr fcc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fcbgelr.cgs b/sim/testsuite/sim/frv/fcbgelr.cgs deleted file mode 100644 index cc1b9d7c78c..00000000000 --- a/sim/testsuite/sim/frv/fcbgelr.cgs +++ /dev/null @@ -1,270 +0,0 @@ -# frv testcase for fcbgelr $FCCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fcbgelr -fcbgelr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbgelr fcc0,0,0 - - set_spr_addr bad,lr - set_fcc 0x1 1 - fcbgelr fcc1,0,1 - - set_spr_addr ok3,lr - set_fcc 0x2 2 - fcbgelr fcc2,0,2 - fail -ok3: - set_spr_addr ok4,lr - set_fcc 0x3 3 - fcbgelr fcc3,0,3 - fail -ok4: - set_spr_addr bad,lr - set_fcc 0x4 0 - fcbgelr fcc0,0,0 - - set_spr_addr bad,lr - set_fcc 0x5 1 - fcbgelr fcc1,0,1 - - set_spr_addr ok7,lr - set_fcc 0x6 2 - fcbgelr fcc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fcbgelr fcc3,0,3 - fail -ok8: - set_spr_addr ok9,lr - set_fcc 0x8 0 - fcbgelr fcc0,0,0 - fail -ok9: - set_spr_addr oka,lr - set_fcc 0x9 1 - fcbgelr fcc1,0,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fcbgelr fcc2,0,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fcbgelr fcc3,0,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fcbgelr fcc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fcbgelr fcc1,0,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fcbgelr fcc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fcbgelr fcc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbgelr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x1 1 - fcbgelr fcc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okj,lr - set_fcc 0x2 2 - fcbgelr fcc2,1,2 - fail -okj: - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_fcc 0x3 3 - fcbgelr fcc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x4 0 - fcbgelr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x5 1 - fcbgelr fcc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_fcc 0x6 2 - fcbgelr fcc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_fcc 0x7 3 - fcbgelr fcc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr okp,lr - set_fcc 0x8 0 - fcbgelr fcc0,1,0 - fail -okp: - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_fcc 0x9 1 - fcbgelr fcc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_fcc 0xa 2 - fcbgelr fcc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_fcc 0xb 3 - fcbgelr fcc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_fcc 0xc 0 - fcbgelr fcc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_fcc 0xd 1 - fcbgelr fcc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_fcc 0xe 2 - fcbgelr fcc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_fcc 0xf 3 - fcbgelr fcc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - - set_fcc 0x0 0 - fcbgelr fcc0,1,0 - set_fcc 0x1 1 - fcbgelr fcc1,1,1 - set_fcc 0x2 2 - fcbgelr fcc2,1,2 - set_fcc 0x3 3 - fcbgelr fcc3,1,3 - set_fcc 0x4 0 - fcbgelr fcc0,1,0 - set_fcc 0x5 1 - fcbgelr fcc1,1,1 - set_fcc 0x6 2 - fcbgelr fcc2,1,2 - set_fcc 0x7 3 - fcbgelr fcc3,1,3 - set_fcc 0x8 0 - fcbgelr fcc0,1,0 - set_fcc 0x9 1 - fcbgelr fcc1,1,1 - set_fcc 0xa 2 - fcbgelr fcc2,1,2 - set_fcc 0xb 3 - fcbgelr fcc3,1,3 - set_fcc 0xc 0 - fcbgelr fcc0,1,0 - set_fcc 0xd 1 - fcbgelr fcc1,1,1 - set_fcc 0xe 2 - fcbgelr fcc2,1,2 - set_fcc 0xf 3 - fcbgelr fcc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcbgelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcbgelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcbgelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcbgelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcbgelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcbgelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcbgelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcbgelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcbgelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcbgelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcbgelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcbgelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcbgelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcbgelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcbgelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcbgelr fcc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fcbgtlr.cgs b/sim/testsuite/sim/frv/fcbgtlr.cgs deleted file mode 100644 index 76204e235ab..00000000000 --- a/sim/testsuite/sim/frv/fcbgtlr.cgs +++ /dev/null @@ -1,262 +0,0 @@ -# frv testcase for fcbgtlr $FCCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fcbgtlr -fcbgtlr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbgtlr fcc0,0,0 - - set_spr_addr bad,lr - set_fcc 0x1 1 - fcbgtlr fcc1,0,1 - - set_spr_addr ok3,lr - set_fcc 0x2 2 - fcbgtlr fcc2,0,2 - fail -ok3: - set_spr_addr ok4,lr - set_fcc 0x3 3 - fcbgtlr fcc3,0,3 - fail -ok4: - set_spr_addr bad,lr - set_fcc 0x4 0 - fcbgtlr fcc0,0,0 - - set_spr_addr bad,lr - set_fcc 0x5 1 - fcbgtlr fcc1,0,1 - - set_spr_addr ok7,lr - set_fcc 0x6 2 - fcbgtlr fcc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fcbgtlr fcc3,0,3 - fail -ok8: - set_spr_addr bad,lr - set_fcc 0x8 0 - fcbgtlr fcc0,0,0 - - set_spr_addr bad,lr - set_fcc 0x9 1 - fcbgtlr fcc1,0,1 - - set_spr_addr okb,lr - set_fcc 0xa 2 - fcbgtlr fcc2,0,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fcbgtlr fcc3,0,3 - fail -okc: - set_spr_addr bad,lr - set_fcc 0xc 0 - fcbgtlr fcc0,0,0 - - set_spr_addr bad,lr - set_fcc 0xd 1 - fcbgtlr fcc1,0,1 - - set_spr_addr okf,lr - set_fcc 0xe 2 - fcbgtlr fcc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fcbgtlr fcc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbgtlr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x1 1 - fcbgtlr fcc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okj,lr - set_fcc 0x2 2 - fcbgtlr fcc2,1,2 - fail -okj: - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_fcc 0x3 3 - fcbgtlr fcc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x4 0 - fcbgtlr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x5 1 - fcbgtlr fcc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_fcc 0x6 2 - fcbgtlr fcc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_fcc 0x7 3 - fcbgtlr fcc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x8 0 - fcbgtlr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x9 1 - fcbgtlr fcc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_fcc 0xa 2 - fcbgtlr fcc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_fcc 0xb 3 - fcbgtlr fcc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0xc 0 - fcbgtlr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0xd 1 - fcbgtlr fcc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_fcc 0xe 2 - fcbgtlr fcc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_fcc 0xf 3 - fcbgtlr fcc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - - set_fcc 0x0 0 - fcbgtlr fcc0,1,0 - set_fcc 0x1 1 - fcbgtlr fcc1,1,1 - set_fcc 0x2 2 - fcbgtlr fcc2,1,2 - set_fcc 0x3 3 - fcbgtlr fcc3,1,3 - set_fcc 0x4 0 - fcbgtlr fcc0,1,0 - set_fcc 0x5 1 - fcbgtlr fcc1,1,1 - set_fcc 0x6 2 - fcbgtlr fcc2,1,2 - set_fcc 0x7 3 - fcbgtlr fcc3,1,3 - set_fcc 0x8 0 - fcbgtlr fcc0,1,0 - set_fcc 0x9 1 - fcbgtlr fcc1,1,1 - set_fcc 0xa 2 - fcbgtlr fcc2,1,2 - set_fcc 0xb 3 - fcbgtlr fcc3,1,3 - set_fcc 0xc 0 - fcbgtlr fcc0,1,0 - set_fcc 0xd 1 - fcbgtlr fcc1,1,1 - set_fcc 0xe 2 - fcbgtlr fcc2,1,2 - set_fcc 0xf 3 - fcbgtlr fcc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcbgtlr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcbgtlr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcbgtlr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcbgtlr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcbgtlr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcbgtlr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcbgtlr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcbgtlr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcbgtlr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcbgtlr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcbgtlr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcbgtlr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcbgtlr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcbgtlr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcbgtlr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcbgtlr fcc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fcblelr.cgs b/sim/testsuite/sim/frv/fcblelr.cgs deleted file mode 100644 index b9850d6863d..00000000000 --- a/sim/testsuite/sim/frv/fcblelr.cgs +++ /dev/null @@ -1,270 +0,0 @@ -# frv testcase for fcblelr $FCCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fcblelr -fcblelr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcblelr fcc0,0,0 - - set_spr_addr bad,lr - set_fcc 0x1 1 - fcblelr fcc1,0,1 - - set_spr_addr bad,lr - set_fcc 0x2 2 - fcblelr fcc2,0,2 - - set_spr_addr bad,lr - set_fcc 0x3 3 - fcblelr fcc3,0,3 - - set_spr_addr ok5,lr - set_fcc 0x4 0 - fcblelr fcc0,0,0 - fail -ok5: - set_spr_addr ok6,lr - set_fcc 0x5 1 - fcblelr fcc1,0,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fcblelr fcc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fcblelr fcc3,0,3 - fail -ok8: - set_spr_addr ok9,lr - set_fcc 0x8 0 - fcblelr fcc0,0,0 - fail -ok9: - set_spr_addr oka,lr - set_fcc 0x9 1 - fcblelr fcc1,0,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fcblelr fcc2,0,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fcblelr fcc3,0,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fcblelr fcc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fcblelr fcc1,0,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fcblelr fcc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fcblelr fcc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcblelr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x1 1 - fcblelr fcc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x2 2 - fcblelr fcc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x3 3 - fcblelr fcc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okl,lr - set_fcc 0x4 0 - fcblelr fcc0,1,0 - fail -okl: - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_fcc 0x5 1 - fcblelr fcc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_fcc 0x6 2 - fcblelr fcc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_fcc 0x7 3 - fcblelr fcc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr okp,lr - set_fcc 0x8 0 - fcblelr fcc0,1,0 - fail -okp: - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_fcc 0x9 1 - fcblelr fcc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_fcc 0xa 2 - fcblelr fcc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_fcc 0xb 3 - fcblelr fcc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_fcc 0xc 0 - fcblelr fcc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_fcc 0xd 1 - fcblelr fcc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_fcc 0xe 2 - fcblelr fcc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_fcc 0xf 3 - fcblelr fcc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - - set_fcc 0x0 0 - fcblelr fcc0,1,0 - set_fcc 0x1 1 - fcblelr fcc1,1,1 - set_fcc 0x2 2 - fcblelr fcc2,1,2 - set_fcc 0x3 3 - fcblelr fcc3,1,3 - set_fcc 0x4 0 - fcblelr fcc0,1,0 - set_fcc 0x5 1 - fcblelr fcc1,1,1 - set_fcc 0x6 2 - fcblelr fcc2,1,2 - set_fcc 0x7 3 - fcblelr fcc3,1,3 - set_fcc 0x8 0 - fcblelr fcc0,1,0 - set_fcc 0x9 1 - fcblelr fcc1,1,1 - set_fcc 0xa 2 - fcblelr fcc2,1,2 - set_fcc 0xb 3 - fcblelr fcc3,1,3 - set_fcc 0xc 0 - fcblelr fcc0,1,0 - set_fcc 0xd 1 - fcblelr fcc1,1,1 - set_fcc 0xe 2 - fcblelr fcc2,1,2 - set_fcc 0xf 3 - fcblelr fcc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcblelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcblelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcblelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcblelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcblelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcblelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcblelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcblelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcblelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcblelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcblelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcblelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcblelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcblelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcblelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcblelr fcc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fcblglr.cgs b/sim/testsuite/sim/frv/fcblglr.cgs deleted file mode 100644 index e875d40fb1d..00000000000 --- a/sim/testsuite/sim/frv/fcblglr.cgs +++ /dev/null @@ -1,270 +0,0 @@ -# frv testcase for fcblglr $FCCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fcblglr -fcblglr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcblglr fcc0,0,0 - - set_spr_addr bad,lr - set_fcc 0x1 1 - fcblglr fcc1,0,1 - - set_spr_addr ok3,lr - set_fcc 0x2 2 - fcblglr fcc2,0,2 - fail -ok3: - set_spr_addr ok4,lr - set_fcc 0x3 3 - fcblglr fcc3,0,3 - fail -ok4: - set_spr_addr ok5,lr - set_fcc 0x4 0 - fcblglr fcc0,0,0 - fail -ok5: - set_spr_addr ok6,lr - set_fcc 0x5 1 - fcblglr fcc1,0,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fcblglr fcc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fcblglr fcc3,0,3 - fail -ok8: - set_spr_addr bad,lr - set_fcc 0x8 0 - fcblglr fcc0,0,0 - - set_spr_addr bad,lr - set_fcc 0x9 1 - fcblglr fcc1,0,1 - - set_spr_addr okb,lr - set_fcc 0xa 2 - fcblglr fcc2,0,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fcblglr fcc3,0,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fcblglr fcc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fcblglr fcc1,0,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fcblglr fcc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fcblglr fcc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcblglr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x1 1 - fcblglr fcc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okj,lr - set_fcc 0x2 2 - fcblglr fcc2,1,2 - fail -okj: - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_fcc 0x3 3 - fcblglr fcc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr okl,lr - set_fcc 0x4 0 - fcblglr fcc0,1,0 - fail -okl: - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_fcc 0x5 1 - fcblglr fcc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_fcc 0x6 2 - fcblglr fcc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_fcc 0x7 3 - fcblglr fcc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x8 0 - fcblglr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x9 1 - fcblglr fcc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_fcc 0xa 2 - fcblglr fcc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_fcc 0xb 3 - fcblglr fcc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_fcc 0xc 0 - fcblglr fcc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_fcc 0xd 1 - fcblglr fcc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_fcc 0xe 2 - fcblglr fcc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_fcc 0xf 3 - fcblglr fcc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - - set_fcc 0x0 0 - fcblglr fcc0,1,0 - set_fcc 0x1 1 - fcblglr fcc1,1,1 - set_fcc 0x2 2 - fcblglr fcc2,1,2 - set_fcc 0x3 3 - fcblglr fcc3,1,3 - set_fcc 0x4 0 - fcblglr fcc0,1,0 - set_fcc 0x5 1 - fcblglr fcc1,1,1 - set_fcc 0x6 2 - fcblglr fcc2,1,2 - set_fcc 0x7 3 - fcblglr fcc3,1,3 - set_fcc 0x8 0 - fcblglr fcc0,1,0 - set_fcc 0x9 1 - fcblglr fcc1,1,1 - set_fcc 0xa 2 - fcblglr fcc2,1,2 - set_fcc 0xb 3 - fcblglr fcc3,1,3 - set_fcc 0xc 0 - fcblglr fcc0,1,0 - set_fcc 0xd 1 - fcblglr fcc1,1,1 - set_fcc 0xe 2 - fcblglr fcc2,1,2 - set_fcc 0xf 3 - fcblglr fcc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcblglr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcblglr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcblglr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcblglr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcblglr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcblglr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcblglr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcblglr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcblglr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcblglr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcblglr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcblglr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcblglr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcblglr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcblglr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcblglr fcc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fcbltlr.cgs b/sim/testsuite/sim/frv/fcbltlr.cgs deleted file mode 100644 index d15dd3083c3..00000000000 --- a/sim/testsuite/sim/frv/fcbltlr.cgs +++ /dev/null @@ -1,262 +0,0 @@ -# frv testcase for fcbltlr $FCCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fcbltlr -fcbltlr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbltlr fcc0,0,0 - - set_spr_addr bad,lr - set_fcc 0x1 1 - fcbltlr fcc1,0,1 - - set_spr_addr bad,lr - set_fcc 0x2 2 - fcbltlr fcc2,0,2 - - set_spr_addr bad,lr - set_fcc 0x3 3 - fcbltlr fcc3,0,3 - - set_spr_addr ok5,lr - set_fcc 0x4 0 - fcbltlr fcc0,0,0 - fail -ok5: - set_spr_addr ok6,lr - set_fcc 0x5 1 - fcbltlr fcc1,0,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fcbltlr fcc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fcbltlr fcc3,0,3 - fail -ok8: - set_spr_addr bad,lr - set_fcc 0x8 0 - fcbltlr fcc0,0,0 - - set_spr_addr bad,lr - set_fcc 0x9 1 - fcbltlr fcc1,0,1 - - set_spr_addr bad,lr - set_fcc 0xa 2 - fcbltlr fcc2,0,2 - - set_spr_addr bad,lr - set_fcc 0xb 3 - fcbltlr fcc3,0,3 - - set_spr_addr okd,lr - set_fcc 0xc 0 - fcbltlr fcc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fcbltlr fcc1,0,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fcbltlr fcc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fcbltlr fcc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbltlr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x1 1 - fcbltlr fcc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x2 2 - fcbltlr fcc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x3 3 - fcbltlr fcc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okl,lr - set_fcc 0x4 0 - fcbltlr fcc0,1,0 - fail -okl: - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_fcc 0x5 1 - fcbltlr fcc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_fcc 0x6 2 - fcbltlr fcc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_fcc 0x7 3 - fcbltlr fcc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x8 0 - fcbltlr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x9 1 - fcbltlr fcc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0xa 2 - fcbltlr fcc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0xb 3 - fcbltlr fcc3,1,3 - - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_fcc 0xc 0 - fcbltlr fcc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_fcc 0xd 1 - fcbltlr fcc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_fcc 0xe 2 - fcbltlr fcc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_fcc 0xf 3 - fcbltlr fcc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - - set_fcc 0x0 0 - fcbltlr fcc0,1,0 - set_fcc 0x1 1 - fcbltlr fcc1,1,1 - set_fcc 0x2 2 - fcbltlr fcc2,1,2 - set_fcc 0x3 3 - fcbltlr fcc3,1,3 - set_fcc 0x4 0 - fcbltlr fcc0,1,0 - set_fcc 0x5 1 - fcbltlr fcc1,1,1 - set_fcc 0x6 2 - fcbltlr fcc2,1,2 - set_fcc 0x7 3 - fcbltlr fcc3,1,3 - set_fcc 0x8 0 - fcbltlr fcc0,1,0 - set_fcc 0x9 1 - fcbltlr fcc1,1,1 - set_fcc 0xa 2 - fcbltlr fcc2,1,2 - set_fcc 0xb 3 - fcbltlr fcc3,1,3 - set_fcc 0xc 0 - fcbltlr fcc0,1,0 - set_fcc 0xd 1 - fcbltlr fcc1,1,1 - set_fcc 0xe 2 - fcbltlr fcc2,1,2 - set_fcc 0xf 3 - fcbltlr fcc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcbltlr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcbltlr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcbltlr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcbltlr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcbltlr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcbltlr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcbltlr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcbltlr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcbltlr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcbltlr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcbltlr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcbltlr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcbltlr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcbltlr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcbltlr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcbltlr fcc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fcbnelr.cgs b/sim/testsuite/sim/frv/fcbnelr.cgs deleted file mode 100644 index cb0aa26a74b..00000000000 --- a/sim/testsuite/sim/frv/fcbnelr.cgs +++ /dev/null @@ -1,274 +0,0 @@ -# frv testcase for fcbnelr $FCCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fcbnelr -fcbnelr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbnelr fcc0,0,0 - - set_spr_addr ok2,lr - set_fcc 0x1 1 - fcbnelr fcc1,0,1 - fail -ok2: - set_spr_addr ok3,lr - set_fcc 0x2 2 - fcbnelr fcc2,0,2 - fail -ok3: - set_spr_addr ok4,lr - set_fcc 0x3 3 - fcbnelr fcc3,0,3 - fail -ok4: - set_spr_addr ok5,lr - set_fcc 0x4 0 - fcbnelr fcc0,0,0 - fail -ok5: - set_spr_addr ok6,lr - set_fcc 0x5 1 - fcbnelr fcc1,0,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fcbnelr fcc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fcbnelr fcc3,0,3 - fail -ok8: - set_spr_addr bad,lr - set_fcc 0x8 0 - fcbnelr fcc0,0,0 - - set_spr_addr oka,lr - set_fcc 0x9 1 - fcbnelr fcc1,0,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fcbnelr fcc2,0,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fcbnelr fcc3,0,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fcbnelr fcc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fcbnelr fcc1,0,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fcbnelr fcc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fcbnelr fcc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbnelr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr oki,lr - set_fcc 0x1 1 - fcbnelr fcc1,1,1 - fail -oki: - set_spr_immed 1,lcr - set_spr_addr okj,lr - set_fcc 0x2 2 - fcbnelr fcc2,1,2 - fail -okj: - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_fcc 0x3 3 - fcbnelr fcc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr okl,lr - set_fcc 0x4 0 - fcbnelr fcc0,1,0 - fail -okl: - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_fcc 0x5 1 - fcbnelr fcc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_fcc 0x6 2 - fcbnelr fcc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_fcc 0x7 3 - fcbnelr fcc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x8 0 - fcbnelr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_fcc 0x9 1 - fcbnelr fcc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_fcc 0xa 2 - fcbnelr fcc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_fcc 0xb 3 - fcbnelr fcc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_fcc 0xc 0 - fcbnelr fcc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_fcc 0xd 1 - fcbnelr fcc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_fcc 0xe 2 - fcbnelr fcc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_fcc 0xf 3 - fcbnelr fcc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - - set_fcc 0x0 0 - fcbnelr fcc0,1,0 - set_fcc 0x1 1 - fcbnelr fcc1,1,1 - set_fcc 0x2 2 - fcbnelr fcc2,1,2 - set_fcc 0x3 3 - fcbnelr fcc3,1,3 - set_fcc 0x4 0 - fcbnelr fcc0,1,0 - set_fcc 0x5 1 - fcbnelr fcc1,1,1 - set_fcc 0x6 2 - fcbnelr fcc2,1,2 - set_fcc 0x7 3 - fcbnelr fcc3,1,3 - set_fcc 0x8 0 - fcbnelr fcc0,1,0 - set_fcc 0x9 1 - fcbnelr fcc1,1,1 - set_fcc 0xa 2 - fcbnelr fcc2,1,2 - set_fcc 0xb 3 - fcbnelr fcc3,1,3 - set_fcc 0xc 0 - fcbnelr fcc0,1,0 - set_fcc 0xd 1 - fcbnelr fcc1,1,1 - set_fcc 0xe 2 - fcbnelr fcc2,1,2 - set_fcc 0xf 3 - fcbnelr fcc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcbnelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcbnelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcbnelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcbnelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcbnelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcbnelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcbnelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcbnelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcbnelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcbnelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcbnelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcbnelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcbnelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcbnelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcbnelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcbnelr fcc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fcbnolr.cgs b/sim/testsuite/sim/frv/fcbnolr.cgs deleted file mode 100644 index 3c1b73a64e6..00000000000 --- a/sim/testsuite/sim/frv/fcbnolr.cgs +++ /dev/null @@ -1,185 +0,0 @@ -# frv testcase for fcbnolr -# mach: all - - .include "testutils.inc" - - start - - .global fcbnolr -fcbnolr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - - set_fcc 0x0 0 - fcbnolr - set_fcc 0x1 1 - fcbnolr - set_fcc 0x2 2 - fcbnolr - set_fcc 0x3 3 - fcbnolr - set_fcc 0x4 0 - fcbnolr - set_fcc 0x5 1 - fcbnolr - set_fcc 0x6 2 - fcbnolr - set_fcc 0x7 3 - fcbnolr - set_fcc 0x8 0 - fcbnolr - set_fcc 0x9 1 - fcbnolr - set_fcc 0xa 2 - fcbnolr - set_fcc 0xb 3 - fcbnolr - set_fcc 0xc 0 - fcbnolr - set_fcc 0xd 1 - fcbnolr - set_fcc 0xe 2 - fcbnolr - set_fcc 0xf 3 - fcbnolr - - ; ccond is true - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcbnolr - - ; ccond is false - set_spr_immed 128,lcr - - set_fcc 0x0 0 - fcbnolr - set_fcc 0x1 1 - fcbnolr - set_fcc 0x2 2 - fcbnolr - set_fcc 0x3 3 - fcbnolr - set_fcc 0x4 0 - fcbnolr - set_fcc 0x5 1 - fcbnolr - set_fcc 0x6 2 - fcbnolr - set_fcc 0x7 3 - fcbnolr - set_fcc 0x8 0 - fcbnolr - set_fcc 0x9 1 - fcbnolr - set_fcc 0xa 2 - fcbnolr - set_fcc 0xb 3 - fcbnolr - set_fcc 0xc 0 - fcbnolr - set_fcc 0xd 1 - fcbnolr - set_fcc 0xe 2 - fcbnolr - set_fcc 0xf 3 - fcbnolr - - ; ccond is false - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcbnolr - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcbnolr - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fcbolr.cgs b/sim/testsuite/sim/frv/fcbolr.cgs deleted file mode 100644 index 31909f1bb2a..00000000000 --- a/sim/testsuite/sim/frv/fcbolr.cgs +++ /dev/null @@ -1,274 +0,0 @@ -# frv testcase for fcbolr $FCCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fcbolr -fcbolr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbolr fcc0,0,0 - - set_spr_addr bad,lr - set_fcc 0x1 1 - fcbolr fcc1,0,1 - - set_spr_addr ok3,lr - set_fcc 0x2 2 - fcbolr fcc2,0,2 - fail -ok3: - set_spr_addr ok4,lr - set_fcc 0x3 3 - fcbolr fcc3,0,3 - fail -ok4: - set_spr_addr ok5,lr - set_fcc 0x4 0 - fcbolr fcc0,0,0 - fail -ok5: - set_spr_addr ok6,lr - set_fcc 0x5 1 - fcbolr fcc1,0,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fcbolr fcc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fcbolr fcc3,0,3 - fail -ok8: - set_spr_addr ok9,lr - set_fcc 0x8 0 - fcbolr fcc0,0,0 - fail -ok9: - set_spr_addr oka,lr - set_fcc 0x9 1 - fcbolr fcc1,0,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fcbolr fcc2,0,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fcbolr fcc3,0,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fcbolr fcc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fcbolr fcc1,0,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fcbolr fcc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fcbolr fcc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbolr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x1 1 - fcbolr fcc1,1,1 - - set_spr_immed 1,lcr - set_spr_addr okj,lr - set_fcc 0x2 2 - fcbolr fcc2,1,2 - fail -okj: - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_fcc 0x3 3 - fcbolr fcc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr okl,lr - set_fcc 0x4 0 - fcbolr fcc0,1,0 - fail -okl: - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_fcc 0x5 1 - fcbolr fcc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_fcc 0x6 2 - fcbolr fcc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_fcc 0x7 3 - fcbolr fcc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr okp,lr - set_fcc 0x8 0 - fcbolr fcc0,1,0 - fail -okp: - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_fcc 0x9 1 - fcbolr fcc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_fcc 0xa 2 - fcbolr fcc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_fcc 0xb 3 - fcbolr fcc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_fcc 0xc 0 - fcbolr fcc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_fcc 0xd 1 - fcbolr fcc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_fcc 0xe 2 - fcbolr fcc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_fcc 0xf 3 - fcbolr fcc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - - set_fcc 0x0 0 - fcbolr fcc0,1,0 - set_fcc 0x1 1 - fcbolr fcc1,1,1 - set_fcc 0x2 2 - fcbolr fcc2,1,2 - set_fcc 0x3 3 - fcbolr fcc3,1,3 - set_fcc 0x4 0 - fcbolr fcc0,1,0 - set_fcc 0x5 1 - fcbolr fcc1,1,1 - set_fcc 0x6 2 - fcbolr fcc2,1,2 - set_fcc 0x7 3 - fcbolr fcc3,1,3 - set_fcc 0x8 0 - fcbolr fcc0,1,0 - set_fcc 0x9 1 - fcbolr fcc1,1,1 - set_fcc 0xa 2 - fcbolr fcc2,1,2 - set_fcc 0xb 3 - fcbolr fcc3,1,3 - set_fcc 0xc 0 - fcbolr fcc0,1,0 - set_fcc 0xd 1 - fcbolr fcc1,1,1 - set_fcc 0xe 2 - fcbolr fcc2,1,2 - set_fcc 0xf 3 - fcbolr fcc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcbolr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcbolr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcbolr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcbolr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcbolr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcbolr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcbolr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcbolr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcbolr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcbolr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcbolr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcbolr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcbolr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcbolr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcbolr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcbolr fcc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fcbralr.cgs b/sim/testsuite/sim/frv/fcbralr.cgs deleted file mode 100644 index 60359d8201e..00000000000 --- a/sim/testsuite/sim/frv/fcbralr.cgs +++ /dev/null @@ -1,276 +0,0 @@ -# frv testcase for fcbralr $ccond -# mach: all - - .include "testutils.inc" - - start - - .global fcbralr -fcbralr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr ok1,lr - set_fcc 0x0 0 - fcbralr 0 - fail -ok1: - set_spr_addr ok2,lr - set_fcc 0x1 1 - fcbralr 0 - fail -ok2: - set_spr_addr ok3,lr - set_fcc 0x2 2 - fcbralr 0 - fail -ok3: - set_spr_addr ok4,lr - set_fcc 0x3 3 - fcbralr 0 - fail -ok4: - set_spr_addr ok5,lr - set_fcc 0x4 0 - fcbralr 0 - fail -ok5: - set_spr_addr ok6,lr - set_fcc 0x5 1 - fcbralr 0 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fcbralr 0 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fcbralr 0 - fail -ok8: - set_spr_addr ok9,lr - set_fcc 0x8 0 - fcbralr 0 - fail -ok9: - set_spr_addr oka,lr - set_fcc 0x9 1 - fcbralr 0 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fcbralr 0 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fcbralr 0 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fcbralr 0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fcbralr 0 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fcbralr 0 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fcbralr 0 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr okh,lr - set_fcc 0x0 0 - fcbralr 1 - fail -okh: - set_spr_immed 1,lcr - set_spr_addr oki,lr - set_fcc 0x1 1 - fcbralr 1 - fail -oki: - set_spr_immed 1,lcr - set_spr_addr okj,lr - set_fcc 0x2 2 - fcbralr 1 - fail -okj: - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_fcc 0x3 3 - fcbralr 1 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr okl,lr - set_fcc 0x4 0 - fcbralr 1 - fail -okl: - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_fcc 0x5 1 - fcbralr 1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_fcc 0x6 2 - fcbralr 1 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_fcc 0x7 3 - fcbralr 1 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr okp,lr - set_fcc 0x8 0 - fcbralr 1 - fail -okp: - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_fcc 0x9 1 - fcbralr 1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_fcc 0xa 2 - fcbralr 1 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_fcc 0xb 3 - fcbralr 1 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_fcc 0xc 0 - fcbralr 1 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_fcc 0xd 1 - fcbralr 1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_fcc 0xe 2 - fcbralr 1 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_fcc 0xf 3 - fcbralr 1 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - - set_fcc 0x0 0 - fcbralr 1 - set_fcc 0x1 1 - fcbralr 1 - set_fcc 0x2 2 - fcbralr 1 - set_fcc 0x3 3 - fcbralr 1 - set_fcc 0x4 0 - fcbralr 1 - set_fcc 0x5 1 - fcbralr 1 - set_fcc 0x6 2 - fcbralr 1 - set_fcc 0x7 3 - fcbralr 1 - set_fcc 0x8 0 - fcbralr 1 - set_fcc 0x9 1 - fcbralr 1 - set_fcc 0xa 2 - fcbralr 1 - set_fcc 0xb 3 - fcbralr 1 - set_fcc 0xc 0 - fcbralr 1 - set_fcc 0xd 1 - fcbralr 1 - set_fcc 0xe 2 - fcbralr 1 - set_fcc 0xf 3 - fcbralr 1 - - ; ccond is false - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcbralr 0 - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcbralr 0 - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcbralr 0 - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcbralr 0 - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcbralr 0 - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcbralr 0 - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcbralr 0 - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcbralr 0 - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcbralr 0 - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcbralr 0 - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcbralr 0 - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcbralr 0 - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcbralr 0 - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcbralr 0 - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcbralr 0 - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcbralr 0 - - pass diff --git a/sim/testsuite/sim/frv/fcbuelr.cgs b/sim/testsuite/sim/frv/fcbuelr.cgs deleted file mode 100644 index e102ee31dec..00000000000 --- a/sim/testsuite/sim/frv/fcbuelr.cgs +++ /dev/null @@ -1,270 +0,0 @@ -# frv testcase for fcbuelr $FCCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fcbuelr -fcbuelr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbuelr fcc0,0,0 - - set_spr_addr ok2,lr - set_fcc 0x1 1 - fcbuelr fcc1,0,1 - fail -ok2: - set_spr_addr bad,lr - set_fcc 0x2 2 - fcbuelr fcc2,0,2 - - set_spr_addr ok4,lr - set_fcc 0x3 3 - fcbuelr fcc3,0,3 - fail -ok4: - set_spr_addr bad,lr - set_fcc 0x4 0 - fcbuelr fcc0,0,0 - - set_spr_addr ok6,lr - set_fcc 0x5 1 - fcbuelr fcc1,0,1 - fail -ok6: - set_spr_addr bad,lr - set_fcc 0x6 2 - fcbuelr fcc2,0,2 - - set_spr_addr ok8,lr - set_fcc 0x7 3 - fcbuelr fcc3,0,3 - fail -ok8: - set_spr_addr ok9,lr - set_fcc 0x8 0 - fcbuelr fcc0,0,0 - fail -ok9: - set_spr_addr oka,lr - set_fcc 0x9 1 - fcbuelr fcc1,0,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fcbuelr fcc2,0,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fcbuelr fcc3,0,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fcbuelr fcc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fcbuelr fcc1,0,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fcbuelr fcc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fcbuelr fcc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbuelr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr oki,lr - set_fcc 0x1 1 - fcbuelr fcc1,1,1 - fail -oki: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x2 2 - fcbuelr fcc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_fcc 0x3 3 - fcbuelr fcc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x4 0 - fcbuelr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_fcc 0x5 1 - fcbuelr fcc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x6 2 - fcbuelr fcc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_fcc 0x7 3 - fcbuelr fcc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr okp,lr - set_fcc 0x8 0 - fcbuelr fcc0,1,0 - fail -okp: - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_fcc 0x9 1 - fcbuelr fcc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_fcc 0xa 2 - fcbuelr fcc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_fcc 0xb 3 - fcbuelr fcc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_fcc 0xc 0 - fcbuelr fcc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_fcc 0xd 1 - fcbuelr fcc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_fcc 0xe 2 - fcbuelr fcc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_fcc 0xf 3 - fcbuelr fcc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - - set_fcc 0x0 0 - fcbuelr fcc0,1,0 - set_fcc 0x1 1 - fcbuelr fcc1,1,1 - set_fcc 0x2 2 - fcbuelr fcc2,1,2 - set_fcc 0x3 3 - fcbuelr fcc3,1,3 - set_fcc 0x4 0 - fcbuelr fcc0,1,0 - set_fcc 0x5 1 - fcbuelr fcc1,1,1 - set_fcc 0x6 2 - fcbuelr fcc2,1,2 - set_fcc 0x7 3 - fcbuelr fcc3,1,3 - set_fcc 0x8 0 - fcbuelr fcc0,1,0 - set_fcc 0x9 1 - fcbuelr fcc1,1,1 - set_fcc 0xa 2 - fcbuelr fcc2,1,2 - set_fcc 0xb 3 - fcbuelr fcc3,1,3 - set_fcc 0xc 0 - fcbuelr fcc0,1,0 - set_fcc 0xd 1 - fcbuelr fcc1,1,1 - set_fcc 0xe 2 - fcbuelr fcc2,1,2 - set_fcc 0xf 3 - fcbuelr fcc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcbuelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcbuelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcbuelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcbuelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcbuelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcbuelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcbuelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcbuelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcbuelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcbuelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcbuelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcbuelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcbuelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcbuelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcbuelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcbuelr fcc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fcbugelr.cgs b/sim/testsuite/sim/frv/fcbugelr.cgs deleted file mode 100644 index 8ecd1411115..00000000000 --- a/sim/testsuite/sim/frv/fcbugelr.cgs +++ /dev/null @@ -1,274 +0,0 @@ -# frv testcase for fcbugelr $FCCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fcbugelr -fcbugelr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbugelr fcc0,0,0 - - set_spr_addr ok2,lr - set_fcc 0x1 1 - fcbugelr fcc1,0,1 - fail -ok2: - set_spr_addr ok3,lr - set_fcc 0x2 2 - fcbugelr fcc2,0,2 - fail -ok3: - set_spr_addr ok4,lr - set_fcc 0x3 3 - fcbugelr fcc3,0,3 - fail -ok4: - set_spr_addr bad,lr - set_fcc 0x4 0 - fcbugelr fcc0,0,0 - - set_spr_addr ok6,lr - set_fcc 0x5 1 - fcbugelr fcc1,0,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fcbugelr fcc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fcbugelr fcc3,0,3 - fail -ok8: - set_spr_addr ok9,lr - set_fcc 0x8 0 - fcbugelr fcc0,0,0 - fail -ok9: - set_spr_addr oka,lr - set_fcc 0x9 1 - fcbugelr fcc1,0,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fcbugelr fcc2,0,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fcbugelr fcc3,0,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fcbugelr fcc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fcbugelr fcc1,0,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fcbugelr fcc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fcbugelr fcc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbugelr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr oki,lr - set_fcc 0x1 1 - fcbugelr fcc1,1,1 - fail -oki: - set_spr_immed 1,lcr - set_spr_addr okj,lr - set_fcc 0x2 2 - fcbugelr fcc2,1,2 - fail -okj: - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_fcc 0x3 3 - fcbugelr fcc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x4 0 - fcbugelr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_fcc 0x5 1 - fcbugelr fcc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_fcc 0x6 2 - fcbugelr fcc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_fcc 0x7 3 - fcbugelr fcc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr okp,lr - set_fcc 0x8 0 - fcbugelr fcc0,1,0 - fail -okp: - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_fcc 0x9 1 - fcbugelr fcc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_fcc 0xa 2 - fcbugelr fcc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_fcc 0xb 3 - fcbugelr fcc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_fcc 0xc 0 - fcbugelr fcc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_fcc 0xd 1 - fcbugelr fcc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_fcc 0xe 2 - fcbugelr fcc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_fcc 0xf 3 - fcbugelr fcc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - - set_fcc 0x0 0 - fcbugelr fcc0,1,0 - set_fcc 0x1 1 - fcbugelr fcc1,1,1 - set_fcc 0x2 2 - fcbugelr fcc2,1,2 - set_fcc 0x3 3 - fcbugelr fcc3,1,3 - set_fcc 0x4 0 - fcbugelr fcc0,1,0 - set_fcc 0x5 1 - fcbugelr fcc1,1,1 - set_fcc 0x6 2 - fcbugelr fcc2,1,2 - set_fcc 0x7 3 - fcbugelr fcc3,1,3 - set_fcc 0x8 0 - fcbugelr fcc0,1,0 - set_fcc 0x9 1 - fcbugelr fcc1,1,1 - set_fcc 0xa 2 - fcbugelr fcc2,1,2 - set_fcc 0xb 3 - fcbugelr fcc3,1,3 - set_fcc 0xc 0 - fcbugelr fcc0,1,0 - set_fcc 0xd 1 - fcbugelr fcc1,1,1 - set_fcc 0xe 2 - fcbugelr fcc2,1,2 - set_fcc 0xf 3 - fcbugelr fcc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcbugelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcbugelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcbugelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcbugelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcbugelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcbugelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcbugelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcbugelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcbugelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcbugelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcbugelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcbugelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcbugelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcbugelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcbugelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcbugelr fcc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fcbuglr.cgs b/sim/testsuite/sim/frv/fcbuglr.cgs deleted file mode 100644 index d9470a81a89..00000000000 --- a/sim/testsuite/sim/frv/fcbuglr.cgs +++ /dev/null @@ -1,270 +0,0 @@ -# frv testcase for fcbuglr $FCCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fcbuglr -fcbuglr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbuglr fcc0,0,0 - - set_spr_addr ok2,lr - set_fcc 0x1 1 - fcbuglr fcc1,0,1 - fail -ok2: - set_spr_addr ok3,lr - set_fcc 0x2 2 - fcbuglr fcc2,0,2 - fail -ok3: - set_spr_addr ok4,lr - set_fcc 0x3 3 - fcbuglr fcc3,0,3 - fail -ok4: - set_spr_addr bad,lr - set_fcc 0x4 0 - fcbuglr fcc0,0,0 - - set_spr_addr ok6,lr - set_fcc 0x5 1 - fcbuglr fcc1,0,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fcbuglr fcc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fcbuglr fcc3,0,3 - fail -ok8: - set_spr_addr bad,lr - set_fcc 0x8 0 - fcbuglr fcc0,0,0 - - set_spr_addr oka,lr - set_fcc 0x9 1 - fcbuglr fcc1,0,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fcbuglr fcc2,0,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fcbuglr fcc3,0,3 - fail -okc: - set_spr_addr bad,lr - set_fcc 0xc 0 - fcbuglr fcc0,0,0 - - set_spr_addr oke,lr - set_fcc 0xd 1 - fcbuglr fcc1,0,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fcbuglr fcc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fcbuglr fcc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbuglr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr oki,lr - set_fcc 0x1 1 - fcbuglr fcc1,1,1 - fail -oki: - set_spr_immed 1,lcr - set_spr_addr okj,lr - set_fcc 0x2 2 - fcbuglr fcc2,1,2 - fail -okj: - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_fcc 0x3 3 - fcbuglr fcc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x4 0 - fcbuglr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_fcc 0x5 1 - fcbuglr fcc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_fcc 0x6 2 - fcbuglr fcc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_fcc 0x7 3 - fcbuglr fcc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x8 0 - fcbuglr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_fcc 0x9 1 - fcbuglr fcc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_fcc 0xa 2 - fcbuglr fcc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_fcc 0xb 3 - fcbuglr fcc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0xc 0 - fcbuglr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_fcc 0xd 1 - fcbuglr fcc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_fcc 0xe 2 - fcbuglr fcc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_fcc 0xf 3 - fcbuglr fcc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - - set_fcc 0x0 0 - fcbuglr fcc0,1,0 - set_fcc 0x1 1 - fcbuglr fcc1,1,1 - set_fcc 0x2 2 - fcbuglr fcc2,1,2 - set_fcc 0x3 3 - fcbuglr fcc3,1,3 - set_fcc 0x4 0 - fcbuglr fcc0,1,0 - set_fcc 0x5 1 - fcbuglr fcc1,1,1 - set_fcc 0x6 2 - fcbuglr fcc2,1,2 - set_fcc 0x7 3 - fcbuglr fcc3,1,3 - set_fcc 0x8 0 - fcbuglr fcc0,1,0 - set_fcc 0x9 1 - fcbuglr fcc1,1,1 - set_fcc 0xa 2 - fcbuglr fcc2,1,2 - set_fcc 0xb 3 - fcbuglr fcc3,1,3 - set_fcc 0xc 0 - fcbuglr fcc0,1,0 - set_fcc 0xd 1 - fcbuglr fcc1,1,1 - set_fcc 0xe 2 - fcbuglr fcc2,1,2 - set_fcc 0xf 3 - fcbuglr fcc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcbuglr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcbuglr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcbuglr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcbuglr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcbuglr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcbuglr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcbuglr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcbuglr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcbuglr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcbuglr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcbuglr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcbuglr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcbuglr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcbuglr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcbuglr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcbuglr fcc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fcbulelr.cgs b/sim/testsuite/sim/frv/fcbulelr.cgs deleted file mode 100644 index 3f1da04a79b..00000000000 --- a/sim/testsuite/sim/frv/fcbulelr.cgs +++ /dev/null @@ -1,274 +0,0 @@ -# frv testcase for fcbulelr $FCCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fcbulelr -fcbulelr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbulelr fcc0,0,0 - - set_spr_addr ok2,lr - set_fcc 0x1 1 - fcbulelr fcc1,0,1 - fail -ok2: - set_spr_addr bad,lr - set_fcc 0x2 2 - fcbulelr fcc2,0,2 - - set_spr_addr ok4,lr - set_fcc 0x3 3 - fcbulelr fcc3,0,3 - fail -ok4: - set_spr_addr ok5,lr - set_fcc 0x4 0 - fcbulelr fcc0,0,0 - fail -ok5: - set_spr_addr ok6,lr - set_fcc 0x5 1 - fcbulelr fcc1,0,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fcbulelr fcc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fcbulelr fcc3,0,3 - fail -ok8: - set_spr_addr ok9,lr - set_fcc 0x8 0 - fcbulelr fcc0,0,0 - fail -ok9: - set_spr_addr oka,lr - set_fcc 0x9 1 - fcbulelr fcc1,0,1 - fail -oka: - set_spr_addr okb,lr - set_fcc 0xa 2 - fcbulelr fcc2,0,2 - fail -okb: - set_spr_addr okc,lr - set_fcc 0xb 3 - fcbulelr fcc3,0,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fcbulelr fcc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fcbulelr fcc1,0,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fcbulelr fcc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fcbulelr fcc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbulelr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr oki,lr - set_fcc 0x1 1 - fcbulelr fcc1,1,1 - fail -oki: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x2 2 - fcbulelr fcc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_fcc 0x3 3 - fcbulelr fcc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr okl,lr - set_fcc 0x4 0 - fcbulelr fcc0,1,0 - fail -okl: - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_fcc 0x5 1 - fcbulelr fcc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_fcc 0x6 2 - fcbulelr fcc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_fcc 0x7 3 - fcbulelr fcc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr okp,lr - set_fcc 0x8 0 - fcbulelr fcc0,1,0 - fail -okp: - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_fcc 0x9 1 - fcbulelr fcc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr okr,lr - set_fcc 0xa 2 - fcbulelr fcc2,1,2 - fail -okr: - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_fcc 0xb 3 - fcbulelr fcc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_fcc 0xc 0 - fcbulelr fcc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_fcc 0xd 1 - fcbulelr fcc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_fcc 0xe 2 - fcbulelr fcc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_fcc 0xf 3 - fcbulelr fcc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - - set_fcc 0x0 0 - fcbulelr fcc0,1,0 - set_fcc 0x1 1 - fcbulelr fcc1,1,1 - set_fcc 0x2 2 - fcbulelr fcc2,1,2 - set_fcc 0x3 3 - fcbulelr fcc3,1,3 - set_fcc 0x4 0 - fcbulelr fcc0,1,0 - set_fcc 0x5 1 - fcbulelr fcc1,1,1 - set_fcc 0x6 2 - fcbulelr fcc2,1,2 - set_fcc 0x7 3 - fcbulelr fcc3,1,3 - set_fcc 0x8 0 - fcbulelr fcc0,1,0 - set_fcc 0x9 1 - fcbulelr fcc1,1,1 - set_fcc 0xa 2 - fcbulelr fcc2,1,2 - set_fcc 0xb 3 - fcbulelr fcc3,1,3 - set_fcc 0xc 0 - fcbulelr fcc0,1,0 - set_fcc 0xd 1 - fcbulelr fcc1,1,1 - set_fcc 0xe 2 - fcbulelr fcc2,1,2 - set_fcc 0xf 3 - fcbulelr fcc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcbulelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcbulelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcbulelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcbulelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcbulelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcbulelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcbulelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcbulelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcbulelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcbulelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcbulelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcbulelr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcbulelr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcbulelr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcbulelr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcbulelr fcc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fcbullr.cgs b/sim/testsuite/sim/frv/fcbullr.cgs deleted file mode 100644 index 1a87dde129e..00000000000 --- a/sim/testsuite/sim/frv/fcbullr.cgs +++ /dev/null @@ -1,270 +0,0 @@ -# frv testcase for fcbullr $FCCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fcbullr -fcbullr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbullr fcc0,0,0 - - set_spr_addr ok2,lr - set_fcc 0x1 1 - fcbullr fcc1,0,1 - fail -ok2: - set_spr_addr bad,lr - set_fcc 0x2 2 - fcbullr fcc2,0,2 - - set_spr_addr ok4,lr - set_fcc 0x3 3 - fcbullr fcc3,0,3 - fail -ok4: - set_spr_addr ok5,lr - set_fcc 0x4 0 - fcbullr fcc0,0,0 - fail -ok5: - set_spr_addr ok6,lr - set_fcc 0x5 1 - fcbullr fcc1,0,1 - fail -ok6: - set_spr_addr ok7,lr - set_fcc 0x6 2 - fcbullr fcc2,0,2 - fail -ok7: - set_spr_addr ok8,lr - set_fcc 0x7 3 - fcbullr fcc3,0,3 - fail -ok8: - set_spr_addr bad,lr - set_fcc 0x8 0 - fcbullr fcc0,0,0 - - set_spr_addr oka,lr - set_fcc 0x9 1 - fcbullr fcc1,0,1 - fail -oka: - set_spr_addr bad,lr - set_fcc 0xa 2 - fcbullr fcc2,0,2 - - set_spr_addr okc,lr - set_fcc 0xb 3 - fcbullr fcc3,0,3 - fail -okc: - set_spr_addr okd,lr - set_fcc 0xc 0 - fcbullr fcc0,0,0 - fail -okd: - set_spr_addr oke,lr - set_fcc 0xd 1 - fcbullr fcc1,0,1 - fail -oke: - set_spr_addr okf,lr - set_fcc 0xe 2 - fcbullr fcc2,0,2 - fail -okf: - set_spr_addr okg,lr - set_fcc 0xf 3 - fcbullr fcc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbullr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr oki,lr - set_fcc 0x1 1 - fcbullr fcc1,1,1 - fail -oki: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x2 2 - fcbullr fcc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_fcc 0x3 3 - fcbullr fcc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr okl,lr - set_fcc 0x4 0 - fcbullr fcc0,1,0 - fail -okl: - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_fcc 0x5 1 - fcbullr fcc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr okn,lr - set_fcc 0x6 2 - fcbullr fcc2,1,2 - fail -okn: - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_fcc 0x7 3 - fcbullr fcc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x8 0 - fcbullr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_fcc 0x9 1 - fcbullr fcc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0xa 2 - fcbullr fcc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_fcc 0xb 3 - fcbullr fcc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr okt,lr - set_fcc 0xc 0 - fcbullr fcc0,1,0 - fail -okt: - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_fcc 0xd 1 - fcbullr fcc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr okv,lr - set_fcc 0xe 2 - fcbullr fcc2,1,2 - fail -okv: - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_fcc 0xf 3 - fcbullr fcc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - - set_fcc 0x0 0 - fcbullr fcc0,1,0 - set_fcc 0x1 1 - fcbullr fcc1,1,1 - set_fcc 0x2 2 - fcbullr fcc2,1,2 - set_fcc 0x3 3 - fcbullr fcc3,1,3 - set_fcc 0x4 0 - fcbullr fcc0,1,0 - set_fcc 0x5 1 - fcbullr fcc1,1,1 - set_fcc 0x6 2 - fcbullr fcc2,1,2 - set_fcc 0x7 3 - fcbullr fcc3,1,3 - set_fcc 0x8 0 - fcbullr fcc0,1,0 - set_fcc 0x9 1 - fcbullr fcc1,1,1 - set_fcc 0xa 2 - fcbullr fcc2,1,2 - set_fcc 0xb 3 - fcbullr fcc3,1,3 - set_fcc 0xc 0 - fcbullr fcc0,1,0 - set_fcc 0xd 1 - fcbullr fcc1,1,1 - set_fcc 0xe 2 - fcbullr fcc2,1,2 - set_fcc 0xf 3 - fcbullr fcc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcbullr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcbullr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcbullr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcbullr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcbullr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcbullr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcbullr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcbullr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcbullr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcbullr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcbullr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcbullr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcbullr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcbullr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcbullr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcbullr fcc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fcbulr.cgs b/sim/testsuite/sim/frv/fcbulr.cgs deleted file mode 100644 index c81dff3e13c..00000000000 --- a/sim/testsuite/sim/frv/fcbulr.cgs +++ /dev/null @@ -1,262 +0,0 @@ -# frv testcase for fcbulr $FCCi,$ccond,$hint -# mach: all - - .include "testutils.inc" - - start - - .global fcbulr -fcbulr: - ; ccond is true - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbulr fcc0,0,0 - - set_spr_addr ok2,lr - set_fcc 0x1 1 - fcbulr fcc1,0,1 - fail -ok2: - set_spr_addr bad,lr - set_fcc 0x2 2 - fcbulr fcc2,0,2 - - set_spr_addr ok4,lr - set_fcc 0x3 3 - fcbulr fcc3,0,3 - fail -ok4: - set_spr_addr bad,lr - set_fcc 0x4 0 - fcbulr fcc0,0,0 - - set_spr_addr ok6,lr - set_fcc 0x5 1 - fcbulr fcc1,0,1 - fail -ok6: - set_spr_addr bad,lr - set_fcc 0x6 2 - fcbulr fcc2,0,2 - - set_spr_addr ok8,lr - set_fcc 0x7 3 - fcbulr fcc3,0,3 - fail -ok8: - set_spr_addr bad,lr - set_fcc 0x8 0 - fcbulr fcc0,0,0 - - set_spr_addr oka,lr - set_fcc 0x9 1 - fcbulr fcc1,0,1 - fail -oka: - set_spr_addr bad,lr - set_fcc 0xa 2 - fcbulr fcc2,0,2 - - set_spr_addr okc,lr - set_fcc 0xb 3 - fcbulr fcc3,0,3 - fail -okc: - set_spr_addr bad,lr - set_fcc 0xc 0 - fcbulr fcc0,0,0 - - set_spr_addr oke,lr - set_fcc 0xd 1 - fcbulr fcc1,0,1 - fail -oke: - set_spr_addr bad,lr - set_fcc 0xe 2 - fcbulr fcc2,0,2 - - set_spr_addr okg,lr - set_fcc 0xf 3 - fcbulr fcc3,0,3 - fail -okg: - - ; ccond is true - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x0 0 - fcbulr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr oki,lr - set_fcc 0x1 1 - fcbulr fcc1,1,1 - fail -oki: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x2 2 - fcbulr fcc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr okk,lr - set_fcc 0x3 3 - fcbulr fcc3,1,3 - fail -okk: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x4 0 - fcbulr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr okm,lr - set_fcc 0x5 1 - fcbulr fcc1,1,1 - fail -okm: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x6 2 - fcbulr fcc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr oko,lr - set_fcc 0x7 3 - fcbulr fcc3,1,3 - fail -oko: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0x8 0 - fcbulr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr okq,lr - set_fcc 0x9 1 - fcbulr fcc1,1,1 - fail -okq: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0xa 2 - fcbulr fcc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr oks,lr - set_fcc 0xb 3 - fcbulr fcc3,1,3 - fail -oks: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0xc 0 - fcbulr fcc0,1,0 - - set_spr_immed 1,lcr - set_spr_addr oku,lr - set_fcc 0xd 1 - fcbulr fcc1,1,1 - fail -oku: - set_spr_immed 1,lcr - set_spr_addr bad,lr - set_fcc 0xe 2 - fcbulr fcc2,1,2 - - set_spr_immed 1,lcr - set_spr_addr okw,lr - set_fcc 0xf 3 - fcbulr fcc3,1,3 - fail -okw: - ; ccond is false - set_spr_immed 128,lcr - - set_fcc 0x0 0 - fcbulr fcc0,1,0 - set_fcc 0x1 1 - fcbulr fcc1,1,1 - set_fcc 0x2 2 - fcbulr fcc2,1,2 - set_fcc 0x3 3 - fcbulr fcc3,1,3 - set_fcc 0x4 0 - fcbulr fcc0,1,0 - set_fcc 0x5 1 - fcbulr fcc1,1,1 - set_fcc 0x6 2 - fcbulr fcc2,1,2 - set_fcc 0x7 3 - fcbulr fcc3,1,3 - set_fcc 0x8 0 - fcbulr fcc0,1,0 - set_fcc 0x9 1 - fcbulr fcc1,1,1 - set_fcc 0xa 2 - fcbulr fcc2,1,2 - set_fcc 0xb 3 - fcbulr fcc3,1,3 - set_fcc 0xc 0 - fcbulr fcc0,1,0 - set_fcc 0xd 1 - fcbulr fcc1,1,1 - set_fcc 0xe 2 - fcbulr fcc2,1,2 - set_fcc 0xf 3 - fcbulr fcc3,1,3 - - ; ccond is false - set_spr_immed 1,lcr - set_fcc 0x0 0 - fcbulr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x1 1 - fcbulr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x2 2 - fcbulr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x3 3 - fcbulr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x4 0 - fcbulr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x5 1 - fcbulr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0x6 2 - fcbulr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0x7 3 - fcbulr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0x8 0 - fcbulr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0x9 1 - fcbulr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xa 2 - fcbulr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xb 3 - fcbulr fcc3,0,3 - set_spr_immed 1,lcr - set_fcc 0xc 0 - fcbulr fcc0,0,0 - set_spr_immed 1,lcr - set_fcc 0xd 1 - fcbulr fcc1,0,1 - set_spr_immed 1,lcr - set_fcc 0xe 2 - fcbulr fcc2,0,2 - set_spr_immed 1,lcr - set_fcc 0xf 3 - fcbulr fcc3,0,3 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fckeq.cgs b/sim/testsuite/sim/frv/fckeq.cgs deleted file mode 100644 index 572a86d2438..00000000000 --- a/sim/testsuite/sim/frv/fckeq.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fckeq $FCCi,$CCj_float -# mach: all - - .include "testutils.inc" - - start - - .global fckeq -fckeq: - set_spr_immed 0x1b1b,cccr - set_fcc 0x0 0 - fckeq fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x1 0 - fckeq fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x2 0 - fckeq fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x3 0 - fckeq fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x4 0 - fckeq fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x5 0 - fckeq fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x6 0 - fckeq fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x7 0 - fckeq fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x8 0 - fckeq fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x9 0 - fckeq fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xa 0 - fckeq fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xb 0 - fckeq fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xc 0 - fckeq fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xd 0 - fckeq fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xe 0 - fckeq fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xf 0 - fckeq fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/fckge.cgs b/sim/testsuite/sim/frv/fckge.cgs deleted file mode 100644 index 91a1efdfa9e..00000000000 --- a/sim/testsuite/sim/frv/fckge.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fckge $FCCi,$CCj_float -# mach: all - - .include "testutils.inc" - - start - - .global fckge -fckge: - set_spr_immed 0x1b1b,cccr - set_fcc 0x0 0 - fckge fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x1 0 - fckge fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x2 0 - fckge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x3 0 - fckge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x4 0 - fckge fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x5 0 - fckge fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x6 0 - fckge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x7 0 - fckge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x8 0 - fckge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x9 0 - fckge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xa 0 - fckge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xb 0 - fckge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xc 0 - fckge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xd 0 - fckge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xe 0 - fckge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xf 0 - fckge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/fckgt.cgs b/sim/testsuite/sim/frv/fckgt.cgs deleted file mode 100644 index 06715f96d0d..00000000000 --- a/sim/testsuite/sim/frv/fckgt.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fckgt $FCCi,$CCj_float -# mach: all - - .include "testutils.inc" - - start - - .global fckgt -fckgt: - set_spr_immed 0x1b1b,cccr - set_fcc 0x0 0 - fckgt fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x1 0 - fckgt fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x2 0 - fckgt fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x3 0 - fckgt fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x4 0 - fckgt fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x5 0 - fckgt fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x6 0 - fckgt fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x7 0 - fckgt fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x8 0 - fckgt fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x9 0 - fckgt fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xa 0 - fckgt fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xb 0 - fckgt fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xc 0 - fckgt fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xd 0 - fckgt fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xe 0 - fckgt fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xf 0 - fckgt fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/fckle.cgs b/sim/testsuite/sim/frv/fckle.cgs deleted file mode 100644 index 7d5e6dae951..00000000000 --- a/sim/testsuite/sim/frv/fckle.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fckle $FCCi,$CCj_float -# mach: all - - .include "testutils.inc" - - start - - .global fckle -fckle: - set_spr_immed 0x1b1b,cccr - set_fcc 0x0 0 - fckle fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x1 0 - fckle fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x2 0 - fckle fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x3 0 - fckle fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x4 0 - fckle fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x5 0 - fckle fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x6 0 - fckle fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x7 0 - fckle fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x8 0 - fckle fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x9 0 - fckle fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xa 0 - fckle fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xb 0 - fckle fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xc 0 - fckle fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xd 0 - fckle fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xe 0 - fckle fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xf 0 - fckle fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/fcklg.cgs b/sim/testsuite/sim/frv/fcklg.cgs deleted file mode 100644 index f8df5a1152c..00000000000 --- a/sim/testsuite/sim/frv/fcklg.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fcklg $FCCi,$CCj_float -# mach: all - - .include "testutils.inc" - - start - - .global fcklg -fcklg: - set_spr_immed 0x1b1b,cccr - set_fcc 0x0 0 - fcklg fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x1 0 - fcklg fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x2 0 - fcklg fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x3 0 - fcklg fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x4 0 - fcklg fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x5 0 - fcklg fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x6 0 - fcklg fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x7 0 - fcklg fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x8 0 - fcklg fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x9 0 - fcklg fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xa 0 - fcklg fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xb 0 - fcklg fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xc 0 - fcklg fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xd 0 - fcklg fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xe 0 - fcklg fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xf 0 - fcklg fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/fcklt.cgs b/sim/testsuite/sim/frv/fcklt.cgs deleted file mode 100644 index 14e53711879..00000000000 --- a/sim/testsuite/sim/frv/fcklt.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fcklt $FCCi,$CCj_float -# mach: all - - .include "testutils.inc" - - start - - .global fcklt -fcklt: - set_spr_immed 0x1b1b,cccr - set_fcc 0x0 0 - fcklt fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x1 0 - fcklt fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x2 0 - fcklt fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x3 0 - fcklt fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x4 0 - fcklt fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x5 0 - fcklt fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x6 0 - fcklt fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x7 0 - fcklt fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x8 0 - fcklt fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x9 0 - fcklt fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xa 0 - fcklt fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xb 0 - fcklt fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xc 0 - fcklt fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xd 0 - fcklt fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xe 0 - fcklt fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xf 0 - fcklt fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/fckne.cgs b/sim/testsuite/sim/frv/fckne.cgs deleted file mode 100644 index 774f8379bfc..00000000000 --- a/sim/testsuite/sim/frv/fckne.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fckne $FCCi,$CCj_float -# mach: all - - .include "testutils.inc" - - start - - .global fckne -fckne: - set_spr_immed 0x1b1b,cccr - set_fcc 0x0 0 - fckne fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x1 0 - fckne fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x2 0 - fckne fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x3 0 - fckne fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x4 0 - fckne fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x5 0 - fckne fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x6 0 - fckne fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x7 0 - fckne fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x8 0 - fckne fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x9 0 - fckne fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xa 0 - fckne fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xb 0 - fckne fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xc 0 - fckne fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xd 0 - fckne fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xe 0 - fckne fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xf 0 - fckne fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/fckno.cgs b/sim/testsuite/sim/frv/fckno.cgs deleted file mode 100644 index 08513a25198..00000000000 --- a/sim/testsuite/sim/frv/fckno.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fckno $CCj_float -# mach: all - - .include "testutils.inc" - - start - - .global fckno -fckno: - set_spr_immed 0x1b1b,cccr - set_fcc 0x0 0 - fckno cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x1 0 - fckno cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x2 0 - fckno cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x3 0 - fckno cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x4 0 - fckno cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x5 0 - fckno cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x6 0 - fckno cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x7 0 - fckno cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x8 0 - fckno cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x9 0 - fckno cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xa 0 - fckno cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xb 0 - fckno cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xc 0 - fckno cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xd 0 - fckno cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xe 0 - fckno cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xf 0 - fckno cc3 - test_spr_immed 0x1b9b,cccr - - pass diff --git a/sim/testsuite/sim/frv/fcko.cgs b/sim/testsuite/sim/frv/fcko.cgs deleted file mode 100644 index 06d56407448..00000000000 --- a/sim/testsuite/sim/frv/fcko.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fcko $FCCi,$CCj_float -# mach: all - - .include "testutils.inc" - - start - - .global fcko -fcko: - set_spr_immed 0x1b1b,cccr - set_fcc 0x0 0 - fcko fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x1 0 - fcko fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x2 0 - fcko fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x3 0 - fcko fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x4 0 - fcko fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x5 0 - fcko fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x6 0 - fcko fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x7 0 - fcko fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x8 0 - fcko fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x9 0 - fcko fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xa 0 - fcko fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xb 0 - fcko fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xc 0 - fcko fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xd 0 - fcko fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xe 0 - fcko fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xf 0 - fcko fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/fckra.cgs b/sim/testsuite/sim/frv/fckra.cgs deleted file mode 100644 index a74b9fc32e6..00000000000 --- a/sim/testsuite/sim/frv/fckra.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fckra $CCj_float -# mach: all - - .include "testutils.inc" - - start - - .global fckra -fckra: - set_spr_immed 0x1b1b,cccr - set_fcc 0x0 0 - fckra cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x1 0 - fckra cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x2 0 - fckra cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x3 0 - fckra cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x4 0 - fckra cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x5 0 - fckra cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x6 0 - fckra cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x7 0 - fckra cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x8 0 - fckra cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x9 0 - fckra cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xa 0 - fckra cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xb 0 - fckra cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xc 0 - fckra cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xd 0 - fckra cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xe 0 - fckra cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xf 0 - fckra cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/fcku.cgs b/sim/testsuite/sim/frv/fcku.cgs deleted file mode 100644 index 9aaa635eef7..00000000000 --- a/sim/testsuite/sim/frv/fcku.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fcku $FCCi,$CCj_float -# mach: all - - .include "testutils.inc" - - start - - .global fcku -fcku: - set_spr_immed 0x1b1b,cccr - set_fcc 0x0 0 - fcku fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x1 0 - fcku fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x2 0 - fcku fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x3 0 - fcku fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x4 0 - fcku fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x5 0 - fcku fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x6 0 - fcku fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x7 0 - fcku fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x8 0 - fcku fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x9 0 - fcku fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xa 0 - fcku fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xb 0 - fcku fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xc 0 - fcku fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xd 0 - fcku fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xe 0 - fcku fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xf 0 - fcku fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/fckue.cgs b/sim/testsuite/sim/frv/fckue.cgs deleted file mode 100644 index 0bd7696171d..00000000000 --- a/sim/testsuite/sim/frv/fckue.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fckue $FCCi,$CCj_float -# mach: all - - .include "testutils.inc" - - start - - .global fckue -fckue: - set_spr_immed 0x1b1b,cccr - set_fcc 0x0 0 - fckue fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x1 0 - fckue fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x2 0 - fckue fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x3 0 - fckue fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x4 0 - fckue fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x5 0 - fckue fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x6 0 - fckue fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x7 0 - fckue fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x8 0 - fckue fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x9 0 - fckue fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xa 0 - fckue fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xb 0 - fckue fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xc 0 - fckue fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xd 0 - fckue fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xe 0 - fckue fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xf 0 - fckue fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/fckug.cgs b/sim/testsuite/sim/frv/fckug.cgs deleted file mode 100644 index f810335eda4..00000000000 --- a/sim/testsuite/sim/frv/fckug.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fckug $FCCi,$CCj_float -# mach: all - - .include "testutils.inc" - - start - - .global fckug -fckug: - set_spr_immed 0x1b1b,cccr - set_fcc 0x0 0 - fckug fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x1 0 - fckug fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x2 0 - fckug fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x3 0 - fckug fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x4 0 - fckug fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x5 0 - fckug fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x6 0 - fckug fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x7 0 - fckug fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x8 0 - fckug fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x9 0 - fckug fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xa 0 - fckug fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xb 0 - fckug fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xc 0 - fckug fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xd 0 - fckug fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xe 0 - fckug fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xf 0 - fckug fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/fckuge.cgs b/sim/testsuite/sim/frv/fckuge.cgs deleted file mode 100644 index d8126389f77..00000000000 --- a/sim/testsuite/sim/frv/fckuge.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fckuge $FCCi,$CCj_float -# mach: all - - .include "testutils.inc" - - start - - .global fckuge -fckuge: - set_spr_immed 0x1b1b,cccr - set_fcc 0x0 0 - fckuge fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x1 0 - fckuge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x2 0 - fckuge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x3 0 - fckuge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x4 0 - fckuge fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x5 0 - fckuge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x6 0 - fckuge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x7 0 - fckuge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x8 0 - fckuge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x9 0 - fckuge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xa 0 - fckuge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xb 0 - fckuge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xc 0 - fckuge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xd 0 - fckuge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xe 0 - fckuge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xf 0 - fckuge fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/fckul.cgs b/sim/testsuite/sim/frv/fckul.cgs deleted file mode 100644 index 2d30d924186..00000000000 --- a/sim/testsuite/sim/frv/fckul.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fckul $FCCi,$CCj_float -# mach: all - - .include "testutils.inc" - - start - - .global fckul -fckul: - set_spr_immed 0x1b1b,cccr - set_fcc 0x0 0 - fckul fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x1 0 - fckul fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x2 0 - fckul fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x3 0 - fckul fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x4 0 - fckul fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x5 0 - fckul fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x6 0 - fckul fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x7 0 - fckul fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x8 0 - fckul fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x9 0 - fckul fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xa 0 - fckul fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xb 0 - fckul fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xc 0 - fckul fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xd 0 - fckul fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xe 0 - fckul fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xf 0 - fckul fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/fckule.cgs b/sim/testsuite/sim/frv/fckule.cgs deleted file mode 100644 index 9830a66a8f5..00000000000 --- a/sim/testsuite/sim/frv/fckule.cgs +++ /dev/null @@ -1,90 +0,0 @@ -# frv testcase for fckule $FCCi,$CCj_float -# mach: all - - .include "testutils.inc" - - start - - .global fckule -fckule: - set_spr_immed 0x1b1b,cccr - set_fcc 0x0 0 - fckule fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x1 0 - fckule fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x2 0 - fckule fcc0,cc3 - test_spr_immed 0x1b9b,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x3 0 - fckule fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x4 0 - fckule fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x5 0 - fckule fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x6 0 - fckule fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x7 0 - fckule fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x8 0 - fckule fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0x9 0 - fckule fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xa 0 - fckule fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xb 0 - fckule fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xc 0 - fckule fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xd 0 - fckule fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xe 0 - fckule fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - set_spr_immed 0x1b1b,cccr - set_fcc 0xf 0 - fckule fcc0,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/fcmpd.cgs b/sim/testsuite/sim/frv/fcmpd.cgs deleted file mode 100644 index 5c862664845..00000000000 --- a/sim/testsuite/sim/frv/fcmpd.cgs +++ /dev/null @@ -1,601 +0,0 @@ -# frv testcase for fcmpd $GRi,$GRj,$FCCi_2 -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - double_constants - start - load_double_constants - - .global fcmpd -fcmpd: - set_fcc 0x7,0 ; Set mask opposite of expected - fcmpd fr0,fr0,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr0,fr4,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr0,fr8,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr0,fr12,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr0,fr16,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr0,fr20,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr0,fr24,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr0,fr28,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr0,fr32,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr0,fr36,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr0,fr40,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr0,fr44,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr0,fr48,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr0,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr0,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr0,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr4,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmpd fr4,fr4,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr4,fr8,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr4,fr12,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr4,fr16,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr4,fr20,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr4,fr24,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr4,fr28,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr4,fr32,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr4,fr36,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr4,fr40,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr4,fr44,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr4,fr48,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr4,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr4,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr4,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr8,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr8,fr4,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmpd fr8,fr8,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr8,fr12,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr8,fr16,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr8,fr20,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr8,fr24,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr8,fr28,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr8,fr32,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr8,fr36,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr8,fr40,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr8,fr44,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr8,fr48,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr8,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr8,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr8,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr12,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr12,fr4,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr12,fr8,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmpd fr12,fr12,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr12,fr16,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr12,fr20,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr12,fr24,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr12,fr28,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr12,fr32,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr12,fr36,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr12,fr40,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr12,fr44,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr12,fr48,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr12,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr12,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr12,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr16,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr16,fr4,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr16,fr8,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr16,fr12,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmpd fr16,fr16,fcc0 - test_fcc 0x8,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmpd fr16,fr20,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr16,fr24,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr16,fr28,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr16,fr32,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr16,fr36,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr16,fr40,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr16,fr44,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr16,fr48,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr16,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr16,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr16,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr20,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr20,fr4,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr20,fr8,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr20,fr12,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmpd fr20,fr16,fcc0 - test_fcc 0x8,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmpd fr20,fr20,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr20,fr24,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr20,fr28,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr20,fr32,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr20,fr36,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr20,fr40,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr20,fr44,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr20,fr48,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr20,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr20,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr20,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr24,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr24,fr4,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr24,fr8,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr24,fr12,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr24,fr16,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr24,fr20,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmpd fr24,fr24,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr24,fr28,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr24,fr32,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr24,fr36,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr24,fr40,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr24,fr44,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr24,fr48,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr24,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr24,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr24,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr28,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr28,fr4,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr28,fr8,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr28,fr12,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr28,fr16,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr28,fr20,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr28,fr24,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmpd fr28,fr28,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr28,fr32,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr28,fr36,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr28,fr40,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr28,fr44,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr28,fr48,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr28,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr28,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr28,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr48,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr48,fr4,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr48,fr8,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr48,fr12,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr48,fr16,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr48,fr20,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr48,fr24,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr48,fr28,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr48,fr32,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr48,fr36,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr48,fr40,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr48,fr44,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmpd fr48,fr48,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmpd fr48,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr48,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr48,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr52,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr52,fr4,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr52,fr8,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr52,fr12,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr52,fr16,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr52,fr20,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr52,fr24,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr52,fr28,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr52,fr32,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr52,fr36,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr52,fr40,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr52,fr44,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmpd fr52,fr48,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmpd fr52,fr52,fcc0 - test_fcc 0x8,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr52,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr52,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr56,fr0,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr56,fr4,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr56,fr8,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr56,fr12,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr56,fr16,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr56,fr20,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr56,fr24,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr56,fr28,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr56,fr32,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr56,fr36,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr56,fr40,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr56,fr44,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr56,fr48,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr56,fr52,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr56,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr56,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr60,fr0,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr60,fr4,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr60,fr8,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr60,fr12,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr60,fr16,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr60,fr20,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr60,fr24,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr60,fr28,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr60,fr32,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr60,fr36,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr60,fr40,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr60,fr44,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr60,fr48,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr60,fr52,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr60,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmpd fr60,fr60,fcc0 - test_fcc 0x1,0 - - pass diff --git a/sim/testsuite/sim/frv/fcmps.cgs b/sim/testsuite/sim/frv/fcmps.cgs deleted file mode 100644 index ea1ccc05f29..00000000000 --- a/sim/testsuite/sim/frv/fcmps.cgs +++ /dev/null @@ -1,600 +0,0 @@ -# frv testcase for fcmps $GRi,$GRj,$FCCi_2 -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fcmps -fcmps: - set_fcc 0x7,0 ; Set mask opposite of expected - fcmps fr0,fr0,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr0,fr4,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr0,fr8,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr0,fr12,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr0,fr16,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr0,fr20,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr0,fr24,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr0,fr28,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr0,fr32,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr0,fr36,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr0,fr40,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr0,fr44,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr0,fr48,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr0,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr0,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr0,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr4,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmps fr4,fr4,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr4,fr8,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr4,fr12,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr4,fr16,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr4,fr20,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr4,fr24,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr4,fr28,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr4,fr32,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr4,fr36,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr4,fr40,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr4,fr44,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr4,fr48,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr4,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr4,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr4,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr8,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr8,fr4,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmps fr8,fr8,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr8,fr12,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr8,fr16,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr8,fr20,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr8,fr24,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr8,fr28,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr8,fr32,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr8,fr36,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr8,fr40,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr8,fr44,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr8,fr48,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr8,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr8,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr8,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr12,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr12,fr4,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr12,fr8,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmps fr12,fr12,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr12,fr16,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr12,fr20,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr12,fr24,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr12,fr28,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr12,fr32,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr12,fr36,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr12,fr40,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr12,fr44,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr12,fr48,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr12,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr12,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr12,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr16,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr16,fr4,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr16,fr8,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr16,fr12,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmps fr16,fr16,fcc0 - test_fcc 0x8,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmps fr16,fr20,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr16,fr24,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr16,fr28,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr16,fr32,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr16,fr36,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr16,fr40,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr16,fr44,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr16,fr48,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr16,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr16,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr16,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr20,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr20,fr4,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr20,fr8,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr20,fr12,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmps fr20,fr16,fcc0 - test_fcc 0x8,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmps fr20,fr20,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr20,fr24,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr20,fr28,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr20,fr32,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr20,fr36,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr20,fr40,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr20,fr44,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr20,fr48,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr20,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr20,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr20,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr24,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr24,fr4,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr24,fr8,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr24,fr12,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr24,fr16,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr24,fr20,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmps fr24,fr24,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr24,fr28,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr24,fr32,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr24,fr36,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr24,fr40,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr24,fr44,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr24,fr48,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr24,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr24,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr24,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr28,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr28,fr4,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr28,fr8,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr28,fr12,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr28,fr16,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr28,fr20,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr28,fr24,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmps fr28,fr28,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr28,fr32,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr28,fr36,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr28,fr40,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr28,fr44,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr28,fr48,fcc0 - test_fcc 0x4,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr28,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr28,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr28,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr48,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr48,fr4,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr48,fr8,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr48,fr12,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr48,fr16,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr48,fr20,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr48,fr24,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr48,fr28,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr48,fr32,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr48,fr36,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr48,fr40,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr48,fr44,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmps fr48,fr48,fcc0 - test_fcc 0x8,0 - set_fcc 0xb,0 ; Set mask opposite of expected - fcmps fr48,fr52,fcc0 - test_fcc 0x4,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr48,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr48,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr52,fr0,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr52,fr4,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr52,fr8,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr52,fr12,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr52,fr16,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr52,fr20,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr52,fr24,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr52,fr28,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr52,fr32,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr52,fr36,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr52,fr40,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr52,fr44,fcc0 - test_fcc 0x2,0 - set_fcc 0xd,0 ; Set mask opposite of expected - fcmps fr52,fr48,fcc0 - test_fcc 0x2,0 - set_fcc 0x7,0 ; Set mask opposite of expected - fcmps fr52,fr52,fcc0 - test_fcc 0x8,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr52,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr52,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr56,fr0,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr56,fr4,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr56,fr8,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr56,fr12,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr56,fr16,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr56,fr20,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr56,fr24,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr56,fr28,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr56,fr32,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr56,fr36,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr56,fr40,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr56,fr44,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr56,fr48,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr56,fr52,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr56,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr56,fr60,fcc0 - test_fcc 0x1,0 - - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr60,fr0,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr60,fr4,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr60,fr8,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr60,fr12,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr60,fr16,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr60,fr20,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr60,fr24,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr60,fr28,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr60,fr32,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr60,fr36,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr60,fr40,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr60,fr44,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr60,fr48,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr60,fr52,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr60,fr56,fcc0 - test_fcc 0x1,0 - set_fcc 0xe,0 ; Set mask opposite of expected - fcmps fr60,fr60,fcc0 - test_fcc 0x1,0 - - pass diff --git a/sim/testsuite/sim/frv/fdabss.cgs b/sim/testsuite/sim/frv/fdabss.cgs deleted file mode 100644 index 83d3e1c723e..00000000000 --- a/sim/testsuite/sim/frv/fdabss.cgs +++ /dev/null @@ -1,25 +0,0 @@ -# frv testcase for fdabss $FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fdabss -fdabss: - set_fr_fr fr8,fr1 - fdabss fr0,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr28 - set_fr_fr fr24,fr13 - fdabss fr12,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - set_fr_fr fr52,fr29 - fdabss fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr52 - - pass diff --git a/sim/testsuite/sim/frv/fdadds.cgs b/sim/testsuite/sim/frv/fdadds.cgs deleted file mode 100644 index ecfa56cded8..00000000000 --- a/sim/testsuite/sim/frv/fdadds.cgs +++ /dev/null @@ -1,134 +0,0 @@ -# frv testcase for fdadds $GRi,$GRj,$GRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global fdadds -fdadds: - fdadds fr16,fr0,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr0 - fdadds fr16,fr4,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr4 - fdadds fr16,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - fdadds fr16,fr12,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr12 - fdadds fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdadds fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdadds fr16,fr24,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - fdadds fr16,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - fdadds fr16,fr32,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - fdadds fr16,fr36,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - fdadds fr16,fr40,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - fdadds fr16,fr44,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - fdadds fr16,fr48,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr48 - fdadds fr16,fr52,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr52 - - fdadds fr20,fr0,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr0 - fdadds fr20,fr4,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr4 - fdadds fr20,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - fdadds fr20,fr12,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr12 - fdadds fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdadds fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdadds fr20,fr24,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - fdadds fr20,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - fdadds fr20,fr32,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - fdadds fr20,fr36,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - fdadds fr20,fr40,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - fdadds fr20,fr44,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - fdadds fr20,fr48,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr48 - fdadds fr20,fr52,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr52 - - fdadds fr8,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdadds fr12,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdadds fr24,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdadds fr28,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - - fdadds fr36,fr40,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - - pass - - diff --git a/sim/testsuite/sim/frv/fdcmps.cgs b/sim/testsuite/sim/frv/fdcmps.cgs deleted file mode 100644 index 397832c3bed..00000000000 --- a/sim/testsuite/sim/frv/fdcmps.cgs +++ /dev/null @@ -1,985 +0,0 @@ -# frv testcase for fdcmps $FRi,$FRj,$FCCi_2 -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global fdcmps -fdcmps: - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - fdcmps fr0,fr0,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr0,fr4,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr0,fr8,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr0,fr12,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr0,fr16,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr0,fr20,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr0,fr24,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr0,fr28,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr0,fr32,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr0,fr36,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr0,fr40,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr0,fr44,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr0,fr48,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr0,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr0,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr0,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr4,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - fdcmps fr4,fr4,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr4,fr8,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr4,fr12,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr4,fr16,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr4,fr20,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr4,fr24,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr4,fr28,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr4,fr32,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr4,fr36,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr4,fr40,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr4,fr44,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr4,fr48,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr4,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr4,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr4,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr8,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr8,fr4,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - fdcmps fr8,fr8,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr8,fr12,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr8,fr16,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr8,fr20,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr8,fr24,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr8,fr28,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr8,fr32,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr8,fr36,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr8,fr40,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr8,fr44,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr8,fr48,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr8,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr8,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr8,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr12,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr12,fr4,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr12,fr8,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - fdcmps fr12,fr12,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr12,fr16,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr12,fr20,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr12,fr24,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr12,fr28,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr12,fr32,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr12,fr36,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr12,fr40,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr12,fr44,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr12,fr48,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr12,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr12,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr12,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr16,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr16,fr4,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr16,fr8,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr16,fr12,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - fdcmps fr16,fr16,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - fdcmps fr16,fr20,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr16,fr24,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr16,fr28,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr16,fr32,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr16,fr36,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr16,fr40,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr16,fr44,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr16,fr48,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr16,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr16,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr16,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr20,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr20,fr4,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr20,fr8,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr20,fr12,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - fdcmps fr20,fr16,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - fdcmps fr20,fr20,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr20,fr24,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr20,fr28,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr20,fr32,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr20,fr36,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr20,fr40,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr20,fr44,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr20,fr48,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr20,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr20,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr20,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr24,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr24,fr4,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr24,fr8,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr24,fr12,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr24,fr16,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr24,fr20,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - fdcmps fr24,fr24,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr24,fr28,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr24,fr32,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr24,fr36,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr24,fr40,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr24,fr44,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr24,fr48,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr24,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr24,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr24,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr28,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr28,fr4,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr28,fr8,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr28,fr12,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr28,fr16,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr28,fr20,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr28,fr24,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - fdcmps fr28,fr28,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr28,fr32,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr28,fr36,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr28,fr40,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr28,fr44,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr28,fr48,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr28,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr28,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr28,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr48,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr48,fr4,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr48,fr8,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr48,fr12,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr48,fr16,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr48,fr20,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr48,fr24,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr48,fr28,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr48,fr32,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr48,fr36,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr48,fr40,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr48,fr44,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - fdcmps fr48,fr48,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - fdcmps fr48,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr48,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr48,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr52,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr52,fr4,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr52,fr8,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr52,fr12,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr52,fr16,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr52,fr20,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr52,fr24,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr52,fr28,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr52,fr32,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr52,fr36,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr52,fr40,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr52,fr44,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - fdcmps fr52,fr48,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - fdcmps fr52,fr52,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr52,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr52,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr56,fr0,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr56,fr4,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr56,fr8,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr56,fr12,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr56,fr16,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr56,fr20,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr56,fr24,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr56,fr28,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr56,fr32,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr56,fr36,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr56,fr40,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr56,fr44,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr56,fr48,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr56,fr52,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr56,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr56,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr60,fr0,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr60,fr4,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr60,fr8,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr60,fr12,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr60,fr16,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr60,fr20,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr60,fr24,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr60,fr28,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr60,fr32,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr60,fr36,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr60,fr40,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr60,fr44,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr60,fr48,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr60,fr52,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr60,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - fdcmps fr60,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - - pass diff --git a/sim/testsuite/sim/frv/fddivs.cgs b/sim/testsuite/sim/frv/fddivs.cgs deleted file mode 100644 index ac423b29b1a..00000000000 --- a/sim/testsuite/sim/frv/fddivs.cgs +++ /dev/null @@ -1,195 +0,0 @@ -# frv testcase for fddivs $FRi,$FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global fddivs -fddivs: - fddivs fr0,fr28,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr0 - fddivs fr4,fr28,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr4 - fddivs fr8,fr28,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - fddivs fr12,fr28,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr12 - fddivs fr16,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr20,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr24,fr28,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - fddivs fr28,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - fddivs fr32,fr28,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - fddivs fr36,fr28,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - fddivs fr40,fr28,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - fddivs fr44,fr28,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - fddivs fr48,fr28,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr48 - fddivs fr52,fr28,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr52 - - fddivs fr16,fr0,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr16,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr16,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr16,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr16,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr16,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr16,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr16,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr16,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr16,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr16,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr16,fr52,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - - fddivs fr20,fr0,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr20,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr20,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr20,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr20,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr20,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr20,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr20,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr20,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr20,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr20,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fddivs fr20,fr52,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - - fddivs fr8,fr28,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - fddivs fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - - fddivs fr40,fr32,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - - pass - - diff --git a/sim/testsuite/sim/frv/fditos.cgs b/sim/testsuite/sim/frv/fditos.cgs deleted file mode 100644 index 412e8afa649..00000000000 --- a/sim/testsuite/sim/frv/fditos.cgs +++ /dev/null @@ -1,25 +0,0 @@ -# frv testcase for fditos $FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fditos -fditos: - set_fr_iimmed 0,0,fr2 - set_fr_iimmed 0x0000,0x0002,fr3 - fditos fr2,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr32 - - set_fr_iimmed 0xdead,0xbeef,fr2 - set_fr_iimmed 0xdead,0xbeef,fr3 - fditos fr2,fr2 - test_fr_iimmed 0xce054904,fr2 - test_fr_iimmed 0xce054904,fr3 - - pass diff --git a/sim/testsuite/sim/frv/fdivd.cgs b/sim/testsuite/sim/frv/fdivd.cgs deleted file mode 100644 index 65222bb64bf..00000000000 --- a/sim/testsuite/sim/frv/fdivd.cgs +++ /dev/null @@ -1,128 +0,0 @@ -# frv testcase for fdivd $GRi,$GRj,$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - double_constants - start - load_double_constants - - .global fdivd -fdivd: - fdivd fr0,fr28,fr2 - test_dfr_dfr fr2,fr0 - fdivd fr4,fr28,fr2 - test_dfr_dfr fr2,fr4 - fdivd fr8,fr28,fr2 - test_dfr_dfr fr2,fr8 - fdivd fr12,fr28,fr2 - test_dfr_dfr fr2,fr12 - fdivd fr16,fr28,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr20,fr28,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr24,fr28,fr2 - test_dfr_dfr fr2,fr24 - fdivd fr28,fr28,fr2 - test_dfr_dfr fr2,fr28 - fdivd fr32,fr28,fr2 - test_dfr_dfr fr2,fr32 - fdivd fr36,fr28,fr2 - test_dfr_dfr fr2,fr36 - fdivd fr40,fr28,fr2 - test_dfr_dfr fr2,fr40 - fdivd fr44,fr28,fr2 - test_dfr_dfr fr2,fr44 - fdivd fr48,fr28,fr2 - test_dfr_dfr fr2,fr48 - fdivd fr52,fr28,fr2 - test_dfr_dfr fr2,fr52 - - fdivd fr16,fr0,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr16,fr4,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr16,fr8,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr16,fr12,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr16,fr24,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr16,fr28,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr16,fr32,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr16,fr36,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr16,fr40,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr16,fr44,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr16,fr48,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr16,fr52,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - - fdivd fr20,fr0,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr20,fr4,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr20,fr8,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr20,fr12,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr20,fr24,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr20,fr28,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr20,fr32,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr20,fr36,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr20,fr40,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr20,fr44,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr20,fr48,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fdivd fr20,fr52,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - - fdivd fr8,fr28,fr2 - test_dfr_dfr fr2,fr8 - fdivd fr28,fr8,fr2 - test_dfr_dfr fr2,fr8 - - fdivd fr40,fr32,fr2 - test_dfr_dfr fr2,fr36 - - pass - - diff --git a/sim/testsuite/sim/frv/fdivs.cgs b/sim/testsuite/sim/frv/fdivs.cgs deleted file mode 100644 index cf2bd4b9b0f..00000000000 --- a/sim/testsuite/sim/frv/fdivs.cgs +++ /dev/null @@ -1,127 +0,0 @@ -# frv testcase for fdivs $GRi,$GRj,$GRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fdivs -fdivs: - fdivs fr0,fr28,fr1 - test_fr_fr fr1,fr0 - fdivs fr4,fr28,fr1 - test_fr_fr fr1,fr4 - fdivs fr8,fr28,fr1 - test_fr_fr fr1,fr8 - fdivs fr12,fr28,fr1 - test_fr_fr fr1,fr12 - fdivs fr16,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr20,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr24,fr28,fr1 - test_fr_fr fr1,fr24 - fdivs fr28,fr28,fr1 - test_fr_fr fr1,fr28 - fdivs fr32,fr28,fr1 - test_fr_fr fr1,fr32 - fdivs fr36,fr28,fr1 - test_fr_fr fr1,fr36 - fdivs fr40,fr28,fr1 - test_fr_fr fr1,fr40 - fdivs fr44,fr28,fr1 - test_fr_fr fr1,fr44 - fdivs fr48,fr28,fr1 - test_fr_fr fr1,fr48 - fdivs fr52,fr28,fr1 - test_fr_fr fr1,fr52 - - fdivs fr16,fr0,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr16,fr4,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr16,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr16,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr16,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr16,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr16,fr32,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr16,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr16,fr40,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr16,fr44,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr16,fr48,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr16,fr52,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - fdivs fr20,fr0,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr20,fr4,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr20,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr20,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr20,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr20,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr20,fr32,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr20,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr20,fr40,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr20,fr44,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr20,fr48,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fdivs fr20,fr52,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - fdivs fr8,fr28,fr1 - test_fr_fr fr1,fr8 - fdivs fr28,fr8,fr1 - test_fr_fr fr1,fr8 - - fdivs fr40,fr32,fr1 - test_fr_fr fr1,fr36 - - pass - - diff --git a/sim/testsuite/sim/frv/fdmadds.cgs b/sim/testsuite/sim/frv/fdmadds.cgs deleted file mode 100644 index 7035366ac50..00000000000 --- a/sim/testsuite/sim/frv/fdmadds.cgs +++ /dev/null @@ -1,226 +0,0 @@ -# frv testcase for fdmadds $GRi,$GRj,$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global fdmadds -fdmadds: - fdmadds fr16,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr16,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr16,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr16,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr16,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr16,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr16,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr16,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr16,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr16,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - - fdmadds fr20,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr20,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr20,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr20,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr20,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr20,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr20,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr20,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr20,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmadds fr20,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - fdmadds fr28,fr0,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr0 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - fdmadds fr28,fr4,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr4 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - fdmadds fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - fdmadds fr28,fr12,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr12 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - fdmadds fr28,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - fdmadds fr28,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - fdmadds fr28,fr24,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - fdmadds fr28,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - fdmadds fr28,fr32,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - fdmadds fr28,fr36,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - fdmadds fr28,fr40,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - fdmadds fr28,fr44,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - fdmadds fr28,fr48,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr48 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - fdmadds fr28,fr52,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr52 - - set_fr_fr fr36,fr2 - set_fr_fr fr36,fr3 - fdmadds fr28,fr8,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - fdmadds fr8,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - - set_fr_fr fr36,fr2 - set_fr_fr fr36,fr3 - fdmadds fr32,fr36,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - - pass diff --git a/sim/testsuite/sim/frv/fdmas.cgs b/sim/testsuite/sim/frv/fdmas.cgs deleted file mode 100644 index a7162db296e..00000000000 --- a/sim/testsuite/sim/frv/fdmas.cgs +++ /dev/null @@ -1,265 +0,0 @@ -# frv testcase for fdmas $FRi,$FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - load_float_constants2 - load_float_constants3 - - .global fdmas -fdmas: - fdmas fr16,fr4,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr4 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr4 - fdmas fr16,fr8,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr8 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr8 - fdmas fr16,fr12,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr12 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr12 - fdmas fr16,fr16,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - fdmas fr16,fr20,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - fdmas fr16,fr24,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr24 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr24 - fdmas fr16,fr28,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr28 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr28 - fdmas fr16,fr32,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr32 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr32 - fdmas fr16,fr36,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr36 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr36 - fdmas fr16,fr40,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr40 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr40 - fdmas fr16,fr44,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr44 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr44 - fdmas fr16,fr48,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr48 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr48 - - fdmas fr20,fr4,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr4 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr4 - fdmas fr20,fr8,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr8 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr8 - fdmas fr20,fr12,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr12 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr12 - fdmas fr20,fr16,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - fdmas fr20,fr20,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - fdmas fr20,fr24,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr24 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr24 - fdmas fr20,fr28,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr28 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr28 - fdmas fr20,fr32,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr32 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr32 - fdmas fr20,fr36,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr36 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr36 - fdmas fr20,fr40,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr40 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr40 - fdmas fr20,fr44,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr44 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr44 - fdmas fr20,fr48,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr48 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr48 - - fdmas fr28,fr0,fr60 - test_fr_fr fr60,fr0 - test_fr_fr fr62,fr0 - fdmas fr28,fr4,fr60 - test_fr_fr fr60,fr4 - test_fr_fr fr62,fr4 - fdmas fr28,fr8,fr60 - test_fr_fr fr60,fr8 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr8 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - fdmas fr28,fr12,fr60 - test_fr_fr fr60,fr12 - test_fr_fr fr62,fr12 - fdmas fr28,fr16,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - fdmas fr28,fr20,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - fdmas fr28,fr24,fr60 - test_fr_fr fr60,fr24 - test_fr_fr fr62,fr24 - fdmas fr28,fr28,fr60 - test_fr_fr fr60,fr28 - test_fr_fr fr62,fr28 - fdmas fr28,fr32,fr60 - test_fr_fr fr60,fr32 - test_fr_fr fr61,fr36 - test_fr_fr fr62,fr32 - test_fr_fr fr63,fr36 - fdmas fr28,fr36,fr60 - test_fr_fr fr60,fr36 - test_fr_fr fr62,fr36 - fdmas fr28,fr40,fr60 - test_fr_fr fr60,fr40 - test_fr_fr fr62,fr40 - fdmas fr28,fr44,fr60 - test_fr_fr fr60,fr44 - test_fr_fr fr62,fr44 - fdmas fr28,fr48,fr60 - test_fr_fr fr60,fr48 - test_fr_fr fr62,fr48 - fdmas fr28,fr52,fr60 - test_fr_fr fr60,fr52 - test_fr_fr fr62,fr52 - - fdmas fr28,fr8,fr60 - test_fr_fr fr60,fr8 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr8 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - fdmas fr8,fr28,fr60 - test_fr_fr fr60,fr8 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr8 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - - fdmas fr32,fr36,fr60 - test_fr_fr fr60,fr40 - test_fr_fr fr62,fr40 - - pass diff --git a/sim/testsuite/sim/frv/fdmovs.cgs b/sim/testsuite/sim/frv/fdmovs.cgs deleted file mode 100644 index 58e9607ccfc..00000000000 --- a/sim/testsuite/sim/frv/fdmovs.cgs +++ /dev/null @@ -1,45 +0,0 @@ -# frv testcase for fdmovs $FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fdmovs -fdmovs: - set_fr_fr fr4,fr1 - fdmovs fr0,fr2 - test_fr_fr fr0,fr2 - test_fr_fr fr4,fr3 - set_fr_fr fr12,fr9 - fdmovs fr8,fr2 - test_fr_fr fr8,fr2 - test_fr_fr fr12,fr3 - set_fr_fr fr20,fr17 - fdmovs fr16,fr2 - test_fr_fr fr16,fr2 - test_fr_fr fr20,fr3 - set_fr_fr fr28,fr25 - fdmovs fr24,fr2 - test_fr_fr fr24,fr2 - test_fr_fr fr28,fr3 - set_fr_fr fr36,fr33 - fdmovs fr32,fr2 - test_fr_fr fr32,fr2 - test_fr_fr fr36,fr3 - set_fr_fr fr44,fr41 - fdmovs fr40,fr2 - test_fr_fr fr40,fr2 - test_fr_fr fr44,fr3 - set_fr_fr fr52,fr49 - fdmovs fr48,fr2 - test_fr_fr fr48,fr2 - test_fr_fr fr52,fr3 - set_fr_fr fr60,fr57 - fdmovs fr56,fr2 - test_fr_iimmed 0x7fc00000,fr2 - test_fr_iimmed 0x7f800001,fr3 - - pass diff --git a/sim/testsuite/sim/frv/fdmss.cgs b/sim/testsuite/sim/frv/fdmss.cgs deleted file mode 100644 index 5457a1ee600..00000000000 --- a/sim/testsuite/sim/frv/fdmss.cgs +++ /dev/null @@ -1,235 +0,0 @@ -# frv testcase for fdmss $FRi,$FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - load_float_constants2 - load_float_constants3 - - .global fdmss -fdmss: - fdmss fr16,fr4,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - fdmss fr16,fr8,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr28 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr28 - fdmss fr16,fr12,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - fdmss fr16,fr16,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - fdmss fr16,fr20,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - fdmss fr16,fr24,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - fdmss fr16,fr28,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr8 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr8 - fdmss fr16,fr32,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - fdmss fr16,fr36,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - fdmss fr16,fr40,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - fdmss fr16,fr44,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - fdmss fr16,fr48,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - - fdmss fr20,fr4,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - fdmss fr20,fr8,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr28 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr28 - fdmss fr20,fr12,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - fdmss fr20,fr16,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - fdmss fr20,fr20,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - fdmss fr20,fr24,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - fdmss fr20,fr28,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr8 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr8 - fdmss fr20,fr32,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - fdmss fr20,fr36,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - fdmss fr20,fr40,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - fdmss fr20,fr44,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - fdmss fr20,fr48,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - - fdmss fr28,fr0,fr60 - test_fr_fr fr60,fr0 - test_fr_fr fr62,fr0 - fdmss fr28,fr4,fr60 - test_fr_fr fr60,fr4 - test_fr_fr fr62,fr4 - fdmss fr28,fr8,fr60 - test_fr_fr fr60,fr8 - test_fr_fr fr61,fr32 - test_fr_fr fr62,fr8 - test_fr_fr fr63,fr32 - fdmss fr28,fr12,fr60 - test_fr_fr fr60,fr12 - test_fr_fr fr62,fr12 - fdmss fr28,fr16,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr28 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr28 - fdmss fr28,fr20,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr28 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr28 - fdmss fr28,fr24,fr60 - test_fr_fr fr60,fr24 - test_fr_fr fr62,fr24 - fdmss fr28,fr28,fr60 - test_fr_fr fr60,fr28 - test_fr_fr fr61,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr62,fr28 - test_fr_fr fr63,fr20 - test_fr_fr fr63,fr16 - fdmss fr28,fr32,fr60 - test_fr_fr fr60,fr32 - test_fr_fr fr61,fr8 - test_fr_fr fr62,fr32 - test_fr_fr fr63,fr8 - fdmss fr28,fr36,fr60 - test_fr_fr fr60,fr36 - test_fr_fr fr62,fr36 - fdmss fr28,fr40,fr60 - test_fr_fr fr60,fr40 - test_fr_fr fr62,fr40 - fdmss fr28,fr44,fr60 - test_fr_fr fr60,fr44 - test_fr_fr fr62,fr44 - fdmss fr28,fr48,fr60 - test_fr_fr fr60,fr48 - test_fr_fr fr62,fr48 - fdmss fr28,fr52,fr60 - test_fr_fr fr60,fr52 - test_fr_fr fr62,fr52 - - fdmss fr28,fr8,fr60 - test_fr_fr fr60,fr8 - test_fr_fr fr61,fr32 - test_fr_fr fr62,fr8 - test_fr_fr fr63,fr32 - fdmss fr8,fr28,fr60 - test_fr_fr fr60,fr8 - test_fr_fr fr62,fr8 - - fdmss fr32,fr36,fr60 - test_fr_fr fr60,fr40 - test_fr_fr fr61,fr8 - test_fr_fr fr62,fr40 - test_fr_fr fr63,fr8 - - pass diff --git a/sim/testsuite/sim/frv/fdmulcs.cgs b/sim/testsuite/sim/frv/fdmulcs.cgs deleted file mode 100644 index a7cb15950d0..00000000000 --- a/sim/testsuite/sim/frv/fdmulcs.cgs +++ /dev/null @@ -1,201 +0,0 @@ -# frv testcase for fdmulcs $FRi,$FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global fdmulcs -fdmulcs: - fdmulcs fr16,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr16,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr16,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr16,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr16,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr16,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr16,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr16,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr16,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr16,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - - fdmulcs fr20,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr20,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr20,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr3,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr2,fr20 - fdmulcs fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr20,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr20,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr20,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr20,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr20,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr20,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr20,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - - fdmulcs fr28,fr0,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr0 - fdmulcs fr28,fr4,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr4 - fdmulcs fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - fdmulcs fr28,fr12,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr12 - fdmulcs fr28,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr28,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmulcs fr28,fr24,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - fdmulcs fr28,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - fdmulcs fr28,fr32,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - fdmulcs fr28,fr36,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - fdmulcs fr28,fr40,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - fdmulcs fr28,fr44,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - fdmulcs fr28,fr48,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr48 - fdmulcs fr28,fr52,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr52 - - fdmulcs fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - fdmulcs fr8,fr28,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - - fdmulcs fr32,fr36,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - - set_fr_fr fr32,fr50 ; 2 - set_fr_fr fr28,fr51 ; 1 - set_fr_fr fr44,fr52 ; 9 - set_fr_fr fr36,fr53 ; 3 - fdmulcs fr50,fr52,fr54 ; 2*3, 1*9 - test_fr_fr fr54,fr40 ; 6 - test_fr_fr fr55,fr44 ; 9 - - pass diff --git a/sim/testsuite/sim/frv/fdmuls.cgs b/sim/testsuite/sim/frv/fdmuls.cgs deleted file mode 100644 index 2c2c05abdf0..00000000000 --- a/sim/testsuite/sim/frv/fdmuls.cgs +++ /dev/null @@ -1,193 +0,0 @@ -# frv testcase for fdmuls $FRi,$FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global fdmuls -fdmuls: - fdmuls fr16,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr16,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr16,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr16,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr16,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr16,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr16,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr16,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr16,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr16,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - - fdmuls fr20,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr20,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr20,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr3,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr2,fr20 - fdmuls fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr20,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr20,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr20,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr20,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr20,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr20,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr20,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - - fdmuls fr28,fr0,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr0 - fdmuls fr28,fr4,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr4 - fdmuls fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - fdmuls fr28,fr12,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr12 - fdmuls fr28,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr28,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdmuls fr28,fr24,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - fdmuls fr28,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - fdmuls fr28,fr32,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - fdmuls fr28,fr36,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - fdmuls fr28,fr40,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - fdmuls fr28,fr44,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - fdmuls fr28,fr48,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr48 - fdmuls fr28,fr52,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr52 - - fdmuls fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - fdmuls fr8,fr28,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - - fdmuls fr32,fr36,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - - pass diff --git a/sim/testsuite/sim/frv/fdnegs.cgs b/sim/testsuite/sim/frv/fdnegs.cgs deleted file mode 100644 index db409cb04a4..00000000000 --- a/sim/testsuite/sim/frv/fdnegs.cgs +++ /dev/null @@ -1,25 +0,0 @@ -# frv testcase for fdnegs $FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fdnegs -fdnegs: - set_fr_fr fr8,fr1 - fdnegs fr0,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr28 - set_fr_fr fr24,fr13 - fdnegs fr12,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr12 - set_fr_fr fr52,fr29 - fdnegs fr28,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr0 - - pass diff --git a/sim/testsuite/sim/frv/fdsads.cgs b/sim/testsuite/sim/frv/fdsads.cgs deleted file mode 100644 index 123810df17d..00000000000 --- a/sim/testsuite/sim/frv/fdsads.cgs +++ /dev/null @@ -1,119 +0,0 @@ -# frv testcase for fdsads $FRi,$FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global fdsads -fdsads: - fdsads fr16,fr0,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr52 - fdsads fr16,fr4,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr48 - fdsads fr16,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr28 - fdsads fr16,fr12,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr24 - fdsads fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdsads fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdsads fr16,fr24,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr12 - fdsads fr16,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr8 - fdsads fr16,fr32,fr2 - test_fr_fr fr2,fr32 - fdsads fr16,fr36,fr2 - test_fr_fr fr2,fr36 - fdsads fr16,fr40,fr2 - test_fr_fr fr2,fr40 - fdsads fr16,fr44,fr2 - test_fr_fr fr2,fr44 - fdsads fr16,fr48,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr4 - fdsads fr16,fr52,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr0 - - fdsads fr20,fr0,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr52 - fdsads fr20,fr4,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr48 - fdsads fr20,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr28 - fdsads fr20,fr12,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr24 - fdsads fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdsads fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdsads fr20,fr24,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr12 - fdsads fr20,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr8 - fdsads fr20,fr32,fr2 - test_fr_fr fr2,fr32 - fdsads fr20,fr36,fr2 - test_fr_fr fr2,fr36 - fdsads fr20,fr40,fr2 - test_fr_fr fr2,fr40 - fdsads fr20,fr44,fr2 - test_fr_fr fr2,fr44 - fdsads fr20,fr48,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr4 - fdsads fr20,fr52,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr0 - - fdsads fr8,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fdsads fr12,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fdsads fr24,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fdsads fr28,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr32 - test_fr_fr fr3,fr32 - - fdsads fr36,fr40,fr2 - test_fr_fr fr2,fr44 - - pass - - diff --git a/sim/testsuite/sim/frv/fdsqrts.cgs b/sim/testsuite/sim/frv/fdsqrts.cgs deleted file mode 100644 index 6026b93a2a0..00000000000 --- a/sim/testsuite/sim/frv/fdsqrts.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# frv testcase for fdsqrts $FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fdsqrts -fdsqrts: - set_fr_iimmed 0x4049,0x0fdb,fr45 ; 3.141592654 - fdsqrts fr44,fr2 ; 9.0 - test_fr_fr fr2,fr36 ; 3.0 - test_fr_iimmed 0x3fe2dfc5,fr3 ; 1.7724539 - - pass diff --git a/sim/testsuite/sim/frv/fdstoi.cgs b/sim/testsuite/sim/frv/fdstoi.cgs deleted file mode 100644 index 5c79e49dfc6..00000000000 --- a/sim/testsuite/sim/frv/fdstoi.cgs +++ /dev/null @@ -1,23 +0,0 @@ -# frv testcase for fdstoi $FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fdstoi -fdstoi: - set_fr_fr fr20,fr17 - fdstoi fr16,fr2 - test_fr_iimmed 0,fr2 - test_fr_iimmed 0,fr3 - - set_fr_iimmed 0xce05,0x4904,fr2 - set_fr_fr fr32,fr3 - fdstoi fr2,fr2 - test_fr_iimmed 0xdeadbf00,fr2 - test_fr_iimmed 0x00000002,fr3 - - pass diff --git a/sim/testsuite/sim/frv/fdsubs.cgs b/sim/testsuite/sim/frv/fdsubs.cgs deleted file mode 100644 index 93dae46d9ee..00000000000 --- a/sim/testsuite/sim/frv/fdsubs.cgs +++ /dev/null @@ -1,117 +0,0 @@ -# frv testcase for fdsubs $FRi,$FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global fdsubs -fdsubs: - fdsubs fr0,fr16,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr0 - fdsubs fr4,fr16,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr4 - fdsubs fr8,fr16,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - fdsubs fr12,fr16,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr12 - fdsubs fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdsubs fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdsubs fr24,fr16,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - fdsubs fr28,fr16,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - fdsubs fr32,fr16,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - fdsubs fr36,fr16,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - fdsubs fr40,fr16,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - fdsubs fr44,fr16,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - fdsubs fr48,fr16,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr48 - fdsubs fr52,fr16,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr52 - - fdsubs fr0,fr20,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr0 - fdsubs fr4,fr20,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr4 - fdsubs fr8,fr20,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - fdsubs fr12,fr20,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr12 - fdsubs fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdsubs fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fdsubs fr24,fr20,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - fdsubs fr28,fr20,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - fdsubs fr32,fr20,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - fdsubs fr36,fr20,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - fdsubs fr40,fr20,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - fdsubs fr44,fr20,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - fdsubs fr48,fr20,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr48 - fdsubs fr52,fr20,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr52 - - fdsubs fr32,fr36,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - - fdsubs fr44,fr40,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - - pass - - diff --git a/sim/testsuite/sim/frv/fdtoi.cgs b/sim/testsuite/sim/frv/fdtoi.cgs deleted file mode 100644 index 1749852263e..00000000000 --- a/sim/testsuite/sim/frv/fdtoi.cgs +++ /dev/null @@ -1,32 +0,0 @@ -# frv testcase for fdtoi $FRj,$FRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global fdtoi -fdtoi: - set_fr_iimmed 0,0,fr2 - set_fr_iimmed 0,0,fr3 - fdtoi fr2,fr2 - test_fr_iimmed 0,fr2 - - set_fr_iimmed 0x4000,0x0000,fr2 - set_fr_iimmed 0x0000,0x0000,fr3 - fdtoi fr2,fr2 - test_fr_iimmed 0x00000002,fr2 - - set_fr_iimmed 0xc1c0,0xa920,fr2 - set_fr_iimmed 0x8880,0x0000,fr3 - fdtoi fr2,fr2 - test_fr_iimmed 0xdeadbeef,fr2 - - set_gr_limmed 0x4031,0x0000,gr8 - set_gr_limmed 0x0000,0x0000,gr9 - movgfd gr8,fr0 - fdtoi fr0,fr0 - test_fr_iimmed 17,fr0 - - pass diff --git a/sim/testsuite/sim/frv/fitod.cgs b/sim/testsuite/sim/frv/fitod.cgs deleted file mode 100644 index 62ef1f21f39..00000000000 --- a/sim/testsuite/sim/frv/fitod.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for fitod $FRj,$FRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global fitod -fitod: - set_fr_iimmed 0,0,fr2 - fitod fr2,fr2 - test_fr_iimmed 0,fr2 - test_fr_iimmed 0,fr3 - - set_fr_iimmed 0x0000,0x0002,fr2 - fitod fr2,fr2 - test_fr_iimmed 0x40000000,fr2 - test_fr_iimmed 0x00000000,fr3 - - set_fr_iimmed 0xdead,0xbeef,fr2 - fitod fr2,fr2 - test_fr_iimmed 0xc1c0a920,fr2 - test_fr_iimmed 0x88800000,fr3 - - pass diff --git a/sim/testsuite/sim/frv/fitos.cgs b/sim/testsuite/sim/frv/fitos.cgs deleted file mode 100644 index 2afe290565c..00000000000 --- a/sim/testsuite/sim/frv/fitos.cgs +++ /dev/null @@ -1,25 +0,0 @@ -# frv testcase for fitos $FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fitos -fitos: - set_fr_iimmed 0,0,fr1 - fitos fr1,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - set_fr_iimmed 0x0000,0x0002,fr1 - fitos fr1,fr1 - test_fr_fr fr1,fr32 - - set_fr_iimmed 0xdead,0xbeef,fr1 - fitos fr1,fr1 - test_fr_iimmed 0xce054904,fr1 - - pass diff --git a/sim/testsuite/sim/frv/fmad.cgs b/sim/testsuite/sim/frv/fmad.cgs deleted file mode 100644 index 64fee9c56ea..00000000000 --- a/sim/testsuite/sim/frv/fmad.cgs +++ /dev/null @@ -1,161 +0,0 @@ -# frv testcase for fmad $FRi,$FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global fmad -fmad: - fmad fr16,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr4 - fmad fr16,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - fmad fr16,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr12 - fmad fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmad fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmad fr16,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr24 - fmad fr16,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - fmad fr16,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr32 - fmad fr16,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr36 - fmad fr16,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr40 - fmad fr16,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr44 - fmad fr16,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr48 - - fmad fr20,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr4 - fmad fr20,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - fmad fr20,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr12 - fmad fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmad fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmad fr20,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr24 - fmad fr20,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - fmad fr20,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr32 - fmad fr20,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr36 - fmad fr20,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr40 - fmad fr20,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr44 - fmad fr20,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr48 - - fmad fr28,fr0,fr2 - test_fr_fr fr2,fr0 - fmad fr28,fr4,fr2 - test_fr_fr fr2,fr4 - fmad fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmad fr28,fr12,fr2 - test_fr_fr fr2,fr12 - fmad fr28,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmad fr28,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmad fr28,fr24,fr2 - test_fr_fr fr2,fr24 - fmad fr28,fr28,fr2 - test_fr_fr fr2,fr28 - fmad fr28,fr32,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr36 - fmad fr28,fr36,fr2 - test_fr_fr fr2,fr36 - fmad fr28,fr40,fr2 - test_fr_fr fr2,fr40 - fmad fr28,fr44,fr2 - test_fr_fr fr2,fr44 - fmad fr28,fr48,fr2 - test_fr_fr fr2,fr48 - fmad fr28,fr52,fr2 - test_fr_fr fr2,fr52 - - fmad fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmad fr8,fr28,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - - fmad fr32,fr36,fr2 - test_fr_fr fr2,fr40 - - pass diff --git a/sim/testsuite/sim/frv/fmaddd.cgs b/sim/testsuite/sim/frv/fmaddd.cgs deleted file mode 100644 index bfa816f1a2a..00000000000 --- a/sim/testsuite/sim/frv/fmaddd.cgs +++ /dev/null @@ -1,143 +0,0 @@ -# frv testcase for fmaddd $GRi,$GRj,$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - double_constants - start - load_double_constants - - .global fmaddd -fmaddd: - set_dfr_dfr fr16,fr2 - fmaddd fr16,fr4,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr16,fr8,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr16,fr12,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr16,fr16,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr16,fr20,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr16,fr24,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr16,fr28,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr16,fr32,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr16,fr36,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr16,fr40,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr16,fr44,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr16,fr48,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - - fmaddd fr20,fr4,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr20,fr8,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr20,fr12,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr20,fr16,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr20,fr20,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr20,fr24,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr20,fr28,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr20,fr32,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr20,fr36,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr20,fr40,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr20,fr44,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmaddd fr20,fr48,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - - set_dfr_dfr fr16,fr2 - fmaddd fr28,fr0,fr2 - test_dfr_dfr fr2,fr0 - set_dfr_dfr fr16,fr2 - fmaddd fr28,fr4,fr2 - test_dfr_dfr fr2,fr4 - set_dfr_dfr fr16,fr2 - fmaddd fr28,fr8,fr2 - test_dfr_dfr fr2,fr8 - set_dfr_dfr fr16,fr2 - fmaddd fr28,fr12,fr2 - test_dfr_dfr fr2,fr12 - set_dfr_dfr fr16,fr2 - fmaddd fr28,fr16,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - set_dfr_dfr fr16,fr2 - fmaddd fr28,fr20,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - set_dfr_dfr fr16,fr2 - fmaddd fr28,fr24,fr2 - test_dfr_dfr fr2,fr24 - set_dfr_dfr fr16,fr2 - fmaddd fr28,fr28,fr2 - test_dfr_dfr fr2,fr28 - set_dfr_dfr fr16,fr2 - fmaddd fr28,fr32,fr2 - test_dfr_dfr fr2,fr32 - set_dfr_dfr fr16,fr2 - fmaddd fr28,fr36,fr2 - test_dfr_dfr fr2,fr36 - set_dfr_dfr fr16,fr2 - fmaddd fr28,fr40,fr2 - test_dfr_dfr fr2,fr40 - set_dfr_dfr fr16,fr2 - fmaddd fr28,fr44,fr2 - test_dfr_dfr fr2,fr44 - set_dfr_dfr fr16,fr2 - fmaddd fr28,fr48,fr2 - test_dfr_dfr fr2,fr48 - set_dfr_dfr fr16,fr2 - fmaddd fr28,fr52,fr2 - test_dfr_dfr fr2,fr52 - - set_dfr_dfr fr36,fr2 - fmaddd fr28,fr8,fr2 - test_dfr_dfr fr2,fr32 - fmaddd fr8,fr28,fr2 - test_dfr_dfr fr2,fr28 - - set_dfr_dfr fr36,fr2 - fmaddd fr32,fr36,fr2 - test_dfr_dfr fr2,fr44 - - pass diff --git a/sim/testsuite/sim/frv/fmadds.cgs b/sim/testsuite/sim/frv/fmadds.cgs deleted file mode 100644 index 128c82a9b56..00000000000 --- a/sim/testsuite/sim/frv/fmadds.cgs +++ /dev/null @@ -1,143 +0,0 @@ -# frv testcase for fmadds $GRi,$GRj,$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fmadds -fmadds: - set_fr_fr fr16,fr1 - fmadds fr16,fr4,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr16,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr16,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr16,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr16,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr16,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr16,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr16,fr32,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr16,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr16,fr40,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr16,fr44,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr16,fr48,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - fmadds fr20,fr4,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr20,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr20,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr20,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr20,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr20,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr20,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr20,fr32,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr20,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr20,fr40,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr20,fr44,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmadds fr20,fr48,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - set_fr_fr fr16,fr1 - fmadds fr28,fr0,fr1 - test_fr_fr fr1,fr0 - set_fr_fr fr16,fr1 - fmadds fr28,fr4,fr1 - test_fr_fr fr1,fr4 - set_fr_fr fr16,fr1 - fmadds fr28,fr8,fr1 - test_fr_fr fr1,fr8 - set_fr_fr fr16,fr1 - fmadds fr28,fr12,fr1 - test_fr_fr fr1,fr12 - set_fr_fr fr16,fr1 - fmadds fr28,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - set_fr_fr fr16,fr1 - fmadds fr28,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - set_fr_fr fr16,fr1 - fmadds fr28,fr24,fr1 - test_fr_fr fr1,fr24 - set_fr_fr fr16,fr1 - fmadds fr28,fr28,fr1 - test_fr_fr fr1,fr28 - set_fr_fr fr16,fr1 - fmadds fr28,fr32,fr1 - test_fr_fr fr1,fr32 - set_fr_fr fr16,fr1 - fmadds fr28,fr36,fr1 - test_fr_fr fr1,fr36 - set_fr_fr fr16,fr1 - fmadds fr28,fr40,fr1 - test_fr_fr fr1,fr40 - set_fr_fr fr16,fr1 - fmadds fr28,fr44,fr1 - test_fr_fr fr1,fr44 - set_fr_fr fr16,fr1 - fmadds fr28,fr48,fr1 - test_fr_fr fr1,fr48 - set_fr_fr fr16,fr1 - fmadds fr28,fr52,fr1 - test_fr_fr fr1,fr52 - - set_fr_fr fr36,fr1 - fmadds fr28,fr8,fr1 - test_fr_fr fr1,fr32 - fmadds fr8,fr28,fr1 - test_fr_fr fr1,fr28 - - set_fr_fr fr36,fr1 - fmadds fr32,fr36,fr1 - test_fr_fr fr1,fr44 - - pass diff --git a/sim/testsuite/sim/frv/fmas.cgs b/sim/testsuite/sim/frv/fmas.cgs deleted file mode 100644 index 1e7b1dfef8b..00000000000 --- a/sim/testsuite/sim/frv/fmas.cgs +++ /dev/null @@ -1,161 +0,0 @@ -# frv testcase for fmas $FRi,$FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global fmas -fmas: - fmas fr16,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr4 - fmas fr16,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - fmas fr16,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr12 - fmas fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmas fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmas fr16,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr24 - fmas fr16,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - fmas fr16,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr32 - fmas fr16,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr36 - fmas fr16,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr40 - fmas fr16,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr44 - fmas fr16,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr48 - - fmas fr20,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr4 - fmas fr20,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - fmas fr20,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr12 - fmas fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmas fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmas fr20,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr24 - fmas fr20,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - fmas fr20,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr32 - fmas fr20,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr36 - fmas fr20,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr40 - fmas fr20,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr44 - fmas fr20,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr48 - - fmas fr28,fr0,fr2 - test_fr_fr fr2,fr0 - fmas fr28,fr4,fr2 - test_fr_fr fr2,fr4 - fmas fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmas fr28,fr12,fr2 - test_fr_fr fr2,fr12 - fmas fr28,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmas fr28,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmas fr28,fr24,fr2 - test_fr_fr fr2,fr24 - fmas fr28,fr28,fr2 - test_fr_fr fr2,fr28 - fmas fr28,fr32,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr36 - fmas fr28,fr36,fr2 - test_fr_fr fr2,fr36 - fmas fr28,fr40,fr2 - test_fr_fr fr2,fr40 - fmas fr28,fr44,fr2 - test_fr_fr fr2,fr44 - fmas fr28,fr48,fr2 - test_fr_fr fr2,fr48 - fmas fr28,fr52,fr2 - test_fr_fr fr2,fr52 - - fmas fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmas fr8,fr28,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - - fmas fr32,fr36,fr2 - test_fr_fr fr2,fr40 - - pass diff --git a/sim/testsuite/sim/frv/fmovd.cgs b/sim/testsuite/sim/frv/fmovd.cgs deleted file mode 100644 index 938faa2adf6..00000000000 --- a/sim/testsuite/sim/frv/fmovd.cgs +++ /dev/null @@ -1,48 +0,0 @@ -# frv testcase for fmovd $FRj,$FRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - double_constants - start - load_double_constants - - .global fmovd -fmovd: - fmovd fr0,fr2 - test_dfr_dfr fr0,fr2 - fmovd fr4,fr2 - test_dfr_dfr fr4,fr2 - fmovd fr8,fr2 - test_dfr_dfr fr8,fr2 - fmovd fr12,fr2 - test_dfr_dfr fr12,fr2 - fmovd fr16,fr2 - test_dfr_dfr fr16,fr2 - fmovd fr20,fr2 - test_dfr_dfr fr20,fr2 - fmovd fr24,fr2 - test_dfr_dfr fr24,fr2 - fmovd fr28,fr2 - test_dfr_dfr fr28,fr2 - fmovd fr32,fr2 - test_dfr_dfr fr32,fr2 - fmovd fr36,fr2 - test_dfr_dfr fr36,fr2 - fmovd fr40,fr2 - test_dfr_dfr fr40,fr2 - fmovd fr44,fr2 - test_dfr_dfr fr44,fr2 - fmovd fr48,fr2 - test_dfr_dfr fr48,fr2 - fmovd fr52,fr2 - test_dfr_dfr fr52,fr2 - fmovd fr56,fr2 - test_fr_iimmed 0x7ff80000,fr2 - test_fr_iimmed 0x00000000,fr3 - fmovd fr60,fr2 - test_fr_iimmed 0x7ff00000,fr2 - test_fr_iimmed 0x00000001,fr3 - - pass diff --git a/sim/testsuite/sim/frv/fmovs.cgs b/sim/testsuite/sim/frv/fmovs.cgs deleted file mode 100644 index 2a70277f6e5..00000000000 --- a/sim/testsuite/sim/frv/fmovs.cgs +++ /dev/null @@ -1,45 +0,0 @@ -# frv testcase for fmovs $FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fmovs -fmovs: - fmovs fr0,fr1 - test_fr_fr fr0,fr1 - fmovs fr4,fr1 - test_fr_fr fr4,fr1 - fmovs fr8,fr1 - test_fr_fr fr8,fr1 - fmovs fr12,fr1 - test_fr_fr fr12,fr1 - fmovs fr16,fr1 - test_fr_fr fr16,fr1 - fmovs fr20,fr1 - test_fr_fr fr20,fr1 - fmovs fr24,fr1 - test_fr_fr fr24,fr1 - fmovs fr28,fr1 - test_fr_fr fr28,fr1 - fmovs fr32,fr1 - test_fr_fr fr32,fr1 - fmovs fr36,fr1 - test_fr_fr fr36,fr1 - fmovs fr40,fr1 - test_fr_fr fr40,fr1 - fmovs fr44,fr1 - test_fr_fr fr44,fr1 - fmovs fr48,fr1 - test_fr_fr fr48,fr1 - fmovs fr52,fr1 - test_fr_fr fr52,fr1 - fmovs fr56,fr1 - test_fr_iimmed 0x7fc00000,fr1 - fmovs fr60,fr1 - test_fr_iimmed 0x7f800001,fr1 - - pass diff --git a/sim/testsuite/sim/frv/fmsd.cgs b/sim/testsuite/sim/frv/fmsd.cgs deleted file mode 100644 index cd2efbd119e..00000000000 --- a/sim/testsuite/sim/frv/fmsd.cgs +++ /dev/null @@ -1,146 +0,0 @@ -# frv testcase for fmsd $FRi,$FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global fmsd -fmsd: - fmsd fr16,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmsd fr16,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - fmsd fr16,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmsd fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmsd fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmsd fr16,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmsd fr16,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - fmsd fr16,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmsd fr16,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmsd fr16,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmsd fr16,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmsd fr16,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - - fmsd fr20,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmsd fr20,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - fmsd fr20,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmsd fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmsd fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmsd fr20,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmsd fr20,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - fmsd fr20,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmsd fr20,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmsd fr20,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmsd fr20,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmsd fr20,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - - fmsd fr28,fr0,fr2 - test_fr_fr fr2,fr0 - fmsd fr28,fr4,fr2 - test_fr_fr fr2,fr4 - fmsd fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr32 - fmsd fr28,fr12,fr2 - test_fr_fr fr2,fr12 - fmsd fr28,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - fmsd fr28,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - fmsd fr28,fr24,fr2 - test_fr_fr fr2,fr24 - fmsd fr28,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr20 - test_fr_fr fr3,fr16 - fmsd fr28,fr32,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr8 - fmsd fr28,fr36,fr2 - test_fr_fr fr2,fr36 - fmsd fr28,fr40,fr2 - test_fr_fr fr2,fr40 - fmsd fr28,fr44,fr2 - test_fr_fr fr2,fr44 - fmsd fr28,fr48,fr2 - test_fr_fr fr2,fr48 - fmsd fr28,fr52,fr2 - test_fr_fr fr2,fr52 - - fmsd fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr32 - fmsd fr8,fr28,fr2 - test_fr_fr fr2,fr8 - - fmsd fr32,fr36,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr8 - - pass diff --git a/sim/testsuite/sim/frv/fmss.cgs b/sim/testsuite/sim/frv/fmss.cgs deleted file mode 100644 index defe0690aac..00000000000 --- a/sim/testsuite/sim/frv/fmss.cgs +++ /dev/null @@ -1,146 +0,0 @@ -# frv testcase for fmss $FRi,$FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global fmss -fmss: - fmss fr16,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmss fr16,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - fmss fr16,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmss fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmss fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmss fr16,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmss fr16,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - fmss fr16,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmss fr16,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmss fr16,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmss fr16,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmss fr16,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - - fmss fr20,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmss fr20,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - fmss fr20,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmss fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmss fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - fmss fr20,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmss fr20,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - fmss fr20,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmss fr20,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmss fr20,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmss fr20,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - fmss fr20,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - - fmss fr28,fr0,fr2 - test_fr_fr fr2,fr0 - fmss fr28,fr4,fr2 - test_fr_fr fr2,fr4 - fmss fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr32 - fmss fr28,fr12,fr2 - test_fr_fr fr2,fr12 - fmss fr28,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - fmss fr28,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - fmss fr28,fr24,fr2 - test_fr_fr fr2,fr24 - fmss fr28,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr20 - test_fr_fr fr3,fr16 - fmss fr28,fr32,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr8 - fmss fr28,fr36,fr2 - test_fr_fr fr2,fr36 - fmss fr28,fr40,fr2 - test_fr_fr fr2,fr40 - fmss fr28,fr44,fr2 - test_fr_fr fr2,fr44 - fmss fr28,fr48,fr2 - test_fr_fr fr2,fr48 - fmss fr28,fr52,fr2 - test_fr_fr fr2,fr52 - - fmss fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr32 - fmss fr8,fr28,fr2 - test_fr_fr fr2,fr8 - - fmss fr32,fr36,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr8 - - pass diff --git a/sim/testsuite/sim/frv/fmsubd.cgs b/sim/testsuite/sim/frv/fmsubd.cgs deleted file mode 100644 index 6b4c943c1bb..00000000000 --- a/sim/testsuite/sim/frv/fmsubd.cgs +++ /dev/null @@ -1,144 +0,0 @@ -# frv testcase for fmsubd $GRi,$GRj,$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - double_constants - start - load_double_constants - - .global fmsubd -fmsubd: - set_dfr_dfr fr16,fr2 - fmsubd fr16,fr4,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr16,fr8,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr16,fr12,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr16,fr16,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr16,fr20,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr16,fr24,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr16,fr28,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr16,fr32,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr16,fr36,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr16,fr40,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr16,fr44,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr16,fr48,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - - fmsubd fr20,fr4,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr20,fr8,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr20,fr12,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr20,fr16,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr20,fr20,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr20,fr24,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr20,fr28,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr20,fr32,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr20,fr36,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr20,fr40,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr20,fr44,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmsubd fr20,fr48,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - - set_dfr_dfr fr16,fr2 - fmsubd fr28,fr0,fr2 - test_dfr_dfr fr2,fr0 - set_dfr_dfr fr16,fr2 - fmsubd fr28,fr4,fr2 - test_dfr_dfr fr2,fr4 - set_dfr_dfr fr16,fr2 - fmsubd fr28,fr8,fr2 - test_dfr_dfr fr2,fr8 - set_dfr_dfr fr16,fr2 - fmsubd fr28,fr12,fr2 - test_dfr_dfr fr2,fr12 - set_dfr_dfr fr16,fr2 - fmsubd fr28,fr16,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - set_dfr_dfr fr16,fr2 - fmsubd fr28,fr20,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - set_dfr_dfr fr16,fr2 - fmsubd fr28,fr24,fr2 - test_dfr_dfr fr2,fr24 - set_dfr_dfr fr16,fr2 - fmsubd fr28,fr28,fr2 - test_dfr_dfr fr2,fr28 - set_dfr_dfr fr16,fr2 - fmsubd fr28,fr32,fr2 - test_dfr_dfr fr2,fr32 - set_dfr_dfr fr16,fr2 - fmsubd fr28,fr36,fr2 - test_dfr_dfr fr2,fr36 - set_dfr_dfr fr16,fr2 - fmsubd fr28,fr40,fr2 - test_dfr_dfr fr2,fr40 - set_dfr_dfr fr16,fr2 - fmsubd fr28,fr44,fr2 - test_dfr_dfr fr2,fr44 - set_dfr_dfr fr16,fr2 - fmsubd fr28,fr48,fr2 - test_dfr_dfr fr2,fr48 - set_dfr_dfr fr16,fr2 - fmsubd fr28,fr52,fr2 - test_dfr_dfr fr2,fr52 - - set_dfr_dfr fr32,fr2 - fmsubd fr8,fr8,fr2 - test_dfr_dfr fr2,fr8 - set_dfr_dfr fr36,fr2 - fmsubd fr36,fr36,fr2 - test_dfr_dfr fr2,fr40 - - fmsubd fr32,fr36,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - - pass diff --git a/sim/testsuite/sim/frv/fmsubs.cgs b/sim/testsuite/sim/frv/fmsubs.cgs deleted file mode 100644 index 14a5bb355a3..00000000000 --- a/sim/testsuite/sim/frv/fmsubs.cgs +++ /dev/null @@ -1,144 +0,0 @@ -# frv testcase for fmsubs $GRi,$GRj,$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fmsubs -fmsubs: - set_fr_fr fr16,fr1 - fmsubs fr16,fr4,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr16,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr16,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr16,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr16,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr16,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr16,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr16,fr32,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr16,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr16,fr40,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr16,fr44,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr16,fr48,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - fmsubs fr20,fr4,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr20,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr20,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr20,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr20,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr20,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr20,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr20,fr32,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr20,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr20,fr40,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr20,fr44,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmsubs fr20,fr48,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - set_fr_fr fr16,fr1 - fmsubs fr28,fr0,fr1 - test_fr_fr fr1,fr0 - set_fr_fr fr16,fr1 - fmsubs fr28,fr4,fr1 - test_fr_fr fr1,fr4 - set_fr_fr fr16,fr1 - fmsubs fr28,fr8,fr1 - test_fr_fr fr1,fr8 - set_fr_fr fr16,fr1 - fmsubs fr28,fr12,fr1 - test_fr_fr fr1,fr12 - set_fr_fr fr16,fr1 - fmsubs fr28,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - set_fr_fr fr16,fr1 - fmsubs fr28,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - set_fr_fr fr16,fr1 - fmsubs fr28,fr24,fr1 - test_fr_fr fr1,fr24 - set_fr_fr fr16,fr1 - fmsubs fr28,fr28,fr1 - test_fr_fr fr1,fr28 - set_fr_fr fr16,fr1 - fmsubs fr28,fr32,fr1 - test_fr_fr fr1,fr32 - set_fr_fr fr16,fr1 - fmsubs fr28,fr36,fr1 - test_fr_fr fr1,fr36 - set_fr_fr fr16,fr1 - fmsubs fr28,fr40,fr1 - test_fr_fr fr1,fr40 - set_fr_fr fr16,fr1 - fmsubs fr28,fr44,fr1 - test_fr_fr fr1,fr44 - set_fr_fr fr16,fr1 - fmsubs fr28,fr48,fr1 - test_fr_fr fr1,fr48 - set_fr_fr fr16,fr1 - fmsubs fr28,fr52,fr1 - test_fr_fr fr1,fr52 - - set_fr_fr fr32,fr1 - fmsubs fr8,fr8,fr1 - test_fr_fr fr1,fr8 - set_fr_fr fr36,fr1 - fmsubs fr36,fr36,fr1 - test_fr_fr fr1,fr40 - - fmsubs fr32,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - pass diff --git a/sim/testsuite/sim/frv/fmuld.cgs b/sim/testsuite/sim/frv/fmuld.cgs deleted file mode 100644 index e06ca07675a..00000000000 --- a/sim/testsuite/sim/frv/fmuld.cgs +++ /dev/null @@ -1,126 +0,0 @@ -# frv testcase for fmuld $GRi,$GRj,$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - double_constants - start - load_double_constants - - .global fmuld -fmuld: - fmuld fr16,fr4,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr16,fr8,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr16,fr12,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr16,fr16,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr16,fr20,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr16,fr24,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr16,fr28,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr16,fr32,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr16,fr36,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr16,fr40,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr16,fr44,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr16,fr48,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - - fmuld fr20,fr4,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr20,fr8,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr20,fr12,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr20,fr16,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr20,fr20,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr20,fr24,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr20,fr28,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr20,fr32,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr20,fr36,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr20,fr40,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr20,fr44,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr20,fr48,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - - fmuld fr28,fr0,fr2 - test_dfr_dfr fr2,fr0 - fmuld fr28,fr4,fr2 - test_dfr_dfr fr2,fr4 - fmuld fr28,fr8,fr2 - test_dfr_dfr fr2,fr8 - fmuld fr28,fr12,fr2 - test_dfr_dfr fr2,fr12 - fmuld fr28,fr16,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr28,fr20,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fmuld fr28,fr24,fr2 - test_dfr_dfr fr2,fr24 - fmuld fr28,fr28,fr2 - test_dfr_dfr fr2,fr28 - fmuld fr28,fr32,fr2 - test_dfr_dfr fr2,fr32 - fmuld fr28,fr36,fr2 - test_dfr_dfr fr2,fr36 - fmuld fr28,fr40,fr2 - test_dfr_dfr fr2,fr40 - fmuld fr28,fr44,fr2 - test_dfr_dfr fr2,fr44 - fmuld fr28,fr48,fr2 - test_dfr_dfr fr2,fr48 - fmuld fr28,fr52,fr2 - test_dfr_dfr fr2,fr52 - - fmuld fr28,fr8,fr2 - test_dfr_dfr fr2,fr8 - fmuld fr8,fr28,fr2 - test_dfr_dfr fr2,fr8 - - fmuld fr32,fr36,fr2 - test_dfr_dfr fr2,fr40 - - pass diff --git a/sim/testsuite/sim/frv/fmuls.cgs b/sim/testsuite/sim/frv/fmuls.cgs deleted file mode 100644 index a92fa1ea83c..00000000000 --- a/sim/testsuite/sim/frv/fmuls.cgs +++ /dev/null @@ -1,125 +0,0 @@ -# frv testcase for fmuls $GRi,$GRj,$GRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fmuls -fmuls: - fmuls fr16,fr4,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr16,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr16,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr16,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr16,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr16,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr16,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr16,fr32,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr16,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr16,fr40,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr16,fr44,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr16,fr48,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - fmuls fr20,fr4,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr20,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr20,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr20,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr20,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr20,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr20,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr20,fr32,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr20,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr20,fr40,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr20,fr44,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr20,fr48,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - - fmuls fr28,fr0,fr1 - test_fr_fr fr1,fr0 - fmuls fr28,fr4,fr1 - test_fr_fr fr1,fr4 - fmuls fr28,fr8,fr1 - test_fr_fr fr1,fr8 - fmuls fr28,fr12,fr1 - test_fr_fr fr1,fr12 - fmuls fr28,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr28,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fmuls fr28,fr24,fr1 - test_fr_fr fr1,fr24 - fmuls fr28,fr28,fr1 - test_fr_fr fr1,fr28 - fmuls fr28,fr32,fr1 - test_fr_fr fr1,fr32 - fmuls fr28,fr36,fr1 - test_fr_fr fr1,fr36 - fmuls fr28,fr40,fr1 - test_fr_fr fr1,fr40 - fmuls fr28,fr44,fr1 - test_fr_fr fr1,fr44 - fmuls fr28,fr48,fr1 - test_fr_fr fr1,fr48 - fmuls fr28,fr52,fr1 - test_fr_fr fr1,fr52 - - fmuls fr28,fr8,fr1 - test_fr_fr fr1,fr8 - fmuls fr8,fr28,fr1 - test_fr_fr fr1,fr8 - - fmuls fr32,fr36,fr1 - test_fr_fr fr1,fr40 - - pass diff --git a/sim/testsuite/sim/frv/fnegd.cgs b/sim/testsuite/sim/frv/fnegd.cgs deleted file mode 100644 index c18721b8e72..00000000000 --- a/sim/testsuite/sim/frv/fnegd.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for fnegd $FRj,$FRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - double_constants - start - load_double_constants - - .global fnegd -fnegd: - fnegd fr0,fr2 - test_dfr_dfr fr2,fr52 - fnegd fr8,fr2 - test_dfr_dfr fr2,fr28 - fnegd fr12,fr2 - test_dfr_dfr fr2,fr24 - fnegd fr24,fr2 - test_dfr_dfr fr2,fr12 - fnegd fr28,fr2 - test_dfr_dfr fr2,fr8 - fnegd fr52,fr2 - test_dfr_dfr fr2,fr0 - - pass diff --git a/sim/testsuite/sim/frv/fnegs.cgs b/sim/testsuite/sim/frv/fnegs.cgs deleted file mode 100644 index fdb87704ab5..00000000000 --- a/sim/testsuite/sim/frv/fnegs.cgs +++ /dev/null @@ -1,25 +0,0 @@ -# frv testcase for fnegs $FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fnegs -fnegs: - fnegs fr0,fr1 - test_fr_fr fr1,fr52 - fnegs fr8,fr1 - test_fr_fr fr1,fr28 - fnegs fr12,fr1 - test_fr_fr fr1,fr24 - fnegs fr24,fr1 - test_fr_fr fr1,fr12 - fnegs fr28,fr1 - test_fr_fr fr1,fr8 - fnegs fr52,fr1 - test_fr_fr fr1,fr0 - - pass diff --git a/sim/testsuite/sim/frv/fnop.cgs b/sim/testsuite/sim/frv/fnop.cgs deleted file mode 100644 index 5e48384751a..00000000000 --- a/sim/testsuite/sim/frv/fnop.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# frv testcase for fnop -# mach: fr500 fr550 frv - - .include "testutils.inc" - - start - - .global fnop -fnop: - fnop - - pass diff --git a/sim/testsuite/sim/frv/fr400/addss.cgs b/sim/testsuite/sim/frv/fr400/addss.cgs deleted file mode 100644 index 631d5741fa5..00000000000 --- a/sim/testsuite/sim/frv/fr400/addss.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# frv testcase for addss $GRi,$GRj,$GRk -# mach: fr400 - - .include "../testutils.inc" - - start - - .global add -add_nosaturate: - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - addss gr7,gr8,gr8 - test_gr_immed 3,gr8 -add_saturate_pos: - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_immed 1,gr8 - addss gr7,gr8,gr8 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_limmed 0x4000,0x0000,gr7 - set_gr_limmed 0x4000,0x0000,gr8 - addss gr7,gr8,gr8 - test_gr_limmed 0x7fff,0xffff,gr8 - -add_saturate_neg: - set_gr_limmed 0x8000,0x0000,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - addss gr7,gr8,gr8 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0x8000,0x0001,gr7 - set_gr_limmed 0x8000,0x0001,gr8 - addss gr7,gr8,gr8 - test_gr_limmed 0x8000,0x0000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/fr400/allinsn.exp b/sim/testsuite/sim/frv/fr400/allinsn.exp deleted file mode 100644 index 53394ecb530..00000000000 --- a/sim/testsuite/sim/frv/fr400/allinsn.exp +++ /dev/null @@ -1,19 +0,0 @@ -# FRV simulator testsuite. - -if [istarget frv*-*] { - # load support procs (none yet) - # load_lib cgen.exp - # all machines - set all_machs "fr400 fr550" - set cpu_option -mcpu - - # The .cgs suffix is for "cgen .s". - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/frv/fr400/csdiv.cgs b/sim/testsuite/sim/frv/fr400/csdiv.cgs deleted file mode 100644 index 9fa6d8c6af9..00000000000 --- a/sim/testsuite/sim/frv/fr400/csdiv.cgs +++ /dev/null @@ -1,187 +0,0 @@ -# frv testcase for csdiv $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "../testutils.inc" - - start - - .global csdiv -csdiv: - set_spr_immed 0x1b1b,cccr - - ; simple division 12 / 3 - set_gr_immed 3,gr3 - set_gr_immed 12,gr1 - csdiv gr1,gr3,gr2,cc4,1 - test_gr_immed 4,gr2 - - ; Random example - set_gr_limmed 0x0123,0x4567,gr3 - set_gr_limmed 0xfedc,0xba98,gr1 - csdiv gr1,gr3,gr2,cc4,1 - test_gr_immed -1,gr2 - - ; Special case from the Arch Spec Vol 2 - and_spr_immed -33,isr ; turn off isr.edem - ; set up exception handler - set_psr_et 1 - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x170,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_gr_immed 0,gr15 - - ; divide will cause overflow - set_spr_addr ok1,lr - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 -e1: csdiv gr1,gr3,gr2,cc4,1 - test_gr_immed 1,gr15 - test_gr_limmed 0x8000,0x0000,gr2 - - ; Special case from the Arch Spec Vol 2 - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc4,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; simple division 12 / 3 - set_gr_immed 3,gr3 - set_gr_immed 12,gr1 - csdiv gr1,gr3,gr2,cc4,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; Random example - set_gr_limmed 0x0123,0x4567,gr3 - set_gr_limmed 0xfedc,0xba98,gr1 - csdiv gr1,gr3,gr2,cc4,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; Special case from the Arch Spec Vol 2 - and_spr_immed -33,isr ; turn off isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc4,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc4,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; simple division 12 / 3 - set_gr_immed 3,gr3 - set_gr_immed 12,gr1 - csdiv gr1,gr3,gr2,cc5,0 - test_gr_immed 4,gr2 - - ; Random example - set_gr_limmed 0x0123,0x4567,gr3 - set_gr_limmed 0xfedc,0xba98,gr1 - csdiv gr1,gr3,gr2,cc5,0 - test_gr_immed -1,gr2 - - ; Special case from the Arch Spec Vol 2 - and_spr_immed -33,isr ; turn off isr.edem - ; divide will cause overflow - set_spr_addr ok1,lr - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 -e2: csdiv gr1,gr3,gr2,cc5,0 - test_gr_immed 2,gr15 - test_gr_limmed 0x8000,0x0000,gr2 - - ; Special case from the Arch Spec Vol 2 - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc5,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; simple division 12 / 3 - set_gr_immed 3,gr3 - set_gr_immed 12,gr1 - csdiv gr1,gr3,gr2,cc5,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; Random example - set_gr_limmed 0x0123,0x4567,gr3 - set_gr_limmed 0xfedc,0xba98,gr1 - csdiv gr1,gr3,gr2,cc5,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; Special case from the Arch Spec Vol 2 - and_spr_immed -33,isr ; turn off isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc5,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc5,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; simple division 12 / 3 - set_gr_immed 3,gr3 - set_gr_immed 12,gr1 - csdiv gr1,gr3,gr2,cc6,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; Random example - set_gr_limmed 0x0123,0x4567,gr3 - set_gr_limmed 0xfedc,0xba98,gr1 - csdiv gr1,gr3,gr2,cc6,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; Special case from the Arch Spec Vol 2 - and_spr_immed -33,isr ; turn off isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc6,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc6,0 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; simple division 12 / 3 - set_gr_immed 3,gr3 - set_gr_immed 12,gr1 - csdiv gr1,gr3,gr2,cc7,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; Random example - set_gr_limmed 0x0123,0x4567,gr3 - set_gr_limmed 0xfedc,0xba98,gr1 - csdiv gr1,gr3,gr2,cc7,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - ; Special case from the Arch Spec Vol 2 - and_spr_immed -33,isr ; turn off isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc7,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - csdiv gr1,gr3,gr2,cc7,1 - test_gr_limmed 0x7fff,0xffff,gr2 - - pass - -ok1: ; exception handler for overflow - test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/fr400/maddaccs.cgs b/sim/testsuite/sim/frv/fr400/maddaccs.cgs deleted file mode 100644 index 98659c42c13..00000000000 --- a/sim/testsuite/sim/frv/fr400/maddaccs.cgs +++ /dev/null @@ -1,131 +0,0 @@ -# frv testcase for maddaccs $ACC40Si,$ACC40Sk -# mach: fr400 - - .include "../testutils.inc" - - start - - .global maddaccs -maddaccs: - set_accg_immed 0,accg0 - set_acc_immed 0x00000000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000000,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x0000,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0xdead0000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x0000beef,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg3 - test_acc_limmed 0xdead,0xbeef,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x0000dead,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xbeef0000,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg3 - test_acc_limmed 0xbeef,0xdead,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x11111111,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg3 - test_acc_limmed 0x2345,0x6789,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xffffffff,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 1,accg3 - test_acc_limmed 0x1234,0x5677,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg3 - test_acc_limmed 0x1234,0x5677,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x7f,accg0 - set_acc_immed 0xfffe7ffe,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x00020001,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x80,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xfffffffe,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0000,acc3 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000001,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x00000001,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - maddaccs.p acc0,acc1 - maddaccs acc2,acc3 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0x8,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0002,acc1 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - pass diff --git a/sim/testsuite/sim/frv/fr400/masaccs.cgs b/sim/testsuite/sim/frv/fr400/masaccs.cgs deleted file mode 100644 index 8fbde91f872..00000000000 --- a/sim/testsuite/sim/frv/fr400/masaccs.cgs +++ /dev/null @@ -1,151 +0,0 @@ -# frv testcase for masaccs $ACC40Si,$ACC40Sk -# mach: fr400 - - .include "../testutils.inc" - - start - - .global masaccs -masaccs: - set_accg_immed 0,accg0 - set_acc_immed 0x00000000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000000,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x0000,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0xdead0000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x0000beef,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0xdead,0xbeef,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0xdeac,0x4111,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x0000dead,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xbeef0000,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0xbeef,0xdead,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0x4111,0xdead,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x11111111,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0x2345,0x6789,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0123,0x4567,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xffffffff,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 1,accg2 - test_acc_limmed 0x1234,0x5677,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0x1234,0x5679,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0x1234,0x5677,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x1234,0x5679,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x7f,accg0 - set_acc_immed 0xfffe7ffe,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x00020001,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xfffc,0x7ffd,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x80,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xfffffffe,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x80,accg2 - test_acc_limmed 0x0000,0x0000,acc2 - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0003,acc3 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000001,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x00000001,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - masaccs.p acc0,acc0 - masaccs acc2,acc2 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0x8,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0000,acc1 - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0002,acc3 - - pass diff --git a/sim/testsuite/sim/frv/fr400/maveh.cgs b/sim/testsuite/sim/frv/fr400/maveh.cgs deleted file mode 100644 index 445e121daf6..00000000000 --- a/sim/testsuite/sim/frv/fr400/maveh.cgs +++ /dev/null @@ -1,319 +0,0 @@ -# frv testcase for maveh $FRi,$FRj,$FRj on fr400 machines -# mach: all - - .include "../testutils.inc" - - start - - .global maveh -maveh: - ; Test Rounding toward positive infinity via RDAV - or_spr_immed 0x20000000,msr0 - and_spr_immed 0xefffffff,msr0 - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - - set_fr_iimmed 0x0001,0x0000,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0002,0x0001,fr12 - - set_fr_iimmed 0x0000,0xffff,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0000,0xffff,fr12 - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xef57,0xdf78,fr12 - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xdf78,0xef57,fr12 - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x11a3,0x33c5,fr12 - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x091a,0x2b3c,fr12 - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x4000,0x4000,fr12 - - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xc000,0xc000,fr12 - - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xc000,0xc000,fr12 - - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - maveh.p fr10,fr10,fr12 - maveh fr11,fr11,fr13 - test_fr_limmed 0x8000,0x8000,fr12 - test_fr_limmed 0x7fff,0x7fff,fr13 - - ; Test Rounding toward nearest via RD - or_spr_immed 0x10000000,msr0 - and_spr_immed 0x3fffffff,msr0 - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - - set_fr_iimmed 0x0001,0x0000,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0002,0x0001,fr12 - - set_fr_iimmed 0x0000,0xffff,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xffff,0xfffe,fr12 - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xef56,0xdf77,fr12 - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xdf77,0xef56,fr12 - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x11a3,0x33c5,fr12 - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x091a,0x2b3c,fr12 - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x4000,0x4000,fr12 - - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xc000,0xbfff,fr12 - - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xbfff,0xbfff,fr12 - - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - maveh.p fr10,fr10,fr12 - maveh fr11,fr11,fr13 - test_fr_limmed 0x8000,0x8000,fr12 - test_fr_limmed 0x7fff,0x7fff,fr13 - - ; Test Rounding toward zero via RD - or_spr_immed 0x50000000,msr0 - and_spr_immed 0x7fffffff,msr0 - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - - set_fr_iimmed 0x0001,0x0000,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0001,0x0000,fr12 - - set_fr_iimmed 0x0000,0xffff,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0000,0xffff,fr12 - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xef57,0xdf78,fr12 - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xdf78,0xef57,fr12 - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x11a2,0x33c4,fr12 - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0919,0x2b3b,fr12 - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x4000,0x3fff,fr12 - - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xc000,0xc000,fr12 - - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xc000,0xc000,fr12 - - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - maveh.p fr10,fr10,fr12 - maveh fr11,fr11,fr13 - test_fr_limmed 0x8000,0x8000,fr12 - test_fr_limmed 0x7fff,0x7fff,fr13 - - ; Test Rounding toward positive infinity via RD - or_spr_immed 0x90000000,msr0 - and_spr_immed 0xbfffffff,msr0 - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - - set_fr_iimmed 0x0001,0x0000,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0002,0x0001,fr12 - - set_fr_iimmed 0x0000,0xffff,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0000,0xffff,fr12 - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xef57,0xdf78,fr12 - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xdf78,0xef57,fr12 - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x11a3,0x33c5,fr12 - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x091a,0x2b3c,fr12 - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x4000,0x4000,fr12 - - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xc000,0xc000,fr12 - - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xc000,0xc000,fr12 - - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - maveh.p fr10,fr10,fr12 - maveh fr11,fr11,fr13 - test_fr_limmed 0x8000,0x8000,fr12 - test_fr_limmed 0x7fff,0x7fff,fr13 - - ; Test Rounding toward negative infinity via RD - or_spr_immed 0xd0000000,msr0 - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - - set_fr_iimmed 0x0001,0x0000,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0001,0x0000,fr12 - - set_fr_iimmed 0x0000,0xffff,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xffff,0xfffe,fr12 - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xef56,0xdf77,fr12 - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xdf77,0xef56,fr12 - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x11a2,0x33c4,fr12 - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0919,0x2b3b,fr12 - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x4000,0x3fff,fr12 - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xc000,0xbfff,fr12 - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xbfff,0xbfff,fr12 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - maveh.p fr10,fr10,fr12 - maveh fr11,fr11,fr13 - test_fr_limmed 0x8000,0x8000,fr12 - test_fr_limmed 0x7fff,0x7fff,fr13 - - pass diff --git a/sim/testsuite/sim/frv/fr400/mclracc.cgs b/sim/testsuite/sim/frv/fr400/mclracc.cgs deleted file mode 100644 index 02975446be4..00000000000 --- a/sim/testsuite/sim/frv/fr400/mclracc.cgs +++ /dev/null @@ -1,79 +0,0 @@ -# frv testcase for mclracc $ACC40k,$A -# mach: all - - .include "../testutils.inc" - - start - - .global mclracc -mclracc: - set_accg_immed 0xff,accg0 - set_acc_immed -1,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed -1,acc1 - set_accg_immed 0xff,accg2 - set_acc_immed -1,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed -1,acc3 - - mclracc acc8,0 ; nop - test_accg_immed 0xff,accg0 - test_acc_immed -1,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -1,acc1 - test_accg_immed 0xff,accg2 - test_acc_immed -1,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed -1,acc3 - - mclracc acc8,1 ; nop - test_accg_immed 0xff,accg0 - test_acc_immed -1,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -1,acc1 - test_accg_immed 0xff,accg2 - test_acc_immed -1,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed -1,acc3 - - mclracc acc2,0 - test_accg_immed 0xff,accg0 - test_acc_immed -1,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -1,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed -1,acc3 - - mclracc acc3,1 - test_accg_immed 0xff,accg0 - test_acc_immed -1,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -1,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - - mclracc acc0,0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -1,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - - mclracc acc0,1 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - - pass diff --git a/sim/testsuite/sim/frv/fr400/mhdseth.cgs b/sim/testsuite/sim/frv/fr400/mhdseth.cgs deleted file mode 100644 index b99c996f78b..00000000000 --- a/sim/testsuite/sim/frv/fr400/mhdseth.cgs +++ /dev/null @@ -1,22 +0,0 @@ -# frv testcase for mhdseth $s12,$FRk -# mach: all - - .include "../testutils.inc" - - start - - .global mhdseth -mhdseth: - set_fr_immed 0,fr1 - mhdseth 0,fr1 - test_fr_iimmed 0,fr1 - mhdseth 1,fr1 - test_fr_iimmed 0x08000800,fr1 - mhdseth 0xf,fr1 - test_fr_iimmed 0x78007800,fr1 - mhdseth -16,fr1 - test_fr_iimmed 0x80008000,fr1 - mhdseth -1,fr1 - test_fr_iimmed 0xf800f800,fr1 - - pass diff --git a/sim/testsuite/sim/frv/fr400/mhdsets.cgs b/sim/testsuite/sim/frv/fr400/mhdsets.cgs deleted file mode 100644 index c495cb7130c..00000000000 --- a/sim/testsuite/sim/frv/fr400/mhdsets.cgs +++ /dev/null @@ -1,20 +0,0 @@ -# frv testcase for mhdsets $s12,$FRk -# mach: all - - .include "../testutils.inc" - - start - - .global mhdsets -mhdsets: - set_fr_immed 0,fr1 - mhdsets 0,fr1 - test_fr_iimmed 0,fr1 - mhdsets 1,fr1 - test_fr_iimmed 0x00010001,fr1 - mhdsets 0x7ff,fr1 - test_fr_iimmed 0x07ff07ff,fr1 - mhdsets -2048,fr1 - test_fr_iimmed 0xf800f800,fr1 - - pass diff --git a/sim/testsuite/sim/frv/fr400/mhsethih.cgs b/sim/testsuite/sim/frv/fr400/mhsethih.cgs deleted file mode 100644 index fed9d2335e7..00000000000 --- a/sim/testsuite/sim/frv/fr400/mhsethih.cgs +++ /dev/null @@ -1,22 +0,0 @@ -# frv testcase for mhsethih $s12,$FRk -# mach: all - - .include "../testutils.inc" - - start - - .global mhsethih -mhsethih: - set_fr_immed 0,fr1 - mhsethih 0,fr1 - test_fr_iimmed 0,fr1 - mhsethih 1,fr1 - test_fr_iimmed 0x08000000,fr1 - mhsethih 0xf,fr1 - test_fr_iimmed 0x78000000,fr1 - mhsethih -16,fr1 - test_fr_iimmed 0x80000000,fr1 - mhsethih -1,fr1 - test_fr_iimmed 0xf8000000,fr1 - - pass diff --git a/sim/testsuite/sim/frv/fr400/mhsethis.cgs b/sim/testsuite/sim/frv/fr400/mhsethis.cgs deleted file mode 100644 index ade9102a5e3..00000000000 --- a/sim/testsuite/sim/frv/fr400/mhsethis.cgs +++ /dev/null @@ -1,25 +0,0 @@ -# frv testcase for mhsethis $s12,$FRk -# mach: all - - .include "../testutils.inc" - - start - - .global mhsethis -mhsethis: - set_fr_immed 0,fr1 - mhsethis 0,fr1 - test_fr_iimmed 0,fr1 - mhsethis 1,fr1 - test_fr_iimmed 0x00010000,fr1 - mhsethis 0x7ff,fr1 - test_fr_iimmed 0x07ff0000,fr1 - mhsethis -2048,fr1 - test_fr_iimmed 0xf8000000,fr1 - - ; Try parallel set of hi and lo at the same time - mhsethis.p 1,fr1 - mhsetlos 2,fr1 - test_fr_iimmed 0x00010002,fr1 - - pass diff --git a/sim/testsuite/sim/frv/fr400/mhsetloh.cgs b/sim/testsuite/sim/frv/fr400/mhsetloh.cgs deleted file mode 100644 index 1dedb836eca..00000000000 --- a/sim/testsuite/sim/frv/fr400/mhsetloh.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# frv testcase for mhsetloh $s12,$FRk -# mach: all - - .include "../testutils.inc" - - start - - .global mhsetloh -mhsetloh: - set_fr_immed 0,fr1 - mhsetloh 0,fr1 - test_fr_iimmed 0,fr1 - mhsetloh 1,fr1 - test_fr_iimmed 0x0000800,fr1 - mhsetloh 0xf,fr1 - test_fr_iimmed 0x00007800,fr1 - mhsetloh -16,fr1 - test_fr_iimmed 0x00008000,fr1 - mhsetloh -1,fr1 - test_fr_iimmed 0x0000f800,fr1 - - ; Try parallel write to both hi and lo - mhsetloh.p 1,fr1 - mhsethih 0xf,fr1 - test_fr_iimmed 0x78000800,fr1 - - pass diff --git a/sim/testsuite/sim/frv/fr400/mhsetlos.cgs b/sim/testsuite/sim/frv/fr400/mhsetlos.cgs deleted file mode 100644 index 8e8839ab6e9..00000000000 --- a/sim/testsuite/sim/frv/fr400/mhsetlos.cgs +++ /dev/null @@ -1,25 +0,0 @@ -# frv testcase for mhsetlos $s12,$FRk -# mach: all - - .include "../testutils.inc" - - start - - .global mhsetlos -mhsetlos: - set_fr_immed 0,fr1 - mhsetlos 0,fr1 - test_fr_iimmed 0,fr1 - mhsetlos 1,fr1 - test_fr_iimmed 0x00000001,fr1 - mhsetlos 0x7ff,fr1 - test_fr_iimmed 0x000007ff,fr1 - mhsetlos -2048,fr1 - test_fr_iimmed 0x0000f800,fr1 - - ; Try parallel set of hi and lo at the same time - mhsethis.p 1,fr1 - mhsetlos 2,fr1 - test_fr_iimmed 0x00010002,fr1 - - pass diff --git a/sim/testsuite/sim/frv/fr400/movgs.cgs b/sim/testsuite/sim/frv/fr400/movgs.cgs deleted file mode 100644 index 4e22aab5b5d..00000000000 --- a/sim/testsuite/sim/frv/fr400/movgs.cgs +++ /dev/null @@ -1,50 +0,0 @@ -# frv testcase for movgs $GRj,iacc0[hl] -# mach: fr400 - - .include "../testutils.inc" - - start - - .global movgs -IACC0H: - set_gr_limmed 0xdead,0xbeef,gr8 - and_spr_immed 0,iacc0h - movgs gr8,iacc0h - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,iacc0h -SPR280: - ; try alternate names for iacc0h - and_spr_immed 0,280 - movgs gr8,spr[280] ; iacc0h is spr number 280 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,spr[280] - -IACC0L: - set_gr_limmed 0xdead,0xbeef,gr8 - and_spr_immed 0,iacc0l - movgs gr8,iacc0l - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,iacc0l -SPR281: - ; try alternate names for iacc0l - and_spr_immed 0,281 - movgs gr8,spr[281] ; iacc0l is spr number 281 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,spr[281] - -IACC0L_SPR281: - ; try crossing between iacc0l and spr[281] - and_spr_immed 0,281 - and_spr_immed 0,iacc0l - movgs gr8,spr[281] ; iacc0l is spr number 281 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,iacc0l - -SPR280_IACC0H: - and_spr_immed 0,280 - and_spr_immed 0,iacc0h - movgs gr8,iacc0h ; iacc0h is spr number 280 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,spr[280] - - pass diff --git a/sim/testsuite/sim/frv/fr400/movsg.cgs b/sim/testsuite/sim/frv/fr400/movsg.cgs deleted file mode 100644 index 3f9df25faf7..00000000000 --- a/sim/testsuite/sim/frv/fr400/movsg.cgs +++ /dev/null @@ -1,65 +0,0 @@ -# frv testcase for movsg iacc0[hl],$GRj -# mach: fr400 - - .include "../testutils.inc" - - start - - .global movsg -Iacc0h: - set_spr_limmed 0xdead,0xbeef,iacc0h - set_gr_limmed 0,0,gr8 - movsg iacc0h,gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,iacc0h -Iacc0l: - set_spr_limmed 0xdead,0xbeef,iacc0l - set_gr_limmed 0,0,gr8 - movsg iacc0l,gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,iacc0l - -Spr280: - set_spr_limmed 0xdead,0xbeef,spr[280] - set_gr_limmed 0,0,gr8 - movsg spr[280],gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,spr[280] -Spr281: - set_spr_limmed 0xdead,0xbeef,spr[281] - set_gr_limmed 0,0,gr8 - movsg spr[281],gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,spr[281] - -Iacc0h_spr280: - set_spr_limmed 0xdead,0xbeef,spr[280] - set_spr_limmed 0xdead,0xbeef,iacc0h - set_gr_limmed 0,0,gr8 - movsg iacc0h,gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,spr[280] -Iacc0l_spr281: - set_spr_limmed 0xdead,0xbeef,spr[281] - set_spr_limmed 0xdead,0xbeef,iacc0l - set_gr_limmed 0,0,gr8 - movsg iacc0l,gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,spr[281] - -Spr280_iacc0h: - set_spr_limmed 0xdead,0xbeef,spr[280] - set_spr_limmed 0xdead,0xbeef,iacc0h - set_gr_limmed 0,0,gr8 - movsg spr[280],gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,iacc0h -Spr281_iacc0l: - set_spr_limmed 0xdead,0xbeef,spr[281] - set_spr_limmed 0xdead,0xbeef,iacc0l - set_gr_limmed 0,0,gr8 - movsg spr[281],gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,iacc0l - - pass diff --git a/sim/testsuite/sim/frv/fr400/msubaccs.cgs b/sim/testsuite/sim/frv/fr400/msubaccs.cgs deleted file mode 100644 index f0aba1dbfb1..00000000000 --- a/sim/testsuite/sim/frv/fr400/msubaccs.cgs +++ /dev/null @@ -1,131 +0,0 @@ -# frv testcase for msubaccs $ACC40Si,$ACC40Sk -# mach: fr400 - - .include "../testutils.inc" - - start - - .global msubaccs -msubaccs: - set_accg_immed 0,accg0 - set_acc_immed 0x00000000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000000,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x0000,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0xdead0000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x0000beef,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg3 - test_acc_limmed 0xdeac,0x4111,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x0000dead,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xbeef0000,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg3 - test_acc_limmed 0x4111,0xdead,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x11111111,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg3 - test_acc_limmed 0x0123,0x4567,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xffffffff,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg3 - test_acc_limmed 0x1234,0x5679,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg3 - test_acc_limmed 0x1234,0x5679,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x7f,accg0 - set_acc_immed 0xfffffffe,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xfffffffe,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x80,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000002,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0000,acc3 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_accg_immed 0,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000001,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x00000001,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0x00000000,acc3 - msubaccs.p acc0,acc1 - msubaccs acc2,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0x8,msr1 ; msr0.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0000,acc1 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - pass diff --git a/sim/testsuite/sim/frv/fr400/scutss.cgs b/sim/testsuite/sim/frv/fr400/scutss.cgs deleted file mode 100644 index aa115b96618..00000000000 --- a/sim/testsuite/sim/frv/fr400/scutss.cgs +++ /dev/null @@ -1,642 +0,0 @@ -# frv testcase for scutss $FRj,$FRk -# mach: fr400 - - .include "../testutils.inc" - - start - - .global scutss -scutss: - set_spr_immed 0xffffffe7,iacc0h - set_spr_immed 0x89abcdef,iacc0l - - set_gr_immed 0,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xffe7,gr11 - - set_gr_immed 1,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xffcf,gr11 - - set_gr_immed 2,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xff9e,gr11 - - set_gr_immed 3,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xff3c,gr11 - - set_gr_immed 4,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xfe78,gr11 - - set_gr_immed 5,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xfcf1,gr11 - - set_gr_immed 6,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xf9e2,gr11 - - set_gr_immed 7,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xf3c4,gr11 - - set_gr_immed 8,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xe789,gr11 - - set_gr_immed 9,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xcf13,gr11 - - set_gr_immed 10,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0x9e26,gr11 - - set_gr_immed 11,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0x3c4d,gr11 - - set_gr_immed 12,gr10 - scutss gr10,gr11 - test_gr_limmed 0xfffe,0x789a,gr11 - - set_gr_immed 13,gr10 - scutss gr10,gr11 - test_gr_limmed 0xfffc,0xf135,gr11 - - set_gr_immed 14,gr10 - scutss gr10,gr11 - test_gr_limmed 0xfff9,0xe26a,gr11 - - set_gr_immed 15,gr10 - scutss gr10,gr11 - test_gr_limmed 0xfff3,0xc4d5,gr11 - - set_gr_immed 16,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffe7,0x89ab,gr11 - - set_gr_immed 17,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffcf,0x1357,gr11 - - set_gr_immed 18,gr10 - scutss gr10,gr11 - test_gr_limmed 0xff9e,0x26af,gr11 - - set_gr_immed 19,gr10 - scutss gr10,gr11 - test_gr_limmed 0xff3c,0x4d5e,gr11 - - set_gr_immed 20,gr10 - scutss gr10,gr11 - test_gr_limmed 0xfe78,0x9abc,gr11 - - set_gr_immed 21,gr10 - scutss gr10,gr11 - test_gr_limmed 0xfcf1,0x3579,gr11 - - set_gr_immed 22,gr10 - scutss gr10,gr11 - test_gr_limmed 0xf9e2,0x6af3,gr11 - - set_gr_immed 23,gr10 - scutss gr10,gr11 - test_gr_limmed 0xf3c4,0xd5e6,gr11 - - set_gr_immed 24,gr10 - scutss gr10,gr11 - test_gr_limmed 0xe789,0xabcd,gr11 - - set_gr_immed 25,gr10 - scutss gr10,gr11 - test_gr_limmed 0xcf13,0x579b,gr11 - - set_gr_immed 26,gr10 - scutss gr10,gr11 - test_gr_limmed 0x9e26,0xaf37,gr11 - - set_gr_immed 27,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 28,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 29,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 30,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 31,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 32,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 33,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 34,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 35,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 36,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 37,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 38,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 39,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 40,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 41,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 42,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 43,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 44,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 45,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 46,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 47,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 48,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 49,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 50,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 51,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 52,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 53,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 54,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 55,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 56,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 57,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 58,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 59,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 60,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 61,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 62,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 63,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 - - set_gr_immed 64,gr10 ; same as -64 - scutss gr10,gr11 - test_gr_immed -1,gr11 - - set_gr_immed 128,gr10 ; same as 0 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xffe7,gr11 - - .global scutss2 -scutss2: - set_spr_immed 0xe789abcd,iacc0h - set_spr_immed 0xefa5a5a5,iacc0l - - set_gr_limmed 0xffff,0xffff,gr10 ; -1 - scutss gr10,gr11 - test_gr_limmed 0xf3c4,0xd5e6,gr11 - - set_gr_limmed 0x0000,0x007e,gr10 ; -2 (only lower 7 bits matter) - scutss gr10,gr11 - test_gr_limmed 0xf9e2,0x6af3,gr11 - - set_gr_immed -3,gr10 - scutss gr10,gr11 - test_gr_limmed 0xfcf1,0x3579,gr11 - - set_gr_immed -4,gr10 - scutss gr10,gr11 - test_gr_limmed 0xfe78,0x9abc,gr11 - - set_gr_immed -5,gr10 - scutss gr10,gr11 - test_gr_limmed 0xff3c,0x4d5e,gr11 - - set_gr_immed -6,gr10 - scutss gr10,gr11 - test_gr_limmed 0xff9e,0x26af,gr11 - - set_gr_immed -7,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffcf,0x1357,gr11 - - set_gr_immed -8,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffe7,0x89ab,gr11 - - set_gr_immed -9,gr10 - scutss gr10,gr11 - test_gr_limmed 0xfff3,0xc4d5,gr11 - - set_gr_immed -10,gr10 - scutss gr10,gr11 - test_gr_limmed 0xfff9,0xe26a,gr11 - - set_gr_immed -11,gr10 - scutss gr10,gr11 - test_gr_limmed 0xfffc,0xf135,gr11 - - set_gr_immed -12,gr10 - scutss gr10,gr11 - test_gr_limmed 0xfffe,0x789a,gr11 - - set_gr_immed -13,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0x3c4d,gr11 - - set_gr_immed -14,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0x9e26,gr11 - - set_gr_immed -15,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xcf13,gr11 - - set_gr_immed -16,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xe789,gr11 - - set_gr_immed -17,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xf3c4,gr11 - - set_gr_immed -18,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xf9e2,gr11 - - set_gr_immed -19,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xfcf1,gr11 - - set_gr_immed -20,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xfe78,gr11 - - set_gr_immed -21,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xff3c,gr11 - - set_gr_immed -22,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xff9e,gr11 - - set_gr_immed -23,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xffcf,gr11 - - set_gr_immed -24,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xffe7,gr11 - - set_gr_immed -25,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xfff3,gr11 - - set_gr_immed -26,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xfff9,gr11 - - set_gr_immed -27,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xfffc,gr11 - - set_gr_immed -28,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xfffe,gr11 - - set_gr_immed -29,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xffff,gr11 - - set_gr_immed -30,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xffff,gr11 - - set_gr_immed -31,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xffff,gr11 - - set_gr_immed -32,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xffff,gr11 - - set_gr_limmed 0,64,gr10 ; same as -32 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xffff,gr11 - - set_spr_immed 0x6789abcd,iacc0h - set_spr_immed 0xefa5a5a5,iacc0l - - set_gr_limmed 0xffff,0xffff,gr10 - scutss gr10,gr11 - test_gr_limmed 0x33c4,0xd5e6,gr11 - - set_gr_limmed 0x0000,0x007e,gr10 ; -2 (only lower 7 bits matter) - scutss gr10,gr11 - test_gr_limmed 0x19e2,0x6af3,gr11 - - set_gr_immed -3,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0cf1,0x3579,gr11 - - set_gr_immed -4,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0678,0x9abc,gr11 - - set_gr_immed -5,gr10 - scutss gr10,gr11 - test_gr_limmed 0x033c,0x4d5e,gr11 - - set_gr_immed -6,gr10 - scutss gr10,gr11 - test_gr_limmed 0x019e,0x26af,gr11 - - set_gr_immed -7,gr10 - scutss gr10,gr11 - test_gr_limmed 0x00cf,0x1357,gr11 - - set_gr_immed -8,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0067,0x89ab,gr11 - - set_gr_immed -9,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0033,0xc4d5,gr11 - - set_gr_immed -10,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0019,0xe26a,gr11 - - set_gr_immed -11,gr10 - scutss gr10,gr11 - test_gr_limmed 0x000c,0xf135,gr11 - - set_gr_immed -12,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0006,0x789a,gr11 - - set_gr_immed -13,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0003,0x3c4d,gr11 - - set_gr_immed -14,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0001,0x9e26,gr11 - - set_gr_immed -15,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0xcf13,gr11 - - set_gr_immed -16,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x6789,gr11 - - set_gr_immed -17,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x33c4,gr11 - - set_gr_immed -18,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x19e2,gr11 - - set_gr_immed -19,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x0cf1,gr11 - - set_gr_immed -20,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x0678,gr11 - - set_gr_immed -21,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x033c,gr11 - - set_gr_immed -22,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x019e,gr11 - - set_gr_immed -23,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x00cf,gr11 - - set_gr_immed -24,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x0067,gr11 - - set_gr_immed -25,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x0033,gr11 - - set_gr_immed -26,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x0019,gr11 - - set_gr_immed -27,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x000c,gr11 - - set_gr_immed -28,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x0006,gr11 - - set_gr_immed -29,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x0003,gr11 - - set_gr_immed -30,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x0001,gr11 - - set_gr_immed -31,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x0000,gr11 - - set_gr_immed -32,gr10 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x0000,gr11 - - set_gr_immed 64,gr10 ; same as -32 - scutss gr10,gr11 - test_gr_limmed 0x0000,0x0000,gr11 - - ; Examples from the customer (modified for iacc0) - set_spr_immed 0xffffffff,iacc0h - set_spr_immed 0xffe00000,iacc0l - - set_gr_limmed 0,16,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xffe0,gr11 - - set_gr_limmed 0,17,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xffc0,gr11 - - set_gr_limmed 0,18,gr10 - scutss gr10,gr11 - test_gr_limmed 0xffff,0xff80,gr11 - - set_spr_immed 0,iacc0h - set_spr_immed 0x003fffff,iacc0l - - set_gr_limmed 0,40,gr10 - scutss gr10,gr11 - test_gr_limmed 0x3fff,0xff00,gr11 - - set_gr_limmed 0,41,gr10 - scutss gr10,gr11 - test_gr_limmed 0x7fff,0xfe00,gr11 - - set_spr_immed 0x7f,iacc0h - set_spr_immed 0xffe00000,iacc0l - - set_gr_limmed 0,40,gr10 - scutss gr10,gr11 - test_gr_limmed 0x7fff,0xffff,gr11 ; saturated - - set_gr_limmed 0,41,gr10 - scutss gr10,gr11 - test_gr_limmed 0x7fff,0xffff,gr11 ; saturated - - set_gr_limmed 0,42,gr10 - scutss gr10,gr11 - test_gr_limmed 0x7fff,0xffff,gr11 ; saturated - - set_spr_immed 0x08,iacc0h - set_spr_immed 0x003fffff,iacc0l - - set_gr_limmed 0,40,gr10 - scutss gr10,gr11 - test_gr_limmed 0x7fff,0xffff,gr11 ; saturated - - set_gr_limmed 0,41,gr10 - scutss gr10,gr11 - test_gr_limmed 0x7fff,0xffff,gr11 ; saturated - - set_spr_immed 0xffffffff,iacc0h - set_spr_immed 0xefe00000,iacc0l - - set_gr_limmed 0,40,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 ; saturated - - set_gr_limmed 0,41,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 ; saturated - - set_gr_limmed 0,42,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 ; saturated - - set_spr_immed 0x80000000,iacc0h - set_spr_immed 0x003fffff,iacc0l - - set_gr_limmed 0,16,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 ; saturated - - set_gr_limmed 0,17,gr10 - scutss gr10,gr11 - test_gr_limmed 0x8000,0x0000,gr11 ; saturated - - set_spr_immed 0xaf5a5a5a,iacc0h - set_spr_immed 0x5a5a5a5a,iacc0l - - set_gr_limmed 0xffff,0xfffc,gr10 - scutss gr10,gr11 - test_gr_limmed 0xfaf5,0xa5a5,gr11 - - set_spr_immed 0x2f5a5a5a,iacc0h - set_spr_immed 0x5a5a5a5a,iacc0l - - set_gr_limmed 0xffff,0xfff9,gr10 - scutss gr10,gr11 - test_gr_limmed 0x005e,0xb4b4,gr11 - - pass diff --git a/sim/testsuite/sim/frv/fr400/sdiv.cgs b/sim/testsuite/sim/frv/fr400/sdiv.cgs deleted file mode 100644 index b9c03cfeea3..00000000000 --- a/sim/testsuite/sim/frv/fr400/sdiv.cgs +++ /dev/null @@ -1,71 +0,0 @@ -# frv testcase for sdiv $GRi,$GRj,$GRk -# mach: all - - .include "../testutils.inc" - - start - - .global sdiv -sdiv: - ; simple division 12 / 3 - set_gr_immed 3,gr3 - set_gr_immed 12,gr1 - sdiv gr1,gr3,gr2 - test_gr_immed 4,gr2 - - ; Random example - set_gr_limmed 0x0123,0x4567,gr3 - set_gr_limmed 0xfedc,0xba98,gr1 - sdiv gr1,gr3,gr2 - test_gr_immed -1,gr2 - - ; Special case from the Arch Spec Vol 2 - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - sdiv gr1,gr3,gr2 - test_gr_limmed 0x7fff,0xffff,gr2 - test_spr_bits 0x4,2,1,isr ; isr.aexc is set - - and_spr_immed -33,isr ; turn off isr.edem - ; set up exception handler - set_psr_et 1 - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x170,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_gr_immed 0,gr15 - - ; divide will cause overflow - set_spr_addr ok1,lr - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 -e1: sdiv gr1,gr3,gr2 ; overflow - test_gr_immed 1,gr15 - test_gr_limmed 0x8000,0x0000,gr2; gr2 updated - - ; divide by zero - set_spr_addr ok2,lr - set_gr_immed 0xdeadbeef,gr2 -e2: sdiv gr1,gr0,gr2 ; divide by zero - test_gr_immed 2,gr15 ; handler called - test_gr_immed 0xdeadbeef,gr2 ; gr2 not updated. - - pass - -ok1: ; exception handler for overflow - test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - inc_gr_immed 1,gr15 - rett 0 - fail - -ok2: ; exception handler for divide by zero - test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/fr400/sdivi.cgs b/sim/testsuite/sim/frv/fr400/sdivi.cgs deleted file mode 100644 index fda573e5842..00000000000 --- a/sim/testsuite/sim/frv/fr400/sdivi.cgs +++ /dev/null @@ -1,70 +0,0 @@ -# frv testcase for sdivi $GRi,$s12,$GRk -# mach: all - - .include "../testutils.inc" - - start - - .global sdivi -sdivi: - ; simple division 12 / 3 - set_gr_immed 12,gr1 - sdivi gr1,3,gr2 - test_gr_immed 4,gr2 - - ; Random example - set_gr_limmed 0xfedc,0xba98,gr1 - sdivi gr1,0x7ff,gr2 - test_gr_limmed 0xffff,0xdb93,gr2 - - ; Random negative example - set_gr_limmed 0xfedc,0xba98,gr1 - sdivi gr1,-2048,gr2 - test_gr_immed 0x2468,gr2 - - ; Special case from the Arch Spec Vol 2 - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_limmed 0x8000,0x0000,gr1 - sdivi gr1,-1,gr2 - test_gr_limmed 0x7fff,0xffff,gr2 - test_spr_bits 0x4,2,1,isr ; isr.aexc is set - - and_spr_immed -33,isr ; turn off isr.edem - ; set up exception handler - set_psr_et 1 - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x170,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_gr_immed 0,gr15 - - ; divide will cause overflow - set_spr_addr ok1,lr - set_gr_limmed 0x8000,0x0000,gr1 -e1: sdivi gr1,-1,gr2 - test_gr_immed 1,gr15 - test_gr_limmed 0x8000,0x0000,gr2 - - ; divide by zero - set_spr_addr ok2,lr -e2: sdivi gr1,0,gr2 ; divide by zero - test_gr_immed 2,gr15 - - pass - -ok1: ; exception handler for overflow - test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - inc_gr_immed 1,gr15 - rett 0 - fail - -ok2: ; exception handler for divide by zero - test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/fr400/slass.cgs b/sim/testsuite/sim/frv/fr400/slass.cgs deleted file mode 100644 index 01000520375..00000000000 --- a/sim/testsuite/sim/frv/fr400/slass.cgs +++ /dev/null @@ -1,104 +0,0 @@ -# frv testcase for slass $GRi,$GRj,$GRk -# mach: fr400 - - .include "../testutils.inc" - - start - - .global sll -slass0: - set_gr_immed 0,gr7 ; Shift by 0 - set_gr_immed 2,gr8 - slass gr8,gr7,gr6 - test_gr_immed 2,gr8 - test_gr_immed 0,gr7 - test_gr_immed 2,gr6 -slass1: - set_gr_immed 1,gr7 ; Shift by 1 - set_gr_immed 2,gr8 - slass gr8,gr7,gr6 - test_gr_immed 2,gr8 - test_gr_immed 1,gr7 - test_gr_immed 4,gr6 - -slass2: - set_gr_immed 31,gr7 ; Shift 1 by 31 - set_gr_immed 1,gr8 - slass gr8,gr7,gr6 - test_gr_immed 1,gr8 - test_gr_immed 31,gr7 - test_gr_limmed 0x7fff,0xffff,gr6 - -slass3: - set_gr_immed 31,gr7 ; Shift -1 by 31 - set_gr_immed -1,gr8 - slass gr8,gr7,gr6 - test_gr_immed -1,gr8 - test_gr_immed 31,gr7 - test_gr_limmed 0x8000,0x0000,gr6 - -slass4: - set_gr_immed 14,gr7 ; Shift 0xffff0000 by 14 - set_gr_limmed 0xffff,0x0000,gr8 - slass gr8,gr7,gr6 - test_gr_limmed 0xffff,0x0000,gr8 - test_gr_immed 14,gr7 - test_gr_limmed 0xc000,0x0000,gr6 - -slass5: - set_gr_immed 15,gr7 ; Shift 0xffff0000 by 15 - set_gr_limmed 0xffff,0x0000,gr8 - slass gr8,gr7,gr6 - test_gr_limmed 0xffff,0x0000,gr8 - test_gr_immed 15,gr7 - test_gr_limmed 0x8000,0x0000,gr6 - -slass6: - set_gr_immed 20,gr7 ; Shift 0xffff0000 by 20 - set_gr_limmed 0xffff,0x0000,gr8 - slass gr8,gr7,gr6 - test_gr_limmed 0xffff,0x0000,gr8 - test_gr_immed 20,gr7 - test_gr_limmed 0x8000,0x0000,gr6 - -slass7: - set_gr_immed 14,gr7 ; Shift 0x0000ffff by 14 - set_gr_limmed 0x0000,0xffff,gr8 - slass gr8,gr7,gr6 - test_gr_limmed 0x0000,0xffff,gr8 - test_gr_immed 14,gr7 - test_gr_limmed 0x3fff,0xc000,gr6 - -slass8: - set_gr_immed 15,gr7 ; Shift 0x0000ffff by 15 - set_gr_limmed 0x0000,0xffff,gr8 - slass gr8,gr7,gr6 - test_gr_limmed 0x0000,0xffff,gr8 - test_gr_immed 15,gr7 - test_gr_limmed 0x7fff,0x8000,gr6 - -slass9: - set_gr_immed 20,gr7 ; Shift 0x0000ffff by 20 - set_gr_limmed 0x0000,0xffff,gr8 - slass gr8,gr7,gr6 - test_gr_limmed 0x0000,0xffff,gr8 - test_gr_immed 20,gr7 - test_gr_limmed 0x7fff,0xffff,gr6 - -slass10: - set_gr_immed 30,gr7 ; Shift 1 by 30 - set_gr_immed 1,gr8 - slass gr8,gr7,gr6 - test_gr_immed 1,gr8 - test_gr_immed 30,gr7 - test_gr_limmed 0x4000,0x0000,gr6 - -slass11: - set_gr_immed 30,gr7 ; Shift -1 by 30 - set_gr_immed -1,gr8 - slass gr8,gr7,gr6 - test_gr_immed -1,gr8 - test_gr_immed 30,gr7 - test_gr_limmed 0xc000,0000,gr6 - - pass diff --git a/sim/testsuite/sim/frv/fr400/smass.cgs b/sim/testsuite/sim/frv/fr400/smass.cgs deleted file mode 100644 index 3df0fa5ddc7..00000000000 --- a/sim/testsuite/sim/frv/fr400/smass.cgs +++ /dev/null @@ -1,359 +0,0 @@ -# frv testcase for smass $GRi,$GRj -# mach: fr400 - - .include "../testutils.inc" - - start - - .global smass -smass1: - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed 3,gr7 - test_gr_immed 2,gr8 - test_spr_immed 7,iacc0l ; result 3*2+1 - test_spr_immed 0,iacc0h -smass2: - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed 1,gr7 - test_gr_immed 2,gr8 - test_spr_immed 3,iacc0l ; result 1*2+1 - test_spr_immed 0,iacc0h -smass3: - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed 1,gr8 - test_gr_immed 2,gr7 - test_spr_immed 3,iacc0l ; result 2*1+1 - test_spr_immed 0,iacc0h -smass4: - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed 2,gr8 - test_gr_immed 0,gr7 - test_spr_immed 1,iacc0l ; result 0*2+1 - test_spr_immed 0,iacc0h -smass5: - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed 0,gr8 - test_gr_immed 2,gr7 - test_spr_immed 1,iacc0l ; result 2*0+1 - test_spr_immed 0,iacc0h -smass6: - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed 2,gr8 - test_gr_limmed 0x3fff,0xffff,gr7 - test_spr_limmed 0x7fff,0xffff,iacc0l ; 3fffffff*2+1 - test_spr_immed 0,iacc0h -smass7: - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed 2,gr8 - test_gr_limmed 0x4000,0x0000,gr7 - test_spr_limmed 0x8000,0x0001,iacc0l ; 40000000*2+1 - test_spr_immed 0,iacc0h -smass8: - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed 4,gr8 - test_gr_limmed 0x4000,0x0000,gr7 - test_spr_immed 1,iacc0l ; 40000000*4+1 - test_spr_immed 1,iacc0h -smass9: - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_immed 0x00000002,iacc0l ; 7fffffff*7fffffff+1 - test_spr_limmed 0x3fff,0xffff,iacc0h -smass10: - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed 2,gr8 - test_gr_immed -3,gr7 - test_spr_immed -5,iacc0l ; -3*2+1 - test_spr_immed -1,iacc0h -smass11: - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed -2,gr8 - test_gr_immed 3,gr7 - test_spr_immed -5,iacc0l ; 3*-2+1 - test_spr_immed -1,iacc0h -smass12: - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed -2,gr8 - test_gr_immed 1,gr7 - test_spr_immed -1,iacc0l ; 1*-2+1 - test_spr_immed -1,iacc0h -smass13: - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed 1,gr8 - test_gr_immed -2,gr7 - test_spr_immed -1,iacc0l ; -2*1+1 - test_spr_immed -1,iacc0h -smass14: - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed -2,gr8 - test_gr_immed 0,gr7 - test_spr_immed 1,iacc0l ; 0*-2+1 - test_spr_immed 0,iacc0h -smass15: - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed 0,gr8 - test_gr_immed -2,gr7 - test_spr_immed 1,iacc0l ; -2*0+1 - test_spr_immed 0,iacc0h -smass16: - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed -2,gr8 - test_gr_limmed 0x2000,0x0001,gr7 - test_spr_limmed 0xbfff,0xffff,iacc0l ; 20000001*-2+1 - test_spr_limmed 0xffff,0xffff,iacc0h -smass17: - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed -2,gr8 - test_gr_limmed 0x4000,0x0000,gr7 - test_spr_limmed 0x8000,0x0001,iacc0l ; 40000000*-2+1 - test_spr_limmed 0xffff,0xffff,iacc0h -smass18: - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed -2,gr8 - test_gr_limmed 0x4000,0x0001,gr7 - test_spr_limmed 0x7fff,0xffff,iacc0l ; 40000001*-2+1 - test_spr_limmed 0xffff,0xffff,iacc0h -smass19: - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed -4,gr8 - test_gr_limmed 0x4000,0x0000,gr7 - test_spr_limmed 0x0000,0x0001,iacc0l ; 40000000*-4+1 - test_spr_limmed 0xffff,0xffff,iacc0h -smass20: - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x8000,0x0000,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_limmed 0x8000,0x0001,iacc0l ; 7fffffff*80000000+1 - test_spr_limmed 0xc000,0x0000,iacc0h -smass21: - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed -2,gr8 - test_gr_immed -3,gr7 - test_spr_immed 7,iacc0l ; -3*-2+1 - test_spr_immed 0,iacc0h -smass22: - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed -2,gr8 - test_gr_immed -1,gr7 - test_spr_immed 3,iacc0l ; -1*-2+1 - test_spr_immed 0,iacc0h -smass23: - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed -1,gr8 - test_gr_immed -2,gr7 - test_spr_immed 3,iacc0l ; -2*-1+1 - test_spr_immed 0,iacc0h -smass24: - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed -2,gr8 - test_gr_limmed 0xc000,0x0001,gr7 - test_spr_limmed 0x7fff,0xffff,iacc0l ; c0000001*-2+1 - test_spr_immed 0,iacc0h -smass25: - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed -2,gr8 - test_gr_limmed 0xc000,0x0000,gr7 - test_spr_limmed 0x8000,0x0001,iacc0l ; c0000000*-2+1 - test_spr_immed 0,iacc0h -smass26: - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_immed -4,gr8 - test_gr_limmed 0xc000,0x0000,gr7 - test_spr_immed 0x00000001,iacc0l ; c0000000*-4+1 - test_spr_immed 1,iacc0h -smass27: - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_gr_limmed 0x8000,0x0001,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_limmed 0x8000,0x0001,gr8 - test_gr_limmed 0x8000,0x0001,gr7 - test_spr_immed 0x00000002,iacc0l ; 80000001*80000001+1 - test_spr_limmed 0x3fff,0xffff,iacc0h -smass28: - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smass gr7,gr8 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_limmed 0x8000,0x0000,gr7 - test_spr_immed 0x00000001,iacc0l ; 80000000*80000000+1 - test_spr_limmed 0x4000,0x0000,iacc0h - -smass29: - set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (pos) - set_gr_limmed 0x7fff,0xffff,gr8 - set_spr_limmed 0xffff,0xfffe,iacc0l - set_spr_limmed 0x4000,0x0000,iacc0h - smass gr7,gr8 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffff*7fffffff+ - test_spr_limmed 0x7fff,0xffff,iacc0h ; 40000000fffffffe - -smass30: - set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (pos) - set_gr_limmed 0x7fff,0xffff,gr8 - set_spr_limmed 0xffff,0xffff,iacc0l - set_spr_limmed 0x4000,0x0000,iacc0h - smass gr7,gr8 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffff*7fffffff+ - test_spr_limmed 0x7fff,0xffff,iacc0h ; 40000000ffffffff - -smass31: - set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (pos) - set_gr_limmed 0x7fff,0xffff,gr8 - set_spr_limmed 0xffff,0xffff,iacc0l - set_spr_limmed 0x7fff,0xffff,iacc0h - smass gr7,gr8 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffff*7fffffff+ - test_spr_limmed 0x7fff,0xffff,iacc0h ; 7fffffffffffffff - -smass32: - set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (neg) - set_gr_limmed 0x8000,0x0000,gr8 - set_spr_limmed 0x8000,0x0000,iacc0l - set_spr_limmed 0xbfff,0xffff,iacc0h - smass gr7,gr8 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+ - test_spr_limmed 0x8000,0x0000,iacc0h ; bfffffff80000000 - -smass33: - set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (neg) - set_gr_limmed 0x8000,0x0000,gr8 - set_spr_limmed 0x7fff,0xffff,iacc0l - set_spr_limmed 0xbfff,0xffff,iacc0h - smass gr7,gr8 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+ - test_spr_limmed 0x8000,0x0000,iacc0h ; bfffffff7fffffff - -smass34: - set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (neg) - set_gr_limmed 0x8000,0x0000,gr8 - set_spr_limmed 0x0000,0x0000,iacc0l - set_spr_limmed 0x8000,0x0000,iacc0h - smass gr7,gr8 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+ - test_spr_limmed 0x8000,0x0000,iacc0h ; 8000000000000000 - - pass diff --git a/sim/testsuite/sim/frv/fr400/smsss.cgs b/sim/testsuite/sim/frv/fr400/smsss.cgs deleted file mode 100644 index 56efa5642c9..00000000000 --- a/sim/testsuite/sim/frv/fr400/smsss.cgs +++ /dev/null @@ -1,354 +0,0 @@ -# frv testcase for smsss $GRi,$GRj -# mach: fr400 - - .include "../testutils.inc" - - start - - .global smsss -smsss1: - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 7,iacc0l - smsss gr7,gr8 - test_gr_immed 3,gr7 - test_gr_immed 2,gr8 - test_spr_immed 1,iacc0l ; result 7-3*2 - test_spr_immed 0,iacc0h -smsss2: - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 3,iacc0l - smsss gr7,gr8 - test_gr_immed 1,gr7 - test_gr_immed 2,gr8 - test_spr_immed 1,iacc0l ; result 3-1*2 - test_spr_immed 0,iacc0h -smsss3: - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 3,iacc0l - smsss gr7,gr8 - test_gr_immed 1,gr8 - test_gr_immed 2,gr7 - test_spr_immed 1,iacc0l ; result 3-2*1 - test_spr_immed 0,iacc0h -smsss4: - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smsss gr7,gr8 - test_gr_immed 2,gr8 - test_gr_immed 0,gr7 - test_spr_immed 1,iacc0l ; result 1-0*2 - test_spr_immed 0,iacc0h -smsss5: - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smsss gr7,gr8 - test_gr_immed 0,gr8 - test_gr_immed 2,gr7 - test_spr_immed 1,iacc0l ; result 1-2*0 - test_spr_immed 0,iacc0h -smsss6: - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - set_spr_immed -1,iacc0h - set_spr_immed -1,iacc0l - smsss gr7,gr8 - test_gr_immed 2,gr8 - test_gr_limmed 0x3fff,0xffff,gr7 - test_spr_limmed 0x8000,0x0001,iacc0l ; -1-3fffffff*2 - test_spr_immed -1,iacc0h -smsss7: - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - set_spr_immed -1,iacc0h - set_spr_limmed 0x8000,0x0001,iacc0l - smsss gr7,gr8 - test_gr_immed 2,gr8 - test_gr_limmed 0x4000,0x0000,gr7 - test_spr_immed 1,iacc0l ; ffffffff80000001-40000000*2 - test_spr_immed -1,iacc0h -smsss8: - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - set_spr_immed -1,iacc0h - set_spr_immed 1,iacc0l - smsss gr7,gr8 - test_gr_immed 4,gr8 - test_gr_limmed 0x4000,0x0000,gr7 - test_spr_immed 1,iacc0l ; ffffffff00000001-40000000*4 - test_spr_immed -2,iacc0h -smsss9: - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - set_spr_limmed 0x7fff,0xffff,iacc0h - set_spr_immed -1,iacc0l - smsss gr7,gr8 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_limmed 0xffff,0xfffe,iacc0l ; 7fffffffffffffff-7fffffff*7fffffff - test_spr_limmed 0x4000,0x0000,iacc0h -smsss10: - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_spr_immed -1,iacc0h - set_spr_immed -5,iacc0l - smsss gr7,gr8 - test_gr_immed 2,gr8 - test_gr_immed -3,gr7 - test_spr_immed 1,iacc0l ; -5-(-3*2) - test_spr_immed 0,iacc0h -smsss11: - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_spr_immed -1,iacc0h - set_spr_immed -5,iacc0l - smsss gr7,gr8 - test_gr_immed -2,gr8 - test_gr_immed 3,gr7 - test_spr_immed 1,iacc0l ; -5-(3*-2) - test_spr_immed 0,iacc0h -smsss12: - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_spr_immed -1,iacc0h - set_spr_immed -1,iacc0l - smsss gr7,gr8 - test_gr_immed -2,gr8 - test_gr_immed 1,gr7 - test_spr_immed 1,iacc0l ; -1-(1*-2) - test_spr_immed 0,iacc0h -smsss13: - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_spr_immed -1,iacc0h - set_spr_immed -1,iacc0l - smsss gr7,gr8 - test_gr_immed 1,gr8 - test_gr_immed -2,gr7 - test_spr_immed 1,iacc0l ; -1-(-2*1) - test_spr_immed 0,iacc0h -smsss14: - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smsss gr7,gr8 - test_gr_immed -2,gr8 - test_gr_immed 0,gr7 - test_spr_immed 1,iacc0l ; 1-(0*-2) - test_spr_immed 0,iacc0h -smsss15: - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smsss gr7,gr8 - test_gr_immed 0,gr8 - test_gr_immed -2,gr7 - test_spr_immed 1,iacc0l ; 1-(-2*0) - test_spr_immed 0,iacc0h -smsss16: - set_gr_limmed 0x2000,0x0000,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_spr_immed 0,iacc0h - set_spr_limmed 0x3fff,0xffff,iacc0l - smsss gr7,gr8 - test_gr_immed -2,gr8 - test_gr_limmed 0x2000,0x0000,gr7 - test_spr_limmed 0x7fff,0xffff,iacc0l - test_spr_immed 0,iacc0h ; 3fffffff-20000001*-2 -smsss17: - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smsss gr7,gr8 - test_gr_immed -2,gr8 - test_gr_limmed 0x4000,0x0000,gr7 - test_spr_limmed 0x8000,0x0001,iacc0l ; 1-40000000*-2 - test_spr_immed 0,iacc0h -smsss18: - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_spr_immed -1,iacc0h - set_spr_immed -1,iacc0l - smsss gr7,gr8 - test_gr_immed -2,gr8 - test_gr_limmed 0x4000,0x0000,gr7 - test_spr_limmed 0x7fff,0xffff,iacc0l - test_spr_immed 0,iacc0h ; -1-40000000*-2 -smsss19: - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 1,iacc0l - smsss gr7,gr8 - test_gr_immed -4,gr8 - test_gr_limmed 0x4000,0x0000,gr7 - test_spr_immed 1,iacc0l ; 200000001-(40000000*-4) - test_spr_immed 1,iacc0h -smsss20: - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x7fff,0xffff,gr8 - set_spr_limmed 0xbfff,0xffff,iacc0h - set_spr_limmed 0x0000,0x0001,iacc0l - smsss gr7,gr8 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_immed 0,iacc0l ; bfffffff00000001-(7fffffff*7fffffff) - test_spr_limmed 0x8000,0x0000,iacc0h -smsss21: - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 7,iacc0l - smsss gr7,gr8 - test_gr_immed -2,gr8 - test_gr_immed -3,gr7 - test_spr_immed 1,iacc0l ; 7-(-3*-2) - test_spr_immed 0,iacc0h -smsss22: - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 3,iacc0l - smsss gr7,gr8 - test_gr_immed -2,gr8 - test_gr_immed -1,gr7 - test_spr_immed 1,iacc0l ; 3-(-1*-2) - test_spr_immed 0,iacc0h -smsss23: - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - set_spr_immed 0,iacc0h - set_spr_immed 3,iacc0l - smsss gr7,gr8 - test_gr_immed -1,gr8 - test_gr_immed -2,gr7 - test_spr_immed 1,iacc0l ; 3-(-2*-1) - test_spr_immed 0,iacc0h -smsss24: - set_gr_immed -32768,gr7 ; 31 bit result - set_gr_immed -32768,gr8 - set_spr_immed 0,iacc0h - set_spr_limmed 0xbfff,0xffff,iacc0l - smsss gr7,gr8 - test_gr_immed -32768,gr8 - test_gr_immed -32768,gr7 - test_spr_limmed 0x7fff,0xffff,iacc0l ; 7ffffffb-(-2*-2) - test_spr_immed 0,iacc0h -smsss25: - set_gr_immed 0xffff,gr7 ; 32 bit result - set_gr_immed 0xffff,gr8 - set_spr_immed 1,iacc0h - set_spr_limmed 0xfffe,0x0000,iacc0l - smsss gr7,gr8 - test_gr_immed 0xffff,gr8 - test_gr_immed 0xffff,gr7 - test_spr_limmed 0xffff,0xffff,iacc0l ; 1fffe0000-ffff*ffff - test_spr_immed 0,iacc0h -smsss26: - set_gr_limmed 0x0001,0x0000,gr7 ; 33 bit result - set_gr_limmed 0x0001,0x0000,gr8 - set_spr_immed 2,iacc0h - set_spr_immed 1,iacc0l - smsss gr7,gr8 - test_gr_limmed 0x0001,0x0000,gr8 - test_gr_limmed 0x0001,0x0000,gr7 - test_spr_immed 1,iacc0l ; 0x200000001-0x10000*0x10000 - test_spr_immed 1,iacc0h -smsss27: - set_gr_immed -2,gr7 ; almost max positive result - set_gr_immed -2,gr8 - set_spr_limmed 0x7fff,0xffff,iacc0h - set_spr_limmed 0xffff,0xffff,iacc0l - smsss gr7,gr8 - test_gr_immed -2,gr8 - test_gr_immed -2,gr7 - test_spr_limmed 0xffff,0xfffb,iacc0l ; maxpos - (-2*-2) - test_spr_limmed 0x7fff,0xffff,iacc0h -smsss28: - set_gr_immed 0,gr7 ; max positive result - set_gr_immed 0,gr8 - set_spr_limmed 0x7fff,0xffff,iacc0h - set_spr_limmed 0xffff,0xffff,iacc0l - smsss gr7,gr8 - test_gr_immed 0,gr8 - test_gr_immed 0,gr7 - test_spr_limmed 0xffff,0xffff,iacc0l ; maxpos-(0*0) - test_spr_limmed 0x7fff,0xffff,iacc0h -smsss29: - set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (pos) - set_gr_limmed 0x8000,0x0000,gr8 - set_spr_limmed 0x4000,0x0000,iacc0h - set_spr_limmed 0x7fff,0xffff,iacc0l - smsss gr7,gr8 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_limmed 0xffff,0xffff,iacc0l ; 400000007fffffff - - test_spr_limmed 0x7fff,0xffff,iacc0h ; 0x80000000*0x7fffffff -smsss30: - set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (pos) - set_gr_limmed 0x8000,0x0000,gr8 - set_spr_limmed 0x4000,0x0000,iacc0h - set_spr_limmed 0x8000,0x0000,iacc0l - smsss gr7,gr8 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_limmed 0xffff,0xffff,iacc0l ; 4000000080000000 - - test_spr_limmed 0x7fff,0xffff,iacc0h ; 0x80000000*0x7fffffff - -smsss31: - set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (pos) - set_gr_limmed 0x8000,0x0000,gr8 - set_spr_limmed 0xffff,0xffff,iacc0l - set_spr_limmed 0x7fff,0xffff,iacc0h - smsss gr7,gr8 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffffffffffff - - test_spr_limmed 0x7fff,0xffff,iacc0h ; 80000000*80000000 -smsss32: - set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (neg) - set_gr_limmed 0x7fff,0xffff,gr8 - set_spr_immed 1,iacc0l - set_spr_limmed 0xbfff,0xffff,iacc0h - smsss gr7,gr8 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_limmed 0x0000,0x0000,iacc0l ; bfffffff00000001 - - test_spr_limmed 0x8000,0x0000,iacc0h ; 0x7fffffff*0x7fffffff -smsss33: - set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (neg) - set_gr_limmed 0x7fff,0xffff,gr8 - set_spr_immed 0,iacc0l - set_spr_limmed 0xbfff,0xffff,iacc0h - smsss gr7,gr8 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+ - test_spr_limmed 0x8000,0x0000,iacc0h ; bfffffff7fffffff -smsss34: - set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (neg) - set_gr_limmed 0x7fff,0xffff,gr8 - set_spr_limmed 0x0000,0x0000,iacc0l - set_spr_limmed 0x8000,0x0000,iacc0h - smsss gr7,gr8 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_limmed 0x0000,0x0000,iacc0l ; 8000000000000000- - test_spr_limmed 0x8000,0x0000,iacc0h ; 7fffffff*7fffffff+ - - pass diff --git a/sim/testsuite/sim/frv/fr400/smu.cgs b/sim/testsuite/sim/frv/fr400/smu.cgs deleted file mode 100644 index d0087df10d0..00000000000 --- a/sim/testsuite/sim/frv/fr400/smu.cgs +++ /dev/null @@ -1,237 +0,0 @@ -# frv testcase for smu $GRi,$GRj -# mach: fr400 - - .include "../testutils.inc" - - start - - .global smu -smu1: - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - smu gr7,gr8 - test_gr_immed 3,gr7 - test_gr_immed 2,gr8 - test_spr_immed 6,iacc0l - test_spr_immed 0,iacc0h -smu2: - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - smu gr7,gr8 - test_gr_immed 1,gr7 - test_gr_immed 2,gr8 - test_spr_immed 2,iacc0l - test_spr_immed 0,iacc0h -smu3: - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - smu gr7,gr8 - test_gr_immed 1,gr8 - test_gr_immed 2,gr7 - test_spr_immed 2,iacc0l - test_spr_immed 0,iacc0h -smu4: - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - smu gr7,gr8 - test_gr_immed 2,gr8 - test_gr_immed 0,gr7 - test_spr_immed 0,iacc0l - test_spr_immed 0,iacc0h -smu5: - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - smu gr7,gr8 - test_gr_immed 0,gr8 - test_gr_immed 2,gr7 - test_spr_immed 0,iacc0l - test_spr_immed 0,iacc0h -smu6: - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - smu gr7,gr8 - test_gr_immed 2,gr8 - test_gr_limmed 0x3fff,0xffff,gr7 - test_spr_limmed 0x7fff,0xfffe,iacc0l - test_spr_immed 0,iacc0h -smu7: - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - smu gr7,gr8 - test_gr_immed 2,gr8 - test_gr_limmed 0x4000,0x0000,gr7 - test_spr_limmed 0x8000,0x0000,iacc0l - test_spr_immed 0,iacc0h -smu8: - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - smu gr7,gr8 - test_gr_immed 4,gr8 - test_gr_limmed 0x4000,0x0000,gr7 - test_spr_immed 0,iacc0l - test_spr_immed 1,iacc0h -smu9: - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - smu gr7,gr8 - test_gr_limmed 0x7fff,0xffff,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_immed 0x00000001,iacc0l - test_spr_limmed 0x3fff,0xffff,iacc0h -smu10: - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - smu gr7,gr8 - test_gr_immed 2,gr8 - test_gr_immed -3,gr7 - test_spr_immed -6,iacc0l - test_spr_immed -1,iacc0h -smu11: - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - smu gr7,gr8 - test_gr_immed -2,gr8 - test_gr_immed 3,gr7 - test_spr_immed -6,iacc0l - test_spr_immed -1,iacc0h -smu12: - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - smu gr7,gr8 - test_gr_immed -2,gr8 - test_gr_immed 1,gr7 - test_spr_immed -2,iacc0l - test_spr_immed -1,iacc0h -smu13: - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - smu gr7,gr8 - test_gr_immed 1,gr8 - test_gr_immed -2,gr7 - test_spr_immed -2,iacc0l - test_spr_immed -1,iacc0h -smu14: - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - smu gr7,gr8 - test_gr_immed -2,gr8 - test_gr_immed 0,gr7 - test_spr_immed 0,iacc0l - test_spr_immed 0,iacc0h -smu15: - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - smu gr7,gr8 - test_gr_immed 0,gr8 - test_gr_immed -2,gr7 - test_spr_immed 0,iacc0l - test_spr_immed 0,iacc0h -smu16: - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - smu gr7,gr8 - test_gr_immed -2,gr8 - test_gr_limmed 0x2000,0x0001,gr7 - test_spr_limmed 0xbfff,0xfffe,iacc0l - test_spr_limmed 0xffff,0xffff,iacc0h -smu17: - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - smu gr7,gr8 - test_gr_immed -2,gr8 - test_gr_limmed 0x4000,0x0000,gr7 - test_spr_limmed 0x8000,0x0000,iacc0l - test_spr_limmed 0xffff,0xffff,iacc0h -smu18: - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_gr_immed -2,gr8 - smu gr7,gr8 - test_gr_immed -2,gr8 - test_gr_limmed 0x4000,0x0001,gr7 - test_spr_limmed 0x7fff,0xfffe,iacc0l - test_spr_limmed 0xffff,0xffff,iacc0h -smu19: - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - smu gr7,gr8 - test_gr_immed -4,gr8 - test_gr_limmed 0x4000,0x0000,gr7 - test_spr_limmed 0x0000,0x0000,iacc0l - test_spr_limmed 0xffff,0xffff,iacc0h -smu20: - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x8000,0x0000,gr8 - smu gr7,gr8 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_limmed 0x7fff,0xffff,gr7 - test_spr_limmed 0x8000,0x0000,iacc0l - test_spr_limmed 0xc000,0x0000,iacc0h -smu21: - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - smu gr7,gr8 - test_gr_immed -2,gr8 - test_gr_immed -3,gr7 - test_spr_immed 6,iacc0l - test_spr_immed 0,iacc0h -smu22: - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - smu gr7,gr8 - test_gr_immed -2,gr8 - test_gr_immed -1,gr7 - test_spr_immed 2,iacc0l - test_spr_immed 0,iacc0h -smu23: - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - smu gr7,gr8 - test_gr_immed -1,gr8 - test_gr_immed -2,gr7 - test_spr_immed 2,iacc0l - test_spr_immed 0,iacc0h -smu24: - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - smu gr7,gr8 - test_gr_immed -2,gr8 - test_gr_limmed 0xc000,0x0001,gr7 - test_spr_limmed 0x7fff,0xfffe,iacc0l - test_spr_immed 0,iacc0h -smu25: - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - smu gr7,gr8 - test_gr_immed -2,gr8 - test_gr_limmed 0xc000,0x0000,gr7 - test_spr_limmed 0x8000,0x0000,iacc0l - test_spr_immed 0,iacc0h -smu26: - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - smu gr7,gr8 - test_gr_immed -4,gr8 - test_gr_limmed 0xc000,0x0000,gr7 - test_spr_immed 0x00000000,iacc0l - test_spr_immed 1,iacc0h -smu27: - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_gr_limmed 0x8000,0x0001,gr8 - smu gr7,gr8 - test_gr_limmed 0x8000,0x0001,gr8 - test_gr_limmed 0x8000,0x0001,gr7 - test_spr_immed 0x00000001,iacc0l - test_spr_limmed 0x3fff,0xffff,iacc0h -smu28: - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - smu gr7,gr8 - test_gr_limmed 0x8000,0x0000,gr8 - test_gr_limmed 0x8000,0x0000,gr7 - test_spr_immed 0x00000000,iacc0l - test_spr_limmed 0x4000,0x0000,iacc0h - - pass diff --git a/sim/testsuite/sim/frv/fr400/subss.cgs b/sim/testsuite/sim/frv/fr400/subss.cgs deleted file mode 100644 index cbaafb5bac7..00000000000 --- a/sim/testsuite/sim/frv/fr400/subss.cgs +++ /dev/null @@ -1,43 +0,0 @@ -# frv testcase for subss $GRi,$GRj,$GRk -# mach: fr400 - - .include "../testutils.inc" - - start - - .global sub -sub_no_saturate: - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - subss gr8,gr7,gr8 - test_gr_immed 1,gr8 - - set_gr_immed 2,gr7 - set_gr_immed 1,gr8 - subss gr8,gr7,gr8 - test_gr_limmed 0xffff,0xffff,gr8 - -sub_saturate_neg: - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - subss gr8,gr7,gr8 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0x7fff,0xffff,gr7 - set_gr_limmed 0xffff,0xfff0,gr8 - subss gr8,gr7,gr8 - test_gr_limmed 0x8000,0x0000,gr8 - -sub_saturate_pos: - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0x7fff,0xffff,gr8 - subss gr8,gr7,gr8 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_immed 0x0010,gr8 - set_gr_limmed 0x8000,0x0000,gr7 - subss gr8,gr7,gr8 - test_gr_limmed 0x7fff,0xffff,gr8 - - - pass diff --git a/sim/testsuite/sim/frv/fr400/udiv.cgs b/sim/testsuite/sim/frv/fr400/udiv.cgs deleted file mode 100644 index dd92bcd0442..00000000000 --- a/sim/testsuite/sim/frv/fr400/udiv.cgs +++ /dev/null @@ -1,46 +0,0 @@ -# frv testcase for udiv $GRi,$GRj,$GRk -# mach: fr400 - - .include "../testutils.inc" - - start - - .global udiv -udiv: - ; simple division 12 / 3 - set_gr_immed 0x00000003,gr2 - set_gr_immed 0x0000000c,gr3 - udiv gr3,gr2,gr3 - test_gr_immed 0x00000003,gr2 - test_gr_immed 0x00000004,gr3 - - ; example 1 from udiv in the fr30 manual - set_gr_limmed 0x0123,0x4567,gr2 - set_gr_limmed 0xfedc,0xba98,gr3 - udiv gr3,gr2,gr3 - test_gr_limmed 0x0123,0x4567,gr2 - test_gr_immed 0x000000e0,gr3 - - ; set up exception handler - set_psr_et 1 - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x170,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_gr_immed 0,gr15 - - ; divide by zero - set_spr_addr ok1,lr -e1: udiv gr1,gr0,gr2 ; divide by zero - test_gr_immed 1,gr15 - - pass - -ok1: ; exception handler for divide by zero - test_spr_bits 0x18,3,0x1,isr ; isr.dtt is set - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/fr400/udivi.cgs b/sim/testsuite/sim/frv/fr400/udivi.cgs deleted file mode 100644 index 69a7937a983..00000000000 --- a/sim/testsuite/sim/frv/fr400/udivi.cgs +++ /dev/null @@ -1,47 +0,0 @@ -# frv testcase for udivi $GRi,$s12,$GRk -# mach: fr400 - - .include "../testutils.inc" - - start - - .global udivi -udivi: - ; simple division 12 / 3 - set_gr_immed 0x0000000c,gr3 - udivi gr3,3,gr3 - test_gr_immed 0x00000004,gr3 - - ; random example - set_gr_limmed 0xfedc,0xba98,gr3 - udivi gr3,0x7ff,gr3 - test_gr_limmed 0x001f,0xdf93,gr3 - - ; random example - set_gr_limmed 0xffff,0xffff,gr3 - udivi gr3,-2048,gr3 - test_gr_immed 1,gr3 - - ; set up exception handler - set_psr_et 1 - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x170,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_gr_immed 0,gr15 - - ; divide by zero - set_spr_addr ok1,lr -e1: udivi gr1,0,gr2 ; divide by zero - test_gr_immed 1,gr15 - - pass - -ok1: ; exception handler for divide by zero - test_spr_bits 0x18,3,0x1,isr ; isr.dtt is set - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/fr500/allinsn.exp b/sim/testsuite/sim/frv/fr500/allinsn.exp deleted file mode 100644 index 7d192593efb..00000000000 --- a/sim/testsuite/sim/frv/fr500/allinsn.exp +++ /dev/null @@ -1,19 +0,0 @@ -# FRV simulator testsuite. - -if [istarget frv*-*] { - # load support procs (none yet) - # load_lib cgen.exp - # all machines - set all_machs "frv fr500 fr550" - set cpu_option -mcpu - - # The .cgs suffix is for "cgen .s". - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/frv/fr500/cmqaddhss.cgs b/sim/testsuite/sim/frv/fr500/cmqaddhss.cgs deleted file mode 100644 index 9c886205b1d..00000000000 --- a/sim/testsuite/sim/frv/fr500/cmqaddhss.cgs +++ /dev/null @@ -1,444 +0,0 @@ -# frv testcase for cmqaddhss $FRi,$FRj,$FRj,$CCi,$cond -# mach: frv fr500 - - .include "../testutils.inc" - - start - - .global cmqaddhss -cmqaddhss: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhss fr10,fr12,fr14,cc0,1 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhss fr10,fr12,fr14,cc0,1 - test_fr_limmed 0xbeef,0xdead,fr14 - test_fr_limmed 0x2345,0x6789,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqaddhss fr10,fr12,fr14,cc0,1 - test_fr_limmed 0x1233,0x5677,fr14 - test_fr_limmed 0x7fff,0x7fff,fr15 - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0xffff,0xfffe,fr12 - set_fr_iimmed 0xfffe,0xfffe,fr13 - cmqaddhss fr10,fr12,fr14,cc4,1 - test_fr_limmed 0x8000,0x8000,fr14 - test_fr_limmed 0x8000,0x8000,fr15 - test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x7fff,0x0000,fr12 - set_fr_iimmed 0x0000,0x8000,fr13 - cmqaddhss.p fr10,fr10,fr14,cc4,1 - cmqaddhss fr12,fr12,fr16,cc4,1 - test_fr_limmed 0x0002,0x0002,fr14 - test_fr_limmed 0xfffe,0xfffe,fr15 - test_fr_limmed 0x7fff,0x0000,fr16 - test_fr_limmed 0x0000,0x8000,fr17 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0x9,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhss fr10,fr12,fr14,cc1,0 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhss fr10,fr12,fr14,cc1,0 - test_fr_limmed 0xbeef,0xdead,fr14 - test_fr_limmed 0x2345,0x6789,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqaddhss fr10,fr12,fr14,cc1,0 - test_fr_limmed 0x1233,0x5677,fr14 - test_fr_limmed 0x7fff,0x7fff,fr15 - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0xffff,0xfffe,fr12 - set_fr_iimmed 0xfffe,0xfffe,fr13 - cmqaddhss fr10,fr12,fr14,cc5,0 - test_fr_limmed 0x8000,0x8000,fr14 - test_fr_limmed 0x8000,0x8000,fr15 - test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x7fff,0x0000,fr12 - set_fr_iimmed 0x0000,0x8000,fr13 - cmqaddhss.p fr10,fr10,fr14,cc5,0 - cmqaddhss fr12,fr12,fr16,cc5,0 - test_fr_limmed 0x0002,0x0002,fr14 - test_fr_limmed 0xfffe,0xfffe,fr15 - test_fr_limmed 0x7fff,0x0000,fr16 - test_fr_limmed 0x0000,0x8000,fr17 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0x9,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhss fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhss fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqaddhss fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0xffff,0xfffe,fr12 - set_fr_iimmed 0xfffe,0xfffe,fr13 - cmqaddhss fr10,fr12,fr14,cc4,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x7fff,0x0000,fr12 - set_fr_iimmed 0x0000,0x8000,fr13 - cmqaddhss.p fr10,fr10,fr14,cc4,0 - cmqaddhss fr12,fr12,fr16,cc4,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhss fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhss fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqaddhss fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0xffff,0xfffe,fr12 - set_fr_iimmed 0xfffe,0xfffe,fr13 - cmqaddhss fr10,fr12,fr14,cc5,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x7fff,0x0000,fr12 - set_fr_iimmed 0x0000,0x8000,fr13 - cmqaddhss.p fr10,fr10,fr14,cc5,1 - cmqaddhss fr12,fr12,fr16,cc5,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhss fr10,fr12,fr14,cc2,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhss fr10,fr12,fr14,cc2,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqaddhss fr10,fr12,fr14,cc2,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0xffff,0xfffe,fr12 - set_fr_iimmed 0xfffe,0xfffe,fr13 - cmqaddhss fr10,fr12,fr14,cc6,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x7fff,0x0000,fr12 - set_fr_iimmed 0x0000,0x8000,fr13 - cmqaddhss.p fr10,fr10,fr14,cc6,1 - cmqaddhss fr12,fr12,fr16,cc6,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set -; - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhss fr10,fr12,fr14,cc3,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhss fr10,fr12,fr14,cc3,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqaddhss fr10,fr12,fr14,cc3,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0xffff,0xfffe,fr12 - set_fr_iimmed 0xfffe,0xfffe,fr13 - cmqaddhss fr10,fr12,fr14,cc7,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x7fff,0x0000,fr12 - set_fr_iimmed 0x0000,0x8000,fr13 - cmqaddhss.p fr10,fr10,fr14,cc7,1 - cmqaddhss fr12,fr12,fr16,cc7,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - pass diff --git a/sim/testsuite/sim/frv/fr500/cmqaddhus.cgs b/sim/testsuite/sim/frv/fr500/cmqaddhus.cgs deleted file mode 100644 index 5b29c9a93b0..00000000000 --- a/sim/testsuite/sim/frv/fr500/cmqaddhus.cgs +++ /dev/null @@ -1,360 +0,0 @@ -# frv testcase for cmqaddhus $FRi,$FRj,$FRj,$CCi,$cond -# mach: frv fr500 - - .include "../testutils.inc" - - start - - .global cmqaddhus -cmqaddhus: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhus fr10,fr12,fr14,cc0,1 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhus fr10,fr12,fr14,cc0,1 - test_fr_limmed 0xbeef,0xdead,fr14 - test_fr_limmed 0x2345,0x6789,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - set_fr_iimmed 0x0002,0x0001,fr12 - set_fr_iimmed 0x0001,0x0002,fr13 - cmqaddhus fr10,fr12,fr14,cc4,1 - test_fr_limmed 0x8000,0x7fff,fr14 - test_fr_limmed 0xffff,0xffff,fr15 - test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0xfffe,0xfffe,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqaddhus.p fr10,fr10,fr14,cc4,1 - cmqaddhus fr12,fr12,fr16,cc4,1 - test_fr_limmed 0x0004,0x0002,fr14 - test_fr_limmed 0x0002,0x0002,fr15 - test_fr_limmed 0xffff,0xffff,fr16 - test_fr_limmed 0xffff,0xffff,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xf,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhus fr10,fr12,fr14,cc1,0 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhus fr10,fr12,fr14,cc1,0 - test_fr_limmed 0xbeef,0xdead,fr14 - test_fr_limmed 0x2345,0x6789,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - set_fr_iimmed 0x0002,0x0001,fr12 - set_fr_iimmed 0x0001,0x0002,fr13 - cmqaddhus fr10,fr12,fr14,cc5,0 - test_fr_limmed 0x8000,0x7fff,fr14 - test_fr_limmed 0xffff,0xffff,fr15 - test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0xfffe,0xfffe,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqaddhus.p fr10,fr10,fr14,cc5,0 - cmqaddhus fr12,fr12,fr16,cc5,0 - test_fr_limmed 0x0004,0x0002,fr14 - test_fr_limmed 0x0002,0x0002,fr15 - test_fr_limmed 0xffff,0xffff,fr16 - test_fr_limmed 0xffff,0xffff,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xf,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhus fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhus fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - set_fr_iimmed 0x0002,0x0001,fr12 - set_fr_iimmed 0x0001,0x0002,fr13 - cmqaddhus fr10,fr12,fr14,cc4,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0xfffe,0xfffe,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqaddhus.p fr10,fr10,fr14,cc4,0 - cmqaddhus fr12,fr12,fr16,cc4,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhus fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhus fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - set_fr_iimmed 0x0002,0x0001,fr12 - set_fr_iimmed 0x0001,0x0002,fr13 - cmqaddhus fr10,fr12,fr14,cc5,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0xfffe,0xfffe,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqaddhus.p fr10,fr10,fr14,cc5,1 - cmqaddhus fr12,fr12,fr16,cc5,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhus fr10,fr12,fr14,cc2,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhus fr10,fr12,fr14,cc2,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - set_fr_iimmed 0x0002,0x0001,fr12 - set_fr_iimmed 0x0001,0x0002,fr13 - cmqaddhus fr10,fr12,fr14,cc6,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0xfffe,0xfffe,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqaddhus.p fr10,fr10,fr14,cc6,0 - cmqaddhus fr12,fr12,fr16,cc6,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhus fr10,fr12,fr14,cc3,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhus fr10,fr12,fr14,cc3,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - set_fr_iimmed 0x0002,0x0001,fr12 - set_fr_iimmed 0x0001,0x0002,fr13 - cmqaddhus fr10,fr12,fr14,cc7,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0xfffe,0xfffe,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqaddhus.p fr10,fr10,fr14,cc7,0 - cmqaddhus fr12,fr12,fr16,cc7,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - pass diff --git a/sim/testsuite/sim/frv/fr500/cmqsubhss.cgs b/sim/testsuite/sim/frv/fr500/cmqsubhss.cgs deleted file mode 100644 index 4dbee66c7e6..00000000000 --- a/sim/testsuite/sim/frv/fr500/cmqsubhss.cgs +++ /dev/null @@ -1,448 +0,0 @@ -# frv testcase for cmqsubhss $FRi,$FRj,$FRj,$CCi,$cond -# mach: frv fr500 - - .include "../testutils.inc" - - start - - .global msubhss -msubhss: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqsubhss fr10,fr12,fr14,cc0,1 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0x4111,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqsubhss fr10,fr12,fr14,cc0,1 - test_fr_limmed 0x4111,0xdead,fr14 - test_fr_limmed 0x0123,0x4567,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0xfffe,0xffff,fr13 - cmqsubhss fr10,fr12,fr14,cc0,1 - test_fr_limmed 0x1235,0x5679,fr14 - test_fr_limmed 0x7fff,0x7fff,fr15 - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhss fr10,fr12,fr14,cc4,1 - test_fr_limmed 0x8000,0x8000,fr14 - test_fr_limmed 0x8000,0x8000,fr15 - test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x8000,0x8000,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqsubhss.p fr10,fr10,fr14,cc4,1 - cmqsubhss fr12,fr10,fr16,cc4,1 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_fr_limmed 0x8000,0x8000,fr16 - test_fr_limmed 0x8001,0x8001,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqsubhss fr10,fr12,fr14,cc1,0 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0x4111,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqsubhss fr10,fr12,fr14,cc1,0 - test_fr_limmed 0x4111,0xdead,fr14 - test_fr_limmed 0x0123,0x4567,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0xfffe,0xffff,fr13 - cmqsubhss fr10,fr12,fr14,cc1,0 - test_fr_limmed 0x1235,0x5679,fr14 - test_fr_limmed 0x7fff,0x7fff,fr15 - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhss fr10,fr12,fr14,cc5,0 - test_fr_limmed 0x8000,0x8000,fr14 - test_fr_limmed 0x8000,0x8000,fr15 - test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x8000,0x8000,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqsubhss.p fr10,fr10,fr14,cc5,0 - cmqsubhss fr12,fr10,fr16,cc5,0 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_fr_limmed 0x8000,0x8000,fr16 - test_fr_limmed 0x8001,0x8001,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqsubhss fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqsubhss fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0xfffe,0xffff,fr13 - cmqsubhss fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhss fr10,fr12,fr14,cc4,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x8000,0x8000,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqsubhss.p fr10,fr10,fr14,cc4,0 - cmqsubhss fr12,fr10,fr16,cc4,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqsubhss fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqsubhss fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0xfffe,0xffff,fr13 - cmqsubhss fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhss fr10,fr12,fr14,cc5,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x8000,0x8000,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqsubhss.p fr10,fr10,fr14,cc5,1 - cmqsubhss fr12,fr10,fr16,cc5,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqsubhss fr10,fr12,fr14,cc2,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqsubhss fr10,fr12,fr14,cc2,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0xfffe,0xffff,fr13 - cmqsubhss fr10,fr12,fr14,cc2,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhss fr10,fr12,fr14,cc6,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x8000,0x8000,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqsubhss.p fr10,fr10,fr14,cc6,1 - cmqsubhss fr12,fr10,fr16,cc6,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqsubhss fr10,fr12,fr14,cc3,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqsubhss fr10,fr12,fr14,cc3,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0xfffe,0xffff,fr13 - cmqsubhss fr10,fr12,fr14,cc3,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhss fr10,fr12,fr14,cc7,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x8000,0x8000,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqsubhss.p fr10,fr10,fr14,cc7,1 - cmqsubhss fr12,fr10,fr16,cc7,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - pass diff --git a/sim/testsuite/sim/frv/fr500/cmqsubhus.cgs b/sim/testsuite/sim/frv/fr500/cmqsubhus.cgs deleted file mode 100644 index f60ae981706..00000000000 --- a/sim/testsuite/sim/frv/fr500/cmqsubhus.cgs +++ /dev/null @@ -1,370 +0,0 @@ -# frv testcase for cmqsubhus $FRi,$FRj,$FRj,$CCi,$cond -# mach: frv fr500 - - .include "../testutils.inc" - - start - - .global cmqsubhus -cmqsubhus: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0xbeef,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0x0000,fr13 - cmqsubhus fr10,fr12,fr14,cc0,1 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc0,1 - test_fr_limmed 0x0123,0x4567,fr14 - test_fr_limmed 0x7ffc,0x7ffd,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc4,1 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - set_fr_iimmed 0x0000,0x0001,fr12 - set_fr_iimmed 0x0002,0x0003,fr13 - cmqsubhus.p fr10,fr10,fr14,cc4,1 - cmqsubhus fr10,fr12,fr16,cc4,1 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_fr_limmed 0x0001,0x0000,fr16 - test_fr_limmed 0x0000,0x0000,fr17 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0x1,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0xbeef,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0x0000,fr13 - cmqsubhus fr10,fr12,fr14,cc1,0 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc1,0 - test_fr_limmed 0x0123,0x4567,fr14 - test_fr_limmed 0x7ffc,0x7ffd,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc5,0 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - set_fr_iimmed 0x0000,0x0001,fr12 - set_fr_iimmed 0x0002,0x0003,fr13 - cmqsubhus.p fr10,fr10,fr14,cc5,0 - cmqsubhus fr10,fr12,fr16,cc5,0 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_fr_limmed 0x0001,0x0000,fr16 - test_fr_limmed 0x0000,0x0000,fr17 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0x1,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0xbeef,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0x0000,fr13 - cmqsubhus fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc4,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - set_fr_iimmed 0x0000,0x0001,fr12 - set_fr_iimmed 0x0002,0x0003,fr13 - cmqsubhus.p fr10,fr10,fr14,cc4,0 - cmqsubhus fr10,fr12,fr16,cc4,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_fr_limmed 0x4444,0x4444,fr17 - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0xbeef,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0x0000,fr13 - cmqsubhus fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc5,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - set_fr_iimmed 0x0000,0x0001,fr12 - set_fr_iimmed 0x0002,0x0003,fr13 - cmqsubhus.p fr10,fr10,fr14,cc5,1 - cmqsubhus fr10,fr12,fr16,cc5,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_fr_limmed 0x4444,0x4444,fr17 - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0xbeef,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0x0000,fr13 - cmqsubhus fr10,fr12,fr14,cc2,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc2,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc6,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - set_fr_iimmed 0x0000,0x0001,fr12 - set_fr_iimmed 0x0002,0x0003,fr13 - cmqsubhus.p fr10,fr10,fr14,cc6,0 - cmqsubhus fr10,fr12,fr16,cc6,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_fr_limmed 0x4444,0x4444,fr17 -; - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0xbeef,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0x0000,fr13 - cmqsubhus fr10,fr12,fr14,cc3,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc3,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc7,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - set_fr_iimmed 0x0000,0x0001,fr12 - set_fr_iimmed 0x0002,0x0003,fr13 - cmqsubhus.p fr10,fr10,fr14,cc7,0 - cmqsubhus fr10,fr12,fr16,cc7,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 2,1,0,msr1 ; msr1.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_fr_limmed 0x4444,0x4444,fr17 - - pass diff --git a/sim/testsuite/sim/frv/fr500/dcpl.cgs b/sim/testsuite/sim/frv/fr500/dcpl.cgs deleted file mode 100644 index c0c904cd820..00000000000 --- a/sim/testsuite/sim/frv/fr500/dcpl.cgs +++ /dev/null @@ -1,65 +0,0 @@ -# FRV testcase for dcpl GRi,GRj,lock -# mach: frv fr500 - - .include "../testutils.inc" - - start - - .global dcpl -dcpl: - or_spr_immed 0xc8000000,hsr0 ; caches enabled -- copy-back mode - - ; preload and lock all the lines in set 0 of the data cache - set_gr_immed 0x70000,gr10 - dcpl gr10,gr0,1 - set_mem_immed 0x11111111,gr10 - test_mem_immed 0x11111111,gr10 - - inc_gr_immed 0x1000,gr10 - set_gr_immed 1,gr11 - dcpl gr10,gr11,1 - set_mem_immed 0x22222222,gr10 - test_mem_immed 0x22222222,gr10 - - inc_gr_immed 0x1000,gr10 - set_gr_immed 63,gr11 - dcpl gr10,gr11,1 - set_mem_immed 0x33333333,gr10 - test_mem_immed 0x33333333,gr10 - - inc_gr_immed 0x1000,gr10 - set_gr_immed 64,gr11 - dcpl gr10,gr11,1 - set_mem_immed 0x44444444,gr10 - test_mem_immed 0x44444444,gr10 - - ; Now write to another address which should be in the same set - ; the write should go through to memory, since all the lines in the - ; set are locked - inc_gr_immed 0x1000,gr10 - set_mem_immed 0xdeadbeef,gr10 - test_mem_immed 0xdeadbeef,gr10 - - ; Invalidate the data cache. Only the last value stored should have made - ; it through to memory - set_gr_immed 0x70000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0,gr10 - - inc_gr_immed 0x1000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0,gr10 - - inc_gr_immed 0x1000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0,gr10 - - inc_gr_immed 0x1000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0,gr10 - - inc_gr_immed 0x1000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0xdeadbeef,gr10 - - pass diff --git a/sim/testsuite/sim/frv/fr500/dcul.cgs b/sim/testsuite/sim/frv/fr500/dcul.cgs deleted file mode 100644 index 1c5bd93c181..00000000000 --- a/sim/testsuite/sim/frv/fr500/dcul.cgs +++ /dev/null @@ -1,118 +0,0 @@ -# FRV testcase for dcul GRi -# mach: frv fr500 - - .include "../testutils.inc" - - start - - .global dcul -dcul: - or_spr_immed 0xc8000000,hsr0 ; caches enabled -- copy-back mode - - ; preload and lock all the lines in set 0 of the data cache - set_gr_immed 0x70000,gr10 - lock_data_cache gr10 - set_mem_immed 0x11111111,gr10 - test_mem_immed 0x11111111,gr10 - - inc_gr_immed 0x1000,gr10 - set_gr_immed 1,gr11 - lock_data_cache gr10 - set_mem_immed 0x22222222,gr10 - test_mem_immed 0x22222222,gr10 - - inc_gr_immed 0x1000,gr10 - set_gr_immed 63,gr11 - lock_data_cache gr10 - set_mem_immed 0x33333333,gr10 - test_mem_immed 0x33333333,gr10 - - inc_gr_immed 0x1000,gr10 - set_gr_immed 64,gr11 - lock_data_cache gr10 - set_mem_immed 0x44444444,gr10 - test_mem_immed 0x44444444,gr10 - - ; Now write to another address which should be in the same set - ; the write should go through to memory, since all the lines in the - ; set are locked - inc_gr_immed 0x1000,gr10 - set_mem_immed 0xdeadbeef,gr10 - test_mem_immed 0xdeadbeef,gr10 - - ; Invalidate the data cache. Only the last value stored should have made - ; it through to memory - set_gr_immed 0x70000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0,gr10 - - inc_gr_immed 0x1000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0,gr10 - - inc_gr_immed 0x1000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0,gr10 - - inc_gr_immed 0x1000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0,gr10 - - inc_gr_immed 0x1000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0xdeadbeef,gr10 - - ; Now preload load and lock all the lines in set 0 of the data cache - ; again - set_gr_immed 0x70000,gr10 - lock_data_cache gr10 - set_mem_immed 0x11111111,gr10 - test_mem_immed 0x11111111,gr10 - - inc_gr_immed 0x1000,gr10 - set_gr_immed 1,gr11 - lock_data_cache gr10 - set_mem_immed 0x22222222,gr10 - test_mem_immed 0x22222222,gr10 - - inc_gr_immed 0x1000,gr10 - set_gr_immed 63,gr11 - lock_data_cache gr10 - set_mem_immed 0x33333333,gr10 - test_mem_immed 0x33333333,gr10 - - inc_gr_immed 0x1000,gr10 - set_gr_immed 64,gr11 - lock_data_cache gr10 - set_mem_immed 0x44444444,gr10 - test_mem_immed 0x44444444,gr10 - - ; unlock one line - set_gr_immed 0x72000,gr10 - dcul gr10 - - ; Now write to another address which should be in the same set. - set_gr_immed 0x75000,gr10 - set_mem_immed 0xbeefdead,gr10 - - ; All of the stored values should be retrievable - - set_gr_immed 0x70000,gr10 - test_mem_immed 0x11111111,gr10 - - inc_gr_immed 0x1000,gr10 - test_mem_immed 0x22222222,gr10 - - inc_gr_immed 0x1000,gr10 - test_mem_immed 0x33333333,gr10 - - inc_gr_immed 0x1000,gr10 - test_mem_immed 0x44444444,gr10 - - inc_gr_immed 0x1000,gr10 - test_mem_immed 0xdeadbeef,gr10 - - inc_gr_immed 0x1000,gr10 - test_mem_immed 0xbeefdead,gr10 - - pass diff --git a/sim/testsuite/sim/frv/fr500/mclracc.cgs b/sim/testsuite/sim/frv/fr500/mclracc.cgs deleted file mode 100644 index 43fcf7599ca..00000000000 --- a/sim/testsuite/sim/frv/fr500/mclracc.cgs +++ /dev/null @@ -1,79 +0,0 @@ -# frv testcase for mclracc $ACC40k,$A -# mach: all - - .include "../testutils.inc" - - start - - .global mclracc -mclracc: - set_accg_immed 0xff,accg0 - set_acc_immed -1,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed -1,acc1 - set_accg_immed 0xff,accg3 - set_acc_immed -1,acc3 - set_accg_immed 0xff,accg7 - set_acc_immed -1,acc7 - - mclracc acc8,0 ; nop - test_accg_immed 0xff,accg0 - test_acc_immed -1,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -1,acc1 - test_accg_immed 0xff,accg3 - test_acc_immed -1,acc3 - test_accg_immed 0xff,accg7 - test_acc_immed -1,acc7 - - mclracc acc8,1 ; nop - test_accg_immed 0xff,accg0 - test_acc_immed -1,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -1,acc1 - test_accg_immed 0xff,accg3 - test_acc_immed -1,acc3 - test_accg_immed 0xff,accg7 - test_acc_immed -1,acc7 - - mclracc acc3,0 - test_accg_immed 0xff,accg0 - test_acc_immed -1,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -1,acc1 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - test_accg_immed 0xff,accg7 - test_acc_immed -1,acc7 - - mclracc acc7,1 - test_accg_immed 0xff,accg0 - test_acc_immed -1,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -1,acc1 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - test_accg_immed 0,accg7 - test_acc_immed 0,acc7 - - mclracc acc0,0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -1,acc1 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - test_accg_immed 0,accg7 - test_acc_immed 0,acc7 - - mclracc acc0,1 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - test_accg_immed 0,accg7 - test_acc_immed 0,acc7 - - pass diff --git a/sim/testsuite/sim/frv/fr500/mqaddhss.cgs b/sim/testsuite/sim/frv/fr500/mqaddhss.cgs deleted file mode 100644 index 7183a3f7eb6..00000000000 --- a/sim/testsuite/sim/frv/fr500/mqaddhss.cgs +++ /dev/null @@ -1,79 +0,0 @@ -# frv testcase for mqaddhss $FRi,$FRj,$FRj -# mach: frv fr500 - - .include "../testutils.inc" - - start - - .global mqaddhss -mqaddhss: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - mqaddhss fr10,fr12,fr14 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - mqaddhss fr10,fr12,fr14 - test_fr_limmed 0xbeef,0xdead,fr14 - test_fr_limmed 0x2345,0x6789,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - mqaddhss fr10,fr12,fr14 - test_fr_limmed 0x1233,0x5677,fr14 - test_fr_limmed 0x7fff,0x7fff,fr15 - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0xffff,0xfffe,fr12 - set_fr_iimmed 0xfffe,0xfffe,fr13 - mqaddhss fr10,fr12,fr14 - test_fr_limmed 0x8000,0x8000,fr14 - test_fr_limmed 0x8000,0x8000,fr15 - test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x7fff,0x0000,fr12 - set_fr_iimmed 0x0000,0x8000,fr13 - mqaddhss.p fr10,fr10,fr14 - mqaddhss fr12,fr12,fr16 - test_fr_limmed 0x0002,0x0002,fr14 - test_fr_limmed 0xfffe,0xfffe,fr15 - test_fr_limmed 0x7fff,0x0000,fr16 - test_fr_limmed 0x0000,0x8000,fr17 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0x9,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/fr500/mqaddhus.cgs b/sim/testsuite/sim/frv/fr500/mqaddhus.cgs deleted file mode 100644 index 9faa109fc2a..00000000000 --- a/sim/testsuite/sim/frv/fr500/mqaddhus.cgs +++ /dev/null @@ -1,65 +0,0 @@ -# frv testcase for mqaddhus $FRi,$FRj,$FRj -# mach: frv fr500 - - .include "../testutils.inc" - - start - - .global mqaddhus -mqaddhus: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - mqaddhus fr10,fr12,fr14 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - mqaddhus fr10,fr12,fr14 - test_fr_limmed 0xbeef,0xdead,fr14 - test_fr_limmed 0x2345,0x6789,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - set_fr_iimmed 0x0002,0x0001,fr12 - set_fr_iimmed 0x0001,0x0002,fr13 - mqaddhus fr10,fr12,fr14 - test_fr_limmed 0x8000,0x7fff,fr14 - test_fr_limmed 0xffff,0xffff,fr15 - test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0xfffe,0xfffe,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - mqaddhus.p fr10,fr10,fr14 - mqaddhus fr12,fr12,fr16 - test_fr_limmed 0x0004,0x0002,fr14 - test_fr_limmed 0x0002,0x0002,fr15 - test_fr_limmed 0xffff,0xffff,fr16 - test_fr_limmed 0xffff,0xffff,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xf,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/fr500/mqsubhss.cgs b/sim/testsuite/sim/frv/fr500/mqsubhss.cgs deleted file mode 100644 index 74d5a870e72..00000000000 --- a/sim/testsuite/sim/frv/fr500/mqsubhss.cgs +++ /dev/null @@ -1,79 +0,0 @@ -# frv testcase for mqsubhss $FRi,$FRj,$FRj -# mach: frv fr500 - - .include "../testutils.inc" - - start - - .global msubhss -msubhss: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - mqsubhss fr10,fr12,fr14 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0x4111,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - mqsubhss fr10,fr12,fr14 - test_fr_limmed 0x4111,0xdead,fr14 - test_fr_limmed 0x0123,0x4567,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0xfffe,0xffff,fr13 - mqsubhss fr10,fr12,fr14 - test_fr_limmed 0x1235,0x5679,fr14 - test_fr_limmed 0x7fff,0x7fff,fr15 - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - mqsubhss fr10,fr12,fr14 - test_fr_limmed 0x8000,0x8000,fr14 - test_fr_limmed 0x8000,0x8000,fr15 - test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x8000,0x8000,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - mqsubhss.p fr10,fr10,fr14 - mqsubhss fr12,fr10,fr16 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_fr_limmed 0x8000,0x8000,fr16 - test_fr_limmed 0x8001,0x8001,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/fr500/mqsubhus.cgs b/sim/testsuite/sim/frv/fr500/mqsubhus.cgs deleted file mode 100644 index 44aa7a94487..00000000000 --- a/sim/testsuite/sim/frv/fr500/mqsubhus.cgs +++ /dev/null @@ -1,66 +0,0 @@ -# frv testcase for msubhus $FRi,$FRj,$FRj -# mach: frv fr500 - - .include "../testutils.inc" - - start - - .global msubhus -msubhus: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0xbeef,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0x0000,fr13 - mqsubhus fr10,fr12,fr14 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - mqsubhus fr10,fr12,fr14 - test_fr_limmed 0x0123,0x4567,fr14 - test_fr_limmed 0x7ffc,0x7ffd,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - mqsubhus fr10,fr12,fr14 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - set_fr_iimmed 0x0000,0x0001,fr12 - set_fr_iimmed 0x0002,0x0003,fr13 - mqsubhus.p fr10,fr10,fr14 - mqsubhus fr10,fr12,fr16 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_fr_limmed 0x0001,0x0000,fr16 - test_fr_limmed 0x0000,0x0000,fr17 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0x1,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/fr550/allinsn.exp b/sim/testsuite/sim/frv/fr550/allinsn.exp deleted file mode 100644 index 1fe17952de1..00000000000 --- a/sim/testsuite/sim/frv/fr550/allinsn.exp +++ /dev/null @@ -1,19 +0,0 @@ -# FRV simulator testsuite. - -if [istarget frv*-*] { - # load support procs (none yet) - # load_lib cgen.exp - # all machines - set all_machs "fr550" - set cpu_option -mcpu - - # The .cgs suffix is for "cgen .s". - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/frv/fr550/cmaddhss.cgs b/sim/testsuite/sim/frv/fr550/cmaddhss.cgs deleted file mode 100644 index 174a3dcc56e..00000000000 --- a/sim/testsuite/sim/frv/fr550/cmaddhss.cgs +++ /dev/null @@ -1,547 +0,0 @@ -# frv testcase for cmaddhss $FRi,$FRj,$FRj,$CCi,$cond -# mach: all - - .include "../testutils.inc" - - start - - .global maddhss -maddhss: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmaddhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0xbeef,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x2345,0x6789,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmaddhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x1233,0x5677,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhss fr10,fr11,fr12,cc4,1 - test_fr_limmed 0x7fff,0x7fff,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc4,1 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc4,1 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmaddhss.p fr10,fr10,fr12,cc4,1 - cmaddhss fr11,fr11,fr13,cc4,1 - test_fr_limmed 0x0002,0x0002,fr12 - test_fr_limmed 0x7fff,0x7fff,fr13 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmaddhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0xbeef,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x2345,0x6789,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmaddhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x1233,0x5677,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhss fr10,fr11,fr12,cc5,0 - test_fr_limmed 0x7fff,0x7fff,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc5,0 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc5,0 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmaddhss.p fr10,fr10,fr12,cc5,0 - cmaddhss fr11,fr11,fr13,cc5,0 - test_fr_limmed 0x0002,0x0002,fr12 - test_fr_limmed 0x7fff,0x7fff,fr13 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmaddhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmaddhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhss fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmaddhss.p fr10,fr10,fr12,cc4,0 - cmaddhss fr11,fr11,fr13,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmaddhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmaddhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhss fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmaddhss.p fr10,fr10,fr12,cc5,1 - cmaddhss fr11,fr11,fr13,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmaddhss fr10,fr11,fr12,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhss fr10,fr11,fr12,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmaddhss fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhss fr10,fr11,fr12,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc6,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmaddhss.p fr10,fr10,fr12,cc6,1 - cmaddhss fr11,fr11,fr13,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set -; - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmaddhss fr10,fr11,fr12,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhss fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhss fr10,fr11,fr12,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmaddhss fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhss fr10,fr11,fr12,cc7,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc7,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhss fr10,fr11,fr12,cc7,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmaddhss.p fr10,fr10,fr12,cc7,1 - cmaddhss fr11,fr11,fr13,cc7,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - pass diff --git a/sim/testsuite/sim/frv/fr550/cmaddhus.cgs b/sim/testsuite/sim/frv/fr550/cmaddhus.cgs deleted file mode 100644 index 40e11529ce7..00000000000 --- a/sim/testsuite/sim/frv/fr550/cmaddhus.cgs +++ /dev/null @@ -1,481 +0,0 @@ -# frv testcase for cmaddhus $FRi,$FRj,$FRj,$CCi,$cond -# mach: all - - .include "../testutils.inc" - - start - - .global cmaddhus -cmaddhus: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmaddhus fr10,fr11,fr12,cc0,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc0,1 - test_fr_limmed 0xbeef,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhus fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x2345,0x6789,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhus fr10,fr11,fr12,cc4,1 - test_fr_limmed 0x8000,0x7fff,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xfffe,0xfffe,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmaddhus fr10,fr11,fr12,cc4,1 - test_fr_limmed 0xffff,0xffff,fr12 - test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhus fr10,fr11,fr12,cc4,1 - test_fr_limmed 0xffff,0xffff,fr12 - test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmaddhus.p fr10,fr10,fr12,cc4,1 - cmaddhus fr11,fr11,fr13,cc4,1 - test_fr_limmed 0x0002,0x0002,fr12 - test_fr_limmed 0xffff,0xffff,fr13 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmaddhus fr10,fr11,fr12,cc1,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc1,0 - test_fr_limmed 0xbeef,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhus fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x2345,0x6789,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhus fr10,fr11,fr12,cc5,0 - test_fr_limmed 0x8000,0x7fff,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xfffe,0xfffe,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmaddhus fr10,fr11,fr12,cc5,0 - test_fr_limmed 0xffff,0xffff,fr12 - test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhus fr10,fr11,fr12,cc5,0 - test_fr_limmed 0xffff,0xffff,fr12 - test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmaddhus.p fr10,fr10,fr12,cc5,0 - cmaddhus fr11,fr11,fr13,cc5,0 - test_fr_limmed 0x0002,0x0002,fr12 - test_fr_limmed 0xffff,0xffff,fr13 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0x0000,fr10 - set_fr_iimmed 0x0000,0xdead,fr11 - cmaddhus fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhus fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhus fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xfffe,0xfffe,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmaddhus fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhus fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmaddhus.p fr10,fr10,fr12,cc4,0 - cmaddhus fr11,fr11,fr13,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0x0000,fr10 - set_fr_iimmed 0x0000,0xdead,fr11 - cmaddhus fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhus fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhus fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xfffe,0xfffe,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmaddhus fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhus fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmaddhus.p fr10,fr10,fr12,cc5,1 - cmaddhus fr11,fr11,fr13,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0x0000,fr10 - set_fr_iimmed 0x0000,0xdead,fr11 - cmaddhus fr10,fr11,fr12,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhus fr10,fr11,fr12,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhus fr10,fr11,fr12,cc6,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xfffe,0xfffe,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmaddhus fr10,fr11,fr12,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhus fr10,fr11,fr12,cc6,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmaddhus.p fr10,fr10,fr12,cc6,0 - cmaddhus fr11,fr11,fr13,cc6,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0x0000,fr10 - set_fr_iimmed 0x0000,0xdead,fr11 - cmaddhus fr10,fr11,fr12,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmaddhus fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmaddhus fr10,fr11,fr12,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmaddhus fr10,fr11,fr12,cc7,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xfffe,0xfffe,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmaddhus fr10,fr11,fr12,cc7,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - cmaddhus fr10,fr11,fr12,cc7,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmaddhus.p fr10,fr10,fr12,cc7,0 - cmaddhus fr11,fr11,fr13,cc7,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - pass diff --git a/sim/testsuite/sim/frv/fr550/cmcpxiu.cgs b/sim/testsuite/sim/frv/fr550/cmcpxiu.cgs deleted file mode 100644 index 341949ba488..00000000000 --- a/sim/testsuite/sim/frv/fr550/cmcpxiu.cgs +++ /dev/null @@ -1,492 +0,0 @@ -# frv testcase for cmcpxiu $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "../testutils.inc" - - start - - .global cmcpxiu -cmcpxiu: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxiu fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 26,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 1,3,fr8 - cmcpxiu fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 5,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxiu fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 0x0001,2,fr8 - cmcpxiu fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x7fff,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 0x0001,2,fr8 - cmcpxiu fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8001,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 17 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 0x00010001,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x0000,0x8000,fr8 - cmcpxiu fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0000,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; almost max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,1 - test_accg_immed 1,accg0 - test_acc_immed 0xfffb0003,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,1 - test_accg_immed 1,accg0 - test_acc_immed 0xfffc0002,acc0 - - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxiu fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 26,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 1,3,fr8 - cmcpxiu fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 5,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxiu fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 0x0001,2,fr8 - cmcpxiu fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x7fff,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 0x0001,2,fr8 - cmcpxiu fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8001,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 17 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 0x00010001,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x0000,0x8000,fr8 - cmcpxiu fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0000,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; almost max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,0 - test_accg_immed 1,accg0 - test_acc_immed 0xfffb0003,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,0 - test_accg_immed 1,accg0 - test_acc_immed 0xfffc0002,acc0 - - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxiu fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 1,3,fr8 - cmcpxiu fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxiu fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 0x0001,2,fr8 - cmcpxiu fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x0000,0x8000,fr8 - cmcpxiu fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0x0001,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxiu fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 1,3,fr8 - cmcpxiu fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxiu fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 0x0001,2,fr8 - cmcpxiu fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x0000,0x8000,fr8 - cmcpxiu fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0x0001,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxiu fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 1,3,fr8 - cmcpxiu fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxiu fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 0x0001,2,fr8 - cmcpxiu fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc2,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxiu fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x0000,0x8000,fr8 - cmcpxiu fr7,fr8,acc0,cc6,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0x0001,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc6,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc6,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - cmcpxiu fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 1,3,fr8 - cmcpxiu fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - cmcpxiu fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 0x0001,2,fr8 - cmcpxiu fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 0x0001,4,fr8 - cmcpxiu fr7,fr8,acc0,cc3,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxiu fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x0000,0x8000,fr8 - cmcpxiu fr7,fr8,acc0,cc7,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0x0001,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc7,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxiu fr7,fr8,acc0,cc7,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is clear - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - pass diff --git a/sim/testsuite/sim/frv/fr550/cmcpxru.cgs b/sim/testsuite/sim/frv/fr550/cmcpxru.cgs deleted file mode 100644 index 3eeb0a041ed..00000000000 --- a/sim/testsuite/sim/frv/fr550/cmcpxru.cgs +++ /dev/null @@ -1,528 +0,0 @@ -# frv testcase for cmcpxru $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "../testutils.inc" - - start - - .global cmcpxru -cmcpxru: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxru fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 14,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 3,1,fr8 - cmcpxru fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 1,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxru fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 2,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x7ffd,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0xffff,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc0,1 - test_accg_immed 0,accg0 - test_acc_immed 0x0001ffff,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxru fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x0000,fr8 - cmcpxru fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0000,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc4,1 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0xffff,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxru fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 14,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 3,1,fr8 - cmcpxru fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 1,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxru fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 2,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x7ffd,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0xffff,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc1,0 - test_accg_immed 0,accg0 - test_acc_immed 0x0001ffff,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxru fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x0000,fr8 - cmcpxru fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0000,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc5,0 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0xffff,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_spr_immed 0,msr0 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxru fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 3,1,fr8 - cmcpxru fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxru fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 2,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc0,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxru fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x0000,fr8 - cmcpxru fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc4,0 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0xffff,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_spr_immed 0,msr0 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxru fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 3,1,fr8 - cmcpxru fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxru fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 2,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc1,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxru fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x0000,fr8 - cmcpxru fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc5,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0xffff,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_spr_immed 0,msr0 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxru fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 3,1,fr8 - cmcpxru fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxru fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 2,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc2,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxru fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x0000,fr8 - cmcpxru fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc6,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0xffff,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 -; - set_spr_immed 0,msr0 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - cmcpxru fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 3,1,fr8 - cmcpxru fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmcpxru fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 2,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 4,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc3,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmcpxru fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x0000,fr8 - cmcpxru fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc7,1 - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0xffff,0x0001,fr8 - cmcpxru fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - cmcpxru fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 1,0,0,msr0 ; msr0.aovf is clear - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - - pass diff --git a/sim/testsuite/sim/frv/fr550/cmmachs.cgs b/sim/testsuite/sim/frv/fr550/cmmachs.cgs deleted file mode 100644 index f716867d35c..00000000000 --- a/sim/testsuite/sim/frv/fr550/cmmachs.cgs +++ /dev/null @@ -1,1545 +0,0 @@ -# frv testcase for cmmachs $GRi,$GRj,$ACCk,$CCi,$cond -# mach: all - - .include "../testutils.inc" - - start - - .global cmmachs -cmmachs: - set_spr_immed 0x1b1b,cccr - - ; Positive operands - set_spr_immed 0x0,msr0 - set_accg_immed 0x0,accg0 - set_acc_immed 0x0,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x0,acc1 - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0,0x8006,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0001,0x0006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0001,0x0006,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0007,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0007,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0001,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xffff,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xffff,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xffff,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xffff,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmachs fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xbffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xbffd,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x3ffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x3ffd,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffd,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffd,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xc003,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xc003,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xc005,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xc005,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x3ffec006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3ffec006,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x7ffec006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x7ffec006,acc1 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachs fr7,fr8,acc0,cc4,1 -;;;;;;;;;;;; - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_accg_immed -128,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed -128,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr7 - set_fr_iimmed 1,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0x8000,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - ; Positive operands - set_spr_immed 0x0,msr0 - set_accg_immed 0x0,accg0 ; saturation - set_acc_immed 0x0,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x0,acc1 - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0,0x8006,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0001,0x0006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0001,0x0006,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0007,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0007,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0001,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xffff,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xffff,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xffff,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xffff,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmachs fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xbffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xbffd,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x3ffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x3ffd,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffd,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffd,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xc003,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xc003,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xc005,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xc005,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x3ffec006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3ffec006,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x7ffec006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x7ffec006,acc1 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr7 - set_fr_iimmed 1,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0x8000,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - ; Positive operands - set_spr_immed 0x0,msr0 - set_accg_immed 0x0,accg0 - set_acc_immed 0x0,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x0,acc1 - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmachs fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr7 - set_fr_iimmed 1,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0x8000,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - ; Positive operands - set_spr_immed 0x0,msr0 - set_accg_immed 0x0,accg0 - set_acc_immed 0x0,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x0,acc1 - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmachs fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr7 - set_fr_iimmed 1,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0x8000,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - ; Positive operands - set_spr_immed 0x0,msr0 - set_accg_immed 0x0,accg0 - set_acc_immed 0x0,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x0,acc1 - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmachs fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachs fr7,fr8,acc0,cc2,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmachs fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachs fr7,fr8,acc0,cc2,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc2,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmachs fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc2,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmachs fr7,fr8,acc0,cc2,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc6,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc6,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmachs fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachs fr7,fr8,acc0,cc6,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachs fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc6,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr7 - set_fr_iimmed 1,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0x8000,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc6,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 -; - ; Positive operands - set_spr_immed 0x0,msr0 - set_accg_immed 0x0,accg0 - set_acc_immed 0x0,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x0,acc1 - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - cmmachs fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachs fr7,fr8,acc0,cc3,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - cmmachs fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachs fr7,fr8,acc0,cc3,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc3,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - cmmachs fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc3,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - cmmachs fr7,fr8,acc0,cc3,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - cmmachs fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc7,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - cmmachs fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc7,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - cmmachs fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachs fr7,fr8,acc0,cc7,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachs fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc7,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr7 - set_fr_iimmed 1,0xffff,fr8 - cmmachs fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0x8000,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachs fr7,fr8,acc0,cc7,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - pass diff --git a/sim/testsuite/sim/frv/fr550/cmmachu.cgs b/sim/testsuite/sim/frv/fr550/cmmachu.cgs deleted file mode 100644 index 176d1b1aca6..00000000000 --- a/sim/testsuite/sim/frv/fr550/cmmachu.cgs +++ /dev/null @@ -1,858 +0,0 @@ -# frv testcase for cmmachu $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "../testutils.inc" - - start - - .global cmmachu -cmmachu: - set_spr_immed 0x1b1b,cccr - - set_spr_immed 0,msr0 - set_accg_immed 0,accg0 - set_acc_immed 0,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmachu fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmachu fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachu fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachu fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8006,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachu fr7,fr8,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0001,0x0006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0001,0x0006,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x00020006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x00020006,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachu fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x40010007,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x40010007,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x8001,0x0007,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x8001,0x0007,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 1,accg0 - test_acc_limmed 0x7fff,0x0008,acc0 - test_accg_immed 1,accg1 - test_acc_limmed 0x7fff,0x0008,acc1 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachu fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_fr_iimmed 0xffff,0x0000,fr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc4,1 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_spr_immed 0,msr0 - set_accg_immed 0,accg0 - set_acc_immed 0,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmachu fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmachu fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachu fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachu fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8006,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachu fr7,fr8,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0001,0x0006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0001,0x0006,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x00020006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x00020006,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachu fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x40010007,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x40010007,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x8001,0x0007,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x8001,0x0007,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 1,accg0 - test_acc_limmed 0x7fff,0x0008,acc0 - test_accg_immed 1,accg1 - test_acc_limmed 0x7fff,0x0008,acc1 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachu fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_fr_iimmed 0xffff,0x0000,fr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc5,0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_spr_immed 0,msr0 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmachu fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmachu fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachu fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachu fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachu fr7,fr8,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - - set_fr_iimmed 0xffff,0x0000,fr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - - set_spr_immed 0,msr0 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmachu fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmachu fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachu fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachu fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachu fr7,fr8,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - - set_fr_iimmed 0xffff,0x0000,fr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - - set_spr_immed 0,msr0 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmachu fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmachu fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachu fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachu fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachu fr7,fr8,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachu fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachu fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - - set_fr_iimmed 0xffff,0x0000,fr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 -; - set_spr_immed 0,msr0 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - cmmachu fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - cmmachu fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - cmmachu fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - cmmachu fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - cmmachu fr7,fr8,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - cmmachu fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - cmmachu fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - cmmachu fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - - set_fr_iimmed 0xffff,0x0000,fr7 - set_fr_iimmed 0xffff,0xffff,fr8 - cmmachu fr7,fr8,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - - pass diff --git a/sim/testsuite/sim/frv/fr550/cmqaddhss.cgs b/sim/testsuite/sim/frv/fr550/cmqaddhss.cgs deleted file mode 100644 index 3d32bec08e4..00000000000 --- a/sim/testsuite/sim/frv/fr550/cmqaddhss.cgs +++ /dev/null @@ -1,429 +0,0 @@ -# frv testcase for cmqaddhss $FRi,$FRj,$FRj,$CCi,$cond -# mach: all - - .include "../testutils.inc" - - start - - .global cmqaddhss -cmqaddhss: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhss fr10,fr12,fr14,cc0,1 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhss fr10,fr12,fr14,cc0,1 - test_fr_limmed 0xbeef,0xdead,fr14 - test_fr_limmed 0x2345,0x6789,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqaddhss fr10,fr12,fr14,cc0,1 - test_fr_limmed 0x1233,0x5677,fr14 - test_fr_limmed 0x7fff,0x7fff,fr15 - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0xffff,0xfffe,fr12 - set_fr_iimmed 0xfffe,0xfffe,fr13 - cmqaddhss fr10,fr12,fr14,cc4,1 - test_fr_limmed 0x8000,0x8000,fr14 - test_fr_limmed 0x8000,0x8000,fr15 - test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x7fff,0x0000,fr12 - set_fr_iimmed 0x0000,0x8000,fr13 - cmqaddhss.p fr10,fr10,fr14,cc4,1 - cmqaddhss fr12,fr12,fr16,cc4,1 - test_fr_limmed 0x0002,0x0002,fr14 - test_fr_limmed 0xfffe,0xfffe,fr15 - test_fr_limmed 0x7fff,0x0000,fr16 - test_fr_limmed 0x0000,0x8000,fr17 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhss fr10,fr12,fr14,cc1,0 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhss fr10,fr12,fr14,cc1,0 - test_fr_limmed 0xbeef,0xdead,fr14 - test_fr_limmed 0x2345,0x6789,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqaddhss fr10,fr12,fr14,cc1,0 - test_fr_limmed 0x1233,0x5677,fr14 - test_fr_limmed 0x7fff,0x7fff,fr15 - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0xffff,0xfffe,fr12 - set_fr_iimmed 0xfffe,0xfffe,fr13 - cmqaddhss fr10,fr12,fr14,cc5,0 - test_fr_limmed 0x8000,0x8000,fr14 - test_fr_limmed 0x8000,0x8000,fr15 - test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x7fff,0x0000,fr12 - set_fr_iimmed 0x0000,0x8000,fr13 - cmqaddhss.p fr10,fr10,fr14,cc5,0 - cmqaddhss fr12,fr12,fr16,cc5,0 - test_fr_limmed 0x0002,0x0002,fr14 - test_fr_limmed 0xfffe,0xfffe,fr15 - test_fr_limmed 0x7fff,0x0000,fr16 - test_fr_limmed 0x0000,0x8000,fr17 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhss fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhss fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqaddhss fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0xffff,0xfffe,fr12 - set_fr_iimmed 0xfffe,0xfffe,fr13 - cmqaddhss fr10,fr12,fr14,cc4,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x7fff,0x0000,fr12 - set_fr_iimmed 0x0000,0x8000,fr13 - cmqaddhss.p fr10,fr10,fr14,cc4,0 - cmqaddhss fr12,fr12,fr16,cc4,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhss fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhss fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqaddhss fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0xffff,0xfffe,fr12 - set_fr_iimmed 0xfffe,0xfffe,fr13 - cmqaddhss fr10,fr12,fr14,cc5,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x7fff,0x0000,fr12 - set_fr_iimmed 0x0000,0x8000,fr13 - cmqaddhss.p fr10,fr10,fr14,cc5,1 - cmqaddhss fr12,fr12,fr16,cc5,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhss fr10,fr12,fr14,cc2,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhss fr10,fr12,fr14,cc2,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqaddhss fr10,fr12,fr14,cc2,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0xffff,0xfffe,fr12 - set_fr_iimmed 0xfffe,0xfffe,fr13 - cmqaddhss fr10,fr12,fr14,cc6,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x7fff,0x0000,fr12 - set_fr_iimmed 0x0000,0x8000,fr13 - cmqaddhss.p fr10,fr10,fr14,cc6,1 - cmqaddhss fr12,fr12,fr16,cc6,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set -; - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhss fr10,fr12,fr14,cc3,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhss fr10,fr12,fr14,cc3,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqaddhss fr10,fr12,fr14,cc3,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0xffff,0xfffe,fr12 - set_fr_iimmed 0xfffe,0xfffe,fr13 - cmqaddhss fr10,fr12,fr14,cc7,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x7fff,0x0000,fr12 - set_fr_iimmed 0x0000,0x8000,fr13 - cmqaddhss.p fr10,fr10,fr14,cc7,1 - cmqaddhss fr12,fr12,fr16,cc7,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - pass diff --git a/sim/testsuite/sim/frv/fr550/cmqaddhus.cgs b/sim/testsuite/sim/frv/fr550/cmqaddhus.cgs deleted file mode 100644 index 4e25ba43ca2..00000000000 --- a/sim/testsuite/sim/frv/fr550/cmqaddhus.cgs +++ /dev/null @@ -1,345 +0,0 @@ -# frv testcase for cmqaddhus $FRi,$FRj,$FRj,$CCi,$cond -# mach: all - - .include "../testutils.inc" - - start - - .global cmqaddhus -cmqaddhus: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhus fr10,fr12,fr14,cc0,1 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhus fr10,fr12,fr14,cc0,1 - test_fr_limmed 0xbeef,0xdead,fr14 - test_fr_limmed 0x2345,0x6789,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - set_fr_iimmed 0x0002,0x0001,fr12 - set_fr_iimmed 0x0001,0x0002,fr13 - cmqaddhus fr10,fr12,fr14,cc4,1 - test_fr_limmed 0x8000,0x7fff,fr14 - test_fr_limmed 0xffff,0xffff,fr15 - test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0xfffe,0xfffe,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqaddhus.p fr10,fr10,fr14,cc4,1 - cmqaddhus fr12,fr12,fr16,cc4,1 - test_fr_limmed 0x0004,0x0002,fr14 - test_fr_limmed 0x0002,0x0002,fr15 - test_fr_limmed 0xffff,0xffff,fr16 - test_fr_limmed 0xffff,0xffff,fr17 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhus fr10,fr12,fr14,cc1,0 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhus fr10,fr12,fr14,cc1,0 - test_fr_limmed 0xbeef,0xdead,fr14 - test_fr_limmed 0x2345,0x6789,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - set_fr_iimmed 0x0002,0x0001,fr12 - set_fr_iimmed 0x0001,0x0002,fr13 - cmqaddhus fr10,fr12,fr14,cc5,0 - test_fr_limmed 0x8000,0x7fff,fr14 - test_fr_limmed 0xffff,0xffff,fr15 - test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0xfffe,0xfffe,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqaddhus.p fr10,fr10,fr14,cc5,0 - cmqaddhus fr12,fr12,fr16,cc5,0 - test_fr_limmed 0x0004,0x0002,fr14 - test_fr_limmed 0x0002,0x0002,fr15 - test_fr_limmed 0xffff,0xffff,fr16 - test_fr_limmed 0xffff,0xffff,fr17 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhus fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhus fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - set_fr_iimmed 0x0002,0x0001,fr12 - set_fr_iimmed 0x0001,0x0002,fr13 - cmqaddhus fr10,fr12,fr14,cc4,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0xfffe,0xfffe,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqaddhus.p fr10,fr10,fr14,cc4,0 - cmqaddhus fr12,fr12,fr16,cc4,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhus fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhus fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - set_fr_iimmed 0x0002,0x0001,fr12 - set_fr_iimmed 0x0001,0x0002,fr13 - cmqaddhus fr10,fr12,fr14,cc5,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0xfffe,0xfffe,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqaddhus.p fr10,fr10,fr14,cc5,1 - cmqaddhus fr12,fr12,fr16,cc5,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhus fr10,fr12,fr14,cc2,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhus fr10,fr12,fr14,cc2,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - set_fr_iimmed 0x0002,0x0001,fr12 - set_fr_iimmed 0x0001,0x0002,fr13 - cmqaddhus fr10,fr12,fr14,cc6,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0xfffe,0xfffe,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqaddhus.p fr10,fr10,fr14,cc6,0 - cmqaddhus fr12,fr12,fr16,cc6,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqaddhus fr10,fr12,fr14,cc3,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqaddhus fr10,fr12,fr14,cc3,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - set_fr_iimmed 0x0002,0x0001,fr12 - set_fr_iimmed 0x0001,0x0002,fr13 - cmqaddhus fr10,fr12,fr14,cc7,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0xfffe,0xfffe,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqaddhus.p fr10,fr10,fr14,cc7,0 - cmqaddhus fr12,fr12,fr16,cc7,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - pass diff --git a/sim/testsuite/sim/frv/fr550/cmqmachs.cgs b/sim/testsuite/sim/frv/fr550/cmqmachs.cgs deleted file mode 100644 index 0aee4f0ab77..00000000000 --- a/sim/testsuite/sim/frv/fr550/cmqmachs.cgs +++ /dev/null @@ -1,1262 +0,0 @@ -# frv testcase for cmqmachs $GRi,$GRj,$ACCk,$CCi,$cond -# mach: all - - .include "../testutils.inc" - - start - - .global cmqmachs -cmqmachs: - set_spr_immed 0x1b1b,cccr - - ; Positive operands - set_spr_immed 0,msr0 - set_accg_immed 0,accg0 - set_acc_immed 0,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmachs fr8,fr10,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachs fr8,fr10,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0,0x7ffe,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0,0x7ffe,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8008,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8008,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x7fff,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x7fff,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmachs fr8,fr10,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8002,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x7ffd,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x7ffd,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmachs fr8,fr10,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8002,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x3ffb,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x3ffb,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0002,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffb,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffb,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmachs fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0008,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0008,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffd,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffd,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachs fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0009,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0009,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x3fffbffd,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x3fffbffd,acc3 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 1,0xffff,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0x80,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - - ; Positive operands - set_spr_immed 0,msr0 - set_accg_immed 0,accg0 - set_acc_immed 0,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmachs fr8,fr10,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachs fr8,fr10,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0,0x7ffe,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0,0x7ffe,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8008,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8008,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x7fff,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x7fff,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmachs fr8,fr10,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8002,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x7ffd,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x7ffd,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmachs fr8,fr10,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8002,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x3ffb,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x3ffb,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0002,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffb,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffb,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmachs fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0008,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0008,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffd,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffd,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachs fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0009,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0009,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x3fffbffd,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x3fffbffd,acc3 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 1,0xffff,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0x80,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - - ; Positive operands - set_spr_immed 0,msr0 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmachs fr8,fr10,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachs fr8,fr10,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmachs fr8,fr10,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmachs fr8,fr10,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmachs fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachs fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0x7f,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_immed 0xffffffff,acc3 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 1,0xffff,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0x80,accg2 ; saturation - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - - ; Positive operands - set_spr_immed 0,msr0 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmachs fr8,fr10,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachs fr8,fr10,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmachs fr8,fr10,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmachs fr8,fr10,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmachs fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachs fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0x7f,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_immed 0xffffffff,acc3 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 1,0xffff,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0x80,accg2 ; saturation - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - - ; Positive operands - set_spr_immed 0,msr0 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmachs fr8,fr10,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachs fr8,fr10,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmachs fr8,fr10,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmachs fr8,fr10,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmachs fr8,fr10,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachs fr8,fr10,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0x7f,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_immed 0xffffffff,acc3 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 1,0xffff,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0x80,accg2 ; saturation - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 -; - ; Positive operands - set_spr_immed 0,msr0 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - cmqmachs fr8,fr10,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachs fr8,fr10,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - cmqmachs fr8,fr10,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - cmqmachs fr8,fr10,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmqmachs fr8,fr10,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachs fr8,fr10,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0x7f,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_immed 0xffffffff,acc3 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 1,0xffff,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - cmqmachs fr8,fr10,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x80,accg0 ; saturation - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0x80,accg2 ; saturation - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - - pass - - diff --git a/sim/testsuite/sim/frv/fr550/cmqmachu.cgs b/sim/testsuite/sim/frv/fr550/cmqmachu.cgs deleted file mode 100644 index 8b880f82436..00000000000 --- a/sim/testsuite/sim/frv/fr550/cmqmachu.cgs +++ /dev/null @@ -1,870 +0,0 @@ -# frv testcase for cmqmachu $GRi,$GRj,$GRk,$CCi,$cond -# mach: all - - .include "../testutils.inc" - - start - - .global cmqmachu -cmqmachu: - set_spr_immed 0x1b1b,cccr - - set_spr_immed 0,msr0 - set_accg_immed 0,accg0 - set_acc_immed 0,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmachu fr8,fr10,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 2,acc2 - test_accg_immed 0,accg3 - test_acc_immed 2,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachu fr8,fr10,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8000,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc0,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8006,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x00018000,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x00018000,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x3fff8007,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff8007,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x4001,0x8000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x4001,0x8000,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 1,accg0 - test_acc_limmed 0x3ffd,0x8008,acc0 - test_accg_immed 1,accg1 - test_acc_limmed 0x3ffd,0x8008,acc1 - test_accg_immed 1,accg2 - test_acc_limmed 0x3fff,0x8001,acc2 - test_accg_immed 1,accg3 - test_acc_limmed 0x3fff,0x8001,acc3 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0xff,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 1,1,fr9 - set_fr_iimmed 1,1,fr11 - cmqmachu fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_fr_iimmed 0xffff,0x0000,fr8 - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0x0000,0xffff,fr9 - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc4,1 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0,accg0 - set_acc_immed 0,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmachu fr8,fr10,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 2,acc2 - test_accg_immed 0,accg3 - test_acc_immed 2,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachu fr8,fr10,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8000,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc1,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8006,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x00018000,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x00018000,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x3fff8007,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff8007,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x4001,0x8000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x4001,0x8000,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 1,accg0 - test_acc_limmed 0x3ffd,0x8008,acc0 - test_accg_immed 1,accg1 - test_acc_limmed 0x3ffd,0x8008,acc1 - test_accg_immed 1,accg2 - test_acc_limmed 0x3fff,0x8001,acc2 - test_accg_immed 1,accg3 - test_acc_limmed 0x3fff,0x8001,acc3 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0xff,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 1,1,fr9 - set_fr_iimmed 1,1,fr11 - cmqmachu fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_fr_iimmed 0xffff,0x0000,fr8 - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0x0000,0xffff,fr9 - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc5,0 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmachu fr8,fr10,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachu fr8,fr10,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc0,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0xff,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 1,1,fr9 - set_fr_iimmed 1,1,fr11 - cmqmachu fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0xff,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed 0xffffffff,acc3 - - set_fr_iimmed 0xffff,0x0000,fr8 - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0x0000,0xffff,fr9 - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc4,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0xff,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed 0xffffffff,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmachu fr8,fr10,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachu fr8,fr10,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc1,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0xff,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 1,1,fr9 - set_fr_iimmed 1,1,fr11 - cmqmachu fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0xff,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed 0xffffffff,acc3 - - set_fr_iimmed 0xffff,0x0000,fr8 - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0x0000,0xffff,fr9 - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc5,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0xff,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed 0xffffffff,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmachu fr8,fr10,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachu fr8,fr10,acc0,cc2,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc2,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc6,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0xff,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 1,1,fr9 - set_fr_iimmed 1,1,fr11 - cmqmachu fr8,fr10,acc0,cc6,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0xff,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed 0xffffffff,acc3 - - set_fr_iimmed 0xffff,0x0000,fr8 - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0x0000,0xffff,fr9 - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc6,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0xff,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed 0xffffffff,acc3 -; - set_spr_immed 0,msr0 - set_accg_immed 0x00000011,accg0 - set_acc_immed 0x11111111,acc0 - set_accg_immed 0x00000022,accg1 - set_acc_immed 0x22222222,acc1 - set_accg_immed 0x00000033,accg2 - set_acc_immed 0x33333333,acc2 - set_accg_immed 0x00000044,accg3 - set_acc_immed 0x44444444,acc3 - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - cmqmachu fr8,fr10,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - cmqmachu fr8,fr10,acc0,cc3,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc3,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - cmqmachu fr8,fr10,acc0,cc7,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x00000011,accg0 - test_acc_immed 0x11111111,acc0 - test_accg_immed 0x00000022,accg1 - test_acc_immed 0x22222222,acc1 - test_accg_immed 0x00000033,accg2 - test_acc_immed 0x33333333,acc2 - test_accg_immed 0x00000044,accg3 - test_acc_immed 0x44444444,acc3 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0xff,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 1,1,fr9 - set_fr_iimmed 1,1,fr11 - cmqmachu fr8,fr10,acc0,cc7,0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0xff,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed 0xffffffff,acc3 - - set_fr_iimmed 0xffff,0x0000,fr8 - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0x0000,0xffff,fr9 - set_fr_iimmed 0xffff,0xffff,fr11 - cmqmachu fr8,fr10,acc0,cc7,1 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 ; saturation - test_acc_immed 0xffffffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xffffffff,acc1 - test_accg_immed 0xff,accg2 ; saturation - test_acc_immed 0xffffffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed 0xffffffff,acc3 - - pass diff --git a/sim/testsuite/sim/frv/fr550/cmqsubhss.cgs b/sim/testsuite/sim/frv/fr550/cmqsubhss.cgs deleted file mode 100644 index 490b449ec83..00000000000 --- a/sim/testsuite/sim/frv/fr550/cmqsubhss.cgs +++ /dev/null @@ -1,429 +0,0 @@ -# frv testcase for cmqsubhss $FRi,$FRj,$FRj,$CCi,$cond -# mach: all - - .include "../testutils.inc" - - start - - .global msubhss -msubhss: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqsubhss fr10,fr12,fr14,cc0,1 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0x4111,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqsubhss fr10,fr12,fr14,cc0,1 - test_fr_limmed 0x4111,0xdead,fr14 - test_fr_limmed 0x0123,0x4567,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0xfffe,0xffff,fr13 - cmqsubhss fr10,fr12,fr14,cc0,1 - test_fr_limmed 0x1235,0x5679,fr14 - test_fr_limmed 0x7fff,0x7fff,fr15 - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhss fr10,fr12,fr14,cc4,1 - test_fr_limmed 0x8000,0x8000,fr14 - test_fr_limmed 0x8000,0x8000,fr15 - test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x8000,0x8000,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqsubhss.p fr10,fr10,fr14,cc4,1 - cmqsubhss fr12,fr10,fr16,cc4,1 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_fr_limmed 0x8000,0x8000,fr16 - test_fr_limmed 0x8001,0x8001,fr17 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqsubhss fr10,fr12,fr14,cc1,0 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0x4111,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqsubhss fr10,fr12,fr14,cc1,0 - test_fr_limmed 0x4111,0xdead,fr14 - test_fr_limmed 0x0123,0x4567,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0xfffe,0xffff,fr13 - cmqsubhss fr10,fr12,fr14,cc1,0 - test_fr_limmed 0x1235,0x5679,fr14 - test_fr_limmed 0x7fff,0x7fff,fr15 - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhss fr10,fr12,fr14,cc5,0 - test_fr_limmed 0x8000,0x8000,fr14 - test_fr_limmed 0x8000,0x8000,fr15 - test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x8000,0x8000,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqsubhss.p fr10,fr10,fr14,cc5,0 - cmqsubhss fr12,fr10,fr16,cc5,0 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_fr_limmed 0x8000,0x8000,fr16 - test_fr_limmed 0x8001,0x8001,fr17 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf not set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqsubhss fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqsubhss fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0xfffe,0xffff,fr13 - cmqsubhss fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhss fr10,fr12,fr14,cc4,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x8000,0x8000,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqsubhss.p fr10,fr10,fr14,cc4,0 - cmqsubhss fr12,fr10,fr16,cc4,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqsubhss fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqsubhss fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0xfffe,0xffff,fr13 - cmqsubhss fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhss fr10,fr12,fr14,cc5,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x8000,0x8000,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqsubhss.p fr10,fr10,fr14,cc5,1 - cmqsubhss fr12,fr10,fr16,cc5,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqsubhss fr10,fr12,fr14,cc2,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqsubhss fr10,fr12,fr14,cc2,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0xfffe,0xffff,fr13 - cmqsubhss fr10,fr12,fr14,cc2,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhss fr10,fr12,fr14,cc6,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x8000,0x8000,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqsubhss.p fr10,fr10,fr14,cc6,1 - cmqsubhss fr12,fr10,fr16,cc6,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is set - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - cmqsubhss fr10,fr12,fr14,cc3,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - cmqsubhss fr10,fr12,fr14,cc3,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0xfffe,0xffff,fr13 - cmqsubhss fr10,fr12,fr14,cc3,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhss fr10,fr12,fr14,cc7,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x8000,0x8000,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - cmqsubhss.p fr10,fr10,fr14,cc7,1 - cmqsubhss fr12,fr10,fr16,cc7,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_fr_limmed 0x4444,0x4444,fr17 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is set - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - pass diff --git a/sim/testsuite/sim/frv/fr550/cmqsubhus.cgs b/sim/testsuite/sim/frv/fr550/cmqsubhus.cgs deleted file mode 100644 index 90bd89ae63f..00000000000 --- a/sim/testsuite/sim/frv/fr550/cmqsubhus.cgs +++ /dev/null @@ -1,351 +0,0 @@ -# frv testcase for cmqsubhus $FRi,$FRj,$FRj,$CCi,$cond -# mach: all - - .include "../testutils.inc" - - start - - .global cmqsubhus -cmqsubhus: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0xbeef,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0x0000,fr13 - cmqsubhus fr10,fr12,fr14,cc0,1 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc0,1 - test_fr_limmed 0x0123,0x4567,fr14 - test_fr_limmed 0x7ffc,0x7ffd,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc4,1 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - set_fr_iimmed 0x0000,0x0001,fr12 - set_fr_iimmed 0x0002,0x0003,fr13 - cmqsubhus.p fr10,fr10,fr14,cc4,1 - cmqsubhus fr10,fr12,fr16,cc4,1 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_fr_limmed 0x0001,0x0000,fr16 - test_fr_limmed 0x0000,0x0000,fr17 - test_spr_bits 0x3c,2,0x1,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0xbeef,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0x0000,fr13 - cmqsubhus fr10,fr12,fr14,cc1,0 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc1,0 - test_fr_limmed 0x0123,0x4567,fr14 - test_fr_limmed 0x7ffc,0x7ffd,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc5,0 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - set_fr_iimmed 0x0000,0x0001,fr12 - set_fr_iimmed 0x0002,0x0003,fr13 - cmqsubhus.p fr10,fr10,fr14,cc5,0 - cmqsubhus fr10,fr12,fr16,cc5,0 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_fr_limmed 0x0001,0x0000,fr16 - test_fr_limmed 0x0000,0x0000,fr17 - test_spr_bits 0x3c,2,0x1,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0xbeef,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0x0000,fr13 - cmqsubhus fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc0,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc4,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - set_fr_iimmed 0x0000,0x0001,fr12 - set_fr_iimmed 0x0002,0x0003,fr13 - cmqsubhus.p fr10,fr10,fr14,cc4,0 - cmqsubhus fr10,fr12,fr16,cc4,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_fr_limmed 0x4444,0x4444,fr17 - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0xbeef,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0x0000,fr13 - cmqsubhus fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc1,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc5,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - set_fr_iimmed 0x0000,0x0001,fr12 - set_fr_iimmed 0x0002,0x0003,fr13 - cmqsubhus.p fr10,fr10,fr14,cc5,1 - cmqsubhus fr10,fr12,fr16,cc5,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_fr_limmed 0x4444,0x4444,fr17 - - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0xbeef,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0x0000,fr13 - cmqsubhus fr10,fr12,fr14,cc2,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc2,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc6,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - set_fr_iimmed 0x0000,0x0001,fr12 - set_fr_iimmed 0x0002,0x0003,fr13 - cmqsubhus.p fr10,fr10,fr14,cc6,0 - cmqsubhus fr10,fr12,fr16,cc6,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_fr_limmed 0x4444,0x4444,fr17 -; - set_fr_iimmed 0x1111,0x1111,fr14 - set_fr_iimmed 0x2222,0x2222,fr15 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0xbeef,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0x0000,fr13 - cmqsubhus fr10,fr12,fr14,cc3,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc3,0 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - cmqsubhus fr10,fr12,fr14,cc7,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x3333,0x3333,fr16 - set_fr_iimmed 0x4444,0x4444,fr17 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - set_fr_iimmed 0x0000,0x0001,fr12 - set_fr_iimmed 0x0002,0x0003,fr13 - cmqsubhus.p fr10,fr10,fr14,cc7,0 - cmqsubhus fr10,fr12,fr16,cc7,1 - test_fr_limmed 0x1111,0x1111,fr14 - test_fr_limmed 0x2222,0x2222,fr15 - test_fr_limmed 0x3333,0x3333,fr16 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_fr_limmed 0x4444,0x4444,fr17 - - pass diff --git a/sim/testsuite/sim/frv/fr550/cmsubhss.cgs b/sim/testsuite/sim/frv/fr550/cmsubhss.cgs deleted file mode 100644 index 9370d54c9cf..00000000000 --- a/sim/testsuite/sim/frv/fr550/cmsubhss.cgs +++ /dev/null @@ -1,547 +0,0 @@ -# frv testcase for cmsubhss $FRi,$FRj,$FRj,$CCi,$cond -# mach: all - - .include "../testutils.inc" - - start - - .global cmsubhss -cmsubhss: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmsubhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0xdead,0x4111,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x4111,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x0123,0x4567,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x1235,0x5679,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc4,1 - test_fr_limmed 0x7fff,0x7fff,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhss fr10,fr11,fr12,cc4,1 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhss fr10,fr11,fr12,cc4,1 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmsubhss.p fr10,fr10,fr12,cc4,1 - cmsubhss fr11,fr10,fr13,cc4,1 - test_fr_limmed 0x0000,0x0000,fr12 - test_fr_limmed 0x8000,0x8000,fr13 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmsubhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0xdead,0x4111,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x4111,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x0123,0x4567,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x1235,0x5679,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc5,0 - test_fr_limmed 0x7fff,0x7fff,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhss fr10,fr11,fr12,cc5,0 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhss fr10,fr11,fr12,cc5,0 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmsubhss.p fr10,fr10,fr12,cc5,0 - cmsubhss fr11,fr10,fr13,cc5,0 - test_fr_limmed 0x0000,0x0000,fr12 - test_fr_limmed 0x8000,0x8000,fr13 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmsubhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhss fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhss fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmsubhss.p fr10,fr10,fr12,cc4,0 - cmsubhss fr11,fr10,fr13,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmsubhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhss fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhss fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmsubhss.p fr10,fr10,fr12,cc5,1 - cmsubhss fr11,fr10,fr13,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmsubhss fr10,fr11,fr12,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhss fr10,fr11,fr12,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhss fr10,fr11,fr12,cc6,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhss fr10,fr11,fr12,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmsubhss.p fr10,fr10,fr12,cc6,1 - cmsubhss fr11,fr10,fr13,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set -; - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - cmsubhss fr10,fr11,fr12,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - cmsubhss fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhss fr10,fr11,fr12,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xffff,fr11 - cmsubhss fr10,fr11,fr12,cc7,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhss fr10,fr11,fr12,cc7,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhss fr10,fr11,fr12,cc7,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - cmsubhss.p fr10,fr10,fr12,cc7,1 - cmsubhss fr11,fr10,fr13,cc7,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - pass diff --git a/sim/testsuite/sim/frv/fr550/cmsubhus.cgs b/sim/testsuite/sim/frv/fr550/cmsubhus.cgs deleted file mode 100644 index 5cf676b7967..00000000000 --- a/sim/testsuite/sim/frv/fr550/cmsubhus.cgs +++ /dev/null @@ -1,427 +0,0 @@ -# frv testcase for cmsubhus $FRi,$FRj,$FRj,$CCi,$cond -# mach: all - - .include "../testutils.inc" - - start - - .global cmsubhus -cmsubhus: - set_spr_immed 0x1b1b,cccr - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0xbeef,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc0,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhus fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x0123,0x4567,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc0,1 - test_fr_limmed 0x7ffc,0x7ffd,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhus fr10,fr11,fr12,cc4,1 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc4,1 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - cmsubhus.p fr10,fr10,fr12,cc4,1 - cmsubhus fr10,fr11,fr13,cc4,1 - test_fr_limmed 0x0000,0x0000,fr12 - test_fr_limmed 0x0000,0x0000,fr13 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0xbeef,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc1,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhus fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x0123,0x4567,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc1,0 - test_fr_limmed 0x7ffc,0x7ffd,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhus fr10,fr11,fr12,cc5,0 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc5,0 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - cmsubhus.p fr10,fr10,fr12,cc5,0 - cmsubhus fr10,fr11,fr13,cc5,0 - test_fr_limmed 0x0000,0x0000,fr12 - test_fr_limmed 0x0000,0x0000,fr13 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhus fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc0,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhus fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - cmsubhus.p fr10,fr10,fr12,cc4,0 - cmsubhus fr10,fr11,fr13,cc4,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhus fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc1,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhus fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - cmsubhus.p fr10,fr10,fr12,cc5,1 - cmsubhus fr10,fr11,fr13,cc5,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhus fr10,fr11,fr12,cc2,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc2,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhus fr10,fr11,fr12,cc6,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc6,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - cmsubhus.p fr10,fr10,fr12,cc6,0 - cmsubhus fr10,fr11,fr13,cc6,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set -; - set_fr_iimmed 0xdead,0xbeef,fr12 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - cmsubhus fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - cmsubhus fr10,fr11,fr12,cc3,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc3,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - cmsubhus fr10,fr11,fr12,cc7,0 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - cmsubhus fr10,fr11,fr12,cc7,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xbeef,0xdead,fr13 - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - cmsubhus.p fr10,fr10,fr12,cc7,0 - cmsubhus fr10,fr11,fr13,cc7,1 - test_fr_limmed 0xdead,0xbeef,fr12 - test_fr_limmed 0xbeef,0xdead,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - pass diff --git a/sim/testsuite/sim/frv/fr550/dcpl.cgs b/sim/testsuite/sim/frv/fr550/dcpl.cgs deleted file mode 100644 index 93c659a5917..00000000000 --- a/sim/testsuite/sim/frv/fr550/dcpl.cgs +++ /dev/null @@ -1,65 +0,0 @@ -# FRV testcase for dcpl GRi,GRj,lock -# mach: all - - .include "../testutils.inc" - - start - - .global dcpl -dcpl: - or_spr_immed 0xc8000000,hsr0 ; caches enabled -- copy-back mode - - ; preload and lock all the lines in set 0 of the data cache - set_gr_immed 0x70000,gr10 - dcpl gr10,gr0,1 - set_mem_immed 0x11111111,gr10 - test_mem_immed 0x11111111,gr10 - - inc_gr_immed 0x2000,gr10 - set_gr_immed 1,gr11 - dcpl gr10,gr11,1 - set_mem_immed 0x22222222,gr10 - test_mem_immed 0x22222222,gr10 - - inc_gr_immed 0x2000,gr10 - set_gr_immed 63,gr11 - dcpl gr10,gr11,1 - set_mem_immed 0x33333333,gr10 - test_mem_immed 0x33333333,gr10 - - inc_gr_immed 0x2000,gr10 - set_gr_immed 64,gr11 - dcpl gr10,gr11,1 - set_mem_immed 0x44444444,gr10 - test_mem_immed 0x44444444,gr10 - - ; Now write to another address which should be in the same set - ; the write should go through to memory, since all the lines in the - ; set are locked - inc_gr_immed 0x2000,gr10 - set_mem_immed 0xdeadbeef,gr10 - test_mem_immed 0xdeadbeef,gr10 - - ; Invalidate the data cache. Only the last value stored should have made - ; it through to memory - set_gr_immed 0x70000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0,gr10 - - inc_gr_immed 0x2000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0,gr10 - - inc_gr_immed 0x2000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0,gr10 - - inc_gr_immed 0x2000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0,gr10 - - inc_gr_immed 0x2000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0xdeadbeef,gr10 - - pass diff --git a/sim/testsuite/sim/frv/fr550/dcul.cgs b/sim/testsuite/sim/frv/fr550/dcul.cgs deleted file mode 100644 index a3bd4be8cd5..00000000000 --- a/sim/testsuite/sim/frv/fr550/dcul.cgs +++ /dev/null @@ -1,118 +0,0 @@ -# FRV testcase for dcul GRi -# mach: all - - .include "../testutils.inc" - - start - - .global dcul -dcul: - or_spr_immed 0xc8000000,hsr0 ; caches enabled -- copy-back mode - - ; preload and lock all the lines in set 0 of the data cache - set_gr_immed 0x70000,gr10 - lock_data_cache gr10 - set_mem_immed 0x11111111,gr10 - test_mem_immed 0x11111111,gr10 - - inc_gr_immed 0x2000,gr10 - set_gr_immed 1,gr11 - lock_data_cache gr10 - set_mem_immed 0x22222222,gr10 - test_mem_immed 0x22222222,gr10 - - inc_gr_immed 0x2000,gr10 - set_gr_immed 63,gr11 - lock_data_cache gr10 - set_mem_immed 0x33333333,gr10 - test_mem_immed 0x33333333,gr10 - - inc_gr_immed 0x2000,gr10 - set_gr_immed 64,gr11 - lock_data_cache gr10 - set_mem_immed 0x44444444,gr10 - test_mem_immed 0x44444444,gr10 - - ; Now write to another address which should be in the same set - ; the write should go through to memory, since all the lines in the - ; set are locked - inc_gr_immed 0x2000,gr10 - set_mem_immed 0xdeadbeef,gr10 - test_mem_immed 0xdeadbeef,gr10 - - ; Invalidate the data cache. Only the last value stored should have made - ; it through to memory - set_gr_immed 0x70000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0,gr10 - - inc_gr_immed 0x2000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0,gr10 - - inc_gr_immed 0x2000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0,gr10 - - inc_gr_immed 0x2000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0,gr10 - - inc_gr_immed 0x2000,gr10 - invalidate_data_cache gr10 - test_mem_immed 0xdeadbeef,gr10 - - ; Now preload load and lock all the lines in set 0 of the data cache - ; again - set_gr_immed 0x70000,gr10 - lock_data_cache gr10 - set_mem_immed 0x11111111,gr10 - test_mem_immed 0x11111111,gr10 - - inc_gr_immed 0x2000,gr10 - set_gr_immed 1,gr11 - lock_data_cache gr10 - set_mem_immed 0x22222222,gr10 - test_mem_immed 0x22222222,gr10 - - inc_gr_immed 0x2000,gr10 - set_gr_immed 63,gr11 - lock_data_cache gr10 - set_mem_immed 0x33333333,gr10 - test_mem_immed 0x33333333,gr10 - - inc_gr_immed 0x2000,gr10 - set_gr_immed 64,gr11 - lock_data_cache gr10 - set_mem_immed 0x44444444,gr10 - test_mem_immed 0x44444444,gr10 - - ; unlock one line - set_gr_immed 0x78000,gr10 - dcul gr10 - - ; Now write to another address which should be in the same set. - set_gr_immed 0x7a000,gr10 - set_mem_immed 0xbeefdead,gr10 - - ; All of the stored values should be retrievable - - set_gr_immed 0x70000,gr10 - test_mem_immed 0x11111111,gr10 - - inc_gr_immed 0x2000,gr10 - test_mem_immed 0x22222222,gr10 - - inc_gr_immed 0x2000,gr10 - test_mem_immed 0x33333333,gr10 - - inc_gr_immed 0x2000,gr10 - test_mem_immed 0x44444444,gr10 - - inc_gr_immed 0x2000,gr10 - test_mem_immed 0xdeadbeef,gr10 - - inc_gr_immed 0x2000,gr10 - test_mem_immed 0xbeefdead,gr10 - - pass diff --git a/sim/testsuite/sim/frv/fr550/mabshs.cgs b/sim/testsuite/sim/frv/fr550/mabshs.cgs deleted file mode 100644 index 9168df8981b..00000000000 --- a/sim/testsuite/sim/frv/fr550/mabshs.cgs +++ /dev/null @@ -1,64 +0,0 @@ -# frv testcase for mabshs $FRj,$FRk -# mach: all - - .include "../testutils.inc" - - start - - .global mabshs -mabshs: - set_fr_iimmed 0x0000,0x0000,fr10 - mabshs fr10,fr11 - test_fr_limmed 0x0000,0x0000,fr11 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0001,0xffff,fr10 - mabshs fr10,fr11 - test_fr_limmed 0x0001,0x0001,fr11 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7fff,0x8001,fr10 - mabshs fr10,fr11 - test_fr_limmed 0x7fff,0x7fff,fr11 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7fff,0x8000,fr10 - mabshs fr10,fr11 - test_fr_limmed 0x7fff,0x7fff,fr11 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8000,0x7fff,fr10 - mabshs fr10,fr11 - test_fr_limmed 0x7fff,0x7fff,fr11 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7fff,0x8000,fr10 - set_fr_iimmed 0x8000,0x7fff,fr11 - mabshs.p fr10,fr12 - mabshs fr11,fr13 - test_fr_limmed 0x7fff,0x7fff,fr12 - test_fr_limmed 0x7fff,0x7fff,fr13 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/fr550/maddaccs.cgs b/sim/testsuite/sim/frv/fr550/maddaccs.cgs deleted file mode 100644 index 262a148470d..00000000000 --- a/sim/testsuite/sim/frv/fr550/maddaccs.cgs +++ /dev/null @@ -1,128 +0,0 @@ -# frv testcase for maddaccs $ACC40Si,$ACC40Sk -# mach: all - - .include "../testutils.inc" - - start - - .global maddaccs -maddaccs: - set_accg_immed 0,accg0 - set_acc_immed 0x00000000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000000,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x0000,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0xdead0000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x0000beef,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg3 - test_acc_limmed 0xdead,0xbeef,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x0000dead,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xbeef0000,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg3 - test_acc_limmed 0xbeef,0xdead,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x11111111,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg3 - test_acc_limmed 0x2345,0x6789,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xffffffff,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 1,accg3 - test_acc_limmed 0x1234,0x5677,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg3 - test_acc_limmed 0x1234,0x5677,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x7f,accg0 - set_acc_immed 0xfffe7ffe,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x00020001,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x80,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xfffffffe,acc1 - maddaccs acc0,acc3 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0000,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000001,acc1 - set_accg_immed 0,accg4 - set_acc_immed 0x00000001,acc4 - set_accg_immed 0x7f,accg5 - set_acc_immed 0xffffffff,acc5 - maddaccs.p acc0,acc1 - maddaccs acc4,acc5 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0002,acc1 - test_accg_immed 0x7f,accg5 - test_acc_limmed 0xffff,0xffff,acc5 - - pass diff --git a/sim/testsuite/sim/frv/fr550/maddhss.cgs b/sim/testsuite/sim/frv/fr550/maddhss.cgs deleted file mode 100644 index 8c5c7143659..00000000000 --- a/sim/testsuite/sim/frv/fr550/maddhss.cgs +++ /dev/null @@ -1,97 +0,0 @@ -# frv testcase for maddhss $FRi,$FRj,$FRj -# mach: all - - .include "../testutils.inc" - - start - - .global maddhss -maddhss: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0xbeef,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0x2345,0x6789,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0x1233,0x5677,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0x7fff,0x7fff,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - maddhss fr10,fr11,fr12 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - maddhss.p fr10,fr10,fr12 - maddhss fr11,fr11,fr13 - test_fr_limmed 0x0002,0x0002,fr12 - test_fr_limmed 0x7fff,0x7fff,fr13 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/fr550/maddhus.cgs b/sim/testsuite/sim/frv/fr550/maddhus.cgs deleted file mode 100644 index 93d06bd5251..00000000000 --- a/sim/testsuite/sim/frv/fr550/maddhus.cgs +++ /dev/null @@ -1,86 +0,0 @@ -# frv testcase for maddhus $FRi,$FRj,$FRj -# mach: all - - .include "../testutils.inc" - - start - - .global maddhus -maddhus: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - maddhus fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - maddhus fr10,fr11,fr12 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - maddhus fr10,fr11,fr12 - test_fr_limmed 0xbeef,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - maddhus fr10,fr11,fr12 - test_fr_limmed 0x2345,0x6789,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - maddhus fr10,fr11,fr12 - test_fr_limmed 0x8000,0x7fff,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xfffe,0xfffe,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - maddhus fr10,fr11,fr12 - test_fr_limmed 0xffff,0xffff,fr12 - test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - maddhus fr10,fr11,fr12 - test_fr_limmed 0xffff,0xffff,fr12 - test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - maddhus.p fr10,fr10,fr12 - maddhus fr11,fr11,fr13 - test_fr_limmed 0x0002,0x0002,fr12 - test_fr_limmed 0xffff,0xffff,fr13 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/fr550/masaccs.cgs b/sim/testsuite/sim/frv/fr550/masaccs.cgs deleted file mode 100644 index 9595d161e5c..00000000000 --- a/sim/testsuite/sim/frv/fr550/masaccs.cgs +++ /dev/null @@ -1,148 +0,0 @@ -# frv testcase for masaccs $ACC40Si,$ACC40Sk -# mach: all - - .include "../testutils.inc" - - start - - .global masaccs -masaccs: - set_accg_immed 0,accg0 - set_acc_immed 0x00000000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000000,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x0000,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0xdead0000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x0000beef,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0xdead,0xbeef,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0xdeac,0x4111,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x0000dead,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xbeef0000,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0xbeef,0xdead,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0x4111,0xdead,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x11111111,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0x2345,0x6789,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0123,0x4567,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xffffffff,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set - test_accg_immed 1,accg2 - test_acc_limmed 0x1234,0x5677,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0x1234,0x5679,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msro.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0x1234,0x5677,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x1234,0x5679,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x7f,accg0 - set_acc_immed 0xfffe7ffe,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x00020001,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xfffc,0x7ffd,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x80,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xfffffffe,acc1 - masaccs acc0,acc2 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x80,accg2 - test_acc_limmed 0x0000,0x0000,acc2 - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0003,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000001,acc1 - set_accg_immed 0,accg4 - set_acc_immed 0x00000001,acc4 - set_accg_immed 0x7f,accg5 - set_acc_immed 0xffffffff,acc5 - masaccs.p acc0,acc0 - masaccs acc4,acc4 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0000,acc1 - test_accg_immed 0x7f,accg4 - test_acc_limmed 0xffff,0xffff,acc4 - test_accg_immed 0x80,accg5 - test_acc_limmed 0x0000,0x0002,acc5 - - pass diff --git a/sim/testsuite/sim/frv/fr550/mdaddaccs.cgs b/sim/testsuite/sim/frv/fr550/mdaddaccs.cgs deleted file mode 100644 index 92d23d0b23a..00000000000 --- a/sim/testsuite/sim/frv/fr550/mdaddaccs.cgs +++ /dev/null @@ -1,102 +0,0 @@ -# frv testcase for mdaddaccs $ACC40Si,$ACC40Sk -# mach: all - - .include "../testutils.inc" - - start - - .global mdaddaccs -mdaddaccs: - set_accg_immed 0,accg0 - set_acc_immed 0x00000000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000000,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0xdead0000,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0x0000beef,acc3 - mdaddaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0xdead,0xbeef,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x0000dead,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xbeef0000,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x12345678,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0x11111111,acc3 - mdaddaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0xbeef,0xdead,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x2345,0x6789,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x12345678,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - mdaddaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 1,accg2 - test_acc_limmed 0x1234,0x5677,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x1234,0x5677,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x7f,accg0 - set_acc_immed 0xfffe7ffe,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x00020001,acc1 - set_accg_immed 0x80,accg2 - set_acc_immed 0x00000001,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xfffffffe,acc3 - mdaddaccs acc0,acc2 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0000,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000001,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x00000001,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - mdaddaccs acc0,acc2 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0002,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - pass diff --git a/sim/testsuite/sim/frv/fr550/mdasaccs.cgs b/sim/testsuite/sim/frv/fr550/mdasaccs.cgs deleted file mode 100644 index 88216212fbf..00000000000 --- a/sim/testsuite/sim/frv/fr550/mdasaccs.cgs +++ /dev/null @@ -1,122 +0,0 @@ -# frv testcase for mdasaccs $ACC40Si,$ACC40Sk -# mach: all - - .include "../testutils.inc" - - start - - .global mdasaccs -mdasaccs: - set_accg_immed 0,accg0 - set_acc_immed 0x00000000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000000,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0xdead0000,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0x0000beef,acc3 - mdasaccs acc0,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0000,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0xdead,0xbeef,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0xdeac,0x4111,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x0000dead,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xbeef0000,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x12345678,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0x11111111,acc3 - mdasaccs acc0,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0xbeef,0xdead,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0x4111,0xdead,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x2345,0x6789,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0123,0x4567,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x12345678,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - mdasaccs acc0,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 1,accg0 - test_acc_limmed 0x1234,0x5677,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0x1234,0x5679,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x1234,0x5677,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x1234,0x5679,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x7f,accg0 - set_acc_immed 0xfffe7ffe,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x00020001,acc1 - set_accg_immed 0x80,accg2 - set_acc_immed 0x00000001,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xfffffffe,acc3 - mdasaccs acc0,acc0 - test_spr_bits 0x3c,2,0xa,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xfffc,0x7ffd,acc1 - test_accg_immed 0x80,accg2 - test_acc_limmed 0x0000,0x0000,acc2 - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0003,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000001,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x00000001,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - mdasaccs acc0,acc0 - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0000,acc1 - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0002,acc3 - - pass diff --git a/sim/testsuite/sim/frv/fr550/mdsubaccs.cgs b/sim/testsuite/sim/frv/fr550/mdsubaccs.cgs deleted file mode 100644 index 1fe7498c4ff..00000000000 --- a/sim/testsuite/sim/frv/fr550/mdsubaccs.cgs +++ /dev/null @@ -1,102 +0,0 @@ -# frv testcase for mdsubaccs $ACC40Si,$ACC40Sk -# mach: all - - .include "../testutils.inc" - - start - - .global mdsubaccs -mdsubaccs: - set_accg_immed 0,accg0 - set_acc_immed 0x00000000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000000,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0xdead0000,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0x0000beef,acc3 - mdsubaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0xdeac,0x4111,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x0000dead,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xbeef0000,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x12345678,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0x11111111,acc3 - mdsubaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg2 - test_acc_limmed 0x4111,0xdead,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0123,0x4567,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x12345678,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - mdsubaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg2 - test_acc_limmed 0x1234,0x5679,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x1234,0x5679,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x7f,accg0 - set_acc_immed 0xfffffffe,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xfffffffe,acc1 - set_accg_immed 0x80,accg2 - set_acc_immed 0x00000001,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0x00000002,acc3 - mdsubaccs acc0,acc2 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0000,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000001,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x00000001,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0x00000000,acc3 - mdsubaccs acc0,acc2 - test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0000,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - pass diff --git a/sim/testsuite/sim/frv/fr550/mmachs.cgs b/sim/testsuite/sim/frv/fr550/mmachs.cgs deleted file mode 100644 index 90140765844..00000000000 --- a/sim/testsuite/sim/frv/fr550/mmachs.cgs +++ /dev/null @@ -1,259 +0,0 @@ -# frv testcase for mmachs $GRi,$GRj,$ACCk -# mach: all - - .include "../testutils.inc" - - start - - .global mmachs -mmachs: - ; Positive operands - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0,0x8006,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0001,0x0006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0001,0x0006,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0007,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0007,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0001,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xffff,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xffff,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xffff,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xffff,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xbffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xbffd,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x3ffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x3ffd,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffd,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffd,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xc003,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xc003,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xc005,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xc005,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x3ffec006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3ffec006,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x7ffec006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x7ffec006,acc1 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - mmachs fr7,fr8,acc0 - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr7 - set_fr_iimmed 1,0xffff,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0x8000,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - pass - - diff --git a/sim/testsuite/sim/frv/fr550/mmachu.cgs b/sim/testsuite/sim/frv/fr550/mmachu.cgs deleted file mode 100644 index cd5c03c32ec..00000000000 --- a/sim/testsuite/sim/frv/fr550/mmachu.cgs +++ /dev/null @@ -1,146 +0,0 @@ -# frv testcase for mmachu $GRi,$GRj,$GRk -# mach: all - - .include "../testutils.inc" - - start - - .global mmachu -mmachu: - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8006,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0001,0x0006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0001,0x0006,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x00020006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x00020006,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x40010007,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x40010007,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x8001,0x0007,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x8001,0x0007,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 1,accg0 - test_acc_limmed 0x7fff,0x0008,acc0 - test_accg_immed 1,accg1 - test_acc_limmed 0x7fff,0x0008,acc1 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_fr_iimmed 0xffff,0x0000,fr7 - set_fr_iimmed 0xffff,0xffff,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - pass diff --git a/sim/testsuite/sim/frv/fr550/mmrdhs.cgs b/sim/testsuite/sim/frv/fr550/mmrdhs.cgs deleted file mode 100644 index 1aeb1b5793c..00000000000 --- a/sim/testsuite/sim/frv/fr550/mmrdhs.cgs +++ /dev/null @@ -1,263 +0,0 @@ -# frv testcase for mmrdhs $GRi,$GRj,$ACCk -# mach: all - - .include "../testutils.inc" - - start - - .global mmrdhs -mmrdhs: - ; Positive operands - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_immed -6,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -6,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_immed -6,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -6,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_immed -8,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -8,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x7ffa,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0x7ffa,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xfffe,0xfffa,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xfffe,0xfffa,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xbfff,0xfff9,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xbfff,0xfff9,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xbfff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xbfff,0xffff,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xc000,0x0001,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xc000,0x0001,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xc000,0x0001,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xc000,0x0001,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xc000,0x4003,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xc000,0x4003,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xc000,0xc003,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xc000,0xc003,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x4003,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x4003,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x3ffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x3ffd,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x3ffb,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x3ffb,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_immed 0xc0013ffa,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xc0013ffa,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg0 - test_acc_immed 0x80013ffa,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0x80013ffa,acc1 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 0xffff,1,fr7 - set_fr_iimmed 1,0xffff,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_fr_iimmed 0x8000,0x0000,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0,1,fr7 - set_fr_iimmed 1,1,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - pass - - diff --git a/sim/testsuite/sim/frv/fr550/mmrdhu.cgs b/sim/testsuite/sim/frv/fr550/mmrdhu.cgs deleted file mode 100644 index 99378bcc9a1..00000000000 --- a/sim/testsuite/sim/frv/fr550/mmrdhu.cgs +++ /dev/null @@ -1,151 +0,0 @@ -# frv testcase for mmrdhu $GRi,$GRj,$GRk -# mach: all - - .include "../testutils.inc" - - start - - .global mmrdhu -mmrdhu: - set_accg_immed 0x80,accg0 - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 - test_acc_immed 0xfffffffa,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xfffffffa,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 - test_acc_immed 0xfffffff8,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xfffffff8,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 - test_acc_immed 0xfffffff8,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xfffffff8,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0x7ffa,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0x7ffa,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xfffe,0xfffa,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xfffe,0xfffa,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xfffd,0xfffa,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xfffd,0xfffa,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xbffe,0xfff9,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xbffe,0xfff9,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0x7ffe,0xfff9,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0x7ffe,0xfff9,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0x7e,accg0 - test_acc_limmed 0x8000,0xfff8,acc0 - test_accg_immed 0x7e,accg1 - test_acc_limmed 0x8000,0xfff8,acc1 - - set_accg_immed 0,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0xffff,fr7 - set_fr_iimmed 0xffff,0xffff,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - pass diff --git a/sim/testsuite/sim/frv/fr550/mqaddhss.cgs b/sim/testsuite/sim/frv/fr550/mqaddhss.cgs deleted file mode 100644 index b0c7853ee46..00000000000 --- a/sim/testsuite/sim/frv/fr550/mqaddhss.cgs +++ /dev/null @@ -1,76 +0,0 @@ -# frv testcase for mqaddhss $FRi,$FRj,$FRj -# mach: all - - .include "../testutils.inc" - - start - - .global mqaddhss -mqaddhss: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - mqaddhss fr10,fr12,fr14 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - mqaddhss fr10,fr12,fr14 - test_fr_limmed 0xbeef,0xdead,fr14 - test_fr_limmed 0x2345,0x6789,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - mqaddhss fr10,fr12,fr14 - test_fr_limmed 0x1233,0x5677,fr14 - test_fr_limmed 0x7fff,0x7fff,fr15 - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0xffff,0xfffe,fr12 - set_fr_iimmed 0xfffe,0xfffe,fr13 - mqaddhss fr10,fr12,fr14 - test_fr_limmed 0x8000,0x8000,fr14 - test_fr_limmed 0x8000,0x8000,fr15 - test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x7fff,0x0000,fr12 - set_fr_iimmed 0x0000,0x8000,fr13 - mqaddhss.p fr10,fr10,fr14 - mqaddhss fr12,fr12,fr16 - test_fr_limmed 0x0002,0x0002,fr14 - test_fr_limmed 0xfffe,0xfffe,fr15 - test_fr_limmed 0x7fff,0x0000,fr16 - test_fr_limmed 0x0000,0x8000,fr17 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/fr550/mqaddhus.cgs b/sim/testsuite/sim/frv/fr550/mqaddhus.cgs deleted file mode 100644 index 7f8b7550a95..00000000000 --- a/sim/testsuite/sim/frv/fr550/mqaddhus.cgs +++ /dev/null @@ -1,62 +0,0 @@ -# frv testcase for mqaddhus $FRi,$FRj,$FRj -# mach: all - - .include "../testutils.inc" - - start - - .global mqaddhus -mqaddhus: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - mqaddhus fr10,fr12,fr14 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - mqaddhus fr10,fr12,fr14 - test_fr_limmed 0xbeef,0xdead,fr14 - test_fr_limmed 0x2345,0x6789,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - set_fr_iimmed 0x0002,0x0001,fr12 - set_fr_iimmed 0x0001,0x0002,fr13 - mqaddhus fr10,fr12,fr14 - test_fr_limmed 0x8000,0x7fff,fr14 - test_fr_limmed 0xffff,0xffff,fr15 - test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0xfffe,0xfffe,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - mqaddhus.p fr10,fr10,fr14 - mqaddhus fr12,fr12,fr16 - test_fr_limmed 0x0004,0x0002,fr14 - test_fr_limmed 0x0002,0x0002,fr15 - test_fr_limmed 0xffff,0xffff,fr16 - test_fr_limmed 0xffff,0xffff,fr17 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/fr550/mqmachs.cgs b/sim/testsuite/sim/frv/fr550/mqmachs.cgs deleted file mode 100644 index 2f18620b025..00000000000 --- a/sim/testsuite/sim/frv/fr550/mqmachs.cgs +++ /dev/null @@ -1,211 +0,0 @@ -# frv testcase for mqmachs $GRi,$GRj,$ACCk -# mach: all - - .include "../testutils.inc" - - start - - .global mqmachs -mqmachs: - ; Positive operands - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0,0x7ffe,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0,0x7ffe,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8008,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8008,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x7fff,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x7fff,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8002,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x7ffd,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x7ffd,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8002,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x3ffb,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x3ffb,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0002,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffb,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffb,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0008,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0008,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffd,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffd,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0009,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0009,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x3fffbffd,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x3fffbffd,acc3 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 1,0xffff,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0x80,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - - pass - - diff --git a/sim/testsuite/sim/frv/fr550/mqmachu.cgs b/sim/testsuite/sim/frv/fr550/mqmachu.cgs deleted file mode 100644 index 71cba98b8c1..00000000000 --- a/sim/testsuite/sim/frv/fr550/mqmachu.cgs +++ /dev/null @@ -1,144 +0,0 @@ -# frv testcase for mqmachu $GRi,$GRj,$GRk -# mach: all - - .include "../testutils.inc" - - start - - .global mqmachu -mqmachu: - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - mqmachu fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 2,acc2 - test_accg_immed 0,accg3 - test_acc_immed 2,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - mqmachu fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8000,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - mqmachu fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8006,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x00018000,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x00018000,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - mqmachu fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x3fff8007,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff8007,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x4001,0x8000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x4001,0x8000,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - mqmachu fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 1,accg0 - test_acc_limmed 0x3ffd,0x8008,acc0 - test_accg_immed 1,accg1 - test_acc_limmed 0x3ffd,0x8008,acc1 - test_accg_immed 1,accg2 - test_acc_limmed 0x3fff,0x8001,acc2 - test_accg_immed 1,accg3 - test_acc_limmed 0x3fff,0x8001,acc3 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0xff,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 1,1,fr9 - set_fr_iimmed 1,1,fr11 - mqmachu fr8,fr10,acc0 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_fr_iimmed 0xffff,0x0000,fr8 - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0x0000,0xffff,fr9 - set_fr_iimmed 0xffff,0xffff,fr11 - mqmachu fr8,fr10,acc0 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - pass diff --git a/sim/testsuite/sim/frv/fr550/mqmacxhs.cgs b/sim/testsuite/sim/frv/fr550/mqmacxhs.cgs deleted file mode 100644 index aded33ee006..00000000000 --- a/sim/testsuite/sim/frv/fr550/mqmacxhs.cgs +++ /dev/null @@ -1,211 +0,0 @@ -# frv testcase for mqmacxhs $GRi,$GRj,$ACCk -# mach: all - - .include "../testutils.inc" - - start - - .global mqmacxhs -mqmacxhs: - ; Positive operands - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 0,2,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 2,1,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 0x3fff,2,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0,0x7ffe,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0,0x7ffe,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 0x4000,2,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8008,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8008,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x7fff,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x7fff,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 2,0xfffd,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8002,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x7ffd,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x7ffd,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0xfffe,0,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0x2001,0xfffe,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8002,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x3ffb,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x3ffb,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0x4000,0xfffe,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x7fff,0x8000,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0002,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffb,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffb,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffe,0xfffd,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0008,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0008,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffd,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffd,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0009,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0009,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x3fffbffd,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x3fffbffd,acc3 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 0xffff,1,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0x80,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - - pass - - diff --git a/sim/testsuite/sim/frv/fr550/mqsubhss.cgs b/sim/testsuite/sim/frv/fr550/mqsubhss.cgs deleted file mode 100644 index a8936e98ba4..00000000000 --- a/sim/testsuite/sim/frv/fr550/mqsubhss.cgs +++ /dev/null @@ -1,76 +0,0 @@ -# frv testcase for mqsubhss $FRi,$FRj,$FRj -# mach: all - - .include "../testutils.inc" - - start - - .global msubhss -msubhss: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0x0000,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0xbeef,fr13 - mqsubhss fr10,fr12,fr14 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0x4111,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - set_fr_iimmed 0xbeef,0x0000,fr12 - set_fr_iimmed 0x1111,0x1111,fr13 - mqsubhss fr10,fr12,fr14 - test_fr_limmed 0x4111,0xdead,fr14 - test_fr_limmed 0x0123,0x4567,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0xfffe,0xffff,fr13 - mqsubhss fr10,fr12,fr14 - test_fr_limmed 0x1235,0x5679,fr14 - test_fr_limmed 0x7fff,0x7fff,fr15 - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8001,0x8001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - mqsubhss fr10,fr12,fr14 - test_fr_limmed 0x8000,0x8000,fr14 - test_fr_limmed 0x8000,0x8000,fr15 - test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - set_fr_iimmed 0x8000,0x8000,fr12 - set_fr_iimmed 0x8000,0x8000,fr13 - mqsubhss.p fr10,fr10,fr14 - mqsubhss fr12,fr10,fr16 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_fr_limmed 0x8000,0x8000,fr16 - test_fr_limmed 0x8001,0x8001,fr17 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/fr550/mqsubhus.cgs b/sim/testsuite/sim/frv/fr550/mqsubhus.cgs deleted file mode 100644 index fc92eb5a7fa..00000000000 --- a/sim/testsuite/sim/frv/fr550/mqsubhus.cgs +++ /dev/null @@ -1,63 +0,0 @@ -# frv testcase for msubhus $FRi,$FRj,$FRj -# mach: all - - .include "../testutils.inc" - - start - - .global msubhus -msubhus: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0xdead,0xbeef,fr11 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0x0000,fr13 - mqsubhus fr10,fr12,fr14 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0xdead,0xbeef,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0x1111,0x1111,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - mqsubhus fr10,fr12,fr14 - test_fr_limmed 0x0123,0x4567,fr14 - test_fr_limmed 0x7ffc,0x7ffd,fr15 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0001,fr11 - set_fr_iimmed 0x0001,0x0002,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - mqsubhus fr10,fr12,fr14 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - set_fr_iimmed 0x0000,0x0001,fr12 - set_fr_iimmed 0x0002,0x0003,fr13 - mqsubhus.p fr10,fr10,fr14 - mqsubhus fr10,fr12,fr16 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - test_fr_limmed 0x0001,0x0000,fr16 - test_fr_limmed 0x0000,0x0000,fr17 - test_spr_bits 0x3c,2,0x1,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/fr550/mqxmachs.cgs b/sim/testsuite/sim/frv/fr550/mqxmachs.cgs deleted file mode 100644 index 3c08e416b74..00000000000 --- a/sim/testsuite/sim/frv/fr550/mqxmachs.cgs +++ /dev/null @@ -1,211 +0,0 @@ -# frv testcase for mqxmachs $GRi,$GRj,$ACCk -# mach: all - - .include "../testutils.inc" - - start - - .global mqxmachs -mqxmachs: - ; Positive operands - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0,accg2 - test_acc_immed 6,acc2 - test_accg_immed 0,accg3 - test_acc_immed 6,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_immed 8,acc2 - test_accg_immed 0,accg3 - test_acc_immed 8,acc3 - test_accg_immed 0,accg0 - test_acc_limmed 0,0x7ffe,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0,0x7ffe,acc1 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8008,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8008,acc3 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x7fff,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x7fff,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8002,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8002,acc3 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x7ffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x7ffd,acc1 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8002,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8002,acc3 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x3ffb,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x3ffb,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0002,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x0002,acc3 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffb,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffb,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0008,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x0008,acc3 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffd,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffd,acc1 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_immed 0x3fff0009,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x3fff0009,acc3 - test_accg_immed 0,accg0 - test_acc_immed 0x3fffbffd,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fffbffd,acc1 - - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 1,0xffff,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - pass - - diff --git a/sim/testsuite/sim/frv/fr550/mqxmacxhs.cgs b/sim/testsuite/sim/frv/fr550/mqxmacxhs.cgs deleted file mode 100644 index 32b043b67e5..00000000000 --- a/sim/testsuite/sim/frv/fr550/mqxmacxhs.cgs +++ /dev/null @@ -1,211 +0,0 @@ -# frv testcase for mqxmacxhs $GRi,$GRj,$ACCk -# mach: all - - .include "../testutils.inc" - - start - - .global mqxmacxhs -mqxmacxhs: - ; Positive operands - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 0,2,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0,accg2 - test_acc_immed 6,acc2 - test_accg_immed 0,accg3 - test_acc_immed 6,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 2,1,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 0x3fff,2,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_immed 8,acc2 - test_accg_immed 0,accg3 - test_acc_immed 8,acc3 - test_accg_immed 0,accg0 - test_acc_limmed 0,0x7ffe,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0,0x7ffe,acc1 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 0x4000,2,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8008,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8008,acc3 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x7fff,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x7fff,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 2,0xfffd,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8002,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8002,acc3 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x7ffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x7ffd,acc1 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0xfffe,0,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0x2001,0xfffe,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8002,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8002,acc3 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x3ffb,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x3ffb,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0x4000,0xfffe,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x7fff,0x8000,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0002,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x0002,acc3 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffb,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffb,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffe,0xfffd,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0008,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x0008,acc3 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffd,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffd,acc1 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg2 - test_acc_immed 0x3fff0009,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x3fff0009,acc3 - test_accg_immed 0,accg0 - test_acc_immed 0x3fffbffd,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fffbffd,acc1 - - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 0xffff,1,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - pass - - diff --git a/sim/testsuite/sim/frv/fr550/msubaccs.cgs b/sim/testsuite/sim/frv/fr550/msubaccs.cgs deleted file mode 100644 index eeaf4a6080f..00000000000 --- a/sim/testsuite/sim/frv/fr550/msubaccs.cgs +++ /dev/null @@ -1,128 +0,0 @@ -# frv testcase for msubaccs $ACC40Si,$ACC40Sk -# mach: all - - .include "../testutils.inc" - - start - - .global msubaccs -msubaccs: - set_accg_immed 0,accg0 - set_acc_immed 0x00000000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000000,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x0000,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0xdead0000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x0000beef,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg3 - test_acc_limmed 0xdeac,0x4111,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x0000dead,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xbeef0000,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg3 - test_acc_limmed 0x4111,0xdead,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x11111111,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg3 - test_acc_limmed 0x0123,0x4567,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xffffffff,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0xff,accg3 - test_acc_limmed 0x1234,0x5679,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - test_accg_immed 0,accg3 - test_acc_limmed 0x1234,0x5679,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x7f,accg0 - set_acc_immed 0xfffffffe,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xfffffffe,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x80,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000002,acc1 - msubaccs acc0,acc3 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0000,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000001,acc1 - set_accg_immed 0,accg4 - set_acc_immed 0x00000001,acc4 - set_accg_immed 0x80,accg5 - set_acc_immed 0x00000000,acc5 - msubaccs.p acc0,acc1 - msubaccs acc4,acc5 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0000,acc1 - test_accg_immed 0x7f,accg5 - test_acc_limmed 0xffff,0xffff,acc5 - - pass diff --git a/sim/testsuite/sim/frv/fr550/msubhss.cgs b/sim/testsuite/sim/frv/fr550/msubhss.cgs deleted file mode 100644 index 6beb6764462..00000000000 --- a/sim/testsuite/sim/frv/fr550/msubhss.cgs +++ /dev/null @@ -1,97 +0,0 @@ -# frv testcase for msubhss $FRi,$FRj,$FRj -# mach: all - - .include "../testutils.inc" - - start - - .global msubhss -msubhss: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - msubhss fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - msubhss fr10,fr11,fr12 - test_fr_limmed 0xdead,0x4111,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - msubhss fr10,fr11,fr12 - test_fr_limmed 0x4111,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - msubhss fr10,fr11,fr12 - test_fr_limmed 0x0123,0x4567,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - msubhss fr10,fr11,fr12 - test_fr_limmed 0x1235,0x5679,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xffff,fr11 - msubhss fr10,fr11,fr12 - test_fr_limmed 0x7fff,0x7fff,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - msubhss fr10,fr11,fr12 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - msubhss fr10,fr11,fr12 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - msubhss.p fr10,fr10,fr12 - msubhss fr11,fr10,fr13 - test_fr_limmed 0x0000,0x0000,fr12 - test_fr_limmed 0x8000,0x8000,fr13 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/fr550/msubhus.cgs b/sim/testsuite/sim/frv/fr550/msubhus.cgs deleted file mode 100644 index 5a3cd26f773..00000000000 --- a/sim/testsuite/sim/frv/fr550/msubhus.cgs +++ /dev/null @@ -1,77 +0,0 @@ -# frv testcase for msubhus $FRi,$FRj,$FRj -# mach: all - - .include "../testutils.inc" - - start - - .global msubhus -msubhus: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - msubhus fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0xdead,0xbeef,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - msubhus fr10,fr11,fr12 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - msubhus fr10,fr11,fr12 - test_fr_limmed 0x0123,0x4567,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - msubhus fr10,fr11,fr12 - test_fr_limmed 0x7ffc,0x7ffd,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set - - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - msubhus fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - msubhus fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - msubhus.p fr10,fr10,fr12 - msubhus fr10,fr11,fr13 - test_fr_limmed 0x0000,0x0000,fr12 - test_fr_limmed 0x0000,0x0000,fr13 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/fr550/mtrap.cgs b/sim/testsuite/sim/frv/fr550/mtrap.cgs deleted file mode 100644 index 83dca7b875a..00000000000 --- a/sim/testsuite/sim/frv/fr550/mtrap.cgs +++ /dev/null @@ -1,50 +0,0 @@ -# frv testcase for mp_exception -# mach: all - - .include "../testutils.inc" - - start - - .global mp_exception -mpx: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 0x0e0,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 - set_spr_immed 128,lcr - set_spr_addr ok1,lr - set_psr_et 1 - set_gr_immed 0,gr5 - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - mqaddhss fr10,fr12,fr14 - test_fr_limmed 0x1233,0x5677,fr14 - test_fr_limmed 0x7fff,0x7fff,fr15 - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - mtrap ; generate interrupt - test_gr_immed 1,gr5 - - and_spr_immed 0xffffc000,msr0 ; Clear msr0 fields - mcmpsh fr10,fr11,fcc0 ; no exception - test_spr_bits 0x7000,12,1,msr0; msr0.mtt is always set - mtrap ; nop - test_gr_immed 1,gr5 - - pass - -; exception handler -ok1: - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - inc_gr_immed 1,gr5 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/fr550/udiv.cgs b/sim/testsuite/sim/frv/fr550/udiv.cgs deleted file mode 100644 index 05cbde425ab..00000000000 --- a/sim/testsuite/sim/frv/fr550/udiv.cgs +++ /dev/null @@ -1,48 +0,0 @@ -# frv testcase for udiv $GRi,$GRj,$GRk -# mach: all - - .include "../testutils.inc" - - start - - .global udiv -udiv: - ; simple division 12 / 3 - set_gr_immed 0x00000003,gr2 - set_gr_immed 0x0000000c,gr3 - udiv gr3,gr2,gr3 - test_gr_immed 0x00000003,gr2 - test_gr_immed 0x00000004,gr3 - - ; example 1 from udiv in the fr30 manual - set_gr_limmed 0x0123,0x4567,gr2 - set_gr_limmed 0xfedc,0xba98,gr3 - udiv gr3,gr2,gr3 - test_gr_limmed 0x0123,0x4567,gr2 - test_gr_immed 0x000000e0,gr3 - - ; set up exception handler - set_psr_et 1 - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x170,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_gr_immed 0,gr15 - - ; divide by zero - set_spr_addr ok1,lr - set_gr_addr e1,gr17 -e1: udiv gr1,gr0,gr2 ; divide by zero - test_gr_immed 1,gr15 - - pass - -ok1: ; exception handler for divide by zero - test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set - test_spr_gr epcr0,gr17 ; return address set - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/fr550/udivi.cgs b/sim/testsuite/sim/frv/fr550/udivi.cgs deleted file mode 100644 index d5ee1c4c145..00000000000 --- a/sim/testsuite/sim/frv/fr550/udivi.cgs +++ /dev/null @@ -1,49 +0,0 @@ -# frv testcase for udivi $GRi,$s12,$GRk -# mach: all - - .include "../testutils.inc" - - start - - .global udivi -udivi: - ; simple division 12 / 3 - set_gr_immed 0x0000000c,gr3 - udivi gr3,3,gr3 - test_gr_immed 0x00000004,gr3 - - ; random example - set_gr_limmed 0xfedc,0xba98,gr3 - udivi gr3,0x7ff,gr3 - test_gr_limmed 0x001f,0xdf93,gr3 - - ; random example - set_gr_limmed 0xffff,0xffff,gr3 - udivi gr3,-2048,gr3 - test_gr_immed 1,gr3 - - ; set up exception handler - set_psr_et 1 - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x170,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_gr_immed 0,gr15 - - ; divide by zero - set_spr_addr ok1,lr - set_gr_addr e1,gr17 -e1: udivi gr1,0,gr2 ; divide by zero - test_gr_immed 1,gr15 - - pass - -ok1: ; exception handler for divide by zero - test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set - test_spr_gr epcr0,gr17 ; return address set - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/fsqrtd.cgs b/sim/testsuite/sim/frv/fsqrtd.cgs deleted file mode 100644 index a428b013b6e..00000000000 --- a/sim/testsuite/sim/frv/fsqrtd.cgs +++ /dev/null @@ -1,22 +0,0 @@ -# frv testcase for fsqrtd $FRj,$FRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - double_constants - start - load_double_constants - - .global fsqrtd -fsqrtd: - fsqrtd fr44,fr2 ; 9.0 - test_dfr_dfr fr2,fr36 ; 3.0 - - set_fr_iimmed 0x4009,0x21fb,fr10 ; 3.141592654 - set_fr_iimmed 0x6000,0x0000,fr11 - fsqrtd fr10,fr10 - test_fr_iimmed 0x3ffc5bf8,fr10 ; 1.7724539 - test_fr_iimmed 0x9853a94d,fr11 - - pass diff --git a/sim/testsuite/sim/frv/fsqrts.cgs b/sim/testsuite/sim/frv/fsqrts.cgs deleted file mode 100644 index e771c40b070..00000000000 --- a/sim/testsuite/sim/frv/fsqrts.cgs +++ /dev/null @@ -1,19 +0,0 @@ -# frv testcase for fsqrts $FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fsqrts -fsqrts: - fsqrts fr44,fr1 ; 9.0 - test_fr_fr fr1,fr36 ; 3.0 - - set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 - fsqrts fr10,fr10 - test_fr_iimmed 0x3fe2dfc5,fr10 ; 1.7724539 - - pass diff --git a/sim/testsuite/sim/frv/fstoi.cgs b/sim/testsuite/sim/frv/fstoi.cgs deleted file mode 100644 index 0a90a2aec2e..00000000000 --- a/sim/testsuite/sim/frv/fstoi.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# frv testcase for fstoi $FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fstoi -fstoi: - fstoi fr16,fr1 - test_fr_iimmed 0,fr1 - fstoi fr20,fr1 - test_fr_iimmed 0,fr1 - - fstoi fr32,fr1 - test_fr_iimmed 0x00000002,fr1 - - set_fr_iimmed 0xce05,0x4904,fr1 - fstoi fr1,fr1 - test_fr_iimmed 0xdeadbf00,fr1 - - pass diff --git a/sim/testsuite/sim/frv/fsubd.cgs b/sim/testsuite/sim/frv/fsubd.cgs deleted file mode 100644 index fed2d04aaf7..00000000000 --- a/sim/testsuite/sim/frv/fsubd.cgs +++ /dev/null @@ -1,83 +0,0 @@ -# frv testcase for fsubd $GRi,$GRj,$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - double_constants - start - load_double_constants - - .global fsubd -fsubd: - fsubd fr0,fr16,fr2 - test_dfr_dfr fr2,fr0 - fsubd fr4,fr16,fr2 - test_dfr_dfr fr2,fr4 - fsubd fr8,fr16,fr2 - test_dfr_dfr fr2,fr8 - fsubd fr12,fr16,fr2 - test_dfr_dfr fr2,fr12 - fsubd fr16,fr16,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fsubd fr20,fr16,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fsubd fr24,fr16,fr2 - test_dfr_dfr fr2,fr24 - fsubd fr28,fr16,fr2 - test_dfr_dfr fr2,fr28 - fsubd fr32,fr16,fr2 - test_dfr_dfr fr2,fr32 - fsubd fr36,fr16,fr2 - test_dfr_dfr fr2,fr36 - fsubd fr40,fr16,fr2 - test_dfr_dfr fr2,fr40 - fsubd fr44,fr16,fr2 - test_dfr_dfr fr2,fr44 - fsubd fr48,fr16,fr2 - test_dfr_dfr fr2,fr48 - fsubd fr52,fr16,fr2 - test_dfr_dfr fr2,fr52 - - fsubd fr0,fr20,fr2 - test_dfr_dfr fr2,fr0 - fsubd fr4,fr20,fr2 - test_dfr_dfr fr2,fr4 - fsubd fr8,fr20,fr2 - test_dfr_dfr fr2,fr8 - fsubd fr12,fr20,fr2 - test_dfr_dfr fr2,fr12 - fsubd fr16,fr20,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fsubd fr20,fr20,fr2 - test_dfr_dfr fr2,fr16 - test_dfr_dfr fr2,fr20 - fsubd fr24,fr20,fr2 - test_dfr_dfr fr2,fr24 - fsubd fr28,fr20,fr2 - test_dfr_dfr fr2,fr28 - fsubd fr32,fr20,fr2 - test_dfr_dfr fr2,fr32 - fsubd fr36,fr20,fr2 - test_dfr_dfr fr2,fr36 - fsubd fr40,fr20,fr2 - test_dfr_dfr fr2,fr40 - fsubd fr44,fr20,fr2 - test_dfr_dfr fr2,fr44 - fsubd fr48,fr20,fr2 - test_dfr_dfr fr2,fr48 - fsubd fr52,fr20,fr2 - test_dfr_dfr fr2,fr52 - - fsubd fr32,fr36,fr2 - test_dfr_dfr fr2,fr8 - - fsubd fr44,fr40,fr2 - test_dfr_dfr fr2,fr36 - - pass - - diff --git a/sim/testsuite/sim/frv/fsubs.cgs b/sim/testsuite/sim/frv/fsubs.cgs deleted file mode 100644 index c1143ade113..00000000000 --- a/sim/testsuite/sim/frv/fsubs.cgs +++ /dev/null @@ -1,82 +0,0 @@ -# frv testcase for fsubs $GRi,$GRj,$GRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global fsubs -fsubs: - fsubs fr0,fr16,fr1 - test_fr_fr fr1,fr0 - fsubs fr4,fr16,fr1 - test_fr_fr fr1,fr4 - fsubs fr8,fr16,fr1 - test_fr_fr fr1,fr8 - fsubs fr12,fr16,fr1 - test_fr_fr fr1,fr12 - fsubs fr16,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fsubs fr20,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fsubs fr24,fr16,fr1 - test_fr_fr fr1,fr24 - fsubs fr28,fr16,fr1 - test_fr_fr fr1,fr28 - fsubs fr32,fr16,fr1 - test_fr_fr fr1,fr32 - fsubs fr36,fr16,fr1 - test_fr_fr fr1,fr36 - fsubs fr40,fr16,fr1 - test_fr_fr fr1,fr40 - fsubs fr44,fr16,fr1 - test_fr_fr fr1,fr44 - fsubs fr48,fr16,fr1 - test_fr_fr fr1,fr48 - fsubs fr52,fr16,fr1 - test_fr_fr fr1,fr52 - - fsubs fr0,fr20,fr1 - test_fr_fr fr1,fr0 - fsubs fr4,fr20,fr1 - test_fr_fr fr1,fr4 - fsubs fr8,fr20,fr1 - test_fr_fr fr1,fr8 - fsubs fr12,fr20,fr1 - test_fr_fr fr1,fr12 - fsubs fr16,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fsubs fr20,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - fsubs fr24,fr20,fr1 - test_fr_fr fr1,fr24 - fsubs fr28,fr20,fr1 - test_fr_fr fr1,fr28 - fsubs fr32,fr20,fr1 - test_fr_fr fr1,fr32 - fsubs fr36,fr20,fr1 - test_fr_fr fr1,fr36 - fsubs fr40,fr20,fr1 - test_fr_fr fr1,fr40 - fsubs fr44,fr20,fr1 - test_fr_fr fr1,fr44 - fsubs fr48,fr20,fr1 - test_fr_fr fr1,fr48 - fsubs fr52,fr20,fr1 - test_fr_fr fr1,fr52 - - fsubs fr32,fr36,fr1 - test_fr_fr fr1,fr8 - - fsubs fr44,fr40,fr1 - test_fr_fr fr1,fr36 - - pass - - diff --git a/sim/testsuite/sim/frv/fteq.cgs b/sim/testsuite/sim/frv/fteq.cgs deleted file mode 100644 index 020a88712ee..00000000000 --- a/sim/testsuite/sim/frv/fteq.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for fteq $FCCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global fteq -fteq: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_fcc 0x0 0 - fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x1 0 - fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x2 0 - fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x3 0 - fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x4 0 - fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x5 0 - fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x6 0 - fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x7 0 - fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok8,lr - set_fcc 0x8 0 - fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - fteq fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftge.cgs b/sim/testsuite/sim/frv/ftge.cgs deleted file mode 100644 index eab7a061701..00000000000 --- a/sim/testsuite/sim/frv/ftge.cgs +++ /dev/null @@ -1,109 +0,0 @@ -# frv testcase for ftge $FCCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global ftge -ftge: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x1 0 - ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_fcc 0x2 0 - ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_fcc 0x4 0 - ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x5 0 - ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_fcc 0x8 0 - ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftgt.cgs b/sim/testsuite/sim/frv/ftgt.cgs deleted file mode 100644 index 9035fbc8773..00000000000 --- a/sim/testsuite/sim/frv/ftgt.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for ftgt $FCCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global ftgt -ftgt: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x1 0 - ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_fcc 0x2 0 - ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_fcc 0x4 0 - ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x5 0 - ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_fcc 0x8 0 - ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x9 0 - ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_spr_addr bad,lr - set_fcc 0xc 0 - ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0xd 0 - ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftgt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftieq.cgs b/sim/testsuite/sim/frv/ftieq.cgs deleted file mode 100644 index a5710ad10dc..00000000000 --- a/sim/testsuite/sim/frv/ftieq.cgs +++ /dev/null @@ -1,100 +0,0 @@ -# frv testcase for ftieq $FCCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global ftieq -ftieq: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x1 0 - ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x2 0 - ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x3 0 - ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x4 0 - ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x5 0 - ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x6 0 - ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x7 0 - ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok8,lr - set_fcc 0x8 0 - ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftieq fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftige.cgs b/sim/testsuite/sim/frv/ftige.cgs deleted file mode 100644 index 5b58ce0c390..00000000000 --- a/sim/testsuite/sim/frv/ftige.cgs +++ /dev/null @@ -1,108 +0,0 @@ -# frv testcase for ftige $FCCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global ftige -ftige: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x1 0 - ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_fcc 0x2 0 - ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_fcc 0x4 0 - ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x5 0 - ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_fcc 0x8 0 - ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftige fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftigt.cgs b/sim/testsuite/sim/frv/ftigt.cgs deleted file mode 100644 index e31ead4cfe3..00000000000 --- a/sim/testsuite/sim/frv/ftigt.cgs +++ /dev/null @@ -1,100 +0,0 @@ -# frv testcase for ftigt $FCCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global ftigt -ftigt: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x1 0 - ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_fcc 0x2 0 - ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_fcc 0x4 0 - ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x5 0 - ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_fcc 0x8 0 - ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x9 0 - ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_spr_addr bad,lr - set_fcc 0xc 0 - ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0xd 0 - ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftigt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftile.cgs b/sim/testsuite/sim/frv/ftile.cgs deleted file mode 100644 index d13eeee67de..00000000000 --- a/sim/testsuite/sim/frv/ftile.cgs +++ /dev/null @@ -1,108 +0,0 @@ -# frv testcase for ftile $FCCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global ftile -ftile: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x1 0 - ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x2 0 - ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x3 0 - ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok4,lr - set_fcc 0x4 0 - ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_fcc 0x8 0 - ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftilg.cgs b/sim/testsuite/sim/frv/ftilg.cgs deleted file mode 100644 index 26127d25aa7..00000000000 --- a/sim/testsuite/sim/frv/ftilg.cgs +++ /dev/null @@ -1,108 +0,0 @@ -# frv testcase for ftilg $FCCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global ftilg -ftilg: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x1 0 - ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_fcc 0x2 0 - ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_fcc 0x4 0 - ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_fcc 0x8 0 - ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x9 0 - ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftilt.cgs b/sim/testsuite/sim/frv/ftilt.cgs deleted file mode 100644 index 7a74d5b6c20..00000000000 --- a/sim/testsuite/sim/frv/ftilt.cgs +++ /dev/null @@ -1,100 +0,0 @@ -# frv testcase for ftilt $FCCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global ftilt -ftilt: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x1 0 - ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x2 0 - ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x3 0 - ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok4,lr - set_fcc 0x4 0 - ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_fcc 0x8 0 - ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x9 0 - ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0xa 0 - ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0xb 0 - ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftilt fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftine.cgs b/sim/testsuite/sim/frv/ftine.cgs deleted file mode 100644 index 89aa5a6302d..00000000000 --- a/sim/testsuite/sim/frv/ftine.cgs +++ /dev/null @@ -1,112 +0,0 @@ -# frv testcase for ftine $FCCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global ftine -ftine: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_fcc 0x1 0 - ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_psr_et 1 - set_spr_addr ok2,lr - set_fcc 0x2 0 - ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_fcc 0x4 0 - ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_fcc 0x8 0 - ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftine fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftino.cgs b/sim/testsuite/sim/frv/ftino.cgs deleted file mode 100644 index b08a571a356..00000000000 --- a/sim/testsuite/sim/frv/ftino.cgs +++ /dev/null @@ -1,53 +0,0 @@ -# frv testcase for ftino -# mach: all - - .include "testutils.inc" - - start - - .global ftinev -ftinev: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_mem_limmed 0x0038,0x2000,gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_gr_immed 0,gr7 - - set_fcc 0x0 0 - ftino ; should branch to tbr + (128 + 4)*16 - set_fcc 0x1 0 - ftino ; should branch to tbr + (128 + 4)*16 - set_fcc 0x2 0 - ftino ; should branch to tbr + (128 + 4)*16 - set_fcc 0x3 0 - ftino ; should branch to tbr + (128 + 4)*16 - set_fcc 0x4 0 - ftino ; should branch to tbr + (128 + 4)*16 - set_fcc 0x5 0 - ftino ; should branch to tbr + (128 + 4)*16 - set_fcc 0x6 0 - ftino ; should branch to tbr + (128 + 4)*16 - set_fcc 0x7 0 - ftino ; should branch to tbr + (128 + 4)*16 - set_fcc 0x8 0 - ftino ; should branch to tbr + (128 + 4)*16 - set_fcc 0x9 0 - ftino ; should branch to tbr + (128 + 4)*16 - set_fcc 0xa 0 - ftino ; should branch to tbr + (128 + 4)*16 - set_fcc 0xb 0 - ftino ; should branch to tbr + (128 + 4)*16 - set_fcc 0xc 0 - ftino ; should branch to tbr + (128 + 4)*16 - set_fcc 0xd 0 - ftino ; should branch to tbr + (128 + 4)*16 - set_fcc 0xe 0 - ftino ; should branch to tbr + (128 + 4)*16 - set_fcc 0xf 0 - ftino ; should branch to tbr + (128 + 4)*16 - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftio.cgs b/sim/testsuite/sim/frv/ftio.cgs deleted file mode 100644 index 083c17064f5..00000000000 --- a/sim/testsuite/sim/frv/ftio.cgs +++ /dev/null @@ -1,112 +0,0 @@ -# frv testcase for ftio $FCCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global ftio -ftio: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x1 0 - ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_fcc 0x2 0 - ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_fcc 0x4 0 - ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_fcc 0x8 0 - ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftio fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftira.cgs b/sim/testsuite/sim/frv/ftira.cgs deleted file mode 100644 index 9382b2b84ae..00000000000 --- a/sim/testsuite/sim/frv/ftira.cgs +++ /dev/null @@ -1,114 +0,0 @@ -# frv testcase for ftira $GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global ftira -ftira: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_psr_et 1 - set_spr_addr ok0,lr - set_fcc 0x0 0 - ftira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_psr_et 1 - set_spr_addr ok1,lr - set_fcc 0x1 0 - ftira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_psr_et 1 - set_spr_addr ok2,lr - set_fcc 0x2 0 - ftira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_fcc 0x4 0 - ftira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_fcc 0x8 0 - ftira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass diff --git a/sim/testsuite/sim/frv/ftiu.cgs b/sim/testsuite/sim/frv/ftiu.cgs deleted file mode 100644 index adc40bead17..00000000000 --- a/sim/testsuite/sim/frv/ftiu.cgs +++ /dev/null @@ -1,100 +0,0 @@ -# frv testcase for ftiu $FCCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global ftiu -ftiu: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_fcc 0x1 0 - ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_fcc 0x2 0 - ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_fcc 0x4 0 - ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_spr_addr bad,lr - set_fcc 0x6 0 - ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_fcc 0x8 0 - ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_spr_addr bad,lr - set_fcc 0xa 0 - ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_spr_addr bad,lr - set_fcc 0xc 0 - ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_spr_addr bad,lr - set_fcc 0xe 0 - ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftiu fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftiue.cgs b/sim/testsuite/sim/frv/ftiue.cgs deleted file mode 100644 index 311143430cf..00000000000 --- a/sim/testsuite/sim/frv/ftiue.cgs +++ /dev/null @@ -1,108 +0,0 @@ -# frv testcase for ftiue $FCCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global ftiue -ftiue: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_fcc 0x1 0 - ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_fcc 0x2 0 - ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_fcc 0x4 0 - ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_spr_addr bad,lr - set_fcc 0x6 0 - ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_fcc 0x8 0 - ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftiue fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftiug.cgs b/sim/testsuite/sim/frv/ftiug.cgs deleted file mode 100644 index 9e16f89480e..00000000000 --- a/sim/testsuite/sim/frv/ftiug.cgs +++ /dev/null @@ -1,108 +0,0 @@ -# frv testcase for ftiug $FCCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global ftiug -ftiug: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_fcc 0x1 0 - ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_psr_et 1 - set_spr_addr ok2,lr - set_fcc 0x2 0 - ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_fcc 0x4 0 - ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_fcc 0x8 0 - ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_spr_addr bad,lr - set_fcc 0xc 0 - ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftiug fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftiuge.cgs b/sim/testsuite/sim/frv/ftiuge.cgs deleted file mode 100644 index bda587e7879..00000000000 --- a/sim/testsuite/sim/frv/ftiuge.cgs +++ /dev/null @@ -1,112 +0,0 @@ -# frv testcase for ftiuge $FCCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global ftiuge -ftiuge: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_fcc 0x1 0 - ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_psr_et 1 - set_spr_addr ok2,lr - set_fcc 0x2 0 - ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_fcc 0x4 0 - ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_fcc 0x8 0 - ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftiul.cgs b/sim/testsuite/sim/frv/ftiul.cgs deleted file mode 100644 index ee5e2ba60aa..00000000000 --- a/sim/testsuite/sim/frv/ftiul.cgs +++ /dev/null @@ -1,108 +0,0 @@ -# frv testcase for ftiul $FCCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global ftiul -ftiul: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_fcc 0x1 0 - ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_fcc 0x2 0 - ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_fcc 0x4 0 - ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_fcc 0x8 0 - ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_spr_addr bad,lr - set_fcc 0xa 0 - ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftle.cgs b/sim/testsuite/sim/frv/ftle.cgs deleted file mode 100644 index 4ffa760577c..00000000000 --- a/sim/testsuite/sim/frv/ftle.cgs +++ /dev/null @@ -1,109 +0,0 @@ -# frv testcase for ftle $FCCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global ftle -ftle: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x1 0 - ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x2 0 - ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x3 0 - ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok4,lr - set_fcc 0x4 0 - ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_fcc 0x8 0 - ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftle fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftlg.cgs b/sim/testsuite/sim/frv/ftlg.cgs deleted file mode 100644 index a72f5026d27..00000000000 --- a/sim/testsuite/sim/frv/ftlg.cgs +++ /dev/null @@ -1,109 +0,0 @@ -# frv testcase for ftlg $FCCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global ftlg -ftlg: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x1 0 - ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_fcc 0x2 0 - ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_fcc 0x4 0 - ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_fcc 0x8 0 - ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x9 0 - ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftlg fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftlt.cgs b/sim/testsuite/sim/frv/ftlt.cgs deleted file mode 100644 index c9343139d4a..00000000000 --- a/sim/testsuite/sim/frv/ftlt.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for ftlt $FCCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global ftlt -ftlt: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x1 0 - ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x2 0 - ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x3 0 - ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok4,lr - set_fcc 0x4 0 - ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_fcc 0x8 0 - ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x9 0 - ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0xa 0 - ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0xb 0 - ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftlt fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftne.cgs b/sim/testsuite/sim/frv/ftne.cgs deleted file mode 100644 index 03b9857eb99..00000000000 --- a/sim/testsuite/sim/frv/ftne.cgs +++ /dev/null @@ -1,113 +0,0 @@ -# frv testcase for ftne $FCCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global ftne -ftne: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_fcc 0x1 0 - ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_psr_et 1 - set_spr_addr ok2,lr - set_fcc 0x2 0 - ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_fcc 0x4 0 - ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_fcc 0x8 0 - ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftne fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftno.cgs b/sim/testsuite/sim/frv/ftno.cgs deleted file mode 100644 index bada522a6a8..00000000000 --- a/sim/testsuite/sim/frv/ftno.cgs +++ /dev/null @@ -1,54 +0,0 @@ -# frv testcase for ftno -# mach: all - - .include "testutils.inc" - - start - - .global ftnev -ftnev: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_mem_limmed 0x0038,0x2000,gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_fcc 0x0 0 - ftno ; should branch to tbr + (128 + 4)*16 - set_fcc 0x1 0 - ftno ; should branch to tbr + (128 + 4)*16 - set_fcc 0x2 0 - ftno ; should branch to tbr + (128 + 4)*16 - set_fcc 0x3 0 - ftno ; should branch to tbr + (128 + 4)*16 - set_fcc 0x4 0 - ftno ; should branch to tbr + (128 + 4)*16 - set_fcc 0x5 0 - ftno ; should branch to tbr + (128 + 4)*16 - set_fcc 0x6 0 - ftno ; should branch to tbr + (128 + 4)*16 - set_fcc 0x7 0 - ftno ; should branch to tbr + (128 + 4)*16 - set_fcc 0x8 0 - ftno ; should branch to tbr + (128 + 4)*16 - set_fcc 0x9 0 - ftno ; should branch to tbr + (128 + 4)*16 - set_fcc 0xa 0 - ftno ; should branch to tbr + (128 + 4)*16 - set_fcc 0xb 0 - ftno ; should branch to tbr + (128 + 4)*16 - set_fcc 0xc 0 - ftno ; should branch to tbr + (128 + 4)*16 - set_fcc 0xd 0 - ftno ; should branch to tbr + (128 + 4)*16 - set_fcc 0xe 0 - ftno ; should branch to tbr + (128 + 4)*16 - set_fcc 0xf 0 - ftno ; should branch to tbr + (128 + 4)*16 - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/fto.cgs b/sim/testsuite/sim/frv/fto.cgs deleted file mode 100644 index 82035f4bec0..00000000000 --- a/sim/testsuite/sim/frv/fto.cgs +++ /dev/null @@ -1,113 +0,0 @@ -# frv testcase for fto $FCCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global fto -fto: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_fcc 0x0 0 - fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_fcc 0x1 0 - fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_fcc 0x2 0 - fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_fcc 0x4 0 - fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_fcc 0x8 0 - fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - fto fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftra.cgs b/sim/testsuite/sim/frv/ftra.cgs deleted file mode 100644 index 7754f697640..00000000000 --- a/sim/testsuite/sim/frv/ftra.cgs +++ /dev/null @@ -1,115 +0,0 @@ -# frv testcase for ftra $GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global ftra -ftra: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_psr_et 1 - set_spr_addr ok0,lr - set_fcc 0x0 0 - ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_psr_et 1 - set_spr_addr ok1,lr - set_fcc 0x1 0 - ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_psr_et 1 - set_spr_addr ok2,lr - set_fcc 0x2 0 - ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_fcc 0x4 0 - ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_fcc 0x8 0 - ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass diff --git a/sim/testsuite/sim/frv/ftu.cgs b/sim/testsuite/sim/frv/ftu.cgs deleted file mode 100644 index 354423baa36..00000000000 --- a/sim/testsuite/sim/frv/ftu.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for ftu $FCCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global ftu -ftu: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_fcc 0x1 0 - ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_fcc 0x2 0 - ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_fcc 0x4 0 - ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_spr_addr bad,lr - set_fcc 0x6 0 - ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_fcc 0x8 0 - ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_spr_addr bad,lr - set_fcc 0xa 0 - ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_spr_addr bad,lr - set_fcc 0xc 0 - ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_spr_addr bad,lr - set_fcc 0xe 0 - ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftu fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftue.cgs b/sim/testsuite/sim/frv/ftue.cgs deleted file mode 100644 index 564bb30265a..00000000000 --- a/sim/testsuite/sim/frv/ftue.cgs +++ /dev/null @@ -1,109 +0,0 @@ -# frv testcase for ftue $FCCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global ftue -ftue: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_fcc 0x1 0 - ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_fcc 0x2 0 - ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_fcc 0x4 0 - ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_spr_addr bad,lr - set_fcc 0x6 0 - ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_fcc 0x8 0 - ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftue fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftug.cgs b/sim/testsuite/sim/frv/ftug.cgs deleted file mode 100644 index cc6a405a596..00000000000 --- a/sim/testsuite/sim/frv/ftug.cgs +++ /dev/null @@ -1,109 +0,0 @@ -# frv testcase for ftug $FCCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global ftug -ftug: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_fcc 0x1 0 - ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_psr_et 1 - set_spr_addr ok2,lr - set_fcc 0x2 0 - ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_fcc 0x4 0 - ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_fcc 0x8 0 - ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_spr_addr bad,lr - set_fcc 0xc 0 - ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftuge.cgs b/sim/testsuite/sim/frv/ftuge.cgs deleted file mode 100644 index 7c04eaf29a4..00000000000 --- a/sim/testsuite/sim/frv/ftuge.cgs +++ /dev/null @@ -1,113 +0,0 @@ -# frv testcase for ftuge $FCCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global ftuge -ftuge: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_fcc 0x1 0 - ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_psr_et 1 - set_spr_addr ok2,lr - set_fcc 0x2 0 - ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_fcc 0x4 0 - ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_fcc 0x8 0 - ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftuge fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftul.cgs b/sim/testsuite/sim/frv/ftul.cgs deleted file mode 100644 index b45ebb35bed..00000000000 --- a/sim/testsuite/sim/frv/ftul.cgs +++ /dev/null @@ -1,109 +0,0 @@ -# frv testcase for ftul $FCCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global ftul -ftul: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_fcc 0x1 0 - ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_fcc 0x2 0 - ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_fcc 0x4 0 - ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_fcc 0x8 0 - ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_spr_addr bad,lr - set_fcc 0xa 0 - ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftul fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/ftule.cgs b/sim/testsuite/sim/frv/ftule.cgs deleted file mode 100644 index 4a93260d3d6..00000000000 --- a/sim/testsuite/sim/frv/ftule.cgs +++ /dev/null @@ -1,113 +0,0 @@ -# frv testcase for ftule $FCCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global ftule -ftule: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_fcc 0x0 0 - ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_fcc 0x1 0 - ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_fcc 0x2 0 - ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok3,lr - set_fcc 0x3 0 - ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_fcc 0x4 0 - ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_fcc 0x5 0 - ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_fcc 0x6 0 - ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_fcc 0x7 0 - ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_fcc 0x8 0 - ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_fcc 0x9 0 - ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_fcc 0xa 0 - ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_fcc 0xb 0 - ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_fcc 0xc 0 - ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_fcc 0xd 0 - ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_fcc 0xe 0 - ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_fcc 0xf 0 - ftule fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/icei.cgs b/sim/testsuite/sim/frv/icei.cgs deleted file mode 100644 index aac925bf29f..00000000000 --- a/sim/testsuite/sim/frv/icei.cgs +++ /dev/null @@ -1,15 +0,0 @@ -# frv testcase for icei @(GRi,GRj),a -# mach: fr400 fr550 - - .include "testutils.inc" - - start - - .global icei -icei: - ; Can't really test this because of SCACHE implementation - set_gr_addr icei,gr10 - icei @(gr10,gr0),1 - icei @(gr10,gr0),1 - - pass diff --git a/sim/testsuite/sim/frv/ici.cgs b/sim/testsuite/sim/frv/ici.cgs deleted file mode 100644 index 8aeacae33a9..00000000000 --- a/sim/testsuite/sim/frv/ici.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# FRV testcase for ici @(GRi,GRj) -# mach: all - - .include "testutils.inc" - - start - - .global ici -ici: - set_gr_immed 1234,gr2 - set_spr_addr ok1,lr - bra testit - -ok1: - ; Change the first insn to set gr1 to 1235 - ; but don't invalidate the insn cache - ; should have no effect - set_gr_mem testit,gr10 - ori gr10,1,gr10 - set_mem_gr gr10,testit - set_gr_addr testit,gr10 - dcf @(gr10,gr0) ; flush data cache - set_spr_addr ok2,lr - bra testit - -ok2: ; Now invalidate the insn cache. The new insn should take effect - ici @(gr10,gr0) - set_gr_immed 1235,gr2 - set_spr_addr ok3,lr - bra testit - -ok3: - pass - -testit: - setlos 1234,gr1 - test_gr_gr gr1,gr2 - bralr - fail diff --git a/sim/testsuite/sim/frv/icpl.cgs b/sim/testsuite/sim/frv/icpl.cgs deleted file mode 100644 index b86ba352796..00000000000 --- a/sim/testsuite/sim/frv/icpl.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# FRV testcase for icpl GRi,GRj,lock -# mach: all - - .include "testutils.inc" - - start - - .global icpl - ; keep this at least 64 bytes away from doit2 - bra icpl -doit1: add gr11,gr12,gr11 - bralr - -icpl: - or_spr_immed 0x80000000,hsr0 ; insn cache: enable - and_spr_immed 0xbfffffff,hsr0 ; data cache: disable - set_gr_immed 0,gr11 - set_gr_immed 1,gr12 - set_gr_immed 2,gr13 - - set_gr_addr doit1,gr10 - icpl gr10,gr0,0 ; preload insns at doit1 - set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11 - - set_gr_addr doit2,gr10 - set_mem_immed 0x9600b00d,gr10 ; change to add gr11,gr13,gr11 - - set_spr_addr ok1,lr - bra doit1 -ok1: test_gr_immed 1,gr11 ; used preloaded add of 1 - - set_spr_addr ok2,lr - bra doit2 -ok2: test_gr_immed 3,gr11 ; used changed add of 2 - - pass - -doit2: add gr11,gr12,gr11 - bralr diff --git a/sim/testsuite/sim/frv/icul.cgs b/sim/testsuite/sim/frv/icul.cgs deleted file mode 100644 index b112f41f5ea..00000000000 --- a/sim/testsuite/sim/frv/icul.cgs +++ /dev/null @@ -1,53 +0,0 @@ -# FRV testcase for icul $GRi -# mach: all - - .include "testutils.inc" - - start - - .global icul -icul: - or_spr_immed 0xc8000000,hsr0 ; caches enabled -- copy-back mode - - ; preload and lock all the lines in set 0 of the insn cache - set_gr_immed 0x70000,gr10 - set_bctrlr_0_0 gr10 - lock_insn_cache gr10 - - inc_gr_immed 0x1000,gr10 - set_bctrlr_0_0 gr10 - lock_insn_cache gr10 - - inc_gr_immed 0x1000,gr10 - set_bctrlr_0_0 gr10 - lock_insn_cache gr10 - - inc_gr_immed 0x1000,gr10 - set_bctrlr_0_0 gr10 - lock_insn_cache gr10 - - ; execute the pre-loaded insn - set_gr_immed 0x70000,gr10 - calll @(gr10,gr0) ; should come right back - inc_gr_immed 0x1000,gr10 - calll @(gr10,gr0) ; should come right back - inc_gr_immed 0x1000,gr10 - calll @(gr10,gr0) ; should come right back - inc_gr_immed 0x1000,gr10 - calll @(gr10,gr0) ; should come right back - - ; Now execute another insn which would have gone into set 0. - inc_gr_immed 0x1000,gr10 - set_bctrlr_0_0 gr10 - set_spr_immed 128,lcr - calll @(gr10,gr0) ; should come right back - - ; Now unlock one of the lines and do it again - set_gr_immed 0x71000,gr10 - icul gr10 - calll @(gr10,gr0) ; should come right back - - inc_gr_immed 0x3000,gr10 - calll @(gr10,gr0) ; should come right back - - pass diff --git a/sim/testsuite/sim/frv/interrupts.exp b/sim/testsuite/sim/frv/interrupts.exp deleted file mode 100644 index e31533e1053..00000000000 --- a/sim/testsuite/sim/frv/interrupts.exp +++ /dev/null @@ -1,19 +0,0 @@ -# FRV simulator testsuite. - -if [istarget frv*-*] { - # load support procs (none yet) - # load_lib cgen.exp - # all machines - set all_machs "frv fr500 fr550 fr400" - set cpu_option -mcpu - - # The .cgs suffix is for "cgen .s". - foreach src [lsort [glob -nocomplain $srcdir/$subdir/interrupts/*.cgs]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/frv/interrupts/Ipipe-fr400.cgs b/sim/testsuite/sim/frv/interrupts/Ipipe-fr400.cgs deleted file mode 100644 index dad9f0e6882..00000000000 --- a/sim/testsuite/sim/frv/interrupts/Ipipe-fr400.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# frv testcase -# mach: fr400 - - .include "testutils.inc" - - start - - .global Ipipe -Ipipe: - ; Clear the packing bit of the insn at 'pack:'. We can't - ; simply use '.p' because the assembler will catch the error. - set_gr_mem pack,gr10 - and_gr_immed 0x7fffffff,gr10 - set_mem_gr gr10,pack - set_gr_addr pack,gr10 - flush_data_cache gr10 - - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 0x070,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 - set_spr_immed 128,lcr - set_spr_addr ok0,lr - set_psr_et 1 - -bundle: add.p gr1,gr1,gr1 -pack: add gr2,gr2,gr2 -bad: add gr3,gr3,gr3 - fail -ok0: - test_spr_immed 1,esfr1 - test_spr_bits 0x3f,0,0xb,esr0 - test_spr_addr bundle,epcr0 - - pass diff --git a/sim/testsuite/sim/frv/interrupts/Ipipe-fr500.cgs b/sim/testsuite/sim/frv/interrupts/Ipipe-fr500.cgs deleted file mode 100644 index b4dd770a56c..00000000000 --- a/sim/testsuite/sim/frv/interrupts/Ipipe-fr500.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# frv testcase -# mach: fr500 - - .include "testutils.inc" - - start - - .global Ipipe -Ipipe: - ; Clear the packing bit of the insn at 'pack:'. We can't - ; simply use '.p' because the assembler will catch the error. - set_gr_mem pack,gr10 - and_gr_immed 0x7fffffff,gr10 - set_mem_gr gr10,pack - set_gr_addr pack,gr10 - flush_data_cache gr10 - - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 0x070,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 - set_spr_immed 128,lcr - set_spr_addr ok0,lr - set_psr_et 1 - - add.p gr1,gr1,gr1 -pack: add gr2,gr2,gr2 -bad: add gr3,gr3,gr3 - fail -ok0: - test_spr_immed 1,esfr1 - test_spr_bits 0x3f,0,0xb,esr0 - test_spr_addr bad,epcr0 - - pass diff --git a/sim/testsuite/sim/frv/interrupts/badalign-fr550.cgs b/sim/testsuite/sim/frv/interrupts/badalign-fr550.cgs deleted file mode 100644 index 6c0369b3426..00000000000 --- a/sim/testsuite/sim/frv/interrupts/badalign-fr550.cgs +++ /dev/null @@ -1,42 +0,0 @@ -# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj) -# mach: fr550 - .include "testutils.inc" - - start - - .global align -align: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x100,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_psr_et 1 - set_gr_immed 0xdeadbeef,gr17 - set_gr_immed 0,gr15 - inc_gr_immed 2,sp ; out of alignment - - test_spr_bits 1,0,0,isr ; ISR.EMAM always clear (not used) - sti gr17,@(sp,0) ; no exception - sti gr17,@(sp,4) ; no exception - ldi @(sp,0),gr18 ; stored at unaligned address - test_gr_immed 0xdeadbeef,gr18 - ldi @(sp,0),gr19 ; no exception - test_gr_immed 0xdeadbeef,gr19 - - and_spr_immed 0xfffffffe,isr ; turn off ISR.EMAM - sti gr17,@(sp,0) ; misaligned -- no exception - test_gr_immed 0,gr15 - - set_gr_gr sp,gr20 - set_gr_immed 1,gr21 - set_gr_immed 0x10101010,gr10 - nop.p - ldu @(sp,gr21),gr10 ; misaligned read no exception - test_gr_immed 0,gr15 ; handler was not called - test_gr_immed 0xadbeefde,gr10 ; gr10 updated - test_gr_immed 1,gr21 ; gr21 not updated - inc_gr_immed 1,gr20 - test_gr_gr gr20,sp ; sp updated - - pass diff --git a/sim/testsuite/sim/frv/interrupts/badalign.cgs b/sim/testsuite/sim/frv/interrupts/badalign.cgs deleted file mode 100644 index b8660219da8..00000000000 --- a/sim/testsuite/sim/frv/interrupts/badalign.cgs +++ /dev/null @@ -1,73 +0,0 @@ -# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj) -# mach: fr500 frv - .include "testutils.inc" - - start - - .global align -align: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x100,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_spr_addr ok1,lr - set_psr_et 1 - set_gr_immed 0xdeadbeef,gr17 - set_gr_immed 0,gr15 - inc_gr_immed 2,sp ; out of alignment - - test_spr_bits 1,0,1,isr ; mem_address_not_aligned is masked - sti gr17,@(sp,0) ; no exception - ldi @(sp,-2),gr18 ; stored at aligned address - test_gr_immed 0xdeadbeef,gr18 - ldi @(sp,0),gr19 ; no exception - test_gr_immed 0xdeadbeef,gr19 - - and_spr_immed 0xfffffffe,isr ; turn off ISR.EMAM - set_gr_addr bad1,gr16 -bad1: sti gr17,@(sp,0) ; misaligned write in slot I1 - test_gr_immed 1,gr15 - - set_gr_addr bad3,gr16 - set_gr_gr sp,gr20 - set_gr_immed 1,gr21 - set_gr_immed 0x10101010,gr10 -bad2: nop.p -bad3: ldu @(sp,gr21),gr10 ; misaligned read in slot I2 - test_gr_immed 2,gr15 ; handler was called - test_gr_immed 0x10101010,gr10 ; gr10 not updated - test_gr_immed 1,gr21 ; gr21 not updated - inc_gr_immed 1,gr20 - test_gr_gr gr20,sp ; sp updated - - pass - -; exception handler -ok1: - cmpi gr15,0,icc0 - bne icc0,0,load - ; handle interrupt on store - test_spr_immed 0x100,esfr1 ; esr8 is active - test_spr_gr epcr8,gr16 - test_spr_bits 0x0001,0,0x1,esr8 ; esr8 is valid - test_spr_bits 0x003e,1,0xb,esr8 ; esr8.ec is set - test_spr_bits 0x0800,11,0x1,esr8 ; esr8.eav is set - test_spr_gr ear8,sp - test_spr_bits 0x01000,12,0x1,esr8 ; esr8.edv is set - test_spr_bits 0x1e000,13,0x3,esr8 ; esr8.edn is 3 - test_spr_gr edr3,gr17 ; edr3 is set - bra ret -load: - ; handle interrupt on load - test_spr_immed 0x200,esfr1 ; esr9 is active - test_spr_gr epcr9,gr16 - test_spr_bits 0x0001,0,0x1,esr9 ; esr9 is valid - test_spr_bits 0x003e,1,0xb,esr9 ; esr9.ec is set - test_spr_bits 0x0800,11,0x1,esr9 ; esr9.eav is set - test_spr_gr ear9,sp - test_spr_bits 0x1000,12,0x0,esr9 ; esr9.edv is not set -ret: - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/interrupts/compound-fr550.cgs b/sim/testsuite/sim/frv/interrupts/compound-fr550.cgs deleted file mode 100644 index 7cd2278280f..00000000000 --- a/sim/testsuite/sim/frv/interrupts/compound-fr550.cgs +++ /dev/null @@ -1,54 +0,0 @@ -# frv testcase to generate compound exception -# mach: fr550 - .include "testutils.inc" - - start - - .global align -align: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x200,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_spr_addr ok1,lr - or_spr_immed 0x04000000,fsr0 ; enabled div/0 fp_exception - set_psr_et 1 - - set_gr_immed 0,gr15 - set_fr_iimmed 0x7f7f,0xffff,fr0 - set_fr_iimmed 0x0000,0x0000,fr1 - - and_spr_immed 0xfffffffe,isr ; enable mem_address_not_aligned - set_gr_addr dividef,gr16 - set_gr_addr dividei,gr17 - set_gr_immed 0xdeadbeef,gr8 - inc_gr_immed 2,sp ; misalign -store: sti.p gr8,@(sp,0) ; misaligned - no exception -dividef:fdivs.p fr0,fr1,fr2 ; fp_exception -dividei:sdiv gr1,gr0,gr1 ; division exception - test_gr_immed 1,gr15 - - pass - -; exception handler -ok1: - ; check fp_exception - test_spr_immed 0x5,esfr1 ; esr2 and esr0 are active - test_spr_gr epcr2,gr16 - test_spr_bits 0x0001,0,0x1,esr2 ; esr2 is valid - test_spr_bits 0x003e,1,0xd,esr2 ; esr2.ec is set - test_spr_bits 0x0800,11,0x0,esr2 ; esr2.eav is clear - - ; check on fp_exception - test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear - test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set - test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is clear - - ; check interrupt on dividei - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/interrupts/compound.cgs b/sim/testsuite/sim/frv/interrupts/compound.cgs deleted file mode 100644 index 2fd928eeee5..00000000000 --- a/sim/testsuite/sim/frv/interrupts/compound.cgs +++ /dev/null @@ -1,66 +0,0 @@ -# frv testcase to generate compound exception -# mach: fr500 frv - .include "testutils.inc" - - start - - .global align -align: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x200,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_spr_addr ok1,lr - or_spr_immed 0x04000000,fsr0 ; enabled div/0 fp_exception - set_psr_et 1 - - set_gr_immed 0,gr15 - set_fr_iimmed 0x7f7f,0xffff,fr0 - set_fr_iimmed 0x0000,0x0000,fr1 - - and_spr_immed 0xfffffffe,isr ; enable mem_address_not_aligned - set_gr_addr store,gr16 - set_gr_addr dividei,gr17 - set_gr_immed 0xdeadbeef,gr8 - inc_gr_immed 2,sp ; misalign -store: sti.p gr8,@(sp,0) ; misaligned write -dividef:fdivs.p fr0,fr1,fr2 ; fp_exception -dividei:sdiv gr1,gr0,gr1 ; division exception - test_gr_immed 1,gr15 - - pass - -; exception handler -ok1: - ; check interrupt on store - test_spr_immed 0x102,esfr1 ; esr8 and esr1 are active - test_spr_gr epcr8,gr16 - test_spr_bits 0x0001,0,0x1,esr8 ; esr8 is valid - test_spr_bits 0x003e,1,0xb,esr8 ; esr8.ec is set - test_spr_bits 0x0800,11,0x1,esr8 ; esr8.eav is set - test_spr_gr ear8,sp - test_spr_bits 0x01000,12,0x1,esr8 ; esr8.edv is set - test_spr_bits 0x1e000,13,0x3,esr8 ; esr8.edn is 3 - test_spr_gr edr3,gr8 ; edr3 is set - - ; check on fp_exception - test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set - test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set - test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is clear - - test_spr_bits 0x80000000,31,0x0,fqst2 ; fq2.miv is set - test_spr_bits 0x18000,15,0x0,fqst2 ; fq2.sie is set - test_spr_bits 0x380,7,0x1,fqst2 ; fq2.ftt is set - test_spr_bits 0x7e,1,0x4,fqst2 ; fq2.cexc is set - test_spr_bits 0x1,0,0x1,fqst2 ; fq2.valid is set - test_spr_immed 0x05e40241,fqop2 ; fq2.opc - - ; check interrupt on dividei - test_spr_gr epcr1,gr17 - test_spr_bits 0x0001,0,0x1,esr1 ; esr1 is valid - test_spr_bits 0x003e,1,0x13,esr1 ; esr1.ec is set - - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/interrupts/data_store_error-fr550.cgs b/sim/testsuite/sim/frv/interrupts/data_store_error-fr550.cgs deleted file mode 100644 index 3924adc576f..00000000000 --- a/sim/testsuite/sim/frv/interrupts/data_store_error-fr550.cgs +++ /dev/null @@ -1,53 +0,0 @@ -# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj) -# mach: fr550 -# sim(fr550): --memory-region 0xfeff0600,0x8000 --memory-region 0xfe800000,0x7f0010 - .include "testutils.inc" - - start - - .global dsr -dsr: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x140,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_psr_et 1 - - set_spr_addr ok0,lr - set_gr_immed 0,gr16 - - set_gr_immed 0xdeadbeef,gr15 - set_gr_addr 0xfeff0600,gr17 -bad1: sti gr15,@(gr17,0) ; no interrupt - test_gr_immed 0,gr16 - - set_gr_immed 0xbeefdead,gr15 - set_gr_addr 0xfeff7ffc,gr17 -bad2: sti gr15,@(gr17,0) ; no interrupt - test_gr_immed 0,gr16 - - set_gr_immed 0xbeefbeef,gr15 - set_gr_addr 0xfe800000,gr17 -bad3: sti gr15,@(gr17,0) ; cause interrupt - test_gr_immed 1,gr16 - - set_gr_immed 0xdeaddead,gr15 - set_gr_addr 0xfefefffc,gr17 -bad4: sti gr15,@(gr17,0) ; cause interrupt - test_gr_immed 2,gr16 - - sti gr0,@(sp,0) ; no interrupt - test_gr_immed 2,gr16 - - pass -ok0: - ; check interrupts - test_spr_immed 0x4000,esfr1 ; esr14 is active - test_spr_bits 0x0001,0,0x1,esr14 ; esr14 is valid - test_spr_bits 0x003e,1,0x0,esr14 ; esr14.ec is set - test_spr_bits 0x0800,11,0x0,esr14 ; esr14.eav is not set - - addi gr16,1,gr16 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/interrupts/data_store_error.cgs b/sim/testsuite/sim/frv/interrupts/data_store_error.cgs deleted file mode 100644 index b967d0a0525..00000000000 --- a/sim/testsuite/sim/frv/interrupts/data_store_error.cgs +++ /dev/null @@ -1,53 +0,0 @@ -# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj) -# mach: fr500 -# sim(fr500): --memory-region 0xfeff0600,0x8000 --memory-region 0xfe800000,0x7f0010 - .include "testutils.inc" - - start - - .global dsr -dsr: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x140,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_psr_et 1 - - set_spr_addr ok0,lr - set_gr_immed 0,gr16 - - set_gr_immed 0xdeadbeef,gr15 - set_gr_addr 0xfeff0600,gr17 -bad1: sti gr15,@(gr17,0) ; cause interrupt - test_gr_immed 1,gr16 - - set_gr_immed 0xbeefdead,gr15 - set_gr_addr 0xfeff7ffc,gr17 -bad2: sti gr15,@(gr17,0) ; cause interrupt - test_gr_immed 2,gr16 - - set_gr_immed 0xbeefbeef,gr15 - set_gr_addr 0xfe800000,gr17 -bad3: sti gr15,@(gr17,0) ; cause interrupt - test_gr_immed 3,gr16 - - set_gr_immed 0xdeaddead,gr15 - set_gr_addr 0xfefefffc,gr17 -bad4: sti gr15,@(gr17,0) ; cause interrupt - test_gr_immed 4,gr16 - - sti gr0,@(sp,0) ; no interrupt - test_gr_immed 4,gr16 - - pass -ok0: - ; check interrupts - test_spr_immed 0x4000,esfr1 ; esr14 is active - test_spr_bits 0x0001,0,0x1,esr14 ; esr14 is valid - test_spr_bits 0x003e,1,0x0,esr14 ; esr14.ec is set - test_spr_bits 0x0800,11,0x0,esr14 ; esr14.eav is not set - - addi gr16,1,gr16 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs b/sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs deleted file mode 100644 index 0bb98d8eb43..00000000000 --- a/sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs +++ /dev/null @@ -1,185 +0,0 @@ -# frv testcase to generate fp_exception -# mach: fr550 - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global align -align: - ; clear the packing bit if the insn at 'pack:'. We can't simply use - ; '.p' because the assembler will catch the error. - set_gr_mem pack,gr10 - and_gr_immed 0x7fffffff,gr10 - set_mem_gr gr10,pack - set_gr_addr pack,gr10 - flush_data_cache gr10 - - ; Make the the source register number odd at badst. We can't simply - ; code an odd register number because the assembler will catch the - ; error. - set_gr_mem badst,gr10 - or_gr_immed 0x02000000,gr10 - set_mem_gr gr10,badst - set_gr_addr badst,gr10 - flush_data_cache gr10 - - ; Make the the dest register number odd at badld. We can't simply - ; code an odd register number because the assembler will catch the - ; error. - set_gr_mem badld,gr10 - or_gr_immed 0x02000000,gr10 - set_mem_gr gr10,badld - set_gr_addr badld,gr10 - flush_data_cache gr10 - - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x070,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - inc_gr_immed 0x060,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_spr_addr ok1,lr - set_psr_et 1 - inc_gr_immed -4,sp ; for alignment - - set_gr_immed 0,gr20 ; PC increment - set_gr_immed 0,gr15 - - set_spr_addr ok3,lr - set_gr_immed 4,gr20 ; PC increment -badst: stdfi fr0,@(sp,0) ; misaligned reg -- slot I0 - test_gr_immed 1,gr15 - - set_spr_addr ok4,lr - set_gr_immed 8,gr20 ; PC increment - nop.p -badld: lddfi @(sp,0),fr8 ; misaligned reg -- slot I1 - test_gr_immed 2,gr15 - - set_spr_addr ok5,lr - set_gr_immed 20,gr20 ; PC increment - fnegs.p fr9,fr9 - fnegs.p fr9,fr10 - fnegs.p fr9,fr11 -pack: fnegs fr10,fr12 - fnegs fr10,fr13 ; packing violation - test_gr_immed 3,gr15 - - set_spr_addr ok1,lr - set_gr_immed 4,gr20 ; PC increment -bad: fmadds fr16,fr4,fr1 ; unimplemented - test_gr_immed 4,gr15 - - and_spr_immed 0xfbffffff,fsr0 ; disable div/0 fp_exception - set_fr_iimmed 0x7f7f,0xffff,fr0 - set_fr_iimmed 0x0000,0x0000,fr1 - fdivs fr0,fr1,fr2 ; div/0 -- no exception - test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is never set - test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set - test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear - - set_spr_addr ok2,lr - set_gr_immed 0,gr20 ; PC increment - or_spr_immed 0x04000000,fsr0 ; enable div/0 fp_exception - set_fr_iimmed 0xdead,0xbeef,fr2 -div0: fdivs fr0,fr1,fr2 ; fp_exception - div/0 - test_fr_iimmed 0xdeadbeef,fr2 ; fr2 not updated - test_gr_immed 5,gr15 - - and_spr_immed 0xfdffffff,fsr0 ; disable inexact fp_exception - fsqrts fr32,fr2 ; inexact -- no exception - test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is never set - test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is set - test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear - - set_fr_fr fr2,fr3 ; sqrt 2 - set_fr_iimmed 0xdead,0xbeef,fr2 - set_spr_addr ok6,lr - or_spr_immed 0x02000000,fsr0 ; enable inexact fp_exception -inxt1: fsqrts fr32,fr2 ; fp_exception - inexact - test_gr_immed 6,gr15 ; handler called - test_fr_fr fr2,fr3 ; fr2 updated - - set_fr_iimmed 0xdead,0xbeef,fr2 - set_spr_addr ok7,lr -inxt2: fsqrts fr32,fr2 ; fp_exception - inexact again - test_gr_immed 7,gr15 ; handler called - test_fr_fr fr2,fr3 ; fr2 updated - - pass - -; exception handler 1 -- illegal_instruction: bad insn -ok1: - test_spr_immed 1,esfr1 ; esr0 active - test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set - test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set - bra ret - -; exception handler 2 - fp_exception: divide by 0 -ok2: - test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear - test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set - test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set - - test_spr_immed 4,esfr1 ; esr2 active - test_spr_bits 0x3e,1,0xd,esr2 ; esr2.ec is set - test_spr_bits 0x1,0,0x1,esr2 ; esr2.valid is set - test_spr_addr div0,epcr2 ; epcr2 is set - bra ret - -; exception handler 3 - illegal_instruction: register exception -ok3: - test_spr_immed 1,esfr1 ; esr0 active - test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set - test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set - bra ret - -; exception handler 4 - illegal_instruction: register exception -ok4: - test_spr_immed 1,esfr1 ; esr0 active - test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set - test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set - bra ret - -; exception handler 5 - illegal_instruction: sequence violation -ok5: - test_spr_immed 1,esfr1 ; esr0 active - test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set - test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set - bra ret - -; exception handler 6 - fp_exception: inexact -ok6: - test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear - test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set - test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set - - test_spr_immed 4,esfr1 ; esr2 active - test_spr_bits 0x3e,1,0xd,esr2 ; esr2.ec is set - test_spr_bits 0x1,0,0x1,esr2 ; esr2.valid is set - test_spr_addr inxt1,epcr2 ; epcr2 is set - bra ret - -; exception handler 7 - fp_exception: inexact again -ok7: - test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear - test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set - test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set - - test_spr_immed 4,esfr1 ; esr2 active - test_spr_bits 0x3e,1,0xd,esr2 ; esr2.ec is set - test_spr_bits 0x1,0,0x1,esr2 ; esr2.valid is set - test_spr_addr inxt2,epcr2 ; epcr2 is set - bra ret - -ret: - inc_gr_immed 1,gr15 - movsg pcsr,gr60 - add gr60,gr20,gr60 - movgs gr60,pcsr - rett 0 - fail - diff --git a/sim/testsuite/sim/frv/interrupts/fp_exception.cgs b/sim/testsuite/sim/frv/interrupts/fp_exception.cgs deleted file mode 100644 index ad5f7e40880..00000000000 --- a/sim/testsuite/sim/frv/interrupts/fp_exception.cgs +++ /dev/null @@ -1,209 +0,0 @@ -# frv testcase to generate fp_exception -# mach: fr500 - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global align -align: - ; clear the packing bit if the insn at 'pack:'. We can't simply use - ; '.p' because the assembler will catch the error. - set_gr_mem pack,gr10 - and_gr_immed 0x7fffffff,gr10 - set_mem_gr gr10,pack - set_gr_addr pack,gr10 - flush_data_cache gr10 - - ; Make the the source register number odd at badst. We can't simply - ; code an odd register number because the assembler will catch the - ; error. - set_gr_mem badst,gr10 - or_gr_immed 0x02000000,gr10 - set_mem_gr gr10,badst - set_gr_addr badst,gr10 - flush_data_cache gr10 - - ; Make the the dest register number odd at ld. We can't simply - ; code an odd register number because the assembler will catch the - ; error. - set_gr_mem badld,gr10 - or_gr_immed 0x02000000,gr10 - set_mem_gr gr10,badld - set_gr_addr badld,gr10 - flush_data_cache gr10 - - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x070,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - inc_gr_immed 0x060,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_spr_addr ok1,lr - set_psr_et 1 - inc_gr_immed -4,sp ; for alignment - - set_gr_immed 0,gr20 ; PC increment - set_gr_immed 0,gr15 - - set_spr_addr ok3,lr -badst: stdfi fr0,@(sp,0) ; misaligned reg -- slot I0 - test_gr_immed 1,gr15 - - set_spr_addr ok4,lr - nop.p -badld: lddfi @(sp,0),fr8 ; misaligned reg -- slot I1 - test_gr_immed 2,gr15 - - set_spr_addr ok5,lr - fnegs.p fr9,fr9 -pack: fnegs fr10,fr10 - fnegs fr10,fr11 ; packing violation - test_gr_immed 3,gr15 - - set_spr_addr ok1,lr - set_gr_immed 4,gr20 ; PC increment -bad: fmadds fr16,fr4,fr1 ; unimplemented - test_gr_immed 4,gr15 - - and_spr_immed 0xfbffffff,fsr0 ; disable div/0 fp_exception - set_fr_iimmed 0x7f7f,0xffff,fr0 - set_fr_iimmed 0x0000,0x0000,fr1 - fdivs fr0,fr1,fr2 ; div/0 -- no exception - test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is still set - test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set - test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear - and_spr_immed 0xffefffff,fsr0 ; Clear fsr0.qne - - set_spr_addr ok2,lr - set_gr_immed 0,gr20 ; PC increment - or_spr_immed 0x04000000,fsr0 ; enable div/0 fp_exception - set_fr_iimmed 0xdead,0xbeef,fr2 - fdivs fr0,fr1,fr2 ; fp_exception - div/0 - test_fr_iimmed 0xdeadbeef,fr2 ; fr2 not updated - test_gr_immed 5,gr15 - - and_spr_immed 0xfdffffff,fsr0 ; disable inexact fp_exception - fsqrts fr32,fr2 ; inexact -- no exception - test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is still set - test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is set - test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear - - set_fr_fr fr2,fr3 ; sqrt 2 - set_fr_iimmed 0xdead,0xbeef,fr2 - set_spr_addr ok6,lr - or_spr_immed 0x02000000,fsr0 ; enable inexact fp_exception - fsqrts fr32,fr2 ; fp_exception - inexact - test_gr_immed 6,gr15 ; handler called - test_fr_fr fr2,fr3 ; fr2 updated - - set_fr_iimmed 0xdead,0xbeef,fr2 - set_spr_addr ok7,lr - fsqrts fr32,fr2 ; fp_exception - inexact again - test_gr_immed 7,gr15 ; handler called - test_fr_fr fr2,fr3 ; fr2 updated - - pass - -; exception handler 1 -- bad insn -ok1: - test_spr_immed 1,esfr1 ; esr0 active - test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set - test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set - test_spr_addr bad,epcr0 - bra ret - -; exception handler 2 - fp_exception: divide by 0 -ok2: - test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set - test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set - test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set - - test_spr_bits 0x80000000,31,0x0,fqst2 ; fq2.miv is set - test_spr_bits 0x18000,15,0x0,fqst2 ; fq2.sie is set - test_spr_bits 0x380,7,0x1,fqst2 ; fq2.ftt is set - test_spr_bits 0x7e,1,0x4,fqst2 ; fq2.cexc is set - test_spr_bits 0x1,0,0x1,fqst2 ; fq2.valid is set - test_spr_immed 0x85e40241,fqop2 ; fq2.opc - bra ret - -; exception handler 3 - fp_exception: register exception -ok3: - test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set - test_spr_bits 0xe0000,17,0x6,fsr0 ; fsr0.ftt is set - test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is clear - - test_spr_bits 0x80000000,31,0x0,fqst2 ; fq2.miv is set - test_spr_bits 0x18000,15,0x0,fqst2 ; fq2.sie is set - test_spr_bits 0x380,7,0x6,fqst2 ; fq2.ftt is set - test_spr_bits 0x7e,1,0x0,fqst2 ; fq2.cexc is set - test_spr_bits 0x1,0,0x1,fqst2 ; fq2.valid is set - test_spr_immed 0x83581000,fqop2 ; fq2.opc - bra ret - -; exception handler 4 - fp_exception: another register exception -ok4: - test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set - test_spr_bits 0xe0000,17,0x6,fsr0 ; fsr0.ftt is set - test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is still clear - - test_spr_bits 0x80000000,31,0x0,fqst3 ; fq3.miv is set - test_spr_bits 0x18000,15,0x0,fqst3 ; fq3.sie is set - test_spr_bits 0x380,7,0x6,fqst3 ; fq3.ftt is set - test_spr_bits 0x7e,1,0x0,fqst3 ; fq3.cexc is set - test_spr_bits 0x1,0,0x1,fqst3 ; fq3.valid is set - test_spr_immed 0x92ec1000,fqop3 ; fq3.opc - bra ret - -; exception handler 5 - fp_exception: sequence violation -ok5: - test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set - test_spr_bits 0xe0000,17,0x4,fsr0 ; fsr0.ftt is set - test_spr_bits 0xfc00,10,0x0,fsr0 ; fsr0.aexc is still clear - - test_spr_bits 0x80000000,31,0x0,fqst3 ; fq3.miv is set - test_spr_bits 0x18000,15,0x0,fqst3 ; fq3.sie is set - test_spr_bits 0x380,7,0x4,fqst3 ; fq3.ftt is set - test_spr_bits 0x7e,1,0x0,fqst3 ; fq3.cexc is set - test_spr_bits 0x1,0,0x1,fqst3 ; fq3.valid is set - test_spr_immed 0x97e400ca,fqop3 ; fq3.opc - bra ret - -; exception handler 6 - fp_exception: inexact -ok6: - test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set - test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set - test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set - - test_spr_bits 0x80000000,31,0x0,fqst0 ; fq0.miv is set - test_spr_bits 0x18000,15,0x0,fqst0 ; fq0.sie is set - test_spr_bits 0x380,7,0x1,fqst0 ; fq0.ftt is set - test_spr_bits 0x7e,1,0x2,fqst0 ; fq0.cexc is set - test_spr_bits 0x1,0,0x1,fqst0 ; fq0.valid is set - test_spr_immed 0x85e40160,fqop0 ; fq0.opc - bra ret - -; exception handler 7 - fp_exception: inexact again -ok7: - test_spr_bits 0x100000,20,0x1,fsr0 ; fsr0.qne is set - test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set - test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set - - test_spr_bits 0x80000000,31,0x0,fqst1 ; fq1.miv is set - test_spr_bits 0x18000,15,0x0,fqst1 ; fq1.sie is set - test_spr_bits 0x380,7,0x1,fqst1 ; fq1.ftt is set - test_spr_bits 0x7e,1,0x2,fqst1 ; fq1.cexc is set - test_spr_bits 0x1,0,0x1,fqst1 ; fq1.valid is set - test_spr_immed 0x85e40160,fqop1 ; fq1.opc - bra ret - -ret: - inc_gr_immed 1,gr15 - movsg pcsr,gr60 - add gr60,gr20,gr60 - movgs gr60,pcsr - rett 0 - fail - diff --git a/sim/testsuite/sim/frv/interrupts/illinsn.cgs b/sim/testsuite/sim/frv/interrupts/illinsn.cgs deleted file mode 100644 index fc44a8fc99e..00000000000 --- a/sim/testsuite/sim/frv/interrupts/illinsn.cgs +++ /dev/null @@ -1,38 +0,0 @@ -# FRV testcase -# mach: fr500 fr550 fr400 - - .include "testutils.inc" - - start - - .global tra -tra: - and_spr_immed 0x3fffffff,hsr0 ; no caches enabled - - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 0x070,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 - inc_gr_immed 0x790,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 - set_spr_immed 128,lcr - set_psr_et 1 - set_spr_addr ok0,lr - - set_gr_addr ill1,gr7 - set_mem_immed 0x81f80000,gr7 ; unknown opcode: 7E -ill1: tira gr0,0 ; should be overridden -ill2: nop ; also illegal, but prev has priority -bad0: fail - - ; check interrupt -ok0: test_spr_addr ill1,pcsr - test_spr_immed 1,esfr1 ; esr0 active - test_spr_bits 0x3f,0,0xb,esr0 - movsg psr,gr28 - srli gr28,28,gr28 - subicc gr28,0x3,gr0,icc3 ; is fr550? - beq icc3,0,no_epcr - test_spr_addr ill1,epcr0 -no_epcr: - pass diff --git a/sim/testsuite/sim/frv/interrupts/insn_access_error-fr550.cgs b/sim/testsuite/sim/frv/interrupts/insn_access_error-fr550.cgs deleted file mode 100644 index 6c4929950ba..00000000000 --- a/sim/testsuite/sim/frv/interrupts/insn_access_error-fr550.cgs +++ /dev/null @@ -1,44 +0,0 @@ -# frv testcase to generate insn_access_error interrupt -# mach: fr550 -# sim: --memory-region 0xfe800000,0x7f0500 --memory-region 0xfeff0540,0xfb00 - .include "testutils.inc" - - start - - .global dsr -dsr: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x020,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_psr_et 1 - - set_spr_addr handler,lr - set_gr_immed 0,gr16 - - set_gr_addr ok0,gr8 - set_gr_addr 0xfe800000,gr17 - jmpl @(gr17,gr0) ; cause interrupt -ok0: - test_gr_immed 1,gr16 - - set_gr_addr ok1,gr8 - set_gr_addr 0xfefffffc,gr17 - jmpl @(gr17,gr0) ; cause interrupt -ok1: - test_gr_immed 2,gr16 - - pass -handler: - ; check interrupts - test_spr_immed 0x1,esfr1 ; esr0 is active -; test_spr_gr epcr0,gr17 ; epcr0 is not used - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x2,esr0 ; esr0.ec is set - test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is not set - - addi gr16,1,gr16 - movgs gr8,pcsr - rett 0 - fail diff --git a/sim/testsuite/sim/frv/interrupts/insn_access_error.cgs b/sim/testsuite/sim/frv/interrupts/insn_access_error.cgs deleted file mode 100644 index 11a9eaf5355..00000000000 --- a/sim/testsuite/sim/frv/interrupts/insn_access_error.cgs +++ /dev/null @@ -1,56 +0,0 @@ -# frv testcase to generate insn_access_error interrupt -# mach: fr500 fr400 -# sim: --memory-region 0xfeff0600,0x8000 --memory-region 0xfe800000,0x7f0040 - .include "testutils.inc" - - start - - .global dsr -dsr: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x020,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_psr_et 1 - - set_spr_addr handler,lr - set_gr_immed 0,gr16 - - set_gr_addr ok0,gr8 - set_gr_addr 0xfeff0600,gr17 - jmpl @(gr17,gr0) ; cause interrupt -ok0: - test_gr_immed 1,gr16 - - set_gr_addr ok1,gr8 - set_gr_addr 0xfeff7ffc,gr17 - jmpl @(gr17,gr0) ; cause interrupt -ok1: - test_gr_immed 2,gr16 - - set_gr_addr ok2,gr8 - set_gr_addr 0xfe800000,gr17 - jmpl @(gr17,gr0) ; cause interrupt -ok2: - test_gr_immed 3,gr16 - - set_gr_addr ok3,gr8 - set_gr_addr 0xfefefffc,gr17 - jmpl @(gr17,gr0) ; cause interrupt -ok3: - test_gr_immed 4,gr16 - - pass -handler: - ; check interrupts - test_spr_immed 0x1,esfr1 ; esr0 is active - test_spr_gr epcr0,gr17 - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x2,esr0 ; esr0.ec is set - test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is not set - - addi gr16,1,gr16 - movgs gr8,pcsr - rett 0 - fail diff --git a/sim/testsuite/sim/frv/interrupts/mp_exception.cgs b/sim/testsuite/sim/frv/interrupts/mp_exception.cgs deleted file mode 100644 index 3203acc85ce..00000000000 --- a/sim/testsuite/sim/frv/interrupts/mp_exception.cgs +++ /dev/null @@ -1,289 +0,0 @@ -# frv testcase for mp_exception -# mach: fr500 fr550 frv -# xerror: - -# This program no longer assembles because the assembler -# now detects the unaligned registers. For this reason -# this test is now marked as "xerror" and prints the -# expected message "fail" - - .include "testutils.inc" - - start - - .global mp_exception -mpx: -.if 1 - fail -.else - or_spr_immed 2,msr0 ; Set msr0.ovf - or_spr_immed 2,msr1 ; Set msr1.ovf - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mcmpsh fr10,fr11,fcc1 ; mp_exception: cr-not-aligned - test_spr_bits 0x7000,12,3,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf is set - - or_spr_immed 2,msr0 ; Set msr0.ovf - or_spr_immed 2,msr1 ; Set msr1.ovf - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mcmpsh.p fr10,fr11,fcc0 ; no exception - mcmpsh fr10,fr11,fcc2 ; no exception - test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - mmulhs.p fr10,fr11,acc3 ; no exception - mmulhs fr10,fr11,acc1 ; mp_exception: acc-not-aligned - test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - or_spr_immed 2,msr0 ; Set msr0.ovf - or_spr_immed 2,msr1 ; Set msr1.ovf - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mmulhu fr10,fr11,acc0 ; no exception - test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - mmulxhs.p fr10,fr11,acc3 ; no exception - mmulxhs fr10,fr11,acc1 ; mp_exception: acc-not-aligned - test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - or_spr_immed 2,msr0 ; Set msr0.ovf - or_spr_immed 2,msr1 ; Set msr1.ovf - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mmulxhu fr10,fr11,acc0 ; no exception - test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - mmachs.p fr10,fr11,acc3 ; no exception - mmachs fr10,fr11,acc1 ; mp_exception: acc-not-aligned - test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - or_spr_immed 2,msr0 ; Set msr0.ovf - or_spr_immed 2,msr1 ; Set msr1.ovf - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mmachu fr10,fr11,acc0 ; no exception - test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - mqaddhss.p fr10,fr12,fr17 ; mp_exception: register-not-aligned - mqaddhss fr10,fr12,fr14 ; no exception - test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - mqaddhss.p fr10,fr12,fr14 ; no exception - mqaddhss fr10,fr13,fr16 ; mp_exception: register-not-aligned - test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - mqaddhss.p fr19,fr12,fr14 ; mp_exception: register-not-aligned - mqaddhss fr10,fr13,fr16 ; mp_exception: register-not-aligned - test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - or_spr_immed 2,msr0 ; Set msr0.ovf - or_spr_immed 2,msr1 ; Set msr1.ovf - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mqaddhss fr10,fr12,fr14 ; no exception - test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - mqmulhs.p fr10,fr11,acc3 ; no exception - mqmulhs fr10,fr11,acc2 ; mp_exception: acc-not-aligned - test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - or_spr_immed 2,msr0 ; Set msr0.ovf - or_spr_immed 2,msr1 ; Set msr1.ovf - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mqmulhu fr10,fr11,acc0 ; mp_exception: register_not_aligned - test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set - - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mqmulhu fr10,fr12,acc0 ; no exception - test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - mqmulxhs.p fr10,fr11,acc3 ; no exception - mqmulxhs fr10,fr11,acc2 ; mp_exception: acc-not-aligned - test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - or_spr_immed 2,msr0 ; Set msr0.ovf - or_spr_immed 2,msr1 ; Set msr1.ovf - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mqmulxhu fr10,fr11,acc0 ; mp_exception: register-not-aligned - test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set - - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mqmulxhu fr10,fr12,acc0 ; no exception - test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,1,msr0 ; msr0.ovf is still set - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - mqmachs.p fr10,fr12,acc3 ; no exception - mqmachs fr10,fr12,acc2 ; mp_exception: acc-not-aligned - test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mqmachu.p fr19,fr12,acc0 ; mp_exception: register-not-aligned - mqmachu fr10,fr12,acc0 ; no exception - test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mqmachu.p fr10,fr12,acc0 ; no exception - mqmachu fr19,fr12,acc0 ; mp_exception: register-not-aligned - test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mqmachu.p fr19,fr12,acc0 ; mp_exception: register-not-aligned - mqmachu fr19,fr12,acc0 ; mp_exception: register-not-aligned - test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - or_spr_immed 2,msr0 ; Set msr0.ovf - or_spr_immed 2,msr1 ; Set msr1.ovf - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mqmachu fr10,fr12,acc0 ; no exception - test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - mqcpxrs.p fr10,fr12,acc0 ; no exception - mqcpxrs fr10,fr12,acc1 ; mp_exception: acc-not-aligned - test_spr_bits 0x7000,12,2,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mqcpxru.p fr19,fr12,acc0 ; mp_exception: register-not-aligned - mqcpxru fr10,fr12,acc0 ; no exception - test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mqcpxru.p fr10,fr12,acc0 ; no exception - mqcpxru fr19,fr12,acc0 ; mp_exception: register-not-aligned - test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mqcpxru.p fr19,fr12,acc0 ; mp_exception: register-not-aligned - mqcpxru fr19,fr12,acc0 ; mp_exception: register-not-aligned - test_spr_bits 0x7000,12,6,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - or_spr_immed 2,msr0 ; Set msr0.ovf - or_spr_immed 2,msr1 ; Set msr1.ovf - and_spr_immed 0xffff8fff,msr0 ; Clear msr0.mtt - mqcpxru fr10,fr12,acc0 ; no exception - test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,1,msr1 ; msr1.ovf still set - - pass -.endif diff --git a/sim/testsuite/sim/frv/interrupts/privileged_instruction.cgs b/sim/testsuite/sim/frv/interrupts/privileged_instruction.cgs deleted file mode 100644 index 9996236b333..00000000000 --- a/sim/testsuite/sim/frv/interrupts/privileged_instruction.cgs +++ /dev/null @@ -1,54 +0,0 @@ -# frv testcase to generate privileged_instruction interrupt -# mach: frv - - .include "testutils.inc" - - start - - .global dsr -dsr: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x060,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_psr_et 1 - and_spr_immed 0xfffffffb,psr ; clear psr.s - - set_spr_addr handler,lr - set_gr_immed 0,gr16 - - set_gr_addr bad1,gr17 -bad1: rett 0 ; cause interrupt - test_gr_immed 1,gr16 - set_gr_addr bad2,gr17 -bad2: rei 0 ; cause interrupt - test_gr_immed 2,gr16 - set_gr_addr bad3,gr17 -bad3: witlb gr0,@(gr0,gr0) ; cause interrupt - test_gr_immed 3,gr16 - set_gr_addr bad4,gr17 -bad4: wdtlb gr0,@(gr0,gr0) ; cause interrupt - test_gr_immed 4,gr16 - set_gr_addr bad5,gr17 -bad5: itlbi @(gr0,gr0) ; cause interrupt - test_gr_immed 5,gr16 - set_gr_addr bad6,gr17 -bad6: dtlbi @(gr0,gr0) ; cause interrupt - test_gr_immed 6,gr16 - - pass -handler: - ; check interrupts - test_spr_immed 0x1,esfr1 ; esr0 is active - test_spr_gr epcr0,gr17 - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x4,esr0 ; esr0.ec is set - test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is not set - - addi gr16,1,gr16 - movsg pcsr,gr8 - addi gr8,4,gr8 - movgs gr8,pcsr - rett 0 - fail diff --git a/sim/testsuite/sim/frv/interrupts/regalign.cgs b/sim/testsuite/sim/frv/interrupts/regalign.cgs deleted file mode 100644 index afa09b5f22e..00000000000 --- a/sim/testsuite/sim/frv/interrupts/regalign.cgs +++ /dev/null @@ -1,130 +0,0 @@ -# frv testcase to generate interrupts for bad register alignment -# mach: frv - .include "testutils.inc" - - start - - .global align -align: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x080,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - inc_gr_immed 0x050,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_spr_addr ok1,lr - set_psr_et 1 - - ; Make the the register number odd at bad[1-4], bad9 and bada. - ; We can't simply code an odd register number because the assembler - ; will catch the error. - set_gr_mem bad1,gr10 - or_gr_immed 0x02000000,gr10 - set_mem_gr gr10,bad1 - set_gr_addr bad1,gr10 - flush_data_cache gr10 - set_gr_mem bad2,gr10 - or_gr_immed 0x02000000,gr10 - set_mem_gr gr10,bad2 - set_gr_addr bad2,gr10 - flush_data_cache gr10 - set_gr_mem bad3,gr10 - or_gr_immed 0x02000000,gr10 - set_mem_gr gr10,bad3 - set_gr_addr bad3,gr10 - flush_data_cache gr10 - set_gr_mem bad4,gr10 - or_gr_immed 0x02000000,gr10 - set_mem_gr gr10,bad4 - set_gr_addr bad4,gr10 - flush_data_cache gr10 - set_gr_mem bad9,gr10 - or_gr_immed 0x02000000,gr10 - set_mem_gr gr10,bad9 - set_gr_addr bad9,gr10 - flush_data_cache gr10 - set_gr_mem bada,gr10 - or_gr_immed 0x02000000,gr10 - set_mem_gr gr10,bada - set_gr_addr bada,gr10 - flush_data_cache gr10 - - set_gr_immed 4,gr20 ; PC increment - set_gr_immed 0,gr15 - inc_gr_immed -12,sp ; for memory alignment - - set_gr_addr bad1,gr17 -bad1: stdi gr0,@(sp,0) ; misaligned reg - test_gr_immed 1,gr15 - - set_gr_addr bad2,gr17 -bad2: lddi @(sp,0),gr8 ; misaligned reg - test_gr_immed 2,gr15 - - set_gr_addr bad3,gr17 -bad3: stdc cpr0,@(sp,gr0) ; misaligned reg - test_gr_immed 3,gr15 - - set_gr_addr bad4,gr17 -bad4: lddc @(sp,gr0),cpr8 ; misaligned reg - test_gr_immed 4,gr15 - - set_gr_addr bad5,gr17 -bad5: stqi gr2,@(sp,0) ; misaligned reg - test_gr_immed 5,gr15 - - set_gr_addr bad6,gr17 -bad6: ldqi @(sp,0),gr10 ; misaligned reg - test_gr_immed 6,gr15 - - set_gr_addr bad7,gr17 -bad7: stqc cpr2,@(sp,gr0) ; misaligned reg - test_gr_immed 7,gr15 - - set_gr_addr bad8,gr17 -bad8: ldqc @(sp,gr0),cpr10 ; misaligned reg - test_gr_immed 8,gr15 - - set_gr_immed 0,gr20 ; PC increment - set_gr_addr bad9,gr17 -bad9: stdfi fr0,@(sp,0) ; misaligned reg - test_gr_immed 9,gr15 - - set_gr_addr bada,gr17 -bada: lddfi @(sp,0),fr8 ; misaligned reg - test_gr_immed 10,gr15 - - set_gr_addr badb,gr17 -badb: stqfi fr2,@(sp,0) ; misaligned reg - test_gr_immed 11,gr15 - - set_gr_addr badc,gr17 -badc: ldqfi @(sp,0),fr10 ; misaligned reg - test_gr_immed 12,gr15 - - pass - -; exception handler -ok1: - cmpi gr20,0,icc0 - beq icc0,0,float - - ; check register_exception - test_spr_immed 0x1,esfr1 ; esr0 is active - test_spr_gr epcr0,gr17 - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0xc,esr0 ; esr0.ec is set - test_spr_bits 0x00c0,6,0x1,esr0 ; esr0.rec is set - test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is not set - movsg pcsr,gr60 - add gr60,gr20,gr60 - movgs gr60,pcsr - bra ret -float: - ; check fp_exception - test_spr_immed 0,esfr1 ; no esr's active -ret: - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/interrupts/reset.cgs b/sim/testsuite/sim/frv/interrupts/reset.cgs deleted file mode 100644 index ff2035c8a7e..00000000000 --- a/sim/testsuite/sim/frv/interrupts/reset.cgs +++ /dev/null @@ -1,81 +0,0 @@ -# frv testcase to generate reset interrupts -# mach: fr500 fr550 fr400 -# sim: --memory-region 0xff000000,64 - - .include "testutils.inc" - - start - - .global reset -reset: - and_spr_immed 0xfffffffb,psr ; turn off PSR.S - set_gr_immed 0xfeff0500,gr10 ; address of reset register - set_spr_immed 0x7fffffff,lcr - set_bctrlr_0_0 gr0 - -; Can't recover from hardware interrupt with enough state intact to verify it -; set_spr_addr ok1,lr -; set_mem_immed 0x3,gr10 ; cause hardware reset -; dcf @(gr10,gr0) ; Wait for store to happen -; fail -; -;ok1: ; reset should branch to reset address which should then branch here -; test_mem_immed 0x00000200,gr10 -; set_spr_addr ok2,lr -; set_mem_immed 0x2,gr10 ; cause hardware reset -; dcf @(gr10,gr0) ; Wait for store to happen -; fail -; -ok2: ; reset should branch to reset address which should then branch here -; test_mem_immed 0x00000200,gr10 - set_spr_addr ok3,lr - set_mem_immed 0x1,gr10 ; cause software reset - dcf @(gr10,gr0) ; Wait for store to happen - fail - -ok3: ; reset should branch to reset address which should then branch here - test_mem_immed 0x00000100,gr10 - test_spr_bits 0x4,2,1,psr ; psr.s is set - test_spr_bits 0x2,1,0,psr ; psr.ps not set - set_spr_addr bad,lr - set_mem_immed 0x0,gr10 ; no reset - test_mem_immed 0x0,gr10 - - ; now retest with HSR0.SA set - set_mem_immed 0,gr0 - set_gr_addr 0xff000000,gr11 - set_bctrlr_0_0 gr11 - or_spr_immed 0x00001000,hsr0 ; set HSR0.SA - -; Can't recover from hardware interrupt with enough state intact to verify it -; set_spr_addr ok4,lr -; dcf @(gr10,gr0) ; Wait for store to happen -; set_mem_immed 0x3,gr10 ; cause hardware reset -; fail -; -;ok4: ; reset should branch to reset address which should then branch here -; test_mem_immed 0x00000200,gr10 -; set_spr_addr ok5,lr -; set_mem_immed 0x2,gr10 ; cause hardware reset -; dcf @(gr10,gr0) ; Wait for store to happen -; fail -; -ok5: ; reset should branch to reset address which should then branch here -; test_mem_immed 0x00000200,gr10 - set_spr_addr ok6,lr - set_mem_immed 0x1,gr10 ; cause software reset - dcf @(gr10,gr0) ; Wait for store to happen - fail - -ok6: ; reset should branch to reset address which should then branch here - test_mem_immed 0x00000100,gr10 - test_spr_bits 0x4,2,1,psr ; psr.s is set - test_spr_bits 0x2,1,1,psr ; psr.ps is set - set_spr_addr bad,lr - set_mem_immed 0x0,gr10 ; no reset - test_mem_immed 0x0,gr10 - - pass - -bad: ; Should never get here - fail diff --git a/sim/testsuite/sim/frv/interrupts/shadow_regs.cgs b/sim/testsuite/sim/frv/interrupts/shadow_regs.cgs deleted file mode 100644 index ee6bea45e71..00000000000 --- a/sim/testsuite/sim/frv/interrupts/shadow_regs.cgs +++ /dev/null @@ -1,205 +0,0 @@ -# FRV testcase for handling of shadow registers SR0-SR4 -# mach: frv - - .include "testutils.inc" - - start - - .global tra -tra: - test_spr_bits 0x800,11,1,psr ; PSR.ESR set - test_spr_bits 0x4,2,1,psr ; PSR.S set - - ; Set up exception handler for later - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - set_spr_immed 128,lcr - set_psr_et 1 - - set_gr_immed 0x11111111,gr4 ; SGR4-7 - set_gr_immed 0x22222222,gr5 - set_gr_immed 0x33333333,gr6 - set_gr_immed 0x44444444,gr7 - set_spr_immed 0x55555555,sr0 ; UGR4-7 - set_spr_immed 0x66666666,sr1 - set_spr_immed 0x77777777,sr2 - set_spr_immed 0x88888888,sr3 - - and_spr_immed 0xfffff7ff,psr ; turn off PSR.ESR - test_gr_immed 0x11111111,gr4 ; SGR4-7 - test_gr_immed 0x22222222,gr5 - test_gr_immed 0x33333333,gr6 - test_gr_immed 0x44444444,gr7 - test_spr_immed 0x11111111,sr0 ; SGR4-7 - test_spr_immed 0x22222222,sr1 - test_spr_immed 0x33333333,sr2 - test_spr_immed 0x44444444,sr3 - - set_spr_immed 0x55555555,sr0 ; SGR4-7 - set_spr_immed 0x66666666,sr1 - set_spr_immed 0x77777777,sr2 - set_spr_immed 0x88888888,sr3 - test_gr_immed 0x55555555,gr4 ; SGR4-7 - test_gr_immed 0x66666666,gr5 - test_gr_immed 0x77777777,gr6 - test_gr_immed 0x88888888,gr7 - test_spr_immed 0x55555555,sr0 ; SGR4-7 - test_spr_immed 0x66666666,sr1 - test_spr_immed 0x77777777,sr2 - test_spr_immed 0x88888888,sr3 - - set_gr_immed 0x11111111,gr4 ; SGR4-7 - set_gr_immed 0x22222222,gr5 - set_gr_immed 0x33333333,gr6 - set_gr_immed 0x44444444,gr7 - test_gr_immed 0x11111111,gr4 ; SGR4-7 - test_gr_immed 0x22222222,gr5 - test_gr_immed 0x33333333,gr6 - test_gr_immed 0x44444444,gr7 - test_spr_immed 0x11111111,sr0 ; SGR4-7 - test_spr_immed 0x22222222,sr1 - test_spr_immed 0x33333333,sr2 - test_spr_immed 0x44444444,sr3 - - or_spr_immed 0x00000800,psr ; turn on PSR.ESR - test_gr_immed 0x11111111,gr4 ; SGR4-7 -- SR0-3 (UGR4-7) are undefined - test_gr_immed 0x22222222,gr5 - test_gr_immed 0x33333333,gr6 - test_gr_immed 0x44444444,gr7 - - set_spr_immed 0x55555555,sr0 ; UGR4-7 - set_spr_immed 0x66666666,sr1 - set_spr_immed 0x77777777,sr2 - set_spr_immed 0x88888888,sr3 - test_gr_immed 0x11111111,gr4 ; SGR4-7 - test_gr_immed 0x22222222,gr5 - test_gr_immed 0x33333333,gr6 - test_gr_immed 0x44444444,gr7 - test_spr_immed 0x55555555,sr0 ; UGR4-7 - test_spr_immed 0x66666666,sr1 - test_spr_immed 0x77777777,sr2 - test_spr_immed 0x88888888,sr3 - - and_spr_immed 0xfffffffb,psr ; turn off PSR.S - test_spr_immed 0x11111111,sr0 ; SGR4-7 - test_spr_immed 0x22222222,sr1 - test_spr_immed 0x33333333,sr2 - test_spr_immed 0x44444444,sr3 - test_gr_immed 0x55555555,gr4 ; UGR4-7 - test_gr_immed 0x66666666,gr5 - test_gr_immed 0x77777777,gr6 - test_gr_immed 0x88888888,gr7 - - ; need to generate a trap to return to supervisor mode - set_spr_addr ok0,lr - tira gr0,4 ; should branch to tbr + (128 + 4)*16 - - test_spr_bits 0x800,11,0,psr ; PSR.ESR clear - test_spr_bits 0x4,2,0,psr ; PSR.S clear - test_gr_immed 0x11111111,gr4 ; SGR4-7 - test_gr_immed 0x22222222,gr5 - test_gr_immed 0x33333333,gr6 - test_gr_immed 0x44444444,gr7 - test_spr_immed 0x11111111,sr0 ; SGR4-7 - test_spr_immed 0x22222222,sr1 - test_spr_immed 0x33333333,sr2 - test_spr_immed 0x44444444,sr3 - - set_gr_immed 0x55555555,gr4 ; SGR4-7 - set_gr_immed 0x66666666,gr5 - set_gr_immed 0x77777777,gr6 - set_gr_immed 0x88888888,gr7 - test_gr_immed 0x55555555,gr4 ; SGR4-7 - test_gr_immed 0x66666666,gr5 - test_gr_immed 0x77777777,gr6 - test_gr_immed 0x88888888,gr7 - test_spr_immed 0x55555555,sr0 ; SGR4-7 - test_spr_immed 0x66666666,sr1 - test_spr_immed 0x77777777,sr2 - test_spr_immed 0x88888888,sr3 - - set_gr_immed 0x11111111,gr4 ; SGR4-7 - set_gr_immed 0x22222222,gr5 - set_gr_immed 0x33333333,gr6 - set_gr_immed 0x44444444,gr7 - test_gr_immed 0x11111111,gr4 ; SGR4-7 - test_gr_immed 0x22222222,gr5 - test_gr_immed 0x33333333,gr6 - test_gr_immed 0x44444444,gr7 - test_spr_immed 0x11111111,sr0 ; SGR4-7 - test_spr_immed 0x22222222,sr1 - test_spr_immed 0x33333333,sr2 - test_spr_immed 0x44444444,sr3 - - ; need to generate a trap to return to supervisor mode - set_spr_addr ok1,lr - tira gr0,4 ; should branch to tbr + (128 + 4)*16 - - pass - -ok0: ; exception handler should branch here the first time - test_spr_bits 0x800,11,1,psr ; PSR.ESR set - test_spr_bits 0x4,2,1,psr ; PSR.S set - test_gr_immed 0x11111111,gr4 ; SGR4-7 - test_gr_immed 0x22222222,gr5 - test_gr_immed 0x33333333,gr6 - test_gr_immed 0x44444444,gr7 - test_spr_immed 0x55555555,sr0 ; UGR4-7 - test_spr_immed 0x66666666,sr1 - test_spr_immed 0x77777777,sr2 - test_spr_immed 0x88888888,sr3 - - and_spr_immed 0xfffff7ff,psr ; turn off PSR.ESR - test_gr_immed 0x11111111,gr4 ; SGR4-7 - test_gr_immed 0x22222222,gr5 - test_gr_immed 0x33333333,gr6 - test_gr_immed 0x44444444,gr7 - test_spr_immed 0x11111111,sr0 ; SGR4-7 - test_spr_immed 0x22222222,sr1 - test_spr_immed 0x33333333,sr2 - test_spr_immed 0x44444444,sr3 - rett 0 - fail - -ok1: ; exception handler should branch here the second time - test_spr_bits 0x800,11,0,psr ; PSR.ESR clear - test_spr_bits 0x4,2,1,psr ; PSR.S set - - test_gr_immed 0x11111111,gr4 ; SGR4-7 - test_gr_immed 0x22222222,gr5 - test_gr_immed 0x33333333,gr6 - test_gr_immed 0x44444444,gr7 - test_spr_immed 0x11111111,sr0 ; SGR4-7 - test_spr_immed 0x22222222,sr1 - test_spr_immed 0x33333333,sr2 - test_spr_immed 0x44444444,sr3 - - set_spr_immed 0x55555555,sr0 ; SGR4-7 - set_spr_immed 0x66666666,sr1 - set_spr_immed 0x77777777,sr2 - set_spr_immed 0x88888888,sr3 - test_gr_immed 0x55555555,gr4 ; SGR4-7 - test_gr_immed 0x66666666,gr5 - test_gr_immed 0x77777777,gr6 - test_gr_immed 0x88888888,gr7 - test_spr_immed 0x55555555,sr0 ; SGR4-7 - test_spr_immed 0x66666666,sr1 - test_spr_immed 0x77777777,sr2 - test_spr_immed 0x88888888,sr3 - - set_gr_immed 0x11111111,gr4 ; SGR4-7 - set_gr_immed 0x22222222,gr5 - set_gr_immed 0x33333333,gr6 - set_gr_immed 0x44444444,gr7 - test_gr_immed 0x11111111,gr4 ; SGR4-7 - test_gr_immed 0x22222222,gr5 - test_gr_immed 0x33333333,gr6 - test_gr_immed 0x44444444,gr7 - test_spr_immed 0x11111111,sr0 ; SGR4-7 - test_spr_immed 0x22222222,sr1 - test_spr_immed 0x33333333,sr2 - test_spr_immed 0x44444444,sr3 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/interrupts/timer.cgs b/sim/testsuite/sim/frv/interrupts/timer.cgs deleted file mode 100644 index e9cebc299bd..00000000000 --- a/sim/testsuite/sim/frv/interrupts/timer.cgs +++ /dev/null @@ -1,31 +0,0 @@ -# frv testcase to generate timer interrupt for st $GRk,@($GRi,$GRj) -# mach: fr500 fr550 fr400 -# sim: --timer 200,14 - .include "testutils.inc" - - start - - .global align -align: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x2e0,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 0x7fffffff,lcr - set_spr_addr ok1,lr - and_spr_immed 0xffffff87,psr ; enable external interrupts - or_spr_immed 0x00000069,psr ; enable external interrupts - - set_gr_immed 10,gr16 - set_gr_immed 0,gr15 - -again: cmp gr15,gr16,icc0 - blt icc0,0,again - - pass - -; exception handler -ok1: - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/jmpil.cgs b/sim/testsuite/sim/frv/jmpil.cgs deleted file mode 100644 index 1d11067f224..00000000000 --- a/sim/testsuite/sim/frv/jmpil.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# frv testcase for jmpil @($GRi,$d12) -# mach: all - - .include "testutils.inc" - - start - - .global jmpil -jmpil: - set_spr_immed 0,lr - set_gr_addr ok1,gr8 - jmpil @(gr8,2) ; target gets aligned down - fail -ok1: - test_spr_immed 0,lr - - pass diff --git a/sim/testsuite/sim/frv/jmpl.cgs b/sim/testsuite/sim/frv/jmpl.cgs deleted file mode 100644 index 9a58e606614..00000000000 --- a/sim/testsuite/sim/frv/jmpl.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# frv testcase for jmpl @($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global jmpl -jmpl: - set_spr_immed 0,lr - set_gr_addr ok1,gr8 - set_gr_immed 1,gr9 ; target gets aligned down - jmpl @(gr8,gr9) - fail -ok1: - test_spr_immed 0,lr - - pass diff --git a/sim/testsuite/sim/frv/jmpl.pcgs b/sim/testsuite/sim/frv/jmpl.pcgs deleted file mode 100644 index 2126820a697..00000000000 --- a/sim/testsuite/sim/frv/jmpl.pcgs +++ /dev/null @@ -1,42 +0,0 @@ -# frv parallel testcase for jmpl @($GRi,$GRj),$LI -# mach: all - - .include "testutils.inc" - - start - - .global jmpl -jmpl: - set_spr_immed 0,lr - set_gr_addr ok1,gr8 - set_gr_immed 0,gr9 - jmpl.p @(gr8,gr9) - setlos 10,gr10 - fail -ok1: - test_spr_immed 0,lr - test_gr_immed 10,gr10 - - set_gr_addr ok2,gr8 - inc_gr_immed -4,gr8 - inc_gr_immed 4,gr9 - calll.p @(gr8,gr9) - setlos 11,gr11 -bad2: - fail -ok2: - test_spr_addr bad2,lr - test_gr_immed 11,gr11 - - set_gr_addr ok3,gr8 - inc_gr_immed 4,gr8 - set_gr_immed -4,gr9 - setlos 12,gr12 - calll @(gr8,gr9) -bad3: - fail -ok3: - test_spr_addr bad3,lr - test_gr_immed 12,gr12 - - pass diff --git a/sim/testsuite/sim/frv/ld.cgs b/sim/testsuite/sim/frv/ld.cgs deleted file mode 100644 index 35206c2ad57..00000000000 --- a/sim/testsuite/sim/frv/ld.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# frv testcase for ld @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ld -ld: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - ld @(sp,gr7),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - ld @(sp,gr7),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - ld @(sp,gr7),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/ldbf.cgs b/sim/testsuite/sim/frv/ldbf.cgs deleted file mode 100644 index 52ac0775b45..00000000000 --- a/sim/testsuite/sim/frv/ldbf.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# frv testcase for ldbf @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldbf -ldbf: - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - ldbf @(sp,gr7),fr8 - test_fr_limmed 0x0000,0x00de,fr8 - - set_gr_immed 1,gr7 - ldbf @(sp,gr7),fr8 - test_fr_limmed 0x0000,0x00ad,fr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - ldbf @(sp,gr7),fr8 - test_fr_limmed 0x0000,0x0000,fr8 - - pass diff --git a/sim/testsuite/sim/frv/ldbfi.cgs b/sim/testsuite/sim/frv/ldbfi.cgs deleted file mode 100644 index 7e918069df9..00000000000 --- a/sim/testsuite/sim/frv/ldbfi.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# frv testcase for ldbfi @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldbfi -ldbfi: - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - ldbfi @(sp,0),fr8 - test_fr_limmed 0x0000,0x00de,fr8 - - ldbfi @(sp,1),fr8 - test_fr_limmed 0x0000,0x00ad,fr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - ldbfi @(sp,-1),fr8 - test_fr_limmed 0x0000,0x0000,fr8 - - pass diff --git a/sim/testsuite/sim/frv/ldbfu.cgs b/sim/testsuite/sim/frv/ldbfu.cgs deleted file mode 100644 index 3cbfb91d959..00000000000 --- a/sim/testsuite/sim/frv/ldbfu.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# frv testcase for ldbfu @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldbfu -ldbfu: - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - ldbfu @(sp,gr7),fr8 - test_fr_limmed 0x0000,0x00de,fr8 - test_gr_gr sp,gr20 - - inc_gr_immed 1,gr20 - set_gr_immed 1,gr7 - ldbfu @(sp,gr7),fr8 - test_fr_limmed 0x0000,0x00ad,fr8 - test_gr_gr sp,gr20 - - inc_gr_immed 2,gr20 - inc_gr_immed -1,sp - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - ldbfu @(sp,gr7),fr8 - test_fr_limmed 0x0000,0x0000,fr8 - test_gr_gr sp,gr20 - - pass diff --git a/sim/testsuite/sim/frv/ldc.cgs b/sim/testsuite/sim/frv/ldc.cgs deleted file mode 100644 index 4593c31d118..00000000000 --- a/sim/testsuite/sim/frv/ldc.cgs +++ /dev/null @@ -1,30 +0,0 @@ -# frv testcase for ldc @($GRi,$GRj),$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global ldc -ldc: - set_mem_limmed 0xdead,0xbeef,sp - set_cpr_limmed 0xbeef,0xdead,cpr8 - - set_gr_immed 0,gr7 - ldc @(sp,gr7),cpr8 - test_cpr_limmed 0xdead,0xbeef,cpr8 - - set_cpr_limmed 0xbeef,0xdead,cpr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - ldc @(sp,gr7),cpr8 - test_cpr_limmed 0xdead,0xbeef,cpr8 - - set_cpr_limmed 0xbeef,0xdead,cpr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - ldc @(sp,gr7),cpr8 - test_cpr_limmed 0xdead,0xbeef,cpr8 - - pass diff --git a/sim/testsuite/sim/frv/ldcu.cgs b/sim/testsuite/sim/frv/ldcu.cgs deleted file mode 100644 index 69890a8f6a4..00000000000 --- a/sim/testsuite/sim/frv/ldcu.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# frv testcase for ldcu @($GRi,$GRj),$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global ldcu -ldcu: - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_cpr_limmed 0xbeef,0xdead,cpr8 - - set_gr_immed 0,gr7 - ldcu @(sp,gr7),cpr8 - test_cpr_limmed 0xdead,0xbeef,cpr8 - test_gr_gr sp,gr20 - - set_cpr_limmed 0xbeef,0xdead,cpr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - ldcu @(sp,gr7),cpr8 - test_cpr_limmed 0xdead,0xbeef,cpr8 - test_gr_gr sp,gr20 - - set_cpr_limmed 0xbeef,0xdead,cpr8 - inc_gr_immed 4,sp - set_gr_immed -4,gr7 - ldcu @(sp,gr7),cpr8 - test_cpr_limmed 0xdead,0xbeef,cpr8 - test_gr_gr sp,gr20 - - pass diff --git a/sim/testsuite/sim/frv/ldd.cgs b/sim/testsuite/sim/frv/ldd.cgs deleted file mode 100644 index fa09d31d963..00000000000 --- a/sim/testsuite/sim/frv/ldd.cgs +++ /dev/null @@ -1,43 +0,0 @@ -# frv testcase for ldd @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldd -ldd: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_immed 0,gr7 - ldd @(sp,gr7),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - ldd @(sp,gr7),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - ldd @(sp,gr7),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - - ; loading into gr0 should have no effect - ; gr1 is sp - set_gr_gr gr1,gr8 - ldd @(sp,gr7),gr0 - test_gr_immed 0,gr0 - test_gr_gr gr1,gr8 - pass diff --git a/sim/testsuite/sim/frv/lddc.cgs b/sim/testsuite/sim/frv/lddc.cgs deleted file mode 100644 index e01a2146ef1..00000000000 --- a/sim/testsuite/sim/frv/lddc.cgs +++ /dev/null @@ -1,45 +0,0 @@ -# frv testcase for lddc @($GRi,$GRj),$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global lddc -lddc: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_cpr_limmed 0xdead,0xbeef,cpr8 - set_cpr_limmed 0xbeef,0xdead,cpr9 - - set_gr_immed 0,gr7 - ; loading into cpr0 is business as usual - set_cpr_limmed 0xdead,0xbeef,cpr0 - set_cpr_limmed 0xbeef,0xdead,cpr1 - lddc @(sp,gr7),cpr0 - test_cpr_limmed 0xbeef,0xdead,cpr0 - test_cpr_limmed 0xdead,0xbeef,cpr1 - - lddc @(sp,gr7),cpr8 - test_cpr_limmed 0xbeef,0xdead,cpr8 - test_cpr_limmed 0xdead,0xbeef,cpr9 - - set_cpr_limmed 0xdead,0xbeef,cpr8 - set_cpr_limmed 0xbeef,0xdead,cpr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - lddc @(sp,gr7),cpr8 - test_cpr_limmed 0xbeef,0xdead,cpr8 - test_cpr_limmed 0xdead,0xbeef,cpr9 - - set_cpr_limmed 0xdead,0xbeef,cpr8 - set_cpr_limmed 0xbeef,0xdead,cpr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - lddc @(sp,gr7),cpr8 - test_cpr_limmed 0xbeef,0xdead,cpr8 - test_cpr_limmed 0xdead,0xbeef,cpr9 - - pass diff --git a/sim/testsuite/sim/frv/lddcu.cgs b/sim/testsuite/sim/frv/lddcu.cgs deleted file mode 100644 index b4ed485fa27..00000000000 --- a/sim/testsuite/sim/frv/lddcu.cgs +++ /dev/null @@ -1,42 +0,0 @@ -# frv testcase for lddcu @($GRi,$GRj),$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global lddcu -lddcu: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_cpr_limmed 0xdead,0xbeef,cpr8 - set_cpr_limmed 0xbeef,0xdead,cpr9 - - set_gr_immed 0,gr7 - lddcu @(sp,gr7),cpr8 - test_cpr_limmed 0xbeef,0xdead,cpr8 - test_cpr_limmed 0xdead,0xbeef,cpr9 - test_gr_gr sp,gr20 - - set_cpr_limmed 0xdead,0xbeef,cpr8 - set_cpr_limmed 0xbeef,0xdead,cpr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - lddcu @(sp,gr7),cpr8 - test_cpr_limmed 0xbeef,0xdead,cpr8 - test_cpr_limmed 0xdead,0xbeef,cpr9 - test_gr_gr sp,gr20 - - set_cpr_limmed 0xdead,0xbeef,cpr8 - set_cpr_limmed 0xbeef,0xdead,cpr9 - inc_gr_immed 8,sp - set_gr_immed -8,gr7 - lddcu @(sp,gr7),cpr8 - test_cpr_limmed 0xbeef,0xdead,cpr8 - test_cpr_limmed 0xdead,0xbeef,cpr9 - test_gr_gr sp,gr20 - - pass diff --git a/sim/testsuite/sim/frv/lddf.cgs b/sim/testsuite/sim/frv/lddf.cgs deleted file mode 100644 index f7bae78935d..00000000000 --- a/sim/testsuite/sim/frv/lddf.cgs +++ /dev/null @@ -1,46 +0,0 @@ -# frv testcase for lddf @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global lddf -lddf: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_immed 0,gr7 - ; loading into fr0 is business as usual - set_fr_iimmed 0xdead,0xbeef,fr0 - set_fr_iimmed 0xbeef,0xdead,fr1 - lddf @(sp,gr7),fr0 - test_fr_limmed 0xbeef,0xdead,fr0 - test_fr_limmed 0xdead,0xbeef,fr1 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - lddf @(sp,gr7),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - lddf @(sp,gr7),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - lddf @(sp,gr7),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - - pass diff --git a/sim/testsuite/sim/frv/lddfi.cgs b/sim/testsuite/sim/frv/lddfi.cgs deleted file mode 100644 index 1eac91632f4..00000000000 --- a/sim/testsuite/sim/frv/lddfi.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# frv testcase for lddfi @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global lddfi -lddfi: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - lddfi @(sp,0),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,sp - lddfi @(sp,8),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 16,sp - lddfi @(sp,-8),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - - pass diff --git a/sim/testsuite/sim/frv/lddfu.cgs b/sim/testsuite/sim/frv/lddfu.cgs deleted file mode 100644 index cb4c86eed02..00000000000 --- a/sim/testsuite/sim/frv/lddfu.cgs +++ /dev/null @@ -1,41 +0,0 @@ -# frv testcase for lddfu @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global lddfu -lddfu: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_immed 0,gr7 - lddfu @(sp,gr7),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - lddfu @(sp,gr7),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 8,sp - set_gr_immed -8,gr7 - lddfu @(sp,gr7),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_gr_gr sp,gr20 - - pass diff --git a/sim/testsuite/sim/frv/lddi.cgs b/sim/testsuite/sim/frv/lddi.cgs deleted file mode 100644 index 38ef2b4f728..00000000000 --- a/sim/testsuite/sim/frv/lddi.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# frv testcase for lddi @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global lddi -lddi: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - lddi @(sp,0),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,sp - lddi @(sp,8),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 16,sp - lddi @(sp,-8),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - - pass diff --git a/sim/testsuite/sim/frv/lddu.cgs b/sim/testsuite/sim/frv/lddu.cgs deleted file mode 100644 index 5b2ead17720..00000000000 --- a/sim/testsuite/sim/frv/lddu.cgs +++ /dev/null @@ -1,50 +0,0 @@ -# frv testcase for lddu @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global lddu -lddu: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_immed 0,gr7 - lddu @(sp,gr7),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - lddu @(sp,gr7),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 8,sp - set_gr_immed -8,gr7 - lddu @(sp,gr7),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 8,sp - set_gr_immed -8,gr7 - set_gr_gr sp,gr8 - lddu @(gr8,gr7),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - - pass diff --git a/sim/testsuite/sim/frv/ldf.cgs b/sim/testsuite/sim/frv/ldf.cgs deleted file mode 100644 index 996d72c9e89..00000000000 --- a/sim/testsuite/sim/frv/ldf.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# frv testcase for ldf @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldf -ldf: - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - ldf @(sp,gr7),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - ldf @(sp,gr7),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - ldf @(sp,gr7),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - pass diff --git a/sim/testsuite/sim/frv/ldfi.cgs b/sim/testsuite/sim/frv/ldfi.cgs deleted file mode 100644 index e5ea94dbda4..00000000000 --- a/sim/testsuite/sim/frv/ldfi.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for ldfi @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldfi -ldfi: - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - ldfi @(sp,0),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,sp - ldfi @(sp,4),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 8,sp - ldfi @(sp,-4),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - pass diff --git a/sim/testsuite/sim/frv/ldfu.cgs b/sim/testsuite/sim/frv/ldfu.cgs deleted file mode 100644 index 08f67db4375..00000000000 --- a/sim/testsuite/sim/frv/ldfu.cgs +++ /dev/null @@ -1,33 +0,0 @@ -# frv testcase for ldfu @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldfu -ldfu: - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - ldfu @(sp,gr7),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - ldfu @(sp,gr7),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 4,sp - set_gr_immed -4,gr7 - ldfu @(sp,gr7),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - test_gr_gr sp,gr20 - - pass diff --git a/sim/testsuite/sim/frv/ldhf.cgs b/sim/testsuite/sim/frv/ldhf.cgs deleted file mode 100644 index 8935ac7fd61..00000000000 --- a/sim/testsuite/sim/frv/ldhf.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# frv testcase for ldhf @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldhf -ldhf: - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - ldhf @(sp,gr7),fr8 - test_fr_limmed 0x0000,0xdead,fr8 - - set_gr_immed 2,gr7 - ldhf @(sp,gr7),fr8 - test_fr_limmed 0x0000,0xbeef,fr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - ldhf @(sp,gr7),fr8 - test_fr_limmed 0x0000,0x0000,fr8 - - pass diff --git a/sim/testsuite/sim/frv/ldhfi.cgs b/sim/testsuite/sim/frv/ldhfi.cgs deleted file mode 100644 index 362ec504854..00000000000 --- a/sim/testsuite/sim/frv/ldhfi.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# frv testcase for ldhfi @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldhfi -ldhfi: - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - ldhfi @(sp,0),fr8 - test_fr_limmed 0x0000,0xdead,fr8 - - ldhfi @(sp,2),fr8 - test_fr_limmed 0x0000,0xbeef,fr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - ldhfi @(sp,-2),fr8 - test_fr_limmed 0x0000,0x0000,fr8 - - pass diff --git a/sim/testsuite/sim/frv/ldhfu.cgs b/sim/testsuite/sim/frv/ldhfu.cgs deleted file mode 100644 index 0b342e1e7dc..00000000000 --- a/sim/testsuite/sim/frv/ldhfu.cgs +++ /dev/null @@ -1,33 +0,0 @@ -# frv testcase for ldhfu @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldhfu -ldhfu: - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - ldhfu @(sp,gr7),fr8 - test_fr_limmed 0x0000,0xdead,fr8 - test_gr_gr sp,gr20 - - inc_gr_immed 2,gr20 - set_gr_immed 2,gr7 - ldhfu @(sp,gr7),fr8 - test_fr_limmed 0x0000,0xbeef,fr8 - test_gr_gr sp,gr20 - - inc_gr_immed -2,sp - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - ldhfu @(sp,gr7),fr8 - test_fr_limmed 0x0000,0x0000,fr8 - test_gr_gr sp,gr20 - - pass diff --git a/sim/testsuite/sim/frv/ldi.cgs b/sim/testsuite/sim/frv/ldi.cgs deleted file mode 100644 index f36b95d9f58..00000000000 --- a/sim/testsuite/sim/frv/ldi.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for ldi @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldi -ldi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - ldi @(sp,0),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,sp - ldi @(sp,4),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 8,sp - ldi @(sp,-4),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/ldq.cgs b/sim/testsuite/sim/frv/ldq.cgs deleted file mode 100644 index e61f1de1c7b..00000000000 --- a/sim/testsuite/sim/frv/ldq.cgs +++ /dev/null @@ -1,64 +0,0 @@ -# frv testcase for ldq @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global ldq -ldq: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_immed 0,gr7 - ldq @(sp,gr7),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - ldq @(sp,gr7),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - ldq @(sp,gr7),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - - ; loading into gr0 has no effect - ; gr1 is sp - set_gr_gr gr1,gr8 - set_gr_limmed 0x1234,0x5678,gr2 - set_gr_limmed 0x9abc,0xdef0,gr3 - ldq @(sp,gr7),gr0 - test_gr_immed 0,gr0 - test_gr_gr gr1,gr8 - set_gr_immed 0x12345678,gr2 - set_gr_immed 0x9abcdef0,gr3 - - pass diff --git a/sim/testsuite/sim/frv/ldqc.cgs b/sim/testsuite/sim/frv/ldqc.cgs deleted file mode 100644 index 64b6a6afa61..00000000000 --- a/sim/testsuite/sim/frv/ldqc.cgs +++ /dev/null @@ -1,60 +0,0 @@ -# frv testcase for ldqc @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global ldqc -ldqc: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_cpr_limmed 0xdead,0xbeef,cpr8 - set_cpr_limmed 0xbeef,0xdead,cpr9 - set_cpr_limmed 0x1234,0x5678,cpr10 - set_cpr_limmed 0x9abc,0xdef0,cpr11 - - set_gr_immed 0,gr7 - ;loading into cpr0 is business as usual - ldqc @(sp,gr7),cpr0 - test_cpr_limmed 0x9abc,0xdef0,cpr0 - test_cpr_limmed 0x1234,0x5678,cpr1 - test_cpr_limmed 0xbeef,0xdead,cpr2 - test_cpr_limmed 0xdead,0xbeef,cpr3 - - ldqc @(sp,gr7),cpr8 - test_cpr_limmed 0x9abc,0xdef0,cpr8 - test_cpr_limmed 0x1234,0x5678,cpr9 - test_cpr_limmed 0xbeef,0xdead,cpr10 - test_cpr_limmed 0xdead,0xbeef,cpr11 - - set_cpr_limmed 0xdead,0xbeef,cpr8 - set_cpr_limmed 0xbeef,0xdead,cpr9 - set_cpr_limmed 0x1234,0x5678,cpr10 - set_cpr_limmed 0x9abc,0xdef0,cpr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - ldqc @(sp,gr7),cpr8 - test_cpr_limmed 0x9abc,0xdef0,cpr8 - test_cpr_limmed 0x1234,0x5678,cpr9 - test_cpr_limmed 0xbeef,0xdead,cpr10 - test_cpr_limmed 0xdead,0xbeef,cpr11 - - set_cpr_limmed 0xdead,0xbeef,cpr8 - set_cpr_limmed 0xbeef,0xdead,cpr9 - set_cpr_limmed 0x1234,0x5678,cpr10 - set_cpr_limmed 0x9abc,0xdef0,cpr11 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - ldqc @(sp,gr7),cpr8 - test_cpr_limmed 0x9abc,0xdef0,cpr8 - test_cpr_limmed 0x1234,0x5678,cpr9 - test_cpr_limmed 0xbeef,0xdead,cpr10 - test_cpr_limmed 0xdead,0xbeef,cpr11 - - pass diff --git a/sim/testsuite/sim/frv/ldqcu.cgs b/sim/testsuite/sim/frv/ldqcu.cgs deleted file mode 100644 index 18d9246c542..00000000000 --- a/sim/testsuite/sim/frv/ldqcu.cgs +++ /dev/null @@ -1,57 +0,0 @@ -# frv testcase for ldqcu @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global ldqcu -ldqcu: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_gr sp,gr20 - set_cpr_limmed 0xdead,0xbeef,cpr8 - set_cpr_limmed 0xbeef,0xdead,cpr9 - set_cpr_limmed 0x1234,0x5678,cpr10 - set_cpr_limmed 0x9abc,0xdef0,cpr11 - - set_gr_immed 0,gr7 - ldqcu @(sp,gr7),cpr8 - test_cpr_limmed 0x9abc,0xdef0,cpr8 - test_cpr_limmed 0x1234,0x5678,cpr9 - test_cpr_limmed 0xbeef,0xdead,cpr10 - test_cpr_limmed 0xdead,0xbeef,cpr11 - test_gr_gr sp,gr20 - - set_cpr_limmed 0xdead,0xbeef,cpr8 - set_cpr_limmed 0xbeef,0xdead,cpr9 - set_cpr_limmed 0x1234,0x5678,cpr10 - set_cpr_limmed 0x9abc,0xdef0,cpr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - ldqcu @(sp,gr7),cpr8 - test_cpr_limmed 0x9abc,0xdef0,cpr8 - test_cpr_limmed 0x1234,0x5678,cpr9 - test_cpr_limmed 0xbeef,0xdead,cpr10 - test_cpr_limmed 0xdead,0xbeef,cpr11 - test_gr_gr sp,gr20 - - set_cpr_limmed 0xdead,0xbeef,cpr8 - set_cpr_limmed 0xbeef,0xdead,cpr9 - set_cpr_limmed 0x1234,0x5678,cpr10 - set_cpr_limmed 0x9abc,0xdef0,cpr11 - inc_gr_immed 16,sp - set_gr_immed -16,gr7 - ldqcu @(sp,gr7),cpr8 - test_cpr_limmed 0x9abc,0xdef0,cpr8 - test_cpr_limmed 0x1234,0x5678,cpr9 - test_cpr_limmed 0xbeef,0xdead,cpr10 - test_cpr_limmed 0xdead,0xbeef,cpr11 - test_gr_gr sp,gr20 - - pass diff --git a/sim/testsuite/sim/frv/ldqf.cgs b/sim/testsuite/sim/frv/ldqf.cgs deleted file mode 100644 index 66fb65c130f..00000000000 --- a/sim/testsuite/sim/frv/ldqf.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for ldqf @($GRi,$GRj),$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global ldqf -ldqf: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - - set_gr_immed 0,gr7 - ; loading into fr0 is business as usual - ldqf @(sp,gr7),fr0 - test_fr_limmed 0x9abc,0xdef0,fr0 - test_fr_limmed 0x1234,0x5678,fr1 - test_fr_limmed 0xbeef,0xdead,fr2 - test_fr_limmed 0xdead,0xbeef,fr3 - - ldqf @(sp,gr7),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - ldqf @(sp,gr7),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - ldqf @(sp,gr7),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - - pass diff --git a/sim/testsuite/sim/frv/ldqfi.cgs b/sim/testsuite/sim/frv/ldqfi.cgs deleted file mode 100644 index 28c3b1f3247..00000000000 --- a/sim/testsuite/sim/frv/ldqfi.cgs +++ /dev/null @@ -1,51 +0,0 @@ -# frv testcase for ldqfi @($GRi,$GRj),$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global ldqfi -ldqfi: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - - ldqfi @(sp,0),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - inc_gr_immed -16,sp - ldqfi @(sp,16),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - inc_gr_immed 32,sp - ldqfi @(sp,-16),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - - pass diff --git a/sim/testsuite/sim/frv/ldqfu.cgs b/sim/testsuite/sim/frv/ldqfu.cgs deleted file mode 100644 index 7287958166d..00000000000 --- a/sim/testsuite/sim/frv/ldqfu.cgs +++ /dev/null @@ -1,58 +0,0 @@ -# frv testcase for ldqfu @($GRi,$GRj),$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global ldqfu -ldqfu: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_gr sp,gr20 - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - - set_gr_immed 0,gr7 - ldqfu @(sp,gr7),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - ldqfu @(sp,gr7),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - test_gr_gr sp,gr20 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - inc_gr_immed 16,sp - set_gr_immed -16,gr7 - ldqfu @(sp,gr7),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - test_gr_gr sp,gr20 - - pass diff --git a/sim/testsuite/sim/frv/ldqi.cgs b/sim/testsuite/sim/frv/ldqi.cgs deleted file mode 100644 index 64d66f2f766..00000000000 --- a/sim/testsuite/sim/frv/ldqi.cgs +++ /dev/null @@ -1,51 +0,0 @@ -# frv testcase for ldqi @($GRi,$GRj),$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global ldqi -ldqi: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - ldqi @(sp,0),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,sp - ldqi @(sp,16),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 32,sp - ldqi @(sp,-16),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - - pass diff --git a/sim/testsuite/sim/frv/ldqu.cgs b/sim/testsuite/sim/frv/ldqu.cgs deleted file mode 100644 index 263eae1b60f..00000000000 --- a/sim/testsuite/sim/frv/ldqu.cgs +++ /dev/null @@ -1,71 +0,0 @@ -# frv testcase for ldqu @($GRi,$GRj),$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global ldqu -ldqu: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_gr sp,gr20 - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_immed 0,gr7 - ldqu @(sp,gr7),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - ldqu @(sp,gr7),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 16,sp - set_gr_immed -16,gr7 - ldqu @(sp,gr7),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - test_gr_gr sp,gr20 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 16,sp - set_gr_immed -16,gr7 - set_gr_gr sp,gr8 - ldqu @(gr8,gr7),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - - pass diff --git a/sim/testsuite/sim/frv/ldsb.cgs b/sim/testsuite/sim/frv/ldsb.cgs deleted file mode 100644 index 4b10639ca9f..00000000000 --- a/sim/testsuite/sim/frv/ldsb.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# frv testcase for ldsb @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldsb -ldsb: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - ldsb @(sp,gr7),gr8 - test_gr_limmed 0xffff,0xffde,gr8 - - set_gr_immed 1,gr7 - ldsb @(sp,gr7),gr8 - test_gr_limmed 0xffff,0xffad,gr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - ldsb @(sp,gr7),gr8 - test_gr_immed 0,gr8 - - pass diff --git a/sim/testsuite/sim/frv/ldsbi.cgs b/sim/testsuite/sim/frv/ldsbi.cgs deleted file mode 100644 index c90a129f317..00000000000 --- a/sim/testsuite/sim/frv/ldsbi.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# frv testcase for ldsbi @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldsbi -ldsbi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - ldsbi @(sp,0),gr8 - test_gr_limmed 0xffff,0xffde,gr8 - - ldsbi @(sp,1),gr8 - test_gr_limmed 0xffff,0xffad,gr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - ldsbi @(sp,-1),gr8 - test_gr_immed 0,gr8 - - pass diff --git a/sim/testsuite/sim/frv/ldsbu.cgs b/sim/testsuite/sim/frv/ldsbu.cgs deleted file mode 100644 index 976cee8204c..00000000000 --- a/sim/testsuite/sim/frv/ldsbu.cgs +++ /dev/null @@ -1,40 +0,0 @@ -# frv testcase for ldsbu @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldsbu -ldsbu: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - ldsbu @(sp,gr7),gr8 - test_gr_limmed 0xffff,0xffde,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 1,gr9 - set_gr_immed 1,gr7 - ldsbu @(sp,gr7),gr8 - test_gr_limmed 0xffff,0xffad,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 2,gr9 - inc_gr_immed -1,sp - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - ldsbu @(sp,gr7),gr8 - test_gr_immed 0,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed -3,sp - set_mem_limmed 0x0000,0x00da,sp - set_gr_immed 3,gr7 - ldsbu @(sp,gr7),sp - test_gr_limmed 0xffff,0xffda,sp - - pass diff --git a/sim/testsuite/sim/frv/ldsh.cgs b/sim/testsuite/sim/frv/ldsh.cgs deleted file mode 100644 index c526f39c71d..00000000000 --- a/sim/testsuite/sim/frv/ldsh.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# frv testcase for ldsh @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldsh -ldsh: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - ldsh @(sp,gr7),gr8 - test_gr_limmed 0xffff,0xdead,gr8 - - set_gr_immed 2,gr7 - ldsh @(sp,gr7),gr8 - test_gr_limmed 0xffff,0xbeef,gr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - ldsh @(sp,gr7),gr8 - test_gr_immed 0,gr8 - - pass diff --git a/sim/testsuite/sim/frv/ldshi.cgs b/sim/testsuite/sim/frv/ldshi.cgs deleted file mode 100644 index 69f99f13e83..00000000000 --- a/sim/testsuite/sim/frv/ldshi.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# frv testcase for ldshi @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldshi -ldshi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - ldshi @(sp,0),gr8 - test_gr_limmed 0xffff,0xdead,gr8 - - ldshi @(sp,2),gr8 - test_gr_limmed 0xffff,0xbeef,gr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - ldshi @(sp,-2),gr8 - test_gr_immed 0,gr8 - - pass diff --git a/sim/testsuite/sim/frv/ldshu.cgs b/sim/testsuite/sim/frv/ldshu.cgs deleted file mode 100644 index f1b8c23c5ea..00000000000 --- a/sim/testsuite/sim/frv/ldshu.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# frv testcase for ldshu @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldshu -ldshu: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - ldshu @(sp,gr7),gr8 - test_gr_limmed 0xffff,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 2,gr9 - set_gr_immed 2,gr7 - ldshu @(sp,gr7),gr8 - test_gr_limmed 0xffff,0xbeef,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed -2,sp - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - ldshu @(sp,gr7),gr8 - test_gr_immed 0,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed -2,sp - set_mem_limmed 0x0000,0xdead,sp - set_gr_immed 2,gr7 - ldshu @(sp,gr7),sp - test_gr_limmed 0xffff,0xdead,sp - - pass diff --git a/sim/testsuite/sim/frv/ldu.cgs b/sim/testsuite/sim/frv/ldu.cgs deleted file mode 100644 index b7f2e34aaaf..00000000000 --- a/sim/testsuite/sim/frv/ldu.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# frv testcase for ldu @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldu -ldu: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - ldu @(sp,gr7),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_gr sp,gr9 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - ldu @(sp,gr7),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_gr sp,gr9 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 4,sp - set_gr_immed -4,gr7 - ldu @(sp,gr7),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_gr sp,gr9 - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - ldu @(sp,gr7),sp - test_gr_limmed 0xdead,0xbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/ldub.cgs b/sim/testsuite/sim/frv/ldub.cgs deleted file mode 100644 index 1e192542a22..00000000000 --- a/sim/testsuite/sim/frv/ldub.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# frv testcase for ldub @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldub -ldub: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - ldub @(sp,gr7),gr8 - test_gr_limmed 0x0000,0x00de,gr8 - - set_gr_immed 1,gr7 - ldub @(sp,gr7),gr8 - test_gr_limmed 0x0000,0x00ad,gr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - ldub @(sp,gr7),gr8 - test_gr_limmed 0x0000,0x0000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/ldubi.cgs b/sim/testsuite/sim/frv/ldubi.cgs deleted file mode 100644 index 4c40beebc5e..00000000000 --- a/sim/testsuite/sim/frv/ldubi.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# frv testcase for ldubi @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldubi -ldubi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - ldubi @(sp,0),gr8 - test_gr_limmed 0x0000,0x00de,gr8 - - ldubi @(sp,1),gr8 - test_gr_limmed 0x0000,0x00ad,gr8 - - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - ldubi @(sp,-1),gr8 - test_gr_limmed 0x0000,0x0000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/ldubu.cgs b/sim/testsuite/sim/frv/ldubu.cgs deleted file mode 100644 index 8c99ab072a5..00000000000 --- a/sim/testsuite/sim/frv/ldubu.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# frv testcase for ldubu @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ldubu -ldubu: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - ldubu @(sp,gr7),gr8 - test_gr_limmed 0x0000,0x00de,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 1,gr9 - set_gr_immed 1,gr7 - ldubu @(sp,gr7),gr8 - test_gr_limmed 0x0000,0x00ad,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 2,gr9 - inc_gr_immed -1,sp - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - ldubu @(sp,gr7),gr8 - test_gr_limmed 0x0000,0x0000,gr8 - - inc_gr_immed -3,sp - set_mem_limmed 0xffff,0xffda,sp - set_gr_immed 3,gr7 - ldubu @(sp,gr7),sp - test_gr_limmed 0x0000,0x00da,sp - - pass diff --git a/sim/testsuite/sim/frv/lduh.cgs b/sim/testsuite/sim/frv/lduh.cgs deleted file mode 100644 index 24c3bac4b40..00000000000 --- a/sim/testsuite/sim/frv/lduh.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# frv testcase for lduh @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global lduh -lduh: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_immed 0,gr7 - lduh @(sp,gr7),gr8 - test_gr_limmed 0x0000,0xdead,gr8 - - set_gr_immed 2,gr7 - lduh @(sp,gr7),gr8 - test_gr_limmed 0x0000,0xbeef,gr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - lduh @(sp,gr7),gr8 - test_gr_limmed 0x0000,0x0000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/lduhi.cgs b/sim/testsuite/sim/frv/lduhi.cgs deleted file mode 100644 index b9896d62f58..00000000000 --- a/sim/testsuite/sim/frv/lduhi.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# frv testcase for lduhi @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global lduhi -lduhi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - lduhi @(sp,0),gr8 - test_gr_limmed 0x0000,0xdead,gr8 - - lduhi @(sp,2),gr8 - test_gr_limmed 0x0000,0xbeef,gr8 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - lduhi @(sp,-2),gr8 - test_gr_limmed 0x0000,0x0000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/lduhu.cgs b/sim/testsuite/sim/frv/lduhu.cgs deleted file mode 100644 index 52faecf6234..00000000000 --- a/sim/testsuite/sim/frv/lduhu.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# frv testcase for lduhu @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global lduhu -lduhu: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - lduhu @(sp,gr7),gr8 - test_gr_limmed 0x0000,0xdead,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed 2,gr9 - set_gr_immed 2,gr7 - lduhu @(sp,gr7),gr8 - test_gr_limmed 0x0000,0xbeef,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed -2,sp - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - lduhu @(sp,gr7),gr8 - test_gr_limmed 0x0000,0x0000,gr8 - test_gr_gr sp,gr9 - - inc_gr_immed -2,sp - set_mem_limmed 0xffff,0xdead,sp - set_gr_immed 2,gr7 - lduhu @(sp,gr7),sp - test_gr_limmed 0x0000,0xdead,sp - - pass diff --git a/sim/testsuite/sim/frv/lrbranch.pcgs b/sim/testsuite/sim/frv/lrbranch.pcgs deleted file mode 100644 index 0ac1a7568dd..00000000000 --- a/sim/testsuite/sim/frv/lrbranch.pcgs +++ /dev/null @@ -1,51 +0,0 @@ -# frv parallel testcase for lr branching -# mach: fr500 fr550 frv - - .include "testutils.inc" - - start - - .global lrbranch -lrbranch: - ; Both conditions true - set_spr_immed 128,lcr - set_spr_addr ok1,lr - set_icc 0x4 0 - bcgelr.p icc0,0,0 - bra ok4 - fail -ok1: - test_spr_immed 127,LCR - - ; Only first condition true - set_spr_immed 128,lcr - set_spr_addr ok2,lr - set_icc 0x0 0 - bcgelr.p icc0,0,0 - bno - fail -ok2: - test_spr_immed 127,LCR - - ; Only second condition true - set_spr_immed 128,lcr - set_spr_addr ok3,lr - set_icc 0x8 0 - bcgelr.p icc0,0,0 - bra ok3 - fail -ok3: - test_spr_immed 127,LCR - - ; Both conditions false - set_spr_immed 128,lcr - set_spr_addr ok4,lr - set_icc 0x0 0 - bceqlr.p icc0,0,0 - bno - test_spr_immed 127,LCR - - pass - -ok4: - fail diff --git a/sim/testsuite/sim/frv/mabshs.cgs b/sim/testsuite/sim/frv/mabshs.cgs deleted file mode 100644 index 29b25328732..00000000000 --- a/sim/testsuite/sim/frv/mabshs.cgs +++ /dev/null @@ -1,67 +0,0 @@ -# frv testcase for mabshs $FRj,$FRk -# mach: fr400 - - .include "testutils.inc" - - start - - .global mabshs -mabshs: - set_fr_iimmed 0x0000,0x0000,fr10 - mabshs fr10,fr11 - test_fr_limmed 0x0000,0x0000,fr11 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0001,0xffff,fr10 - mabshs fr10,fr11 - test_fr_limmed 0x0001,0x0001,fr11 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7fff,0x8001,fr10 - mabshs fr10,fr11 - test_fr_limmed 0x7fff,0x7fff,fr11 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7fff,0x8000,fr10 - mabshs fr10,fr11 - test_fr_limmed 0x7fff,0x7fff,fr11 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8000,0x7fff,fr10 - mabshs fr10,fr11 - test_fr_limmed 0x7fff,0x7fff,fr11 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x7fff,0x8000,fr10 - set_fr_iimmed 0x8000,0x7fff,fr11 - mabshs.p fr10,fr12 - mabshs fr11,fr13 - test_fr_limmed 0x7fff,0x7fff,fr12 - test_fr_limmed 0x7fff,0x7fff,fr13 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 0x3c,2,0x8,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/maddhss.cgs b/sim/testsuite/sim/frv/maddhss.cgs deleted file mode 100644 index 289ecc77d8a..00000000000 --- a/sim/testsuite/sim/frv/maddhss.cgs +++ /dev/null @@ -1,100 +0,0 @@ -# frv testcase for maddhss $FRi,$FRj,$FRj -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global maddhss -maddhss: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0xbeef,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0x2345,0x6789,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0x1233,0x5677,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0x7fff,0x7fff,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - maddhss fr10,fr11,fr12 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - maddhss fr10,fr11,fr12 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - maddhss.p fr10,fr10,fr12 - maddhss fr11,fr11,fr13 - test_fr_limmed 0x0002,0x0002,fr12 - test_fr_limmed 0x7fff,0x7fff,fr13 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/maddhus.cgs b/sim/testsuite/sim/frv/maddhus.cgs deleted file mode 100644 index fe96e696629..00000000000 --- a/sim/testsuite/sim/frv/maddhus.cgs +++ /dev/null @@ -1,89 +0,0 @@ -# frv testcase for maddhus $FRi,$FRj,$FRj -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global maddhus -maddhus: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - maddhus fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - maddhus fr10,fr11,fr12 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - maddhus fr10,fr11,fr12 - test_fr_limmed 0xbeef,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - maddhus fr10,fr11,fr12 - test_fr_limmed 0x2345,0x6789,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - maddhus fr10,fr11,fr12 - test_fr_limmed 0x8000,0x7fff,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xfffe,0xfffe,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - maddhus fr10,fr11,fr12 - test_fr_limmed 0xffff,0xffff,fr12 - test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0002,0x0001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - maddhus fr10,fr11,fr12 - test_fr_limmed 0xffff,0xffff,fr12 - test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - maddhus.p fr10,fr10,fr12 - maddhus fr11,fr11,fr13 - test_fr_limmed 0x0002,0x0002,fr12 - test_fr_limmed 0xffff,0xffff,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/mand.cgs b/sim/testsuite/sim/frv/mand.cgs deleted file mode 100644 index c6aa993fa0a..00000000000 --- a/sim/testsuite/sim/frv/mand.cgs +++ /dev/null @@ -1,23 +0,0 @@ -# frv testcase for mand $FRinti,$FRintj,$FRintk -# mach: all - - .include "testutils.inc" - - start - - .global mand -mand: - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - mand fr7,fr8,fr8 - test_fr_iimmed 0,fr8 - - set_fr_iimmed 0xffff,0x0000,fr8 - mand fr7,fr8,fr8 - test_fr_iimmed 0xaaaa0000,fr8 - - set_fr_iimmed 0x0000,0xffff,fr8 - mand fr7,fr8,fr8 - test_fr_iimmed 0x0000aaaa,fr8 - - pass diff --git a/sim/testsuite/sim/frv/maveh.cgs b/sim/testsuite/sim/frv/maveh.cgs deleted file mode 100644 index d48ad72553b..00000000000 --- a/sim/testsuite/sim/frv/maveh.cgs +++ /dev/null @@ -1,72 +0,0 @@ -# frv testcase for maveh $FRi,$FRj,$FRj -# mach: all - - .include "testutils.inc" - - start - - .global maveh -maveh: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - - set_fr_iimmed 0x0001,0x0000,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0001,0x0000,fr12 - - set_fr_iimmed 0x0000,0xffff,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xffff,0xfffe,fr12 - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xef56,0xdf77,fr12 - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xdf77,0xef56,fr12 - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x11a2,0x33c4,fr12 - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x0919,0x2b3b,fr12 - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0x4000,0x3fff,fr12 - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xffff,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xc000,0xbfff,fr12 - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0xfffe,0xfffe,fr11 - maveh fr10,fr11,fr12 - test_fr_limmed 0xbfff,0xbfff,fr12 - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - maveh.p fr10,fr10,fr12 - maveh fr11,fr11,fr13 - test_fr_limmed 0x8000,0x8000,fr12 - test_fr_limmed 0x7fff,0x7fff,fr13 - - pass diff --git a/sim/testsuite/sim/frv/mbtoh.cgs b/sim/testsuite/sim/frv/mbtoh.cgs deleted file mode 100644 index 52895ad4a21..00000000000 --- a/sim/testsuite/sim/frv/mbtoh.cgs +++ /dev/null @@ -1,20 +0,0 @@ -# frv testcase for mbtoh $FRj,$FRk -# mach: all - - .include "testutils.inc" - - start - - .global mbtoh -mbtoh: - set_fr_iimmed 0xdead,0xbeef,fr10 - mbtoh fr10,fr12 - test_fr_limmed 0x00de,0x00ad,fr12 - test_fr_limmed 0x00be,0x00ef,fr13 - - set_fr_iimmed 0x1234,0x5678,fr10 - mbtoh fr10,fr12 - test_fr_limmed 0x0012,0x0034,fr12 - test_fr_limmed 0x0056,0x0078,fr13 - - pass diff --git a/sim/testsuite/sim/frv/mbtohe.cgs b/sim/testsuite/sim/frv/mbtohe.cgs deleted file mode 100644 index 1e978ec59e4..00000000000 --- a/sim/testsuite/sim/frv/mbtohe.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# frv testcase for mbtohe $FRj,$FRk -# mach: frv - - .include "testutils.inc" - - start - - .global mbtohe -mbtohe: - set_fr_iimmed 0xdead,0xbeef,fr10 - mbtohe fr10,fr12 - test_fr_limmed 0x00de,0x00de,fr12 - test_fr_limmed 0x00ad,0x00ad,fr13 - test_fr_limmed 0x00be,0x00be,fr14 - test_fr_limmed 0x00ef,0x00ef,fr15 - - set_fr_iimmed 0x1234,0x5678,fr10 - mbtohe fr10,fr12 - test_fr_limmed 0x0012,0x0012,fr12 - test_fr_limmed 0x0034,0x0034,fr13 - test_fr_limmed 0x0056,0x0056,fr14 - test_fr_limmed 0x0078,0x0078,fr15 - - pass diff --git a/sim/testsuite/sim/frv/mclracc.cgs b/sim/testsuite/sim/frv/mclracc.cgs deleted file mode 100644 index 7972b9a9cfc..00000000000 --- a/sim/testsuite/sim/frv/mclracc.cgs +++ /dev/null @@ -1,79 +0,0 @@ -# frv testcase for mclracc $ACC40k,$A -# mach: frv - - .include "testutils.inc" - - start - - .global mclracc -mclracc: - set_accg_immed 0xff,accg0 - set_acc_immed -1,acc0 - set_accg_immed 0xff,accg8 - set_acc_immed -1,acc8 - set_accg_immed 0xff,accg31 - set_acc_immed -1,acc31 - set_accg_immed 0xff,accg62 - set_acc_immed -1,acc62 - - mclracc acc63,0 ; nop - test_accg_immed 0xff,accg0 - test_acc_immed -1,acc0 - test_accg_immed 0xff,accg8 - test_acc_immed -1,acc8 - test_accg_immed 0xff,accg31 - test_acc_immed -1,acc31 - test_accg_immed 0xff,accg62 - test_acc_immed -1,acc62 - - mclracc acc63,1 ; nop - test_accg_immed 0xff,accg0 - test_acc_immed -1,acc0 - test_accg_immed 0xff,accg8 - test_acc_immed -1,acc8 - test_accg_immed 0xff,accg31 - test_acc_immed -1,acc31 - test_accg_immed 0xff,accg62 - test_acc_immed -1,acc62 - - mclracc acc31,0 - test_accg_immed 0xff,accg0 - test_acc_immed -1,acc0 - test_accg_immed 0xff,accg8 - test_acc_immed -1,acc8 - test_accg_immed 0,accg31 - test_acc_immed 0,acc31 - test_accg_immed 0xff,accg62 - test_acc_immed -1,acc62 - - mclracc acc62,1 - test_accg_immed 0xff,accg0 - test_acc_immed -1,acc0 - test_accg_immed 0xff,accg8 - test_acc_immed -1,acc8 - test_accg_immed 0,accg31 - test_acc_immed 0,acc31 - test_accg_immed 0,accg62 - test_acc_immed 0,acc62 - - mclracc acc0,0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0xff,accg8 - test_acc_immed -1,acc8 - test_accg_immed 0,accg31 - test_acc_immed 0,acc31 - test_accg_immed 0,accg62 - test_acc_immed 0,acc62 - - mclracc acc0,1 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg8 - test_acc_immed 0,acc8 - test_accg_immed 0,accg31 - test_acc_immed 0,acc31 - test_accg_immed 0,accg62 - test_acc_immed 0,acc62 - - pass diff --git a/sim/testsuite/sim/frv/mcmpsh.cgs b/sim/testsuite/sim/frv/mcmpsh.cgs deleted file mode 100644 index 50e986d0406..00000000000 --- a/sim/testsuite/sim/frv/mcmpsh.cgs +++ /dev/null @@ -1,138 +0,0 @@ -# frv testcase for mcmpsh $FRi,$FRj,$FCCk -# mach: all - - .include "testutils.inc" - - start - - .global mcmpsh -mcmpsh: - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - mcmpsh fr10,fr11,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x7fff,0x8000,fr11 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - mcmpsh fr10,fr11,fcc0 - test_fcc 0x8,0 - test_fcc 0x2,1 - - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x7fff,fr11 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - mcmpsh fr10,fr11,fcc0 - test_fcc 0x2,0 - test_fcc 0x8,1 - - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - mcmpsh fr10,fr11,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - - set_fr_iimmed 0x7fff,0x8000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - mcmpsh fr10,fr11,fcc0 - test_fcc 0x8,0 - test_fcc 0x4,1 - - set_fr_iimmed 0x7fff,0x8000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr11 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - mcmpsh fr10,fr11,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - - set_fr_iimmed 0x7fff,0x8000,fr10 - set_fr_iimmed 0x8000,0x7fff,fr11 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - mcmpsh fr10,fr11,fcc0 - test_fcc 0x2,0 - test_fcc 0x4,1 - - set_fr_iimmed 0x7fff,0x8000,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - mcmpsh fr10,fr11,fcc0 - test_fcc 0x2,0 - test_fcc 0x8,1 - - set_fr_iimmed 0x8000,0x7fff,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - mcmpsh fr10,fr11,fcc0 - test_fcc 0x4,0 - test_fcc 0x8,1 - - set_fr_iimmed 0x8000,0x7fff,fr10 - set_fr_iimmed 0x7fff,0x8000,fr11 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - mcmpsh fr10,fr11,fcc0 - test_fcc 0x4,0 - test_fcc 0x2,1 - - set_fr_iimmed 0x8000,0x7fff,fr10 - set_fr_iimmed 0x8000,0x7fff,fr11 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - mcmpsh fr10,fr11,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - - set_fr_iimmed 0x8000,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - mcmpsh fr10,fr11,fcc0 - test_fcc 0x8,0 - test_fcc 0x2,1 - - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - mcmpsh fr10,fr11,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr11 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - mcmpsh fr10,fr11,fcc0 - test_fcc 0x4,0 - test_fcc 0x8,1 - - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0x8000,0x7fff,fr11 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - mcmpsh fr10,fr11,fcc0 - test_fcc 0x8,0 - test_fcc 0x4,1 - - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - mcmpsh fr10,fr11,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - - pass diff --git a/sim/testsuite/sim/frv/mcmpuh.cgs b/sim/testsuite/sim/frv/mcmpuh.cgs deleted file mode 100644 index a6670b736f7..00000000000 --- a/sim/testsuite/sim/frv/mcmpuh.cgs +++ /dev/null @@ -1,138 +0,0 @@ -# frv testcase for mcmpuh $FRi,$FRj,$FCCk -# mach: all - - .include "testutils.inc" - - start - - .global mcmpuh -mcmpuh: - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - mcmpuh fr10,fr11,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x7fff,0x8000,fr11 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - mcmpuh fr10,fr11,fcc0 - test_fcc 0x8,0 - test_fcc 0x4,1 - - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x7fff,fr11 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - mcmpuh fr10,fr11,fcc0 - test_fcc 0x4,0 - test_fcc 0x8,1 - - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - mcmpuh fr10,fr11,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - - set_fr_iimmed 0x7fff,0x8000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - mcmpuh fr10,fr11,fcc0 - test_fcc 0x8,0 - test_fcc 0x2,1 - - set_fr_iimmed 0x7fff,0x8000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr11 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - mcmpuh fr10,fr11,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - - set_fr_iimmed 0x7fff,0x8000,fr10 - set_fr_iimmed 0x8000,0x7fff,fr11 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - mcmpuh fr10,fr11,fcc0 - test_fcc 0x4,0 - test_fcc 0x2,1 - - set_fr_iimmed 0x7fff,0x8000,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - mcmpuh fr10,fr11,fcc0 - test_fcc 0x4,0 - test_fcc 0x8,1 - - set_fr_iimmed 0x8000,0x7fff,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - mcmpuh fr10,fr11,fcc0 - test_fcc 0x2,0 - test_fcc 0x8,1 - - set_fr_iimmed 0x8000,0x7fff,fr10 - set_fr_iimmed 0x7fff,0x8000,fr11 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - mcmpuh fr10,fr11,fcc0 - test_fcc 0x2,0 - test_fcc 0x4,1 - - set_fr_iimmed 0x8000,0x7fff,fr10 - set_fr_iimmed 0x8000,0x7fff,fr11 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - mcmpuh fr10,fr11,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - - set_fr_iimmed 0x8000,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - mcmpuh fr10,fr11,fcc0 - test_fcc 0x8,0 - test_fcc 0x4,1 - - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - mcmpuh fr10,fr11,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr11 - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - mcmpuh fr10,fr11,fcc0 - test_fcc 0x2,0 - test_fcc 0x8,1 - - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0x8000,0x7fff,fr11 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - mcmpuh fr10,fr11,fcc0 - test_fcc 0x8,0 - test_fcc 0x2,1 - - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - mcmpuh fr10,fr11,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - - pass diff --git a/sim/testsuite/sim/frv/mcop1.cgs b/sim/testsuite/sim/frv/mcop1.cgs deleted file mode 100644 index 5405456f51f..00000000000 --- a/sim/testsuite/sim/frv/mcop1.cgs +++ /dev/null @@ -1,40 +0,0 @@ -# frv testcase for mcop1 $FRi,$FRj,$FRk -# mach: frv - - .include "testutils.inc" - - start - - .global mcop1 -mcop1: - mcop1.p fr19,fr12,fr13 ; mp_exception: not-implemented - mcop1 fr20,fr14,fr18 ; mp_exception: not-implemented - test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - mcop1.p fr19,fr12,fr13 ; mp_exception: not-implemented - mcop1 fr20,fr14,fr18 ; mp_exception: not-implemented - test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - mcop1 fr19,fr12,fr13 ; mp_exception: not-implemented - test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - mcop1 fr19,fr12,fr13 ; mp_exception: not-implemented - test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - pass diff --git a/sim/testsuite/sim/frv/mcop2.cgs b/sim/testsuite/sim/frv/mcop2.cgs deleted file mode 100644 index f423a3ef7f7..00000000000 --- a/sim/testsuite/sim/frv/mcop2.cgs +++ /dev/null @@ -1,40 +0,0 @@ -# frv testcase for mcop2 $FRi,$FRj,$FRk -# mach: frv - - .include "testutils.inc" - - start - - .global mcop2 -mcop2: - mcop2.p fr19,fr12,fr13 ; mp_exception: not-implemented - mcop2 fr20,fr14,fr18 ; mp_exception: not-implemented - test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - mcop2.p fr19,fr12,fr13 ; mp_exception: not-implemented - mcop2 fr20,fr14,fr18 ; mp_exception: not-implemented - test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - mcop2 fr19,fr12,fr13 ; mp_exception: not-implemented - test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - mcop2 fr19,fr12,fr13 ; mp_exception: not-implemented - test_spr_bits 0x7000,12,5,msr0; msr0.mtt is set - test_spr_bits 0x003c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 0x0002,1,0,msr0 ; msr0.ovf is clear - test_spr_bits 0x003c,2,0,msr1 ; msr1.sie is clear - test_spr_bits 0x0002,1,0,msr1 ; msr1.ovf is clear - - pass diff --git a/sim/testsuite/sim/frv/mcplhi.cgs b/sim/testsuite/sim/frv/mcplhi.cgs deleted file mode 100644 index d1a52eb637a..00000000000 --- a/sim/testsuite/sim/frv/mcplhi.cgs +++ /dev/null @@ -1,53 +0,0 @@ -# frv testcase for mcplhi $FRi,$s6,$FRk -# mach: fr400 fr550 - - .include "testutils.inc" - - start - - .global mcplhi -mcplhi: - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - mcplhi fr8,0x0,fr10 ; Shift by 0 - test_fr_iimmed 0xdead5678,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcplhi fr8,0x1,fr10 ; Shift by 1 - test_fr_iimmed 0xbd5b5678,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcplhi fr8,0x4,fr10 ; Shift by 4 - test_fr_iimmed 0xeadf5678,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcplhi fr8,0xc,fr10 ; Shift by 12 - test_fr_iimmed 0xdeef5678,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcplhi fr8,0xf,fr10 ; Shift by 15 - test_fr_iimmed 0xbeef5678,fr10 - - ; test again with truncated shift values - set_fr_iimmed 0x1234,0x5678,fr10 - mcplhi fr8,0x10,fr10 ; Shift by 0 - test_fr_iimmed 0xdead5678,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcplhi fr8,0x21,fr10 ; Shift by 1 - test_fr_iimmed 0xbd5b5678,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcplhi fr8,0x34,fr10 ; Shift by 4 - test_fr_iimmed 0xeadf5678,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcplhi fr8,0x1c,fr10 ; Shift by 12 - test_fr_iimmed 0xdeef5678,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcplhi fr8,0x2f,fr10 ; Shift by 15 - test_fr_iimmed 0xbeef5678,fr10 - - pass diff --git a/sim/testsuite/sim/frv/mcpli.cgs b/sim/testsuite/sim/frv/mcpli.cgs deleted file mode 100644 index b63ec67a733..00000000000 --- a/sim/testsuite/sim/frv/mcpli.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for mcpli $FRi,$s6,$FRk -# mach: fr400 fr550 - - .include "testutils.inc" - - start - - .global mcpli -mcpli: - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - mcpli fr8,0x0,fr10 ; Shift by 0 - test_fr_iimmed 0xdeadbeef,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcpli fr8,0x1,fr10 ; Shift by 1 - test_fr_iimmed 0xbd5b7ddf,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcpli fr8,0x4,fr10 ; Shift by 4 - test_fr_iimmed 0xeadbeefd,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcpli fr8,0xc,fr10 ; Shift by 12 - test_fr_iimmed 0xdbeefead,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcpli fr8,0x1c,fr10 ; Shift by 28 - test_fr_iimmed 0xfeefdead,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcpli fr8,0x1f,fr10 ; Shift by 31 - test_fr_iimmed 0xbeefdead,fr10 - - ; test again with truncated shift values - set_fr_iimmed 0x1234,0x5678,fr10 - mcpli fr8,0x20,fr10 ; Shift by 0 - test_fr_iimmed 0xdeadbeef,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcpli fr8,0x21,fr10 ; Shift by 1 - test_fr_iimmed 0xbd5b7ddf,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcpli fr8,0x24,fr10 ; Shift by 4 - test_fr_iimmed 0xeadbeefd,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcpli fr8,0x2c,fr10 ; Shift by 12 - test_fr_iimmed 0xdbeefead,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcpli fr8,0x3c,fr10 ; Shift by 28 - test_fr_iimmed 0xfeefdead,fr10 - - set_fr_iimmed 0x1234,0x5678,fr10 - mcpli fr8,0x3f,fr10 ; Shift by 31 - test_fr_iimmed 0xbeefdead,fr10 - - pass diff --git a/sim/testsuite/sim/frv/mcpxis.cgs b/sim/testsuite/sim/frv/mcpxis.cgs deleted file mode 100644 index c3dad019c90..00000000000 --- a/sim/testsuite/sim/frv/mcpxis.cgs +++ /dev/null @@ -1,115 +0,0 @@ -# frv testcase for mcpxis $GRi,$GRj,$ACCk -# mach: all - - .include "testutils.inc" - - start - - .global mcpxis -mcpxis: - ; Positive operands - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0x00,accg0 - test_acc_immed 26,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 3,acc0 - - set_fr_iimmed 0x3ff8,2,fr7 ; 15 bit result - set_fr_iimmed 0x0007,2,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0,0x7ffe,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 0x2000,2,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0xc000,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x0001,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 1,0xfffd,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -9,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -6,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0xfffe,1,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -2,acc0 - - set_fr_iimmed 0x2001,0xffff,fr7 ; 15 bit result - set_fr_iimmed 0xffff,0xfffe,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbfff,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0x0003,0xfffe,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x7ffa,acc0 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0x8001,0x0000,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x8000,0x0000,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffb,0xfffd,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0x00,accg0 - test_acc_immed 26,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 3,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x7fff,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - mcpxis fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x40000000,acc0 - - pass diff --git a/sim/testsuite/sim/frv/mcpxiu.cgs b/sim/testsuite/sim/frv/mcpxiu.cgs deleted file mode 100644 index 198f0568c40..00000000000 --- a/sim/testsuite/sim/frv/mcpxiu.cgs +++ /dev/null @@ -1,76 +0,0 @@ -# frv testcase for mcpxiu $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global mcpxiu -mcpxiu: - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - mcpxiu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 26,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 1,3,fr8 - mcpxiu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 5,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - mcpxiu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 0x0001,2,fr8 - mcpxiu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x7fff,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 0x0001,2,fr8 - mcpxiu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8001,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 17 bit result - set_fr_iimmed 0x0001,4,fr8 - mcpxiu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x00010001,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - mcpxiu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x0000,0x8000,fr8 - mcpxiu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0000,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - mcpxiu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; almost max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - mcpxiu fr7,fr8,acc0 - test_accg_immed 1,accg0 - test_acc_immed 0xfffb0003,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - mcpxiu fr7,fr8,acc0 - test_accg_immed 1,accg0 - test_acc_immed 0xfffc0002,acc0 - - pass diff --git a/sim/testsuite/sim/frv/mcpxrs.cgs b/sim/testsuite/sim/frv/mcpxrs.cgs deleted file mode 100644 index 1d62a96e7dc..00000000000 --- a/sim/testsuite/sim/frv/mcpxrs.cgs +++ /dev/null @@ -1,115 +0,0 @@ -# frv testcase for mcpxrs $GRi,$GRj,$ACCk -# mach: all - - .include "testutils.inc" - - start - - .global mcpxrs -mcpxrs: - ; Positive operands - set_fr_iimmed 2,4,fr7 ; multiply small numbers - set_fr_iimmed 3,5,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -14,acc0 - - set_fr_iimmed 3,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,1,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 1,acc0 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x0007,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0,0x7ff0,acc0 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x2000,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x4000,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x0001,acc0 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,1,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -3,acc0 - - set_fr_iimmed 0xfffe,2,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 1,0xfffe,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -2,acc0 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0xfff9,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbff0,acc0 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x0003,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x8006,acc0 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0x8000,0x8000,acc0 - - set_fr_iimmed 0x8000,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x7fff,0x8000,acc0 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffc,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffb,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -14,acc0 - - set_fr_iimmed 0xffff,0xffff,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 1,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; almost max positive result - set_fr_iimmed 0x7fff,0x8001,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - - set_fr_iimmed 0x8000,0x0000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - mcpxrs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x40000000,acc0 - - pass diff --git a/sim/testsuite/sim/frv/mcpxru.cgs b/sim/testsuite/sim/frv/mcpxru.cgs deleted file mode 100644 index 8a543926e69..00000000000 --- a/sim/testsuite/sim/frv/mcpxru.cgs +++ /dev/null @@ -1,94 +0,0 @@ -# frv testcase for mcpxru $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global mcpxru -mcpxru: - set_fr_iimmed 4,2,fr7 ; multiply small numbers - set_fr_iimmed 5,3,fr8 - mcpxru fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 14,acc0 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 3,1,fr8 - mcpxru fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 1,acc0 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - mcpxru fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0x3fff,1,fr7 ; 15 bit result - set_fr_iimmed 2,0x0001,fr8 - mcpxru fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x7ffd,acc0 - - set_fr_iimmed 0x4000,1,fr7 ; 16 bit result - set_fr_iimmed 4,0x0001,fr8 - mcpxru fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0xffff,acc0 - - set_fr_iimmed 0x8000,1,fr7 ; 17 bit result - set_fr_iimmed 4,0x0001,fr8 - mcpxru fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x0001ffff,acc0 - - set_fr_iimmed 0x7fff,0x0000,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - mcpxru fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x0000,fr8 - mcpxru fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0000,acc0 - - set_fr_iimmed 0xffff,0x0000,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - mcpxru fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - - set_fr_iimmed 0x0000,0x0001,fr7 ; saturation - set_fr_iimmed 0xffff,0x0001,fr8 - mcpxru fr7,fr8,acc0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0x0000,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - mcpxru fr7,fr8,acc0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0xfffe,0xffff,fr7 ; saturation - set_fr_iimmed 0xffff,0xffff,fr8 - mcpxru fr7,fr8,acc0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - - pass diff --git a/sim/testsuite/sim/frv/mcut.cgs b/sim/testsuite/sim/frv/mcut.cgs deleted file mode 100644 index d6211ab7593..00000000000 --- a/sim/testsuite/sim/frv/mcut.cgs +++ /dev/null @@ -1,509 +0,0 @@ -# frv testcase for mcut $ACC40i,$FRj,$FRk -# mach: all - - .include "testutils.inc" - - start - - .global mcut -mcut: - set_accg_immed 0xffffffe7,accg0 - set_acc_immed 0x89abcdef,acc0 - - set_fr_iimmed 0,0,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xe789abcd,fr11 - - set_fr_iimmed 0,1,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xcf13579b,fr11 - - set_fr_iimmed 0,2,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x9e26af37,fr11 - - set_fr_iimmed 0,3,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x3c4d5e6f,fr11 - - set_fr_iimmed 0,4,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x789abcde,fr11 - - set_fr_iimmed 0,5,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xf13579bd,fr11 - - set_fr_iimmed 0,6,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xe26af37b,fr11 - - set_fr_iimmed 0,7,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xc4d5e6f7,fr11 - - set_fr_iimmed 0,8,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x89abcdef,fr11 - - set_fr_iimmed 0,9,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x13579bde,fr11 - - set_fr_iimmed 0,10,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x26af37bc,fr11 - - set_fr_iimmed 0,11,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x4d5e6f78,fr11 - - set_fr_iimmed 0,12,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x9abcdef0,fr11 - - set_fr_iimmed 0,13,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x3579bde0,fr11 - - set_fr_iimmed 0,14,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x6af37bc0,fr11 - - set_fr_iimmed 0,15,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xd5e6f780,fr11 - - set_fr_iimmed 0,16,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xabcdef00,fr11 - - set_fr_iimmed 0,17,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x579bde00,fr11 - - set_fr_iimmed 0,18,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xaf37bc00,fr11 - - set_fr_iimmed 0,19,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x5e6f7800,fr11 - - set_fr_iimmed 0,20,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xbcdef000,fr11 - - set_fr_iimmed 0,21,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x79bde000,fr11 - - set_fr_iimmed 0,22,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xf37bc000,fr11 - - set_fr_iimmed 0,23,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xe6f78000,fr11 - - set_fr_iimmed 0,24,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xcdef0000,fr11 - - set_fr_iimmed 0,25,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x9bde0000,fr11 - - set_fr_iimmed 0,26,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x37bc0000,fr11 - - set_fr_iimmed 0,27,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x6f780000,fr11 - - set_fr_iimmed 0,28,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xdef00000,fr11 - - set_fr_iimmed 0,29,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xbde00000,fr11 - - set_fr_iimmed 0,30,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x7bc00000,fr11 - - set_fr_iimmed 0,31,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xf7800000,fr11 - - set_fr_iimmed 0,31,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xf7800000,fr11 - - set_fr_iimmed 0,64,fr10 ; same as 0 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xe789abcd,fr11 - - set_fr_iimmed 0xffff,0xffff,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xf3c4d5e6,fr11 - - set_fr_iimmed 0x0000,0x003e,fr10 ; only lower 6 bits matter - mcut acc0,fr10,fr11 - test_fr_iimmed 0xf9e26af3,fr11 - - set_fr_iimmed 0xffff,0xfffd,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xfcf13579,fr11 - - set_fr_iimmed 0xffff,0xfffc,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xfe789abc,fr11 - - set_fr_iimmed 0xffff,0xfffb,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xff3c4d5e,fr11 - - set_fr_iimmed 0xffff,0xfffa,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xff9e26af,fr11 - - set_fr_iimmed 0xffff,0xfff9,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xffcf1357,fr11 - - set_fr_iimmed 0xffff,0xfff8,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xffe789ab,fr11 - - set_fr_iimmed 0xffff,0xfff7,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xfff3c4d5,fr11 - - set_fr_iimmed 0xffff,0xfff6,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xfff9e26a,fr11 - - set_fr_iimmed 0xffff,0xfff5,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xfffcf135,fr11 - - set_fr_iimmed 0xffff,0xfff4,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xfffe789a,fr11 - - set_fr_iimmed 0xffff,0xfff3,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xffff3c4d,fr11 - - set_fr_iimmed 0xffff,0xfff2,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xffff9e26,fr11 - - set_fr_iimmed 0xffff,0xfff1,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xffffcf13,fr11 - - set_fr_iimmed 0xffff,0xfff0,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xffffe789,fr11 - - set_fr_iimmed 0xffff,0xffef,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xfffff3c4,fr11 - - set_fr_iimmed 0xffff,0xffee,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xfffff9e2,fr11 - - set_fr_iimmed 0xffff,0xffed,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xfffffcf1,fr11 - - set_fr_iimmed 0xffff,0xffec,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xfffffe78,fr11 - - set_fr_iimmed 0xffff,0xffeb,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xffffff3c,fr11 - - set_fr_iimmed 0xffff,0xffea,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xffffff9e,fr11 - - set_fr_iimmed 0xffff,0xffe9,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xffffffcf,fr11 - - set_fr_iimmed 0xffff,0xffe8,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xffffffe7,fr11 - - set_fr_iimmed 0xffff,0xffe7,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xfffffff3,fr11 - - set_fr_iimmed 0xffff,0xffe6,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xfffffff9,fr11 - - set_fr_iimmed 0xffff,0xffe5,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xfffffffc,fr11 - - set_fr_iimmed 0xffff,0xffe4,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xfffffffe,fr11 - - set_fr_iimmed 0xffff,0xffe3,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xffffffff,fr11 - - set_fr_iimmed 0xffff,0xffe2,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xffffffff,fr11 - - set_fr_iimmed 0xffff,0xffe1,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xffffffff,fr11 - - set_fr_iimmed 0xffff,0xffe0,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xffffffff,fr11 - - set_fr_iimmed 0,32,fr10 ; same as -32 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xffffffff,fr11 - - set_accg_immed 0xffffff67,accg0 - set_acc_immed 0x89abcdef,acc0 - - set_fr_iimmed 0xffff,0xffff,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x33c4d5e6,fr11 - - set_fr_iimmed 0x0000,0x003e,fr10 ; only lower 6 bits matter - mcut acc0,fr10,fr11 - test_fr_iimmed 0x19e26af3,fr11 - - set_fr_iimmed 0xffff,0xfffd,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x0cf13579,fr11 - - set_fr_iimmed 0xffff,0xfffc,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x06789abc,fr11 - - set_fr_iimmed 0xffff,0xfffb,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x033c4d5e,fr11 - - set_fr_iimmed 0xffff,0xfffa,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x019e26af,fr11 - - set_fr_iimmed 0xffff,0xfff9,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x00cf1357,fr11 - - set_fr_iimmed 0xffff,0xfff8,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x006789ab,fr11 - - set_fr_iimmed 0xffff,0xfff7,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x0033c4d5,fr11 - - set_fr_iimmed 0xffff,0xfff6,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x0019e26a,fr11 - - set_fr_iimmed 0xffff,0xfff5,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x000cf135,fr11 - - set_fr_iimmed 0xffff,0xfff4,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x0006789a,fr11 - - set_fr_iimmed 0xffff,0xfff3,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x00033c4d,fr11 - - set_fr_iimmed 0xffff,0xfff2,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x00019e26,fr11 - - set_fr_iimmed 0xffff,0xfff1,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x0000cf13,fr11 - - set_fr_iimmed 0xffff,0xfff0,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x00006789,fr11 - - set_fr_iimmed 0xffff,0xffef,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x000033c4,fr11 - - set_fr_iimmed 0xffff,0xffee,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x000019e2,fr11 - - set_fr_iimmed 0xffff,0xffed,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x00000cf1,fr11 - - set_fr_iimmed 0xffff,0xffec,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x00000678,fr11 - - set_fr_iimmed 0xffff,0xffeb,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x0000033c,fr11 - - set_fr_iimmed 0xffff,0xffea,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x0000019e,fr11 - - set_fr_iimmed 0xffff,0xffe9,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x000000cf,fr11 - - set_fr_iimmed 0xffff,0xffe8,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x00000067,fr11 - - set_fr_iimmed 0xffff,0xffe7,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x00000033,fr11 - - set_fr_iimmed 0xffff,0xffe6,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x00000019,fr11 - - set_fr_iimmed 0xffff,0xffe5,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x0000000c,fr11 - - set_fr_iimmed 0xffff,0xffe4,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x00000006,fr11 - - set_fr_iimmed 0xffff,0xffe3,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x00000003,fr11 - - set_fr_iimmed 0xffff,0xffe2,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x00000001,fr11 - - set_fr_iimmed 0xffff,0xffe1,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x00000000,fr11 - - set_fr_iimmed 0xffff,0xffe0,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x00000000,fr11 - - set_fr_iimmed 0,32,fr10 ; same as -32 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x00000000,fr11 - - ; Examples from the customer - set_accg_immed 0xffffffff,accg0 - set_acc_immed 0xffe00000,acc0 - - set_fr_iimmed 0,16,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xe0000000,fr11 - - set_fr_iimmed 0,17,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xc0000000,fr11 - - set_fr_iimmed 0,18,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_accg_immed 0,accg0 - set_acc_immed 0x003fffff,acc0 - - set_fr_iimmed 0,16,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x3fffff00,fr11 - - set_fr_iimmed 0,17,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x7ffffe00,fr11 - - set_accg_immed 0x7f,accg0 - set_acc_immed 0xffe00000,acc0 - - set_fr_iimmed 0,16,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xe0000000,fr11 - - set_fr_iimmed 0,17,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xc0000000,fr11 - - set_fr_iimmed 0,18,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_accg_immed 0x08,accg0 - set_acc_immed 0x003fffff,acc0 - - set_fr_iimmed 0,16,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x3fffff00,fr11 - - set_fr_iimmed 0,17,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x7ffffe00,fr11 - - set_accg_immed 0xff,accg0 - set_acc_immed 0xefe00000,acc0 - - set_fr_iimmed 0,16,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xe0000000,fr11 - - set_fr_iimmed 0,17,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xc0000000,fr11 - - set_fr_iimmed 0,18,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_accg_immed 0x80,accg0 - set_acc_immed 0x003fffff,acc0 - - set_fr_iimmed 0,16,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x3fffff00,fr11 - - set_fr_iimmed 0,17,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x7ffffe00,fr11 - - set_accg_immed 0xffffffaf,accg0 - set_acc_immed 0x5a5a5a5a,acc0 - - set_fr_iimmed 0xffff,0xfffc,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0xfaf5a5a5,fr11 - - set_accg_immed 0x0000002f,accg0 - set_acc_immed 0x5a5a5a5a,acc0 - - set_fr_iimmed 0xffff,0xfff9,fr10 - mcut acc0,fr10,fr11 - test_fr_iimmed 0x005eb4b4,fr11 - - pass diff --git a/sim/testsuite/sim/frv/mcuti.cgs b/sim/testsuite/sim/frv/mcuti.cgs deleted file mode 100644 index e2e702fd79d..00000000000 --- a/sim/testsuite/sim/frv/mcuti.cgs +++ /dev/null @@ -1,381 +0,0 @@ -# frv testcase for mcuti $ACC40i,$s6,$FRk -# mach: all - - .include "testutils.inc" - - start - - .global mcuti -mcuti: - set_accg_immed 0xffffffe7,accg0 - set_acc_immed 0x89abcdef,acc0 - - mcuti acc0,0,fr11 - test_fr_iimmed 0xe789abcd,fr11 - - mcuti acc0,1,fr11 - test_fr_iimmed 0xcf13579b,fr11 - - mcuti acc0,2,fr11 - test_fr_iimmed 0x9e26af37,fr11 - - set_fr_iimmed 0,3,fr10 - mcuti acc0,3,fr11 - test_fr_iimmed 0x3c4d5e6f,fr11 - - mcuti acc0,4,fr11 - test_fr_iimmed 0x789abcde,fr11 - - mcuti acc0,5,fr11 - test_fr_iimmed 0xf13579bd,fr11 - - mcuti acc0,6,fr11 - test_fr_iimmed 0xe26af37b,fr11 - - mcuti acc0,7,fr11 - test_fr_iimmed 0xc4d5e6f7,fr11 - - mcuti acc0,8,fr11 - test_fr_iimmed 0x89abcdef,fr11 - - mcuti acc0,9,fr11 - test_fr_iimmed 0x13579bde,fr11 - - mcuti acc0,10,fr11 - test_fr_iimmed 0x26af37bc,fr11 - - mcuti acc0,11,fr11 - test_fr_iimmed 0x4d5e6f78,fr11 - - mcuti acc0,12,fr11 - test_fr_iimmed 0x9abcdef0,fr11 - - mcuti acc0,13,fr11 - test_fr_iimmed 0x3579bde0,fr11 - - mcuti acc0,14,fr11 - test_fr_iimmed 0x6af37bc0,fr11 - - mcuti acc0,15,fr11 - test_fr_iimmed 0xd5e6f780,fr11 - - mcuti acc0,16,fr11 - test_fr_iimmed 0xabcdef00,fr11 - - mcuti acc0,17,fr11 - test_fr_iimmed 0x579bde00,fr11 - - mcuti acc0,18,fr11 - test_fr_iimmed 0xaf37bc00,fr11 - - mcuti acc0,19,fr11 - test_fr_iimmed 0x5e6f7800,fr11 - - mcuti acc0,20,fr11 - test_fr_iimmed 0xbcdef000,fr11 - - mcuti acc0,21,fr11 - test_fr_iimmed 0x79bde000,fr11 - - mcuti acc0,22,fr11 - test_fr_iimmed 0xf37bc000,fr11 - - mcuti acc0,23,fr11 - test_fr_iimmed 0xe6f78000,fr11 - - mcuti acc0,24,fr11 - test_fr_iimmed 0xcdef0000,fr11 - - mcuti acc0,25,fr11 - test_fr_iimmed 0x9bde0000,fr11 - - mcuti acc0,26,fr11 - test_fr_iimmed 0x37bc0000,fr11 - - mcuti acc0,27,fr11 - test_fr_iimmed 0x6f780000,fr11 - - mcuti acc0,28,fr11 - test_fr_iimmed 0xdef00000,fr11 - - mcuti acc0,29,fr11 - test_fr_iimmed 0xbde00000,fr11 - - mcuti acc0,30,fr11 - test_fr_iimmed 0x7bc00000,fr11 - - mcuti acc0,31,fr11 - test_fr_iimmed 0xf7800000,fr11 - - mcuti acc0,-1,fr11 - test_fr_iimmed 0xf3c4d5e6,fr11 - - mcuti acc0,-2,fr11 - test_fr_iimmed 0xf9e26af3,fr11 - - mcuti acc0,-3,fr11 - test_fr_iimmed 0xfcf13579,fr11 - - mcuti acc0,-4,fr11 - test_fr_iimmed 0xfe789abc,fr11 - - mcuti acc0,-5,fr11 - test_fr_iimmed 0xff3c4d5e,fr11 - - mcuti acc0,-6,fr11 - test_fr_iimmed 0xff9e26af,fr11 - - mcuti acc0,-7,fr11 - test_fr_iimmed 0xffcf1357,fr11 - - mcuti acc0,-8,fr11 - test_fr_iimmed 0xffe789ab,fr11 - - mcuti acc0,-9,fr11 - test_fr_iimmed 0xfff3c4d5,fr11 - - mcuti acc0,-10,fr11 - test_fr_iimmed 0xfff9e26a,fr11 - - mcuti acc0,-11,fr11 - test_fr_iimmed 0xfffcf135,fr11 - - mcuti acc0,-12,fr11 - test_fr_iimmed 0xfffe789a,fr11 - - mcuti acc0,-13,fr11 - test_fr_iimmed 0xffff3c4d,fr11 - - mcuti acc0,-14,fr11 - test_fr_iimmed 0xffff9e26,fr11 - - mcuti acc0,-15,fr11 - test_fr_iimmed 0xffffcf13,fr11 - - mcuti acc0,-16,fr11 - test_fr_iimmed 0xffffe789,fr11 - - mcuti acc0,-17,fr11 - test_fr_iimmed 0xfffff3c4,fr11 - - mcuti acc0,-18,fr11 - test_fr_iimmed 0xfffff9e2,fr11 - - mcuti acc0,-19,fr11 - test_fr_iimmed 0xfffffcf1,fr11 - - mcuti acc0,-20,fr11 - test_fr_iimmed 0xfffffe78,fr11 - - mcuti acc0,-21,fr11 - test_fr_iimmed 0xffffff3c,fr11 - - mcuti acc0,-22,fr11 - test_fr_iimmed 0xffffff9e,fr11 - - mcuti acc0,-23,fr11 - test_fr_iimmed 0xffffffcf,fr11 - - mcuti acc0,-24,fr11 - test_fr_iimmed 0xffffffe7,fr11 - - mcuti acc0,-25,fr11 - test_fr_iimmed 0xfffffff3,fr11 - - mcuti acc0,-26,fr11 - test_fr_iimmed 0xfffffff9,fr11 - - mcuti acc0,-27,fr11 - test_fr_iimmed 0xfffffffc,fr11 - - mcuti acc0,-28,fr11 - test_fr_iimmed 0xfffffffe,fr11 - - mcuti acc0,-29,fr11 - test_fr_iimmed 0xffffffff,fr11 - - mcuti acc0,-30,fr11 - test_fr_iimmed 0xffffffff,fr11 - - mcuti acc0,-31,fr11 - test_fr_iimmed 0xffffffff,fr11 - - mcuti acc0,-32,fr11 - test_fr_iimmed 0xffffffff,fr11 - - set_accg_immed 0xffffff67,accg0 - set_acc_immed 0x89abcdef,acc0 - - mcuti acc0,-1,fr11 - test_fr_iimmed 0x33c4d5e6,fr11 - - mcuti acc0,-2,fr11 - test_fr_iimmed 0x19e26af3,fr11 - - mcuti acc0,-3,fr11 - test_fr_iimmed 0x0cf13579,fr11 - - mcuti acc0,-4,fr11 - test_fr_iimmed 0x06789abc,fr11 - - mcuti acc0,-5,fr11 - test_fr_iimmed 0x033c4d5e,fr11 - - mcuti acc0,-6,fr11 - test_fr_iimmed 0x019e26af,fr11 - - mcuti acc0,-7,fr11 - test_fr_iimmed 0x00cf1357,fr11 - - mcuti acc0,-8,fr11 - test_fr_iimmed 0x006789ab,fr11 - - mcuti acc0,-9,fr11 - test_fr_iimmed 0x0033c4d5,fr11 - - mcuti acc0,-10,fr11 - test_fr_iimmed 0x0019e26a,fr11 - - mcuti acc0,-11,fr11 - test_fr_iimmed 0x000cf135,fr11 - - mcuti acc0,-12,fr11 - test_fr_iimmed 0x0006789a,fr11 - - mcuti acc0,-13,fr11 - test_fr_iimmed 0x00033c4d,fr11 - - mcuti acc0,-14,fr11 - test_fr_iimmed 0x00019e26,fr11 - - mcuti acc0,-15,fr11 - test_fr_iimmed 0x0000cf13,fr11 - - mcuti acc0,-16,fr11 - test_fr_iimmed 0x00006789,fr11 - - mcuti acc0,-17,fr11 - test_fr_iimmed 0x000033c4,fr11 - - mcuti acc0,-18,fr11 - test_fr_iimmed 0x000019e2,fr11 - - mcuti acc0,-19,fr11 - test_fr_iimmed 0x00000cf1,fr11 - - mcuti acc0,-20,fr11 - test_fr_iimmed 0x00000678,fr11 - - mcuti acc0,-21,fr11 - test_fr_iimmed 0x0000033c,fr11 - - mcuti acc0,-22,fr11 - test_fr_iimmed 0x0000019e,fr11 - - mcuti acc0,-23,fr11 - test_fr_iimmed 0x000000cf,fr11 - - mcuti acc0,-24,fr11 - test_fr_iimmed 0x00000067,fr11 - - mcuti acc0,-25,fr11 - test_fr_iimmed 0x00000033,fr11 - - mcuti acc0,-26,fr11 - test_fr_iimmed 0x00000019,fr11 - - mcuti acc0,-27,fr11 - test_fr_iimmed 0x0000000c,fr11 - - mcuti acc0,-28,fr11 - test_fr_iimmed 0x00000006,fr11 - - mcuti acc0,-29,fr11 - test_fr_iimmed 0x00000003,fr11 - - mcuti acc0,-30,fr11 - test_fr_iimmed 0x00000001,fr11 - - mcuti acc0,-31,fr11 - test_fr_iimmed 0x00000000,fr11 - - mcuti acc0,-32,fr11 - test_fr_iimmed 0x00000000,fr11 - - ; Examples from the customer - set_accg_immed 0xffffffff,accg0 - set_acc_immed 0xffe00000,acc0 - - mcuti acc0,16,fr11 - test_fr_iimmed 0xe0000000,fr11 - - mcuti acc0,17,fr11 - test_fr_iimmed 0xc0000000,fr11 - - mcuti acc0,18,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_accg_immed 0,accg0 - set_acc_immed 0x003fffff,acc0 - - mcuti acc0,16,fr11 - test_fr_iimmed 0x3fffff00,fr11 - - mcuti acc0,17,fr11 - test_fr_iimmed 0x7ffffe00,fr11 - - set_accg_immed 0x7f,accg0 - set_acc_immed 0xffe00000,acc0 - - mcuti acc0,16,fr11 - test_fr_iimmed 0xe0000000,fr11 - - mcuti acc0,17,fr11 - test_fr_iimmed 0xc0000000,fr11 - - mcuti acc0,18,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_accg_immed 0x08,accg0 - set_acc_immed 0x003fffff,acc0 - - mcuti acc0,16,fr11 - test_fr_iimmed 0x3fffff00,fr11 - - mcuti acc0,17,fr11 - test_fr_iimmed 0x7ffffe00,fr11 - - set_accg_immed 0xff,accg0 - set_acc_immed 0xefe00000,acc0 - - mcuti acc0,16,fr11 - test_fr_iimmed 0xe0000000,fr11 - - mcuti acc0,17,fr11 - test_fr_iimmed 0xc0000000,fr11 - - mcuti acc0,18,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_accg_immed 0x80,accg0 - set_acc_immed 0x003fffff,acc0 - - mcuti acc0,16,fr11 - test_fr_iimmed 0x3fffff00,fr11 - - mcuti acc0,17,fr11 - test_fr_iimmed 0x7ffffe00,fr11 - - set_accg_immed 0xffffffaf,accg0 - set_acc_immed 0x5a5a5a5a,acc0 - - mcuti acc0,-4,fr11 - test_fr_iimmed 0xfaf5a5a5,fr11 - - set_accg_immed 0x0000002f,accg0 - set_acc_immed 0x5a5a5a5a,acc0 - - mcuti acc0,-7,fr11 - test_fr_iimmed 0x005eb4b4,fr11 - - pass diff --git a/sim/testsuite/sim/frv/mcutss.cgs b/sim/testsuite/sim/frv/mcutss.cgs deleted file mode 100644 index efe3278864c..00000000000 --- a/sim/testsuite/sim/frv/mcutss.cgs +++ /dev/null @@ -1,505 +0,0 @@ -# frv testcase for mcutss $ACC40i,$FRj,$FRk -# mach: all - - .include "testutils.inc" - - start - - .global mcutss -mcutss: - set_accg_immed 0xffffffe7,accg0 - set_acc_immed 0x89abcdef,acc0 - - set_fr_iimmed 0,0,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xe789abcd,fr11 - - set_fr_iimmed 0,1,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xcf13579b,fr11 - - set_fr_iimmed 0,2,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x9e26af37,fr11 - - set_fr_iimmed 0,3,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,4,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,5,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,6,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,7,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,8,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,9,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,10,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,11,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,12,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,13,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,14,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,15,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,16,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,17,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,18,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,19,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,20,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,21,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,22,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,23,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,24,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,25,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,26,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,27,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,28,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,29,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,30,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,31,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_fr_iimmed 0,64,fr10 ; same as 0 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xe789abcd,fr11 - - set_fr_iimmed 0xffff,0xffff,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xf3c4d5e6,fr11 - - set_fr_iimmed 0x0000,0x003e,fr10 ; only lower 6 bits matter - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xf9e26af3,fr11 - - set_fr_iimmed 0xffff,0xfffd,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xfcf13579,fr11 - - set_fr_iimmed 0xffff,0xfffc,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xfe789abc,fr11 - - set_fr_iimmed 0xffff,0xfffb,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xff3c4d5e,fr11 - - set_fr_iimmed 0xffff,0xfffa,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xff9e26af,fr11 - - set_fr_iimmed 0xffff,0xfff9,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xffcf1357,fr11 - - set_fr_iimmed 0xffff,0xfff8,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xffe789ab,fr11 - - set_fr_iimmed 0xffff,0xfff7,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xfff3c4d5,fr11 - - set_fr_iimmed 0xffff,0xfff6,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xfff9e26a,fr11 - - set_fr_iimmed 0xffff,0xfff5,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xfffcf135,fr11 - - set_fr_iimmed 0xffff,0xfff4,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xfffe789a,fr11 - - set_fr_iimmed 0xffff,0xfff3,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xffff3c4d,fr11 - - set_fr_iimmed 0xffff,0xfff2,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xffff9e26,fr11 - - set_fr_iimmed 0xffff,0xfff1,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xffffcf13,fr11 - - set_fr_iimmed 0xffff,0xfff0,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xffffe789,fr11 - - set_fr_iimmed 0xffff,0xffef,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xfffff3c4,fr11 - - set_fr_iimmed 0xffff,0xffee,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xfffff9e2,fr11 - - set_fr_iimmed 0xffff,0xffed,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xfffffcf1,fr11 - - set_fr_iimmed 0xffff,0xffec,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xfffffe78,fr11 - - set_fr_iimmed 0xffff,0xffeb,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xffffff3c,fr11 - - set_fr_iimmed 0xffff,0xffea,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xffffff9e,fr11 - - set_fr_iimmed 0xffff,0xffe9,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xffffffcf,fr11 - - set_fr_iimmed 0xffff,0xffe8,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xffffffe7,fr11 - - set_fr_iimmed 0xffff,0xffe7,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xfffffff3,fr11 - - set_fr_iimmed 0xffff,0xffe6,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xfffffff9,fr11 - - set_fr_iimmed 0xffff,0xffe5,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xfffffffc,fr11 - - set_fr_iimmed 0xffff,0xffe4,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xfffffffe,fr11 - - set_fr_iimmed 0xffff,0xffe3,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xffffffff,fr11 - - set_fr_iimmed 0xffff,0xffe2,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xffffffff,fr11 - - set_fr_iimmed 0xffff,0xffe1,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xffffffff,fr11 - - set_fr_iimmed 0xffff,0xffe0,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xffffffff,fr11 - - set_fr_iimmed 0,32,fr10 ; same as -32 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xffffffff,fr11 - - set_accg_immed 0xffffff67,accg0 - set_acc_immed 0x89abcdef,acc0 - - set_fr_iimmed 0xffff,0xffff,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x33c4d5e6,fr11 - - set_fr_iimmed 0x0000,0x003e,fr10 ; only lower 6 bits matter - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x19e26af3,fr11 - - set_fr_iimmed 0xffff,0xfffd,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x0cf13579,fr11 - - set_fr_iimmed 0xffff,0xfffc,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x06789abc,fr11 - - set_fr_iimmed 0xffff,0xfffb,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x033c4d5e,fr11 - - set_fr_iimmed 0xffff,0xfffa,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x019e26af,fr11 - - set_fr_iimmed 0xffff,0xfff9,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x00cf1357,fr11 - - set_fr_iimmed 0xffff,0xfff8,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x006789ab,fr11 - - set_fr_iimmed 0xffff,0xfff7,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x0033c4d5,fr11 - - set_fr_iimmed 0xffff,0xfff6,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x0019e26a,fr11 - - set_fr_iimmed 0xffff,0xfff5,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x000cf135,fr11 - - set_fr_iimmed 0xffff,0xfff4,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x0006789a,fr11 - - set_fr_iimmed 0xffff,0xfff3,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x00033c4d,fr11 - - set_fr_iimmed 0xffff,0xfff2,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x00019e26,fr11 - - set_fr_iimmed 0xffff,0xfff1,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x0000cf13,fr11 - - set_fr_iimmed 0xffff,0xfff0,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x00006789,fr11 - - set_fr_iimmed 0xffff,0xffef,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x000033c4,fr11 - - set_fr_iimmed 0xffff,0xffee,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x000019e2,fr11 - - set_fr_iimmed 0xffff,0xffed,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x00000cf1,fr11 - - set_fr_iimmed 0xffff,0xffec,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x00000678,fr11 - - set_fr_iimmed 0xffff,0xffeb,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x0000033c,fr11 - - set_fr_iimmed 0xffff,0xffea,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x0000019e,fr11 - - set_fr_iimmed 0xffff,0xffe9,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x000000cf,fr11 - - set_fr_iimmed 0xffff,0xffe8,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x00000067,fr11 - - set_fr_iimmed 0xffff,0xffe7,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x00000033,fr11 - - set_fr_iimmed 0xffff,0xffe6,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x00000019,fr11 - - set_fr_iimmed 0xffff,0xffe5,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x0000000c,fr11 - - set_fr_iimmed 0xffff,0xffe4,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x00000006,fr11 - - set_fr_iimmed 0xffff,0xffe3,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x00000003,fr11 - - set_fr_iimmed 0xffff,0xffe2,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x00000001,fr11 - - set_fr_iimmed 0xffff,0xffe1,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x00000000,fr11 - - set_fr_iimmed 0xffff,0xffe0,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x00000000,fr11 - - set_fr_iimmed 0,32,fr10 ; same as -32 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x00000000,fr11 - - ; Examples from the customer - set_accg_immed 0xffffffff,accg0 - set_acc_immed 0xffe00000,acc0 - - set_fr_iimmed 0,16,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xe0000000,fr11 - - set_fr_iimmed 0,17,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xc0000000,fr11 - - set_fr_iimmed 0,18,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_accg_immed 0,accg0 - set_acc_immed 0x003fffff,acc0 - - set_fr_iimmed 0,16,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x3fffff00,fr11 - - set_fr_iimmed 0,17,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x7ffffe00,fr11 - - set_accg_immed 0x7f,accg0 - set_acc_immed 0xffe00000,acc0 - - set_fr_iimmed 0,16,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x7fffffff,fr11 ; saturated - - set_fr_iimmed 0,17,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x7fffffff,fr11 ; saturated - - set_fr_iimmed 0,18,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x7fffffff,fr11 ; saturated - - set_accg_immed 0x08,accg0 - set_acc_immed 0x003fffff,acc0 - - set_fr_iimmed 0,16,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x7fffffff,fr11 ; saturated - - set_fr_iimmed 0,17,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x7fffffff,fr11 ; saturated - - set_accg_immed 0xff,accg0 - set_acc_immed 0xefe00000,acc0 - - set_fr_iimmed 0,16,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 ; saturated - - set_fr_iimmed 0,17,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 ; saturated - - set_fr_iimmed 0,18,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 ; saturated - - set_accg_immed 0x80,accg0 - set_acc_immed 0x003fffff,acc0 - - set_fr_iimmed 0,16,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 ; saturated - - set_fr_iimmed 0,17,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 ; saturated - - set_accg_immed 0xffffffaf,accg0 - set_acc_immed 0x5a5a5a5a,acc0 - - set_fr_iimmed 0xffff,0xfffc,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0xfaf5a5a5,fr11 - - set_accg_immed 0x0000002f,accg0 - set_acc_immed 0x5a5a5a5a,acc0 - - set_fr_iimmed 0xffff,0xfff9,fr10 - mcutss acc0,fr10,fr11 - test_fr_iimmed 0x005eb4b4,fr11 - - pass diff --git a/sim/testsuite/sim/frv/mcutssi.cgs b/sim/testsuite/sim/frv/mcutssi.cgs deleted file mode 100644 index 739912f5131..00000000000 --- a/sim/testsuite/sim/frv/mcutssi.cgs +++ /dev/null @@ -1,380 +0,0 @@ -# frv testcase for mcutssi $ACC40i,$s6,$FRk -# mach: all - - .include "testutils.inc" - - start - - .global mcutssi -mcutssi: - set_accg_immed 0xffffffe7,accg0 - set_acc_immed 0x89abcdef,acc0 - - mcutssi acc0,0,fr11 - test_fr_iimmed 0xe789abcd,fr11 - - mcutssi acc0,1,fr11 - test_fr_iimmed 0xcf13579b,fr11 - - mcutssi acc0,2,fr11 - test_fr_iimmed 0x9e26af37,fr11 - - mcutssi acc0,3,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,4,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,5,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,6,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,7,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,8,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,9,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,10,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,11,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,12,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,13,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,14,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,15,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,16,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,17,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,18,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,19,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,20,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,21,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,22,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,23,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,24,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,25,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,26,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,27,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,28,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,29,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,30,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,31,fr11 - test_fr_iimmed 0x80000000,fr11 - - mcutssi acc0,-1,fr11 - test_fr_iimmed 0xf3c4d5e6,fr11 - - mcutssi acc0,-2,fr11 - test_fr_iimmed 0xf9e26af3,fr11 - - mcutssi acc0,-3,fr11 - test_fr_iimmed 0xfcf13579,fr11 - - mcutssi acc0,-4,fr11 - test_fr_iimmed 0xfe789abc,fr11 - - mcutssi acc0,-5,fr11 - test_fr_iimmed 0xff3c4d5e,fr11 - - mcutssi acc0,-6,fr11 - test_fr_iimmed 0xff9e26af,fr11 - - mcutssi acc0,-7,fr11 - test_fr_iimmed 0xffcf1357,fr11 - - mcutssi acc0,-8,fr11 - test_fr_iimmed 0xffe789ab,fr11 - - mcutssi acc0,-9,fr11 - test_fr_iimmed 0xfff3c4d5,fr11 - - mcutssi acc0,-10,fr11 - test_fr_iimmed 0xfff9e26a,fr11 - - mcutssi acc0,-11,fr11 - test_fr_iimmed 0xfffcf135,fr11 - - mcutssi acc0,-12,fr11 - test_fr_iimmed 0xfffe789a,fr11 - - mcutssi acc0,-13,fr11 - test_fr_iimmed 0xffff3c4d,fr11 - - mcutssi acc0,-14,fr11 - test_fr_iimmed 0xffff9e26,fr11 - - mcutssi acc0,-15,fr11 - test_fr_iimmed 0xffffcf13,fr11 - - mcutssi acc0,-16,fr11 - test_fr_iimmed 0xffffe789,fr11 - - mcutssi acc0,-17,fr11 - test_fr_iimmed 0xfffff3c4,fr11 - - mcutssi acc0,-18,fr11 - test_fr_iimmed 0xfffff9e2,fr11 - - mcutssi acc0,-19,fr11 - test_fr_iimmed 0xfffffcf1,fr11 - - mcutssi acc0,-20,fr11 - test_fr_iimmed 0xfffffe78,fr11 - - mcutssi acc0,-21,fr11 - test_fr_iimmed 0xffffff3c,fr11 - - mcutssi acc0,-22,fr11 - test_fr_iimmed 0xffffff9e,fr11 - - mcutssi acc0,-23,fr11 - test_fr_iimmed 0xffffffcf,fr11 - - mcutssi acc0,-24,fr11 - test_fr_iimmed 0xffffffe7,fr11 - - mcutssi acc0,-25,fr11 - test_fr_iimmed 0xfffffff3,fr11 - - mcutssi acc0,-26,fr11 - test_fr_iimmed 0xfffffff9,fr11 - - mcutssi acc0,-27,fr11 - test_fr_iimmed 0xfffffffc,fr11 - - mcutssi acc0,-28,fr11 - test_fr_iimmed 0xfffffffe,fr11 - - mcutssi acc0,-29,fr11 - test_fr_iimmed 0xffffffff,fr11 - - mcutssi acc0,-30,fr11 - test_fr_iimmed 0xffffffff,fr11 - - mcutssi acc0,-31,fr11 - test_fr_iimmed 0xffffffff,fr11 - - mcutssi acc0,-32,fr11 - test_fr_iimmed 0xffffffff,fr11 - - set_accg_immed 0xffffff67,accg0 - set_acc_immed 0x89abcdef,acc0 - - mcutssi acc0,-1,fr11 - test_fr_iimmed 0x33c4d5e6,fr11 - - mcutssi acc0,-2,fr11 - test_fr_iimmed 0x19e26af3,fr11 - - mcutssi acc0,-3,fr11 - test_fr_iimmed 0x0cf13579,fr11 - - mcutssi acc0,-4,fr11 - test_fr_iimmed 0x06789abc,fr11 - - mcutssi acc0,-5,fr11 - test_fr_iimmed 0x033c4d5e,fr11 - - mcutssi acc0,-6,fr11 - test_fr_iimmed 0x019e26af,fr11 - - mcutssi acc0,-7,fr11 - test_fr_iimmed 0x00cf1357,fr11 - - mcutssi acc0,-8,fr11 - test_fr_iimmed 0x006789ab,fr11 - - mcutssi acc0,-9,fr11 - test_fr_iimmed 0x0033c4d5,fr11 - - mcutssi acc0,-10,fr11 - test_fr_iimmed 0x0019e26a,fr11 - - mcutssi acc0,-11,fr11 - test_fr_iimmed 0x000cf135,fr11 - - mcutssi acc0,-12,fr11 - test_fr_iimmed 0x0006789a,fr11 - - mcutssi acc0,-13,fr11 - test_fr_iimmed 0x00033c4d,fr11 - - mcutssi acc0,-14,fr11 - test_fr_iimmed 0x00019e26,fr11 - - mcutssi acc0,-15,fr11 - test_fr_iimmed 0x0000cf13,fr11 - - mcutssi acc0,-16,fr11 - test_fr_iimmed 0x00006789,fr11 - - mcutssi acc0,-17,fr11 - test_fr_iimmed 0x000033c4,fr11 - - mcutssi acc0,-18,fr11 - test_fr_iimmed 0x000019e2,fr11 - - mcutssi acc0,-19,fr11 - test_fr_iimmed 0x00000cf1,fr11 - - mcutssi acc0,-20,fr11 - test_fr_iimmed 0x00000678,fr11 - - mcutssi acc0,-21,fr11 - test_fr_iimmed 0x0000033c,fr11 - - mcutssi acc0,-22,fr11 - test_fr_iimmed 0x0000019e,fr11 - - mcutssi acc0,-23,fr11 - test_fr_iimmed 0x000000cf,fr11 - - mcutssi acc0,-24,fr11 - test_fr_iimmed 0x00000067,fr11 - - mcutssi acc0,-25,fr11 - test_fr_iimmed 0x00000033,fr11 - - mcutssi acc0,-26,fr11 - test_fr_iimmed 0x00000019,fr11 - - mcutssi acc0,-27,fr11 - test_fr_iimmed 0x0000000c,fr11 - - mcutssi acc0,-28,fr11 - test_fr_iimmed 0x00000006,fr11 - - mcutssi acc0,-29,fr11 - test_fr_iimmed 0x00000003,fr11 - - mcutssi acc0,-30,fr11 - test_fr_iimmed 0x00000001,fr11 - - mcutssi acc0,-31,fr11 - test_fr_iimmed 0x00000000,fr11 - - mcutssi acc0,-32,fr11 - test_fr_iimmed 0x00000000,fr11 - - ; Examples from the customer - set_accg_immed 0xffffffff,accg0 - set_acc_immed 0xffe00000,acc0 - - mcutssi acc0,16,fr11 - test_fr_iimmed 0xe0000000,fr11 - - mcutssi acc0,17,fr11 - test_fr_iimmed 0xc0000000,fr11 - - mcutssi acc0,18,fr11 - test_fr_iimmed 0x80000000,fr11 - - set_accg_immed 0,accg0 - set_acc_immed 0x003fffff,acc0 - - mcutssi acc0,16,fr11 - test_fr_iimmed 0x3fffff00,fr11 - - mcutssi acc0,17,fr11 - test_fr_iimmed 0x7ffffe00,fr11 - - set_accg_immed 0x7f,accg0 - set_acc_immed 0xffe00000,acc0 - - mcutssi acc0,16,fr11 - test_fr_iimmed 0x7fffffff,fr11 ; saturated - - mcutssi acc0,17,fr11 - test_fr_iimmed 0x7fffffff,fr11 ; saturated - - mcutssi acc0,18,fr11 - test_fr_iimmed 0x7fffffff,fr11 ; saturated - - set_accg_immed 0x08,accg0 - set_acc_immed 0x003fffff,acc0 - - mcutssi acc0,16,fr11 - test_fr_iimmed 0x7fffffff,fr11 ; saturated - - mcutssi acc0,17,fr11 - test_fr_iimmed 0x7fffffff,fr11 ; saturated - - set_accg_immed 0xff,accg0 - set_acc_immed 0xefe00000,acc0 - - mcutssi acc0,16,fr11 - test_fr_iimmed 0x80000000,fr11 ; saturated - - mcutssi acc0,17,fr11 - test_fr_iimmed 0x80000000,fr11 ; saturated - - mcutssi acc0,18,fr11 - test_fr_iimmed 0x80000000,fr11 ; saturated - - set_accg_immed 0x80,accg0 - set_acc_immed 0x003fffff,acc0 - - mcutssi acc0,16,fr11 - test_fr_iimmed 0x80000000,fr11 ; saturated - - mcutssi acc0,17,fr11 - test_fr_iimmed 0x80000000,fr11 ; saturated - - set_accg_immed 0xffffffaf,accg0 - set_acc_immed 0x5a5a5a5a,acc0 - - mcutssi acc0,-4,fr11 - test_fr_iimmed 0xfaf5a5a5,fr11 - - set_accg_immed 0x0000002f,accg0 - set_acc_immed 0x5a5a5a5a,acc0 - - mcutssi acc0,-7,fr11 - test_fr_iimmed 0x005eb4b4,fr11 - - pass diff --git a/sim/testsuite/sim/frv/mdaddaccs.cgs b/sim/testsuite/sim/frv/mdaddaccs.cgs deleted file mode 100644 index 553c4a773c7..00000000000 --- a/sim/testsuite/sim/frv/mdaddaccs.cgs +++ /dev/null @@ -1,102 +0,0 @@ -# frv testcase for mdaddaccs $ACC40Si,$ACC40Sk -# mach: fr400 - - .include "testutils.inc" - - start - - .global mdaddaccs -mdaddaccs: - set_accg_immed 0,accg0 - set_acc_immed 0x00000000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000000,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0xdead0000,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0x0000beef,acc3 - mdaddaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0xdead,0xbeef,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x0000dead,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xbeef0000,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x12345678,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0x11111111,acc3 - mdaddaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0xbeef,0xdead,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x2345,0x6789,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x12345678,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - mdaddaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 1,accg2 - test_acc_limmed 0x1234,0x5677,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x1234,0x5677,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x7f,accg0 - set_acc_immed 0xfffe7ffe,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x00020001,acc1 - set_accg_immed 0x80,accg2 - set_acc_immed 0x00000001,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xfffffffe,acc3 - mdaddaccs acc0,acc2 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0000,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000001,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x00000001,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - mdaddaccs acc0,acc2 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0002,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - pass diff --git a/sim/testsuite/sim/frv/mdasaccs.cgs b/sim/testsuite/sim/frv/mdasaccs.cgs deleted file mode 100644 index 0535b6295b2..00000000000 --- a/sim/testsuite/sim/frv/mdasaccs.cgs +++ /dev/null @@ -1,122 +0,0 @@ -# frv testcase for mdasaccs $ACC40Si,$ACC40Sk -# mach: fr400 - - .include "testutils.inc" - - start - - .global mdasaccs -mdasaccs: - set_accg_immed 0,accg0 - set_acc_immed 0x00000000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000000,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0xdead0000,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0x0000beef,acc3 - mdasaccs acc0,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0000,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0xdead,0xbeef,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0xdeac,0x4111,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x0000dead,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xbeef0000,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x12345678,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0x11111111,acc3 - mdasaccs acc0,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0xbeef,0xdead,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0x4111,0xdead,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x2345,0x6789,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0123,0x4567,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x12345678,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - mdasaccs acc0,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 1,accg0 - test_acc_limmed 0x1234,0x5677,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0x1234,0x5679,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x1234,0x5677,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x1234,0x5679,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x7f,accg0 - set_acc_immed 0xfffe7ffe,acc0 - set_accg_immed 0x0,accg1 - set_acc_immed 0x00020001,acc1 - set_accg_immed 0x80,accg2 - set_acc_immed 0x00000001,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xfffffffe,acc3 - mdasaccs acc0,acc0 - test_spr_bits 0x3c,2,0xa,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xfffc,0x7ffd,acc1 - test_accg_immed 0x80,accg2 - test_acc_limmed 0x0000,0x0000,acc2 - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0003,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000001,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x00000001,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - mdasaccs acc0,acc0 - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0000,acc1 - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0002,acc3 - - pass diff --git a/sim/testsuite/sim/frv/mdcutssi.cgs b/sim/testsuite/sim/frv/mdcutssi.cgs deleted file mode 100644 index 8e5216c347d..00000000000 --- a/sim/testsuite/sim/frv/mdcutssi.cgs +++ /dev/null @@ -1,513 +0,0 @@ -# frv testcase for mdcutssi $ACC40i,$s6,$FRk -# mach: fr400 fr550 - - .include "testutils.inc" - - start - - .global mdcutssi -mdcutssi: - set_accg_immed 0xffffffe7,accg0 - set_acc_immed 0x89abcdef,acc0 - set_accg_immed 0xffffffe7,accg1 - set_acc_immed 0x89abcdef,acc1 - - mdcutssi acc0,0,fr10 - test_fr_iimmed 0xe789abcd,fr10 - test_fr_iimmed 0xe789abcd,fr11 - - mdcutssi acc0,1,fr10 - test_fr_iimmed 0xcf13579b,fr10 - test_fr_iimmed 0xcf13579b,fr11 - - mdcutssi acc0,2,fr10 - test_fr_iimmed 0x9e26af37,fr10 - test_fr_iimmed 0x9e26af37,fr11 - - mdcutssi acc0,3,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,4,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,5,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,6,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,7,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,8,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,9,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,10,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,11,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,12,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,13,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,14,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,15,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,16,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,17,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,18,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,19,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,20,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,21,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,22,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,23,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,24,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,25,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,26,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,27,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,28,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,29,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,30,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,31,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - mdcutssi acc0,-1,fr10 - test_fr_iimmed 0xf3c4d5e6,fr10 - test_fr_iimmed 0xf3c4d5e6,fr11 - - mdcutssi acc0,-2,fr10 - test_fr_iimmed 0xf9e26af3,fr10 - test_fr_iimmed 0xf9e26af3,fr11 - - mdcutssi acc0,-3,fr10 - test_fr_iimmed 0xfcf13579,fr10 - test_fr_iimmed 0xfcf13579,fr11 - - mdcutssi acc0,-4,fr10 - test_fr_iimmed 0xfe789abc,fr10 - test_fr_iimmed 0xfe789abc,fr11 - - mdcutssi acc0,-5,fr10 - test_fr_iimmed 0xff3c4d5e,fr10 - test_fr_iimmed 0xff3c4d5e,fr11 - - mdcutssi acc0,-6,fr10 - test_fr_iimmed 0xff9e26af,fr10 - test_fr_iimmed 0xff9e26af,fr11 - - mdcutssi acc0,-7,fr10 - test_fr_iimmed 0xffcf1357,fr10 - test_fr_iimmed 0xffcf1357,fr11 - - mdcutssi acc0,-8,fr10 - test_fr_iimmed 0xffe789ab,fr10 - test_fr_iimmed 0xffe789ab,fr11 - - mdcutssi acc0,-9,fr10 - test_fr_iimmed 0xfff3c4d5,fr10 - test_fr_iimmed 0xfff3c4d5,fr11 - - mdcutssi acc0,-10,fr10 - test_fr_iimmed 0xfff9e26a,fr10 - test_fr_iimmed 0xfff9e26a,fr11 - - mdcutssi acc0,-11,fr10 - test_fr_iimmed 0xfffcf135,fr10 - test_fr_iimmed 0xfffcf135,fr11 - - mdcutssi acc0,-12,fr10 - test_fr_iimmed 0xfffe789a,fr10 - test_fr_iimmed 0xfffe789a,fr11 - - mdcutssi acc0,-13,fr10 - test_fr_iimmed 0xffff3c4d,fr10 - test_fr_iimmed 0xffff3c4d,fr11 - - mdcutssi acc0,-14,fr10 - test_fr_iimmed 0xffff9e26,fr10 - test_fr_iimmed 0xffff9e26,fr11 - - mdcutssi acc0,-15,fr10 - test_fr_iimmed 0xffffcf13,fr10 - test_fr_iimmed 0xffffcf13,fr11 - - mdcutssi acc0,-16,fr10 - test_fr_iimmed 0xffffe789,fr10 - test_fr_iimmed 0xffffe789,fr11 - - mdcutssi acc0,-17,fr10 - test_fr_iimmed 0xfffff3c4,fr10 - test_fr_iimmed 0xfffff3c4,fr11 - - mdcutssi acc0,-18,fr10 - test_fr_iimmed 0xfffff9e2,fr10 - test_fr_iimmed 0xfffff9e2,fr11 - - mdcutssi acc0,-19,fr10 - test_fr_iimmed 0xfffffcf1,fr10 - test_fr_iimmed 0xfffffcf1,fr11 - - mdcutssi acc0,-20,fr10 - test_fr_iimmed 0xfffffe78,fr10 - test_fr_iimmed 0xfffffe78,fr11 - - mdcutssi acc0,-21,fr10 - test_fr_iimmed 0xffffff3c,fr10 - test_fr_iimmed 0xffffff3c,fr11 - - mdcutssi acc0,-22,fr10 - test_fr_iimmed 0xffffff9e,fr10 - test_fr_iimmed 0xffffff9e,fr11 - - mdcutssi acc0,-23,fr10 - test_fr_iimmed 0xffffffcf,fr10 - test_fr_iimmed 0xffffffcf,fr11 - - mdcutssi acc0,-24,fr10 - test_fr_iimmed 0xffffffe7,fr10 - test_fr_iimmed 0xffffffe7,fr11 - - mdcutssi acc0,-25,fr10 - test_fr_iimmed 0xfffffff3,fr10 - test_fr_iimmed 0xfffffff3,fr11 - - mdcutssi acc0,-26,fr10 - test_fr_iimmed 0xfffffff9,fr10 - test_fr_iimmed 0xfffffff9,fr11 - - mdcutssi acc0,-27,fr10 - test_fr_iimmed 0xfffffffc,fr10 - test_fr_iimmed 0xfffffffc,fr11 - - mdcutssi acc0,-28,fr10 - test_fr_iimmed 0xfffffffe,fr10 - test_fr_iimmed 0xfffffffe,fr11 - - mdcutssi acc0,-29,fr10 - test_fr_iimmed 0xffffffff,fr10 - test_fr_iimmed 0xffffffff,fr11 - - mdcutssi acc0,-30,fr10 - test_fr_iimmed 0xffffffff,fr10 - test_fr_iimmed 0xffffffff,fr11 - - mdcutssi acc0,-31,fr10 - test_fr_iimmed 0xffffffff,fr10 - test_fr_iimmed 0xffffffff,fr11 - - mdcutssi acc0,-32,fr10 - test_fr_iimmed 0xffffffff,fr10 - test_fr_iimmed 0xffffffff,fr11 - - set_accg_immed 0xffffff67,accg0 - set_acc_immed 0x89abcdef,acc0 - set_accg_immed 0xffffff67,accg1 - set_acc_immed 0x89abcdef,acc1 - - mdcutssi acc0,-1,fr10 - test_fr_iimmed 0x33c4d5e6,fr10 - test_fr_iimmed 0x33c4d5e6,fr11 - - mdcutssi acc0,-2,fr10 - test_fr_iimmed 0x19e26af3,fr10 - test_fr_iimmed 0x19e26af3,fr11 - - mdcutssi acc0,-3,fr10 - test_fr_iimmed 0x0cf13579,fr10 - test_fr_iimmed 0x0cf13579,fr11 - - mdcutssi acc0,-4,fr10 - test_fr_iimmed 0x06789abc,fr10 - test_fr_iimmed 0x06789abc,fr11 - - mdcutssi acc0,-5,fr10 - test_fr_iimmed 0x033c4d5e,fr10 - test_fr_iimmed 0x033c4d5e,fr11 - - mdcutssi acc0,-6,fr10 - test_fr_iimmed 0x019e26af,fr10 - test_fr_iimmed 0x019e26af,fr11 - - mdcutssi acc0,-7,fr10 - test_fr_iimmed 0x00cf1357,fr10 - test_fr_iimmed 0x00cf1357,fr11 - - mdcutssi acc0,-8,fr10 - test_fr_iimmed 0x006789ab,fr10 - test_fr_iimmed 0x006789ab,fr11 - - mdcutssi acc0,-9,fr10 - test_fr_iimmed 0x0033c4d5,fr10 - test_fr_iimmed 0x0033c4d5,fr11 - - mdcutssi acc0,-10,fr10 - test_fr_iimmed 0x0019e26a,fr10 - test_fr_iimmed 0x0019e26a,fr11 - - mdcutssi acc0,-11,fr10 - test_fr_iimmed 0x000cf135,fr10 - test_fr_iimmed 0x000cf135,fr11 - - mdcutssi acc0,-12,fr10 - test_fr_iimmed 0x0006789a,fr10 - test_fr_iimmed 0x0006789a,fr11 - - mdcutssi acc0,-13,fr10 - test_fr_iimmed 0x00033c4d,fr10 - test_fr_iimmed 0x00033c4d,fr11 - - mdcutssi acc0,-14,fr10 - test_fr_iimmed 0x00019e26,fr10 - test_fr_iimmed 0x00019e26,fr11 - - mdcutssi acc0,-15,fr10 - test_fr_iimmed 0x0000cf13,fr10 - test_fr_iimmed 0x0000cf13,fr11 - - mdcutssi acc0,-16,fr10 - test_fr_iimmed 0x00006789,fr10 - test_fr_iimmed 0x00006789,fr11 - - mdcutssi acc0,-17,fr10 - test_fr_iimmed 0x000033c4,fr10 - test_fr_iimmed 0x000033c4,fr11 - - mdcutssi acc0,-18,fr10 - test_fr_iimmed 0x000019e2,fr10 - test_fr_iimmed 0x000019e2,fr11 - - mdcutssi acc0,-19,fr10 - test_fr_iimmed 0x00000cf1,fr10 - test_fr_iimmed 0x00000cf1,fr11 - - mdcutssi acc0,-20,fr10 - test_fr_iimmed 0x00000678,fr10 - test_fr_iimmed 0x00000678,fr11 - - mdcutssi acc0,-21,fr10 - test_fr_iimmed 0x0000033c,fr10 - test_fr_iimmed 0x0000033c,fr11 - - mdcutssi acc0,-22,fr10 - test_fr_iimmed 0x0000019e,fr10 - test_fr_iimmed 0x0000019e,fr11 - - mdcutssi acc0,-23,fr10 - test_fr_iimmed 0x000000cf,fr10 - test_fr_iimmed 0x000000cf,fr11 - - mdcutssi acc0,-24,fr10 - test_fr_iimmed 0x00000067,fr10 - test_fr_iimmed 0x00000067,fr11 - - mdcutssi acc0,-25,fr10 - test_fr_iimmed 0x00000033,fr10 - test_fr_iimmed 0x00000033,fr11 - - mdcutssi acc0,-26,fr10 - test_fr_iimmed 0x00000019,fr10 - test_fr_iimmed 0x00000019,fr11 - - mdcutssi acc0,-27,fr10 - test_fr_iimmed 0x0000000c,fr10 - test_fr_iimmed 0x0000000c,fr11 - - mdcutssi acc0,-28,fr10 - test_fr_iimmed 0x00000006,fr10 - test_fr_iimmed 0x00000006,fr11 - - mdcutssi acc0,-29,fr10 - test_fr_iimmed 0x00000003,fr10 - test_fr_iimmed 0x00000003,fr11 - - mdcutssi acc0,-30,fr10 - test_fr_iimmed 0x00000001,fr10 - test_fr_iimmed 0x00000001,fr11 - - mdcutssi acc0,-31,fr10 - test_fr_iimmed 0x00000000,fr10 - test_fr_iimmed 0x00000000,fr11 - - mdcutssi acc0,-32,fr10 - test_fr_iimmed 0x00000000,fr10 - test_fr_iimmed 0x00000000,fr11 - - ; Examples from the customer - set_accg_immed 0xffffffff,accg0 - set_acc_immed 0xffe00000,acc0 - set_accg_immed 0xffffffff,accg1 - set_acc_immed 0xffe00000,acc1 - - mdcutssi acc0,16,fr10 - test_fr_iimmed 0xe0000000,fr10 - test_fr_iimmed 0xe0000000,fr11 - - mdcutssi acc0,17,fr10 - test_fr_iimmed 0xc0000000,fr10 - test_fr_iimmed 0xc0000000,fr11 - - mdcutssi acc0,18,fr10 - test_fr_iimmed 0x80000000,fr10 - test_fr_iimmed 0x80000000,fr11 - - set_accg_immed 0,accg0 - set_acc_immed 0x003fffff,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x003fffff,acc1 - - mdcutssi acc0,16,fr10 - test_fr_iimmed 0x3fffff00,fr10 - test_fr_iimmed 0x3fffff00,fr11 - - mdcutssi acc0,17,fr10 - test_fr_iimmed 0x7ffffe00,fr10 - test_fr_iimmed 0x7ffffe00,fr11 - - set_accg_immed 0x7f,accg0 - set_acc_immed 0xffe00000,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffe00000,acc1 - - mdcutssi acc0,16,fr10 - test_fr_iimmed 0x7fffffff,fr10 ; saturated - test_fr_iimmed 0x7fffffff,fr11 ; saturated - - mdcutssi acc0,17,fr10 - test_fr_iimmed 0x7fffffff,fr10 ; saturated - test_fr_iimmed 0x7fffffff,fr11 ; saturated - - mdcutssi acc0,18,fr10 - test_fr_iimmed 0x7fffffff,fr10 ; saturated - test_fr_iimmed 0x7fffffff,fr11 ; saturated - - set_accg_immed 0x08,accg0 - set_acc_immed 0x003fffff,acc0 - set_accg_immed 0x08,accg1 - set_acc_immed 0x003fffff,acc1 - - mdcutssi acc0,16,fr10 - test_fr_iimmed 0x7fffffff,fr10 ; saturated - test_fr_iimmed 0x7fffffff,fr11 ; saturated - - mdcutssi acc0,17,fr10 - test_fr_iimmed 0x7fffffff,fr10 ; saturated - test_fr_iimmed 0x7fffffff,fr11 ; saturated - - set_accg_immed 0xff,accg0 - set_acc_immed 0xefe00000,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xefe00000,acc1 - - mdcutssi acc0,16,fr10 - test_fr_iimmed 0x80000000,fr10 ; saturated - test_fr_iimmed 0x80000000,fr11 ; saturated - - mdcutssi acc0,17,fr10 - test_fr_iimmed 0x80000000,fr10 ; saturated - test_fr_iimmed 0x80000000,fr11 ; saturated - - mdcutssi acc0,18,fr10 - test_fr_iimmed 0x80000000,fr10 ; saturated - test_fr_iimmed 0x80000000,fr11 ; saturated - - set_accg_immed 0x80,accg0 - set_acc_immed 0x003fffff,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0x003fffff,acc1 - - mdcutssi acc0,16,fr10 - test_fr_iimmed 0x80000000,fr10 ; saturated - test_fr_iimmed 0x80000000,fr11 ; saturated - - mdcutssi acc0,17,fr10 - test_fr_iimmed 0x80000000,fr10 ; saturated - test_fr_iimmed 0x80000000,fr11 ; saturated - - set_accg_immed 0xffffffaf,accg0 - set_acc_immed 0x5a5a5a5a,acc0 - set_accg_immed 0xffffffaf,accg1 - set_acc_immed 0x5a5a5a5a,acc1 - - mdcutssi acc0,-4,fr10 - test_fr_iimmed 0xfaf5a5a5,fr10 - test_fr_iimmed 0xfaf5a5a5,fr11 - - set_accg_immed 0x0000002f,accg0 - set_acc_immed 0x5a5a5a5a,acc0 - set_accg_immed 0x0000002f,accg1 - set_acc_immed 0x5a5a5a5a,acc1 - - mdcutssi acc0,-7,fr10 - test_fr_iimmed 0x005eb4b4,fr10 - test_fr_iimmed 0x005eb4b4,fr11 - - pass diff --git a/sim/testsuite/sim/frv/mdpackh.cgs b/sim/testsuite/sim/frv/mdpackh.cgs deleted file mode 100644 index cbd0bc80008..00000000000 --- a/sim/testsuite/sim/frv/mdpackh.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# frv testcase for mdpackh $FRi,$FRj,$FRj -# mach: all - - .include "testutils.inc" - - start - - .global mdpackh -mdpackh: - set_fr_iimmed 0xdead,0xbeef,fr10 - set_fr_iimmed 0xaaaa,0xbbbb,fr11 - set_fr_iimmed 0x1234,0x5678,fr12 - set_fr_iimmed 0xcccc,0xdddd,fr13 - mdpackh fr10,fr12,fr14 - test_fr_limmed 0xbeef,0x5678,fr14 - test_fr_limmed 0xbbbb,0xdddd,fr15 - - pass diff --git a/sim/testsuite/sim/frv/mdrotli.cgs b/sim/testsuite/sim/frv/mdrotli.cgs deleted file mode 100644 index 1d2e183a1c9..00000000000 --- a/sim/testsuite/sim/frv/mdrotli.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# frv testcase for mdrotli $FRi,$s6,$FRk -# mach: fr400 fr550 - - .include "testutils.inc" - - start - - .global mdrotli -mdrotli: - set_fr_iimmed 0,2,fr8 - set_fr_iimmed 0,2,fr9 - mdrotli fr8,-32,fr8 ; Shift by 0 - test_fr_iimmed 2,fr8 - test_fr_iimmed 2,fr9 - - set_fr_iimmed 0,2,fr8 - set_fr_iimmed 0,2,fr9 - mdrotli fr8,1,fr8 ; Shift by 1 - test_fr_iimmed 4,fr8 - test_fr_iimmed 4,fr9 - - set_fr_iimmed 0,1,fr8 - set_fr_iimmed 0,2,fr9 - mdrotli fr8,31,fr8 ; Shift by 31 - test_fr_iimmed 0x80000000,fr8 - test_fr_iimmed 1,fr9 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - mdrotli fr8,16,fr8 - test_fr_iimmed 0xbeefdead,fr8 - test_fr_iimmed 0xdeadbeef,fr9 - - pass diff --git a/sim/testsuite/sim/frv/mdsubaccs.cgs b/sim/testsuite/sim/frv/mdsubaccs.cgs deleted file mode 100644 index 73d2e2dc899..00000000000 --- a/sim/testsuite/sim/frv/mdsubaccs.cgs +++ /dev/null @@ -1,102 +0,0 @@ -# frv testcase for mdsubaccs $ACC40Si,$ACC40Sk -# mach: fr400 - - .include "testutils.inc" - - start - - .global mdsubaccs -mdsubaccs: - set_accg_immed 0,accg0 - set_acc_immed 0x00000000,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000000,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0xdead0000,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0x0000beef,acc3 - mdsubaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0xdeac,0x4111,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x0000dead,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xbeef0000,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x12345678,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0x11111111,acc3 - mdsubaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg2 - test_acc_limmed 0x4111,0xdead,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0123,0x4567,acc3 - - set_accg_immed 0,accg0 - set_acc_immed 0x12345678,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x12345678,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - mdsubaccs acc0,acc2 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg2 - test_acc_limmed 0x1234,0x5679,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x1234,0x5679,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0x7f,accg0 - set_acc_immed 0xfffffffe,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xfffffffe,acc1 - set_accg_immed 0x80,accg2 - set_acc_immed 0x00000001,acc2 - set_accg_immed 0,accg3 - set_acc_immed 0x00000002,acc3 - mdsubaccs acc0,acc2 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x80,accg3 - test_acc_limmed 0x0000,0x0000,acc3 - - set_spr_immed 0,msr0 - set_accg_immed 0,accg0 - set_acc_immed 0x00000001,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0x00000001,acc1 - set_accg_immed 0,accg2 - set_acc_immed 0x00000001,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0x00000000,acc3 - mdsubaccs acc0,acc2 - test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0000,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - pass diff --git a/sim/testsuite/sim/frv/mdunpackh.cgs b/sim/testsuite/sim/frv/mdunpackh.cgs deleted file mode 100644 index 02870c8c14d..00000000000 --- a/sim/testsuite/sim/frv/mdunpackh.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for mdunpackh $FRi,$FRj -# mach: frv - - .include "testutils.inc" - - start - - .global mdunpackh -mdunpackh: - set_fr_iimmed 0xdead,0xbeef,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - mdunpackh fr10,fr12 - test_fr_limmed 0xdead,0xdead,fr12 - test_fr_limmed 0xbeef,0xbeef,fr13 - test_fr_limmed 0x1234,0x1234,fr14 - test_fr_limmed 0x5678,0x5678,fr15 - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xdead,0xbeef,fr11 - mdunpackh fr10,fr12 - test_fr_limmed 0x1234,0x1234,fr12 - test_fr_limmed 0x5678,0x5678,fr13 - test_fr_limmed 0xdead,0xdead,fr14 - test_fr_limmed 0xbeef,0xbeef,fr15 - - pass diff --git a/sim/testsuite/sim/frv/membar.cgs b/sim/testsuite/sim/frv/membar.cgs deleted file mode 100644 index aae1d1a8e21..00000000000 --- a/sim/testsuite/sim/frv/membar.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# frv testcase for membar -# mach: all - - .include "testutils.inc" - - start - - .global membar -membar: - membar - - pass diff --git a/sim/testsuite/sim/frv/mexpdhd.cgs b/sim/testsuite/sim/frv/mexpdhd.cgs deleted file mode 100644 index d5f95ce98bd..00000000000 --- a/sim/testsuite/sim/frv/mexpdhd.cgs +++ /dev/null @@ -1,27 +0,0 @@ -# frv testcase for mexpdhd $FRi,$s6,$FRj -# mach: all - - .include "testutils.inc" - - start - - .global mexpdhd -mexpdhd: - set_fr_iimmed 0xdead,0xbeef,fr10 - mexpdhd fr10,0,fr12 - test_fr_limmed 0xdead,0xdead,fr12 - test_fr_limmed 0xdead,0xdead,fr13 - - mexpdhd fr10,1,fr12 - test_fr_limmed 0xbeef,0xbeef,fr12 - test_fr_limmed 0xbeef,0xbeef,fr13 - - mexpdhd fr10,62,fr12 - test_fr_limmed 0xdead,0xdead,fr12 - test_fr_limmed 0xdead,0xdead,fr13 - - mexpdhd fr10,63,fr12 - test_fr_limmed 0xbeef,0xbeef,fr12 - test_fr_limmed 0xbeef,0xbeef,fr13 - - pass diff --git a/sim/testsuite/sim/frv/mexpdhw.cgs b/sim/testsuite/sim/frv/mexpdhw.cgs deleted file mode 100644 index a13b0f24ce0..00000000000 --- a/sim/testsuite/sim/frv/mexpdhw.cgs +++ /dev/null @@ -1,23 +0,0 @@ -# frv testcase for mexpdhw $FRi,$s6,$FRj -# mach: all - - .include "testutils.inc" - - start - - .global mexpdhw -mexpdhw: - set_fr_iimmed 0xdead,0xbeef,fr10 - mexpdhw fr10,0,fr12 - test_fr_limmed 0xdead,0xdead,fr12 - - mexpdhw fr10,1,fr12 - test_fr_limmed 0xbeef,0xbeef,fr12 - - mexpdhw fr10,62,fr12 - test_fr_limmed 0xdead,0xdead,fr12 - - mexpdhw fr10,63,fr12 - test_fr_limmed 0xbeef,0xbeef,fr12 - - pass diff --git a/sim/testsuite/sim/frv/mhdseth.cgs b/sim/testsuite/sim/frv/mhdseth.cgs deleted file mode 100644 index 7c09b2d9d00..00000000000 --- a/sim/testsuite/sim/frv/mhdseth.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for mhdseth $s5,$FRk -# mach: fr400 fr550 - - .include "testutils.inc" - - start - - .global setlo -setlo: - set_fr_iimmed 0xdead,0xbeef,fr1 - mhdseth 0,fr1 - test_fr_limmed 0x06ad,0x06ef,fr1 - - mhdseth 1,fr1 - test_fr_limmed 0x0ead,0x0eef,fr1 - - mhdseth 0xf,fr1 - test_fr_limmed 0x7ead,0x7eef,fr1 - - mhdseth -16,fr1 - test_fr_limmed 0x86ad,0x86ef,fr1 - - mhdseth -1,fr1 - test_fr_limmed 0xfead,0xfeef,fr1 - - pass diff --git a/sim/testsuite/sim/frv/mhdsets.cgs b/sim/testsuite/sim/frv/mhdsets.cgs deleted file mode 100644 index 1f2681450be..00000000000 --- a/sim/testsuite/sim/frv/mhdsets.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for mhdsets $u12,$FRk -# mach: fr400 fr550 - - .include "testutils.inc" - - start - - .global setlo -setlo: - set_fr_iimmed 0xdead,0xbeef,fr1 - mhdsets 0,fr1 - test_fr_limmed 0x0000,0x0000,fr1 - - mhdsets 1,fr1 - test_fr_limmed 0x0001,0x0001,fr1 - - mhdsets 0x07ff,fr1 - test_fr_limmed 0x07ff,0x07ff,fr1 - - mhdsets -2048,fr1 - test_fr_limmed 0xf800,0xf800,fr1 - - mhdsets -1,fr1 - test_fr_limmed 0xffff,0xffff,fr1 - - pass diff --git a/sim/testsuite/sim/frv/mhsethih.cgs b/sim/testsuite/sim/frv/mhsethih.cgs deleted file mode 100644 index f05eb77509d..00000000000 --- a/sim/testsuite/sim/frv/mhsethih.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for mhsethih $s5,$FRk -# mach: fr400 fr550 - - .include "testutils.inc" - - start - - .global setlo -setlo: - set_fr_iimmed 0xdead,0xbeef,fr1 - mhsethih 0,fr1 - test_fr_limmed 0x06ad,0xbeef,fr1 - - mhsethih 1,fr1 - test_fr_limmed 0x0ead,0xbeef,fr1 - - mhsethih 0xf,fr1 - test_fr_limmed 0x7ead,0xbeef,fr1 - - mhsethih -16,fr1 - test_fr_limmed 0x86ad,0xbeef,fr1 - - mhsethih -1,fr1 - test_fr_limmed 0xfead,0xbeef,fr1 - - pass diff --git a/sim/testsuite/sim/frv/mhsethis.cgs b/sim/testsuite/sim/frv/mhsethis.cgs deleted file mode 100644 index cf893366cbe..00000000000 --- a/sim/testsuite/sim/frv/mhsethis.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for mhsethis $u12,$FRk -# mach: fr400 fr550 - - .include "testutils.inc" - - start - - .global setlo -setlo: - set_fr_iimmed 0xdead,0xbeef,fr1 - mhsethis 0,fr1 - test_fr_limmed 0x0000,0xbeef,fr1 - - mhsethis 1,fr1 - test_fr_limmed 0x0001,0xbeef,fr1 - - mhsethis 0x07ff,fr1 - test_fr_limmed 0x07ff,0xbeef,fr1 - - mhsethis -2048,fr1 - test_fr_limmed 0xf800,0xbeef,fr1 - - mhsethis -1,fr1 - test_fr_limmed 0xffff,0xbeef,fr1 - - pass diff --git a/sim/testsuite/sim/frv/mhsetloh.cgs b/sim/testsuite/sim/frv/mhsetloh.cgs deleted file mode 100644 index 930628d97e9..00000000000 --- a/sim/testsuite/sim/frv/mhsetloh.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for mhsetloh $s5,$FRk -# mach: fr400 fr550 - - .include "testutils.inc" - - start - - .global setlo -setlo: - set_fr_iimmed 0xdead,0xbeef,fr1 - mhsetloh 0,fr1 - test_fr_limmed 0xdead,0x06ef,fr1 - - mhsetloh 1,fr1 - test_fr_limmed 0xdead,0x0eef,fr1 - - mhsetloh 0xf,fr1 - test_fr_limmed 0xdead,0x7eef,fr1 - - mhsetloh -16,fr1 - test_fr_limmed 0xdead,0x86ef,fr1 - - mhsetloh -1,fr1 - test_fr_limmed 0xdead,0xfeef,fr1 - - pass diff --git a/sim/testsuite/sim/frv/mhsetlos.cgs b/sim/testsuite/sim/frv/mhsetlos.cgs deleted file mode 100644 index fb404a23ebb..00000000000 --- a/sim/testsuite/sim/frv/mhsetlos.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for mhsetlos $u12,$FRk -# mach: fr400 fr550 - - .include "testutils.inc" - - start - - .global setlo -setlo: - set_fr_iimmed 0xdead,0xbeef,fr1 - mhsetlos 0,fr1 - test_fr_limmed 0xdead,0x0000,fr1 - - mhsetlos 1,fr1 - test_fr_limmed 0xdead,0x0001,fr1 - - mhsetlos 0x07ff,fr1 - test_fr_limmed 0xdead,0x07ff,fr1 - - mhsetlos -2048,fr1 - test_fr_limmed 0xdead,0xf800,fr1 - - mhsetlos -1,fr1 - test_fr_limmed 0xdead,0xffff,fr1 - - pass diff --git a/sim/testsuite/sim/frv/mhtob.cgs b/sim/testsuite/sim/frv/mhtob.cgs deleted file mode 100644 index efd83d73bde..00000000000 --- a/sim/testsuite/sim/frv/mhtob.cgs +++ /dev/null @@ -1,25 +0,0 @@ -# frv testcase for mhtob $FRj,$FRk -# mach: all - - .include "testutils.inc" - - start - - .global mhtob -mhtob: - set_fr_iimmed 0x00ad,0x00ef,fr10 - set_fr_iimmed 0x0034,0x0078,fr11 - mhtob fr10,fr12 - test_fr_limmed 0xadef,0x3478,fr12 - - set_fr_iimmed 0xdead,0xbeef,fr10 ; saturation - set_fr_iimmed 0x1234,0x5678,fr11 - mhtob fr10,fr12 - test_fr_limmed 0xffff,0xffff,fr12 - - set_fr_iimmed 0x0134,0x0878,fr10 ; saturation - set_fr_iimmed 0x10ad,0x80ef,fr11 - mhtob fr10,fr12 - test_fr_limmed 0xffff,0xffff,fr12 - - pass diff --git a/sim/testsuite/sim/frv/mmachs.cgs b/sim/testsuite/sim/frv/mmachs.cgs deleted file mode 100644 index 0292161b432..00000000000 --- a/sim/testsuite/sim/frv/mmachs.cgs +++ /dev/null @@ -1,259 +0,0 @@ -# frv testcase for mmachs $GRi,$GRj,$ACCk -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global mmachs -mmachs: - ; Positive operands - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0,0x8006,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0001,0x0006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0001,0x0006,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0007,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0007,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0001,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xffff,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xffff,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xffff,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xffff,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0xbffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0xbffd,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x3ffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x3ffd,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffd,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffd,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xc003,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xc003,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xc005,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xc005,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x3ffec006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3ffec006,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x7ffec006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x7ffec006,acc1 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - mmachs fr7,fr8,acc0 - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr7 - set_fr_iimmed 1,0xffff,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0x8000,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmachs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - pass - - diff --git a/sim/testsuite/sim/frv/mmachu.cgs b/sim/testsuite/sim/frv/mmachu.cgs deleted file mode 100644 index aad07c7fba8..00000000000 --- a/sim/testsuite/sim/frv/mmachu.cgs +++ /dev/null @@ -1,146 +0,0 @@ -# frv testcase for mmachu $GRi,$GRj,$GRk -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global mmachu -mmachu: - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8006,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0001,0x0006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0001,0x0006,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x00020006,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x00020006,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x40010007,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x40010007,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x8001,0x0007,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x8001,0x0007,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 1,accg0 - test_acc_limmed 0x7fff,0x0008,acc0 - test_accg_immed 1,accg1 - test_acc_limmed 0x7fff,0x0008,acc1 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_fr_iimmed 0xffff,0x0000,fr7 - set_fr_iimmed 0xffff,0xffff,fr8 - mmachu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - pass diff --git a/sim/testsuite/sim/frv/mmrdhs.cgs b/sim/testsuite/sim/frv/mmrdhs.cgs deleted file mode 100644 index 6295bc1687f..00000000000 --- a/sim/testsuite/sim/frv/mmrdhs.cgs +++ /dev/null @@ -1,263 +0,0 @@ -# frv testcase for mmrdhs $GRi,$GRj,$ACCk -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global mmrdhs -mmrdhs: - ; Positive operands - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_immed -6,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -6,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_immed -6,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -6,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_immed -8,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -8,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x7ffa,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0x7ffa,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xfffe,0xfffa,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xfffe,0xfffa,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xbfff,0xfff9,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xbfff,0xfff9,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xbfff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xbfff,0xffff,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xc000,0x0001,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xc000,0x0001,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xc000,0x0001,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xc000,0x0001,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xc000,0x4003,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xc000,0x4003,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xc000,0xc003,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xc000,0xc003,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x4003,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x4003,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x3ffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x3ffd,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x3ffb,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x3ffb,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_immed 0xc0013ffa,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0xc0013ffa,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0xff,accg0 - test_acc_immed 0x80013ffa,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed 0x80013ffa,acc1 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 0xffff,1,fr7 - set_fr_iimmed 1,0xffff,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_fr_iimmed 0x8000,0x0000,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0,1,fr7 - set_fr_iimmed 1,1,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmrdhs fr7,fr8,acc0 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - pass - - diff --git a/sim/testsuite/sim/frv/mmrdhu.cgs b/sim/testsuite/sim/frv/mmrdhu.cgs deleted file mode 100644 index b1c0243c383..00000000000 --- a/sim/testsuite/sim/frv/mmrdhu.cgs +++ /dev/null @@ -1,151 +0,0 @@ -# frv testcase for mmrdhu $GRi,$GRj,$GRk -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global mmrdhu -mmrdhu: - set_accg_immed 0x80,accg0 - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 - test_acc_immed 0xfffffffa,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xfffffffa,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 - test_acc_immed 0xfffffff8,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xfffffff8,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 - test_acc_immed 0xfffffff8,acc0 - test_accg_immed 0x7f,accg1 - test_acc_immed 0xfffffff8,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0x7ffa,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0x7ffa,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xfffe,0xfffa,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xfffe,0xfffa,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xfffd,0xfffa,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xfffd,0xfffa,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xbffe,0xfff9,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xbffe,0xfff9,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0x7ffe,0xfff9,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0x7ffe,0xfff9,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0x7e,accg0 - test_acc_limmed 0x8000,0xfff8,acc0 - test_accg_immed 0x7e,accg1 - test_acc_limmed 0x8000,0xfff8,acc1 - - set_accg_immed 0,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 1,1,fr7 - set_fr_iimmed 1,1,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0xffff,fr7 - set_fr_iimmed 0xffff,0xffff,fr8 - mmrdhu fr7,fr8,acc0 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - pass diff --git a/sim/testsuite/sim/frv/mmulhs.cgs b/sim/testsuite/sim/frv/mmulhs.cgs deleted file mode 100644 index 21045006dab..00000000000 --- a/sim/testsuite/sim/frv/mmulhs.cgs +++ /dev/null @@ -1,141 +0,0 @@ -# frv testcase for mmulhs $GRi,$GRj,$ACCk -# mach: all - - .include "testutils.inc" - - start - - .global mmulhs -mmulhs: - ; Positive operands - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - mmulhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - mmulhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - mmulhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - mmulhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0,0x7ffe,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0,0x7ffe,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - mmulhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8000,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmulhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x0001,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr8 - mmulhs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -6,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -6,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr8 - mmulhs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -2,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -2,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr8 - mmulhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr8 - mmulhs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffe,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffe,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr8 - mmulhs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x8000,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0x8000,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr8 - mmulhs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xc000,0x8000,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xc000,0x8000,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr8 - mmulhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr8 - mmulhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - mmulhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - mmulhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x40000000,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x40000000,acc1 - - pass diff --git a/sim/testsuite/sim/frv/mmulhu.cgs b/sim/testsuite/sim/frv/mmulhu.cgs deleted file mode 100644 index 53e9b7062f5..00000000000 --- a/sim/testsuite/sim/frv/mmulhu.cgs +++ /dev/null @@ -1,82 +0,0 @@ -# frv testcase for mmulhu $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global mmulhu -mmulhu: - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 2,3,fr8 - mmulhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - mmulhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 2,0,fr8 - mmulhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr8 - mmulhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x7ffe,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x7ffe,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 2,0x4000,fr8 - mmulhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8000,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 2,0x8000,fr8 - mmulhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x00010000,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x00010000,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmulhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - mmulhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0000,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - mmulhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0xfffe,0x0001,acc1 - - pass diff --git a/sim/testsuite/sim/frv/mmulxhs.cgs b/sim/testsuite/sim/frv/mmulxhs.cgs deleted file mode 100644 index 449becfb4d9..00000000000 --- a/sim/testsuite/sim/frv/mmulxhs.cgs +++ /dev/null @@ -1,141 +0,0 @@ -# frv testcase for mmulxhs $GRi,$GRj,$ACCk -# mach: all - - .include "testutils.inc" - - start - - .global mmulxhs -mmulxhs: - ; Positive operands - set_fr_iimmed 2,3,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - mmulxhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 4,acc0 - test_accg_immed 0,accg1 - test_acc_immed 9,acc1 - - set_fr_iimmed 0,1,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - mmulxhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 2,1,fr7 ; multiply by 1 - set_fr_iimmed 2,1,fr8 - mmulxhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 0x3fff,2,fr8 - mmulxhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0,0x7ffe,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0,0x7ffe,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 0x4000,2,fr8 - mmulxhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8000,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmulxhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x0001,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 2,0xfffd,fr8 - mmulxhs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -6,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -6,acc1 - - set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr8 - mmulxhs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -2,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -2,acc1 - - set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 - set_fr_iimmed 0xfffe,0,fr8 - mmulxhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result - set_fr_iimmed 0x2001,0xfffe,fr8 - mmulxhs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffe,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffe,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result - set_fr_iimmed 0x4000,0xfffe,fr8 - mmulxhs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x8000,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0x8000,acc1 - - set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result - set_fr_iimmed 0x7fff,0x8000,fr8 - mmulxhs fr7,fr8,acc0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xc000,0x8000,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xc000,0x8000,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers - set_fr_iimmed 0xfffe,0xfffd,fr8 - mmulxhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr8 - mmulxhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - - set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr8 - mmulxhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - mmulxhs fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x40000000,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x40000000,acc1 - - pass diff --git a/sim/testsuite/sim/frv/mmulxhu.cgs b/sim/testsuite/sim/frv/mmulxhu.cgs deleted file mode 100644 index 866b64e50f4..00000000000 --- a/sim/testsuite/sim/frv/mmulxhu.cgs +++ /dev/null @@ -1,82 +0,0 @@ -# frv testcase for mmulxhu $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global mmulxhu -mmulxhu: - set_fr_iimmed 3,2,fr7 ; multiply small numbers - set_fr_iimmed 3,2,fr8 - mmulxhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 1,2,fr7 ; multiply by 1 - set_fr_iimmed 1,2,fr8 - mmulxhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - - set_fr_iimmed 0,2,fr7 ; multiply by 0 - set_fr_iimmed 0,2,fr8 - mmulxhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result - set_fr_iimmed 0x3fff,2,fr8 - mmulxhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x7ffe,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x7ffe,acc1 - - set_fr_iimmed 0x4000,2,fr7 ; 16 bit result - set_fr_iimmed 0x4000,2,fr8 - mmulxhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8000,acc1 - - set_fr_iimmed 0x8000,2,fr7 ; 17 bit result - set_fr_iimmed 0x8000,2,fr8 - mmulxhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x00010000,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x00010000,acc1 - - set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr8 - mmulxhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - - set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr8 - mmulxhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x4000,0x0000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0000,acc1 - - set_fr_iimmed 0xffff,0xffff,fr7 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr8 - mmulxhu fr7,fr8,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0xfffe,0x0001,acc1 - - pass diff --git a/sim/testsuite/sim/frv/mnop.cgs b/sim/testsuite/sim/frv/mnop.cgs deleted file mode 100644 index 54dda66b94c..00000000000 --- a/sim/testsuite/sim/frv/mnop.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# frv testcase for mnop -# mach: all - - .include "testutils.inc" - - start - - .global mnop -mnop: - mnop - - pass diff --git a/sim/testsuite/sim/frv/mnot.cgs b/sim/testsuite/sim/frv/mnot.cgs deleted file mode 100644 index 3a90781a0e8..00000000000 --- a/sim/testsuite/sim/frv/mnot.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# frv testcase for mnot $FRintj,$FRintk -# mach: all - - .include "testutils.inc" - - start - - .global mnot -mnot: - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - mnot fr7,fr7 - test_fr_iimmed 0x55555555,fr7 - - set_fr_iimmed 0xdead,0xbeef,fr7 - mnot fr7,fr7 - test_fr_iimmed 0x21524110,fr7 - - pass diff --git a/sim/testsuite/sim/frv/mor.cgs b/sim/testsuite/sim/frv/mor.cgs deleted file mode 100644 index 72feaffb64d..00000000000 --- a/sim/testsuite/sim/frv/mor.cgs +++ /dev/null @@ -1,25 +0,0 @@ -# frv testcase for mor $FRinti,$FRintj,$FRintk -# mach: all - - .include "testutils.inc" - - start - - .global mor -mor: - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - mor fr7,fr8,fr8 - test_fr_iimmed 0xffffffff,fr8 - - set_fr_iimmed 0x0000,0x0000,fr7 - set_fr_iimmed 0x0000,0x0000,fr8 - mor fr7,fr8,fr8 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xdead,0x0000,fr7 - set_fr_iimmed 0x0000,0xbeef,fr8 - mor fr7,fr8,fr8 - test_fr_iimmed 0xdeadbeef,fr8 - - pass diff --git a/sim/testsuite/sim/frv/mov.cgs b/sim/testsuite/sim/frv/mov.cgs deleted file mode 100644 index 8a077eb5e54..00000000000 --- a/sim/testsuite/sim/frv/mov.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# frv testcase for mov $GRi,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ori -ori: - set_gr_immed 0xdeadbeef,gr7 - set_gr_immed 0xbeefdead,gr8 - set_icc 0x08,0 - mov gr7,gr8 - test_icc 1 0 0 0 icc0 - test_gr_immed 0xdeadbeef,gr7 - test_gr_immed 0xdeadbeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/movfg.cgs b/sim/testsuite/sim/frv/movfg.cgs deleted file mode 100644 index c3da00ec16b..00000000000 --- a/sim/testsuite/sim/frv/movfg.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# frv testcase for movfg $FRk,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global movfg -movfg: - set_fr_iimmed 0xdead,0xbeef,fr8 - set_gr_limmed 0,0,gr8 - movfg fr8,gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - pass diff --git a/sim/testsuite/sim/frv/movfgd.cgs b/sim/testsuite/sim/frv/movfgd.cgs deleted file mode 100644 index cc2d60de0ff..00000000000 --- a/sim/testsuite/sim/frv/movfgd.cgs +++ /dev/null @@ -1,20 +0,0 @@ -# frv testcase for movfgd $FRk,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global movfgd -movfgd: - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_gr_limmed 0,0,gr8 - set_gr_limmed 0,0,gr9 - movfgd fr8,gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - pass diff --git a/sim/testsuite/sim/frv/movfgq.cgs b/sim/testsuite/sim/frv/movfgq.cgs deleted file mode 100644 index b3a90e817ad..00000000000 --- a/sim/testsuite/sim/frv/movfgq.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# frv testcase for movfgq $FRk,$GRj -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global movfgq -movfgq: - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - set_gr_limmed 0,0,gr8 - set_gr_limmed 0,0,gr9 - set_gr_limmed 0,0,gr10 - set_gr_limmed 0,0,gr11 - movfgq fr8,gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - test_fr_limmed 0x1234,0x5678,fr10 - test_fr_limmed 0x9abc,0xdef0,fr11 - - pass diff --git a/sim/testsuite/sim/frv/movgf.cgs b/sim/testsuite/sim/frv/movgf.cgs deleted file mode 100644 index 40fae33f072..00000000000 --- a/sim/testsuite/sim/frv/movgf.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# frv testcase for movgf $GRj,$FRk -# mach: all - - .include "testutils.inc" - - start - - .global movgf -movgf: - set_gr_limmed 0xdead,0xbeef,gr8 - set_fr_iimmed 0,0,fr8 - movgf gr8,fr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_fr_limmed 0xdead,0xbeef,fr8 - - pass diff --git a/sim/testsuite/sim/frv/movgfd.cgs b/sim/testsuite/sim/frv/movgfd.cgs deleted file mode 100644 index df844ccf6cb..00000000000 --- a/sim/testsuite/sim/frv/movgfd.cgs +++ /dev/null @@ -1,20 +0,0 @@ -# frv testcase for movgfd $GRj,$FRk -# mach: all - - .include "testutils.inc" - - start - - .global movgfd -movgfd: - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_fr_iimmed 0,0,fr8 - set_fr_iimmed 0,0,fr9 - movgfd gr8,fr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - - pass diff --git a/sim/testsuite/sim/frv/movgfq.cgs b/sim/testsuite/sim/frv/movgfq.cgs deleted file mode 100644 index 0196133496a..00000000000 --- a/sim/testsuite/sim/frv/movgfq.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# frv testcase for movgfq $GRj,$FRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global movgfq -movgfq: - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - set_fr_iimmed 0,0,fr8 - set_fr_iimmed 0,0,fr9 - set_fr_iimmed 0,0,fr10 - set_fr_iimmed 0,0,fr11 - movgfq gr8,fr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_limmed 0xbeef,0xdead,gr9 - test_gr_limmed 0x1234,0x5678,gr10 - test_gr_limmed 0x9abc,0xdef0,gr11 - test_fr_limmed 0xdead,0xbeef,fr8 - test_fr_limmed 0xbeef,0xdead,fr9 - test_fr_limmed 0x1234,0x5678,fr10 - test_fr_limmed 0x9abc,0xdef0,fr11 - - pass diff --git a/sim/testsuite/sim/frv/movgs.cgs b/sim/testsuite/sim/frv/movgs.cgs deleted file mode 100644 index f9d2f549932..00000000000 --- a/sim/testsuite/sim/frv/movgs.cgs +++ /dev/null @@ -1,22 +0,0 @@ -# frv testcase for movgs $GRj,$FRk -# mach: all - - .include "testutils.inc" - - start - - .global movgs -movgs: - set_gr_limmed 0xdead,0xbeef,gr8 - and_spr_immed 0,lcr - movgs gr8,lcr - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,lcr - - ; try alternate names for lcr - and_spr_immed 0,273 - movgs gr8,spr[273] ; lcr is spr number 273 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,spr[273] - - pass diff --git a/sim/testsuite/sim/frv/movsg.cgs b/sim/testsuite/sim/frv/movsg.cgs deleted file mode 100644 index b26dbc18a57..00000000000 --- a/sim/testsuite/sim/frv/movsg.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# frv testcase for movsg $FRk,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global movsg -movsg: - set_spr_limmed 0xdead,0xbeef,lcr - set_gr_limmed 0,0,gr8 - movsg lcr,gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0xdead,0xbeef,lcr - - pass diff --git a/sim/testsuite/sim/frv/mpackh.cgs b/sim/testsuite/sim/frv/mpackh.cgs deleted file mode 100644 index 5a87cc6b5d0..00000000000 --- a/sim/testsuite/sim/frv/mpackh.cgs +++ /dev/null @@ -1,15 +0,0 @@ -# frv testcase for mpackh $FRi,$FRj,$FRj -# mach: all - - .include "testutils.inc" - - start - - .global mpackh -mpackh: - set_fr_iimmed 0xdead,0xbeef,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - mpackh fr10,fr11,fr12 - test_fr_limmed 0xbeef,0x5678,fr12 - - pass diff --git a/sim/testsuite/sim/frv/mqcpxis.cgs b/sim/testsuite/sim/frv/mqcpxis.cgs deleted file mode 100644 index 397f5335d21..00000000000 --- a/sim/testsuite/sim/frv/mqcpxis.cgs +++ /dev/null @@ -1,103 +0,0 @@ -# frv testcase for mqcpxis $GRi,$GRj,$ACCk -# mach: all - - .include "testutils.inc" - - start - - .global mqcpxis -mqcpxis: - ; Positive operands - set_fr_iimmed 2,4,fr8 ; multiply small numbers - set_fr_iimmed 5,3,fr10 - set_fr_iimmed 3,1,fr9 ; multiply by 0 - set_fr_iimmed 0,2,fr11 - mqcpxis fr8,fr10,acc0 - test_accg_immed 0x00,accg0 - test_acc_immed 26,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x3fff,1,fr9 ; 15 bit result - set_fr_iimmed 0x0001,2,fr11 - mqcpxis fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 3,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0,0x7fff,acc1 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 0x2000,2,fr10 - set_fr_iimmed 0x7fff,0x0000,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqcpxis fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0xc000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x0001,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 1,0xfffd,fr10 - set_fr_iimmed 0xfffe,2,fr9 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr11 - mqcpxis fr8,fr10,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -9,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -6,acc1 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0xfffe,1,fr10 - set_fr_iimmed 0x2001,0xffff,fr9 ; 15 bit result - set_fr_iimmed 0xffff,0xfffe,fr11 - mqcpxis fr8,fr10,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -2,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbfff,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0x0003,0xfffe,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr11 - mqcpxis fr8,fr10,acc0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x7ffa,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0x8001,0x0000,acc1 - - ; Negative operands - set_fr_iimmed 0x8000,0x8000,fr8 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0xfffe,0xfffc,fr9 ; multiply small numbers - set_fr_iimmed 0xfffb,0xfffd,fr11 - mqcpxis fr8,fr10,acc0 - test_accg_immed 0x00,accg0 - test_acc_limmed 0x8000,0x0000,acc0 - test_accg_immed 0x00,accg1 - test_acc_immed 26,acc1 - - set_fr_iimmed 0xffff,0xffff,fr8 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr10 - set_fr_iimmed 0x7fff,0x0000,fr9 ; almost max positive result - set_fr_iimmed 0x8001,0x7fff,fr11 - mqcpxis fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 3,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - - set_fr_iimmed 0x8000,0x0000,fr8 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0x8000,0x0000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - mqcpxis fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x40000000,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x40000000,acc1 - - pass diff --git a/sim/testsuite/sim/frv/mqcpxiu.cgs b/sim/testsuite/sim/frv/mqcpxiu.cgs deleted file mode 100644 index 22d48f6333c..00000000000 --- a/sim/testsuite/sim/frv/mqcpxiu.cgs +++ /dev/null @@ -1,60 +0,0 @@ -# frv testcase for mqcpxiu $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global mqcpxiu -mqcpxiu: - set_fr_iimmed 4,2,fr8 ; multiply small numbers - set_fr_iimmed 3,5,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 1,3,fr11 - mqcpxiu fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 26,acc0 - test_accg_immed 0,accg1 - test_acc_immed 5,acc1 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 0,2,fr10 - set_fr_iimmed 0x3fff,1,fr9 ; 15 bit result - set_fr_iimmed 0x0001,2,fr11 - mqcpxiu fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x7fff,acc1 - - set_fr_iimmed 0x4000,1,fr8 ; 16 bit result - set_fr_iimmed 0x0001,2,fr10 - set_fr_iimmed 0x4000,1,fr9 ; 17 bit result - set_fr_iimmed 0x0001,4,fr11 - mqcpxiu fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x0010001,acc1 - - set_fr_iimmed 0x7fff,0x0000,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x0000,0x8000,fr11 - mqcpxiu fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0000,acc1 - - set_fr_iimmed 0xffff,0x0000,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - mqcpxiu fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - test_accg_immed 1,accg1 - test_acc_immed 0xfffc0002,acc1 - - pass diff --git a/sim/testsuite/sim/frv/mqcpxrs.cgs b/sim/testsuite/sim/frv/mqcpxrs.cgs deleted file mode 100644 index d1d1f48db1c..00000000000 --- a/sim/testsuite/sim/frv/mqcpxrs.cgs +++ /dev/null @@ -1,103 +0,0 @@ -# frv testcase for mqcpxrs $GRi,$GRj,$ACCk -# mach: all - - .include "testutils.inc" - - start - - .global mqcpxrs -mqcpxrs: - ; Positive operands - set_fr_iimmed 2,4,fr8 ; multiply small numbers - set_fr_iimmed 3,5,fr10 - set_fr_iimmed 3,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - mqcpxrs fr8,fr10,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -14,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x0007,fr11 - mqcpxrs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 1,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0,0x7ff0,acc1 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x2000,fr10 - set_fr_iimmed 0x7fff,0x0000,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqcpxrs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x4000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x0001,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,1,fr10 - set_fr_iimmed 0xfffe,2,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - mqcpxrs fr8,fr10,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -3,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 1,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0xfff9,fr11 - mqcpxrs fr8,fr10,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -2,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbff0,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x0003,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x8000,fr11 - mqcpxrs fr8,fr10,acc0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x8006,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0x8000,0x8000,acc1 - - ; Negative operands - set_fr_iimmed 0x8000,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0xfffe,0xfffc,fr9 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffb,fr11 - mqcpxrs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x7fff,0x8000,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -14,acc1 - - set_fr_iimmed 0xffff,0xffff,fr8 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr10 - set_fr_iimmed 0x7fff,0x0000,fr9 ; almost max positive result - set_fr_iimmed 0x7fff,0x8001,fr11 - mqcpxrs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 1,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - - set_fr_iimmed 0x8000,0x0000,fr8 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr10 - set_fr_iimmed 0x8000,0x0000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - mqcpxrs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x40000000,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x40000000,acc1 - - pass diff --git a/sim/testsuite/sim/frv/mqcpxru.cgs b/sim/testsuite/sim/frv/mqcpxru.cgs deleted file mode 100644 index 45e1b358bed..00000000000 --- a/sim/testsuite/sim/frv/mqcpxru.cgs +++ /dev/null @@ -1,78 +0,0 @@ -# frv testcase for mqcpxru $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global mqcpxru -mqcpxru: - set_fr_iimmed 4,2,fr8 ; multiply small numbers - set_fr_iimmed 5,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 3,1,fr11 - mqcpxru fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 14,acc0 - test_accg_immed 0,accg1 - test_acc_immed 1,acc1 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,1,fr9 ; 15 bit result - set_fr_iimmed 2,0x0001,fr11 - mqcpxru fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x7ffd,acc1 - - set_fr_iimmed 0x4000,1,fr8 ; 16 bit result - set_fr_iimmed 4,0x0001,fr10 - set_fr_iimmed 0x8000,1,fr9 ; 17 bit result - set_fr_iimmed 4,0x0001,fr11 - mqcpxru fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0xffff,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x0001ffff,acc1 - - set_fr_iimmed 0x7fff,0x0000,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x0000,fr11 - mqcpxru fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x4000,0x0000,acc1 - - set_fr_iimmed 0xffff,0x0000,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0x0000,0x0001,fr9 ; saturation - set_fr_iimmed 0xffff,0x0001,fr11 - mqcpxru fr8,fr10,acc0 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - set_fr_iimmed 0x0000,0xffff,fr8 ; saturation - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xfffe,0xffff,fr9 ; saturation - set_fr_iimmed 0xffff,0xffff,fr11 - mqcpxru fr8,fr10,acc0 - test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - - pass diff --git a/sim/testsuite/sim/frv/mqmachs.cgs b/sim/testsuite/sim/frv/mqmachs.cgs deleted file mode 100644 index 5608c647150..00000000000 --- a/sim/testsuite/sim/frv/mqmachs.cgs +++ /dev/null @@ -1,211 +0,0 @@ -# frv testcase for mqmachs $GRi,$GRj,$ACCk -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global mqmachs -mqmachs: - ; Positive operands - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0,0x7ffe,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0,0x7ffe,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8008,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8008,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x7fff,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x7fff,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8002,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x7ffd,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x7ffd,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8002,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x3ffb,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x3ffb,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0002,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffb,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffb,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0008,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0008,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffd,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffd,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0009,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0009,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x3fffbffd,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x3fffbffd,acc3 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 1,0xffff,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0x80,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - - pass - - diff --git a/sim/testsuite/sim/frv/mqmachu.cgs b/sim/testsuite/sim/frv/mqmachu.cgs deleted file mode 100644 index e16be68bd6b..00000000000 --- a/sim/testsuite/sim/frv/mqmachu.cgs +++ /dev/null @@ -1,144 +0,0 @@ -# frv testcase for mqmachu $GRi,$GRj,$GRk -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global mqmachu -mqmachu: - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - mqmachu fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 2,acc2 - test_accg_immed 0,accg3 - test_acc_immed 2,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - mqmachu fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8000,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - mqmachu fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8006,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8006,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x00018000,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x00018000,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - mqmachu fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x3fff8007,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff8007,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x4001,0x8000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x4001,0x8000,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - mqmachu fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 1,accg0 - test_acc_limmed 0x3ffd,0x8008,acc0 - test_accg_immed 1,accg1 - test_acc_limmed 0x3ffd,0x8008,acc1 - test_accg_immed 1,accg2 - test_acc_limmed 0x3fff,0x8001,acc2 - test_accg_immed 1,accg3 - test_acc_limmed 0x3fff,0x8001,acc3 - - set_accg_immed 0xff,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0xff,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0xff,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0xff,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 1,1,fr9 - set_fr_iimmed 1,1,fr11 - mqmachu fr8,fr10,acc0 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_fr_iimmed 0xffff,0x0000,fr8 - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0x0000,0xffff,fr9 - set_fr_iimmed 0xffff,0xffff,fr11 - mqmachu fr8,fr10,acc0 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - pass diff --git a/sim/testsuite/sim/frv/mqmacxhs.cgs b/sim/testsuite/sim/frv/mqmacxhs.cgs deleted file mode 100644 index 0be1151c69a..00000000000 --- a/sim/testsuite/sim/frv/mqmacxhs.cgs +++ /dev/null @@ -1,211 +0,0 @@ -# frv testcase for mqmacxhs $GRi,$GRj,$ACCk -# mach: fr400 - - .include "testutils.inc" - - start - - .global mqmacxhs -mqmacxhs: - ; Positive operands - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 0,2,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 2,1,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 0x3fff,2,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 8,acc0 - test_accg_immed 0,accg1 - test_acc_immed 8,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0,0x7ffe,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0,0x7ffe,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 0x4000,2,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8008,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8008,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x7fff,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x7fff,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 2,0xfffd,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8002,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x7ffd,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x7ffd,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0xfffe,0,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0x2001,0xfffe,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8002,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x3ffb,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x3ffb,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0x4000,0xfffe,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x7fff,0x8000,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0002,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0002,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffb,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffb,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffe,0xfffd,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x0008,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x0008,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffd,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffd,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0009,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0009,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x3fffbffd,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x3fffbffd,acc3 - - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 0xffff,1,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0x80,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - - pass - - diff --git a/sim/testsuite/sim/frv/mqmulhs.cgs b/sim/testsuite/sim/frv/mqmulhs.cgs deleted file mode 100644 index 0a10c2908ce..00000000000 --- a/sim/testsuite/sim/frv/mqmulhs.cgs +++ /dev/null @@ -1,125 +0,0 @@ -# frv testcase for mqmulhs $GRi,$GRj,$ACCk -# mach: all - - .include "testutils.inc" - - start - - .global mqmulhs -mqmulhs: - ; Positive operands - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - mqmulhs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - mqmulhs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0,0x7ffe,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0,0x7ffe,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqmulhs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8000,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x0001,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x0001,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - mqmulhs fr8,fr10,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -6,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -6,acc1 - test_accg_immed 0xff,accg2 - test_acc_immed -2,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed -2,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - mqmulhs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffe,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffe,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - mqmulhs fr8,fr10,acc0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x8000,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0x8000,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xc000,0x8000,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xc000,0x8000,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - mqmulhs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 2,acc2 - test_accg_immed 0,accg3 - test_acc_immed 2,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - mqmulhs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x40000000,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x40000000,acc3 - - pass diff --git a/sim/testsuite/sim/frv/mqmulhu.cgs b/sim/testsuite/sim/frv/mqmulhu.cgs deleted file mode 100644 index e94c09ae97e..00000000000 --- a/sim/testsuite/sim/frv/mqmulhu.cgs +++ /dev/null @@ -1,80 +0,0 @@ -# frv testcase for mqmulhu $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global mqmulhu -mqmulhu: - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 2,1,fr11 - mqmulhu fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 2,acc2 - test_accg_immed 0,accg3 - test_acc_immed 2,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 2,0,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - mqmulhu fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x7ffe,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x7ffe,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 2,0x8000,fr11 - mqmulhu fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8000,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x00010000,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x00010000,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - mqmulhu fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x4000,0x0000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x4000,0x0000,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - mqmulhu fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0xfffe,0x0001,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0xfffe,0x0001,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0xfffe,0x0001,acc3 - - pass diff --git a/sim/testsuite/sim/frv/mqmulxhs.cgs b/sim/testsuite/sim/frv/mqmulxhs.cgs deleted file mode 100644 index 7686bc1cf5c..00000000000 --- a/sim/testsuite/sim/frv/mqmulxhs.cgs +++ /dev/null @@ -1,125 +0,0 @@ -# frv testcase for mqmulxhs $GRi,$GRj,$ACCk -# mach: all - - .include "testutils.inc" - - start - - .global mqmulxhs -mqmulxhs: - ; Positive operands - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 0,2,fr11 - mqmulxhs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 4,acc0 - test_accg_immed 0,accg1 - test_acc_immed 9,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 2,1,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 0x3fff,2,fr11 - mqmulxhs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 2,acc0 - test_accg_immed 0,accg1 - test_acc_immed 2,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0,0x7ffe,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0,0x7ffe,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 0x4000,2,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqmulxhs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8000,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x3fff,0x0001,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x3fff,0x0001,acc3 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 2,0xfffd,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr11 - mqmulxhs fr8,fr10,acc0 - test_accg_immed 0xff,accg0 - test_acc_immed -6,acc0 - test_accg_immed 0xff,accg1 - test_acc_immed -6,acc1 - test_accg_immed 0xff,accg2 - test_acc_immed -2,acc2 - test_accg_immed 0xff,accg3 - test_acc_immed -2,acc3 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0xfffe,0,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0x2001,0xfffe,fr11 - mqmulxhs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xffff,0xbffe,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xffff,0xbffe,acc3 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0x4000,0xfffe,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x7fff,0x8000,fr11 - mqmulxhs fr8,fr10,acc0 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0x8000,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0x8000,acc1 - test_accg_immed 0xff,accg2 - test_acc_limmed 0xc000,0x8000,acc2 - test_accg_immed 0xff,accg3 - test_acc_limmed 0xc000,0x8000,acc3 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffe,0xfffd,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr11 - mqmulxhs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 2,acc2 - test_accg_immed 0,accg3 - test_acc_immed 2,acc3 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - mqmulxhs fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x40000000,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x40000000,acc3 - - pass diff --git a/sim/testsuite/sim/frv/mqmulxhu.cgs b/sim/testsuite/sim/frv/mqmulxhu.cgs deleted file mode 100644 index b60e421bc73..00000000000 --- a/sim/testsuite/sim/frv/mqmulxhu.cgs +++ /dev/null @@ -1,80 +0,0 @@ -# frv testcase for mqmulxhu $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global mqmulxhu -mqmulxhu: - set_fr_iimmed 3,2,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 1,2,fr9 ; multiply by 1 - set_fr_iimmed 1,2,fr11 - mqmulxhu fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 6,acc0 - test_accg_immed 0,accg1 - test_acc_immed 6,acc1 - test_accg_immed 0,accg2 - test_acc_immed 2,acc2 - test_accg_immed 0,accg3 - test_acc_immed 2,acc3 - - set_fr_iimmed 0,2,fr8 ; multiply by 0 - set_fr_iimmed 0,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 0x3fff,2,fr11 - mqmulxhu fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x7ffe,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x7ffe,acc3 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 0x4000,2,fr10 - set_fr_iimmed 0x8000,2,fr9 ; 17 bit result - set_fr_iimmed 0x8000,2,fr11 - mqmulxhu fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0x0000,0x8000,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x0000,0x8000,acc1 - test_accg_immed 0,accg2 - test_acc_immed 0x00010000,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x00010000,acc3 - - set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - mqmulxhu fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_immed 0x3fff0001,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fff0001,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0x4000,0x0000,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x4000,0x0000,acc3 - - set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result - set_fr_iimmed 0xffff,0xffff,fr11 - mqmulxhu fr8,fr10,acc0 - test_accg_immed 0,accg0 - test_acc_limmed 0xfffe,0x0001,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0xfffe,0x0001,acc1 - test_accg_immed 0,accg2 - test_acc_limmed 0xfffe,0x0001,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0xfffe,0x0001,acc3 - - pass diff --git a/sim/testsuite/sim/frv/mqsaths.cgs b/sim/testsuite/sim/frv/mqsaths.cgs deleted file mode 100644 index 61ff112b5c6..00000000000 --- a/sim/testsuite/sim/frv/mqsaths.cgs +++ /dev/null @@ -1,50 +0,0 @@ -# frv testcase for mqsaths $FRi,$FRj,$FRj -# mach: fr400 fr550 - - .include "testutils.inc" - - start - - .global mqsaths -mqsaths: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0001,0x7fff,fr11 - set_fr_iimmed 0x0000,0x0000,fr13 - mqsaths fr10,fr12,fr14 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - - set_fr_iimmed 0xffff,0x8000,fr10 - set_fr_iimmed 0x0000,0x0000,fr12 - set_fr_iimmed 0x0000,0x0000,fr11 - set_fr_iimmed 0x0040,0x0040,fr13 - mqsaths fr10,fr12,fr14 - test_fr_limmed 0xffff,0xffff,fr14 - test_fr_limmed 0x0000,0x0000,fr15 - - set_fr_iimmed 0x0001,0x7fff,fr10 - set_fr_iimmed 0x0040,0x0040,fr12 - set_fr_iimmed 0xffff,0x8000,fr11 - set_fr_iimmed 0x0040,0x0040,fr13 - mqsaths fr10,fr12,fr14 - test_fr_limmed 0x0001,0x0040,fr14 - test_fr_limmed 0xffff,0xffbf,fr15 - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr12 - set_fr_iimmed 0x0001,0x7fff,fr11 - set_fr_iimmed 0x7fff,0x7fff,fr13 - mqsaths fr10,fr12,fr14 - test_fr_limmed 0x0000,0x0000,fr14 - test_fr_limmed 0x0001,0x7fff,fr15 - - set_fr_iimmed 0xffff,0x8000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr12 - set_fr_iimmed 0xffff,0x8000,fr11 - set_fr_iimmed 0x7fff,0x7fff,fr13 - mqsaths fr10,fr12,fr14 - test_fr_limmed 0xffff,0x8000,fr14 - test_fr_limmed 0xffff,0x8000,fr15 - - pass diff --git a/sim/testsuite/sim/frv/mqxmachs.cgs b/sim/testsuite/sim/frv/mqxmachs.cgs deleted file mode 100644 index 6791ed31874..00000000000 --- a/sim/testsuite/sim/frv/mqxmachs.cgs +++ /dev/null @@ -1,211 +0,0 @@ -# frv testcase for mqxmachs $GRi,$GRj,$ACCk -# mach: fr400 - - .include "testutils.inc" - - start - - .global mqxmachs -mqxmachs: - ; Positive operands - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 3,2,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 2,0,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0,accg2 - test_acc_immed 6,acc2 - test_accg_immed 0,accg3 - test_acc_immed 6,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 1,2,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 2,0x3fff,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_immed 8,acc2 - test_accg_immed 0,accg3 - test_acc_immed 8,acc3 - test_accg_immed 0,accg0 - test_acc_limmed 0,0x7ffe,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0,0x7ffe,acc1 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 2,0x4000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8008,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8008,acc3 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x7fff,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x7fff,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,2,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 1,0xfffe,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8002,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8002,acc3 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x7ffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x7ffd,acc1 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0,0xfffe,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0xfffe,0x2001,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8002,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8002,acc3 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x3ffb,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x3ffb,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0xfffe,0x4000,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x8000,0x7fff,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0002,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x0002,acc3 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffb,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffb,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffd,0xfffe,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xfffe,0xffff,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0008,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x0008,acc3 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffd,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffd,acc1 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_immed 0x3fff0009,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x3fff0009,acc3 - test_accg_immed 0,accg0 - test_acc_immed 0x3fffbffd,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fffbffd,acc1 - - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 1,0xffff,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqxmachs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - pass - - diff --git a/sim/testsuite/sim/frv/mqxmacxhs.cgs b/sim/testsuite/sim/frv/mqxmacxhs.cgs deleted file mode 100644 index c644eed231c..00000000000 --- a/sim/testsuite/sim/frv/mqxmacxhs.cgs +++ /dev/null @@ -1,211 +0,0 @@ -# frv testcase for mqxmacxhs $GRi,$GRj,$ACCk -# mach: fr400 - - .include "testutils.inc" - - start - - .global mqxmacxhs -mqxmacxhs: - ; Positive operands - set_fr_iimmed 2,3,fr8 ; multiply small numbers - set_fr_iimmed 2,3,fr10 - set_fr_iimmed 0,1,fr9 ; multiply by 0 - set_fr_iimmed 0,2,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0,acc1 - test_accg_immed 0,accg2 - test_acc_immed 6,acc2 - test_accg_immed 0,accg3 - test_acc_immed 6,acc3 - - set_fr_iimmed 2,1,fr8 ; multiply by 1 - set_fr_iimmed 2,1,fr10 - set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result - set_fr_iimmed 0x3fff,2,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_immed 8,acc2 - test_accg_immed 0,accg3 - test_acc_immed 8,acc3 - test_accg_immed 0,accg0 - test_acc_limmed 0,0x7ffe,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0,0x7ffe,acc1 - - set_fr_iimmed 0x4000,2,fr8 ; 16 bit result - set_fr_iimmed 0x4000,2,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; max positive result - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8008,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8008,acc3 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x7fff,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x7fff,acc1 - - ; Mixed operands - set_fr_iimmed 2,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 2,0xfffd,fr10 - set_fr_iimmed 0xfffe,1,fr9 ; multiply by 1 - set_fr_iimmed 0xfffe,1,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8002,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8002,acc3 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x7ffd,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x7ffd,acc1 - - set_fr_iimmed 0xfffe,0,fr8 ; multiply by 0 - set_fr_iimmed 0xfffe,0,fr10 - set_fr_iimmed 0x2001,0xfffe,fr9 ; 15 bit result - set_fr_iimmed 0x2001,0xfffe,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x8002,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x8002,acc3 - test_accg_immed 0,accg0 - test_acc_limmed 0x3fff,0x3ffb,acc0 - test_accg_immed 0,accg1 - test_acc_limmed 0x3fff,0x3ffb,acc1 - - set_fr_iimmed 0x4000,0xfffe,fr8 ; 16 bit result - set_fr_iimmed 0x4000,0xfffe,fr10 - set_fr_iimmed 0x7fff,0x8000,fr9 ; max negative result - set_fr_iimmed 0x7fff,0x8000,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0002,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x0002,acc3 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffb,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffb,acc1 - - ; Negative operands - set_fr_iimmed 0xfffe,0xfffd,fr8 ; multiply small numbers - set_fr_iimmed 0xfffe,0xfffd,fr10 - set_fr_iimmed 0xffff,0xfffe,fr9 ; multiply by -1 - set_fr_iimmed 0xffff,0xfffe,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_limmed 0x0000,0x0008,acc2 - test_accg_immed 0,accg3 - test_acc_limmed 0x0000,0x0008,acc3 - test_accg_immed 0xff,accg0 - test_acc_limmed 0xffff,0xbffd,acc0 - test_accg_immed 0xff,accg1 - test_acc_limmed 0xffff,0xbffd,acc1 - - set_fr_iimmed 0x8001,0x8001,fr8 ; almost max positive result - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result - set_fr_iimmed 0x8000,0x8000,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - test_accg_immed 0,accg2 - test_acc_immed 0x3fff0009,acc2 - test_accg_immed 0,accg3 - test_acc_immed 0x3fff0009,acc3 - test_accg_immed 0,accg0 - test_acc_immed 0x3fffbffd,acc0 - test_accg_immed 0,accg1 - test_acc_immed 0x3fffbffd,acc1 - - set_accg_immed 0x7f,accg2 ; saturation - set_acc_immed 0xffffffff,acc2 - set_accg_immed 0x7f,accg3 - set_acc_immed 0xffffffff,acc3 - set_accg_immed 0x7f,accg0 ; saturation - set_acc_immed 0xffffffff,acc0 - set_accg_immed 0x7f,accg1 - set_acc_immed 0xffffffff,acc1 - set_fr_iimmed 1,1,fr8 - set_fr_iimmed 1,1,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x7f,accg2 - test_acc_limmed 0xffff,0xffff,acc2 - test_accg_immed 0x7f,accg3 - test_acc_limmed 0xffff,0xffff,acc3 - test_accg_immed 0x7f,accg0 - test_acc_limmed 0xffff,0xffff,acc0 - test_accg_immed 0x7f,accg1 - test_acc_limmed 0xffff,0xffff,acc1 - - set_accg_immed 0x80,accg2 ; saturation - set_acc_immed 0,acc2 - set_accg_immed 0x80,accg3 - set_acc_immed 0,acc3 - set_accg_immed 0x80,accg0 ; saturation - set_acc_immed 0,acc0 - set_accg_immed 0x80,accg1 - set_acc_immed 0,acc1 - set_fr_iimmed 0xffff,0,fr8 - set_fr_iimmed 0xffff,1,fr10 - set_fr_iimmed 0x0000,0x8000,fr9 ; saturation - set_fr_iimmed 0x7fff,0x7fff,fr11 - mqxmacxhs fr8,fr10,acc0 - test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf is set - test_spr_bits 1,0,1,msr0 ; msr0.aovf is set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set - test_accg_immed 0x80,accg2 - test_acc_immed 0,acc2 - test_accg_immed 0x80,accg3 - test_acc_immed 0,acc3 - test_accg_immed 0x80,accg0 - test_acc_immed 0,acc0 - test_accg_immed 0x80,accg1 - test_acc_immed 0,acc1 - - pass - - diff --git a/sim/testsuite/sim/frv/mrdacc.cgs b/sim/testsuite/sim/frv/mrdacc.cgs deleted file mode 100644 index 217803655b6..00000000000 --- a/sim/testsuite/sim/frv/mrdacc.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for mrdacc $ACC40i,$FRintk -# mach: all - - .include "testutils.inc" - - start - - .global mrdacc -mrdacc: - set_accg_immed 0,accg0 - set_acc_immed 0,acc0 - set_accg_immed -1,accg3 - set_acc_immed -1,acc3 - set_accg_immed 0x12,accg2 - set_acc_immed 0xdeadbeef,acc2 - - mrdacc acc0,fr10 - test_fr_iimmed 0,fr10 - - mrdacc acc3,fr10 - test_fr_iimmed 0xffffffff,fr10 - - mrdacc acc2,fr10 - test_fr_iimmed 0xdeadbeef,fr10 - - pass diff --git a/sim/testsuite/sim/frv/mrdaccg.cgs b/sim/testsuite/sim/frv/mrdaccg.cgs deleted file mode 100644 index 96e94065e63..00000000000 --- a/sim/testsuite/sim/frv/mrdaccg.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for mrdaccg $ACC40i,$FRintk -# mach: all - - .include "testutils.inc" - - start - - .global mrdaccg -mrdaccg: - set_accg_immed 0,accg0 - set_acc_immed 0,acc0 - set_accg_immed -1,accg3 - set_acc_immed -1,acc3 - set_accg_immed 0x12,accg2 - set_acc_immed 0xdeadbeef,acc2 - - mrdaccg accg0,fr10 - test_fr_iimmed 0,fr10 - - mrdaccg accg3,fr10 - test_fr_iimmed 0x000000ff,fr10 - - mrdaccg accg2,fr10 - test_fr_iimmed 0x00000012,fr10 - - pass diff --git a/sim/testsuite/sim/frv/mrotli.cgs b/sim/testsuite/sim/frv/mrotli.cgs deleted file mode 100644 index 02220ee4942..00000000000 --- a/sim/testsuite/sim/frv/mrotli.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# frv testcase for mrotli $FRi,$s6,$FRk -# mach: all - - .include "testutils.inc" - - start - - .global mrotli -mrotli: - set_fr_iimmed 0,2,fr8 - mrotli fr8,0x20,fr8 ; Shift by 0 - test_fr_iimmed 2,fr8 - - set_fr_iimmed 0,2,fr8 - mrotli fr8,0,fr8 ; Shift by 0 - test_fr_iimmed 2,fr8 - - set_fr_iimmed 0,2,fr8 - mrotli fr8,1,fr8 ; Shift by 1 - test_fr_iimmed 4,fr8 - - set_fr_iimmed 0,1,fr8 - mrotli fr8,31,fr8 ; Shift by 31 - test_fr_iimmed 0x80000000,fr8 - - set_fr_iimmed 0,2,fr8 - mrotli fr8,31,fr8 ; max rotation - test_fr_iimmed 1,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr8 - mrotli fr8,16,fr8 - test_fr_iimmed 0xbeefdead,fr8 - - pass diff --git a/sim/testsuite/sim/frv/mrotri.cgs b/sim/testsuite/sim/frv/mrotri.cgs deleted file mode 100644 index 17a5c74e7e7..00000000000 --- a/sim/testsuite/sim/frv/mrotri.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# frv testcase for mrotri $FRinti,$s6,$FRintk -# mach: all - - .include "testutils.inc" - - start - - .global mrotri -mrotri: - set_fr_iimmed 0x8000,0x0000,fr8 - mrotri fr8,0x20,fr8 ; Shift by 0 - test_fr_iimmed 0x80000000,fr8 - - set_fr_iimmed 0x8000,0x0000,fr8 - mrotri fr8,0,fr8 ; Shift by 0 - test_fr_iimmed 0x80000000,fr8 - - set_fr_iimmed 0x8000,0x0000,fr8 - mrotri fr8,1,fr8 ; Shift by 1 - test_fr_iimmed 0x40000000,fr8 - - set_fr_iimmed 0x8000,0x0000,fr8 - mrotri fr8,31,fr8 ; Shift by 31 - test_fr_iimmed 1,fr8 - - set_fr_iimmed 0x4000,0x0000,fr8 - mrotri fr8,31,fr8 ; max shift - test_fr_iimmed 0x80000000,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr8 - mrotri fr8,16,fr8 ; max shift - test_fr_iimmed 0xbeefdead,fr8 - - pass diff --git a/sim/testsuite/sim/frv/msaths.cgs b/sim/testsuite/sim/frv/msaths.cgs deleted file mode 100644 index 513d5d3d66a..00000000000 --- a/sim/testsuite/sim/frv/msaths.cgs +++ /dev/null @@ -1,55 +0,0 @@ -# frv testcase for msaths $FRi,$FRj,$FRj -# mach: all - - .include "testutils.inc" - - start - - .global msaths -msaths: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - msaths fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - - set_fr_iimmed 0x0001,0x7fff,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - msaths fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - - set_fr_iimmed 0xffff,0x8000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - msaths fr10,fr11,fr12 - test_fr_limmed 0xffff,0xffff,fr12 - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0040,0x0040,fr11 - msaths fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - - set_fr_iimmed 0x0001,0x7fff,fr10 - set_fr_iimmed 0x0040,0x0040,fr11 - msaths fr10,fr11,fr12 - test_fr_limmed 0x0001,0x0040,fr12 - - set_fr_iimmed 0xffff,0x8000,fr10 - set_fr_iimmed 0x0040,0x0040,fr11 - msaths fr10,fr11,fr12 - test_fr_limmed 0xffff,0xffbf,fr12 - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - msaths fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - - set_fr_iimmed 0x0001,0x7fff,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - msaths fr10,fr11,fr12 - test_fr_limmed 0x0001,0x7fff,fr12 - - set_fr_iimmed 0xffff,0x8000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - msaths fr10,fr11,fr12 - test_fr_limmed 0xffff,0x8000,fr12 - - pass diff --git a/sim/testsuite/sim/frv/msathu.cgs b/sim/testsuite/sim/frv/msathu.cgs deleted file mode 100644 index 4f376b2c34d..00000000000 --- a/sim/testsuite/sim/frv/msathu.cgs +++ /dev/null @@ -1,55 +0,0 @@ -# frv testcase for msathu $FRi,$FRj,$FRj -# mach: all - - .include "testutils.inc" - - start - - .global msathu -msathu: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - msathu fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - - set_fr_iimmed 0x0001,0x7fff,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - msathu fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - - set_fr_iimmed 0xffff,0x8000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - msathu fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0040,0x0040,fr11 - msathu fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - - set_fr_iimmed 0x0001,0x7fff,fr10 - set_fr_iimmed 0x0040,0x0040,fr11 - msathu fr10,fr11,fr12 - test_fr_limmed 0x0001,0x0040,fr12 - - set_fr_iimmed 0xffff,0x8000,fr10 - set_fr_iimmed 0x0040,0x0040,fr11 - msathu fr10,fr11,fr12 - test_fr_limmed 0x0040,0x0040,fr12 - - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - msathu fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - - set_fr_iimmed 0x0001,0x7fff,fr10 - set_fr_iimmed 0x7fff,0x7fff,fr11 - msathu fr10,fr11,fr12 - test_fr_limmed 0x0001,0x7fff,fr12 - - set_fr_iimmed 0xffff,0xffff,fr10 - set_fr_iimmed 0x7fff,0xffff,fr11 - msathu fr10,fr11,fr12 - test_fr_limmed 0x7fff,0xffff,fr12 - - pass diff --git a/sim/testsuite/sim/frv/msllhi.cgs b/sim/testsuite/sim/frv/msllhi.cgs deleted file mode 100644 index 4340b9f9c06..00000000000 --- a/sim/testsuite/sim/frv/msllhi.cgs +++ /dev/null @@ -1,30 +0,0 @@ -# frv testcase for msllhi $FRi,$s6,$FRk -# mach: all - - .include "testutils.inc" - - start - - .global msllhi -msllhi: - set_fr_iimmed 2,2,fr8 - msllhi fr8,0x20,fr8 ; Shift by 0 - test_fr_limmed 2,2,fr8 - - set_fr_iimmed 2,2,fr8 - msllhi fr8,0,fr8 ; Shift by 0 - test_fr_limmed 2,2,fr8 - - set_fr_iimmed 2,2,fr8 - msllhi fr8,1,fr8 ; Shift by 1 - test_fr_limmed 4,4,fr8 - - set_fr_iimmed 1,1,fr8 - msllhi fr8,31,fr8 ; Shift by 15 - test_fr_limmed 0x8000,0x8000,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr8 - msllhi fr8,15,fr8 - test_fr_iimmed 0x80008000,fr8 - - pass diff --git a/sim/testsuite/sim/frv/msrahi.cgs b/sim/testsuite/sim/frv/msrahi.cgs deleted file mode 100644 index 182f84e2147..00000000000 --- a/sim/testsuite/sim/frv/msrahi.cgs +++ /dev/null @@ -1,30 +0,0 @@ -# frv testcase for msrahi $FRi,$s6,$FRk -# mach: all - - .include "testutils.inc" - - start - - .global msrahi -msrahi: - set_fr_iimmed 2,2,fr8 - msrahi fr8,0x20,fr8 ; Shift by 0 - test_fr_limmed 2,2,fr8 - - set_fr_iimmed 2,2,fr8 - msrahi fr8,0,fr8 ; Shift by 0 - test_fr_limmed 2,2,fr8 - - set_fr_iimmed 3,2,fr8 - msrahi fr8,1,fr8 ; Shift by 1 - test_fr_limmed 1,1,fr8 - - set_fr_iimmed 0x8000,0x7fff,fr8 - msrahi fr8,31,fr8 ; Shift by 15 - test_fr_limmed 0xffff,0x0000,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr8 - msrahi fr8,15,fr8 - test_fr_iimmed 0xffffffff,fr8 - - pass diff --git a/sim/testsuite/sim/frv/msrlhi.cgs b/sim/testsuite/sim/frv/msrlhi.cgs deleted file mode 100644 index c9971a98a68..00000000000 --- a/sim/testsuite/sim/frv/msrlhi.cgs +++ /dev/null @@ -1,30 +0,0 @@ -# frv testcase for msrlhi $FRi,$s6,$FRk -# mach: all - - .include "testutils.inc" - - start - - .global msrlhi -msrlhi: - set_fr_iimmed 2,2,fr8 - msrlhi fr8,0x20,fr8 ; Shift by 0 - test_fr_limmed 2,2,fr8 - - set_fr_iimmed 2,2,fr8 - msrlhi fr8,0,fr8 ; Shift by 0 - test_fr_limmed 2,2,fr8 - - set_fr_iimmed 3,2,fr8 - msrlhi fr8,1,fr8 ; Shift by 1 - test_fr_limmed 1,1,fr8 - - set_fr_iimmed 0xffff,0x8000,fr8 - msrlhi fr8,31,fr8 ; Shift by 15 - test_fr_limmed 0x0001,0x0001,fr8 - - set_fr_iimmed 0xdead,0xbeef,fr8 - msrlhi fr8,15,fr8 - test_fr_iimmed 0x00010001,fr8 - - pass diff --git a/sim/testsuite/sim/frv/msubhss.cgs b/sim/testsuite/sim/frv/msubhss.cgs deleted file mode 100644 index 1ba334367e4..00000000000 --- a/sim/testsuite/sim/frv/msubhss.cgs +++ /dev/null @@ -1,100 +0,0 @@ -# frv testcase for msubhss $FRi,$FRj,$FRj -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global msubhss -msubhss: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - msubhss fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0x0000,fr10 - set_fr_iimmed 0x0000,0xbeef,fr11 - msubhss fr10,fr11,fr12 - test_fr_limmed 0xdead,0x4111,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0000,0xdead,fr10 - set_fr_iimmed 0xbeef,0x0000,fr11 - msubhss fr10,fr11,fr12 - test_fr_limmed 0x4111,0xdead,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - msubhss fr10,fr11,fr12 - test_fr_limmed 0x0123,0x4567,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xffff,0xffff,fr11 - msubhss fr10,fr11,fr12 - test_fr_limmed 0x1235,0x5679,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0xfffe,0xffff,fr11 - msubhss fr10,fr11,fr12 - test_fr_limmed 0x7fff,0x7fff,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - msubhss fr10,fr11,fr12 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x8001,0x8001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - msubhss fr10,fr11,fr12 - test_fr_limmed 0x8000,0x8000,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x8000,0x8000,fr11 - msubhss.p fr10,fr10,fr12 - msubhss fr11,fr10,fr13 - test_fr_limmed 0x0000,0x0000,fr12 - test_fr_limmed 0x8000,0x8000,fr13 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/msubhus.cgs b/sim/testsuite/sim/frv/msubhus.cgs deleted file mode 100644 index 1a002da42d5..00000000000 --- a/sim/testsuite/sim/frv/msubhus.cgs +++ /dev/null @@ -1,80 +0,0 @@ -# frv testcase for msubhus $FRi,$FRj,$FRj -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global msubhus -msubhus: - set_fr_iimmed 0x0000,0x0000,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - msubhus fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0xdead,0xbeef,fr10 - set_fr_iimmed 0x0000,0x0000,fr11 - msubhus fr10,fr11,fr12 - test_fr_limmed 0xdead,0xbeef,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x1111,0x1111,fr11 - msubhus fr10,fr11,fr12 - test_fr_limmed 0x0123,0x4567,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x7ffe,0x7ffe,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - msubhus fr10,fr11,fr12 - test_fr_limmed 0x7ffc,0x7ffd,fr12 - test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 1,0,0,msr0 ; msr0.aovf not set - test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set - - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0001,0x0002,fr11 - msubhus fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0001,fr11 - msubhus fr10,fr11,fr12 - test_fr_limmed 0x0000,0x0000,fr12 - test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - set_spr_immed 0,msr0 - set_spr_immed 0,msr1 - set_fr_iimmed 0x0001,0x0001,fr10 - set_fr_iimmed 0x0002,0x0002,fr11 - msubhus.p fr10,fr10,fr12 - msubhus fr10,fr11,fr13 - test_fr_limmed 0x0000,0x0000,fr12 - test_fr_limmed 0x0000,0x0000,fr13 - test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear - test_spr_bits 2,1,0,msr0 ; msr0.ovf not set - test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set - test_spr_bits 2,1,1,msr1 ; msr1.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - - pass diff --git a/sim/testsuite/sim/frv/mtrap.cgs b/sim/testsuite/sim/frv/mtrap.cgs deleted file mode 100644 index 65b947a24de..00000000000 --- a/sim/testsuite/sim/frv/mtrap.cgs +++ /dev/null @@ -1,50 +0,0 @@ -# frv testcase for mp_exception -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global mp_exception -mpx: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 0x0e0,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 - set_spr_immed 128,lcr - set_spr_addr ok1,lr - set_psr_et 1 - set_gr_immed 0,gr5 - - set_spr_immed 0,msr0 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x7ffe,0x7ffe,fr11 - set_fr_iimmed 0xffff,0xffff,fr12 - set_fr_iimmed 0x0002,0x0001,fr13 - mqaddhss fr10,fr12,fr14 - test_fr_limmed 0x1233,0x5677,fr14 - test_fr_limmed 0x7fff,0x7fff,fr15 - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - mtrap ; generate interrupt - test_gr_immed 1,gr5 - - and_spr_immed 0xffffc000,msr0 ; Clear msr0 fields - mcmpsh fr10,fr11,fcc0 ; no exception - test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear - mtrap ; nop - test_gr_immed 1,gr5 - - pass - -; exception handler -ok1: - test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set - test_spr_bits 2,1,1,msr0 ; msr0.ovf set - test_spr_bits 1,0,1,msr0 ; msr0.aovf set - test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set - inc_gr_immed 1,gr5 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/munpackh.cgs b/sim/testsuite/sim/frv/munpackh.cgs deleted file mode 100644 index 45b2bd82421..00000000000 --- a/sim/testsuite/sim/frv/munpackh.cgs +++ /dev/null @@ -1,22 +0,0 @@ -# frv testcase for munpackh $FRi,$FRj -# mach: all - - .include "testutils.inc" - - start - - .global munpackh -munpackh: - set_fr_iimmed 0xdead,0xbeef,fr10 - set_fr_iimmed 0x1234,0x5678,fr11 - munpackh fr10,fr12 - test_fr_limmed 0xdead,0xdead,fr12 - test_fr_limmed 0xbeef,0xbeef,fr13 - - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0xdead,0xbeef,fr11 - munpackh fr10,fr12 - test_fr_limmed 0x1234,0x1234,fr12 - test_fr_limmed 0x5678,0x5678,fr13 - - pass diff --git a/sim/testsuite/sim/frv/mwcut.cgs b/sim/testsuite/sim/frv/mwcut.cgs deleted file mode 100644 index 0e31b8fa93a..00000000000 --- a/sim/testsuite/sim/frv/mwcut.cgs +++ /dev/null @@ -1,269 +0,0 @@ -# frv testcase for mwcut $FRi,FRj,$FRk -# mach: all - - .include "testutils.inc" - - start - - .global mwcut -mwcut: - set_fr_iimmed 0x0123,0x4567,fr8 - set_fr_iimmed 0x89ab,0xcdef,fr9 - - set_fr_iimmed 0,0,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x01234567,fr11 - - set_fr_iimmed 0,1,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x02468acf,fr11 - - set_fr_iimmed 0,2,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x048d159e,fr11 - - set_fr_iimmed 0,3,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x091a2b3c,fr11 - - set_fr_iimmed 0,4,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x12345678,fr11 - - set_fr_iimmed 0,5,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x2468acf1,fr11 - - set_fr_iimmed 0,6,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x48d159e2,fr11 - - set_fr_iimmed 0,7,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x91a2b3c4,fr11 - - set_fr_iimmed 0,8,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x23456789,fr11 - - set_fr_iimmed 0,9,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x468acf13,fr11 - - set_fr_iimmed 0,10,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x8d159e26,fr11 - - set_fr_iimmed 0,11,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x1a2b3c4d,fr11 - - set_fr_iimmed 0,12,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x3456789a,fr11 - - set_fr_iimmed 0,13,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x68acf135,fr11 - - set_fr_iimmed 0,14,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xd159e26a,fr11 - - set_fr_iimmed 0,15,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xa2b3c4d5,fr11 - - set_fr_iimmed 0,16,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x456789ab,fr11 - - set_fr_iimmed 0,17,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x8acf1357,fr11 - - set_fr_iimmed 0,18,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x159e26af,fr11 - - set_fr_iimmed 0,19,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x2b3c4d5e,fr11 - - set_fr_iimmed 0,20,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x56789abc,fr11 - - set_fr_iimmed 0,21,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xacf13579,fr11 - - set_fr_iimmed 0,22,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x59e26af3,fr11 - - set_fr_iimmed 0,23,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xb3c4d5e6,fr11 - - set_fr_iimmed 0,24,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x6789abcd,fr11 - - set_fr_iimmed 0,25,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xcf13579b,fr11 - - set_fr_iimmed 0,26,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x9e26af37,fr11 - - set_fr_iimmed 0,27,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x3c4d5e6f,fr11 - - set_fr_iimmed 0,28,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x789abcde,fr11 - - set_fr_iimmed 0,29,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xf13579bd,fr11 - - set_fr_iimmed 0,30,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xe26af37b,fr11 - - set_fr_iimmed 0,31,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xc4d5e6f7,fr11 - - set_fr_iimmed 0,32,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x89abcdef,fr11 - - set_fr_iimmed 0,33,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x13579bde,fr11 - - set_fr_iimmed 0,34,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x26af37bc,fr11 - - set_fr_iimmed 0,35,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x4d5e6f78,fr11 - - set_fr_iimmed 0,36,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x9abcdef0,fr11 - - set_fr_iimmed 0,37,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x3579bde0,fr11 - - set_fr_iimmed 0,38,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x6af37bc0,fr11 - - set_fr_iimmed 0,39,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xd5e6f780,fr11 - - set_fr_iimmed 0,40,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xabcdef00,fr11 - - set_fr_iimmed 0,41,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x579bde00,fr11 - - set_fr_iimmed 0,42,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xaf37bc00,fr11 - - set_fr_iimmed 0,43,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x5e6f7800,fr11 - - set_fr_iimmed 0,44,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xbcdef000,fr11 - - set_fr_iimmed 0,45,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x79bde000,fr11 - - set_fr_iimmed 0,46,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xf37bc000,fr11 - - set_fr_iimmed 0,47,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xe6f78000,fr11 - - set_fr_iimmed 0,48,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xcdef0000,fr11 - - set_fr_iimmed 0,49,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x9bde0000,fr11 - - set_fr_iimmed 0,50,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x37bc0000,fr11 - - set_fr_iimmed 0,51,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x6f780000,fr11 - - set_fr_iimmed 0,52,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xdef00000,fr11 - - set_fr_iimmed 0,53,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xbde00000,fr11 - - set_fr_iimmed 0,54,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x7bc00000,fr11 - - set_fr_iimmed 0,55,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xf7800000,fr11 - - set_fr_iimmed 0,56,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xef000000,fr11 - - set_fr_iimmed 0,57,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xde000000,fr11 - - set_fr_iimmed 0,58,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xbc000000,fr11 - - set_fr_iimmed 0,59,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x78000000,fr11 - - set_fr_iimmed 0,60,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xf0000000,fr11 - - set_fr_iimmed 0,61,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xe0000000,fr11 - - set_fr_iimmed 0,62,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0xc0000000,fr11 - - set_fr_iimmed 0,63,fr10 - mwcut fr8,fr10,fr11 - test_fr_iimmed 0x80000000,fr11 - - pass diff --git a/sim/testsuite/sim/frv/mwcuti.cgs b/sim/testsuite/sim/frv/mwcuti.cgs deleted file mode 100644 index 338eab86389..00000000000 --- a/sim/testsuite/sim/frv/mwcuti.cgs +++ /dev/null @@ -1,205 +0,0 @@ -# frv testcase for mwcuti $FRi,s6,$FRk -# mach: all - - .include "testutils.inc" - - start - - .global mwcuti -mwcuti: - set_fr_iimmed 0x0123,0x4567,fr8 - set_fr_iimmed 0x89ab,0xcdef,fr9 - - mwcuti fr8,0,fr11 - test_fr_iimmed 0x01234567,fr11 - - mwcuti fr8,1,fr11 - test_fr_iimmed 0x02468acf,fr11 - - mwcuti fr8,2,fr11 - test_fr_iimmed 0x048d159e,fr11 - - mwcuti fr8,3,fr11 - test_fr_iimmed 0x091a2b3c,fr11 - - mwcuti fr8,4,fr11 - test_fr_iimmed 0x12345678,fr11 - - mwcuti fr8,5,fr11 - test_fr_iimmed 0x2468acf1,fr11 - - mwcuti fr8,6,fr11 - test_fr_iimmed 0x48d159e2,fr11 - - mwcuti fr8,7,fr11 - test_fr_iimmed 0x91a2b3c4,fr11 - - mwcuti fr8,8,fr11 - test_fr_iimmed 0x23456789,fr11 - - mwcuti fr8,9,fr11 - test_fr_iimmed 0x468acf13,fr11 - - mwcuti fr8,10,fr11 - test_fr_iimmed 0x8d159e26,fr11 - - mwcuti fr8,11,fr11 - test_fr_iimmed 0x1a2b3c4d,fr11 - - mwcuti fr8,12,fr11 - test_fr_iimmed 0x3456789a,fr11 - - mwcuti fr8,13,fr11 - test_fr_iimmed 0x68acf135,fr11 - - mwcuti fr8,14,fr11 - test_fr_iimmed 0xd159e26a,fr11 - - mwcuti fr8,15,fr11 - test_fr_iimmed 0xa2b3c4d5,fr11 - - mwcuti fr8,16,fr11 - test_fr_iimmed 0x456789ab,fr11 - - mwcuti fr8,17,fr11 - test_fr_iimmed 0x8acf1357,fr11 - - mwcuti fr8,18,fr11 - test_fr_iimmed 0x159e26af,fr11 - - mwcuti fr8,19,fr11 - test_fr_iimmed 0x2b3c4d5e,fr11 - - mwcuti fr8,20,fr11 - test_fr_iimmed 0x56789abc,fr11 - - mwcuti fr8,21,fr11 - test_fr_iimmed 0xacf13579,fr11 - - mwcuti fr8,22,fr11 - test_fr_iimmed 0x59e26af3,fr11 - - mwcuti fr8,23,fr11 - test_fr_iimmed 0xb3c4d5e6,fr11 - - mwcuti fr8,24,fr11 - test_fr_iimmed 0x6789abcd,fr11 - - mwcuti fr8,25,fr11 - test_fr_iimmed 0xcf13579b,fr11 - - mwcuti fr8,26,fr11 - test_fr_iimmed 0x9e26af37,fr11 - - mwcuti fr8,27,fr11 - test_fr_iimmed 0x3c4d5e6f,fr11 - - mwcuti fr8,28,fr11 - test_fr_iimmed 0x789abcde,fr11 - - mwcuti fr8,29,fr11 - test_fr_iimmed 0xf13579bd,fr11 - - mwcuti fr8,30,fr11 - test_fr_iimmed 0xe26af37b,fr11 - - mwcuti fr8,31,fr11 - test_fr_iimmed 0xc4d5e6f7,fr11 - - mwcuti fr8,32,fr11 - test_fr_iimmed 0x89abcdef,fr11 - - mwcuti fr8,33,fr11 - test_fr_iimmed 0x13579bde,fr11 - - mwcuti fr8,34,fr11 - test_fr_iimmed 0x26af37bc,fr11 - - mwcuti fr8,35,fr11 - test_fr_iimmed 0x4d5e6f78,fr11 - - mwcuti fr8,36,fr11 - test_fr_iimmed 0x9abcdef0,fr11 - - mwcuti fr8,37,fr11 - test_fr_iimmed 0x3579bde0,fr11 - - mwcuti fr8,38,fr11 - test_fr_iimmed 0x6af37bc0,fr11 - - mwcuti fr8,39,fr11 - test_fr_iimmed 0xd5e6f780,fr11 - - mwcuti fr8,40,fr11 - test_fr_iimmed 0xabcdef00,fr11 - - mwcuti fr8,41,fr11 - test_fr_iimmed 0x579bde00,fr11 - - mwcuti fr8,42,fr11 - test_fr_iimmed 0xaf37bc00,fr11 - - mwcuti fr8,43,fr11 - test_fr_iimmed 0x5e6f7800,fr11 - - mwcuti fr8,44,fr11 - test_fr_iimmed 0xbcdef000,fr11 - - mwcuti fr8,45,fr11 - test_fr_iimmed 0x79bde000,fr11 - - mwcuti fr8,46,fr11 - test_fr_iimmed 0xf37bc000,fr11 - - mwcuti fr8,47,fr11 - test_fr_iimmed 0xe6f78000,fr11 - - mwcuti fr8,48,fr11 - test_fr_iimmed 0xcdef0000,fr11 - - mwcuti fr8,49,fr11 - test_fr_iimmed 0x9bde0000,fr11 - - mwcuti fr8,50,fr11 - test_fr_iimmed 0x37bc0000,fr11 - - mwcuti fr8,51,fr11 - test_fr_iimmed 0x6f780000,fr11 - - mwcuti fr8,52,fr11 - test_fr_iimmed 0xdef00000,fr11 - - mwcuti fr8,53,fr11 - test_fr_iimmed 0xbde00000,fr11 - - mwcuti fr8,54,fr11 - test_fr_iimmed 0x7bc00000,fr11 - - mwcuti fr8,55,fr11 - test_fr_iimmed 0xf7800000,fr11 - - mwcuti fr8,56,fr11 - test_fr_iimmed 0xef000000,fr11 - - mwcuti fr8,57,fr11 - test_fr_iimmed 0xde000000,fr11 - - mwcuti fr8,58,fr11 - test_fr_iimmed 0xbc000000,fr11 - - mwcuti fr8,59,fr11 - test_fr_iimmed 0x78000000,fr11 - - mwcuti fr8,60,fr11 - test_fr_iimmed 0xf0000000,fr11 - - mwcuti fr8,61,fr11 - test_fr_iimmed 0xe0000000,fr11 - - mwcuti fr8,62,fr11 - test_fr_iimmed 0xc0000000,fr11 - - mwcuti fr8,63,fr11 - test_fr_iimmed 0x80000000,fr11 - - pass diff --git a/sim/testsuite/sim/frv/mwtacc.cgs b/sim/testsuite/sim/frv/mwtacc.cgs deleted file mode 100644 index 20b4d31885b..00000000000 --- a/sim/testsuite/sim/frv/mwtacc.cgs +++ /dev/null @@ -1,23 +0,0 @@ -# frv testcase for mwtacc $FRinti,$ACC40k -# mach: all - - .include "testutils.inc" - - start - - .global mwtacc -mwtacc: - test_accg_immed 0x00,accg0 - test_acc_immed 0x00000000,acc0 - - set_fr_iimmed 0xdead,0xbeef,fr10 - mwtacc fr10,acc0 - test_accg_immed 0x00,accg0 - test_acc_immed 0xdeadbeef,acc0 - - set_fr_iimmed 0x1234,0x5678,fr10 - mwtacc fr10,acc0 - test_accg_immed 0x00,accg0 - test_acc_immed 0x12345678,acc0 - - pass diff --git a/sim/testsuite/sim/frv/mwtaccg.cgs b/sim/testsuite/sim/frv/mwtaccg.cgs deleted file mode 100644 index 6e26bab287b..00000000000 --- a/sim/testsuite/sim/frv/mwtaccg.cgs +++ /dev/null @@ -1,23 +0,0 @@ -# frv testcase for mwtaccg $FRinti,$ACC40k -# mach: all - - .include "testutils.inc" - - start - - .global mwtaccg -mwtaccg: - test_accg_immed 0x00,accg0 - test_acc_immed 0x00000000,acc0 - - set_fr_iimmed 0xdead,0xbeef,fr10 - mwtaccg fr10,accg0 - test_accg_immed 0xef,accg0 - test_acc_immed 0,acc0 - - set_fr_iimmed 0x1234,0x5678,fr10 - mwtaccg fr10,accg0 - test_accg_immed 0x78,accg0 - test_acc_immed 0,acc0 - - pass diff --git a/sim/testsuite/sim/frv/mxor.cgs b/sim/testsuite/sim/frv/mxor.cgs deleted file mode 100644 index 6d1cce11bf5..00000000000 --- a/sim/testsuite/sim/frv/mxor.cgs +++ /dev/null @@ -1,30 +0,0 @@ -# frv testcase for mxor $FRinti,$FRintj,$FRintk -# mach: all - - .include "testutils.inc" - - start - - .global mxor -mxor: - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0x5555,0x5555,fr8 - mxor fr7,fr8,fr8 - test_fr_iimmed 0xffffffff,fr8 - - set_fr_iimmed 0x0000,0x0000,fr7 - set_fr_iimmed 0x0000,0x0000,fr8 - mxor fr7,fr8,fr8 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xaaaa,0xaaaa,fr7 - set_fr_iimmed 0xaaaa,0xaaaa,fr8 - mxor fr7,fr8,fr8 - test_fr_iimmed 0x00000000,fr8 - - set_fr_iimmed 0xdead,0x0000,fr7 - set_fr_iimmed 0x0000,0xbeef,fr8 - mxor fr7,fr8,fr8 - test_fr_iimmed 0xdeadbeef,fr8 - - pass diff --git a/sim/testsuite/sim/frv/nandcr.cgs b/sim/testsuite/sim/frv/nandcr.cgs deleted file mode 100644 index 8d3298fd787..00000000000 --- a/sim/testsuite/sim/frv/nandcr.cgs +++ /dev/null @@ -1,59 +0,0 @@ -# frv testcase for nandcr $CCi,$CCj,$CCk -# mach: all - - .include "testutils.inc" - - start - - .global nandcr -nandcr: - set_spr_immed 0x1b1b,cccr - nandcr cc7,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - nandcr cc7,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - nandcr cc7,cc5,cc3 - test_spr_immed 0x1b1b,cccr - - nandcr cc7,cc4,cc3 - test_spr_immed 0x1b1b,cccr - - nandcr cc6,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - nandcr cc6,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - nandcr cc6,cc5,cc3 - test_spr_immed 0x1b1b,cccr - - nandcr cc6,cc4,cc3 - test_spr_immed 0x1b1b,cccr - - nandcr cc5,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - nandcr cc5,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - nandcr cc5,cc5,cc3 - test_spr_immed 0x1b1b,cccr - - nandcr cc5,cc4,cc3 - test_spr_immed 0x1b1b,cccr - - nandcr cc4,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - nandcr cc4,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - nandcr cc4,cc5,cc3 - test_spr_immed 0x1bdb,cccr - - nandcr cc4,cc4,cc3 - test_spr_immed 0x1b9b,cccr - - pass diff --git a/sim/testsuite/sim/frv/nandncr.cgs b/sim/testsuite/sim/frv/nandncr.cgs deleted file mode 100644 index c761c56102c..00000000000 --- a/sim/testsuite/sim/frv/nandncr.cgs +++ /dev/null @@ -1,59 +0,0 @@ -# frv testcase for nandncr $CCi,$CCj,$CCk -# mach: all - - .include "testutils.inc" - - start - - .global nandncr -nandncr: - set_spr_immed 0x1b1b,cccr - nandncr cc7,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - nandncr cc7,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - nandncr cc7,cc5,cc3 - test_spr_immed 0x1b1b,cccr - - nandncr cc7,cc4,cc3 - test_spr_immed 0x1b1b,cccr - - nandncr cc6,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - nandncr cc6,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - nandncr cc6,cc5,cc3 - test_spr_immed 0x1b1b,cccr - - nandncr cc6,cc4,cc3 - test_spr_immed 0x1b1b,cccr - - nandncr cc5,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - nandncr cc5,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - nandncr cc5,cc5,cc3 - test_spr_immed 0x1bdb,cccr - - nandncr cc5,cc4,cc3 - test_spr_immed 0x1b9b,cccr - - nandncr cc4,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - nandncr cc4,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - nandncr cc4,cc5,cc3 - test_spr_immed 0x1b1b,cccr - - nandncr cc4,cc4,cc3 - test_spr_immed 0x1b1b,cccr - - pass diff --git a/sim/testsuite/sim/frv/nfadds.cgs b/sim/testsuite/sim/frv/nfadds.cgs deleted file mode 100644 index bdfa1dc124f..00000000000 --- a/sim/testsuite/sim/frv/nfadds.cgs +++ /dev/null @@ -1,179 +0,0 @@ -# frv testcase for nfadds $GRi,$GRj,$GRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global nfadds -nfadds: - nfadds fr16,fr0,fr1 - test_fr_fr fr1,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr16,fr4,fr1 - test_fr_fr fr1,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr16,fr8,fr1 - test_fr_fr fr1,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr16,fr12,fr1 - test_fr_fr fr1,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr16,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr16,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr16,fr24,fr1 - test_fr_fr fr1,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr16,fr28,fr1 - test_fr_fr fr1,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr16,fr32,fr1 - test_fr_fr fr1,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr16,fr36,fr1 - test_fr_fr fr1,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr16,fr40,fr1 - test_fr_fr fr1,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr16,fr44,fr1 - test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr16,fr48,fr1 - test_fr_fr fr1,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr16,fr52,fr1 - test_fr_fr fr1,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfadds fr20,fr0,fr1 - test_fr_fr fr1,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr20,fr4,fr1 - test_fr_fr fr1,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr20,fr8,fr1 - test_fr_fr fr1,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr20,fr12,fr1 - test_fr_fr fr1,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr20,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr20,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr20,fr24,fr1 - test_fr_fr fr1,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr20,fr28,fr1 - test_fr_fr fr1,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr20,fr32,fr1 - test_fr_fr fr1,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr20,fr36,fr1 - test_fr_fr fr1,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr20,fr40,fr1 - test_fr_fr fr1,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr20,fr44,fr1 - test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr20,fr48,fr1 - test_fr_fr fr1,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr20,fr52,fr1 - test_fr_fr fr1,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfadds fr8,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr12,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr24,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfadds fr28,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfadds fr36,fr40,fr1 - test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; try to cause exceptions - nfadds fr48,fr28,fr1 -; test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfadds fr52,fr28,fr1 -; test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfadds fr56,fr28,fr1 -; test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfadds fr60,fr28,fr1 -; test_fr_fr fr1,fr44 - test_spr_immed 2,fner1 - test_spr_immed 0,fner0 - - pass - - diff --git a/sim/testsuite/sim/frv/nfdadds.cgs b/sim/testsuite/sim/frv/nfdadds.cgs deleted file mode 100644 index 0be25e7a3b5..00000000000 --- a/sim/testsuite/sim/frv/nfdadds.cgs +++ /dev/null @@ -1,225 +0,0 @@ -# frv testcase for nfdadds $FRi,$FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global nfdadds -nfdadds: - nfdadds fr16,fr0,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr16,fr4,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr16,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr16,fr12,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr16,fr24,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr16,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr16,fr32,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr16,fr36,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr16,fr40,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr16,fr44,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr16,fr48,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr16,fr52,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdadds fr20,fr0,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr20,fr4,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr20,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr20,fr12,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr20,fr24,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr20,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr20,fr32,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr20,fr36,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr20,fr40,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr20,fr44,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr20,fr48,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr20,fr52,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdadds fr8,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr12,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr24,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdadds fr28,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdadds fr36,fr40,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; try to cause exceptions - nfdadds fr48,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdadds fr52,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdadds fr56,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdadds fr60,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0xc,fner1 - test_spr_immed 0,fner0 - - pass - - diff --git a/sim/testsuite/sim/frv/nfdcmps.cgs b/sim/testsuite/sim/frv/nfdcmps.cgs deleted file mode 100644 index 977805ab2d7..00000000000 --- a/sim/testsuite/sim/frv/nfdcmps.cgs +++ /dev/null @@ -1,1549 +0,0 @@ -# frv testcase for nfdcmps $FRi,$FRj,$FCCi_2 -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global nfdcmps -nfdcmps: - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - nfdcmps fr0,fr0,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr0,fr4,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr0,fr8,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr0,fr12,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr0,fr16,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr0,fr20,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr0,fr24,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr0,fr28,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr0,fr32,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr0,fr36,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr0,fr40,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr0,fr44,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr0,fr48,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr0,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr0,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr0,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr4,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - nfdcmps fr4,fr4,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr4,fr8,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr4,fr12,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr4,fr16,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr4,fr20,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr4,fr24,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr4,fr28,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr4,fr32,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr4,fr36,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr4,fr40,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr4,fr44,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr4,fr48,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr4,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr4,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr4,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr8,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr8,fr4,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - nfdcmps fr8,fr8,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr8,fr12,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr8,fr16,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr8,fr20,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr8,fr24,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr8,fr28,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr8,fr32,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr8,fr36,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr8,fr40,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr8,fr44,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr8,fr48,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr8,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr8,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr8,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr12,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr12,fr4,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr12,fr8,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - nfdcmps fr12,fr12,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr12,fr16,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr12,fr20,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr12,fr24,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr12,fr28,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr12,fr32,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr12,fr36,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr12,fr40,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr12,fr44,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr12,fr48,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr12,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr12,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr12,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr16,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr16,fr4,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr16,fr8,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr16,fr12,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - nfdcmps fr16,fr16,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - nfdcmps fr16,fr20,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr16,fr24,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr16,fr28,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr16,fr32,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr16,fr36,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr16,fr40,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr16,fr44,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr16,fr48,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr16,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr16,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr16,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr20,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr20,fr4,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr20,fr8,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr20,fr12,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - nfdcmps fr20,fr16,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - nfdcmps fr20,fr20,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr20,fr24,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr20,fr28,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr20,fr32,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr20,fr36,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr20,fr40,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr20,fr44,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr20,fr48,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr20,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr20,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr20,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr24,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr24,fr4,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr24,fr8,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr24,fr12,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr24,fr16,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr24,fr20,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - nfdcmps fr24,fr24,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr24,fr28,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr24,fr32,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr24,fr36,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr24,fr40,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr24,fr44,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr24,fr48,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr24,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr24,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr24,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr28,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr28,fr4,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr28,fr8,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr28,fr12,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr28,fr16,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr28,fr20,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr28,fr24,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - nfdcmps fr28,fr28,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr28,fr32,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr28,fr36,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr28,fr40,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr28,fr44,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr28,fr48,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr28,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr28,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr28,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr48,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr48,fr4,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr48,fr8,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr48,fr12,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr48,fr16,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr48,fr20,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr48,fr24,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr48,fr28,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr48,fr32,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr48,fr36,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr48,fr40,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr48,fr44,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - nfdcmps fr48,fr48,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xb,0 ; Set mask opposite of expected - set_fcc 0xb,1 ; Set mask opposite of expected - nfdcmps fr48,fr52,fcc0 - test_fcc 0x4,0 - test_fcc 0x4,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr48,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr48,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr52,fr0,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr52,fr4,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr52,fr8,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr52,fr12,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr52,fr16,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr52,fr20,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr52,fr24,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr52,fr28,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr52,fr32,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr52,fr36,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr52,fr40,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr52,fr44,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xd,0 ; Set mask opposite of expected - set_fcc 0xd,1 ; Set mask opposite of expected - nfdcmps fr52,fr48,fcc0 - test_fcc 0x2,0 - test_fcc 0x2,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0x7,0 ; Set mask opposite of expected - set_fcc 0x7,1 ; Set mask opposite of expected - nfdcmps fr52,fr52,fcc0 - test_fcc 0x8,0 - test_fcc 0x8,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr52,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr52,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr56,fr0,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr56,fr4,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr56,fr8,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr56,fr12,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr56,fr16,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr56,fr20,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr56,fr24,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr56,fr28,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr56,fr32,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr56,fr36,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr56,fr40,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr56,fr44,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr56,fr48,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr56,fr52,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr56,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr56,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr60,fr0,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr60,fr4,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr60,fr8,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr60,fr12,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr60,fr16,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr60,fr20,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr60,fr24,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr60,fr28,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr60,fr32,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr60,fr36,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr60,fr40,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr60,fr44,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr60,fr48,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr60,fr52,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr60,fr56,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fcc 0xe,0 ; Set mask opposite of expected - set_fcc 0xe,1 ; Set mask opposite of expected - nfdcmps fr60,fr60,fcc0 - test_fcc 0x1,0 - test_fcc 0x1,1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nfddivs.cgs b/sim/testsuite/sim/frv/nfddivs.cgs deleted file mode 100644 index 0b16447057e..00000000000 --- a/sim/testsuite/sim/frv/nfddivs.cgs +++ /dev/null @@ -1,306 +0,0 @@ -# frv testcase for nfddivs $FRi,$FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global nfddivs -nfddivs: - nfddivs fr0,fr28,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr4,fr28,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr8,fr28,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr12,fr28,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr16,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr20,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr24,fr28,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr28,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr32,fr28,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr36,fr28,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr40,fr28,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr44,fr28,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr48,fr28,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr52,fr28,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfddivs fr16,fr0,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr16,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr16,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr16,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr16,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr16,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr16,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr16,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr16,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr16,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr16,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr16,fr52,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfddivs fr20,fr0,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr20,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr20,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr20,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr20,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr20,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr20,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr20,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr20,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr20,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr20,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr20,fr52,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfddivs fr8,fr28,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfddivs fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfddivs fr40,fr32,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; try to cause exceptions - set_spr_immed 0,fner0 - set_spr_immed 0,fner1 - nfddivs fr48,fr20,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0xc,fner1 - test_spr_immed 0,fner0 - - set_spr_immed 0,fner0 - set_spr_immed 0,fner1 - nfddivs fr52,fr16,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0x0,fner1 - test_spr_immed 0,fner0 - - nfddivs fr56,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfddivs fr60,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0xc,fner1 - test_spr_immed 0,fner0 - - pass - - diff --git a/sim/testsuite/sim/frv/nfditos.cgs b/sim/testsuite/sim/frv/nfditos.cgs deleted file mode 100644 index 1200944332d..00000000000 --- a/sim/testsuite/sim/frv/nfditos.cgs +++ /dev/null @@ -1,31 +0,0 @@ -# frv testcase for nfditos $FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global nfditos -nfditos: - set_fr_iimmed 0,0,fr2 - set_fr_iimmed 0x0000,0x0002,fr3 - nfditos fr2,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fr_iimmed 0xdead,0xbeef,fr2 - set_fr_iimmed 0xdead,0xbeef,fr3 - nfditos fr2,fr2 - test_fr_iimmed 0xce054904,fr2 - test_fr_iimmed 0xce054904,fr3 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; TODO test cases to set ne flags - - pass diff --git a/sim/testsuite/sim/frv/nfdivs.cgs b/sim/testsuite/sim/frv/nfdivs.cgs deleted file mode 100644 index 73e58b82b50..00000000000 --- a/sim/testsuite/sim/frv/nfdivs.cgs +++ /dev/null @@ -1,234 +0,0 @@ -# frv testcase for nfdivs $FRi,$FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global nfdivs -nfdivs: - nfdivs fr0,fr28,fr1 - test_fr_fr fr1,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr4,fr28,fr1 - test_fr_fr fr1,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr8,fr28,fr1 - test_fr_fr fr1,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr12,fr28,fr1 - test_fr_fr fr1,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr16,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr20,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr24,fr28,fr1 - test_fr_fr fr1,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr28,fr28,fr1 - test_fr_fr fr1,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr32,fr28,fr1 - test_fr_fr fr1,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr36,fr28,fr1 - test_fr_fr fr1,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr40,fr28,fr1 - test_fr_fr fr1,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr44,fr28,fr1 - test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr48,fr28,fr1 - test_fr_fr fr1,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr52,fr28,fr1 - test_fr_fr fr1,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdivs fr16,fr0,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr16,fr4,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr16,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr16,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr16,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr16,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr16,fr32,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr16,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr16,fr40,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr16,fr44,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr16,fr48,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr16,fr52,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdivs fr20,fr0,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr20,fr4,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr20,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr20,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr20,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr20,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr20,fr32,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr20,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr20,fr40,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr20,fr44,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr20,fr48,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr20,fr52,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdivs fr8,fr28,fr1 - test_fr_fr fr1,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdivs fr28,fr8,fr1 - test_fr_fr fr1,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdivs fr40,fr32,fr1 - test_fr_fr fr1,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; try to cause exceptions - set_spr_immed 0,fner0 - set_spr_immed 0,fner1 - nfdivs fr48,fr20,fr1 -; test_fr_fr fr1,fr44 - test_spr_immed 2,fner1 - test_spr_immed 0,fner0 - - set_spr_immed 0,fner0 - set_spr_immed 0,fner1 - nfdivs fr52,fr16,fr1 -; test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdivs fr56,fr28,fr1 -; test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdivs fr60,fr28,fr1 -; test_fr_fr fr1,fr44 - test_spr_immed 2,fner1 - test_spr_immed 0,fner0 - - pass - - diff --git a/sim/testsuite/sim/frv/nfdmadds.cgs b/sim/testsuite/sim/frv/nfdmadds.cgs deleted file mode 100644 index 1af110cee6d..00000000000 --- a/sim/testsuite/sim/frv/nfdmadds.cgs +++ /dev/null @@ -1,310 +0,0 @@ -# frv testcase for nfdmadds $GRi,$GRj,$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global nfdmadds -nfdmadds: - nfdmadds fr16,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr16,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr16,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr16,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr16,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr16,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr16,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr16,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr16,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr16,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmadds fr20,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr20,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr20,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr20,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr20,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr20,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr20,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr20,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr20,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr20,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - nfdmadds fr28,fr0,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - nfdmadds fr28,fr4,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - nfdmadds fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - nfdmadds fr28,fr12,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - nfdmadds fr28,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - nfdmadds fr28,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - nfdmadds fr28,fr24,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - nfdmadds fr28,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - nfdmadds fr28,fr32,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - nfdmadds fr28,fr36,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - nfdmadds fr28,fr40,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - nfdmadds fr28,fr44,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - nfdmadds fr28,fr48,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr2 - set_fr_fr fr16,fr3 - nfdmadds fr28,fr52,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fr_fr fr36,fr2 - set_fr_fr fr36,fr3 - nfdmadds fr28,fr8,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmadds fr8,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fr_fr fr36,fr2 - set_fr_fr fr36,fr3 - nfdmadds fr32,fr36,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; TODO -- test cases to set ne flags - - pass diff --git a/sim/testsuite/sim/frv/nfdmas.cgs b/sim/testsuite/sim/frv/nfdmas.cgs deleted file mode 100644 index 07f76aafb55..00000000000 --- a/sim/testsuite/sim/frv/nfdmas.cgs +++ /dev/null @@ -1,349 +0,0 @@ -# frv testcase for nfdmas $FRi,$FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - load_float_constants2 - load_float_constants3 - - .global nfdmas -nfdmas: - nfdmas fr16,fr4,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr4 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr16,fr8,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr8 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr16,fr12,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr12 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr16,fr16,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr16,fr20,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr16,fr24,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr24 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr16,fr28,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr28 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr16,fr32,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr32 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr16,fr36,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr36 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr16,fr40,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr40 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr16,fr44,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr44 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr16,fr48,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr48 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmas fr20,fr4,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr4 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr20,fr8,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr8 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr20,fr12,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr12 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr20,fr16,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr20,fr20,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr20,fr24,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr24 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr20,fr28,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr28 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr20,fr32,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr32 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr20,fr36,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr36 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr20,fr40,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr40 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr20,fr44,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr44 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr20,fr48,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr48 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmas fr28,fr0,fr60 - test_fr_fr fr60,fr0 - test_fr_fr fr62,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr28,fr4,fr60 - test_fr_fr fr60,fr4 - test_fr_fr fr62,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr28,fr8,fr60 - test_fr_fr fr60,fr8 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr8 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr28,fr12,fr60 - test_fr_fr fr60,fr12 - test_fr_fr fr62,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr28,fr16,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr28,fr20,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr28,fr24,fr60 - test_fr_fr fr60,fr24 - test_fr_fr fr62,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr28,fr28,fr60 - test_fr_fr fr60,fr28 - test_fr_fr fr62,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr28,fr32,fr60 - test_fr_fr fr60,fr32 - test_fr_fr fr61,fr36 - test_fr_fr fr62,fr32 - test_fr_fr fr63,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr28,fr36,fr60 - test_fr_fr fr60,fr36 - test_fr_fr fr62,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr28,fr40,fr60 - test_fr_fr fr60,fr40 - test_fr_fr fr62,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr28,fr44,fr60 - test_fr_fr fr60,fr44 - test_fr_fr fr62,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr28,fr48,fr60 - test_fr_fr fr60,fr48 - test_fr_fr fr62,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr28,fr52,fr60 - test_fr_fr fr60,fr52 - test_fr_fr fr62,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmas fr28,fr8,fr60 - test_fr_fr fr60,fr8 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr8 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmas fr8,fr28,fr60 - test_fr_fr fr60,fr8 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr8 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmas fr32,fr36,fr60 - test_fr_fr fr60,fr40 - test_fr_fr fr62,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; TODO -- test cases to set ne flags - - pass diff --git a/sim/testsuite/sim/frv/nfdmss.cgs b/sim/testsuite/sim/frv/nfdmss.cgs deleted file mode 100644 index 3633d706544..00000000000 --- a/sim/testsuite/sim/frv/nfdmss.cgs +++ /dev/null @@ -1,319 +0,0 @@ -# frv testcase for nfdmss $FRi,$FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - load_float_constants2 - load_float_constants3 - - .global nfdmss -nfdmss: - nfdmss fr16,fr4,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr16,fr8,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr28 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr16,fr12,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr16,fr16,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr16,fr20,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr16,fr24,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr16,fr28,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr8 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr16,fr32,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr16,fr36,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr16,fr40,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr16,fr44,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr16,fr48,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmss fr20,fr4,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr20,fr8,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr28 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr20,fr12,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr20,fr16,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr20,fr20,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr61,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr16 - test_fr_fr fr63,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr20,fr24,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr20,fr28,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr8 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr20,fr32,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr20,fr36,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr20,fr40,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr20,fr44,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr20,fr48,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmss fr28,fr0,fr60 - test_fr_fr fr60,fr0 - test_fr_fr fr62,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr28,fr4,fr60 - test_fr_fr fr60,fr4 - test_fr_fr fr62,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr28,fr8,fr60 - test_fr_fr fr60,fr8 - test_fr_fr fr61,fr32 - test_fr_fr fr62,fr8 - test_fr_fr fr63,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr28,fr12,fr60 - test_fr_fr fr60,fr12 - test_fr_fr fr62,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr28,fr16,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr28 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr28,fr20,fr60 - test_fr_fr fr60,fr16 - test_fr_fr fr60,fr20 - test_fr_fr fr61,fr28 - test_fr_fr fr62,fr16 - test_fr_fr fr62,fr20 - test_fr_fr fr63,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr28,fr24,fr60 - test_fr_fr fr60,fr24 - test_fr_fr fr62,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr28,fr28,fr60 - test_fr_fr fr60,fr28 - test_fr_fr fr61,fr20 - test_fr_fr fr61,fr16 - test_fr_fr fr62,fr28 - test_fr_fr fr63,fr20 - test_fr_fr fr63,fr16 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr28,fr32,fr60 - test_fr_fr fr60,fr32 - test_fr_fr fr61,fr8 - test_fr_fr fr62,fr32 - test_fr_fr fr63,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr28,fr36,fr60 - test_fr_fr fr60,fr36 - test_fr_fr fr62,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr28,fr40,fr60 - test_fr_fr fr60,fr40 - test_fr_fr fr62,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr28,fr44,fr60 - test_fr_fr fr60,fr44 - test_fr_fr fr62,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr28,fr48,fr60 - test_fr_fr fr60,fr48 - test_fr_fr fr62,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr28,fr52,fr60 - test_fr_fr fr60,fr52 - test_fr_fr fr62,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmss fr28,fr8,fr60 - test_fr_fr fr60,fr8 - test_fr_fr fr61,fr32 - test_fr_fr fr62,fr8 - test_fr_fr fr63,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmss fr8,fr28,fr60 - test_fr_fr fr60,fr8 - test_fr_fr fr62,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmss fr32,fr36,fr60 - test_fr_fr fr60,fr40 - test_fr_fr fr61,fr8 - test_fr_fr fr62,fr40 - test_fr_fr fr63,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; TODO -- test cases to set ne flags - - pass diff --git a/sim/testsuite/sim/frv/nfdmulcs.cgs b/sim/testsuite/sim/frv/nfdmulcs.cgs deleted file mode 100644 index 227ff291311..00000000000 --- a/sim/testsuite/sim/frv/nfdmulcs.cgs +++ /dev/null @@ -1,313 +0,0 @@ -# frv testcase for nfdmulcs $FRi,$FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global nfdmulcs -nfdmulcs: - nfdmulcs fr16,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr16,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr16,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr16,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr16,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr16,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr16,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr16,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr16,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr16,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmulcs fr20,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr20,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr20,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr3,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr20,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr20,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr20,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr20,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr20,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr20,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr20,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmulcs fr28,fr0,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr28,fr4,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr28,fr12,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr28,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr28,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr28,fr24,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr28,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr28,fr32,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr28,fr36,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr28,fr40,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr28,fr44,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr28,fr48,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr28,fr52,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmulcs fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmulcs fr8,fr28,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmulcs fr32,fr36,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; try to cause exceptions - nfdmulcs fr48,fr32,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmulcs fr52,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmulcs fr56,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmulcs fr60,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0xc,fner1 - test_spr_immed 0,fner0 - - ; test all regs different - set_spr_immed 0,fner0 - set_spr_immed 0,fner1 - set_fr_fr fr32,fr50 ; 2 - set_fr_fr fr28,fr51 ; 1 - set_fr_fr fr44,fr52 ; 9 - set_fr_fr fr36,fr53 ; 3 - nfdmulcs fr50,fr52,fr54 ; 2*3, 1*9 - test_fr_fr fr54,fr40 ; 6 - test_fr_fr fr55,fr44 ; 9 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nfdmuls.cgs b/sim/testsuite/sim/frv/nfdmuls.cgs deleted file mode 100644 index efe158035d7..00000000000 --- a/sim/testsuite/sim/frv/nfdmuls.cgs +++ /dev/null @@ -1,300 +0,0 @@ -# frv testcase for nfdmuls $FRi,$FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global nfdmuls -nfdmuls: - nfdmuls fr16,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr16,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr16,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr16,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr16,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr16,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr16,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr16,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr16,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr16,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmuls fr20,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr20,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr20,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr3,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr20,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr20,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr20,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr20,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr20,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr20,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr20,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmuls fr28,fr0,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr28,fr4,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr28,fr12,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr28,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr28,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr28,fr24,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr28,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr28,fr32,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr28,fr36,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr28,fr40,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr28,fr44,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr28,fr48,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr28,fr52,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmuls fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdmuls fr8,fr28,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmuls fr32,fr36,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; try to cause exceptions - nfdmuls fr48,fr32,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmuls fr52,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmuls fr56,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdmuls fr60,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0xc,fner1 - test_spr_immed 0,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nfdsads.cgs b/sim/testsuite/sim/frv/nfdsads.cgs deleted file mode 100644 index 6c06f16c0c2..00000000000 --- a/sim/testsuite/sim/frv/nfdsads.cgs +++ /dev/null @@ -1,212 +0,0 @@ -# frv testcase for nfdsads $FRi,$FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global nfdsads -nfdsads: - nfdsads fr16,fr0,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr16,fr4,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr16,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr16,fr12,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr16,fr24,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr16,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr16,fr32,fr2 - test_fr_fr fr2,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr16,fr36,fr2 - test_fr_fr fr2,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr16,fr40,fr2 - test_fr_fr fr2,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr16,fr44,fr2 - test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr16,fr48,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr16,fr52,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdsads fr20,fr0,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr20,fr4,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr20,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr20,fr12,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr20,fr24,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr20,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr20,fr32,fr2 - test_fr_fr fr2,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr20,fr36,fr2 - test_fr_fr fr2,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr20,fr40,fr2 - test_fr_fr fr2,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr20,fr44,fr2 - test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr20,fr48,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr20,fr52,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdsads fr8,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr12,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr24,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsads fr28,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr32 - test_fr_fr fr3,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdsads fr36,fr40,fr2 - test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; try to cause exceptions - set_fr_fr fr4,fr49 - nfdsads fr48,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fr_fr fr0,fr53 - nfdsads fr52,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdsads fr56,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdsads fr60,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0xc,fner1 - test_spr_immed 0,fner0 - - pass - - diff --git a/sim/testsuite/sim/frv/nfdsqrts.cgs b/sim/testsuite/sim/frv/nfdsqrts.cgs deleted file mode 100644 index 1a906bb7279..00000000000 --- a/sim/testsuite/sim/frv/nfdsqrts.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# frv testcase for nfdsqrts $FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global nfdsqrts -nfdsqrts: - set_fr_iimmed 0x4049,0x0fdb,fr45 ; 3.141592654 - nfdsqrts fr44,fr2 ; 9.0 - test_fr_fr fr2,fr36 ; 3.0 - test_fr_iimmed 0x3fe2dfc5,fr3 ; 1.7724539 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; TODO test cases to set ne flags - - pass diff --git a/sim/testsuite/sim/frv/nfdstoi.cgs b/sim/testsuite/sim/frv/nfdstoi.cgs deleted file mode 100644 index 56dc941bb70..00000000000 --- a/sim/testsuite/sim/frv/nfdstoi.cgs +++ /dev/null @@ -1,29 +0,0 @@ -# frv testcase for nfdstoi $FRj,$FRk -# mach: frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global nfdstoi -nfdstoi: - set_fr_fr fr20,fr17 - nfdstoi fr16,fr2 - test_fr_iimmed 0,fr2 - test_fr_iimmed 0,fr3 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fr_iimmed 0xce05,0x4904,fr2 - set_fr_fr fr32,fr3 - nfdstoi fr2,fr2 - test_fr_iimmed 0xdeadbf00,fr2 - test_fr_iimmed 0x00000002,fr3 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; TODO test cases to set ne flags - - pass diff --git a/sim/testsuite/sim/frv/nfdsubs.cgs b/sim/testsuite/sim/frv/nfdsubs.cgs deleted file mode 100644 index c981aab3624..00000000000 --- a/sim/testsuite/sim/frv/nfdsubs.cgs +++ /dev/null @@ -1,202 +0,0 @@ -# frv testcase for nfdsubs $FRi,$FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global nfdsubs -nfdsubs: - nfdsubs fr0,fr16,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr4,fr16,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr8,fr16,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr12,fr16,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr24,fr16,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr28,fr16,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr32,fr16,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr36,fr16,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr40,fr16,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr44,fr16,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr48,fr16,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr52,fr16,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdsubs fr0,fr20,fr2 - test_fr_fr fr2,fr0 - test_fr_fr fr3,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr4,fr20,fr2 - test_fr_fr fr2,fr4 - test_fr_fr fr3,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr8,fr20,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr12,fr20,fr2 - test_fr_fr fr2,fr12 - test_fr_fr fr3,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr24,fr20,fr2 - test_fr_fr fr2,fr24 - test_fr_fr fr3,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr28,fr20,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr32,fr20,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr36,fr20,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr40,fr20,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr44,fr20,fr2 - test_fr_fr fr2,fr44 - test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr48,fr20,fr2 - test_fr_fr fr2,fr48 - test_fr_fr fr3,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfdsubs fr52,fr20,fr2 - test_fr_fr fr2,fr52 - test_fr_fr fr3,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdsubs fr32,fr36,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdsubs fr44,fr40,fr2 - test_fr_fr fr2,fr36 - test_fr_fr fr3,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; try to cause exceptions - nfdsubs fr4,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdsubs fr0,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdsubs fr56,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfdsubs fr60,fr28,fr2 -; test_fr_fr fr2,fr44 -; test_fr_fr fr3,fr44 - test_spr_immed 0xc,fner1 - test_spr_immed 0,fner0 - - pass - - diff --git a/sim/testsuite/sim/frv/nfitos.cgs b/sim/testsuite/sim/frv/nfitos.cgs deleted file mode 100644 index 539f7b281c5..00000000000 --- a/sim/testsuite/sim/frv/nfitos.cgs +++ /dev/null @@ -1,44 +0,0 @@ -# frv testcase for nfitos $FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global nfitos -nfitos: - set_fr_iimmed 0,0,fr1 - nfitos fr1,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fr_iimmed 0x0000,0x0002,fr1 - nfitos fr1,fr1 - test_fr_fr fr1,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fr_iimmed 0xdead,0xbeef,fr1 - nfitos fr1,fr1 - test_fr_iimmed 0xce054904,fr1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; These were an attempt to cause overflow - set_fr_iimmed 0x7fff,0xffff,fr1 - nfitos fr1,fr1 - test_fr_iimmed 0x4f000000,fr1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fr_iimmed 0x8000,0x0000,fr1 - nfitos fr1,fr1 - test_fr_iimmed 0xcf000000,fr1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nfmadds.cgs b/sim/testsuite/sim/frv/nfmadds.cgs deleted file mode 100644 index 2113cd27716..00000000000 --- a/sim/testsuite/sim/frv/nfmadds.cgs +++ /dev/null @@ -1,227 +0,0 @@ -# frv testcase for nfmadds $GRi,$GRj,$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global nfmadds -nfmadds: - set_fr_fr fr16,fr1 - nfmadds fr16,fr4,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr16,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr16,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr16,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr16,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr16,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr16,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr16,fr32,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr16,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr16,fr40,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr16,fr44,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr16,fr48,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmadds fr20,fr4,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr20,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr20,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr20,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr20,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr20,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr20,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr20,fr32,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr20,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr20,fr40,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr20,fr44,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr20,fr48,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fr_fr fr16,fr1 - nfmadds fr28,fr0,fr1 - test_fr_fr fr1,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmadds fr28,fr4,fr1 - test_fr_fr fr1,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmadds fr28,fr8,fr1 - test_fr_fr fr1,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmadds fr28,fr12,fr1 - test_fr_fr fr1,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmadds fr28,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmadds fr28,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmadds fr28,fr24,fr1 - test_fr_fr fr1,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmadds fr28,fr28,fr1 - test_fr_fr fr1,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmadds fr28,fr32,fr1 - test_fr_fr fr1,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmadds fr28,fr36,fr1 - test_fr_fr fr1,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmadds fr28,fr40,fr1 - test_fr_fr fr1,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmadds fr28,fr44,fr1 - test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmadds fr28,fr48,fr1 - test_fr_fr fr1,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmadds fr28,fr52,fr1 - test_fr_fr fr1,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fr_fr fr36,fr1 - nfmadds fr28,fr8,fr1 - test_fr_fr fr1,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmadds fr8,fr28,fr1 - test_fr_fr fr1,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fr_fr fr36,fr1 - nfmadds fr32,fr36,fr1 - test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; TODO test cases to set ne flags - - pass diff --git a/sim/testsuite/sim/frv/nfmas.cgs b/sim/testsuite/sim/frv/nfmas.cgs deleted file mode 100644 index b688dbdf4d2..00000000000 --- a/sim/testsuite/sim/frv/nfmas.cgs +++ /dev/null @@ -1,297 +0,0 @@ -# frv testcase for nfmas $FRi,$FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global nfmas -nfmas: - nfmas fr16,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr16,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr16,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr16,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr16,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr16,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr16,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr16,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr16,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr16,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmas fr20,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr20,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr20,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr20,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr20,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr20,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr20,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr20,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr20,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr20,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmas fr28,fr0,fr2 - test_fr_fr fr2,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr28,fr4,fr2 - test_fr_fr fr2,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr28,fr12,fr2 - test_fr_fr fr2,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr28,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr28,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr28,fr24,fr2 - test_fr_fr fr2,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr28,fr28,fr2 - test_fr_fr fr2,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr28,fr32,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr28,fr36,fr2 - test_fr_fr fr2,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr28,fr40,fr2 - test_fr_fr fr2,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr28,fr44,fr2 - test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr28,fr48,fr2 - test_fr_fr fr2,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr28,fr52,fr2 - test_fr_fr fr2,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmas fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmas fr8,fr28,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmas fr32,fr36,fr2 - test_fr_fr fr2,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; try to cause exceptions - set_spr_immed 0,fner0 - set_spr_immed 0,fner1 - nfmas fr48,fr28,fr1 -; test_fr_fr fr1,fr44 -; test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmas fr52,fr28,fr1 -; test_fr_fr fr1,fr44 -; test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmas fr56,fr28,fr1 -; test_fr_fr fr1,fr44 -; test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmas fr60,fr28,fr1 -; test_fr_fr fr1,fr44 -; test_fr_fr fr2,fr44 - test_spr_immed 6,fner1 - test_spr_immed 0,fner0 - - set_spr_immed 0,fner0 - set_spr_immed 0,fner1 - nfmas fr48,fr32,fr1 -; test_fr_fr fr1,fr44 -; test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmas fr52,fr28,fr1 -; test_fr_fr fr1,fr44 -; test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmas fr56,fr28,fr1 -; test_fr_fr fr1,fr44 -; test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmas fr60,fr28,fr1 -; test_fr_fr fr1,fr44 -; test_fr_fr fr2,fr44 - test_spr_immed 6,fner1 - test_spr_immed 0,fner0 - - pass - diff --git a/sim/testsuite/sim/frv/nfmss.cgs b/sim/testsuite/sim/frv/nfmss.cgs deleted file mode 100644 index bc7c8ef6cbb..00000000000 --- a/sim/testsuite/sim/frv/nfmss.cgs +++ /dev/null @@ -1,279 +0,0 @@ -# frv testcase for nfmss $FRi,$FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - load_float_constants1 - - .global nfmss -nfmss: - nfmss fr16,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr16,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr16,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr16,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr16,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr16,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr16,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr16,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr16,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr16,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr16,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr16,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmss fr20,fr4,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr20,fr8,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr20,fr12,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr20,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr20,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr16 - test_fr_fr fr3,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr20,fr24,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr20,fr28,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr20,fr32,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr20,fr36,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr20,fr40,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr20,fr44,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr20,fr48,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmss fr28,fr0,fr2 - test_fr_fr fr2,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr28,fr4,fr2 - test_fr_fr fr2,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr28,fr12,fr2 - test_fr_fr fr2,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr28,fr16,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr28,fr20,fr2 - test_fr_fr fr2,fr16 - test_fr_fr fr2,fr20 - test_fr_fr fr3,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr28,fr24,fr2 - test_fr_fr fr2,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr28,fr28,fr2 - test_fr_fr fr2,fr28 - test_fr_fr fr3,fr20 - test_fr_fr fr3,fr16 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr28,fr32,fr2 - test_fr_fr fr2,fr32 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr28,fr36,fr2 - test_fr_fr fr2,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr28,fr40,fr2 - test_fr_fr fr2,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr28,fr44,fr2 - test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr28,fr48,fr2 - test_fr_fr fr2,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr28,fr52,fr2 - test_fr_fr fr2,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmss fr28,fr8,fr2 - test_fr_fr fr2,fr8 - test_fr_fr fr3,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmss fr8,fr28,fr2 - test_fr_fr fr2,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmss fr32,fr36,fr2 - test_fr_fr fr2,fr40 - test_fr_fr fr3,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; try to cause exceptions - nfmss fr4,fr28,fr1 -; test_fr_fr fr1,fr44 -; test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmss fr0,fr28,fr1 -; test_fr_fr fr1,fr44 -; test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmss fr56,fr28,fr1 -; test_fr_fr fr1,fr44 -; test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmss fr60,fr28,fr1 -; test_fr_fr fr1,fr44 -; test_fr_fr fr2,fr44 - test_spr_immed 0x6,fner1 - test_spr_immed 0,fner0 - - set_spr_immed 0,fner0 - set_spr_immed 0,fner1 - nfmss fr48,fr32,fr1 -; test_fr_fr fr1,fr44 -; test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmss fr52,fr28,fr1 -; test_fr_fr fr1,fr44 -; test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmss fr56,fr28,fr1 -; test_fr_fr fr1,fr44 -; test_fr_fr fr2,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmss fr60,fr28,fr1 -; test_fr_fr fr1,fr44 -; test_fr_fr fr2,fr44 - test_spr_immed 0x6,fner1 - test_spr_immed 0,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nfmsubs.cgs b/sim/testsuite/sim/frv/nfmsubs.cgs deleted file mode 100644 index 1ae87e36d1f..00000000000 --- a/sim/testsuite/sim/frv/nfmsubs.cgs +++ /dev/null @@ -1,227 +0,0 @@ -# frv testcase for nfmsubs $GRi,$GRj,$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global nfmsubs -nfmsubs: - set_fr_fr fr16,fr1 - nfmsubs fr16,fr4,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr16,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr16,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr16,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr16,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr16,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr16,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr16,fr32,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr16,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr16,fr40,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr16,fr44,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr16,fr48,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmsubs fr20,fr4,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr20,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr20,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr20,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr20,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr20,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr20,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr20,fr32,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr20,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr20,fr40,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr20,fr44,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmsubs fr20,fr48,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fr_fr fr16,fr1 - nfmsubs fr28,fr0,fr1 - test_fr_fr fr1,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmsubs fr28,fr4,fr1 - test_fr_fr fr1,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmsubs fr28,fr8,fr1 - test_fr_fr fr1,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmsubs fr28,fr12,fr1 - test_fr_fr fr1,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmsubs fr28,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmsubs fr28,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmsubs fr28,fr24,fr1 - test_fr_fr fr1,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmsubs fr28,fr28,fr1 - test_fr_fr fr1,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmsubs fr28,fr32,fr1 - test_fr_fr fr1,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmsubs fr28,fr36,fr1 - test_fr_fr fr1,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmsubs fr28,fr40,fr1 - test_fr_fr fr1,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmsubs fr28,fr44,fr1 - test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmsubs fr28,fr48,fr1 - test_fr_fr fr1,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr16,fr1 - nfmsubs fr28,fr52,fr1 - test_fr_fr fr1,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fr_fr fr32,fr1 - nfmsubs fr8,fr8,fr1 - test_fr_fr fr1,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - set_fr_fr fr36,fr1 - nfmsubs fr36,fr36,fr1 - test_fr_fr fr1,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmsubs fr32,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; TODO test cases to set ne flags - pass diff --git a/sim/testsuite/sim/frv/nfmuls.cgs b/sim/testsuite/sim/frv/nfmuls.cgs deleted file mode 100644 index e4b0d2eebbc..00000000000 --- a/sim/testsuite/sim/frv/nfmuls.cgs +++ /dev/null @@ -1,228 +0,0 @@ -# frv testcase for nfmuls $FRi,$FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global nfmuls -nfmuls: - nfmuls fr16,fr4,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr16,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr16,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr16,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr16,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr16,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr16,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr16,fr32,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr16,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr16,fr40,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr16,fr44,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr16,fr48,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmuls fr20,fr4,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr20,fr8,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr20,fr12,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr20,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr20,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr20,fr24,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr20,fr28,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr20,fr32,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr20,fr36,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr20,fr40,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr20,fr44,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr20,fr48,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmuls fr28,fr0,fr1 - test_fr_fr fr1,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr28,fr4,fr1 - test_fr_fr fr1,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr28,fr8,fr1 - test_fr_fr fr1,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr28,fr12,fr1 - test_fr_fr fr1,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr28,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr28,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr28,fr24,fr1 - test_fr_fr fr1,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr28,fr28,fr1 - test_fr_fr fr1,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr28,fr32,fr1 - test_fr_fr fr1,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr28,fr36,fr1 - test_fr_fr fr1,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr28,fr40,fr1 - test_fr_fr fr1,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr28,fr44,fr1 - test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr28,fr48,fr1 - test_fr_fr fr1,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr28,fr52,fr1 - test_fr_fr fr1,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmuls fr28,fr8,fr1 - test_fr_fr fr1,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfmuls fr8,fr28,fr1 - test_fr_fr fr1,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmuls fr32,fr36,fr1 - test_fr_fr fr1,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; try to cause exceptions - nfmuls fr48,fr32,fr1 -; test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmuls fr52,fr28,fr1 -; test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmuls fr56,fr28,fr1 -; test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfmuls fr60,fr28,fr1 -; test_fr_fr fr1,fr44 - test_spr_immed 2,fner1 - test_spr_immed 0,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nfsqrts.cgs b/sim/testsuite/sim/frv/nfsqrts.cgs deleted file mode 100644 index 8ada77a85e0..00000000000 --- a/sim/testsuite/sim/frv/nfsqrts.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# frv testcase for nfsqrts $FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global nfsqrts -nfsqrts: - nfsqrts fr44,fr1 ; 9.0 - test_fr_fr fr1,fr36 ; 3.0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fr_iimmed 0x4049,0x0fdb,fr10 ; 3.141592654 - nfsqrts fr10,fr10 - test_fr_iimmed 0x3fe2dfc5,fr10 ; 1.7724539 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; fp_exceptions - nfsqrts fr8,fr1 ; -1 -- invalid - test_fr_iimmed 0x7fc00000,fr1 ; nan1 - test_spr_immed 2,fner1 - test_spr_immed 0,fner0 - test_spr_bits 0x80000000,31,0x0,fqst0 ; fq0.miv is clear - test_spr_bits 0x18000,15,0x0,fqst0 ; fq0.sie is clear - test_spr_bits 0x380,7,0x0,fqst0 ; fq0.ftt is clear - test_spr_bits 0x7e,1,0x0,fqst0 ; fq0.cexc is clear - test_spr_bits 0x1,0,0x0,fqst0 ; fq0.valid is clear - test_spr_immed 0,fqop0 ; fq0.opc - - pass diff --git a/sim/testsuite/sim/frv/nfstoi.cgs b/sim/testsuite/sim/frv/nfstoi.cgs deleted file mode 100644 index 296812827ae..00000000000 --- a/sim/testsuite/sim/frv/nfstoi.cgs +++ /dev/null @@ -1,49 +0,0 @@ -# frv testcase for nfstoi $FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global nfstoi -nfstoi: - nfstoi fr16,fr1 - test_fr_iimmed 0,fr1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfstoi fr20,fr1 - test_fr_iimmed 0,fr1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfstoi fr32,fr1 - test_fr_iimmed 0x00000002,fr1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - set_fr_iimmed 0xce05,0x4904,fr1 - nfstoi fr1,fr1 - test_fr_iimmed 0xdeadbf00,fr1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; These were an attempt to cause overflow and nan exceptions - nfstoi fr48,fr1 - test_fr_iimmed 0x7fffffff,fr1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfstoi fr52,fr1 - test_fr_iimmed 0x7fffffff,fr1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfstoi fr56,fr1 - test_fr_iimmed 0x80000000,fr1 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nfsubs.cgs b/sim/testsuite/sim/frv/nfsubs.cgs deleted file mode 100644 index 3da08b9ffb7..00000000000 --- a/sim/testsuite/sim/frv/nfsubs.cgs +++ /dev/null @@ -1,163 +0,0 @@ -# frv testcase for nfsubs $FRi,$FRj,$FRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - float_constants - start - load_float_constants - - .global nfsubs -nfsubs: - nfsubs fr0,fr16,fr1 - test_fr_fr fr1,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr4,fr16,fr1 - test_fr_fr fr1,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr8,fr16,fr1 - test_fr_fr fr1,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr12,fr16,fr1 - test_fr_fr fr1,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr16,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr20,fr16,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr24,fr16,fr1 - test_fr_fr fr1,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr28,fr16,fr1 - test_fr_fr fr1,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr32,fr16,fr1 - test_fr_fr fr1,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr36,fr16,fr1 - test_fr_fr fr1,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr40,fr16,fr1 - test_fr_fr fr1,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr44,fr16,fr1 - test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr48,fr16,fr1 - test_fr_fr fr1,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr52,fr16,fr1 - test_fr_fr fr1,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfsubs fr0,fr20,fr1 - test_fr_fr fr1,fr0 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr4,fr20,fr1 - test_fr_fr fr1,fr4 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr8,fr20,fr1 - test_fr_fr fr1,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr12,fr20,fr1 - test_fr_fr fr1,fr12 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr16,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr20,fr20,fr1 - test_fr_fr fr1,fr16 - test_fr_fr fr1,fr20 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr24,fr20,fr1 - test_fr_fr fr1,fr24 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr28,fr20,fr1 - test_fr_fr fr1,fr28 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr32,fr20,fr1 - test_fr_fr fr1,fr32 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr36,fr20,fr1 - test_fr_fr fr1,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr40,fr20,fr1 - test_fr_fr fr1,fr40 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr44,fr20,fr1 - test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr48,fr20,fr1 - test_fr_fr fr1,fr48 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - nfsubs fr52,fr20,fr1 - test_fr_fr fr1,fr52 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfsubs fr32,fr36,fr1 - test_fr_fr fr1,fr8 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfsubs fr44,fr40,fr1 - test_fr_fr fr1,fr36 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - ; try to cause exceptions - nfsubs fr4,fr28,fr1 -; test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfsubs fr0,fr28,fr1 -; test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfsubs fr56,fr28,fr1 -; test_fr_fr fr1,fr44 - test_spr_immed 0,fner1 - test_spr_immed 0,fner0 - - nfsubs fr60,fr28,fr1 -; test_fr_fr fr1,fr44 - test_spr_immed 2,fner1 - test_spr_immed 0,fner0 - - pass - - diff --git a/sim/testsuite/sim/frv/nld.cgs b/sim/testsuite/sim/frv/nld.cgs deleted file mode 100644 index 297468b44d6..00000000000 --- a/sim/testsuite/sim/frv/nld.cgs +++ /dev/null @@ -1,42 +0,0 @@ -# frv testcase for nld @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nld -nld: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr20 - set_gr_immed 0,gr7 - nld @(sp,gr7),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0x8880,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - nld @(sp,gr7),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0x8880,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - nld @(sp,gr7),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0x8880,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nldbf.cgs b/sim/testsuite/sim/frv/nldbf.cgs deleted file mode 100644 index 1a5c25b6741..00000000000 --- a/sim/testsuite/sim/frv/nldbf.cgs +++ /dev/null @@ -1,42 +0,0 @@ -# frv testcase for nldbf @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldbf -nldbf: - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_gr sp,gr20 - set_gr_immed 0,gr7 - nldbf @(sp,gr7),fr8 - test_fr_limmed 0x0000,0x00de,fr8 - test_spr_limmed 0xc800,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - inc_gr_immed 1,gr20 - set_gr_immed 1,gr7 - nldbf @(sp,gr7),fr8 - test_fr_limmed 0x0000,0x00ad,fr8 - test_spr_limmed 0xc800,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - inc_gr_immed 2,gr20 - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - nldbf @(sp,gr7),fr8 - test_fr_limmed 0x0000,0x0000,fr8 - test_spr_limmed 0xc800,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nldbfi.cgs b/sim/testsuite/sim/frv/nldbfi.cgs deleted file mode 100644 index aa90bc91194..00000000000 --- a/sim/testsuite/sim/frv/nldbfi.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# frv testcase for nldbfi @($GRi,$d12),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldbfi -nldbfi: - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_gr sp,gr20 - nldbfi @(sp,0),fr8 - test_fr_limmed 0x0000,0x00de,fr8 - test_spr_limmed 0xc800,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - inc_gr_immed 1,gr20 - nldbfi @(sp,1),fr8 - test_fr_limmed 0x0000,0x00ad,fr8 - test_spr_limmed 0xc800,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - inc_gr_immed 2,gr20 - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - nldbfi @(sp,-1),fr8 - test_fr_limmed 0x0000,0x0000,fr8 - test_spr_limmed 0xc800,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nldbfu.cgs b/sim/testsuite/sim/frv/nldbfu.cgs deleted file mode 100644 index 174042b4bc1..00000000000 --- a/sim/testsuite/sim/frv/nldbfu.cgs +++ /dev/null @@ -1,46 +0,0 @@ -# frv testcase for nldbfu @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldbfu -nldbfu: - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - nldbfu @(sp,gr7),fr8 - test_fr_limmed 0x0000,0x00de,fr8 - test_gr_gr sp,gr20 - test_spr_limmed 0xc800,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - inc_gr_immed 1,gr20 - set_gr_immed 1,gr7 - nldbfu @(sp,gr7),fr8 - test_fr_limmed 0x0000,0x00ad,fr8 - test_gr_gr sp,gr20 - test_spr_limmed 0xc800,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - inc_gr_immed 2,gr20 - inc_gr_immed -1,sp - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - nldbfu @(sp,gr7),fr8 - test_fr_limmed 0x0000,0x0000,fr8 - test_gr_gr sp,gr20 - test_spr_limmed 0xc800,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nldd.cgs b/sim/testsuite/sim/frv/nldd.cgs deleted file mode 100644 index 1f457611709..00000000000 --- a/sim/testsuite/sim/frv/nldd.cgs +++ /dev/null @@ -1,50 +0,0 @@ -# frv testcase for nldd @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldd -nldd: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_gr sp,gr20 - set_gr_immed 0,gr7 - nldd @(sp,gr7),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_spr_limmed 0x88a0,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - nldd @(sp,gr7),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_spr_limmed 0x88a0,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - nldd @(sp,gr7),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_spr_limmed 0x88a0,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nlddf.cgs b/sim/testsuite/sim/frv/nlddf.cgs deleted file mode 100644 index d30b6dd2385..00000000000 --- a/sim/testsuite/sim/frv/nlddf.cgs +++ /dev/null @@ -1,50 +0,0 @@ -# frv testcase for nlddf @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nlddf -nlddf: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_gr sp,gr20 - set_gr_immed 0,gr7 - nlddf @(sp,gr7),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_spr_limmed 0xc8a0,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - nlddf @(sp,gr7),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_spr_limmed 0xc8a0,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 16,sp - set_gr_immed -8,gr7 - nlddf @(sp,gr7),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_spr_limmed 0xc8a0,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nlddfi.cgs b/sim/testsuite/sim/frv/nlddfi.cgs deleted file mode 100644 index b58ad6ffe3c..00000000000 --- a/sim/testsuite/sim/frv/nlddfi.cgs +++ /dev/null @@ -1,47 +0,0 @@ -# frv testcase for nlddfi @($GRi,$d12),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nlddfi -nlddfi: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_gr sp,gr20 - nlddfi @(sp,0),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_spr_limmed 0xc8a0,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,sp - nlddfi @(sp,8),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_spr_limmed 0xc8a0,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 16,sp - nlddfi @(sp,-8),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_spr_limmed 0xc8a0,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nlddfu.cgs b/sim/testsuite/sim/frv/nlddfu.cgs deleted file mode 100644 index d45c995cd2c..00000000000 --- a/sim/testsuite/sim/frv/nlddfu.cgs +++ /dev/null @@ -1,53 +0,0 @@ -# frv testcase for nlddfu @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nlddfu -nlddfu: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - - set_gr_immed 0,gr7 - nlddfu @(sp,gr7),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_gr_gr sp,gr20 - test_spr_limmed 0xc8a0,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - nlddfu @(sp,gr7),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_gr_gr sp,gr20 - test_spr_limmed 0xc8a0,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - inc_gr_immed 8,sp - set_gr_immed -8,gr7 - nlddfu @(sp,gr7),fr8 - test_fr_limmed 0xbeef,0xdead,fr8 - test_fr_limmed 0xdead,0xbeef,fr9 - test_gr_gr sp,gr20 - test_spr_limmed 0xc8a0,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nlddi.cgs b/sim/testsuite/sim/frv/nlddi.cgs deleted file mode 100644 index 04d24875417..00000000000 --- a/sim/testsuite/sim/frv/nlddi.cgs +++ /dev/null @@ -1,47 +0,0 @@ -# frv testcase for nlddi @($GRi,$d12),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nlddi -nlddi: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_gr sp,gr20 - nlddi @(sp,0),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_spr_limmed 0x88a0,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,sp - nlddi @(sp,8),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_spr_limmed 0x88a0,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 16,sp - nlddi @(sp,-8),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_spr_limmed 0x88a0,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nlddu.cgs b/sim/testsuite/sim/frv/nlddu.cgs deleted file mode 100644 index 44565c8a6ff..00000000000 --- a/sim/testsuite/sim/frv/nlddu.cgs +++ /dev/null @@ -1,66 +0,0 @@ -# frv testcase for nlddu @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nlddu -nlddu: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr20 - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - - set_gr_immed 0,gr7 - nlddu @(sp,gr7),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_gr_gr sp,gr20 - test_spr_limmed 0x88a0,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed -8,sp - set_gr_immed 8,gr7 - nlddu @(sp,gr7),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_gr_gr sp,gr20 - test_spr_limmed 0x88a0,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 8,sp - set_gr_immed -8,gr7 - nlddu @(sp,gr7),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_gr_gr sp,gr20 - test_spr_limmed 0x88a0,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - inc_gr_immed 8,sp - set_gr_immed -8,gr7 - set_gr_gr sp,gr8 - nlddu @(gr8,gr7),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_gr_limmed 0xdead,0xbeef,gr9 - test_spr_limmed 0x88a0,0x0c01,nesr3 - test_spr_gr neear3,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nldf.cgs b/sim/testsuite/sim/frv/nldf.cgs deleted file mode 100644 index 6aabc67ea57..00000000000 --- a/sim/testsuite/sim/frv/nldf.cgs +++ /dev/null @@ -1,42 +0,0 @@ -# frv testcase for nldf @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldf -nldf: - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_gr sp,gr20 - set_gr_immed 0,gr7 - nldf @(sp,gr7),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - test_spr_limmed 0xc880,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - nldf @(sp,gr7),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - test_spr_limmed 0xc880,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 8,sp - set_gr_immed -4,gr7 - nldf @(sp,gr7),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - test_spr_limmed 0xc880,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nldfi.cgs b/sim/testsuite/sim/frv/nldfi.cgs deleted file mode 100644 index 20f62dfc15f..00000000000 --- a/sim/testsuite/sim/frv/nldfi.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# frv testcase for nldfi @($GRi,$d12),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldfi -nldfi: - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_gr sp,gr20 - nldfi @(sp,0),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - test_spr_limmed 0xc880,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,sp - nldfi @(sp,4),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - test_spr_limmed 0xc880,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 8,sp - nldfi @(sp,-4),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - test_spr_limmed 0xc880,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nldfu.cgs b/sim/testsuite/sim/frv/nldfu.cgs deleted file mode 100644 index 8e95016b608..00000000000 --- a/sim/testsuite/sim/frv/nldfu.cgs +++ /dev/null @@ -1,45 +0,0 @@ -# frv testcase for nldfu @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldfu -nldfu: - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - nldfu @(sp,gr7),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - test_gr_gr sp,gr20 - test_spr_limmed 0xc880,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - nldfu @(sp,gr7),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - test_gr_gr sp,gr20 - test_spr_limmed 0xc880,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xbeef,0xdead,fr8 - inc_gr_immed 4,sp - set_gr_immed -4,gr7 - nldfu @(sp,gr7),fr8 - test_fr_limmed 0xdead,0xbeef,fr8 - test_gr_gr sp,gr20 - test_spr_limmed 0xc880,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nldhf.cgs b/sim/testsuite/sim/frv/nldhf.cgs deleted file mode 100644 index b90d8f9f301..00000000000 --- a/sim/testsuite/sim/frv/nldhf.cgs +++ /dev/null @@ -1,41 +0,0 @@ -# frv testcase for nldhf @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldhf -nldhf: - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_gr sp,gr20 - set_gr_immed 0,gr7 - nldhf @(sp,gr7),fr8 - test_fr_limmed 0x0000,0xdead,fr8 - test_spr_limmed 0xc840,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - inc_gr_immed 2,gr20 - set_gr_immed 2,gr7 - nldhf @(sp,gr7),fr8 - test_fr_limmed 0x0000,0xbeef,fr8 - test_spr_limmed 0xc840,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - nldhf @(sp,gr7),fr8 - test_fr_limmed 0x0000,0x0000,fr8 - test_spr_limmed 0xc840,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nldhfi.cgs b/sim/testsuite/sim/frv/nldhfi.cgs deleted file mode 100644 index bcd52ed6e99..00000000000 --- a/sim/testsuite/sim/frv/nldhfi.cgs +++ /dev/null @@ -1,38 +0,0 @@ -# frv testcase for nldhfi @($GRi,$d12),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldhfi -nldhfi: - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_gr sp,gr20 - nldhfi @(sp,0),fr8 - test_fr_limmed 0x0000,0xdead,fr8 - test_spr_limmed 0xc840,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - inc_gr_immed 2,gr20 - nldhfi @(sp,2),fr8 - test_fr_limmed 0x0000,0xbeef,fr8 - test_spr_limmed 0xc840,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - nldhfi @(sp,-2),fr8 - test_fr_limmed 0x0000,0x0000,fr8 - test_spr_limmed 0xc840,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nldhfu.cgs b/sim/testsuite/sim/frv/nldhfu.cgs deleted file mode 100644 index 97d1dd9037f..00000000000 --- a/sim/testsuite/sim/frv/nldhfu.cgs +++ /dev/null @@ -1,45 +0,0 @@ -# frv testcase for nldhfu @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldhfu -nldhfu: - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xbeef,0xdead,fr8 - - set_gr_immed 0,gr7 - nldhfu @(sp,gr7),fr8 - test_fr_limmed 0x0000,0xdead,fr8 - test_gr_gr sp,gr20 - test_spr_limmed 0xc840,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - inc_gr_immed 2,gr20 - set_gr_immed 2,gr7 - nldhfu @(sp,gr7),fr8 - test_fr_limmed 0x0000,0xbeef,fr8 - test_gr_gr sp,gr20 - test_spr_limmed 0xc840,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - inc_gr_immed -2,sp - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - nldhfu @(sp,gr7),fr8 - test_fr_limmed 0x0000,0x0000,fr8 - test_gr_gr sp,gr20 - test_spr_limmed 0xc840,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nldi.cgs b/sim/testsuite/sim/frv/nldi.cgs deleted file mode 100644 index c70f0cb9eb4..00000000000 --- a/sim/testsuite/sim/frv/nldi.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# frv testcase for nldi @($GRi,$d12),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldi -nldi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr20 - nldi @(sp,0),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0x8880,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,sp - nldi @(sp,4),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0x8880,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 8,sp - nldi @(sp,-4),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_spr_limmed 0x8880,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nldq.cgs b/sim/testsuite/sim/frv/nldq.cgs deleted file mode 100644 index 0338e19fc0c..00000000000 --- a/sim/testsuite/sim/frv/nldq.cgs +++ /dev/null @@ -1,67 +0,0 @@ -# frv testcase for nldq @($GRi,$GRj),$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global nldq -nldq: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_gr sp,gr20 - set_gr_immed 0,gr7 - nldq @(sp,gr7),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - test_spr_limmed 0x88c0,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - nldq @(sp,gr7),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - test_spr_limmed 0x88c0,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - nldq @(sp,gr7),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - test_spr_limmed 0x88c0,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nldqf.cgs b/sim/testsuite/sim/frv/nldqf.cgs deleted file mode 100644 index 8e268acc85d..00000000000 --- a/sim/testsuite/sim/frv/nldqf.cgs +++ /dev/null @@ -1,67 +0,0 @@ -# frv testcase for nldqf @($GRi,$GRj),$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global nldqf -nldqf: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - - set_gr_gr sp,gr20 - set_gr_immed 0,gr7 - nldqf @(sp,gr7),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - test_spr_limmed 0xc8c0,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - nldqf @(sp,gr7),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - test_spr_limmed 0xc8c0,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - inc_gr_immed 32,sp - set_gr_immed -16,gr7 - nldqf @(sp,gr7),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - test_spr_limmed 0xc8c0,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nldqfi.cgs b/sim/testsuite/sim/frv/nldqfi.cgs deleted file mode 100644 index ff05fae7ad3..00000000000 --- a/sim/testsuite/sim/frv/nldqfi.cgs +++ /dev/null @@ -1,64 +0,0 @@ -# frv testcase for nldqfi @($GRi,$GRj),$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global nldqfi -nldqfi: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - - set_gr_gr sp,gr20 - nldqfi @(sp,0),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - test_spr_limmed 0xc8c0,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - inc_gr_immed -16,sp - nldqfi @(sp,16),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - test_spr_limmed 0xc8c0,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - inc_gr_immed 32,sp - nldqfi @(sp,-16),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - test_spr_limmed 0xc8c0,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nldqfu.cgs b/sim/testsuite/sim/frv/nldqfu.cgs deleted file mode 100644 index ffe2990cff0..00000000000 --- a/sim/testsuite/sim/frv/nldqfu.cgs +++ /dev/null @@ -1,70 +0,0 @@ -# frv testcase for nldqfu @($GRi,$GRj),$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global nldqfu -nldqfu: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_gr sp,gr20 - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - - set_gr_immed 0,gr7 - nldqfu @(sp,gr7),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - test_gr_gr sp,gr20 - test_spr_limmed 0xc8c0,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - nldqfu @(sp,gr7),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - test_gr_gr sp,gr20 - test_spr_limmed 0xc8c0,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - set_fr_iimmed 0xdead,0xbeef,fr8 - set_fr_iimmed 0xbeef,0xdead,fr9 - set_fr_iimmed 0x1234,0x5678,fr10 - set_fr_iimmed 0x9abc,0xdef0,fr11 - inc_gr_immed 16,sp - set_gr_immed -16,gr7 - nldqfu @(sp,gr7),fr8 - test_fr_limmed 0x9abc,0xdef0,fr8 - test_fr_limmed 0x1234,0x5678,fr9 - test_fr_limmed 0xbeef,0xdead,fr10 - test_fr_limmed 0xdead,0xbeef,fr11 - test_gr_gr sp,gr20 - test_spr_limmed 0xc8c0,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,fner1 - test_spr_limmed 0x0000,0x0000,fner0 - - pass diff --git a/sim/testsuite/sim/frv/nldqu.cgs b/sim/testsuite/sim/frv/nldqu.cgs deleted file mode 100644 index a7e8b30fd2a..00000000000 --- a/sim/testsuite/sim/frv/nldqu.cgs +++ /dev/null @@ -1,87 +0,0 @@ -# frv testcase for nldqu @($GRi,$GRj),$GRk -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global nldqu -nldqu: - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - inc_gr_immed -4,sp - set_mem_limmed 0x9abc,0xdef0,sp - set_gr_gr sp,gr20 - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - - set_gr_immed 0,gr7 - nldqu @(sp,gr7),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - test_gr_gr sp,gr20 - test_spr_limmed 0x88c0,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed -16,sp - set_gr_immed 16,gr7 - nldqu @(sp,gr7),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - test_gr_gr sp,gr20 - test_spr_limmed 0x88c0,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 16,sp - set_gr_immed -16,gr7 - nldqu @(sp,gr7),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - test_gr_gr sp,gr20 - test_spr_limmed 0x88c0,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xdead,0xbeef,gr8 - set_gr_limmed 0xbeef,0xdead,gr9 - set_gr_limmed 0x1234,0x5678,gr10 - set_gr_limmed 0x9abc,0xdef0,gr11 - inc_gr_immed 16,sp - set_gr_immed -16,gr7 - set_gr_gr sp,gr8 - nldqu @(gr8,gr7),gr8 - test_gr_limmed 0x9abc,0xdef0,gr8 - test_gr_limmed 0x1234,0x5678,gr9 - test_gr_limmed 0xbeef,0xdead,gr10 - test_gr_limmed 0xdead,0xbeef,gr11 - test_spr_limmed 0x88c0,0x0c01,nesr3 - test_spr_gr neear3,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nldsb.cgs b/sim/testsuite/sim/frv/nldsb.cgs deleted file mode 100644 index 1db547c7cab..00000000000 --- a/sim/testsuite/sim/frv/nldsb.cgs +++ /dev/null @@ -1,42 +0,0 @@ -# frv testcase for nldsb @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldsb -nldsb: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr20 - set_gr_immed 0,gr7 - nldsb @(sp,gr7),gr8 - test_gr_limmed 0xffff,0xffde,gr8 - test_spr_limmed 0x8820,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 1,gr20 - set_gr_immed 1,gr7 - nldsb @(sp,gr7),gr8 - test_gr_limmed 0xffff,0xffad,gr8 - test_spr_limmed 0x8820,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 2,gr20 - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - nldsb @(sp,gr7),gr8 - test_gr_immed 0,gr8 - test_spr_limmed 0x8820,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nldsbi.cgs b/sim/testsuite/sim/frv/nldsbi.cgs deleted file mode 100644 index 4b9dcba3e68..00000000000 --- a/sim/testsuite/sim/frv/nldsbi.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# frv testcase for nldsbi @($GRi,$d12),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldsbi -nldsbi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr20 - nldsbi @(sp,0),gr8 - test_gr_limmed 0xffff,0xffde,gr8 - test_spr_limmed 0x8820,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 1,gr20 - nldsbi @(sp,1),gr8 - test_gr_limmed 0xffff,0xffad,gr8 - test_spr_limmed 0x8820,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 2,gr20 - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - nldsbi @(sp,-1),gr8 - test_gr_immed 0,gr8 - test_spr_limmed 0x8820,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nldsbu.cgs b/sim/testsuite/sim/frv/nldsbu.cgs deleted file mode 100644 index e60ffc011e2..00000000000 --- a/sim/testsuite/sim/frv/nldsbu.cgs +++ /dev/null @@ -1,56 +0,0 @@ -# frv testcase for nldsbu @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldsbu -nldsbu: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - nldsbu @(sp,gr7),gr8 - test_gr_limmed 0xffff,0xffde,gr8 - test_gr_gr sp,gr9 - test_spr_limmed 0x8820,0x0001,nesr0 - test_spr_gr neear0,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 1,gr9 - set_gr_immed 1,gr7 - nldsbu @(sp,gr7),gr8 - test_gr_limmed 0xffff,0xffad,gr8 - test_gr_gr sp,gr9 - test_spr_limmed 0x8820,0x0401,nesr1 - test_spr_gr neear1,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 2,gr9 - inc_gr_immed -1,sp - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - nldsbu @(sp,gr7),gr8 - test_gr_immed 0,gr8 - test_gr_gr sp,gr9 - test_spr_limmed 0x8820,0x0801,nesr2 - test_spr_gr neear2,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed -3,sp - set_mem_limmed 0x0000,0x00da,sp - set_gr_immed 3,gr7 - nldsbu @(sp,gr7),sp - test_gr_limmed 0xffff,0xffda,sp - test_spr_limmed 0x8120,0x0c01,nesr3 - test_spr_gr neear3,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nldsh.cgs b/sim/testsuite/sim/frv/nldsh.cgs deleted file mode 100644 index afc00c49df5..00000000000 --- a/sim/testsuite/sim/frv/nldsh.cgs +++ /dev/null @@ -1,41 +0,0 @@ -# frv testcase for nldsh @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldsh -nldsh: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr20 - set_gr_immed 0,gr7 - nldsh @(sp,gr7),gr8 - test_gr_limmed 0xffff,0xdead,gr8 - test_spr_limmed 0x8860,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 2,gr20 - set_gr_immed 2,gr7 - nldsh @(sp,gr7),gr8 - test_gr_limmed 0xffff,0xbeef,gr8 - test_spr_limmed 0x8860,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - nldsh @(sp,gr7),gr8 - test_gr_immed 0,gr8 - test_spr_limmed 0x8860,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nldshi.cgs b/sim/testsuite/sim/frv/nldshi.cgs deleted file mode 100644 index 60de1564874..00000000000 --- a/sim/testsuite/sim/frv/nldshi.cgs +++ /dev/null @@ -1,38 +0,0 @@ -# frv testcase for nldshi @($GRi,$d12),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldshi -nldshi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr20 - nldshi @(sp,0),gr8 - test_gr_limmed 0xffff,0xdead,gr8 - test_spr_limmed 0x8860,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 2,gr20 - nldshi @(sp,2),gr8 - test_gr_limmed 0xffff,0xbeef,gr8 - test_spr_limmed 0x8860,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - nldshi @(sp,-2),gr8 - test_gr_immed 0,gr8 - test_spr_limmed 0x8860,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nldshu.cgs b/sim/testsuite/sim/frv/nldshu.cgs deleted file mode 100644 index 775b760df8f..00000000000 --- a/sim/testsuite/sim/frv/nldshu.cgs +++ /dev/null @@ -1,55 +0,0 @@ -# frv testcase for nldshu @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldshu -nldshu: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - nldshu @(sp,gr7),gr8 - test_gr_limmed 0xffff,0xdead,gr8 - test_gr_gr sp,gr9 - test_spr_limmed 0x8860,0x0001,nesr0 - test_spr_gr neear0,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 2,gr9 - set_gr_immed 2,gr7 - nldshu @(sp,gr7),gr8 - test_gr_limmed 0xffff,0xbeef,gr8 - test_gr_gr sp,gr9 - test_spr_limmed 0x8860,0x0401,nesr1 - test_spr_gr neear1,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed -2,sp - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - nldshu @(sp,gr7),gr8 - test_gr_immed 0,gr8 - test_gr_gr sp,gr9 - test_spr_limmed 0x8860,0x0801,nesr2 - test_spr_gr neear2,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed -2,sp - set_mem_limmed 0x0000,0xdead,sp - set_gr_immed 2,gr7 - nldshu @(sp,gr7),sp - test_gr_limmed 0xffff,0xdead,sp - test_spr_limmed 0x8160,0x0c01,nesr3 - test_spr_gr neear3,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nldu.cgs b/sim/testsuite/sim/frv/nldu.cgs deleted file mode 100644 index 0d1735e8848..00000000000 --- a/sim/testsuite/sim/frv/nldu.cgs +++ /dev/null @@ -1,55 +0,0 @@ -# frv testcase for nldu @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldu -nldu: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - nldu @(sp,gr7),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_gr sp,gr9 - test_spr_limmed 0x8880,0x0001,nesr0 - test_spr_gr neear0,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - nldu @(sp,gr7),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_gr sp,gr9 - test_spr_limmed 0x8880,0x0401,nesr1 - test_spr_gr neear1,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_gr_limmed 0xbeef,0xdead,gr8 - inc_gr_immed 4,sp - set_gr_immed -4,gr7 - nldu @(sp,gr7),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_gr_gr sp,gr9 - test_spr_limmed 0x8880,0x0801,nesr2 - test_spr_gr neear2,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - nldu @(sp,gr7),sp - test_gr_limmed 0xdead,0xbeef,sp - test_spr_limmed 0x8180,0x0c01,nesr3 - test_spr_gr neear3,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nldub.cgs b/sim/testsuite/sim/frv/nldub.cgs deleted file mode 100644 index 2067bcc089d..00000000000 --- a/sim/testsuite/sim/frv/nldub.cgs +++ /dev/null @@ -1,42 +0,0 @@ -# frv testcase for nldub @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldub -nldub: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr20 - set_gr_immed 0,gr7 - nldub @(sp,gr7),gr8 - test_gr_limmed 0x0000,0x00de,gr8 - test_spr_limmed 0x8800,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 1,gr20 - set_gr_immed 1,gr7 - nldub @(sp,gr7),gr8 - test_gr_limmed 0x0000,0x00ad,gr8 - test_spr_limmed 0x8800,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 2,gr20 - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - nldub @(sp,gr7),gr8 - test_gr_limmed 0x0000,0x0000,gr8 - test_spr_limmed 0x8800,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nldubi.cgs b/sim/testsuite/sim/frv/nldubi.cgs deleted file mode 100644 index 8eba5164120..00000000000 --- a/sim/testsuite/sim/frv/nldubi.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# frv testcase for nldubi @($GRi,$d12),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldubi -nldubi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr20 - nldubi @(sp,0),gr8 - test_gr_limmed 0x0000,0x00de,gr8 - test_spr_limmed 0x8800,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 1,gr20 - nldubi @(sp,1),gr8 - test_gr_limmed 0x0000,0x00ad,gr8 - test_spr_limmed 0x8800,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 2,gr20 - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - nldubi @(sp,-1),gr8 - test_gr_limmed 0x0000,0x0000,gr8 - test_spr_limmed 0x8800,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nldubu.cgs b/sim/testsuite/sim/frv/nldubu.cgs deleted file mode 100644 index acf9d9c818e..00000000000 --- a/sim/testsuite/sim/frv/nldubu.cgs +++ /dev/null @@ -1,55 +0,0 @@ -# frv testcase for nldubu @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nldubu -nldubu: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - nldubu @(sp,gr7),gr8 - test_gr_limmed 0x0000,0x00de,gr8 - test_gr_gr sp,gr9 - test_spr_limmed 0x8800,0x0001,nesr0 - test_spr_gr neear0,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 1,gr9 - set_gr_immed 1,gr7 - nldubu @(sp,gr7),gr8 - test_gr_limmed 0x0000,0x00ad,gr8 - test_gr_gr sp,gr9 - test_spr_limmed 0x8800,0x0401,nesr1 - test_spr_gr neear1,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 2,gr9 - inc_gr_immed -1,sp - set_mem_limmed 0xffff,0xff00,sp - inc_gr_immed 4,sp - set_gr_immed -1,gr7 - nldubu @(sp,gr7),gr8 - test_gr_limmed 0x0000,0x0000,gr8 - test_spr_limmed 0x8800,0x0801,nesr2 - test_spr_gr neear2,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed -3,sp - set_mem_limmed 0xffff,0xffda,sp - set_gr_immed 3,gr7 - nldubu @(sp,gr7),sp - test_gr_limmed 0x0000,0x00da,sp - test_spr_limmed 0x8100,0x0c01,nesr3 - test_spr_gr neear3,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nlduh.cgs b/sim/testsuite/sim/frv/nlduh.cgs deleted file mode 100644 index 1871a22044b..00000000000 --- a/sim/testsuite/sim/frv/nlduh.cgs +++ /dev/null @@ -1,41 +0,0 @@ -# frv testcase for nlduh @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nlduh -nlduh: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr20 - set_gr_immed 0,gr7 - nlduh @(sp,gr7),gr8 - test_gr_limmed 0x0000,0xdead,gr8 - test_spr_limmed 0x8840,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 2,gr20 - set_gr_immed 2,gr7 - nlduh @(sp,gr7),gr8 - test_gr_limmed 0x0000,0xbeef,gr8 - test_spr_limmed 0x8840,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - nlduh @(sp,gr7),gr8 - test_gr_limmed 0x0000,0x0000,gr8 - test_spr_limmed 0x8840,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nlduhi.cgs b/sim/testsuite/sim/frv/nlduhi.cgs deleted file mode 100644 index ae7171ee417..00000000000 --- a/sim/testsuite/sim/frv/nlduhi.cgs +++ /dev/null @@ -1,38 +0,0 @@ -# frv testcase for nlduhi @($GRi,$d12),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nlduhi -nlduhi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr20 - nlduhi @(sp,0),gr8 - test_gr_limmed 0x0000,0xdead,gr8 - test_spr_limmed 0x8840,0x0001,nesr0 - test_spr_gr neear0,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 2,gr20 - nlduhi @(sp,2),gr8 - test_gr_limmed 0x0000,0xbeef,gr8 - test_spr_limmed 0x8840,0x0401,nesr1 - test_spr_gr neear1,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - nlduhi @(sp,-2),gr8 - test_gr_limmed 0x0000,0x0000,gr8 - test_spr_limmed 0x8840,0x0801,nesr2 - test_spr_gr neear2,gr20 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nlduhu.cgs b/sim/testsuite/sim/frv/nlduhu.cgs deleted file mode 100644 index 8142fc59517..00000000000 --- a/sim/testsuite/sim/frv/nlduhu.cgs +++ /dev/null @@ -1,55 +0,0 @@ -# frv testcase for nlduhu @($GRi,$GRj),$GRk -# mach: frv - - .include "testutils.inc" - - start - - .global nlduhu -nlduhu: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xbeef,0xdead,gr8 - - set_gr_gr sp,gr9 - set_gr_immed 0,gr7 - nlduhu @(sp,gr7),gr8 - test_gr_limmed 0x0000,0xdead,gr8 - test_gr_gr sp,gr9 - test_spr_limmed 0x8840,0x0001,nesr0 - test_spr_gr neear0,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed 2,gr9 - set_gr_immed 2,gr7 - nlduhu @(sp,gr7),gr8 - test_gr_limmed 0x0000,0xbeef,gr8 - test_gr_gr sp,gr9 - test_spr_limmed 0x8840,0x0401,nesr1 - test_spr_gr neear1,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed -2,sp - set_mem_limmed 0xffff,0x0000,sp - inc_gr_immed 4,sp - set_gr_immed -2,gr7 - nlduhu @(sp,gr7),gr8 - test_gr_limmed 0x0000,0x0000,gr8 - test_gr_gr sp,gr9 - test_spr_limmed 0x8840,0x0801,nesr2 - test_spr_gr neear2,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - inc_gr_immed -2,sp - set_mem_limmed 0xffff,0xdead,sp - set_gr_immed 2,gr7 - nlduhu @(sp,gr7),sp - test_gr_limmed 0x0000,0xdead,sp - test_spr_limmed 0x8140,0x0c01,nesr3 - test_spr_gr neear3,gr9 - test_spr_limmed 0x0000,0x0000,gner1 - test_spr_limmed 0x0000,0x0000,gner0 - - pass diff --git a/sim/testsuite/sim/frv/nop.cgs b/sim/testsuite/sim/frv/nop.cgs deleted file mode 100644 index 7180066ce9c..00000000000 --- a/sim/testsuite/sim/frv/nop.cgs +++ /dev/null @@ -1,12 +0,0 @@ -# frv testcase for nop -# mach: all - - .include "testutils.inc" - - start - - .global nop -nop: - nop - - pass diff --git a/sim/testsuite/sim/frv/norcr.cgs b/sim/testsuite/sim/frv/norcr.cgs deleted file mode 100644 index e097a1b3667..00000000000 --- a/sim/testsuite/sim/frv/norcr.cgs +++ /dev/null @@ -1,59 +0,0 @@ -# frv testcase for norcr $CCi,$CCj,$CCk -# mach: all - - .include "testutils.inc" - - start - - .global norcr -norcr: - set_spr_immed 0x1b1b,cccr - norcr cc7,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - norcr cc7,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - norcr cc7,cc5,cc3 - test_spr_immed 0x1bdb,cccr - - norcr cc7,cc4,cc3 - test_spr_immed 0x1b9b,cccr - - norcr cc6,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - norcr cc6,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - norcr cc6,cc5,cc3 - test_spr_immed 0x1bdb,cccr - - norcr cc6,cc4,cc3 - test_spr_immed 0x1b9b,cccr - - norcr cc5,cc7,cc3 - test_spr_immed 0x1bdb,cccr - - norcr cc5,cc6,cc3 - test_spr_immed 0x1bdb,cccr - - norcr cc5,cc5,cc3 - test_spr_immed 0x1bdb,cccr - - norcr cc5,cc4,cc3 - test_spr_immed 0x1b9b,cccr - - norcr cc4,cc7,cc3 - test_spr_immed 0x1b9b,cccr - - norcr cc4,cc6,cc3 - test_spr_immed 0x1b9b,cccr - - norcr cc4,cc5,cc3 - test_spr_immed 0x1b9b,cccr - - norcr cc4,cc4,cc3 - test_spr_immed 0x1b9b,cccr - - pass diff --git a/sim/testsuite/sim/frv/norncr.cgs b/sim/testsuite/sim/frv/norncr.cgs deleted file mode 100644 index a7b95da6b6b..00000000000 --- a/sim/testsuite/sim/frv/norncr.cgs +++ /dev/null @@ -1,59 +0,0 @@ -# frv testcase for norncr $CCi,$CCj,$CCk -# mach: all - - .include "testutils.inc" - - start - - .global norncr -norncr: - set_spr_immed 0x1b1b,cccr - norncr cc7,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - norncr cc7,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - norncr cc7,cc5,cc3 - test_spr_immed 0x1bdb,cccr - - norncr cc7,cc4,cc3 - test_spr_immed 0x1b9b,cccr - - norncr cc6,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - norncr cc6,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - norncr cc6,cc5,cc3 - test_spr_immed 0x1bdb,cccr - - norncr cc6,cc4,cc3 - test_spr_immed 0x1b9b,cccr - - norncr cc5,cc7,cc3 - test_spr_immed 0x1b9b,cccr - - norncr cc5,cc6,cc3 - test_spr_immed 0x1b9b,cccr - - norncr cc5,cc5,cc3 - test_spr_immed 0x1b9b,cccr - - norncr cc5,cc4,cc3 - test_spr_immed 0x1b9b,cccr - - norncr cc4,cc7,cc3 - test_spr_immed 0x1bdb,cccr - - norncr cc4,cc6,cc3 - test_spr_immed 0x1bdb,cccr - - norncr cc4,cc5,cc3 - test_spr_immed 0x1bdb,cccr - - norncr cc4,cc4,cc3 - test_spr_immed 0x1b9b,cccr - - pass diff --git a/sim/testsuite/sim/frv/not.cgs b/sim/testsuite/sim/frv/not.cgs deleted file mode 100644 index e44eabfcd0a..00000000000 --- a/sim/testsuite/sim/frv/not.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# frv testcase for not $GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global not -not: - set_gr_limmed 0xaaaa,0xaaaa,gr7 - not gr7,gr7 - test_gr_limmed 0x5555,0x5555,gr7 - - set_gr_limmed 0xdead,0xbeef,gr7 - not gr7,gr7 - test_gr_limmed 0x2152,0x4110,gr7 - - pass diff --git a/sim/testsuite/sim/frv/notcr.cgs b/sim/testsuite/sim/frv/notcr.cgs deleted file mode 100644 index e6c08e0603a..00000000000 --- a/sim/testsuite/sim/frv/notcr.cgs +++ /dev/null @@ -1,23 +0,0 @@ -# frv testcase for notcr $CCi,$CCj,$CCk -# mach: all - - .include "testutils.inc" - - start - - .global notcr -notcr: - set_spr_immed 0x1b1b,cccr - notcr cc7,cc3 - test_spr_immed 0x1b5b,cccr - - notcr cc6,cc3 - test_spr_immed 0x1b1b,cccr - - notcr cc5,cc3 - test_spr_immed 0x1bdb,cccr - - notcr cc4,cc3 - test_spr_immed 0x1b9b,cccr - - pass diff --git a/sim/testsuite/sim/frv/nsdiv.cgs b/sim/testsuite/sim/frv/nsdiv.cgs deleted file mode 100644 index 533f2ef5c94..00000000000 --- a/sim/testsuite/sim/frv/nsdiv.cgs +++ /dev/null @@ -1,64 +0,0 @@ -# frv testcase for nsdiv $GRi,$GRj,$GRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - start - - .global nsdiv -nsdiv: - set_spr_immed 0,gner0 - set_spr_immed 0,gner1 - - ; simple division 12 / 3 - set_gr_immed 3,gr3 - set_gr_immed 12,gr1 - nsdiv gr1,gr3,gr2 - test_gr_immed 4,gr2 - test_spr_immed 0,gner0 - test_spr_immed 0,gner1 - - ; Random example - set_gr_limmed 0x0123,0x4567,gr3 - set_gr_limmed 0xfedc,0xba98,gr1 - nsdiv gr1,gr3,gr2 - test_gr_immed -1,gr2 - test_spr_immed 0,gner0 - test_spr_immed 0,gner1 - - ; Special case from the Arch Spec Vol 2 - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - set_spr_immed 4,gner1 ; turn on NE bit for gr2 - nsdiv gr1,gr3,gr2 ; overflow is masked - test_gr_limmed 0x7fff,0xffff,gr2 - test_spr_bits 0x4,2,1,isr ; isr.aexc is set - test_spr_immed 0,gner0 - test_spr_immed 0,gner1 - - nsdiv gr1,gr0,gr32 ; divide by zero - test_spr_immed 1,gner0 - test_spr_immed 0,gner1 - - and_spr_immed -33,isr ; turn off isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - nsdiv gr1,gr3,gr2 - test_gr_limmed 0x8000,0x0000,gr2 - test_spr_immed 1,gner0 - test_spr_immed 4,gner1 - - nsdiv gr1,gr0,gr10 ; divide by zero - test_spr_immed 1,gner0 - test_spr_immed 0x00000404,gner1 - - ; simple division 12 / 3 -- should turn off ne flag - set_gr_immed 3,gr3 - set_gr_immed 12,gr1 - nsdiv gr1,gr3,gr2 - test_gr_immed 4,gr2 - test_spr_immed 1,gner0 - test_spr_immed 0x00000400,gner1 - - pass diff --git a/sim/testsuite/sim/frv/nsdivi.cgs b/sim/testsuite/sim/frv/nsdivi.cgs deleted file mode 100644 index 014fadd5814..00000000000 --- a/sim/testsuite/sim/frv/nsdivi.cgs +++ /dev/null @@ -1,64 +0,0 @@ -# frv testcase for nsdivi $GRi,$s12,$GRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - start - - .global nsdivi -nsdivi: - set_spr_immed 0,gner0 - set_spr_immed 0,gner1 - - ; simple division 12 / 3 - set_gr_immed 12,gr1 - nsdivi gr1,3,gr2 - test_gr_immed 4,gr2 - test_spr_immed 0,gner0 - test_spr_immed 0,gner1 - - ; Random example - set_gr_limmed 0xfedc,0xba98,gr1 - nsdivi gr1,0x7ff,gr2 - test_gr_limmed 0xffff,0xdb93,gr2 - test_spr_immed 0,gner0 - test_spr_immed 0,gner1 - - ; Random negative example - set_gr_limmed 0xfedc,0xba98,gr1 - nsdivi gr1,-2048,gr2 - test_gr_immed 0x2468,gr2 - test_spr_immed 0,gner0 - test_spr_immed 0,gner1 - - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_limmed 0x8000,0x0000,gr1 - nsdivi gr1,-1,gr2 - test_gr_limmed 0x7fff,0xffff,gr2 - test_spr_immed 0,gner0 - test_spr_immed 0,gner1 - - nsdivi gr1,0,gr32 ; divide by zero - test_spr_immed 1,gner0 - test_spr_immed 0,gner1 - - ; Special case from the Arch Spec Vol 2 - and_spr_immed -33,isr ; turn off isr.edem - set_gr_limmed 0x8000,0x0000,gr1 - nsdivi gr1,-1,gr2 - test_gr_limmed 0x8000,0x0000,gr2 - test_spr_immed 1,gner0 - test_spr_immed 4,gner1 - - nsdivi gr1,0,gr10 ; divide by zero - test_spr_immed 1,gner0 - test_spr_immed 0x00000404,gner1 - - ; simple division 12 / 3 -- should turn off ne flag - set_gr_immed 12,gr1 - nsdivi gr1,3,gr2 - test_gr_immed 4,gr2 - test_spr_immed 1,gner0 - test_spr_immed 0x00000400,gner1 - - pass diff --git a/sim/testsuite/sim/frv/nudiv.cgs b/sim/testsuite/sim/frv/nudiv.cgs deleted file mode 100644 index 58bce82af09..00000000000 --- a/sim/testsuite/sim/frv/nudiv.cgs +++ /dev/null @@ -1,49 +0,0 @@ -# frv testcase for nudiv $GRi,$GRj,$GRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - start - - .global nudiv -nudiv: - set_spr_immed 0,gner0 - set_spr_immed 0,gner1 - - ; simple division 12 / 3 - set_gr_immed 0x00000003,gr2 - set_gr_immed 0x0000000c,gr3 - nudiv gr3,gr2,gr3 - test_gr_immed 0x00000003,gr2 - test_gr_immed 0x00000004,gr3 - test_spr_immed 0,gner0 - test_spr_immed 0,gner1 - - ; example 1 from the fr30 manual - set_gr_limmed 0x0123,0x4567,gr2 - set_gr_limmed 0xfedc,0xba98,gr3 - nudiv gr3,gr2,gr3 - test_gr_limmed 0x0123,0x4567,gr2 - test_gr_immed 0x000000e0,gr3 - test_spr_immed 0,gner0 - test_spr_immed 0,gner1 - - or_spr_immed 0x20,isr ; turn on isr.edem - nudiv gr1,gr0,gr32 ; divide by zero - test_spr_immed 1,gner0 - test_spr_immed 0,gner1 - - and_spr_immed -33,isr ; turn off isr.edem - nudiv gr1,gr0,gr10 ; divide by zero - test_spr_immed 1,gner0 - test_spr_immed 0x00000400,gner1 - - ; simple division 12 / 3 -- should turn off ne flag - set_gr_immed 12,gr1 - set_gr_immed 3,gr3 - nudiv gr1,gr3,gr10 - test_gr_immed 4,gr10 - test_spr_immed 1,gner0 - test_spr_immed 0,gner1 - - pass diff --git a/sim/testsuite/sim/frv/nudivi.cgs b/sim/testsuite/sim/frv/nudivi.cgs deleted file mode 100644 index 2426eb38fdc..00000000000 --- a/sim/testsuite/sim/frv/nudivi.cgs +++ /dev/null @@ -1,51 +0,0 @@ -# frv testcase for nudivi $GRi,$s12,$GRk -# mach: fr500 fr550 frv - - .include "testutils.inc" - - start - - .global nudivi -nudivi: - set_spr_immed 0,gner0 - set_spr_immed 0,gner1 - - ; simple division 12 / 3 - set_gr_immed 0x0000000c,gr3 - nudivi gr3,3,gr3 - test_gr_immed 0x00000004,gr3 - test_spr_immed 0,gner0 - test_spr_immed 0,gner1 - - ; random example - set_gr_limmed 0xfedc,0xba98,gr3 - nudivi gr3,0x7ff,gr3 - test_gr_limmed 0x001f,0xdf93,gr3 - test_spr_immed 0,gner0 - test_spr_immed 0,gner1 - - ; random example - set_gr_limmed 0xffff,0xffff,gr3 - nudivi gr3,-2048,gr3 - test_gr_immed 1,gr3 - test_spr_immed 0,gner0 - test_spr_immed 0,gner1 - - or_spr_immed 0x20,isr ; turn on isr.edem - nudivi gr1,0,gr32 ; divide by zero - test_spr_immed 1,gner0 - test_spr_immed 0,gner1 - - and_spr_immed -33,isr ; turn off isr.edem - nudivi gr1,0,gr10 ; divide by zero - test_spr_immed 1,gner0 - test_spr_immed 0x00000400,gner1 - - ; simple division 12 / 3 -- should turn off ne flag - set_gr_immed 12,gr1 - nudivi gr1,3,gr10 - test_gr_immed 4,gr10 - test_spr_immed 1,gner0 - test_spr_immed 0,gner1 - - pass diff --git a/sim/testsuite/sim/frv/or.cgs b/sim/testsuite/sim/frv/or.cgs deleted file mode 100644 index b432429a013..00000000000 --- a/sim/testsuite/sim/frv/or.cgs +++ /dev/null @@ -1,31 +0,0 @@ -# frv testcase for or $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global or -or: - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - or gr7,gr8,gr8 - test_icc 0 1 1 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 0x00000000,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - or gr7,gr8,gr8 - test_icc 1 0 0 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - or gr7,gr8,gr8 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0xdead,0xbeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/orcc.cgs b/sim/testsuite/sim/frv/orcc.cgs deleted file mode 100644 index a0a3e5bdeda..00000000000 --- a/sim/testsuite/sim/frv/orcc.cgs +++ /dev/null @@ -1,31 +0,0 @@ -# frv testcase for orcc $GRi,$GRj,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global orcc -orcc: - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - orcc gr7,gr8,gr8,icc0 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 0x00000000,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - orcc gr7,gr8,gr8,icc0 - test_icc 0 1 0 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - orcc gr7,gr8,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xdead,0xbeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/orcr.cgs b/sim/testsuite/sim/frv/orcr.cgs deleted file mode 100644 index a5114b248e7..00000000000 --- a/sim/testsuite/sim/frv/orcr.cgs +++ /dev/null @@ -1,59 +0,0 @@ -# frv testcase for orcr $CCi,$CCj,$CCk -# mach: all - - .include "testutils.inc" - - start - - .global orcr -orcr: - set_spr_immed 0x1b1b,cccr - orcr cc7,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - orcr cc7,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - orcr cc7,cc5,cc3 - test_spr_immed 0x1b9b,cccr - - orcr cc7,cc4,cc3 - test_spr_immed 0x1bdb,cccr - - orcr cc6,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - orcr cc6,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - orcr cc6,cc5,cc3 - test_spr_immed 0x1b9b,cccr - - orcr cc6,cc4,cc3 - test_spr_immed 0x1bdb,cccr - - orcr cc5,cc7,cc3 - test_spr_immed 0x1b9b,cccr - - orcr cc5,cc6,cc3 - test_spr_immed 0x1b9b,cccr - - orcr cc5,cc5,cc3 - test_spr_immed 0x1b9b,cccr - - orcr cc5,cc4,cc3 - test_spr_immed 0x1bdb,cccr - - orcr cc4,cc7,cc3 - test_spr_immed 0x1bdb,cccr - - orcr cc4,cc6,cc3 - test_spr_immed 0x1bdb,cccr - - orcr cc4,cc5,cc3 - test_spr_immed 0x1bdb,cccr - - orcr cc4,cc4,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/ori.cgs b/sim/testsuite/sim/frv/ori.cgs deleted file mode 100644 index aa1d61a1d0a..00000000000 --- a/sim/testsuite/sim/frv/ori.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# frv testcase for ori $GRi,$s12,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global ori -ori: - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_icc 0x07,0 ; Set mask opposite of expected - ori gr7,0x555,gr8 - test_icc 0 1 1 1 icc0 - test_gr_limmed 0xaaaa,0xafff,gr8 - - set_gr_immed 0x00000000,gr7 - set_icc 0x08,0 ; Set mask opposite of expected - ori gr7,0,gr8 - test_icc 1 0 0 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0xb800,gr7 - set_icc 0x05,0 ; Set mask opposite of expected - ori gr7,0x6ef,gr8 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xdead,0xb000,gr7 - set_icc 0x05,0 ; Set mask opposite of expected - ori gr7,-273,gr8 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0xffff,0xfeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/oricc.cgs b/sim/testsuite/sim/frv/oricc.cgs deleted file mode 100644 index 71e6d53320a..00000000000 --- a/sim/testsuite/sim/frv/oricc.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# frv testcase for oricc $GRi,$s10,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global oricc -oricc: - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_icc 0x07,0 ; Set mask opposite of expected - oricc gr7,0x155,gr8,icc0 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0xaaaa,0xabff,gr8 - - set_gr_immed 0x00000000,gr7 - set_icc 0x08,0 ; Set mask opposite of expected - oricc gr7,0,gr8,icc0 - test_icc 0 1 0 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0xbe00,gr7 - set_icc 0x05,0 ; Set mask opposite of expected - oricc gr7,0x0ef,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xdead,0xbeef,gr8 - - set_gr_limmed 0xdead,0xb000,gr7 - set_icc 0x05,0 ; Set mask opposite of expected - oricc gr7,-273,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xffff,0xfeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/orncr.cgs b/sim/testsuite/sim/frv/orncr.cgs deleted file mode 100644 index b0e4e5914f8..00000000000 --- a/sim/testsuite/sim/frv/orncr.cgs +++ /dev/null @@ -1,59 +0,0 @@ -# frv testcase for orncr $CCi,$CCj,$CCk -# mach: all - - .include "testutils.inc" - - start - - .global orncr -orncr: - set_spr_immed 0x1b1b,cccr - orncr cc7,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - orncr cc7,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - orncr cc7,cc5,cc3 - test_spr_immed 0x1b9b,cccr - - orncr cc7,cc4,cc3 - test_spr_immed 0x1bdb,cccr - - orncr cc6,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - orncr cc6,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - orncr cc6,cc5,cc3 - test_spr_immed 0x1b9b,cccr - - orncr cc6,cc4,cc3 - test_spr_immed 0x1bdb,cccr - - orncr cc5,cc7,cc3 - test_spr_immed 0x1bdb,cccr - - orncr cc5,cc6,cc3 - test_spr_immed 0x1bdb,cccr - - orncr cc5,cc5,cc3 - test_spr_immed 0x1bdb,cccr - - orncr cc5,cc4,cc3 - test_spr_immed 0x1bdb,cccr - - orncr cc4,cc7,cc3 - test_spr_immed 0x1b9b,cccr - - orncr cc4,cc6,cc3 - test_spr_immed 0x1b9b,cccr - - orncr cc4,cc5,cc3 - test_spr_immed 0x1b9b,cccr - - orncr cc4,cc4,cc3 - test_spr_immed 0x1bdb,cccr - - pass diff --git a/sim/testsuite/sim/frv/parallel.exp b/sim/testsuite/sim/frv/parallel.exp deleted file mode 100644 index 8101a67afb5..00000000000 --- a/sim/testsuite/sim/frv/parallel.exp +++ /dev/null @@ -1,19 +0,0 @@ -# FRV simulator testsuite. - -if [istarget frv*-*] { - # load support procs (none yet) - # load_lib cgen.exp - # all machines - set all_machs "frv fr500 fr550 fr400" - set cpu_option -mcpu - - # The .pcgs suffix is for "parallel cgen .s". - foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.pcgs]] { - # If we're only testing specific files and this isn't one of them, - # skip it. - if ![runtest_file_p $runtests $src] { - continue - } - run_sim_test $src $all_machs - } -} diff --git a/sim/testsuite/sim/frv/ret.cgs b/sim/testsuite/sim/frv/ret.cgs deleted file mode 100644 index 14479980a59..00000000000 --- a/sim/testsuite/sim/frv/ret.cgs +++ /dev/null @@ -1,91 +0,0 @@ -# frv testcase for ret -# mach: all - - .include "testutils.inc" - - start - - .global ret -ret: - set_spr_addr ok1,lr - set_icc 0x0 0 - ret - fail -ok1: - set_spr_addr ok2,lr - set_icc 0x1 1 - ret - fail -ok2: - set_spr_addr ok3,lr - set_icc 0x2 2 - ret - fail -ok3: - set_spr_addr ok4,lr - set_icc 0x3 3 - ret - fail -ok4: - set_spr_addr ok5,lr - set_icc 0x4 0 - ret - fail -ok5: - set_spr_addr ok6,lr - set_icc 0x5 1 - ret - fail -ok6: - set_spr_addr ok7,lr - set_icc 0x6 2 - ret - fail -ok7: - set_spr_addr ok8,lr - set_icc 0x7 3 - ret - fail -ok8: - set_spr_addr ok9,lr - set_icc 0x8 0 - ret - fail -ok9: - set_spr_addr oka,lr - set_icc 0x9 1 - ret - fail -oka: - set_spr_addr okb,lr - set_icc 0xa 2 - ret - fail -okb: - set_spr_addr okc,lr - set_icc 0xb 3 - ret - fail -okc: - set_spr_addr okd,lr - set_icc 0xc 0 - ret - fail -okd: - set_spr_addr oke,lr - set_icc 0xd 1 - ret - fail -oke: - set_spr_addr okf,lr - set_icc 0xe 2 - ret - fail -okf: - set_spr_addr okg,lr - set_icc 0xf 3 - ret - fail -okg: - - pass diff --git a/sim/testsuite/sim/frv/rett.cgs b/sim/testsuite/sim/frv/rett.cgs deleted file mode 100644 index f964baea2aa..00000000000 --- a/sim/testsuite/sim/frv/rett.cgs +++ /dev/null @@ -1,30 +0,0 @@ -# frv testcase for rett $debug -# mach: all - - .include "testutils.inc" - - start - - .global rett -rett: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x0 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 -ok0: - test_gr_immed 1,gr7 - pass - fail -ok1: - inc_gr_immed 1,gr7 - rett 1 ; should be a nop - rett 0 - fail diff --git a/sim/testsuite/sim/frv/scan.cgs b/sim/testsuite/sim/frv/scan.cgs deleted file mode 100644 index d19107df12e..00000000000 --- a/sim/testsuite/sim/frv/scan.cgs +++ /dev/null @@ -1,73 +0,0 @@ -# frv testcase for scan $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global scan -scan: - set_gr_limmed 0x2aaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - scan gr7,gr8,gr9 - test_gr_immed 0,gr9 - test_gr_limmed 0x2aaa,0xaaaa,gr7 - test_gr_limmed 0xaaaa,0xaaaa,gr8 - - set_gr_limmed 0x2aaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaab,gr8 - scan gr7,gr8,gr9 - test_gr_immed 0,gr9 - test_gr_limmed 0x2aaa,0xaaaa,gr7 - test_gr_limmed 0xaaaa,0xaaab,gr8 - - set_gr_limmed 0xd555,0x5555,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - scan gr7,gr8,gr9 - test_gr_immed 63,gr9 - test_gr_limmed 0xd555,0x5555,gr7 - test_gr_limmed 0xaaaa,0xaaaa,gr8 - - set_gr_limmed 0xd555,0x5555,gr7 - set_gr_limmed 0xaaaa,0xaaab,gr8 - scan gr7,gr8,gr9 - test_gr_immed 63,gr9 - test_gr_limmed 0xd555,0x5555,gr7 - test_gr_limmed 0xaaaa,0xaaab,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0x7fff,0xffff,gr8 - scan gr7,gr8,gr9 - test_gr_immed 0,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xbfff,0xffff,gr8 - scan gr7,gr8,gr9 - test_gr_immed 2,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xbfff,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xfffe,0xffff,gr8 - scan gr7,gr8,gr9 - test_gr_immed 16,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xfffe,0xffff,gr8 - - set_gr_limmed 0xffff,0xffff,gr7 - set_gr_limmed 0xffff,0xfffd,gr8 - scan gr7,gr8,gr9 - test_gr_immed 31,gr9 - test_gr_limmed 0xffff,0xffff,gr7 - test_gr_limmed 0xffff,0xfffd,gr8 - - set_gr_limmed 0xdead,0xbeef,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - scan gr7,gr8,gr9 - test_gr_immed 7,gr9 - test_gr_limmed 0xdead,0xbeef,gr7 - test_gr_limmed 0xbeef,0xdead,gr8 - - pass diff --git a/sim/testsuite/sim/frv/scani.cgs b/sim/testsuite/sim/frv/scani.cgs deleted file mode 100644 index 97175dc1051..00000000000 --- a/sim/testsuite/sim/frv/scani.cgs +++ /dev/null @@ -1,55 +0,0 @@ -# frv testcase for scani $GRi,$s12,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global scani -scani: - set_gr_limmed 0xffff,0xfeaa,gr7 - scani gr7,0x2aa,gr9 - test_gr_immed 0,gr9 - test_gr_limmed 0xffff,0xfeaa,gr7 - - set_gr_limmed 0xffff,0xfeaa,gr7 - scani gr7,0x2ab,gr9 - test_gr_immed 0,gr9 - test_gr_limmed 0xffff,0xfeaa,gr7 - - set_gr_limmed 0x0000,0x0155,gr7 - scani gr7,0x2aa,gr9 - test_gr_immed 63,gr9 - test_gr_limmed 0x0000,0x0155,gr7 - - set_gr_limmed 0x0000,0x0155,gr7 - scani gr7,0x2ab,gr9 - test_gr_immed 63,gr9 - test_gr_limmed 0x0000,0x0155,gr7 - - set_gr_limmed 0x7fff,0xffff,gr7 - scani gr7,-1,gr9 - test_gr_immed 0,gr9 - test_gr_limmed 0x7fff,0xffff,gr7 - - set_gr_limmed 0xbfff,0xffff,gr7 - scani gr7,-1,gr9 - test_gr_immed 1,gr9 - test_gr_limmed 0xbfff,0xffff,gr7 - - set_gr_limmed 0xfffe,0xffff,gr7 - scani gr7,-1,gr9 - test_gr_immed 15,gr9 - test_gr_limmed 0xfffe,0xffff,gr7 - - set_gr_limmed 0xffff,0xfffd,gr7 - scani gr7,-1,gr9 - test_gr_immed 30,gr9 - test_gr_limmed 0xffff,0xfffd,gr7 - - set_gr_limmed 0xdead,0xbeef,gr7 - scani gr7,-2048,gr9 - test_gr_immed 2,gr9 - test_gr_limmed 0xdead,0xbeef,gr7 - - pass diff --git a/sim/testsuite/sim/frv/sdiv.cgs b/sim/testsuite/sim/frv/sdiv.cgs deleted file mode 100644 index d193b2318c1..00000000000 --- a/sim/testsuite/sim/frv/sdiv.cgs +++ /dev/null @@ -1,75 +0,0 @@ -# frv testcase for sdiv $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global sdiv -sdiv: - ; simple division 12 / 3 - set_gr_immed 3,gr3 - set_gr_immed 12,gr1 - sdiv gr1,gr3,gr2 - test_gr_immed 4,gr2 - - ; Random example - set_gr_limmed 0x0123,0x4567,gr3 - set_gr_limmed 0xfedc,0xba98,gr1 - sdiv gr1,gr3,gr2 - test_gr_immed -1,gr2 - - ; Special case from the Arch Spec Vol 2 - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 - sdiv gr1,gr3,gr2 - test_gr_limmed 0x7fff,0xffff,gr2 - test_spr_bits 0x4,2,1,isr ; isr.aexc is set - - and_spr_immed -33,isr ; turn off isr.edem - ; set up exception handler - set_psr_et 1 - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x170,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_gr_immed 0,gr15 - - ; divide will cause overflow - set_spr_addr ok1,lr - set_gr_addr e1,gr17 - set_gr_immed -1,gr3 - set_gr_limmed 0x8000,0x0000,gr1 -e1: sdiv gr1,gr3,gr2 ; overflow - test_gr_immed 1,gr15 - test_gr_limmed 0x8000,0x0000,gr2; gr2 updated - - ; divide by zero - set_spr_addr ok2,lr - set_gr_addr e2,gr17 - set_gr_immed 0xdeadbeef,gr2 -e2: sdiv gr1,gr0,gr2 ; divide by zero - test_gr_immed 2,gr15 ; handler called - test_gr_immed 0xdeadbeef,gr2 ; gr2 not updated. - - pass - -ok1: ; exception handler for overflow - test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set - test_spr_gr epcr0,gr17 ; return address set - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - inc_gr_immed 1,gr15 - rett 0 - fail - -ok2: ; exception handler for divide by zero - test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set - test_spr_gr epcr0,gr17 ; return address set - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/sdivi.cgs b/sim/testsuite/sim/frv/sdivi.cgs deleted file mode 100644 index eb781e720a4..00000000000 --- a/sim/testsuite/sim/frv/sdivi.cgs +++ /dev/null @@ -1,74 +0,0 @@ -# frv testcase for sdivi $GRi,$s12,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global sdivi -sdivi: - ; simple division 12 / 3 - set_gr_immed 12,gr1 - sdivi gr1,3,gr2 - test_gr_immed 4,gr2 - - ; Random example - set_gr_limmed 0xfedc,0xba98,gr1 - sdivi gr1,0x7ff,gr2 - test_gr_limmed 0xffff,0xdb93,gr2 - - ; Random negative example - set_gr_limmed 0xfedc,0xba98,gr1 - sdivi gr1,-2048,gr2 - test_gr_immed 0x2468,gr2 - - ; Special case from the Arch Spec Vol 2 - or_spr_immed 0x20,isr ; turn on isr.edem - set_gr_limmed 0x8000,0x0000,gr1 - sdivi gr1,-1,gr2 - test_gr_limmed 0x7fff,0xffff,gr2 - test_spr_bits 0x4,2,1,isr ; isr.aexc is set - - and_spr_immed -33,isr ; turn off isr.edem - ; set up exception handler - set_psr_et 1 - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x170,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_gr_immed 0,gr15 - - ; divide will cause overflow - set_spr_addr ok1,lr - set_gr_addr e1,gr17 - set_gr_limmed 0x8000,0x0000,gr1 -e1: sdivi gr1,-1,gr2 - test_gr_immed 1,gr15 - test_gr_limmed 0x8000,0x0000,gr2 - - ; divide by zero - set_spr_addr ok2,lr - set_gr_addr e2,gr17 -e2: sdivi gr1,0,gr2 ; divide by zero - test_gr_immed 2,gr15 - - pass - -ok1: ; exception handler for overflow - test_spr_bits 0x18,3,0x2,isr ; isr.dtt is set - test_spr_gr epcr0,gr17 ; return address set - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - inc_gr_immed 1,gr15 - rett 0 - fail - -ok2: ; exception handler for divide by zero - test_spr_bits 0x18,3,0x3,isr ; isr.dtt is set - test_spr_gr epcr0,gr17 ; return address set - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/sethi.cgs b/sim/testsuite/sim/frv/sethi.cgs deleted file mode 100644 index 00a3bdd6137..00000000000 --- a/sim/testsuite/sim/frv/sethi.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# frv testcase for sethi $s16,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global sethi -sethi: - set_gr_immed 0,gr1 - sethi 0,gr1 - test_gr_immed 0,gr1 - sethi 1,gr1 - test_gr_immed 0x00010000,gr1 - sethi 0x7fff,gr1 - test_gr_immed 0x7fff0000,gr1 - - pass diff --git a/sim/testsuite/sim/frv/sethilo.pcgs b/sim/testsuite/sim/frv/sethilo.pcgs deleted file mode 100644 index c8e7b602ce5..00000000000 --- a/sim/testsuite/sim/frv/sethilo.pcgs +++ /dev/null @@ -1,18 +0,0 @@ -# frv parallel testcase for sethi $s16,$GRk and setlo $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global sethilo -sethilo: - sethi.p 0xdead,gr7 - setlo 0xbeef,gr7 - test_gr_immed 0xdeadbeef,gr7 - - setlo.p 0xdead,gr7 - sethi 0xbeef,gr7 - test_gr_immed 0xbeefdead,gr7 - - pass diff --git a/sim/testsuite/sim/frv/setlo.cgs b/sim/testsuite/sim/frv/setlo.cgs deleted file mode 100644 index 6bdac2eba2e..00000000000 --- a/sim/testsuite/sim/frv/setlo.cgs +++ /dev/null @@ -1,18 +0,0 @@ -# frv testcase for setlo $s16,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global setlo -setlo: - set_gr_immed 0,gr1 - setlo 0,gr1 - test_gr_immed 0,gr1 - setlo 1,gr1 - test_gr_immed 1,gr1 - setlo 0x7fff,gr1 - test_gr_immed 0x7fff,gr1 - - pass diff --git a/sim/testsuite/sim/frv/setlos.cgs b/sim/testsuite/sim/frv/setlos.cgs deleted file mode 100644 index 8979d13a7e1..00000000000 --- a/sim/testsuite/sim/frv/setlos.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# frv testcase for setlos $s16,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global setlos -setlos: - setlos 0,gr1 - test_gr_immed 0,gr1 - setlos 1,gr1 - test_gr_immed 1,gr1 - setlos 0x7fff,gr1 - test_gr_immed 0x7fff,gr1 - setlos -1,gr1 - test_gr_immed -1,gr1 - setlos -32768,gr1 - test_gr_immed -32768,gr1 - - pass diff --git a/sim/testsuite/sim/frv/sll.cgs b/sim/testsuite/sim/frv/sll.cgs deleted file mode 100644 index 9103cf6874a..00000000000 --- a/sim/testsuite/sim/frv/sll.cgs +++ /dev/null @@ -1,38 +0,0 @@ -# frv testcase for sll $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global sll -sll: - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_immed 2,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - sll gr8,gr7,gr8 - test_icc 1 1 0 1 icc0 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - sll gr8,gr7,gr8 - test_icc 1 1 1 1 icc0 - test_gr_immed 4,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_immed 1,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - sll gr8,gr7,gr8 - test_icc 0 1 1 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_immed 2,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - sll gr8,gr7,gr8 - test_icc 1 0 1 0 icc0 - test_gr_immed 0x00000000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/sllcc.cgs b/sim/testsuite/sim/frv/sllcc.cgs deleted file mode 100644 index 533b5045399..00000000000 --- a/sim/testsuite/sim/frv/sllcc.cgs +++ /dev/null @@ -1,38 +0,0 @@ -# frv testcase for sllcc $GRi,$GRj,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global sllcc -sllcc: - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - sllcc gr8,gr7,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_immed 2,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - sllcc gr8,gr7,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_immed 4,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_immed 1,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - sllcc gr8,gr7,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_immed 2,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - sllcc gr8,gr7,gr8,icc0 - test_icc 0 1 1 0 icc0 - test_gr_immed 0x00000000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/slli.cgs b/sim/testsuite/sim/frv/slli.cgs deleted file mode 100644 index 80c25c0043a..00000000000 --- a/sim/testsuite/sim/frv/slli.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# frv testcase for slli $GRi,$s12,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global slli -slli: - set_gr_immed 2,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - slli gr8,0x7e0,gr8 ; Shift by 0 - test_icc 1 1 0 1 icc0 - test_gr_immed 2,gr8 - - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - slli gr8,-31,gr8 ; Shift by 1 - test_icc 1 1 1 1 icc0 - test_gr_immed 4,gr8 - - set_gr_immed 1,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - slli gr8,31,gr8 ; Shift by 31 - test_icc 0 1 1 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_immed 2,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - slli gr8,31,gr8 ; clear register - test_icc 1 0 1 0 icc0 - test_gr_immed 0x00000000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/sllicc.cgs b/sim/testsuite/sim/frv/sllicc.cgs deleted file mode 100644 index b8e4c7da788..00000000000 --- a/sim/testsuite/sim/frv/sllicc.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# frv testcase for sllicc $GRi,$s10,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global sllicc -sllicc: - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - sllicc gr8,0x1e0,gr8,icc0 ; Shift by 0 - test_icc 0 0 0 1 icc0 - test_gr_immed 2,gr8 - - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - sllicc gr8,-31,gr8,icc0 ; Shift by 1 - test_icc 0 0 0 1 icc0 - test_gr_immed 4,gr8 - - set_gr_immed 1,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - sllicc gr8,31,gr8,icc0 ; Shift by 31 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_immed 2,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - sllicc gr8,31,gr8,icc0 ; clear register - test_icc 0 1 1 0 icc0 - test_gr_immed 0x00000000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/smul.cgs b/sim/testsuite/sim/frv/smul.cgs deleted file mode 100644 index ed065a93d14..00000000000 --- a/sim/testsuite/sim/frv/smul.cgs +++ /dev/null @@ -1,182 +0,0 @@ -# frv testcase for smul $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global smul -smul: - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - smul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - smul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - smul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - smul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - smul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - smul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - smul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - smul gr7,gr8,gr8 - test_gr_immed 1,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - smul gr7,gr8,gr8 - test_gr_limmed 0x3fff,0xffff,gr8 - test_gr_immed 0x00000001,gr9 - - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - smul gr7,gr8,gr8 - test_gr_immed -1,gr8 - test_gr_immed -6,gr9 - - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - smul gr7,gr8,gr8 - test_gr_immed -1,gr8 - test_gr_immed -6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - smul gr7,gr8,gr8 - test_gr_immed -1,gr8 - test_gr_immed -2,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - smul gr7,gr8,gr8 - test_gr_immed -1,gr8 - test_gr_immed -2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - smul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - smul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - smul gr7,gr8,gr8 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0xbfff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - smul gr7,gr8,gr8 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_gr_immed -2,gr8 - smul gr7,gr8,gr8 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - smul gr7,gr8,gr8 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x8000,0x0000,gr8 - smul gr7,gr8,gr8 - test_gr_limmed 0xc000,0x0000,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - smul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - smul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - smul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - smul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - smul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - smul gr7,gr8,gr8 - test_gr_immed 1,gr8 - test_gr_immed 0x00000000,gr9 - - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_gr_limmed 0x8000,0x0001,gr8 - smul gr7,gr8,gr8 - test_gr_limmed 0x3fff,0xffff,gr8 - test_gr_immed 0x00000001,gr9 - - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - smul gr7,gr8,gr8 - test_gr_limmed 0x4000,0x0000,gr8 - test_gr_immed 0x00000000,gr9 - - pass diff --git a/sim/testsuite/sim/frv/smulcc.cgs b/sim/testsuite/sim/frv/smulcc.cgs deleted file mode 100644 index 76a009ec22f..00000000000 --- a/sim/testsuite/sim/frv/smulcc.cgs +++ /dev/null @@ -1,238 +0,0 @@ -# frv testcase for smulcc $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global smulcc -smulcc: - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_icc 0x0,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - set_icc 0x1,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_icc 0x2,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - set_icc 0xb,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 1 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_icc 0x8,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 1 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - set_icc 0xd,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - set_icc 0xe,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed 4,gr8 - set_icc 0xf,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 0 1 1 icc0 - test_gr_immed 1,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - set_icc 0xc,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_limmed 0x3fff,0xffff,gr8 - test_gr_immed 0x00000001,gr9 - - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_icc 0x5,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_immed -1,gr8 - test_gr_immed -6,gr9 - - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_icc 0x6,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 1 0 1 0 icc0 - test_gr_immed -1,gr8 - test_gr_immed -6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_icc 0x7,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 1 0 1 1 icc0 - test_gr_immed -1,gr8 - test_gr_immed -2,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_icc 0x4,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 1 0 0 0 icc0 - test_gr_immed -1,gr8 - test_gr_immed -2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed -2,gr8 - set_icc 0x9,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 1 0 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_icc 0xa,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 1 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_icc 0x7,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0xbfff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x4,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 1 0 0 0 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0x5,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_icc 0x6,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x7,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0xc000,0x0000,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_gr_immed -2,gr8 - set_icc 0xc,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed -1,gr7 ; multiply by 1 - set_gr_immed -2,gr8 - set_icc 0xd,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_gr_immed -1,gr8 - set_icc 0xe,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_gr_immed -2,gr8 - set_icc 0xf,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 0 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_gr_immed -2,gr8 - set_icc 0xc,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_gr_immed -4,gr8 - set_icc 0xd,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_immed 1,gr8 - test_gr_immed 0x00000000,gr9 - - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_gr_limmed 0x8000,0x0001,gr8 - set_icc 0xe,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_limmed 0x3fff,0xffff,gr8 - test_gr_immed 0x00000001,gr9 - - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0xf,0 - smulcc gr7,gr8,gr8,icc0 - test_icc 0 0 1 1 icc0 - test_gr_limmed 0x4000,0x0000,gr8 - test_gr_immed 0x00000000,gr9 - - pass diff --git a/sim/testsuite/sim/frv/smuli.cgs b/sim/testsuite/sim/frv/smuli.cgs deleted file mode 100644 index 19a695cf56b..00000000000 --- a/sim/testsuite/sim/frv/smuli.cgs +++ /dev/null @@ -1,210 +0,0 @@ -# frv testcase for smuli $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global smuli -smuli: - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_icc 0x0,0 - smuli gr7,2,gr8 - test_icc 0 0 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_icc 0x1,0 - smuli gr7,2,gr8 - test_icc 0 0 0 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_icc 0x2,0 - smuli gr7,1,gr8 - test_icc 0 0 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_icc 0x3,0 - smuli gr7,2,gr8 - test_icc 0 0 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_icc 0x4,0 - smuli gr7,0,gr8 - test_icc 0 1 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_icc 0x5,0 - smuli gr7,2,gr8 - test_icc 0 1 0 1 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_icc 0x6,0 - smuli gr7,2,gr8 - test_icc 0 1 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_icc 0x7,0 - smuli gr7,4,gr8 - test_icc 0 1 1 1 icc0 - test_gr_immed 1,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_icc 0x8,0 - smuli gr7,0x7ff,gr8 - test_icc 1 0 0 0 icc0 - test_gr_immed 0x3ff,gr8 - test_gr_limmed 0x7fff,0xf801,gr9 - - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_icc 0x9,0 - smuli gr7,2,gr8 - test_icc 1 0 0 1 icc0 - test_gr_immed -1,gr8 - test_gr_immed -6,gr9 - - set_gr_immed 3,gr7 ; multiply small numbers - set_icc 0xa,0 - smuli gr7,-2,gr8 - test_icc 1 0 1 0 icc0 - test_gr_immed -1,gr8 - test_gr_immed -6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_icc 0xb,0 - smuli gr7,-2,gr8 - test_icc 1 0 1 1 icc0 - test_gr_immed -1,gr8 - test_gr_immed -2,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_icc 0xc,0 - smuli gr7,1,gr8 - test_icc 1 1 0 0 icc0 - test_gr_immed -1,gr8 - test_gr_immed -2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_icc 0xd,0 - smuli gr7,-2,gr8 - test_icc 1 1 0 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 0 - set_icc 0xe,0 - smuli gr7,0,gr8 - test_icc 1 1 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_icc 0xf,0 - smuli gr7,-2,gr8 - test_icc 1 1 1 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0xbfff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_icc 0x0,0 - smuli gr7,-2,gr8 - test_icc 0 0 0 0 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_icc 0x1,0 - smuli gr7,-2,gr8 - test_icc 0 0 0 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_icc 0x2,0 - smuli gr7,-4,gr8 - test_icc 0 0 1 0 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_icc 0x3,0 - smuli gr7,-2048,gr8 - test_icc 0 0 1 1 icc0 - test_gr_limmed 0xffff,0xfc00,gr8 - test_gr_limmed 0x0000,0x0800,gr9 - - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_icc 0x4,0 - smuli gr7,-2,gr8 - test_icc 0 1 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed -1,gr7 ; multiply by 1 - set_icc 0x5,0 - smuli gr7,-2,gr8 - test_icc 0 1 0 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_icc 0x6,0 - smuli gr7,-1,gr8 - test_icc 0 1 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_icc 0x7,0 - smuli gr7,-2,gr8 - test_icc 0 1 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_icc 0x8,0 - smuli gr7,-2,gr8 - test_icc 1 0 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_icc 0x9,0 - smuli gr7,-4,gr8 - test_icc 1 0 0 1 icc0 - test_gr_immed 1,gr8 - test_gr_immed 0x00000000,gr9 - - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_icc 0xa,0 - smuli gr7,-2048,gr8 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0x0000,0x03ff,gr8 - test_gr_limmed 0xffff,0xf800,gr9 - - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_icc 0xb,0 - smuli gr7,-2048,gr8 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0x0000,0x0400,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - pass diff --git a/sim/testsuite/sim/frv/smulicc.cgs b/sim/testsuite/sim/frv/smulicc.cgs deleted file mode 100644 index e9aa889c249..00000000000 --- a/sim/testsuite/sim/frv/smulicc.cgs +++ /dev/null @@ -1,210 +0,0 @@ -# frv testcase for smulicc $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global smulicc -smulicc: - ; Positive operands - set_gr_immed 3,gr7 ; multiply small numbers - set_icc 0x0,0 - smulicc gr7,2,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_icc 0x1,0 - smulicc gr7,2,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_icc 0x2,0 - smulicc gr7,1,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_icc 0x3,0 - smulicc gr7,2,gr8,icc0 - test_icc 0 1 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_icc 0x4,0 - smulicc gr7,0,gr8,icc0 - test_icc 0 1 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_icc 0x5,0 - smulicc gr7,2,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_icc 0x6,0 - smulicc gr7,2,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_icc 0x7,0 - smulicc gr7,4,gr8,icc0 - test_icc 0 0 1 1 icc0 - test_gr_immed 1,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_icc 0x8,0 - smulicc gr7,0x1ff,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 0xff,gr8 - test_gr_limmed 0x7fff,0xfe01,gr9 - - ; Mixed operands - set_gr_immed -3,gr7 ; multiply small numbers - set_icc 0x9,0 - smulicc gr7,2,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_immed -1,gr8 - test_gr_immed -6,gr9 - - set_gr_immed 3,gr7 ; multiply small numbers - set_icc 0xa,0 - smulicc gr7,-2,gr8,icc0 - test_icc 1 0 1 0 icc0 - test_gr_immed -1,gr8 - test_gr_immed -6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_icc 0xb,0 - smulicc gr7,-2,gr8,icc0 - test_icc 1 0 1 1 icc0 - test_gr_immed -1,gr8 - test_gr_immed -2,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_icc 0xc,0 - smulicc gr7,1,gr8,icc0 - test_icc 1 0 0 0 icc0 - test_gr_immed -1,gr8 - test_gr_immed -2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_icc 0xd,0 - smulicc gr7,-2,gr8,icc0 - test_icc 0 1 0 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed -2,gr7 ; multiply by 0 - set_icc 0xe,0 - smulicc gr7,0,gr8,icc0 - test_icc 0 1 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x2000,0x0001,gr7 ; 31 bit result - set_icc 0xf,0 - smulicc gr7,-2,gr8,icc0 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0xbfff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_icc 0x0,0 - smulicc gr7,-2,gr8,icc0 - test_icc 1 0 0 0 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x4000,0x0001,gr7 ; 32 bit result - set_icc 0x1,0 - smulicc gr7,-2,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result - set_icc 0x2,0 - smulicc gr7,-4,gr8,icc0 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result - set_icc 0x3,0 - smulicc gr7,-512,gr8,icc0 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0xffff,0xff00,gr8 - test_gr_limmed 0x0000,0x0200,gr9 - - ; Negative operands - set_gr_immed -3,gr7 ; multiply small numbers - set_icc 0x4,0 - smulicc gr7,-2,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed -1,gr7 ; multiply by 1 - set_icc 0x5,0 - smulicc gr7,-2,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed -2,gr7 ; multiply by 1 - set_icc 0x6,0 - smulicc gr7,-1,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_limmed 0xc000,0x0001,gr7 ; 31 bit result - set_icc 0x7,0 - smulicc gr7,-2,gr8,icc0 - test_icc 0 0 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 32 bit result - set_icc 0x8,0 - smulicc gr7,-2,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0xc000,0x0000,gr7 ; 33 bit result - set_icc 0x9,0 - smulicc gr7,-4,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_immed 1,gr8 - test_gr_immed 0x00000000,gr9 - - set_gr_limmed 0x8000,0x0001,gr7 ; almost max positive result - set_icc 0xa,0 - smulicc gr7,-512,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_limmed 0x0000,0x00ff,gr8 - test_gr_limmed 0xffff,0xfe00,gr9 - - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_icc 0xb,0 - smulicc gr7,-512,gr8,icc0 - test_icc 0 0 1 1 icc0 - test_gr_limmed 0x0000,0x0100,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - pass diff --git a/sim/testsuite/sim/frv/sra.cgs b/sim/testsuite/sim/frv/sra.cgs deleted file mode 100644 index 0f0c8644d03..00000000000 --- a/sim/testsuite/sim/frv/sra.cgs +++ /dev/null @@ -1,38 +0,0 @@ -# frv testcase for sra $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global sra -sra: - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - sra gr8,gr7,gr8 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - sra gr8,gr7,gr8 - test_icc 1 1 1 1 icc0 - test_gr_limmed 0xc000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - sra gr8,gr7,gr8 - test_icc 1 1 1 1 icc0 - test_gr_immed -1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - sra gr8,gr7,gr8 - test_icc 1 0 1 0 icc0 - test_gr_immed 0x00000000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/sracc.cgs b/sim/testsuite/sim/frv/sracc.cgs deleted file mode 100644 index 14f4a8bf49c..00000000000 --- a/sim/testsuite/sim/frv/sracc.cgs +++ /dev/null @@ -1,38 +0,0 @@ -# frv testcase for sracc $GRi,$GRj,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global sracc -sracc: - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - sracc gr8,gr7,gr8,icc0 - test_icc 1 0 0 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - sracc gr8,gr7,gr8,icc0 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0xc000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - sracc gr8,gr7,gr8,icc0 - test_icc 1 0 1 0 icc0 - test_gr_immed -1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - sracc gr8,gr7,gr8,icc0 - test_icc 0 1 1 1 icc0 - test_gr_immed 0x00000000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/srai.cgs b/sim/testsuite/sim/frv/srai.cgs deleted file mode 100644 index 02b9654f587..00000000000 --- a/sim/testsuite/sim/frv/srai.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# frv testcase for srai $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global srai -srai: - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - srai gr8,0x7e0,gr8 ; Shift by 0 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - srai gr8,-31,gr8 ; Shift by 1 - test_icc 1 1 1 1 icc0 - test_gr_limmed 0xc000,0x0000,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - srai gr8,31,gr8 ; Shift by 31 - test_icc 1 1 1 1 icc0 - test_gr_immed -1,gr8 - - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - srai gr8,31,gr8 ; clear register - test_icc 1 0 1 0 icc0 - test_gr_immed 0x00000000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/sraicc.cgs b/sim/testsuite/sim/frv/sraicc.cgs deleted file mode 100644 index 5dbd1e600c6..00000000000 --- a/sim/testsuite/sim/frv/sraicc.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# frv testcase for sraicc $GRi,$GRj,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global sraicc -sraicc: - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - sraicc gr8,0x1e0,gr8,icc0 ; Shift by 0 - test_icc 1 0 0 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - sraicc gr8,-31,gr8,icc0 ; Shift by 1 - test_icc 1 0 1 0 icc0 - test_gr_limmed 0xc000,0x0000,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - sraicc gr8,31,gr8,icc0 ; Shift by 31 - test_icc 1 0 1 0 icc0 - test_gr_immed -1,gr8 - - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - sraicc gr8,31,gr8,icc0 ; clear register - test_icc 0 1 1 1 icc0 - test_gr_immed 0x00000000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/srl.cgs b/sim/testsuite/sim/frv/srl.cgs deleted file mode 100644 index 045e75edba6..00000000000 --- a/sim/testsuite/sim/frv/srl.cgs +++ /dev/null @@ -1,38 +0,0 @@ -# frv testcase for srl $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global srl -srl: - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - srl gr8,gr7,gr8 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - srl gr8,gr7,gr8 - test_icc 1 1 1 1 icc0 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - srl gr8,gr7,gr8 - test_icc 1 1 1 1 icc0 - test_gr_immed 1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - srl gr8,gr7,gr8 - test_icc 1 0 1 0 icc0 - test_gr_immed 0x00000000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/srlcc.cgs b/sim/testsuite/sim/frv/srlcc.cgs deleted file mode 100644 index 1450a4b9ed9..00000000000 --- a/sim/testsuite/sim/frv/srlcc.cgs +++ /dev/null @@ -1,38 +0,0 @@ -# frv testcase for srlcc $GRi,$GRj,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global srlcc -srlcc: - set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - srlcc gr8,gr7,gr8,icc0 - test_icc 1 0 0 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - srlcc gr8,gr7,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - srlcc gr8,gr7,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_immed 1,gr8 - - set_gr_limmed 0xdead,0xbeff,gr7 ; clear register - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - srlcc gr8,gr7,gr8,icc0 - test_icc 0 1 1 1 icc0 - test_gr_immed 0x00000000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/srli.cgs b/sim/testsuite/sim/frv/srli.cgs deleted file mode 100644 index 72207d3a3e3..00000000000 --- a/sim/testsuite/sim/frv/srli.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# frv testcase for srli $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global srli -srli: - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - srli gr8,0x7e0,gr8 ; Shift by 0 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - srli gr8,-31,gr8 ; Shift by 1 - test_icc 1 1 1 1 icc0 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - srli gr8,31,gr8 ; Shift by 31 - test_icc 1 1 1 1 icc0 - test_gr_immed 1,gr8 - - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - srli gr8,31,gr8 ; clear register - test_icc 1 0 1 0 icc0 - test_gr_immed 0x00000000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/srlicc.cgs b/sim/testsuite/sim/frv/srlicc.cgs deleted file mode 100644 index d232802eb57..00000000000 --- a/sim/testsuite/sim/frv/srlicc.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# frv testcase for srlicc $GRi,$s10,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global srlicc -srlicc: - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - srlicc gr8,0x1e0,gr8,icc0 ; Shift by 0 - test_icc 1 0 0 0 icc0 - test_gr_limmed 0x8000,0x0000,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - srlicc gr8,-31,gr8,icc0 ; Shift by 1 - test_icc 0 0 1 0 icc0 - test_gr_limmed 0x4000,0x0000,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - srlicc gr8,31,gr8,icc0 ; Shift by 31 - test_icc 0 0 1 0 icc0 - test_gr_immed 1,gr8 - - set_gr_limmed 0x4000,0x0000,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - srlicc gr8,31,gr8,icc0 ; clear register - test_icc 0 1 1 1 icc0 - test_gr_immed 0x00000000,gr8 - - pass diff --git a/sim/testsuite/sim/frv/st.cgs b/sim/testsuite/sim/frv/st.cgs deleted file mode 100644 index 557713c0594..00000000000 --- a/sim/testsuite/sim/frv/st.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# frv testcase for st $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global add -add: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - st gr8,@(sp,gr7) - test_mem_limmed 0xffff,0xffff,sp - - pass diff --git a/sim/testsuite/sim/frv/stb.cgs b/sim/testsuite/sim/frv/stb.cgs deleted file mode 100644 index 15fa1e65398..00000000000 --- a/sim/testsuite/sim/frv/stb.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# frv testcase for stb $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global add -add: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - stb gr8,@(sp,gr7) - test_mem_limmed 0xffad,0xbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/stbf.cgs b/sim/testsuite/sim/frv/stbf.cgs deleted file mode 100644 index 741327d8a11..00000000000 --- a/sim/testsuite/sim/frv/stbf.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# frv testcase for stbf $FRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global stbf -stbf: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - stbf fr8,@(sp,gr7) - test_mem_limmed 0xffad,0xbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/stbfi.cgs b/sim/testsuite/sim/frv/stbfi.cgs deleted file mode 100644 index cfea70867f3..00000000000 --- a/sim/testsuite/sim/frv/stbfi.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# frv testcase for stbfi $FRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global stbfi -stbfi: - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_fr_iimmed 0xffff,0xffff,fr8 - stbfi fr8,@(sp,0) - test_mem_limmed 0xffad,0xbeef,sp - - inc_gr_immed 0x801,sp ; 2049 - stbfi fr8,@(sp,-2048) - test_mem_limmed 0xffff,0xbeef,gr20 - - inc_gr_immed -4094,sp - stbfi fr8,@(sp,0x7ff) - test_mem_limmed 0xffff,0xffef,gr20 - - pass diff --git a/sim/testsuite/sim/frv/stbfu.cgs b/sim/testsuite/sim/frv/stbfu.cgs deleted file mode 100644 index 01bbb99ca9e..00000000000 --- a/sim/testsuite/sim/frv/stbfu.cgs +++ /dev/null @@ -1,19 +0,0 @@ -# frv testcase for stbfu $FRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global stbfu -stbfu: - set_gr_gr sp,gr9 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - stbfu fr8,@(sp,gr7) - test_mem_limmed 0xffad,0xbeef,sp - test_gr_gr sp,gr9 - - pass diff --git a/sim/testsuite/sim/frv/stbi.cgs b/sim/testsuite/sim/frv/stbi.cgs deleted file mode 100644 index f23efc9155a..00000000000 --- a/sim/testsuite/sim/frv/stbi.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# frv testcase for stbi $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global stbi -stbi: - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_limmed 0xffff,0xffff,gr8 - stbi gr8,@(sp,0) - test_mem_limmed 0xffad,0xbeef,sp - - inc_gr_immed 0x801,sp ; 2049 - stbi gr8,@(sp,-2048) - test_mem_limmed 0xffff,0xbeef,gr20 - - inc_gr_immed -4094,sp - stbi gr8,@(sp,0x7ff) - test_mem_limmed 0xffff,0xffef,gr20 - - pass diff --git a/sim/testsuite/sim/frv/stbu.cgs b/sim/testsuite/sim/frv/stbu.cgs deleted file mode 100644 index e56ad1137d1..00000000000 --- a/sim/testsuite/sim/frv/stbu.cgs +++ /dev/null @@ -1,19 +0,0 @@ -# frv testcase for stbu $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global stbu -stbu: - set_gr_gr sp,gr9 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - stbu gr8,@(sp,gr7) - test_mem_limmed 0xffad,0xbeef,sp - test_gr_gr sp,gr9 - - pass diff --git a/sim/testsuite/sim/frv/stc.cgs b/sim/testsuite/sim/frv/stc.cgs deleted file mode 100644 index 581297cef9d..00000000000 --- a/sim/testsuite/sim/frv/stc.cgs +++ /dev/null @@ -1,17 +0,0 @@ -# frv testcase for stc $CPRk,@($GRi,$GRj) -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global stc -stc: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_cpr_limmed 0xffff,0xffff,cpr8 - stc cpr8,@(sp,gr7) - test_mem_limmed 0xffff,0xffff,sp - - pass diff --git a/sim/testsuite/sim/frv/stcu.cgs b/sim/testsuite/sim/frv/stcu.cgs deleted file mode 100644 index eb9e6c5efa1..00000000000 --- a/sim/testsuite/sim/frv/stcu.cgs +++ /dev/null @@ -1,33 +0,0 @@ -# frv testcase for stcu $CPRk,@($GRi,$GRj) -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global stcu -stcu: - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_cpr_limmed 0xffff,0xffff,cpr8 - stcu cpr8,@(sp,gr7) - test_mem_limmed 0xffff,0xffff,sp - test_gr_gr sp,gr20 - - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_cpr_limmed 0x1234,0x5678,cpr8 - stcu cpr8,@(sp,gr7) - test_mem_limmed 0x1234,0x5678,sp - test_gr_gr sp,gr20 - - inc_gr_immed 4,sp - set_gr_immed -4,gr7 - set_cpr_limmed 0x9abc,0xdef0,cpr8 - stcu cpr8,@(sp,gr7) - test_mem_limmed 0x9abc,0xdef0,sp - test_gr_gr sp,gr20 - - pass diff --git a/sim/testsuite/sim/frv/std.cgs b/sim/testsuite/sim/frv/std.cgs deleted file mode 100644 index 8a2ed12e99f..00000000000 --- a/sim/testsuite/sim/frv/std.cgs +++ /dev/null @@ -1,32 +0,0 @@ -# frv testcase for std $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global add -add: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - std gr8,@(sp,gr7) - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr3 ; sp is gr1 - set_gr_limmed 0xbeef,0xdead,gr0 - set_gr_limmed 0xdead,0xbeef,gr1 - std gr0,@(gr3,gr7) - test_mem_immed 0,gr3 - inc_gr_immed 4,gr3 - test_mem_immed 0,gr3 - - pass diff --git a/sim/testsuite/sim/frv/std.pcgs b/sim/testsuite/sim/frv/std.pcgs deleted file mode 100644 index d518b8b9746..00000000000 --- a/sim/testsuite/sim/frv/std.pcgs +++ /dev/null @@ -1,37 +0,0 @@ -# frv parallel testcase for std $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global add -add: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - std gr8,@(sp,gr7) ; non parallel - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 4,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - std.p gr8,@(sp,gr0) ; parallel - setlos 0,gr8 - ld @(sp,gr0),gr10 - ld @(sp,gr7),gr11 - test_mem_limmed 0xbeef,0xdead,sp ; memory is set - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - test_gr_immed 0xbeefdead,gr10 ; regs were pre-loaded - test_gr_immed 0xdeadbeef,gr11 ; not this one - - pass diff --git a/sim/testsuite/sim/frv/stdc.cgs b/sim/testsuite/sim/frv/stdc.cgs deleted file mode 100644 index bdff0ac81c9..00000000000 --- a/sim/testsuite/sim/frv/stdc.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# frv testcase for stdc $CPk,@($GRi,$GRj) -# mach: frv - - .include "testutils.inc" - - start - - .global stdc -stdc: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_cpr_limmed 0xbeef,0xdead,cpr8 - set_cpr_limmed 0xdead,0xbeef,cpr9 - stdc cpr8,@(sp,gr7) - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/stdc.pcgs b/sim/testsuite/sim/frv/stdc.pcgs deleted file mode 100644 index 46c49250566..00000000000 --- a/sim/testsuite/sim/frv/stdc.pcgs +++ /dev/null @@ -1,38 +0,0 @@ -# frv parallel testcase for stdc $CPk,@($GRi,$GRj) -# mach: frv - - .include "testutils.inc" - - start - - .global stdc -stdc: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_cpr_limmed 0xbeef,0xdead,cpr8 - set_cpr_limmed 0xdead,0xbeef,cpr9 - stdc cpr8,@(sp,gr7) ; non parallel - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 4,gr7 - set_cpr_limmed 0xbeef,0xdead,cpr8 - set_cpr_limmed 0xdead,0xbeef,cpr9 - stdc.p cpr8,@(sp,gr0) ; parallel - addi sp,4,sp - subi sp,4,sp - ldc @(sp,gr0),cpr10 - ldc @(sp,gr7),cpr11 - test_mem_limmed 0xbeef,0xdead,sp ; memory is set - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - test_cpr_limmed 0xbeef,0xdead,cpr10 - test_cpr_limmed 0xdead,0xbeef,cpr11 - - pass diff --git a/sim/testsuite/sim/frv/stdcu.cgs b/sim/testsuite/sim/frv/stdcu.cgs deleted file mode 100644 index bbae5fff096..00000000000 --- a/sim/testsuite/sim/frv/stdcu.cgs +++ /dev/null @@ -1,44 +0,0 @@ -# frv testcase for stdcu $CPk,@($GRi,$GRj) -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global stdcu -stdcu: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr20 - set_gr_immed 0,gr7 - set_cpr_limmed 0xbeef,0xdead,cpr8 - set_cpr_limmed 0xdead,0xbeef,cpr9 - stdcu cpr8,@(sp,gr7) - test_gr_gr sp,gr20 - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - - inc_gr_immed -12,sp - set_gr_immed 8,gr7 - set_cpr_limmed 0x1234,0x5678,cpr8 - set_cpr_limmed 0x9abc,0xdef0,cpr9 - stdcu cpr8,@(sp,gr7) - test_gr_gr sp,gr20 - test_mem_limmed 0x1234,0x5678,sp - inc_gr_immed 4,sp - test_mem_limmed 0x9abc,0xdef0,sp - - inc_gr_immed 4,sp - set_gr_immed -8,gr7 - set_cpr_limmed 0xfedc,0xba98,cpr8 - set_cpr_limmed 0x7654,0x3210,cpr9 - stdcu cpr8,@(sp,gr7) - test_gr_gr sp,gr20 - test_mem_limmed 0xfedc,0xba98,sp - inc_gr_immed 4,sp - test_mem_limmed 0x7654,0x3210,sp - - pass diff --git a/sim/testsuite/sim/frv/stdf.cgs b/sim/testsuite/sim/frv/stdf.cgs deleted file mode 100644 index 82c1461d97a..00000000000 --- a/sim/testsuite/sim/frv/stdf.cgs +++ /dev/null @@ -1,21 +0,0 @@ -# frv testcase for stdf $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global stdf -stdf: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - stdf fr8,@(sp,gr7) - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/stdf.pcgs b/sim/testsuite/sim/frv/stdf.pcgs deleted file mode 100644 index 7ef991c45f2..00000000000 --- a/sim/testsuite/sim/frv/stdf.pcgs +++ /dev/null @@ -1,37 +0,0 @@ -# frv parallel testcase for stdf $GRk,@($GRi,$GRj) -# mach: fr500 fr550 frv - - .include "testutils.inc" - - start - - .global stdf -stdf: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - stdf fr8,@(sp,gr7) ; non parallel - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 4,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - stdf.p fr8,@(sp,gr0) ; parallel - fnegs fr8,fr8 - ldf @(sp,gr0),fr10 - ldf @(sp,gr7),fr11 ; memory is set - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - test_fr_iimmed 0xbeefdead,fr10 ; regs were pre-loaded - test_fr_iimmed 0xdeadbeef,fr11 ; not this one - - pass diff --git a/sim/testsuite/sim/frv/stdfi.cgs b/sim/testsuite/sim/frv/stdfi.cgs deleted file mode 100644 index fea9b5171dd..00000000000 --- a/sim/testsuite/sim/frv/stdfi.cgs +++ /dev/null @@ -1,56 +0,0 @@ -# frv testcase for stdfi $FRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global stdfi -stdfi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr20 - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr21 - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - set_gr_gr sp,gr22 - inc_gr_immed -4,sp - set_mem_limmed 0x8765,0x4321,sp - set_gr_gr sp,gr23 - inc_gr_immed -4,sp - set_mem_limmed 0xfedc,0xba98,sp - set_gr_gr sp,gr24 - inc_gr_immed -4,sp - set_mem_limmed 0x89ab,0xcdef,sp - set_gr_gr sp,gr25 - set_fr_iimmed 0xffff,0xffff,fr8 - set_fr_iimmed 0xffff,0xffff,fr9 - - stdfi fr8,@(sp,0) - test_mem_limmed 0xffff,0xffff,gr25 - test_mem_limmed 0xffff,0xffff,gr24 - test_mem_limmed 0x8765,0x4321,gr23 - test_mem_limmed 0x1234,0x5678,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed 0x808,sp ; 2056 - stdfi fr8,@(sp,-2048) - test_mem_limmed 0xffff,0xffff,gr25 - test_mem_limmed 0xffff,0xffff,gr24 - test_mem_limmed 0xffff,0xffff,gr23 - test_mem_limmed 0xffff,0xffff,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed -4080,sp - stdfi fr8,@(sp,0x7f8) - test_mem_limmed 0xffff,0xffff,gr25 - test_mem_limmed 0xffff,0xffff,gr24 - test_mem_limmed 0xffff,0xffff,gr23 - test_mem_limmed 0xffff,0xffff,gr22 - test_mem_limmed 0xffff,0xffff,gr21 - test_mem_limmed 0xffff,0xffff,gr20 - - pass diff --git a/sim/testsuite/sim/frv/stdfu.cgs b/sim/testsuite/sim/frv/stdfu.cgs deleted file mode 100644 index 439cfa0a9b4..00000000000 --- a/sim/testsuite/sim/frv/stdfu.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# frv testcase for stdfu $FRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global stdfu -stdfu: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr20 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - stdfu fr8,@(sp,gr7) - test_gr_gr sp,gr20 - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/stdi.cgs b/sim/testsuite/sim/frv/stdi.cgs deleted file mode 100644 index e1a783d71aa..00000000000 --- a/sim/testsuite/sim/frv/stdi.cgs +++ /dev/null @@ -1,56 +0,0 @@ -# frv testcase for stdi $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global stdi -stdi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr20 - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr21 - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - set_gr_gr sp,gr22 - inc_gr_immed -4,sp - set_mem_limmed 0x8765,0x4321,sp - set_gr_gr sp,gr23 - inc_gr_immed -4,sp - set_mem_limmed 0xfedc,0xba98,sp - set_gr_gr sp,gr24 - inc_gr_immed -4,sp - set_mem_limmed 0x89ab,0xcdef,sp - set_gr_gr sp,gr25 - set_gr_limmed 0xffff,0xffff,gr8 - set_gr_limmed 0xffff,0xffff,gr9 - - stdi gr8,@(sp,0) - test_mem_limmed 0xffff,0xffff,gr25 - test_mem_limmed 0xffff,0xffff,gr24 - test_mem_limmed 0x8765,0x4321,gr23 - test_mem_limmed 0x1234,0x5678,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed 0x808,sp ; 2056 - stdi gr8,@(sp,-2048) - test_mem_limmed 0xffff,0xffff,gr25 - test_mem_limmed 0xffff,0xffff,gr24 - test_mem_limmed 0xffff,0xffff,gr23 - test_mem_limmed 0xffff,0xffff,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed -4080,sp - stdi gr8,@(sp,0x7f8) - test_mem_limmed 0xffff,0xffff,gr25 - test_mem_limmed 0xffff,0xffff,gr24 - test_mem_limmed 0xffff,0xffff,gr23 - test_mem_limmed 0xffff,0xffff,gr22 - test_mem_limmed 0xffff,0xffff,gr21 - test_mem_limmed 0xffff,0xffff,gr20 - - pass diff --git a/sim/testsuite/sim/frv/stdu.cgs b/sim/testsuite/sim/frv/stdu.cgs deleted file mode 100644 index b5f122f5ef7..00000000000 --- a/sim/testsuite/sim/frv/stdu.cgs +++ /dev/null @@ -1,24 +0,0 @@ -# frv testcase for stdu $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global stdu -stdu: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr20 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - stdu gr8,@(sp,gr7) - test_gr_gr sp,gr20 - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/stf.cgs b/sim/testsuite/sim/frv/stf.cgs deleted file mode 100644 index 5ebc060bef2..00000000000 --- a/sim/testsuite/sim/frv/stf.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# frv testcase for stf $FRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global stf -stf: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - stf fr8,@(sp,gr7) - test_mem_limmed 0xffff,0xffff,sp - - pass diff --git a/sim/testsuite/sim/frv/stfi.cgs b/sim/testsuite/sim/frv/stfi.cgs deleted file mode 100644 index cfce1fdfe57..00000000000 --- a/sim/testsuite/sim/frv/stfi.cgs +++ /dev/null @@ -1,37 +0,0 @@ -# frv testcase for stfi $FRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global stfi -stfi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr20 - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr21 - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - set_gr_gr sp,gr22 - set_fr_iimmed 0xffff,0xffff,fr8 - - stfi fr8,@(sp,0) - test_mem_limmed 0xffff,0xffff,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed 0x804,sp ; 2052 - stfi fr8,@(sp,-2048) - test_mem_limmed 0xffff,0xffff,gr22 - test_mem_limmed 0xffff,0xffff,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed -4088,sp - stfi fr8,@(sp,0x7fc) - test_mem_limmed 0xffff,0xffff,gr22 - test_mem_limmed 0xffff,0xffff,gr21 - test_mem_limmed 0xffff,0xffff,gr20 - - pass diff --git a/sim/testsuite/sim/frv/stfu.cgs b/sim/testsuite/sim/frv/stfu.cgs deleted file mode 100644 index e47e61dc56c..00000000000 --- a/sim/testsuite/sim/frv/stfu.cgs +++ /dev/null @@ -1,19 +0,0 @@ -# frv testcase for stfu $FRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global stfu -stfu: - set_gr_gr sp,gr9 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - stfu fr8,@(sp,gr7) - test_mem_limmed 0xffff,0xffff,sp - test_gr_gr sp,gr9 - - pass diff --git a/sim/testsuite/sim/frv/sth.cgs b/sim/testsuite/sim/frv/sth.cgs deleted file mode 100644 index c11ae407cd0..00000000000 --- a/sim/testsuite/sim/frv/sth.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# frv testcase for sth $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global add -add: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - sth gr8,@(sp,gr7) - test_mem_limmed 0xffff,0xbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/sthf.cgs b/sim/testsuite/sim/frv/sthf.cgs deleted file mode 100644 index 7310e4ee8c1..00000000000 --- a/sim/testsuite/sim/frv/sthf.cgs +++ /dev/null @@ -1,16 +0,0 @@ -# frv testcase for sthf $FRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global sthf -sthf: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - sthf fr8,@(sp,gr7) - test_mem_limmed 0xffff,0xbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/sthfi.cgs b/sim/testsuite/sim/frv/sthfi.cgs deleted file mode 100644 index ae9da976fd2..00000000000 --- a/sim/testsuite/sim/frv/sthfi.cgs +++ /dev/null @@ -1,31 +0,0 @@ -# frv testcase for sthfi $FRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global sthfi -sthfi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr20 - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr21 - set_fr_iimmed 0xffff,0xffff,fr8 - - sthfi fr8,@(sp,0) - test_mem_limmed 0xffff,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed 0x802,sp ; 2050 - sthfi fr8,@(sp,-2048) - test_mem_limmed 0xffff,0xffff,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed -4092,sp - sthfi fr8,@(sp,0x7fe) - test_mem_limmed 0xffff,0xffff,gr21 - test_mem_limmed 0xffff,0xbeef,gr20 - - pass diff --git a/sim/testsuite/sim/frv/sthfu.cgs b/sim/testsuite/sim/frv/sthfu.cgs deleted file mode 100644 index df472e73525..00000000000 --- a/sim/testsuite/sim/frv/sthfu.cgs +++ /dev/null @@ -1,19 +0,0 @@ -# frv testcase for sthfu $FRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global sthfu -sthfu: - set_gr_gr sp,gr9 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_fr_iimmed 0xffff,0xffff,fr8 - sthfu fr8,@(sp,gr7) - test_mem_limmed 0xffff,0xbeef,sp - test_gr_gr sp,gr9 - - pass diff --git a/sim/testsuite/sim/frv/sthi.cgs b/sim/testsuite/sim/frv/sthi.cgs deleted file mode 100644 index 93636e90956..00000000000 --- a/sim/testsuite/sim/frv/sthi.cgs +++ /dev/null @@ -1,31 +0,0 @@ -# frv testcase for sthi $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global sthi -sthi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr20 - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr21 - set_gr_limmed 0xffff,0xffff,gr8 - - sthi gr8,@(sp,0) - test_mem_limmed 0xffff,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed 0x802,sp ; 2050 - sthi gr8,@(sp,-2048) - test_mem_limmed 0xffff,0xffff,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed -4092,sp - sthi gr8,@(sp,0x7fe) - test_mem_limmed 0xffff,0xffff,gr21 - test_mem_limmed 0xffff,0xbeef,gr20 - - pass diff --git a/sim/testsuite/sim/frv/sthu.cgs b/sim/testsuite/sim/frv/sthu.cgs deleted file mode 100644 index ab35b30d396..00000000000 --- a/sim/testsuite/sim/frv/sthu.cgs +++ /dev/null @@ -1,19 +0,0 @@ -# frv testcase for sthu $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global sthu -sthu: - set_gr_gr sp,gr9 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - sthu gr8,@(sp,gr7) - test_mem_limmed 0xffff,0xbeef,sp - test_gr_gr sp,gr9 - - pass diff --git a/sim/testsuite/sim/frv/sti.cgs b/sim/testsuite/sim/frv/sti.cgs deleted file mode 100644 index ce05003d227..00000000000 --- a/sim/testsuite/sim/frv/sti.cgs +++ /dev/null @@ -1,37 +0,0 @@ -# frv testcase for sti $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global sti -sti: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr20 - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr21 - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - set_gr_gr sp,gr22 - set_gr_limmed 0xffff,0xffff,gr8 - - sti gr8,@(sp,0) - test_mem_limmed 0xffff,0xffff,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed 0x804,sp ; 2052 - sti gr8,@(sp,-2048) - test_mem_limmed 0xffff,0xffff,gr22 - test_mem_limmed 0xffff,0xffff,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - inc_gr_immed -4088,sp - sti gr8,@(sp,0x7fc) - test_mem_limmed 0xffff,0xffff,gr22 - test_mem_limmed 0xffff,0xffff,gr21 - test_mem_limmed 0xffff,0xffff,gr20 - - pass diff --git a/sim/testsuite/sim/frv/stq.cgs b/sim/testsuite/sim/frv/stq.cgs deleted file mode 100644 index 5ec836952f0..00000000000 --- a/sim/testsuite/sim/frv/stq.cgs +++ /dev/null @@ -1,53 +0,0 @@ -# frv testcase for stq $GRk,@($GRi,$GRj) -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global stq -stq: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - set_gr_limmed 0xdead,0xdead,gr10 - set_gr_limmed 0xbeef,0xbeef,gr11 - stq gr8,@(sp,gr7) - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xbeef,0xbeef,sp - - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_gr sp,gr4 ; sp is gr1 - set_gr_limmed 0xbeef,0xdead,gr0 - set_gr_limmed 0xdead,0xbeef,gr1 - set_gr_limmed 0xdead,0xdead,gr2 - set_gr_limmed 0xbeef,0xbeef,gr3 - stq gr0,@(gr4,gr7) - test_mem_immed 0,gr4 - inc_gr_immed 4,gr4 - test_mem_immed 0,gr4 - inc_gr_immed 4,gr4 - test_mem_immed 0,gr4 - inc_gr_immed 4,gr4 - test_mem_immed 0,gr4 - - pass diff --git a/sim/testsuite/sim/frv/stq.pcgs b/sim/testsuite/sim/frv/stq.pcgs deleted file mode 100644 index 268dd9eafbf..00000000000 --- a/sim/testsuite/sim/frv/stq.pcgs +++ /dev/null @@ -1,59 +0,0 @@ -# frv parallel testcase for stq $GRk,@($GRi,$GRj) -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global stq -stq: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - set_gr_limmed 0xdead,0xdead,gr10 - set_gr_limmed 0xbeef,0xbeef,gr11 - stq gr8,@(sp,gr7) ; non parallel - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xbeef,0xbeef,sp - - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_immed 0,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - set_gr_limmed 0xdead,0xdead,gr10 - set_gr_limmed 0xbeef,0xbeef,gr11 - stq.p gr8,@(sp,gr7) ; parallel - setlos 0,gr8 - ldq @(sp,gr7),gr12 - test_mem_limmed 0xbeef,0xdead,sp ; memory is set - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xbeef,0xbeef,sp - test_gr_immed 0xbeefdead,gr12 - test_gr_immed 0xdeadbeef,gr13 - test_gr_immed 0xdeaddead,gr14 - test_gr_immed 0xbeefbeef,gr15 - - pass diff --git a/sim/testsuite/sim/frv/stqc.cgs b/sim/testsuite/sim/frv/stqc.cgs deleted file mode 100644 index 19fc79d6e09..00000000000 --- a/sim/testsuite/sim/frv/stqc.cgs +++ /dev/null @@ -1,32 +0,0 @@ -# frv testcase for stqc $CPRk,@($GRi,$GRj) -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global stqc -stqc: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_immed 0,gr7 - set_cpr_limmed 0xbeef,0xdead,cpr8 - set_cpr_limmed 0xdead,0xbeef,cpr9 - set_cpr_limmed 0xdead,0xdead,cpr10 - set_cpr_limmed 0xbeef,0xbeef,cpr11 - stqc cpr8,@(sp,gr7) - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xbeef,0xbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/stqc.pcgs b/sim/testsuite/sim/frv/stqc.pcgs deleted file mode 100644 index bda68bac785..00000000000 --- a/sim/testsuite/sim/frv/stqc.pcgs +++ /dev/null @@ -1,60 +0,0 @@ -# frv parallel testcase for stqc $CPRk,@($GRi,$GRj) -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global stqc -stqc: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_immed 0,gr7 - set_cpr_limmed 0xbeef,0xdead,cpr8 - set_cpr_limmed 0xdead,0xbeef,cpr9 - set_cpr_limmed 0xdead,0xdead,cpr10 - set_cpr_limmed 0xbeef,0xbeef,cpr11 - stqc cpr8,@(sp,gr7) ; non parallel - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xbeef,0xbeef,sp - - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_immed 0,gr7 - set_cpr_limmed 0xbeef,0xdead,cpr8 - set_cpr_limmed 0xdead,0xbeef,cpr9 - set_cpr_limmed 0xdead,0xdead,cpr10 - set_cpr_limmed 0xbeef,0xbeef,cpr11 - stqc.p cpr8,@(sp,gr7) ; parallel - addi sp,4,sp - subi sp,4,sp - ldqc @(sp,gr7),cpr12 - test_mem_limmed 0xbeef,0xdead,sp ; memory is set - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xbeef,0xbeef,sp - test_cpr_limmed 0xbeef,0xdead,cpr12 - test_cpr_limmed 0xdead,0xbeef,cpr13 - test_cpr_limmed 0xdead,0xdead,cpr14 - test_cpr_limmed 0xbeef,0xbeef,cpr15 - - pass diff --git a/sim/testsuite/sim/frv/stqcu.cgs b/sim/testsuite/sim/frv/stqcu.cgs deleted file mode 100644 index a7746caa538..00000000000 --- a/sim/testsuite/sim/frv/stqcu.cgs +++ /dev/null @@ -1,66 +0,0 @@ -# frv testcase for stqcu $CPRk,@($GRi,$GRj) -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global stqcu -stqcu: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_gr sp,gr20 - set_gr_immed 0,gr7 - set_cpr_limmed 0xbeef,0xdead,cpr8 - set_cpr_limmed 0xdead,0xbeef,cpr9 - set_cpr_limmed 0xdead,0xdead,cpr10 - set_cpr_limmed 0xbeef,0xbeef,cpr11 - stqcu cpr8,@(sp,gr7) - test_gr_gr sp,gr20 - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xbeef,0xbeef,sp - - inc_gr_immed -28,sp - set_gr_immed 16,gr7 - set_cpr_limmed 0x1111,0x1111,cpr8 - set_cpr_limmed 0x2222,0x2222,cpr9 - set_cpr_limmed 0x3333,0x3333,cpr10 - set_cpr_limmed 0x4444,0x4444,cpr11 - stqcu cpr8,@(sp,gr7) - test_gr_gr sp,gr20 - test_mem_limmed 0x1111,0x1111,sp - inc_gr_immed 4,sp - test_mem_limmed 0x2222,0x2222,sp - inc_gr_immed 4,sp - test_mem_limmed 0x3333,0x3333,sp - inc_gr_immed 4,sp - test_mem_limmed 0x4444,0x4444,sp - - inc_gr_immed 4,sp - set_gr_immed -16,gr7 - set_cpr_limmed 0x5555,0x5555,cpr8 - set_cpr_limmed 0x6666,0x6666,cpr9 - set_cpr_limmed 0x7777,0x7777,cpr10 - set_cpr_limmed 0x8888,0x8888,cpr11 - stqcu cpr8,@(sp,gr7) - test_gr_gr sp,gr20 - test_mem_limmed 0x5555,0x5555,sp - inc_gr_immed 4,sp - test_mem_limmed 0x6666,0x6666,sp - inc_gr_immed 4,sp - test_mem_limmed 0x7777,0x7777,sp - inc_gr_immed 4,sp - test_mem_limmed 0x8888,0x8888,sp - - pass diff --git a/sim/testsuite/sim/frv/stqf.cgs b/sim/testsuite/sim/frv/stqf.cgs deleted file mode 100644 index 24dbb42ff35..00000000000 --- a/sim/testsuite/sim/frv/stqf.cgs +++ /dev/null @@ -1,32 +0,0 @@ -# frv testcase for stqf $GRk,@($GRi,$GRj) -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global stqf -stqf: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - set_fr_iimmed 0xdead,0xdead,fr10 - set_fr_iimmed 0xbeef,0xbeef,fr11 - stqf fr8,@(sp,gr7) - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xbeef,0xbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/stqf.pcgs b/sim/testsuite/sim/frv/stqf.pcgs deleted file mode 100644 index 497f5fb8096..00000000000 --- a/sim/testsuite/sim/frv/stqf.pcgs +++ /dev/null @@ -1,59 +0,0 @@ -# frv parallel testcase for stqf $GRk,@($GRi,$GRj) -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global stqf -stqf: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - set_fr_iimmed 0xdead,0xdead,fr10 - set_fr_iimmed 0xbeef,0xbeef,fr11 - stqf fr8,@(sp,gr7) ; non-parallel - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xbeef,0xbeef,sp - - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_immed 0,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - set_fr_iimmed 0xdead,0xdead,fr10 - set_fr_iimmed 0xbeef,0xbeef,fr11 - stqf.p fr8,@(sp,gr7) ; parallel - fnegs fr8,fr8 - ldqf @(sp,gr7),fr12 - test_mem_limmed 0xbeef,0xdead,sp ; memory is set - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xbeef,0xbeef,sp - test_fr_iimmed 0xbeefdead,fr12 - test_fr_iimmed 0xdeadbeef,fr13 - test_fr_iimmed 0xdeaddead,fr14 - test_fr_iimmed 0xbeefbeef,fr15 - - pass diff --git a/sim/testsuite/sim/frv/stqfi.cgs b/sim/testsuite/sim/frv/stqfi.cgs deleted file mode 100644 index 6a36a903fb8..00000000000 --- a/sim/testsuite/sim/frv/stqfi.cgs +++ /dev/null @@ -1,95 +0,0 @@ -# frv testcase for stqfi $FRk,@($GRi,$GRj) -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global stqfi -stqfi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr10 - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr11 - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - set_gr_gr sp,gr12 - inc_gr_immed -4,sp - set_mem_limmed 0x8765,0x4321,sp - set_gr_gr sp,gr13 - inc_gr_immed -4,sp - set_mem_limmed 0xfedc,0xba98,sp - set_gr_gr sp,gr14 - inc_gr_immed -4,sp - set_mem_limmed 0x89ab,0xcdef,sp - set_gr_gr sp,gr15 - inc_gr_immed -4,sp - set_mem_limmed 0x2345,0x6789,sp - set_gr_gr sp,gr16 - inc_gr_immed -4,sp - set_mem_limmed 0x9876,0x5432,sp - set_gr_gr sp,gr17 - inc_gr_immed -4,sp - set_mem_limmed 0x3456,0x789a,sp - set_gr_gr sp,gr18 - inc_gr_immed -4,sp - set_mem_limmed 0xa987,0x6543,sp - set_gr_gr sp,gr19 - inc_gr_immed -4,sp - set_mem_limmed 0x4567,0x89ab,sp - set_gr_gr sp,gr20 - inc_gr_immed -4,sp - set_mem_limmed 0xba98,0x7654,sp - set_gr_gr sp,gr21 - set_fr_iimmed 0xffff,0xffff,fr8 - set_fr_iimmed 0xeeee,0xeeee,fr9 - set_fr_iimmed 0xdddd,0xdddd,fr10 - set_fr_iimmed 0xcccc,0xcccc,fr11 - - stqfi fr8,@(sp,0) - test_mem_limmed 0xffff,0xffff,gr21 - test_mem_limmed 0xeeee,0xeeee,gr20 - test_mem_limmed 0xdddd,0xdddd,gr19 - test_mem_limmed 0xcccc,0xcccc,gr18 - test_mem_limmed 0x9876,0x5432,gr17 - test_mem_limmed 0x2345,0x6789,gr16 - test_mem_limmed 0x89ab,0xcdef,gr15 - test_mem_limmed 0xfedc,0xba98,gr14 - test_mem_limmed 0x8765,0x4321,gr13 - test_mem_limmed 0x1234,0x5678,gr12 - test_mem_limmed 0xbeef,0xdead,gr11 - test_mem_limmed 0xdead,0xbeef,gr10 - - inc_gr_immed 0x810,sp ; 2064 - stqfi fr8,@(sp,-2048) - test_mem_limmed 0xffff,0xffff,gr21 - test_mem_limmed 0xeeee,0xeeee,gr20 - test_mem_limmed 0xdddd,0xdddd,gr19 - test_mem_limmed 0xcccc,0xcccc,gr18 - test_mem_limmed 0xffff,0xffff,gr17 - test_mem_limmed 0xeeee,0xeeee,gr16 - test_mem_limmed 0xdddd,0xdddd,gr15 - test_mem_limmed 0xcccc,0xcccc,gr14 - test_mem_limmed 0x8765,0x4321,gr13 - test_mem_limmed 0x1234,0x5678,gr12 - test_mem_limmed 0xbeef,0xdead,gr11 - test_mem_limmed 0xdead,0xbeef,gr10 - - inc_gr_immed -4064,sp - stqfi fr8,@(sp,0x7f0) - test_mem_limmed 0xffff,0xffff,gr21 - test_mem_limmed 0xeeee,0xeeee,gr20 - test_mem_limmed 0xdddd,0xdddd,gr19 - test_mem_limmed 0xcccc,0xcccc,gr18 - test_mem_limmed 0xffff,0xffff,gr17 - test_mem_limmed 0xeeee,0xeeee,gr16 - test_mem_limmed 0xdddd,0xdddd,gr15 - test_mem_limmed 0xcccc,0xcccc,gr14 - test_mem_limmed 0xffff,0xffff,gr13 - test_mem_limmed 0xeeee,0xeeee,gr12 - test_mem_limmed 0xdddd,0xdddd,gr11 - test_mem_limmed 0xcccc,0xcccc,gr10 - - pass diff --git a/sim/testsuite/sim/frv/stqfu.cgs b/sim/testsuite/sim/frv/stqfu.cgs deleted file mode 100644 index 80a1494d973..00000000000 --- a/sim/testsuite/sim/frv/stqfu.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# frv testcase for stqfu $FRk,@($GRi,$GRj) -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global stqfu -stqfu: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_gr sp,gr20 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_fr_iimmed 0xbeef,0xdead,fr8 - set_fr_iimmed 0xdead,0xbeef,fr9 - set_fr_iimmed 0xdead,0xdead,fr10 - set_fr_iimmed 0xbeef,0xbeef,fr11 - stqfu fr8,@(sp,gr7) - test_gr_gr sp,gr20 - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xbeef,0xbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/stqi.cgs b/sim/testsuite/sim/frv/stqi.cgs deleted file mode 100644 index 5a3680ef1c3..00000000000 --- a/sim/testsuite/sim/frv/stqi.cgs +++ /dev/null @@ -1,95 +0,0 @@ -# frv testcase for stqi $GRk,@($GRi,$GRj) -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global stqi -stqi: - set_mem_limmed 0xdead,0xbeef,sp - set_gr_gr sp,gr10 - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xdead,sp - set_gr_gr sp,gr11 - inc_gr_immed -4,sp - set_mem_limmed 0x1234,0x5678,sp - set_gr_gr sp,gr12 - inc_gr_immed -4,sp - set_mem_limmed 0x8765,0x4321,sp - set_gr_gr sp,gr13 - inc_gr_immed -4,sp - set_mem_limmed 0xfedc,0xba98,sp - set_gr_gr sp,gr14 - inc_gr_immed -4,sp - set_mem_limmed 0x89ab,0xcdef,sp - set_gr_gr sp,gr15 - inc_gr_immed -4,sp - set_mem_limmed 0x2345,0x6789,sp - set_gr_gr sp,gr16 - inc_gr_immed -4,sp - set_mem_limmed 0x9876,0x5432,sp - set_gr_gr sp,gr17 - inc_gr_immed -4,sp - set_mem_limmed 0x3456,0x789a,sp - set_gr_gr sp,gr18 - inc_gr_immed -4,sp - set_mem_limmed 0xa987,0x6543,sp - set_gr_gr sp,gr19 - inc_gr_immed -4,sp - set_mem_limmed 0x4567,0x89ab,sp - set_gr_gr sp,gr20 - inc_gr_immed -4,sp - set_mem_limmed 0xba98,0x7654,sp - set_gr_gr sp,gr21 - set_gr_limmed 0xffff,0xffff,gr4 - set_gr_limmed 0xeeee,0xeeee,gr5 - set_gr_limmed 0xdddd,0xdddd,gr6 - set_gr_limmed 0xcccc,0xcccc,gr7 - - stqi gr4,@(sp,0) - test_mem_limmed 0xffff,0xffff,gr21 - test_mem_limmed 0xeeee,0xeeee,gr20 - test_mem_limmed 0xdddd,0xdddd,gr19 - test_mem_limmed 0xcccc,0xcccc,gr18 - test_mem_limmed 0x9876,0x5432,gr17 - test_mem_limmed 0x2345,0x6789,gr16 - test_mem_limmed 0x89ab,0xcdef,gr15 - test_mem_limmed 0xfedc,0xba98,gr14 - test_mem_limmed 0x8765,0x4321,gr13 - test_mem_limmed 0x1234,0x5678,gr12 - test_mem_limmed 0xbeef,0xdead,gr11 - test_mem_limmed 0xdead,0xbeef,gr10 - - inc_gr_immed 0x810,sp ; 2064 - stqi gr4,@(sp,-2048) - test_mem_limmed 0xffff,0xffff,gr21 - test_mem_limmed 0xeeee,0xeeee,gr20 - test_mem_limmed 0xdddd,0xdddd,gr19 - test_mem_limmed 0xcccc,0xcccc,gr18 - test_mem_limmed 0xffff,0xffff,gr17 - test_mem_limmed 0xeeee,0xeeee,gr16 - test_mem_limmed 0xdddd,0xdddd,gr15 - test_mem_limmed 0xcccc,0xcccc,gr14 - test_mem_limmed 0x8765,0x4321,gr13 - test_mem_limmed 0x1234,0x5678,gr12 - test_mem_limmed 0xbeef,0xdead,gr11 - test_mem_limmed 0xdead,0xbeef,gr10 - - inc_gr_immed -4064,sp - stqi gr4,@(sp,0x7f0) - test_mem_limmed 0xffff,0xffff,gr21 - test_mem_limmed 0xeeee,0xeeee,gr20 - test_mem_limmed 0xdddd,0xdddd,gr19 - test_mem_limmed 0xcccc,0xcccc,gr18 - test_mem_limmed 0xffff,0xffff,gr17 - test_mem_limmed 0xeeee,0xeeee,gr16 - test_mem_limmed 0xdddd,0xdddd,gr15 - test_mem_limmed 0xcccc,0xcccc,gr14 - test_mem_limmed 0xffff,0xffff,gr13 - test_mem_limmed 0xeeee,0xeeee,gr12 - test_mem_limmed 0xdddd,0xdddd,gr11 - test_mem_limmed 0xcccc,0xcccc,gr10 - - pass diff --git a/sim/testsuite/sim/frv/stqu.cgs b/sim/testsuite/sim/frv/stqu.cgs deleted file mode 100644 index 31e8de51a6a..00000000000 --- a/sim/testsuite/sim/frv/stqu.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# frv testcase for stqu $GRk,@($GRi,$GRj) -# mach: frv -# as(frv): -mcpu=frv - - .include "testutils.inc" - - start - - .global stqu -stqu: - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_mem_limmed 0xdead,0xdead,sp - inc_gr_immed -4,sp - set_mem_limmed 0xbeef,0xbeef,sp - set_gr_gr sp,gr20 - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_limmed 0xdead,0xbeef,gr9 - set_gr_limmed 0xdead,0xdead,gr10 - set_gr_limmed 0xbeef,0xbeef,gr11 - stqu gr8,@(sp,gr7) - test_gr_gr sp,gr20 - test_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - test_mem_limmed 0xdead,0xdead,sp - inc_gr_immed 4,sp - test_mem_limmed 0xbeef,0xbeef,sp - - pass diff --git a/sim/testsuite/sim/frv/stu.cgs b/sim/testsuite/sim/frv/stu.cgs deleted file mode 100644 index cc480405426..00000000000 --- a/sim/testsuite/sim/frv/stu.cgs +++ /dev/null @@ -1,19 +0,0 @@ -# frv testcase for stu $GRk,@($GRi,$GRj) -# mach: all - - .include "testutils.inc" - - start - - .global stu -stu: - set_gr_gr sp,gr9 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_gr_immed 4,gr7 - set_gr_limmed 0xffff,0xffff,gr8 - stu gr8,@(sp,gr7) - test_mem_limmed 0xffff,0xffff,sp - test_gr_gr sp,gr9 - - pass diff --git a/sim/testsuite/sim/frv/sub.cgs b/sim/testsuite/sim/frv/sub.cgs deleted file mode 100644 index 5a1410ca6f2..00000000000 --- a/sim/testsuite/sim/frv/sub.cgs +++ /dev/null @@ -1,26 +0,0 @@ -# frv testcase for sub $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global sub -sub: - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - sub gr8,gr7,gr8 - test_gr_immed 1,gr8 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - sub gr8,gr7,gr8 - test_gr_limmed 0x7fff,0xffff,gr8 - - sub gr8,gr8,gr8 - test_gr_immed 0,gr8 - - sub gr8,gr7,gr8 - test_gr_immed -1,gr8 - - pass diff --git a/sim/testsuite/sim/frv/subcc.cgs b/sim/testsuite/sim/frv/subcc.cgs deleted file mode 100644 index 188e0ff8a99..00000000000 --- a/sim/testsuite/sim/frv/subcc.cgs +++ /dev/null @@ -1,34 +0,0 @@ -# frv testcase for subcc $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global subcc -subcc: - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - subcc gr8,gr7,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 1,gr8 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - subcc gr8,gr7,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_icc 0x0b,0 ; Set mask opposite of expected - subcc gr8,gr8,gr8,icc0 - test_icc 0 1 0 0 icc0 - test_gr_immed 0,gr8 - - set_icc 0x06,0 ; Set mask opposite of expected - subcc gr8,gr7,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - pass diff --git a/sim/testsuite/sim/frv/subi.cgs b/sim/testsuite/sim/frv/subi.cgs deleted file mode 100644 index c6328389f58..00000000000 --- a/sim/testsuite/sim/frv/subi.cgs +++ /dev/null @@ -1,56 +0,0 @@ -# frv testcase for subi $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global subi -subi: - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - subi gr8,1,gr8 - test_icc 1 1 1 1 icc0 - test_gr_immed 1,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - subi gr8,1,gr8 - test_icc 1 1 0 1 icc0 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_immed 0x7ff,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - subi gr8,0x7ff,gr8 - test_icc 1 0 1 1 icc0 - test_gr_immed 0,gr8 - - set_icc 0x06,0 ; Set mask opposite of expected - subi gr8,1,gr8 - test_icc 0 1 1 0 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 2,gr8 - set_icc 0x0e,0 ; Set mask opposite of expected - subi gr8,-1,gr8 - test_icc 1 1 1 0 icc0 - test_gr_immed 3,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x06,0 ; Set mask opposite of expected - subi gr8,-1,gr8 - test_icc 0 1 1 0 icc0 - test_gr_limmed 0x8000,0x0001,gr8 - - set_gr_immed -2048,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - subi gr8,-2048,gr8 - test_icc 1 0 1 1 icc0 - test_gr_immed 0,gr8 - - set_icc 0x0e,0 ; Set mask opposite of expected - subi gr8,-1,gr8 - test_icc 1 1 1 0 icc0 - test_gr_immed 1,gr8 - - pass diff --git a/sim/testsuite/sim/frv/subicc.cgs b/sim/testsuite/sim/frv/subicc.cgs deleted file mode 100644 index b2296ee02c8..00000000000 --- a/sim/testsuite/sim/frv/subicc.cgs +++ /dev/null @@ -1,56 +0,0 @@ -# frv testcase for subicc $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global subicc -subicc: - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - subicc gr8,1,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 1,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - subicc gr8,1,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_immed 0x1ff,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - subicc gr8,0x1ff,gr8,icc0 - test_icc 0 1 0 0 icc0 - test_gr_immed 0,gr8 - - set_icc 0x06,0 ; Set mask opposite of expected - subicc gr8,1,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 2,gr8 - set_icc 0x0e,0 ; Set mask opposite of expected - subicc gr8,-1,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_immed 3,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x06,0 ; Set mask opposite of expected - subicc gr8,-1,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0x8000,0x0001,gr8 - - set_gr_immed -512,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - subicc gr8,-512,gr8,icc0 - test_icc 0 1 0 0 icc0 - test_gr_immed 0,gr8 - - set_icc 0x0e,0 ; Set mask opposite of expected - subicc gr8,-1,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_immed 1,gr8 - - pass diff --git a/sim/testsuite/sim/frv/subx.cgs b/sim/testsuite/sim/frv/subx.cgs deleted file mode 100644 index 4559a52cdd7..00000000000 --- a/sim/testsuite/sim/frv/subx.cgs +++ /dev/null @@ -1,60 +0,0 @@ -# frv testcase for subx $GRi,$GRj,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global subx -subx: - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0e,0 ; Make sure carry is off - subx gr8,gr7,gr8,icc0 - test_icc 1 1 1 0 icc0 - test_gr_immed 1,gr8 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0c,0 ; Make sure carry is off - subx gr8,gr7,gr8,icc0 - test_icc 1 1 0 0 icc0 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_icc 0x0a,0 ; Make sure carry is off - subx gr8,gr8,gr8,icc0 - test_icc 1 0 1 0 icc0 - test_gr_immed 0,gr8 - - set_icc 0x06,0 ; Make sure carry is off - subx gr8,gr7,gr8,icc0 - test_icc 0 1 1 0 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 3,gr8 - set_icc 0x0f,0 ; Make sure carry is on - subx gr8,gr7,gr8,icc0 - test_icc 1 1 1 1 icc0 - test_gr_immed 1,gr8 - - set_gr_immed 0,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,0 ; Make sure carry is on - subx gr8,gr7,gr8,icc0 - test_icc 1 1 0 1 icc0 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_limmed 0x7fff,0xfffe,gr7 - set_icc 0x0b,0 ; Make sure carry is on - subx gr8,gr7,gr8,icc0 - test_icc 1 0 1 1 icc0 - test_gr_immed 0,gr8 - - set_gr_immed 0,gr7 - set_icc 0x07,0 ; Make sure carry is on - subx gr8,gr7,gr8,icc0 - test_icc 0 1 1 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - pass diff --git a/sim/testsuite/sim/frv/subxcc.cgs b/sim/testsuite/sim/frv/subxcc.cgs deleted file mode 100644 index 713a2a71be0..00000000000 --- a/sim/testsuite/sim/frv/subxcc.cgs +++ /dev/null @@ -1,60 +0,0 @@ -# frv testcase for subxcc $GRi,$GRj,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global subxcc -subxcc: - set_gr_immed 1,gr7 - set_gr_immed 2,gr8 - set_icc 0x0e,0 ; Make sure carry is off - subxcc gr8,gr7,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 1,gr8 - - set_gr_immed 1,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0c,0 ; Make sure carry is off - subxcc gr8,gr7,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_icc 0x0a,0 ; Make sure carry is off - subxcc gr8,gr8,gr8,icc0 - test_icc 0 1 0 0 icc0 - test_gr_immed 0,gr8 - - set_icc 0x06,0 ; Make sure carry is off - subxcc gr8,gr7,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 1,gr7 - set_gr_immed 3,gr8 - set_icc 0x0f,0 ; Make sure carry is on - subxcc gr8,gr7,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 1,gr8 - - set_gr_immed 0,gr7 - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,0 ; Make sure carry is on - subxcc gr8,gr7,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_limmed 0x7fff,0xfffe,gr7 - set_icc 0x0b,0 ; Make sure carry is on - subxcc gr8,gr7,gr8,icc0 - test_icc 0 1 0 0 icc0 - test_gr_immed 0,gr8 - - set_gr_immed 0,gr7 - set_icc 0x07,0 ; Make sure carry is on - subxcc gr8,gr7,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - pass diff --git a/sim/testsuite/sim/frv/subxi.cgs b/sim/testsuite/sim/frv/subxi.cgs deleted file mode 100644 index bbe8e4ddfdf..00000000000 --- a/sim/testsuite/sim/frv/subxi.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for subxi $GRi,$GRj,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global subxi -subxi: - set_gr_immed 2,gr8 - set_icc 0x0e,0 ; Make sure carry is off - subxi gr8,1,gr8,icc0 - test_icc 1 1 1 0 icc0 - test_gr_immed 1,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0c,0 ; Make sure carry is off - subxi gr8,1,gr8,icc0 - test_icc 1 1 0 0 icc0 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_immed 0x1ff,gr8 - set_icc 0x0a,0 ; Make sure carry is off - subxi gr8,0x1ff,gr8,icc0 - test_icc 1 0 1 0 icc0 - test_gr_immed 0,gr8 - - set_icc 0x06,0 ; Make sure carry is off - subxi gr8,1,gr8,icc0 - test_icc 0 1 1 0 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 3,gr8 - set_icc 0x0f,0 ; Make sure carry is on - subxi gr8,1,gr8,icc0 - test_icc 1 1 1 1 icc0 - test_gr_immed 1,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,0 ; Make sure carry is on - subxi gr8,0,gr8,icc0 - test_icc 1 1 0 1 icc0 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_immed 0x200,gr8 - set_icc 0x0b,0 ; Make sure carry is on - subxi gr8,0x1ff,gr8,icc0 - test_icc 1 0 1 1 icc0 - test_gr_immed 0,gr8 - - set_icc 0x07,0 ; Make sure carry is on - subxi gr8,0,gr8,icc0 - test_icc 0 1 1 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_icc 0x07,0 ; Make sure carry is on - subxi gr8,-512,gr8,icc0 - test_icc 0 1 1 1 icc0 - test_gr_immed 510,gr8 - - pass diff --git a/sim/testsuite/sim/frv/subxicc.cgs b/sim/testsuite/sim/frv/subxicc.cgs deleted file mode 100644 index 369cab9dce0..00000000000 --- a/sim/testsuite/sim/frv/subxicc.cgs +++ /dev/null @@ -1,61 +0,0 @@ -# frv testcase for subxicc $GRi,$GRj,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global subxicc -subxicc: - set_gr_immed 2,gr8 - set_icc 0x0e,0 ; Make sure carry is off - subxicc gr8,1,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 1,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0c,0 ; Make sure carry is off - subxicc gr8,1,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_immed 0x1ff,gr8 - set_icc 0x0a,0 ; Make sure carry is off - subxicc gr8,0x1ff,gr8,icc0 - test_icc 0 1 0 0 icc0 - test_gr_immed 0,gr8 - - set_icc 0x06,0 ; Make sure carry is off - subxicc gr8,1,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 3,gr8 - set_icc 0x0f,0 ; Make sure carry is on - subxicc gr8,1,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 1,gr8 - - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,0 ; Make sure carry is on - subxicc gr8,0,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_limmed 0x7fff,0xffff,gr8 - - set_gr_immed 0x200,gr8 - set_icc 0x0b,0 ; Make sure carry is on - subxicc gr8,0x1ff,gr8,icc0 - test_icc 0 1 0 0 icc0 - test_gr_immed 0,gr8 - - set_icc 0x07,0 ; Make sure carry is on - subxicc gr8,0,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_icc 0x07,0 ; Make sure carry is on - subxicc gr8,-512,gr8,icc0 - test_icc 0 0 0 0 icc0 - test_gr_immed 510,gr8 - - pass diff --git a/sim/testsuite/sim/frv/swap.cgs b/sim/testsuite/sim/frv/swap.cgs deleted file mode 100644 index 1e229032868..00000000000 --- a/sim/testsuite/sim/frv/swap.cgs +++ /dev/null @@ -1,42 +0,0 @@ -# frv testcase for swap @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global swap -swap: - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_gr_gr sp,gr21 - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_gr_gr sp,gr22 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - - set_gr_limmed 0xbeef,0xdead,gr8 - set_gr_immed -4,gr7 - swap @(sp,gr7),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_mem_limmed 0xbeef,0xdead,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 0,gr7 - swap @(sp,gr7),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_mem_limmed 0xbeef,0xdead,gr22 - test_mem_limmed 0xdead,0xbeef,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - set_gr_immed 4,gr7 - swap @(sp,gr7),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_mem_limmed 0xbeef,0xdead,gr22 - test_mem_limmed 0xdead,0xbeef,gr21 - test_mem_limmed 0xbeef,0xdead,gr20 - - pass diff --git a/sim/testsuite/sim/frv/swapi.cgs b/sim/testsuite/sim/frv/swapi.cgs deleted file mode 100644 index 4951bfa7cfd..00000000000 --- a/sim/testsuite/sim/frv/swapi.cgs +++ /dev/null @@ -1,39 +0,0 @@ -# frv testcase for swapi @($GRi,$GRj),$GRk -# mach: all - - .include "testutils.inc" - - start - - .global swapi -swapi: - set_gr_gr sp,gr20 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed -4,sp - set_gr_gr sp,gr21 - set_mem_limmed 0xbeef,0xdead,sp - inc_gr_immed -4,sp - set_gr_gr sp,gr22 - set_mem_limmed 0xdead,0xbeef,sp - inc_gr_immed 4,sp - - set_gr_limmed 0xbeef,0xdead,gr8 - swapi @(sp,-4),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_mem_limmed 0xbeef,0xdead,gr22 - test_mem_limmed 0xbeef,0xdead,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - swapi @(sp,0),gr8 - test_gr_limmed 0xbeef,0xdead,gr8 - test_mem_limmed 0xbeef,0xdead,gr22 - test_mem_limmed 0xdead,0xbeef,gr21 - test_mem_limmed 0xdead,0xbeef,gr20 - - swapi @(sp,4),gr8 - test_gr_limmed 0xdead,0xbeef,gr8 - test_mem_limmed 0xbeef,0xdead,gr22 - test_mem_limmed 0xdead,0xbeef,gr21 - test_mem_limmed 0xbeef,0xdead,gr20 - - pass diff --git a/sim/testsuite/sim/frv/tc.cgs b/sim/testsuite/sim/frv/tc.cgs deleted file mode 100644 index 116190b0f59..00000000000 --- a/sim/testsuite/sim/frv/tc.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for tc $ICCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global tc -tc: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_icc 0x0 0 - tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x1 0 - tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_icc 0x2 0 - tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok3,lr - set_icc 0x3 0 - tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_icc 0x4 0 - tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok5,lr - set_icc 0x5 0 - tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_spr_addr bad,lr - set_icc 0x6 0 - tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok7,lr - set_icc 0x7 0 - tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_icc 0x8 0 - tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok9,lr - set_icc 0x9 0 - tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_spr_addr bad,lr - set_icc 0xa 0 - tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okb,lr - set_icc 0xb 0 - tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_spr_addr bad,lr - set_icc 0xc 0 - tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okd,lr - set_icc 0xd 0 - tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_spr_addr bad,lr - set_icc 0xe 0 - tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okf,lr - set_icc 0xf 0 - tc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/teq.cgs b/sim/testsuite/sim/frv/teq.cgs deleted file mode 100644 index 59c60914a7c..00000000000 --- a/sim/testsuite/sim/frv/teq.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for teq $ICCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global teq -teq: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_icc 0x0 0 - teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x1 0 - teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x2 0 - teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x3 0 - teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok4,lr - set_icc 0x4 0 - teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_icc 0x5 0 - teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_icc 0x6 0 - teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_icc 0x7 0 - teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_icc 0x8 0 - teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x9 0 - teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xa 0 - teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xb 0 - teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okc,lr - set_icc 0xc 0 - teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_icc 0xd 0 - teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_icc 0xe 0 - teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_icc 0xf 0 - teq icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/testutils.inc b/sim/testsuite/sim/frv/testutils.inc deleted file mode 100644 index 8261b4faab8..00000000000 --- a/sim/testsuite/sim/frv/testutils.inc +++ /dev/null @@ -1,656 +0,0 @@ -# gr28-gr31, fr31, icc3, fcc3 are used as tmps. -# consider them call clobbered by these macros. - - .macro start - .data -failmsg: - .ascii "fail\n" -passmsg: - .ascii "pass\n" - .text - .global _start -_start: - ; enable data and insn caches in copy-back mode - ; Also enable all registers - or_spr_immed 0xc80003c0,hsr0 - and_spr_immed 0xfffff3ff,hsr0 - - ; turn on psr.nem, psr.cm, psr.ef, psr.em, psr.esr, - ; disable external interrupts - or_spr_immed 0x69f8,psr - - ; If fsr exists, enable all fp_exceptions except inexact - movsg psr,gr28 - srli gr28,28,gr28 - subicc gr28,0x2,gr0,icc3 ; is fr400? - beq icc3,0,nofsr0 - or_spr_immed 0x3d000000,fsr0 -nofsr0: - - ; Set the stack pointer - sethi.p 0x7,sp - setlo 0xfffc,sp ; TODO -- what's a good value for this? - - ; Set the TBR address - sethi.p 0xf,gr28 - setlo 0xf000,gr28 - movgs gr28,tbr ; TODO -- what's a good value for this? - - ; Go to user mode -- causes too many problems - ;and_spr_immed 0xfffffffb,psr - .endm - -; Set GR with another GR - .macro set_gr_gr src targ - addi \src,0,\targ - .endm - -; Set GR with immediate value - .macro set_gr_immed val reg - .if (\val >= -32768) && (\val <= 23767) - setlos \val,\reg - .else - setlo.p %lo(\val),\reg - sethi %hi(\val),\reg - .endif - .endm - - .macro set_gr_limmed valh vall reg - sethi.p \valh,\reg - setlo \vall,\reg - .endm - -; Set GR with address value - .macro set_gr_addr addr reg - sethi.p %hi(\addr),\reg - setlo %lo(\addr),\reg - .endm - -; Set GR with SPR - .macro set_gr_spr src targ - movsg \src,\targ - .endm - -; Set GR with a value from memory - .macro set_gr_mem addr reg - set_gr_addr \addr,gr28 - ldi @(gr28,0),\reg - .endm - -; Increment GR with immediate value - .macro inc_gr_immed val reg - .if (\val >= -2048) && (\val <= 2047) - addi \reg,\val,\reg - .else - set_gr_immed \val,gr28 - add \reg,gr28,\reg - .endif - .endm - -; AND GR with immediate value - .macro and_gr_immed val reg - .if (\val >= -2048) && (\val <= 2047) - andi \reg,\val,\reg - .else - set_gr_immed \val,gr28 - and \reg,gr28,\reg - .endif - .endm - -; OR GR with immediate value - .macro or_gr_immed val reg - .if (\val >= -2048) && (\val <= 2047) - ori \reg,\val,\reg - .else - set_gr_immed \val,gr28 - or \reg,gr28,\reg - .endif - .endm - -; Set FR with another FR - .macro set_fr_fr src targ - fmovs \src,\targ - .endm - -; Set FR with integer immediate value - .macro set_fr_iimmed valh vall reg - set_gr_limmed \valh,\vall,gr28 - movgf gr28,\reg - .endm - -; Set FR with integer immediate value - .macro set_fr_immed val reg - set_gr_immed \val,gr28 - movgf gr28,\reg - .endm - -; Set FR with a value from memory - .macro set_fr_mem addr reg - set_gr_addr \addr,gr28 - ldfi @(gr28,0),\reg - .endm - -; Set double FR with another double FR - .macro set_dfr_dfr src targ - fmovd \src,\targ - .endm - -; Set double FR with a value from memory - .macro set_dfr_mem addr reg - set_gr_addr \addr,gr28 - lddfi @(gr28,0),\reg - .endm - -; Set CPR with immediate value - .macro set_cpr_immed val reg - addi sp,-4,gr28 - set_gr_immed \val,gr29 - st gr29,@(gr28,gr0) - ldc @(gr28,gr0),\reg - .endm - - .macro set_cpr_limmed valh vall reg - addi sp,-4,gr28 - set_gr_limmed \valh,\vall,gr29 - st gr29,@(gr28,gr0) - ldc @(gr28,gr0),\reg - .endm - -; Set SPR with immediate value - .macro set_spr_immed val reg - set_gr_immed \val,gr28 - movgs gr28,\reg - .endm - - .macro set_spr_limmed valh vall reg - set_gr_limmed \valh,\vall,gr28 - movgs gr28,\reg - .endm - - .macro set_spr_addr addr reg - set_gr_addr \addr,gr28 - movgs gr28,\reg - .endm - -; increment SPR with immediate value - .macro inc_spr_immed val reg - movsg \reg,gr28 - inc_gr_immed \val,gr28 - movgs gr28,\reg - .endm - -; OR spr with immediate value - .macro or_spr_immed val reg - movsg \reg,gr28 - set_gr_immed \val,gr29 - or gr28,gr29,gr28 - movgs gr28,\reg - .endm - -; AND spr with immediate value - .macro and_spr_immed val reg - movsg \reg,gr28 - set_gr_immed \val,gr29 - and gr28,gr29,gr28 - movgs gr28,\reg - .endm - -; Set accumulator with immediate value - .macro set_acc_immed val reg - set_fr_immed \val,fr31 - mwtacc fr31,\reg - .endm - -; Set accumulator guard with immediate value - .macro set_accg_immed val reg - set_fr_immed \val,fr31 - mwtaccg fr31,\reg - .endm - -; Set memory with immediate value - .macro set_mem_immed val base - set_gr_immed \val,gr28 - sti gr28,@(\base,0) - .endm - - .macro set_mem_limmed valh vall base - set_gr_limmed \valh,\vall,gr28 - sti gr28,@(\base,0) - .endm - -; Set memory with GR value - .macro set_mem_gr reg addr - set_gr_addr \addr,gr28 - sti \reg,@(gr28,0) - .endm - -; Test the value of a general register against another general register - .macro test_gr_gr reg1 reg2 - subcc \reg1,\reg2,gr0,icc3 - beq icc3,0,test_gr\@ - fail -test_gr\@: - .endm - -; Test the value of an immediate against a general register - .macro test_gr_immed val reg - .if (\val >= -512) && (\val <= 511) - subicc \reg,\val,gr0,icc3 - .else - set_gr_immed \val,gr28 - subcc \reg,gr28,gr0,icc3 - .endif - beq icc3,0,test_gr\@ - fail -test_gr\@: - .endm - - .macro test_gr_limmed valh vall reg - set_gr_limmed \valh,\vall,gr28 - subcc \reg,gr28,gr0,icc3 - beq icc3,0,test_gr\@ - fail -test_gr\@: - .endm - -; Test the value of an floating register against an integer immediate - .macro test_fr_limmed valh vall reg - movfg \reg,gr29 - set_gr_limmed \valh,\vall,gr28 - subcc gr29,gr28,gr0,icc3 - beq icc3,0,test_gr\@ - fail -test_gr\@: - .endm - - .macro test_fr_iimmed val reg - movfg \reg,gr29 - set_gr_immed \val,gr28 - subcc gr29,gr28,gr0,icc3 - beq icc3,0,test_gr\@ - fail -test_gr\@: - .endm - -; Test the value of a floating register against another floating point register - .macro test_fr_fr reg1 reg2 - fcmps \reg1,\reg2,fcc3 - fbeq fcc3,0,test_gr\@ - fail -test_gr\@: - .endm - -; Test the value of a double floating register against another -; double floating point register - .macro test_dfr_dfr reg1 reg2 - fcmpd \reg1,\reg2,fcc3 - fbeq fcc3,0,test_gr\@ - fail -test_gr\@: - .endm - -; Test the value of a special purpose register against an integer immediate - .macro test_spr_immed val reg - movsg \reg,gr29 - set_gr_immed \val,gr28 - subcc gr29,gr28,gr0,icc3 - beq icc3,0,test_gr\@ - fail -test_gr\@: - .endm - - .macro test_spr_limmed valh vall reg - movsg \reg,gr29 - set_gr_limmed \valh,\vall,gr28 - subcc gr29,gr28,gr0,icc3 - beq icc3,0,test_gr\@ - fail -test_gr\@: - .endm - - .macro test_spr_gr spr gr - movsg \spr,gr28 - test_gr_gr \gr,gr28 - .endm - - .macro test_spr_addr addr reg - movsg \reg,gr29 - set_gr_addr \addr,gr28 - test_gr_gr gr28,gr29 - .endm - -; Test spr bits masked and shifted against the given value - .macro test_spr_bits mask,shift,val,reg - movsg \reg,gr28 - set_gr_immed \mask,gr29 - and gr28,gr29,gr28 - srli gr28,\shift,gr29 - test_gr_immed \val,gr29 - .endm - - -; Test the value of an accumulator against an integer immediate - .macro test_acc_immed val reg - mrdacc \reg,fr31 - test_fr_iimmed \val,fr31 - .endm - -; Test the value of an accumulator against an integer immediate - .macro test_acc_limmed valh vall reg - mrdacc \reg,fr31 - test_fr_limmed \valh,\vall,fr31 - .endm - -; Test the value of an accumulator guard against an integer immediate - .macro test_accg_immed val reg - mrdaccg \reg,fr31 - test_fr_iimmed \val,fr31 - .endm - -; Test CPR agains an immediate value - .macro test_cpr_limmed valh vall reg - addi sp,-4,gr31 - stc \reg,@(gr31,gr0) - test_mem_limmed \valh,\vall,gr31 - .endm - -; Test the value of an immediate against memory - .macro test_mem_immed val base - ldi @(\base,0),gr29 - .if (\val >= -512) && (\val <= 511) - subicc gr29,\val,gr0,icc3 - .else - set_gr_immed \val,gr28 - subcc gr29,gr28,gr0,icc3 - .endif - beq icc3,0,test_gr\@ - fail -test_gr\@: - .endm - - .macro test_mem_limmed valh vall base - ldi @(\base,0),gr29 - set_gr_limmed \valh,\vall,gr28 - subcc gr29,gr28,gr0,icc3 - beq icc3,0,test_gr\@ - fail -test_gr\@: - .endm - -; Set an integer condition code - .macro set_icc mask iccno - set_gr_immed 4,gr29 - smuli gr29,\iccno,gr30 - addi gr31,16,gr31 - set_gr_immed 0xf,gr28 - sll gr28,gr31,gr28 - not gr28,gr28 - movsg ccr,gr29 - and gr28,gr29,gr29 - set_gr_immed \mask,gr28 - sll gr28,gr31,gr28 - or gr28,gr29,gr29 - movgs gr29,ccr - .endm -; started here -; Test the condition codes - .macro test_icc N Z V C iccno - .if (\N == 1) - bp \iccno,0,fail\@ - .else - bn \iccno,0,fail\@ - .endif - .if (\Z == 1) - bne \iccno,0,fail\@ - .else - beq \iccno,0,fail\@ - .endif - .if (\V == 1) - bnv \iccno,0,fail\@ - .else - bv \iccno,0,fail\@ - .endif - .if (\C == 1) - bnc \iccno,0,fail\@ - .else - bc \iccno,0,fail\@ - .endif - bra test_cc\@ -fail\@: - fail -test_cc\@: - .endm - -; Set an floating point condition code - .macro set_fcc mask fccno - set_gr_immed 4,gr29 - smuli gr29,\fccno,gr30 - set_gr_immed 0xf,gr28 - sll gr28,gr31,gr28 - not gr28,gr28 - movsg ccr,gr29 - and gr28,gr29,gr29 - set_gr_immed \mask,gr28 - sll gr28,gr31,gr28 - or gr28,gr29,gr29 - movgs gr29,ccr - .endm - -; Test the condition codes - .macro test_fcc val fccno - set_gr_immed 4,gr29 - smuli gr29,\fccno,gr30 - movsg ccr,gr29 - srl gr29,gr31,gr29 - andi gr29,0xf,gr29 - test_gr_immed \val,gr29 - .endm - -; Set PSR.ET - .macro set_psr_et val - movsg psr,gr28 - .if (\val == 1) - ori gr28,1,gr28 ; Turn on SPR.ET - .else - andi gr28,0xfffffffe,gr28 ; Turn off SPR.ET - .endif - movgs gr28,psr - .endm - -; Floating point constants - .macro float_constants -f0: .float 0.0 -f1: .float 1.0 -f2: .float 2.0 -f3: .float 3.0 -f6: .float 6.0 -f9: .float 9.0 -fn0: .float -0.0 -fn1: .float -1.0 -finf: .long 0x7f800000 -fninf: .long 0xff800000 -fmax: .long 0x7f7fffff -fmin: .long 0xff7fffff -feps: .long 0x00400000 -fneps: .long 0x80400000 -fnan1: .long 0x7fc00000 -fnan2: .long 0x7f800001 - .endm - - .macro double_constants -d0: .double 0.0 -d1: .double 1.0 -d2: .double 2.0 -d3: .double 3.0 -d6: .double 6.0 -d9: .double 9.0 -dn0: .double -0.0 -dn1: .double -1.0 -dinf: .long 0x7ff00000 - .long 0x00000000 -dninf: .long 0xfff00000 - .long 0x00000000 -dmax: .long 0x7fefffff - .long 0xffffffff -dmin: .long 0xffefffff - .long 0xffffffff -deps: .long 0x00080000 - .long 0x00000000 -dneps: .long 0x80080000 - .long 0x00000000 -dnan1: .long 0x7ff80000 - .long 0x00000000 -dnan2: .long 0x7ff00000 - .long 0x00000001 - .endm - -; Load floating point constants - .macro load_float_constants - set_fr_mem fninf,fr0 - set_fr_mem fmin,fr4 - set_fr_mem fn1,fr8 - set_fr_mem fneps,fr12 - set_fr_mem fn0,fr16 - set_fr_mem f0,fr20 - set_fr_mem feps,fr24 - set_fr_mem f1,fr28 - set_fr_mem f2,fr32 - set_fr_mem f3,fr36 - set_fr_mem f6,fr40 - set_fr_mem f9,fr44 - set_fr_mem fmax,fr48 - set_fr_mem finf,fr52 - set_fr_mem fnan1,fr56 - set_fr_mem fnan2,fr60 - .endm - - .macro load_float_constants1 - set_fr_mem fninf,fr1 - set_fr_mem fmin,fr5 - set_fr_mem fn1,fr9 - set_fr_mem fneps,fr13 - set_fr_mem fn0,fr17 - set_fr_mem f0,fr21 - set_fr_mem feps,fr25 - set_fr_mem f1,fr29 - set_fr_mem f2,fr33 - set_fr_mem f3,fr37 - set_fr_mem f6,fr41 - set_fr_mem f9,fr45 - set_fr_mem fmax,fr49 - set_fr_mem finf,fr53 - set_fr_mem fnan1,fr57 - set_fr_mem fnan2,fr61 - .endm - - .macro load_float_constants2 - set_fr_mem fninf,fr2 - set_fr_mem fmin,fr6 - set_fr_mem fn1,fr10 - set_fr_mem fneps,fr14 - set_fr_mem fn0,fr18 - set_fr_mem f0,fr22 - set_fr_mem feps,fr26 - set_fr_mem f1,fr30 - set_fr_mem f2,fr34 - set_fr_mem f3,fr38 - set_fr_mem f6,fr42 - set_fr_mem f9,fr46 - set_fr_mem fmax,fr50 - set_fr_mem finf,fr54 - set_fr_mem fnan1,fr58 - set_fr_mem fnan2,fr62 - .endm - - .macro load_float_constants3 - set_fr_mem fninf,fr3 - set_fr_mem fmin,fr7 - set_fr_mem fn1,fr11 - set_fr_mem fneps,fr15 - set_fr_mem fn0,fr19 - set_fr_mem f0,fr23 - set_fr_mem feps,fr27 - set_fr_mem f1,fr31 - set_fr_mem f2,fr35 - set_fr_mem f3,fr39 - set_fr_mem f6,fr43 - set_fr_mem f9,fr47 - set_fr_mem fmax,fr51 - set_fr_mem finf,fr55 - set_fr_mem fnan1,fr59 - set_fr_mem fnan2,fr63 - .endm - - .macro load_double_constants - set_dfr_mem dninf,fr0 - set_dfr_mem dmin,fr4 - set_dfr_mem dn1,fr8 - set_dfr_mem dneps,fr12 - set_dfr_mem dn0,fr16 - set_dfr_mem d0,fr20 - set_dfr_mem deps,fr24 - set_dfr_mem d1,fr28 - set_dfr_mem d2,fr32 - set_dfr_mem d3,fr36 - set_dfr_mem d6,fr40 - set_dfr_mem d9,fr44 - set_dfr_mem dmax,fr48 - set_dfr_mem dinf,fr52 - set_dfr_mem dnan1,fr56 - set_dfr_mem dnan2,fr60 - .endm - -; Lock the insn cache at the given address - .macro lock_insn_cache address - icpl \address,gr0,1 - .endm - -; Lock the data cache at the given address - .macro lock_data_cache address - dcpl \address,gr0,1 - .endm - -; Invalidate the data cache at the given address - .macro invalidate_data_cache address - dci @(\address,gr0) - .endm - -; Flush the data cache at the given address - .macro flush_data_cache address - dcf @(\address,gr0) - .endm - -; Write a bctrlr 0,0 insn at the address contained in the given register - .macro set_bctrlr_0_0 address - set_mem_immed 0x80382000,\address ; bctrlr 0,0 - flush_data_cache \address - .endm - -; Exit with return code - .macro exit rc - setlos #1,gr7 - set_gr_immed \rc,gr8 - tira gr0,#0 - .endm - -; Pass the test case - .macro pass -pass\@: - setlos.p #5,gr10 - setlos #1,gr8 - setlos #5,gr7 - set_gr_addr passmsg,gr9 - tira gr0,#0 - exit #0 - .endm - -; Fail the testcase - .macro fail -fail\@: - setlos.p #5,gr10 - setlos #1,gr8 - setlos #5,gr7 - set_gr_addr failmsg,gr9 - tira gr0,#0 - exit #1 - .endm diff --git a/sim/testsuite/sim/frv/tge.cgs b/sim/testsuite/sim/frv/tge.cgs deleted file mode 100644 index 3e12d9245d1..00000000000 --- a/sim/testsuite/sim/frv/tge.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for tge $ICCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global tge -tge: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_psr_et 1 - set_spr_addr ok0,lr - set_icc 0x0 0 - tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x1 0 - tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_icc 0x2 0 - tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x3 0 - tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok4,lr - set_icc 0x4 0 - tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_icc 0x5 0 - tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_spr_addr bad,lr - set_icc 0x6 0 - tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x7 0 - tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x8 0 - tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x9 0 - tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oka,lr - set_icc 0xa 0 - tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_icc 0xb 0 - tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_spr_addr bad,lr - set_icc 0xc 0 - tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xd 0 - tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oke,lr - set_icc 0xe 0 - tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_icc 0xf 0 - tge icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tgt.cgs b/sim/testsuite/sim/frv/tgt.cgs deleted file mode 100644 index 7e01330f031..00000000000 --- a/sim/testsuite/sim/frv/tgt.cgs +++ /dev/null @@ -1,93 +0,0 @@ -# frv testcase for tgt $ICCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global tgt -tgt: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_psr_et 1 - set_spr_addr ok0,lr - set_icc 0x0 0 - tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x1 0 - tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_icc 0x2 0 - tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x3 0 - tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x4 0 - tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x5 0 - tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x6 0 - tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x7 0 - tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x8 0 - tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x9 0 - tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oka,lr - set_icc 0xa 0 - tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_icc 0xb 0 - tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_spr_addr bad,lr - set_icc 0xc 0 - tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xd 0 - tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xe 0 - tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xf 0 - tgt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/thi.cgs b/sim/testsuite/sim/frv/thi.cgs deleted file mode 100644 index 36cc9237647..00000000000 --- a/sim/testsuite/sim/frv/thi.cgs +++ /dev/null @@ -1,93 +0,0 @@ -# frv testcase for thi $ICCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global thi -thi: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_psr_et 1 - set_spr_addr ok0,lr - set_icc 0x0 0 - thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_spr_addr bad,lr - set_icc 0x1 0 - thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_icc 0x2 0 - thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_spr_addr bad,lr - set_icc 0x3 0 - thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x4 0 - thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x5 0 - thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x6 0 - thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x7 0 - thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok8,lr - set_icc 0x8 0 - thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_spr_addr bad,lr - set_icc 0x9 0 - thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oka,lr - set_icc 0xa 0 - thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_spr_addr bad,lr - set_icc 0xb 0 - thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xc 0 - thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xd 0 - thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xe 0 - thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xf 0 - thi icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tic.cgs b/sim/testsuite/sim/frv/tic.cgs deleted file mode 100644 index 8c746f5d29c..00000000000 --- a/sim/testsuite/sim/frv/tic.cgs +++ /dev/null @@ -1,100 +0,0 @@ -# frv testcase for tic $ICCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global tic -tic: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_icc 0x0 0 - tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x1 0 - tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_icc 0x2 0 - tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok3,lr - set_icc 0x3 0 - tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_icc 0x4 0 - tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok5,lr - set_icc 0x5 0 - tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_spr_addr bad,lr - set_icc 0x6 0 - tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok7,lr - set_icc 0x7 0 - tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_icc 0x8 0 - tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok9,lr - set_icc 0x9 0 - tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_spr_addr bad,lr - set_icc 0xa 0 - tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okb,lr - set_icc 0xb 0 - tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_spr_addr bad,lr - set_icc 0xc 0 - tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okd,lr - set_icc 0xd 0 - tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_spr_addr bad,lr - set_icc 0xe 0 - tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okf,lr - set_icc 0xf 0 - tic icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tieq.cgs b/sim/testsuite/sim/frv/tieq.cgs deleted file mode 100644 index 5dfc0e66f19..00000000000 --- a/sim/testsuite/sim/frv/tieq.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for tieq $ICCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global tieq -tieq: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_icc 0x0 0 - tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x1 0 - tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x2 0 - tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x3 0 - tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok4,lr - set_icc 0x4 0 - tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_icc 0x5 0 - tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_icc 0x6 0 - tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_icc 0x7 0 - tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr bad,lr - set_icc 0x8 0 - tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x9 0 - tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xa 0 - tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xb 0 - tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okc,lr - set_icc 0xc 0 - tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_icc 0xd 0 - tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_icc 0xe 0 - tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_icc 0xf 0 - tieq icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tige.cgs b/sim/testsuite/sim/frv/tige.cgs deleted file mode 100644 index cde3ac866c4..00000000000 --- a/sim/testsuite/sim/frv/tige.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for tige $ICCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global tige -tige: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_psr_et 1 - set_spr_addr ok0,lr - set_icc 0x0 0 - tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x1 0 - tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_icc 0x2 0 - tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x3 0 - tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok4,lr - set_icc 0x4 0 - tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_icc 0x5 0 - tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr bad,lr - set_icc 0x6 0 - tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x7 0 - tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x8 0 - tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x9 0 - tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oka,lr - set_icc 0xa 0 - tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_icc 0xb 0 - tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_spr_addr bad,lr - set_icc 0xc 0 - tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xd 0 - tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oke,lr - set_icc 0xe 0 - tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_icc 0xf 0 - tige icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tigt.cgs b/sim/testsuite/sim/frv/tigt.cgs deleted file mode 100644 index 163d92f179f..00000000000 --- a/sim/testsuite/sim/frv/tigt.cgs +++ /dev/null @@ -1,92 +0,0 @@ -# frv testcase for tigt $ICCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global tigt -tigt: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_psr_et 1 - set_spr_addr ok0,lr - set_icc 0x0 0 - tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x1 0 - tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_icc 0x2 0 - tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x3 0 - tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x4 0 - tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x5 0 - tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x6 0 - tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x7 0 - tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x8 0 - tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x9 0 - tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oka,lr - set_icc 0xa 0 - tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_icc 0xb 0 - tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_spr_addr bad,lr - set_icc 0xc 0 - tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xd 0 - tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xe 0 - tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xf 0 - tigt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tihi.cgs b/sim/testsuite/sim/frv/tihi.cgs deleted file mode 100644 index e564fc2982d..00000000000 --- a/sim/testsuite/sim/frv/tihi.cgs +++ /dev/null @@ -1,92 +0,0 @@ -# frv testcase for tihi $ICCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global tihi -tihi: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_psr_et 1 - set_spr_addr ok0,lr - set_icc 0x0 0 - tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_spr_addr bad,lr - set_icc 0x1 0 - tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_icc 0x2 0 - tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_spr_addr bad,lr - set_icc 0x3 0 - tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x4 0 - tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x5 0 - tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x6 0 - tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x7 0 - tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok8,lr - set_icc 0x8 0 - tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_spr_addr bad,lr - set_icc 0x9 0 - tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oka,lr - set_icc 0xa 0 - tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_spr_addr bad,lr - set_icc 0xb 0 - tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xc 0 - tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xd 0 - tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xe 0 - tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xf 0 - tihi icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tile.cgs b/sim/testsuite/sim/frv/tile.cgs deleted file mode 100644 index 7f5ef2a7ab8..00000000000 --- a/sim/testsuite/sim/frv/tile.cgs +++ /dev/null @@ -1,108 +0,0 @@ -# frv testcase for tile $ICCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global tile -tile: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_icc 0x0 0 - tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x1 0 - tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_icc 0x2 0 - tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_icc 0x3 0 - tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_icc 0x4 0 - tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_icc 0x5 0 - tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_icc 0x6 0 - tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_icc 0x7 0 - tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_icc 0x8 0 - tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_icc 0x9 0 - tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_spr_addr bad,lr - set_icc 0xa 0 - tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xb 0 - tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okc,lr - set_icc 0xc 0 - tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_icc 0xd 0 - tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_icc 0xe 0 - tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_icc 0xf 0 - tile icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tils.cgs b/sim/testsuite/sim/frv/tils.cgs deleted file mode 100644 index 5713de5cfc5..00000000000 --- a/sim/testsuite/sim/frv/tils.cgs +++ /dev/null @@ -1,108 +0,0 @@ -# frv testcase for tils $ICCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global tils -tils: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_icc 0x0 0 - tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x1 0 - tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_icc 0x2 0 - tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok3,lr - set_icc 0x3 0 - tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_icc 0x4 0 - tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_icc 0x5 0 - tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_icc 0x6 0 - tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_icc 0x7 0 - tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_icc 0x8 0 - tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok9,lr - set_icc 0x9 0 - tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_spr_addr bad,lr - set_icc 0xa 0 - tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okb,lr - set_icc 0xb 0 - tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_icc 0xc 0 - tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_icc 0xd 0 - tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_icc 0xe 0 - tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_icc 0xf 0 - tils icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tilt.cgs b/sim/testsuite/sim/frv/tilt.cgs deleted file mode 100644 index 4d596b01b9f..00000000000 --- a/sim/testsuite/sim/frv/tilt.cgs +++ /dev/null @@ -1,100 +0,0 @@ -# frv testcase for tilt $ICCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global tilt -tilt: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_icc 0x0 0 - tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x1 0 - tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_icc 0x2 0 - tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_icc 0x3 0 - tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_icc 0x4 0 - tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x5 0 - tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok6,lr - set_icc 0x6 0 - tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_icc 0x7 0 - tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_icc 0x8 0 - tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_icc 0x9 0 - tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_spr_addr bad,lr - set_icc 0xa 0 - tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xb 0 - tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okc,lr - set_icc 0xc 0 - tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_icc 0xd 0 - tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_spr_addr bad,lr - set_icc 0xe 0 - tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xf 0 - tilt icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tin.cgs b/sim/testsuite/sim/frv/tin.cgs deleted file mode 100644 index f55c921c012..00000000000 --- a/sim/testsuite/sim/frv/tin.cgs +++ /dev/null @@ -1,100 +0,0 @@ -# frv testcase for tin $ICCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global tin -tin: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_icc 0x0 0 - tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x1 0 - tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x2 0 - tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x3 0 - tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x4 0 - tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x5 0 - tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x6 0 - tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x7 0 - tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok8,lr - set_icc 0x8 0 - tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_icc 0x9 0 - tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_icc 0xa 0 - tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_icc 0xb 0 - tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_icc 0xc 0 - tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_icc 0xd 0 - tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_icc 0xe 0 - tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_icc 0xf 0 - tin icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tinc.cgs b/sim/testsuite/sim/frv/tinc.cgs deleted file mode 100644 index 8e99e31531f..00000000000 --- a/sim/testsuite/sim/frv/tinc.cgs +++ /dev/null @@ -1,100 +0,0 @@ -# frv testcase for tinc $ICCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global tinc -tinc: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_psr_et 1 - set_spr_addr ok0,lr - set_icc 0x0 0 - tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_spr_addr bad,lr - set_icc 0x1 0 - tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_icc 0x2 0 - tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_spr_addr bad,lr - set_icc 0x3 0 - tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok4,lr - set_icc 0x4 0 - tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_spr_addr bad,lr - set_icc 0x5 0 - tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok6,lr - set_icc 0x6 0 - tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_spr_addr bad,lr - set_icc 0x7 0 - tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok8,lr - set_icc 0x8 0 - tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_spr_addr bad,lr - set_icc 0x9 0 - tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oka,lr - set_icc 0xa 0 - tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_spr_addr bad,lr - set_icc 0xb 0 - tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okc,lr - set_icc 0xc 0 - tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_spr_addr bad,lr - set_icc 0xd 0 - tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oke,lr - set_icc 0xe 0 - tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_spr_addr bad,lr - set_icc 0xf 0 - tinc icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tine.cgs b/sim/testsuite/sim/frv/tine.cgs deleted file mode 100644 index d7e8b005416..00000000000 --- a/sim/testsuite/sim/frv/tine.cgs +++ /dev/null @@ -1,100 +0,0 @@ -# frv testcase for tine $ICCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global tine -tine: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_psr_et 1 - set_spr_addr ok0,lr - set_icc 0x0 0 - tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x1 0 - tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_psr_et 1 - set_spr_addr ok2,lr - set_icc 0x2 0 - tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_icc 0x3 0 - tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_icc 0x4 0 - tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x5 0 - tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x6 0 - tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x7 0 - tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok8,lr - set_icc 0x8 0 - tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_icc 0x9 0 - tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_icc 0xa 0 - tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_icc 0xb 0 - tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_spr_addr bad,lr - set_icc 0xc 0 - tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xd 0 - tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xe 0 - tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xf 0 - tine icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tino.cgs b/sim/testsuite/sim/frv/tino.cgs deleted file mode 100644 index 65a2d6d2835..00000000000 --- a/sim/testsuite/sim/frv/tino.cgs +++ /dev/null @@ -1,53 +0,0 @@ -# frv testcase for tino -# mach: all - - .include "testutils.inc" - - start - - .global tinev -tinev: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_mem_limmed 0x0038,0x2000,gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_gr_immed 0,gr7 - - set_icc 0x0 0 - tino ; should branch to tbr + (128 + 4)*16 - set_icc 0x1 0 - tino ; should branch to tbr + (128 + 4)*16 - set_icc 0x2 0 - tino ; should branch to tbr + (128 + 4)*16 - set_icc 0x3 0 - tino ; should branch to tbr + (128 + 4)*16 - set_icc 0x4 0 - tino ; should branch to tbr + (128 + 4)*16 - set_icc 0x5 0 - tino ; should branch to tbr + (128 + 4)*16 - set_icc 0x6 0 - tino ; should branch to tbr + (128 + 4)*16 - set_icc 0x7 0 - tino ; should branch to tbr + (128 + 4)*16 - set_icc 0x8 0 - tino ; should branch to tbr + (128 + 4)*16 - set_icc 0x9 0 - tino ; should branch to tbr + (128 + 4)*16 - set_icc 0xa 0 - tino ; should branch to tbr + (128 + 4)*16 - set_icc 0xb 0 - tino ; should branch to tbr + (128 + 4)*16 - set_icc 0xc 0 - tino ; should branch to tbr + (128 + 4)*16 - set_icc 0xd 0 - tino ; should branch to tbr + (128 + 4)*16 - set_icc 0xe 0 - tino ; should branch to tbr + (128 + 4)*16 - set_icc 0xf 0 - tino ; should branch to tbr + (128 + 4)*16 - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tinv.cgs b/sim/testsuite/sim/frv/tinv.cgs deleted file mode 100644 index 7ec34a42271..00000000000 --- a/sim/testsuite/sim/frv/tinv.cgs +++ /dev/null @@ -1,100 +0,0 @@ -# frv testcase for tinv $ICCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global tinv -tinv: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_psr_et 1 - set_spr_addr ok0,lr - set_icc 0x0 0 - tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x1 0 - tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_icc 0x2 0 - tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x3 0 - tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok4,lr - set_icc 0x4 0 - tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_icc 0x5 0 - tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_spr_addr bad,lr - set_icc 0x6 0 - tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x7 0 - tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok8,lr - set_icc 0x8 0 - tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_icc 0x9 0 - tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_spr_addr bad,lr - set_icc 0xa 0 - tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xb 0 - tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okc,lr - set_icc 0xc 0 - tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_icc 0xd 0 - tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_spr_addr bad,lr - set_icc 0xe 0 - tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xf 0 - tinv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tip.cgs b/sim/testsuite/sim/frv/tip.cgs deleted file mode 100644 index 835342292f4..00000000000 --- a/sim/testsuite/sim/frv/tip.cgs +++ /dev/null @@ -1,100 +0,0 @@ -# frv testcase for tip $ICCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global tip -tip: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_psr_et 1 - set_spr_addr ok0,lr - set_icc 0x0 0 - tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x1 0 - tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_psr_et 1 - set_spr_addr ok2,lr - set_icc 0x2 0 - tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_icc 0x3 0 - tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_icc 0x4 0 - tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_icc 0x5 0 - tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_icc 0x6 0 - tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_icc 0x7 0 - tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_icc 0x8 0 - tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x9 0 - tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xa 0 - tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xb 0 - tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xc 0 - tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xd 0 - tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xe 0 - tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xf 0 - tip icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tira.cgs b/sim/testsuite/sim/frv/tira.cgs deleted file mode 100644 index bd3139e628d..00000000000 --- a/sim/testsuite/sim/frv/tira.cgs +++ /dev/null @@ -1,114 +0,0 @@ -# frv testcase for tira $GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global tira -tira: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_psr_et 1 - set_spr_addr ok0,lr - set_icc 0x0 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x1 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_psr_et 1 - set_spr_addr ok2,lr - set_icc 0x2 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_icc 0x3 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_icc 0x4 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_icc 0x5 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_icc 0x6 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_icc 0x7 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_icc 0x8 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_icc 0x9 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_icc 0xa 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_icc 0xb 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_icc 0xc 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_icc 0xd 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_icc 0xe 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_icc 0xf 0 - tira gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass diff --git a/sim/testsuite/sim/frv/tiv.cgs b/sim/testsuite/sim/frv/tiv.cgs deleted file mode 100644 index 84a25762eb7..00000000000 --- a/sim/testsuite/sim/frv/tiv.cgs +++ /dev/null @@ -1,100 +0,0 @@ -# frv testcase for tiv $ICCi_2,$GRi,$s12 -# mach: all - - .include "testutils.inc" - - start - - .global tiv -tiv: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - - set_spr_addr bad,lr - set_icc 0x0 0 - tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x1 0 - tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_icc 0x2 0 - tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_icc 0x3 0 - tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_icc 0x4 0 - tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x5 0 - tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok6,lr - set_icc 0x6 0 - tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_icc 0x7 0 - tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_icc 0x8 0 - tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x9 0 - tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oka,lr - set_icc 0xa 0 - tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_icc 0xb 0 - tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_spr_addr bad,lr - set_icc 0xc 0 - tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xd 0 - tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oke,lr - set_icc 0xe 0 - tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_icc 0xf 0 - tiv icc0,gr7,4 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tle.cgs b/sim/testsuite/sim/frv/tle.cgs deleted file mode 100644 index 1322821b60e..00000000000 --- a/sim/testsuite/sim/frv/tle.cgs +++ /dev/null @@ -1,109 +0,0 @@ -# frv testcase for tle $ICCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global tle -tle: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_icc 0x0 0 - tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x1 0 - tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_icc 0x2 0 - tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_icc 0x3 0 - tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_icc 0x4 0 - tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_icc 0x5 0 - tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_icc 0x6 0 - tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_icc 0x7 0 - tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_icc 0x8 0 - tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_icc 0x9 0 - tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_spr_addr bad,lr - set_icc 0xa 0 - tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xb 0 - tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okc,lr - set_icc 0xc 0 - tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_icc 0xd 0 - tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_icc 0xe 0 - tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_icc 0xf 0 - tle icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tls.cgs b/sim/testsuite/sim/frv/tls.cgs deleted file mode 100644 index 708e61735c0..00000000000 --- a/sim/testsuite/sim/frv/tls.cgs +++ /dev/null @@ -1,109 +0,0 @@ -# frv testcase for tls $ICCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global tls -tls: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_icc 0x0 0 - tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x1 0 - tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_icc 0x2 0 - tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok3,lr - set_icc 0x3 0 - tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_icc 0x4 0 - tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_icc 0x5 0 - tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_icc 0x6 0 - tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_icc 0x7 0 - tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_icc 0x8 0 - tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok9,lr - set_icc 0x9 0 - tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_spr_addr bad,lr - set_icc 0xa 0 - tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okb,lr - set_icc 0xb 0 - tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_icc 0xc 0 - tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_icc 0xd 0 - tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_icc 0xe 0 - tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_icc 0xf 0 - tls icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tlt.cgs b/sim/testsuite/sim/frv/tlt.cgs deleted file mode 100644 index 12ee05b7f97..00000000000 --- a/sim/testsuite/sim/frv/tlt.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for tlt $ICCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global tlt -tlt: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_icc 0x0 0 - tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x1 0 - tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_icc 0x2 0 - tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_icc 0x3 0 - tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_icc 0x4 0 - tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x5 0 - tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok6,lr - set_icc 0x6 0 - tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_icc 0x7 0 - tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_icc 0x8 0 - tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_icc 0x9 0 - tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_spr_addr bad,lr - set_icc 0xa 0 - tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xb 0 - tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okc,lr - set_icc 0xc 0 - tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_icc 0xd 0 - tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_spr_addr bad,lr - set_icc 0xe 0 - tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xf 0 - tlt icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tn.cgs b/sim/testsuite/sim/frv/tn.cgs deleted file mode 100644 index 05b04240aa2..00000000000 --- a/sim/testsuite/sim/frv/tn.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for tn $ICCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global tn -tn: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_icc 0x0 0 - tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x1 0 - tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x2 0 - tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x3 0 - tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x4 0 - tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x5 0 - tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x6 0 - tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x7 0 - tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok8,lr - set_icc 0x8 0 - tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_icc 0x9 0 - tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_icc 0xa 0 - tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_icc 0xb 0 - tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_icc 0xc 0 - tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_icc 0xd 0 - tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_icc 0xe 0 - tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_icc 0xf 0 - tn icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tnc.cgs b/sim/testsuite/sim/frv/tnc.cgs deleted file mode 100644 index 808db3c2c95..00000000000 --- a/sim/testsuite/sim/frv/tnc.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for tnc $ICCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global tnc -tnc: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_psr_et 1 - set_spr_addr ok0,lr - set_icc 0x0 0 - tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_spr_addr bad,lr - set_icc 0x1 0 - tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_icc 0x2 0 - tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_spr_addr bad,lr - set_icc 0x3 0 - tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok4,lr - set_icc 0x4 0 - tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_spr_addr bad,lr - set_icc 0x5 0 - tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok6,lr - set_icc 0x6 0 - tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_spr_addr bad,lr - set_icc 0x7 0 - tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok8,lr - set_icc 0x8 0 - tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_spr_addr bad,lr - set_icc 0x9 0 - tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oka,lr - set_icc 0xa 0 - tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_spr_addr bad,lr - set_icc 0xb 0 - tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okc,lr - set_icc 0xc 0 - tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_spr_addr bad,lr - set_icc 0xd 0 - tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oke,lr - set_icc 0xe 0 - tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_spr_addr bad,lr - set_icc 0xf 0 - tnc icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tne.cgs b/sim/testsuite/sim/frv/tne.cgs deleted file mode 100644 index 880188d2919..00000000000 --- a/sim/testsuite/sim/frv/tne.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for tne $ICCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global tne -tne: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_psr_et 1 - set_spr_addr ok0,lr - set_icc 0x0 0 - tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x1 0 - tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_psr_et 1 - set_spr_addr ok2,lr - set_icc 0x2 0 - tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_icc 0x3 0 - tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_icc 0x4 0 - tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x5 0 - tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x6 0 - tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x7 0 - tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok8,lr - set_icc 0x8 0 - tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_icc 0x9 0 - tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_icc 0xa 0 - tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_icc 0xb 0 - tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_spr_addr bad,lr - set_icc 0xc 0 - tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xd 0 - tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xe 0 - tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xf 0 - tne icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tno.cgs b/sim/testsuite/sim/frv/tno.cgs deleted file mode 100644 index df499699367..00000000000 --- a/sim/testsuite/sim/frv/tno.cgs +++ /dev/null @@ -1,54 +0,0 @@ -# frv testcase for tno -# mach: all - - .include "testutils.inc" - - start - - .global tno -tno: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_mem_limmed 0x0038,0x2000,gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_spr_addr bad,lr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_icc 0x0 0 - tno ; should branch to tbr + (128 + 4)*16 - set_icc 0x1 0 - tno ; should branch to tbr + (128 + 4)*16 - set_icc 0x2 0 - tno ; should branch to tbr + (128 + 4)*16 - set_icc 0x3 0 - tno ; should branch to tbr + (128 + 4)*16 - set_icc 0x4 0 - tno ; should branch to tbr + (128 + 4)*16 - set_icc 0x5 0 - tno ; should branch to tbr + (128 + 4)*16 - set_icc 0x6 0 - tno ; should branch to tbr + (128 + 4)*16 - set_icc 0x7 0 - tno ; should branch to tbr + (128 + 4)*16 - set_icc 0x8 0 - tno ; should branch to tbr + (128 + 4)*16 - set_icc 0x9 0 - tno ; should branch to tbr + (128 + 4)*16 - set_icc 0xa 0 - tno ; should branch to tbr + (128 + 4)*16 - set_icc 0xb 0 - tno ; should branch to tbr + (128 + 4)*16 - set_icc 0xc 0 - tno ; should branch to tbr + (128 + 4)*16 - set_icc 0xd 0 - tno ; should branch to tbr + (128 + 4)*16 - set_icc 0xe 0 - tno ; should branch to tbr + (128 + 4)*16 - set_icc 0xf 0 - tno ; should branch to tbr + (128 + 4)*16 - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tnv.cgs b/sim/testsuite/sim/frv/tnv.cgs deleted file mode 100644 index d7f9241b05b..00000000000 --- a/sim/testsuite/sim/frv/tnv.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for tnv $ICCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global tnv -tnv: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_psr_et 1 - set_spr_addr ok0,lr - set_icc 0x0 0 - tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x1 0 - tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_spr_addr bad,lr - set_icc 0x2 0 - tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x3 0 - tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok4,lr - set_icc 0x4 0 - tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_icc 0x5 0 - tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_spr_addr bad,lr - set_icc 0x6 0 - tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x7 0 - tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok8,lr - set_icc 0x8 0 - tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_icc 0x9 0 - tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_spr_addr bad,lr - set_icc 0xa 0 - tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xb 0 - tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr okc,lr - set_icc 0xc 0 - tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_icc 0xd 0 - tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_spr_addr bad,lr - set_icc 0xe 0 - tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xf 0 - tnv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tp.cgs b/sim/testsuite/sim/frv/tp.cgs deleted file mode 100644 index 2709e31cf2b..00000000000 --- a/sim/testsuite/sim/frv/tp.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for tp $ICCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global tp -tp: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_psr_et 1 - set_spr_addr ok0,lr - set_icc 0x0 0 - tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok0: - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x1 0 - tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_psr_et 1 - set_spr_addr ok2,lr - set_icc 0x2 0 - tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_icc 0x3 0 - tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_icc 0x4 0 - tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_icc 0x5 0 - tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_icc 0x6 0 - tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_icc 0x7 0 - tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_icc 0x8 0 - tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x9 0 - tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xa 0 - tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xb 0 - tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xc 0 - tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xd 0 - tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xe 0 - tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xf 0 - tp icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/tra.cgs b/sim/testsuite/sim/frv/tra.cgs deleted file mode 100644 index 368c83acdca..00000000000 --- a/sim/testsuite/sim/frv/tra.cgs +++ /dev/null @@ -1,117 +0,0 @@ -# frv testcase for tra $GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global tra -tra: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_psr_et 1 - set_spr_addr ok0,lr - set_icc 0x0 0 - tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 -bad0: - fail -ok0: - test_spr_addr bad0,pcsr - set_psr_et 1 - set_spr_addr ok1,lr - set_icc 0x1 0 - tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok1: - set_psr_et 1 - set_spr_addr ok2,lr - set_icc 0x2 0 - tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_icc 0x3 0 - tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_psr_et 1 - set_spr_addr ok4,lr - set_icc 0x4 0 - tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok4: - set_psr_et 1 - set_spr_addr ok5,lr - set_icc 0x5 0 - tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok5: - set_psr_et 1 - set_spr_addr ok6,lr - set_icc 0x6 0 - tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_icc 0x7 0 - tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_psr_et 1 - set_spr_addr ok8,lr - set_icc 0x8 0 - tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok8: - set_psr_et 1 - set_spr_addr ok9,lr - set_icc 0x9 0 - tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok9: - set_psr_et 1 - set_spr_addr oka,lr - set_icc 0xa 0 - tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_icc 0xb 0 - tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_psr_et 1 - set_spr_addr okc,lr - set_icc 0xc 0 - tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okc: - set_psr_et 1 - set_spr_addr okd,lr - set_icc 0xd 0 - tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okd: - set_psr_et 1 - set_spr_addr oke,lr - set_icc 0xe 0 - tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_icc 0xf 0 - tra gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass diff --git a/sim/testsuite/sim/frv/tv.cgs b/sim/testsuite/sim/frv/tv.cgs deleted file mode 100644 index d173f2994e4..00000000000 --- a/sim/testsuite/sim/frv/tv.cgs +++ /dev/null @@ -1,101 +0,0 @@ -# frv testcase for tv $ICCi_2,$GRi,$GRj -# mach: all - - .include "testutils.inc" - - start - - .global tv -tv: - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr7 - inc_gr_immed 2112,gr7 ; address of exception handler - set_bctrlr_0_0 gr7 ; bctrlr 0,0 - - set_spr_immed 128,lcr - set_gr_immed 0,gr7 - set_gr_immed 4,gr8 - - set_spr_addr bad,lr - set_icc 0x0 0 - tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x1 0 - tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok2,lr - set_icc 0x2 0 - tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok2: - set_psr_et 1 - set_spr_addr ok3,lr - set_icc 0x3 0 - tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok3: - set_spr_addr bad,lr - set_icc 0x4 0 - tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x5 0 - tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr ok6,lr - set_icc 0x6 0 - tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok6: - set_psr_et 1 - set_spr_addr ok7,lr - set_icc 0x7 0 - tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -ok7: - set_spr_addr bad,lr - set_icc 0x8 0 - tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0x9 0 - tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oka,lr - set_icc 0xa 0 - tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oka: - set_psr_et 1 - set_spr_addr okb,lr - set_icc 0xb 0 - tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okb: - set_spr_addr bad,lr - set_icc 0xc 0 - tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_spr_addr bad,lr - set_icc 0xd 0 - tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - - set_psr_et 1 - set_spr_addr oke,lr - set_icc 0xe 0 - tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -oke: - set_psr_et 1 - set_spr_addr okf,lr - set_icc 0xf 0 - tv icc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16 - fail -okf: - pass -bad: - fail diff --git a/sim/testsuite/sim/frv/udiv.cgs b/sim/testsuite/sim/frv/udiv.cgs deleted file mode 100644 index 35cfa8c84ab..00000000000 --- a/sim/testsuite/sim/frv/udiv.cgs +++ /dev/null @@ -1,48 +0,0 @@ -# frv testcase for udiv $GRi,$GRj,$GRk -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global udiv -udiv: - ; simple division 12 / 3 - set_gr_immed 0x00000003,gr2 - set_gr_immed 0x0000000c,gr3 - udiv gr3,gr2,gr3 - test_gr_immed 0x00000003,gr2 - test_gr_immed 0x00000004,gr3 - - ; example 1 from udiv in the fr30 manual - set_gr_limmed 0x0123,0x4567,gr2 - set_gr_limmed 0xfedc,0xba98,gr3 - udiv gr3,gr2,gr3 - test_gr_limmed 0x0123,0x4567,gr2 - test_gr_immed 0x000000e0,gr3 - - ; set up exception handler - set_psr_et 1 - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x170,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_gr_immed 0,gr15 - - ; divide by zero - set_spr_addr ok1,lr - set_gr_addr e1,gr17 -e1: udiv gr1,gr0,gr2 ; divide by zero - test_gr_immed 1,gr15 - - pass - -ok1: ; exception handler for divide by zero - test_spr_bits 0x18,3,0x1,isr ; isr.dtt is set - test_spr_gr epcr0,gr17 ; return address set - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/udivi.cgs b/sim/testsuite/sim/frv/udivi.cgs deleted file mode 100644 index 6a505900d07..00000000000 --- a/sim/testsuite/sim/frv/udivi.cgs +++ /dev/null @@ -1,49 +0,0 @@ -# frv testcase for udivi $GRi,$s12,$GRk -# mach: frv fr500 fr400 - - .include "testutils.inc" - - start - - .global udivi -udivi: - ; simple division 12 / 3 - set_gr_immed 0x0000000c,gr3 - udivi gr3,3,gr3 - test_gr_immed 0x00000004,gr3 - - ; random example - set_gr_limmed 0xfedc,0xba98,gr3 - udivi gr3,0x7ff,gr3 - test_gr_limmed 0x001f,0xdf93,gr3 - - ; random example - set_gr_limmed 0xffff,0xffff,gr3 - udivi gr3,-2048,gr3 - test_gr_immed 1,gr3 - - ; set up exception handler - set_psr_et 1 - and_spr_immed -4081,tbr ; clear tbr.tt - set_gr_spr tbr,gr17 - inc_gr_immed 0x170,gr17 ; address of exception handler - set_bctrlr_0_0 gr17 - set_spr_immed 128,lcr - set_gr_immed 0,gr15 - - ; divide by zero - set_spr_addr ok1,lr - set_gr_addr e1,gr17 -e1: udivi gr1,0,gr2 ; divide by zero - test_gr_immed 1,gr15 - - pass - -ok1: ; exception handler for divide by zero - test_spr_bits 0x18,3,0x1,isr ; isr.dtt is set - test_spr_gr epcr0,gr17 ; return address set - test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid - test_spr_bits 0x003e,1,0x13,esr0 ; esr0.ec is set - inc_gr_immed 1,gr15 - rett 0 - fail diff --git a/sim/testsuite/sim/frv/umul.cgs b/sim/testsuite/sim/frv/umul.cgs deleted file mode 100644 index 6c612217036..00000000000 --- a/sim/testsuite/sim/frv/umul.cgs +++ /dev/null @@ -1,76 +0,0 @@ -# frv testcase for umul $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global umul -umul: - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - umul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - umul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - umul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - umul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - umul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - umul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - umul gr7,gr8,gr8 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x8000,0x0000,gr7 ; 33 bit result - set_gr_immed 2,gr8 - umul gr7,gr8,gr8 - test_gr_immed 1,gr8 - test_gr_immed 0x00000000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - umul gr7,gr8,gr8 - test_gr_limmed 0x3fff,0xffff,gr8 - test_gr_immed 0x00000001,gr9 - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - umul gr7,gr8,gr8 - test_gr_limmed 0x4000,0x0000,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xffff,0xffff,gr7 ; max positive result - set_gr_limmed 0xffff,0xffff,gr8 - umul gr7,gr8,gr8 - test_gr_limmed 0xffff,0xfffe,gr8 - test_gr_immed 1,gr9 - - pass diff --git a/sim/testsuite/sim/frv/umulcc.cgs b/sim/testsuite/sim/frv/umulcc.cgs deleted file mode 100644 index c2b5cff0ea5..00000000000 --- a/sim/testsuite/sim/frv/umulcc.cgs +++ /dev/null @@ -1,98 +0,0 @@ -# frv testcase for umulcc $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global umulcc -umulcc: - set_gr_immed 3,gr7 ; multiply small numbers - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - umulcc gr7,gr8,gr8,icc0 - test_icc 0 0 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_gr_immed 2,gr8 - set_icc 0x0e,0 ; Set mask opposite of expected - umulcc gr7,gr8,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_gr_immed 1,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - umulcc gr7,gr8,gr8,icc0 - test_icc 0 0 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_gr_immed 2,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - umulcc gr7,gr8,gr8,icc0 - test_icc 0 1 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_gr_immed 0,gr8 - set_icc 0x0a,0 ; Set mask opposite of expected - umulcc gr7,gr8,gr8,icc0 - test_icc 0 1 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_gr_immed 2,gr8 - set_icc 0x0f,0 ; Set mask opposite of expected - umulcc gr7,gr8,gr8,icc0 - test_icc 0 0 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_gr_immed 2,gr8 - set_icc 0x0e,0 ; Set mask opposite of expected - umulcc gr7,gr8,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x8000,0x0000,gr7 ; 33 bit result - set_gr_immed 2,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - umulcc gr7,gr8,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_immed 1,gr8 - test_gr_immed 0x00000000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_gr_limmed 0x7fff,0xffff,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - umulcc gr7,gr8,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_limmed 0x3fff,0xffff,gr8 - test_gr_immed 1,gr9 - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_gr_limmed 0x8000,0x0000,gr8 - set_icc 0x0d,0 ; Set mask opposite of expected - umulcc gr7,gr8,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_limmed 0x4000,0x0000,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0xffff,0xffff,gr7 ; max positive result - set_gr_limmed 0xffff,0xffff,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - umulcc gr7,gr8,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xffff,0xfffe,gr8 - test_gr_immed 1,gr9 - - pass diff --git a/sim/testsuite/sim/frv/umuli.cgs b/sim/testsuite/sim/frv/umuli.cgs deleted file mode 100644 index 6f1b9c12211..00000000000 --- a/sim/testsuite/sim/frv/umuli.cgs +++ /dev/null @@ -1,87 +0,0 @@ -# frv testcase for umuli $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global umuli -umuli: - set_gr_immed 3,gr7 ; multiply small numbers - set_icc 0x0f,0 ; Set mask opposite of expected - umuli gr7,2,gr8 - test_icc 1 1 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_icc 0x0e,0 ; Set mask opposite of expected - umuli gr7,2,gr8 - test_icc 1 1 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_icc 0x0f,0 ; Set mask opposite of expected - umuli gr7,1,gr8 - test_icc 1 1 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_icc 0x0b,0 ; Set mask opposite of expected - umuli gr7,2,gr8 - test_icc 1 0 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_icc 0x0a,0 ; Set mask opposite of expected - umuli gr7,0,gr8 - test_icc 1 0 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_icc 0x0f,0 ; Set mask opposite of expected - umuli gr7,2,gr8 - test_icc 1 1 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_icc 0x0e,0 ; Set mask opposite of expected - umuli gr7,2,gr8 - test_icc 1 1 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x8000,0x0000,gr7 ; 33 bit result - set_icc 0x09,0 ; Set mask opposite of expected - umuli gr7,2,gr8 - test_icc 1 0 0 1 icc0 - test_gr_immed 1,gr8 - test_gr_immed 0x00000000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_icc 0x0d,0 ; Set mask opposite of expected - umuli gr7,0x7ff,gr8 - test_icc 1 1 0 1 icc0 - test_gr_immed 0x3ff,gr8 - test_gr_limmed 0x7fff,0xf801,gr9 - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_icc 0x09,0 ; Set mask opposite of expected - umuli gr7,-2048,gr8 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0x7fff,0xfc00,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0xffff,0xffff,gr7 ; max positive result - set_icc 0x05,0 ; Set mask opposite of expected - umuli gr7,-1,gr8 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0xffff,0xfffe,gr8 - test_gr_immed 1,gr9 - - pass diff --git a/sim/testsuite/sim/frv/umulicc.cgs b/sim/testsuite/sim/frv/umulicc.cgs deleted file mode 100644 index 0d0d0c1cd0c..00000000000 --- a/sim/testsuite/sim/frv/umulicc.cgs +++ /dev/null @@ -1,87 +0,0 @@ -# frv testcase for umulicc $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global umulicc -umulicc: - set_gr_immed 3,gr7 ; multiply small numbers - set_icc 0x0f,0 ; Set mask opposite of expected - umulicc gr7,2,gr8,icc0 - test_icc 0 0 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 6,gr9 - - set_gr_immed 1,gr7 ; multiply by 1 - set_icc 0x0e,0 ; Set mask opposite of expected - umulicc gr7,2,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 2,gr7 ; multiply by 1 - set_icc 0x0f,0 ; Set mask opposite of expected - umulicc gr7,1,gr8,icc0 - test_icc 0 0 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 2,gr9 - - set_gr_immed 0,gr7 ; multiply by 0 - set_icc 0x0b,0 ; Set mask opposite of expected - umulicc gr7,2,gr8,icc0 - test_icc 0 1 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_immed 2,gr7 ; multiply by 0 - set_icc 0x0a,0 ; Set mask opposite of expected - umulicc gr7,0,gr8,icc0 - test_icc 0 1 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_immed 0,gr9 - - set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result - set_icc 0x0f,0 ; Set mask opposite of expected - umulicc gr7,2,gr8,icc0 - test_icc 0 0 1 1 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x7fff,0xfffe,gr9 - - set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result - set_icc 0x0e,0 ; Set mask opposite of expected - umulicc gr7,2,gr8,icc0 - test_icc 0 0 1 0 icc0 - test_gr_immed 0,gr8 - test_gr_limmed 0x8000,0x0000,gr9 - - set_gr_limmed 0x8000,0x0000,gr7 ; 33 bit result - set_icc 0x09,0 ; Set mask opposite of expected - umulicc gr7,2,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_immed 1,gr8 - test_gr_immed 0x00000000,gr9 - - set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result - set_icc 0x0d,0 ; Set mask opposite of expected - umulicc gr7,0x1ff,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_immed 0xff,gr8 - test_gr_limmed 0x7fff,0xfe01,gr9 - - set_gr_limmed 0x8000,0x0000,gr7 ; max positive result - set_icc 0x09,0 ; Set mask opposite of expected - umulicc gr7,-512,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_limmed 0x7fff,0xff00,gr8 - test_gr_limmed 0x0000,0x0000,gr9 - - set_gr_limmed 0xffff,0xffff,gr7 ; max positive result - set_icc 0x05,0 ; Set mask opposite of expected - umulicc gr7,-1,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xffff,0xfffe,gr8 - test_gr_immed 1,gr9 - - pass diff --git a/sim/testsuite/sim/frv/xor.cgs b/sim/testsuite/sim/frv/xor.cgs deleted file mode 100644 index 97310e440a7..00000000000 --- a/sim/testsuite/sim/frv/xor.cgs +++ /dev/null @@ -1,38 +0,0 @@ -# frv testcase for xor $GRi,$GRj,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global xor -xor: - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - xor gr7,gr8,gr8 - test_icc 0 1 1 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 0x00000000,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - xor gr7,gr8,gr8 - test_icc 1 0 0 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - xor gr7,gr8,gr8 - test_icc 1 0 1 1 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - xor gr7,gr8,gr8 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0xdead,0xbeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/xorcc.cgs b/sim/testsuite/sim/frv/xorcc.cgs deleted file mode 100644 index 9516b789153..00000000000 --- a/sim/testsuite/sim/frv/xorcc.cgs +++ /dev/null @@ -1,38 +0,0 @@ -# frv testcase for xorcc $GRi,$GRj,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global xorcc -xorcc: - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0x5555,0x5555,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - xorcc gr7,gr8,gr8,icc0 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0xffff,0xffff,gr8 - - set_gr_immed 0x00000000,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - xorcc gr7,gr8,gr8,icc0 - test_icc 0 1 0 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_icc 0x0b,0 ; Set mask opposite of expected - xorcc gr7,gr8,gr8,icc0 - test_icc 0 1 1 1 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_gr_limmed 0x0000,0xbeef,gr8 - set_icc 0x05,0 ; Set mask opposite of expected - xorcc gr7,gr8,gr8,icc0 - test_icc 1 0 0 1 icc0 - test_gr_limmed 0xdead,0xbeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/xorcr.cgs b/sim/testsuite/sim/frv/xorcr.cgs deleted file mode 100644 index bcb153bc97f..00000000000 --- a/sim/testsuite/sim/frv/xorcr.cgs +++ /dev/null @@ -1,59 +0,0 @@ -# frv testcase for xorcr $CCi,$CCj,$CCk -# mach: all - - .include "testutils.inc" - - start - - .global xorcr -xorcr: - set_spr_immed 0x1b1b,cccr - xorcr cc7,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - xorcr cc7,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - xorcr cc7,cc5,cc3 - test_spr_immed 0x1b1b,cccr - - xorcr cc7,cc4,cc3 - test_spr_immed 0x1b1b,cccr - - xorcr cc6,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - xorcr cc6,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - xorcr cc6,cc5,cc3 - test_spr_immed 0x1b1b,cccr - - xorcr cc6,cc4,cc3 - test_spr_immed 0x1b1b,cccr - - xorcr cc5,cc7,cc3 - test_spr_immed 0x1b1b,cccr - - xorcr cc5,cc6,cc3 - test_spr_immed 0x1b1b,cccr - - xorcr cc5,cc5,cc3 - test_spr_immed 0x1b9b,cccr - - xorcr cc5,cc4,cc3 - test_spr_immed 0x1bdb,cccr - - xorcr cc4,cc7,cc3 - test_spr_immed 0x1bdb,cccr - - xorcr cc4,cc6,cc3 - test_spr_immed 0x1bdb,cccr - - xorcr cc4,cc5,cc3 - test_spr_immed 0x1bdb,cccr - - xorcr cc4,cc4,cc3 - test_spr_immed 0x1b9b,cccr - - pass diff --git a/sim/testsuite/sim/frv/xori.cgs b/sim/testsuite/sim/frv/xori.cgs deleted file mode 100644 index ed26660faf8..00000000000 --- a/sim/testsuite/sim/frv/xori.cgs +++ /dev/null @@ -1,35 +0,0 @@ -# frv testcase for xori $GRi,$s12,$GRk -# mach: all - - .include "testutils.inc" - - start - - .global xori -xori: - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_icc 0x07,0 ; Set mask opposite of expected - xori gr7,0x555,gr8 - test_icc 0 1 1 1 icc0 - test_gr_limmed 0xaaaa,0xafff,gr8 - - set_gr_immed 0x00000000,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - xori gr7,0,gr8 - test_icc 1 0 0 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_icc 0x0b,0 ; Set mask opposite of expected - xori gr7,0x2aa,gr8 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0xaaaa,0xa800,gr8 - - set_gr_limmed 0xdead,0x0000,gr7 - set_icc 0x05,0 ; Set mask opposite of expected - xori gr7,-273,gr8 - test_icc 0 1 0 1 icc0 - test_gr_limmed 0x2152,0xfeef,gr8 - - pass diff --git a/sim/testsuite/sim/frv/xoricc.cgs b/sim/testsuite/sim/frv/xoricc.cgs deleted file mode 100644 index b473620bbf1..00000000000 --- a/sim/testsuite/sim/frv/xoricc.cgs +++ /dev/null @@ -1,36 +0,0 @@ -# frv testcase for xoricc $GRi,$s10,$GRk,$ICCi_1 -# mach: all - - .include "testutils.inc" - - start - - .global xoricc -xoricc: - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_icc 0x07,0 ; Set mask opposite of expected - xoricc gr7,0x155,gr8,icc0 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0xaaaa,0xabff,gr8 - - set_gr_immed 0x00000000,gr7 - set_gr_immed 0x00000000,gr8 - set_icc 0x08,0 ; Set mask opposite of expected - xoricc gr7,0,gr8,icc0 - test_icc 0 1 0 0 icc0 - test_gr_immed 0x00000000,gr8 - - set_gr_limmed 0xaaaa,0xaaaa,gr7 - set_gr_limmed 0xaaaa,0xaaaa,gr8 - set_icc 0x07,0 ; Set mask opposite of expected - xoricc gr7,0xaa,gr8,icc0 - test_icc 1 0 1 1 icc0 - test_gr_limmed 0xaaaa,0xaa00,gr8 - - set_gr_limmed 0xdead,0xb000,gr7 - set_icc 0x0d,0 ; Set mask opposite of expected - xoricc gr7,-273,gr8,icc0 - test_icc 0 0 0 1 icc0 - test_gr_limmed 0x2152,0x4eef,gr8 - - pass diff --git a/sim/testsuite/sim/mips/ChangeLog b/sim/testsuite/sim/mips/ChangeLog deleted file mode 100644 index 67e7bfa2fe2..00000000000 --- a/sim/testsuite/sim/mips/ChangeLog +++ /dev/null @@ -1,5 +0,0 @@ -2004-01-26 Chris Demetriou - - * basic.exp: New file. - * testutils.inc: New file. - * sanity.s: New file. diff --git a/sim/testsuite/sim/mips/basic.exp b/sim/testsuite/sim/mips/basic.exp deleted file mode 100644 index 63dc086f525..00000000000 --- a/sim/testsuite/sim/mips/basic.exp +++ /dev/null @@ -1,26 +0,0 @@ -# MIPS simulator instruction tests - -# As gross as it is, we unset the linker script specifid by the target -# board. The MIPS libgloss linker scripts include libgcc (and possibly -# other libraries), which the linker (used to link these tests rather -# than the compiler) can't necessarily find. -unset_currtarget_info ldscript - -# Only test mips*-elf (e.g., no mips-linux), and only test if the target -# board really is a simulator (sim tests don't work on real HW). -if {[istarget mips*-elf] && [board_info target exists is_simulator]} { - - if {[istarget mipsisa64*-elf]} { - set models "mips1 mips2 mips3 mips4 mips32 mips64" - } elseif {[istarget mipsisa32*-elf]} { - set models "mips1 mips2 mips32" - } elseif {[istarget mips64*-elf]} { - set models "mips1 mips2 mips3" - } else { - # fall back to just testing mips1 code. - set models "mips1" - } - set cpu_option -march - - run_sim_test sanity.s $models -} diff --git a/sim/testsuite/sim/mips/sanity.s b/sim/testsuite/sim/mips/sanity.s deleted file mode 100644 index 74551edd404..00000000000 --- a/sim/testsuite/sim/mips/sanity.s +++ /dev/null @@ -1,20 +0,0 @@ -# mips test sanity, expected to pass. -# mach: all -# as: -mabi=eabi -# ld: -N -Ttext=0x80010000 -# output: *\\npass\\n - - .include "testutils.inc" - - setup - - .set noreorder - - .ent DIAG -DIAG: - - writemsg "Sanity is good!" - - pass - - .end DIAG diff --git a/sim/testsuite/sim/mips/testutils.inc b/sim/testsuite/sim/mips/testutils.inc deleted file mode 100644 index f111f793140..00000000000 --- a/sim/testsuite/sim/mips/testutils.inc +++ /dev/null @@ -1,149 +0,0 @@ -# MIPS simulator testsuite utility functions. -# Copyright (C) 2004 Free Software Foundation, Inc. -# Contributed by Chris Demetriou of Broadcom Corporation. -# -# This file is part of the GNU simulators. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - - -# $1, $4, $5, %6, are used as temps by the macros defined here. - - .macro writemsg msg - .data -901: .ascii "\msg\n" -902: - .previous - la $5, 901b - li $6, 902b - 901b - .set push - .set noreorder - jal _dowrite - li $4, 0 - .set pop - .endm - - - # The MIPS simulator uses "break 0x3ff" as the code to exit, - # with the return value in $4 (a0). - .macro exit rc - li $4, \rc - break 0x3ff - .endm - - - .macro setup - - .global _start - .ent _start -_start: - .set push - .set noreorder - j DIAG - nop - .set pop - .end _start - - .global _fail - .ent _fail -_fail: - writemsg "fail" - exit 1 - .end _fail - - .global _pass - .ent _pass -_pass: - writemsg "pass" - exit 0 - .end _pass - - # The MIPS simulator can use multiple different monitor types, - # so we hard-code the simulator "write" reserved instruction opcode, - # rather than jumping to a vector that invokes it. The operation - # expects RA to point to the location at which to continue - # after writing. - .global _dowrite - .ent _dowrite -_dowrite: - # Write opcode (reserved instruction). See sim_monitor and its - # callers in sim/mips/interp.c. - .word 0x00000005 | ((8 << 1) << 6) - .end _dowrite - - .endm # setup - - - .macro pass - .set push - .set noreorder - j _pass - nop - .set pop - .endm - - - .macro fail - .set push - .set noreorder - j _fail - nop - .set pop - .endm - - - .macro load32 reg, val - li \reg, \val - .endm - - - .macro load64 reg, val - dli \reg, \val - .endm - - - .macro loadaddr reg, addr - la \reg, \addr - .endm - - - .macro checkreg reg, expreg - .set push - .set noat - .set noreorder - beq \expreg, \reg, 901f - nop - fail -901: - .set pop - .endm - - - .macro check32 reg, val - .set push - .set noat - load32 $1, \val - checkreg \reg, $1 - .set pop - .endm - - - .macro check64 reg, val - .set push - .set noat - load64 $1, \val - checkreg \reg, $1 - .set pop - .endm diff --git a/sim/testsuite/sim/sh/ChangeLog b/sim/testsuite/sim/sh/ChangeLog deleted file mode 100644 index e3fecbd3a15..00000000000 --- a/sim/testsuite/sim/sh/ChangeLog +++ /dev/null @@ -1,47 +0,0 @@ -2004-02-12 Michael Snyder - - * and.s, movi.s, sett.s: New files. - * allinsn.exp: Add new tests. - * testutils.inc (set_sr_bit): Fix macro labels. - -2004-01-07 Michael Snyder - - * dmxy.s, fipr.s, fpchg.s, ldrc.s, loop.s, movli.s, movua.s, - movxy.s, pabs.s, pclr.s, prnd.s, psub.s, pswap.s: New files. - * allinsn.exp: Add new tests. - * testutils.inc (set_sr_bit): Add argument. - (set_greg): Add .align directives. - -2003-08-11 Michael Snyder - - * macl.s: New file. - * macw.s: New file. - * allinsn.exp: Add new tests for mac.w and mac.l. - -2003-07-25 Michael Snyder - - * pshai.s, pshar.s, pshli.s, pshlr.s: New files. - * allinsn.exp: Add psha, pshl tests. - * pdec.s, pinc.s, padd.s, paddc.s: New files. - * allinsn.exp: Add pdec, pinc, padd, paddc tests. - * pand.s, pdmsb.s: New files. - * allinsn.exp: Add pand, pdmsb tests. - -2003-07-23 Michael Snyder - - * pmuls.s: New file. - -2003-07-08 Michael Snyder - - * allinsn.exp, testutils.inc, add.s, fabs.s, fadd.s, fcmpeq.s, - fcmpgt.s, fcnvds.s, fcnvsd.s, fdiv.s, fldi0.s, fldi1.s, flds.s, - float.s, fmac.s, fmov.s, fmul.s, fneg.s, frchg.s, fschg.s, - fsqrt.s, fsub.s, ftrc.s, shll16.s, shll2.s, shll8.s, shll.s, - shlr16.s, shlr2.s, shlr8.s, shlr.s, swap.s: New files. - -Local Variables: -mode: change-log -left-margin: 8 -fill-column: 74 -version-control: never -End: diff --git a/sim/testsuite/sim/sh/add.s b/sim/testsuite/sim/sh/add.s deleted file mode 100644 index 95192518a84..00000000000 --- a/sim/testsuite/sim/sh/add.s +++ /dev/null @@ -1,86 +0,0 @@ -# sh testcase for add -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - .align 2 -_x: .long 1 -_y: .long 1 - - start - -add_reg_reg_direct: - set_grs_a5a5 - mov.l i, r1 - mov.l j, r2 - add r1, r2 - test_gr0_a5a5 - assertreg 2 r1 - assertreg 4 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - -add_reg_reg_indirect: - set_grs_a5a5 - mov.l x, r1 - mov.l y, r2 - mov.l @r1, r1 - mov.l @r2, r2 - add r1, r2 - test_gr0_a5a5 - assertreg 1 r1 - assertreg 2 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - -add_imm_reg: - set_grs_a5a5 - add #0x16, r1 - test_gr0_a5a5 - assertreg 0xa5a5a5bb r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - pass - - exit 0 - - .align 2 -x: .long _x -y: .long _y -i: .long 2 -j: .long 2 - diff --git a/sim/testsuite/sim/sh/allinsn.exp b/sim/testsuite/sim/sh/allinsn.exp deleted file mode 100644 index 0ec39f580a8..00000000000 --- a/sim/testsuite/sim/sh/allinsn.exp +++ /dev/null @@ -1,65 +0,0 @@ -# sh tests - -set all "sh shdsp" - -if [istarget sh-*elf] { - run_sim_test add.s $all - run_sim_test and.s $all - run_sim_test dmxy.s shdsp - run_sim_test fabs.s sh - run_sim_test fadd.s sh - run_sim_test fcmpeq.s sh - run_sim_test fcmpgt.s sh - run_sim_test fcnvds.s sh - run_sim_test fcnvsd.s sh - run_sim_test fdiv.s sh - run_sim_test fipr.s sh - run_sim_test fldi0.s sh - run_sim_test fldi1.s sh - run_sim_test flds.s sh - run_sim_test float.s sh - run_sim_test fmac.s sh - run_sim_test fmov.s sh - run_sim_test fmul.s sh - run_sim_test fneg.s sh - run_sim_test fpchg.s sh - run_sim_test frchg.s sh - run_sim_test fschg.s sh - run_sim_test fsqrt.s sh - run_sim_test fsub.s sh - run_sim_test ftrc.s sh - run_sim_test ldrc.s shdsp - run_sim_test loop.s shdsp - run_sim_test macl.s sh - run_sim_test macw.s sh - run_sim_test movi.s $all - run_sim_test movli.s $all - run_sim_test movua.s $all - run_sim_test movxy.s shdsp - run_sim_test pabs.s shdsp - run_sim_test paddc.s shdsp - run_sim_test padd.s shdsp - run_sim_test pand.s shdsp - run_sim_test pclr.s shdsp - run_sim_test pdec.s shdsp - run_sim_test pdmsb.s shdsp - run_sim_test pinc.s shdsp - run_sim_test pmuls.s shdsp - run_sim_test prnd.s shdsp - run_sim_test pshai.s shdsp - run_sim_test pshar.s shdsp - run_sim_test pshli.s shdsp - run_sim_test pshlr.s shdsp - run_sim_test psub.s shdsp - run_sim_test pswap.s shdsp - run_sim_test sett.s $all - run_sim_test shll.s $all - run_sim_test shll2.s $all - run_sim_test shll8.s $all - run_sim_test shll16.s $all - run_sim_test shlr.s $all - run_sim_test shlr2.s $all - run_sim_test shlr8.s $all - run_sim_test shlr16.s $all - run_sim_test swap.s $all -} diff --git a/sim/testsuite/sim/sh/and.s b/sim/testsuite/sim/sh/and.s deleted file mode 100644 index 00934473f97..00000000000 --- a/sim/testsuite/sim/sh/and.s +++ /dev/null @@ -1,89 +0,0 @@ -# sh testcase for and -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - .align 2 -_x: .long 0xa5a5a5a5 -_y: .long 0x55555555 - - start - -and_reg_reg_direct: - set_grs_a5a5 - mov.l i, r1 - mov.l j, r2 - and r1, r2 - test_gr0_a5a5 - assertreg 0xa5a5a5a5 r1 - assertreg 0xa0a0a0a0 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - bra and_imm_reg - nop - - .align 2 -i: .long 0xa5a5a5a5 -j: .long 0xaaaaaaaa - -and_imm_reg: - set_grs_a5a5 - and #0xff, r0 - assertreg 0xa5, r0 - test_gr_a5a5 r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - -and_b_imm_ind: - set_grs_a5a5 - mov.l x, r0 - and.b #0x55, @(r0, GBR) - mov.l @r0, r0 - - assertreg 0xa5a5a505, r0 - test_gr_a5a5 r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - pass - - exit 0 - - .align 2 -x: .long _x -y: .long _y - diff --git a/sim/testsuite/sim/sh/dmxy.s b/sim/testsuite/sim/sh/dmxy.s deleted file mode 100644 index 0e96963aee9..00000000000 --- a/sim/testsuite/sim/sh/dmxy.s +++ /dev/null @@ -1,21 +0,0 @@ -# sh testcase for setdmx, setdmy, clrdmxy -# mach: shdsp -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - set_grs_a5a5 - setdmx - test_sr_bit_set 0x400 - test_sr_bit_clear 0x800 - setdmy - test_sr_bit_clear 0x400 - test_sr_bit_set 0x800 - clrdmxy - test_sr_bit_clear 0x400 - test_sr_bit_clear 0x800 - - test_grs_a5a5 - pass - exit 0 diff --git a/sim/testsuite/sim/sh/fabs.s b/sim/testsuite/sim/sh/fabs.s deleted file mode 100644 index 1fb354e5922..00000000000 --- a/sim/testsuite/sim/sh/fabs.s +++ /dev/null @@ -1,115 +0,0 @@ -# sh testcase for fabs -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start -fabs_freg_b0: - single_prec - bank0 - set_grs_a5a5 - set_fprs_a5a5 - # fabs(0.0) = 0.0. - fldi0 fr0 - fabs fr0 - fldi0 fr1 - fcmp/eq fr0, fr1 - bt .L1 - fail -.L1: - # fabs(1.0) = 1.0. - fldi1 fr0 - fabs fr0 - fldi1 fr1 - fcmp/eq fr0, fr1 - bt .L2 - fail -.L2: - # fabs(-1.0) = 1.0. - fldi1 fr0 - fneg fr0 - fabs fr0 - fldi1 fr1 - fcmp/eq fr0, fr1 - bt .L3 - fail -.L3: - test_grs_a5a5 - test_fpr_a5a5 fr2 - test_fpr_a5a5 fr3 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - -fabs_dreg_b0: - # double precision tests. - set_grs_a5a5 - set_fprs_a5a5 - double_prec - # fabs(0.0) = 0.0. - fldi0 fr0 - flds fr0, fpul - fcnvsd fpul, dr0 - fabs dr0 - assert_dpreg_i 0 dr0 - - # fabs(1.0) = 1.0. - fldi1 fr0 - flds fr0, fpul - fcnvsd fpul, dr0 - fabs dr0 - assert_dpreg_i 1 dr0 - - # check. - fldi1 fr2 - flds fr2, fpul - fcnvsd fpul, dr2 - fcmp/eq dr0, dr2 - bt .L4 - fail - -.L4: - # fabs(-1.0) = 1.0. - fldi1 fr0 - fneg fr0 - flds fr0, fpul - fcnvsd fpul, dr0 - fabs dr0 - assert_dpreg_i 1 dr0 - - # check. - fldi1 fr2 - flds fr2, fpul - fcnvsd fpul, dr2 - fcmp/eq dr0, dr2 - bt .L5 - fail -.L5: - test_grs_a5a5 - assert_dpreg_i 1 dr0 - assert_dpreg_i 1 dr2 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/fadd.s b/sim/testsuite/sim/sh/fadd.s deleted file mode 100644 index 72431f0f871..00000000000 --- a/sim/testsuite/sim/sh/fadd.s +++ /dev/null @@ -1,75 +0,0 @@ -# sh testcase for fadd -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start -fadd_freg_freg_b0: - set_grs_a5a5 - set_fprs_a5a5 - bank0 - - fldi1 fr0 - fldi1 fr1 - fadd fr0, fr1 - assert_fpreg_i 2 fr1 - - fldi0 fr0 - fldi1 fr1 - fadd fr0, fr1 - assert_fpreg_i 1 fr1 - - fldi1 fr0 - fldi0 fr1 - fadd fr0, fr1 - assert_fpreg_i 1 fr1 - test_grs_a5a5 - assert_fpreg_i 1 fr0 - test_fpr_a5a5 fr2 - test_fpr_a5a5 fr3 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - -fadd_dreg_dreg_b0: - set_grs_a5a5 - set_fprs_a5a5 - double_prec - fldi1 fr0 - fldi1 fr2 - flds fr0, fpul - fcnvsd fpul, dr0 - flds fr2, fpul - fcnvsd fpul, dr2 - fadd dr0, dr2 - fcnvds dr2, fpul - fsts fpul, fr0 - - test_grs_a5a5 - assert_fpreg_i 2, fr0 - assert_dpreg_i 2, dr2 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/fcmpeq.s b/sim/testsuite/sim/sh/fcmpeq.s deleted file mode 100644 index 9c0ef57298e..00000000000 --- a/sim/testsuite/sim/sh/fcmpeq.s +++ /dev/null @@ -1,119 +0,0 @@ -# sh testcase for fcmpeq -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start -fcmpeq_single: - set_grs_a5a5 - set_fprs_a5a5 - # 1.0 == 1.0. - fldi1 fr0 - fldi1 fr1 - fcmp/eq fr0, fr1 - bt .L0 - fail -.L0: - # 0.0 != 1.0. - fldi0 fr0 - fldi1 fr1 - fcmp/eq fr0, fr1 - bf .L1 - fail -.L1: - # 1.0 != 0.0. - fldi1 fr0 - fldi0 fr1 - fcmp/eq fr0, fr1 - bf .L2 - fail -.L2: - # 2.0 != 1.0 - fldi1 fr0 - fadd fr0, fr0 - fldi1 fr1 - fcmp/eq fr0, fr1 - bf .L3 - fail -.L3: - test_grs_a5a5 - assert_fpreg_i 2, fr0 - assert_fpreg_i 1, fr1 - test_fpr_a5a5 fr2 - test_fpr_a5a5 fr3 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - -fcmpeq_double: - # 1.0 == 1.0 - set_grs_a5a5 - set_fprs_a5a5 - double_prec - fldi1 fr0 - fldi1 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - fcmp/eq dr0, dr2 - bt .L10 - fail -.L10: - # 0.0 != 1.0 - fldi0 fr0 - fldi1 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - fcmp/eq dr0, dr2 - bf .L11 - fail -.L11: - # 1.0 != 0.0 - fldi1 fr0 - fldi0 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - fcmp/eq dr0, dr2 - bf .L12 - fail -.L12: - # 2.0 != 1.0 - fldi1 fr0 - single_prec - fadd fr0, fr0 - double_prec - fldi1 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - fcmp/eq dr0, dr2 - bf .L13 - fail -.L13: - test_grs_a5a5 - assert_dpreg_i 2, dr0 - assert_dpreg_i 1, dr2 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - - pass - exit 0 - diff --git a/sim/testsuite/sim/sh/fcmpgt.s b/sim/testsuite/sim/sh/fcmpgt.s deleted file mode 100644 index c6945bae377..00000000000 --- a/sim/testsuite/sim/sh/fcmpgt.s +++ /dev/null @@ -1,119 +0,0 @@ -# sh testcase for fcmpgt -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start -fcmpgt_single: - set_grs_a5a5 - set_fprs_a5a5 - # 1.0 !> 1.0. - fldi1 fr0 - fldi1 fr1 - fcmp/gt fr0, fr1 - bf .L0 - fail -.L0: - # 0.0 !> 1.0. - fldi0 fr0 - fldi1 fr1 - fcmp/gt fr0, fr1 - bt .L1 - fail -.L1: - # 1.0 > 0.0. - fldi1 fr0 - fldi0 fr1 - fcmp/gt fr0, fr1 - bf .L2 - fail -.L2: - # 2.0 > 1.0 - fldi1 fr0 - fadd fr0, fr0 - fldi1 fr1 - fcmp/gt fr0, fr1 - bf .L3 - fail -.L3: - test_grs_a5a5 - assert_fpreg_i 2, fr0 - assert_fpreg_i 1, fr1 - test_fpr_a5a5 fr2 - test_fpr_a5a5 fr3 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - -fcmpgt_double: - # double precision tests. - set_grs_a5a5 - set_fprs_a5a5 - double_prec - # 1.0 !> 1.0. - fldi1 fr0 - fldi1 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - fcmp/gt dr0, dr2 - bf .L10 - fail -.L10: - # 0.0 !> 1.0. - fldi0 fr0 - fldi1 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - fcmp/gt dr0, dr2 - bt .L11 - fail -.L11: - # 1.0 > 0.0. - fldi1 fr0 - fldi0 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - fcmp/gt dr0, dr2 - bf .L12 - fail -.L12: - # 2.0 > 1.0. - fldi1 fr0 - single_prec - fadd fr0, fr0 - double_prec - fldi1 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - fcmp/gt dr0, dr2 - bf .L13 - fail -.L13: - test_grs_a5a5 - assert_dpreg_i 2, dr0 - assert_dpreg_i 1, dr2 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/fcnvds.s b/sim/testsuite/sim/sh/fcnvds.s deleted file mode 100644 index cffcb4940b8..00000000000 --- a/sim/testsuite/sim/sh/fcnvds.s +++ /dev/null @@ -1,56 +0,0 @@ -# sh testcase for fcnvds -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start - double_prec - sz_64 - set_grs_a5a5 - set_fprs_a5a5 - mov.l ax, r0 - fmov @r0, dr0 - fcnvds dr0, fpul - fsts fpul, fr2 - - assert_dpreg_i 5, dr0 - single_prec - assert_fpreg_i 5, fr2 - test_fpr_a5a5 fr3 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - - assertreg0 x - test_gr_a5a5 r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - pass - exit 0 - - .align 2 -x: .double 5.0 -ax: .long x - diff --git a/sim/testsuite/sim/sh/fcnvsd.s b/sim/testsuite/sim/sh/fcnvsd.s deleted file mode 100644 index 6592540e4f1..00000000000 --- a/sim/testsuite/sim/sh/fcnvsd.s +++ /dev/null @@ -1,40 +0,0 @@ -# sh testcase for fcnvsd -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start - set_grs_a5a5 - set_fprs_a5a5 - double_prec - fldi1 fr0 - flds fr0, fpul - fcnvsd fpul, dr2 - assert_dpreg_i 1, dr2 - - # Convert back. - fcnvds dr2, fpul - fsts fpul, fr1 - single_prec - assert_fpreg_i 1, fr1 - fcmp/eq fr0, fr1 - bt .L0 - fail -.L0: - test_grs_a5a5 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - pass - exit 0 - diff --git a/sim/testsuite/sim/sh/fdiv.s b/sim/testsuite/sim/sh/fdiv.s deleted file mode 100644 index 629e774bd67..00000000000 --- a/sim/testsuite/sim/sh/fdiv.s +++ /dev/null @@ -1,91 +0,0 @@ -# sh testcase for fdiv -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start -fdiv_single: - # Single test - set_grs_a5a5 - set_fprs_a5a5 - single_prec - # 1.0 / 0.0 should be INF - # (and not crash the sim). - fldi0 fr0 - fldi1 fr1 - fdiv fr0, fr1 - assert_fpreg_x 0x7f800000, fr1 - - # 0.0 / 1.0 == 0.0. - fldi0 fr0 - fldi1 fr1 - fdiv fr1, fr0 - assert_fpreg_x 0, fr0 - - # 2.0 / 1.0 == 2.0. - fldi1 fr1 - fldi1 fr2 - fadd fr2, fr2 - fdiv fr1, fr2 - assert_fpreg_i 2, fr2 - - # (1.0 / 2.0) + (1.0 / 2.0) == 1.0. - fldi1 fr1 - fldi1 fr2 - fadd fr2, fr2 - fdiv fr2, fr1 - # fr1 should contain 0.5. - fadd fr1, fr1 - assert_fpreg_i 1, fr1 - test_grs_a5a5 - assert_fpreg_i 2, fr2 - test_fpr_a5a5 fr3 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - -fdiv_double: - # Double test - set_grs_a5a5 - set_fprs_a5a5 - # (1.0 / 2.0) + (1.0 / 2.0) == 1.0. - fldi1 fr1 - fldi1 fr2 - # This add must be in single precision. The rest must be in double. - fadd fr2, fr2 - double_prec - _s2d fr1, dr0 - _s2d fr2, dr2 - fdiv dr2, dr0 - # dr0 should contain 0.5. - # double it, expect 1.0. - fadd dr0, dr0 - assert_dpreg_i 1, dr0 - assert_dpreg_i 2, dr2 - test_grs_a5a5 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - - pass - exit 0 - diff --git a/sim/testsuite/sim/sh/fipr.s b/sim/testsuite/sim/sh/fipr.s deleted file mode 100644 index 6a949aa6ec7..00000000000 --- a/sim/testsuite/sim/sh/fipr.s +++ /dev/null @@ -1,137 +0,0 @@ -# sh testcase for fipr $fvm, $fvn -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start -initv0: - set_grs_a5a5 - set_fprs_a5a5 - # Load 1 into fr0. - fldi1 fr0 - # Load 2 into fr1. - fldi1 fr1 - fadd fr1, fr1 - # Load 4 into fr2. - fldi1 fr2 - fadd fr2, fr2 - fadd fr2, fr2 - # Load 8 into fr3. - fmov fr2, fr3 - fadd fr2, fr3 - -initv8: - fldi1 fr8 - fldi0 fr9 - fldi1 fr10 - fldi0 fr11 - - fipr fv0, fv8 -test1: - # Result will be in fr11. - assert_fpreg_i 1, fr0 - assert_fpreg_i 2, fr1 - assert_fpreg_i 4, fr2 - assert_fpreg_i 8, fr3 - assert_fpreg_x 0xa5a5a5a5, fr4 - assert_fpreg_x 0xa5a5a5a5, fr5 - assert_fpreg_x 0xa5a5a5a5, fr6 - assert_fpreg_x 0xa5a5a5a5, fr7 - assert_fpreg_i 1, fr8 - assert_fpreg_i 0, fr9 - assert_fpreg_i 1, fr10 - assert_fpreg_i 5, fr11 - assert_fpreg_x 0xa5a5a5a5, fr12 - assert_fpreg_x 0xa5a5a5a5, fr13 - assert_fpreg_x 0xa5a5a5a5, fr14 - assert_fpreg_x 0xa5a5a5a5, fr15 - - test_grs_a5a5 -test_infp: - # Test positive infinity - fldi0 fr11 - mov.l infp, r0 - lds r0, fpul - fsts fpul, fr0 - fipr fv0, fv8 - # fr11 should be plus infinity - assert_fpreg_x 0x7f800000, fr11 -test_infm: - # Test negitive infinity - fldi0 fr11 - mov.l infm, r0 - lds r0, fpul - fsts fpul, fr0 - fipr fv0, fv8 - # fr11 should be plus infinity - assert_fpreg_x 0xff800000, fr11 -test_qnanp: - # Test positive qnan - fldi0 fr11 - mov.l qnanp, r0 - lds r0, fpul - fsts fpul, fr0 - fipr fv0, fv8 - # fr11 should be plus qnan (or greater) - flds fr11, fpul - sts fpul, r1 - cmp/ge r0, r1 - bt .L0 - fail -.L0: -test_snanp: - # Test positive snan - fldi0 fr11 - mov.l snanp, r0 - lds r0, fpul - fsts fpul, fr0 - fipr fv0, fv8 - # fr11 should be plus snan (or greater) - flds fr11, fpul - sts fpul, r1 - cmp/ge r0, r1 - bt .L1 - fail -.L1: -.if 0 - # Handling of nan and inf not implemented yet. -test_qnanm: - # Test negantive qnan - fldi0 fr11 - mov.l qnanm, r0 - lds r0, fpul - fsts fpul, fr0 - fipr fv0, fv8 - # fr11 should be minus qnan (or less) - flds fr11, fpul - sts fpul, r1 - cmp/ge r1, r0 - bt .L2 - fail -.L2: -test_snanm: - # Test negative snan - fldi0 fr11 - mov.l snanm, r0 - lds r0, fpul - fsts fpul, fr0 - fipr fv0, fv8 - # fr11 should be minus snan (or less) - flds fr11, fpul - sts fpul, r1 - cmp/ge r1, r0 - bt .L3 - fail -.L3: -.endif - pass - exit 0 - - .align 2 -qnanp: .long 0x7f800001 -qnanm: .long 0xff800001 -snanp: .long 0x7fc00000 -snanm: .long 0xffc00000 -infp: .long 0x7f800000 -infm: .long 0xff800000 diff --git a/sim/testsuite/sim/sh/fldi0.s b/sim/testsuite/sim/sh/fldi0.s deleted file mode 100644 index 1e2005832b0..00000000000 --- a/sim/testsuite/sim/sh/fldi0.s +++ /dev/null @@ -1,37 +0,0 @@ -# sh testcase for fldi0 $frn -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start -fldi0_single: - set_grs_a5a5 - set_fprs_a5a5 - fldi0 fr0 - fldi0 fr2 - fldi0 fr4 - fldi0 fr6 - fldi0 fr8 - fldi0 fr10 - fldi0 fr12 - fldi0 fr14 - test_grs_a5a5 - assert_fpreg_i 0 fr0 - assert_fpreg_i 0 fr2 - assert_fpreg_i 0 fr4 - assert_fpreg_i 0 fr6 - assert_fpreg_i 0 fr8 - assert_fpreg_i 0 fr10 - assert_fpreg_i 0 fr12 - assert_fpreg_i 0 fr14 - assert_fpreg_x 0xa5a5a5a5 fr1 - assert_fpreg_x 0xa5a5a5a5 fr3 - assert_fpreg_x 0xa5a5a5a5 fr5 - assert_fpreg_x 0xa5a5a5a5 fr7 - assert_fpreg_x 0xa5a5a5a5 fr9 - assert_fpreg_x 0xa5a5a5a5 fr11 - assert_fpreg_x 0xa5a5a5a5 fr13 - assert_fpreg_x 0xa5a5a5a5 fr15 - pass - exit 0 diff --git a/sim/testsuite/sim/sh/fldi1.s b/sim/testsuite/sim/sh/fldi1.s deleted file mode 100644 index 1b7c1701c7d..00000000000 --- a/sim/testsuite/sim/sh/fldi1.s +++ /dev/null @@ -1,38 +0,0 @@ -# sh testcase for fldi1 $frn -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start -fldi1_single: - set_grs_a5a5 - set_fprs_a5a5 - fldi1 fr1 - fldi1 fr3 - fldi1 fr5 - fldi1 fr7 - fldi1 fr9 - fldi1 fr11 - fldi1 fr13 - fldi1 fr15 - test_grs_a5a5 - assert_fpreg_x 0xa5a5a5a5 fr0 - assert_fpreg_x 0xa5a5a5a5 fr2 - assert_fpreg_x 0xa5a5a5a5 fr4 - assert_fpreg_x 0xa5a5a5a5 fr6 - assert_fpreg_x 0xa5a5a5a5 fr8 - assert_fpreg_x 0xa5a5a5a5 fr10 - assert_fpreg_x 0xa5a5a5a5 fr12 - assert_fpreg_x 0xa5a5a5a5 fr14 - assert_fpreg_i 1 fr1 - assert_fpreg_i 1 fr3 - assert_fpreg_i 1 fr5 - assert_fpreg_i 1 fr7 - assert_fpreg_i 1 fr9 - assert_fpreg_i 1 fr11 - assert_fpreg_i 1 fr13 - assert_fpreg_i 1 fr15 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/flds.s b/sim/testsuite/sim/sh/flds.s deleted file mode 100644 index 086b4edf057..00000000000 --- a/sim/testsuite/sim/sh/flds.s +++ /dev/null @@ -1,43 +0,0 @@ -# sh testcase for flds -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start -flds_zero: - set_grs_a5a5 - set_fprs_a5a5 - fldi0 fr0 - flds fr0, fpul - fsts fpul, fr1 - fcmp/eq fr0, fr1 - bt flds_one - fail -flds_one: - fldi1 fr0 - flds fr0, fpul - fsts fpul, fr1 - fcmp/eq fr0, fr1 - bt .L0 - fail -.L0: - test_grs_a5a5 - assert_fpreg_i 1, fr0 - assert_fpreg_i 1, fr1 - test_fpr_a5a5 fr2 - test_fpr_a5a5 fr3 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - pass - exit 0 diff --git a/sim/testsuite/sim/sh/float.s b/sim/testsuite/sim/sh/float.s deleted file mode 100644 index e5a3bc6dbfc..00000000000 --- a/sim/testsuite/sim/sh/float.s +++ /dev/null @@ -1,149 +0,0 @@ -# sh testcase for float -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start - -float_pos: - set_grs_a5a5 - set_fprs_a5a5 - single_prec - mov #3, r0 - lds r0, fpul - float fpul, fr2 - - # Check the result. - fldi1 fr0 - fldi1 fr1 - fadd fr0, fr1 - fadd fr0, fr1 - fcmp/eq fr1, fr2 - bt float_neg - fail - -float_neg: - mov #3, r0 - neg r0, r0 - lds r0, fpul - float fpul, fr2 - - # Check the result. - fldi1 fr0 - fldi1 fr1 - fadd fr0, fr1 - fadd fr0, fr1 - fneg fr1 - fcmp/eq fr1, fr2 - bt .L0 - fail -.L0: - assertreg0 -3 - test_gr_a5a5 r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - assert_fpreg_i 1, fr0 - assert_fpreg_i -3, fr1 - assert_fpreg_i -3, fr2 - test_fpr_a5a5 fr3 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - -double_pos: - set_grs_a5a5 - set_fprs_a5a5 - double_prec - mov #3, r0 - lds r0, fpul - float fpul, dr4 - - # check the result. - fldi1 fr0 - fldi1 fr1 - single_prec - fadd fr0, fr1 - fadd fr0, fr1 - double_prec - _s2d fr1, dr2 - fcmp/eq dr2, dr4 - bt double_neg - fail - -double_neg: - double_prec - mov #3, r0 - neg r0, r0 - lds r0, fpul - float fpul, dr4 - - # check the result. - fldi1 fr0 - fldi1 fr1 - single_prec - fadd fr0, fr1 - fadd fr0, fr1 - fneg fr1 - double_prec - _s2d fr1, dr2 - fcmp/eq dr2, dr4 - bt .L2 - fail -.L2: - assertreg0 -3 - test_gr_a5a5 r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - single_prec - assert_fpreg_i 1, fr0 - assert_fpreg_i -3, fr1 - double_prec - assert_dpreg_i -3, dr2 - assert_dpreg_i -3, dr4 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/fmac.s b/sim/testsuite/sim/sh/fmac.s deleted file mode 100644 index eba1da5f4d8..00000000000 --- a/sim/testsuite/sim/sh/fmac.s +++ /dev/null @@ -1,98 +0,0 @@ -# sh testcase for fmac -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start -fmac_: - set_grs_a5a5 - set_fprs_a5a5 - # 0.0 * x + y = y. - - fldi0 fr0 - fldi1 fr1 - fldi1 fr2 - fmac fr0, fr1, fr2 - # check result. - fldi1 fr0 - fcmp/eq fr0, fr2 - bt .L0 - fail -.L0: - # x * y + 0.0 = x * y. - - fldi1 fr0 - fldi1 fr1 - fldi0 fr2 - # double it. - fadd fr1, fr2 - fmac fr0, fr1, fr2 - # check result. - fldi1 fr0 - fadd fr0, fr0 - fcmp/eq fr0, fr2 - bt .L1 - fail -.L1: - # x * 0.0 + y = y. - - fldi1 fr0 - fldi0 fr1 - fldi1 fr2 - fadd fr2, fr2 - fmac fr0, fr1, fr2 - # check result. - fldi1 fr0 - # double fr0. - fadd fr0, fr0 - fcmp/eq fr0, fr2 - bt .L2 - fail -.L2: - # x * 0.0 + 0.0 = 0.0 - - fldi1 fr0 - fadd fr0, fr0 - fldi0 fr1 - fldi0 fr2 - fmac fr0, fr1, fr2 - # check result. - fldi0 fr0 - fcmp/eq fr0, fr2 - bt .L3 - fail -.L3: - # 0.0 * x + 0.0 = 0.0. - - fldi0 fr0 - fldi1 fr1 - # double it. - fadd fr1, fr1 - fldi0 fr2 - fmac fr0, fr1, fr2 - # check result. - fldi0 fr0 - fcmp/eq fr0, fr2 - bt .L4 - fail -.L4: - test_grs_a5a5 - assert_fpreg_i 0, fr0 - assert_fpreg_i 2, fr1 - assert_fpreg_i 0, fr2 - test_fpr_a5a5 fr3 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - pass - exit 0 diff --git a/sim/testsuite/sim/sh/fmov.s b/sim/testsuite/sim/sh/fmov.s deleted file mode 100644 index 29c51b5d1e5..00000000000 --- a/sim/testsuite/sim/sh/fmov.s +++ /dev/null @@ -1,322 +0,0 @@ -# sh testcase for all fmov instructions -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - .macro init - fldi0 fr0 - fldi1 fr1 - fldi1 fr2 - fldi1 fr3 - .endm - - start - -fmov1: # Test fr -> fr. - set_grs_a5a5 - set_fprs_a5a5 - init - single_prec - sz_32 - fmov fr0, fr1 - # Ensure fr0 and fr1 are now equal. - fcmp/eq fr0, fr1 - bt fmov2 - fail - -fmov2: # Test dr -> dr. - init - double_prec - sz_64 - fmov dr0, dr2 - # Ensure dr0 and dr2 are now equal. - fcmp/eq dr0, dr2 - bt fmov3 - fail - -fmov3: # Test dr -> xd and xd -> dr. - init - sz_64 - fmov dr0, xd0 - # Ensure dr0 and xd0 are now equal. - fmov xd0, dr2 - fcmp/eq dr0, dr2 - bt fmov4 - fail - -fmov4: # Test xd -> xd. - init - sz_64 - double_prec - fmov dr0, xd0 - fmov xd0, xd2 - fmov xd2, dr2 - # Ensure dr0 and dr2 are now equal. - fcmp/eq dr0, dr2 - bt .L0 - fail - - # FIXME: test fmov.s fr -> @gr, fmov dr -> @gr - # FIXME: test fmov.s @gr -> fr, fmov @gr -> dr - # FIXME: test fmov.s @gr+ -> fr, fmov @gr+ -> dr - # FIXME: test fmov.s fr -> @-gr, fmov dr -> @-gr - # FIXME: test fmov.s @(r0,gr) -> fr, fmov @(r0,gr) -> dr - # FIXME: test fmov.s fr -> @(r0,gr), fmov dr -> @(r0,gr) - -.L0: - test_grs_a5a5 - sz_32 - single_prec - assert_fpreg_i 0, fr0 - assert_fpreg_i 1, fr1 - assert_fpreg_i 0, fr2 - assert_fpreg_i 1, fr3 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - -fmov5: # Test fr -> @rn and @rn -> fr. - init - sz_32 - single_prec - # FIXME! Use a reserved memory location! - mov #40, r0 - shll8 r0 - fmov fr0, @r0 - fmov @r0, fr1 - fcmp/eq fr0, fr1 - bt fmov6 - fail - -fmov6: # Test dr -> @rn and @rn -> dr. - init - sz_64 - double_prec - mov #40, r0 - shll8 r0 - fmov dr0, @r0 - fmov @r0, dr2 - fcmp/eq dr0, dr2 - bt fmov7 - fail - -fmov7: # Test xd -> @rn and @rn -> xd. - init - sz_64 - double_prec - mov #40, r0 - shll8 r0 - fmov dr0, xd0 - fmov xd0, @r0 - fmov @r0, xd2 - fmov xd2, dr2 - fcmp/eq dr0, dr2 - bt fmov8 - fail - -fmov8: # Test fr -> @-rn. - init - sz_32 - single_prec - mov #40, r0 - shll8 r0 - # Preserve. - mov r0, r1 - fmov fr0, @-r0 - fmov @r0, fr2 - fcmp/eq fr0, fr2 - bt f8b - fail -f8b: # check pre-dec. - add #4, r0 - cmp/eq r0, r1 - bt fmov9 - fail - -fmov9: # Test dr -> @-rn. - init - sz_64 - double_prec - mov #40, r0 - shll8 r0 - # Preserve r0. - mov r0, r1 - fmov dr0, @-r0 - fmov @r0, dr2 - fcmp/eq dr0, dr2 - bt f9b - fail -f9b: # check pre-dec. - add #8, r0 - cmp/eq r0, r1 - bt fmov10 - fail - -fmov10: # Test xd -> @-rn. - init - sz_64 - double_prec - mov #40, r0 - shll8 r0 - # Preserve r0. - mov r0, r1 - fmov dr0, xd0 - fmov xd0, @-r0 - fmov @r0, xd2 - fmov xd2, dr2 - fcmp/eq dr0, dr2 - bt f10b - fail -f10b: # check pre-dec. - add #8, r0 - cmp/eq r0, r1 - bt fmov11 - fail - -fmov11: # Test @rn+ -> fr. - init - sz_32 - single_prec - mov #40, r0 - shll8 r0 - # Preserve r0. - mov r0, r1 - fmov fr0, @r0 - fmov @r0+, fr2 - fcmp/eq fr0, fr2 - bt f11b - fail -f11b: # check post-inc. - add #4, r1 - cmp/eq r0, r1 - bt fmov12 - fail - -fmov12: # Test @rn+ -> dr. - init - sz_64 - double_prec - mov #40, r0 - shll8 r0 - # preserve r0. - mov r0, r1 - fmov dr0, @r0 - fmov @r0+, dr2 - fcmp/eq dr0, dr2 - bt f12b - fail -f12b: # check post-inc. - add #8, r1 - cmp/eq r0, r1 - bt fmov13 - fail - -fmov13: # Test @rn -> xd. - init - sz_64 - double_prec - mov #40, r0 - shll8 r0 - # Preserve r0. - mov r0, r1 - fmov dr0, xd0 - fmov xd0, @r0 - fmov @r0+, xd2 - fmov xd2, dr2 - fcmp/eq dr0, dr2 - bt f13b - fail -f13b: - add #8, r1 - cmp/eq r0, r1 - bt fmov14 - fail - -fmov14: # Test fr -> @(r0,rn), @(r0, rn) -> fr. - init - sz_32 - single_prec - mov #40, r0 - shll8 r0 - mov #0, r1 - fmov fr0, @(r0, r1) - fmov @(r0, r1), fr1 - fcmp/eq fr0, fr1 - bt fmov15 - fail - -fmov15: # Test dr -> @(r0, rn), @(r0, rn) -> dr. - init - sz_64 - double_prec - mov #40, r0 - shll8 r0 - mov #0, r1 - fmov dr0, @(r0, r1) - fmov @(r0, r1), dr2 - fcmp/eq dr0, dr2 - bt fmov16 - fail - -fmov16: # Test xd -> @(r0, rn), @(r0, rn) -> xd. - init - sz_64 - double_prec - mov #40, r0 - shll8 r0 - mov #0, r1 - fmov dr0, xd0 - fmov xd0, @(r0, r1) - fmov @(r0, r1), xd2 - fmov xd2, dr2 - fcmp/eq dr0, dr2 - bt .L1 - fail -.L1: - assertreg0 0x2800 - assertreg 0, r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - sz_32 - single_prec - assert_fpreg_i 0, fr0 - assert_fpreg_i 1, fr1 - assert_fpreg_i 0, fr2 - assert_fpreg_i 1, fr3 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/fmul.s b/sim/testsuite/sim/sh/fmul.s deleted file mode 100644 index 81a2545ccfa..00000000000 --- a/sim/testsuite/sim/sh/fmul.s +++ /dev/null @@ -1,116 +0,0 @@ -# sh testcase for fmul -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - .macro init - fldi0 fr0 - fldi1 fr1 - fldi1 fr2 - fadd fr2, fr2 - .endm - - start -fmul_single: - set_grs_a5a5 - set_fprs_a5a5 - # 0.0 * 0.0 = 0.0. - init - fmul fr0, fr0 - assert_fpreg_i 0, fr0 - - # 0.0 * 1.0 = 0.0. - init - fmul fr1, fr0 - assert_fpreg_i 0, fr0 - - # 1.0 * 0.0 = 0.0. - init - fmul fr0, fr1 - assert_fpreg_i 0, fr1 - - # 1.0 * 1.0 = 1.0. - init - fmul fr1, fr1 - assert_fpreg_i 1, fr1 - - # 2.0 * 1.0 = 2.0. - init - fmul fr2, fr1 - assert_fpreg_i 2, fr1 - - test_grs_a5a5 - assert_fpreg_i 0, fr0 - assert_fpreg_i 2, fr1 - assert_fpreg_i 2, fr2 - test_fpr_a5a5 fr3 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - - .macro dinit - fldi0 fr0 - fldi1 fr2 - fldi1 fr4 - single_prec - fadd fr4, fr4 - double_prec - _s2d fr0, dr0 - _s2d fr2, dr2 - _s2d fr4, dr4 - .endm - -fmul_double: - double_prec - # 0.0 * 0.0 = 0.0. - dinit - fmul dr0, dr0 - assert_dpreg_i 0, dr0 - - # 0.0 * 1.0 = 0.0. - dinit - fmul dr2, dr0 - assert_dpreg_i 0, dr0 - - # 1.0 * 0.0 = 0.0. - dinit - fmul dr0, dr2 - assert_dpreg_i 0, dr2 - - # 1.0 * 1.0 = 1.0. - dinit - fmul dr2, dr2 - assert_dpreg_i 1, dr2 - - # 2.0 * 1.0 = 2.0. - dinit - fmul dr4, dr2 - assert_dpreg_i 2, dr2 - - test_grs_a5a5 - assert_dpreg_i 0, dr0 - assert_dpreg_i 2, dr2 - assert_dpreg_i 2, dr4 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/fneg.s b/sim/testsuite/sim/sh/fneg.s deleted file mode 100644 index dd5fe5d8bab..00000000000 --- a/sim/testsuite/sim/sh/fneg.s +++ /dev/null @@ -1,112 +0,0 @@ -# sh testcase for fneg -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start -fneg_single: - set_grs_a5a5 - set_fprs_a5a5 - # neg(0.0) = 0.0. - fldi0 fr0 - fldi0 fr1 - fneg fr0 - fcmp/eq fr0, fr1 - bt .L0 - fail -.L0: - # neg(1.0) = fsub(0,1) - fldi1 fr0 - fneg fr0 - fldi0 fr1 - fldi1 fr2 - fsub fr2, fr1 - fcmp/eq fr0, fr1 - bt .L1 - fail -.L1: - # neg(neg(1.0)) = 1.0. - fldi1 fr0 - fldi1 fr1 - fneg fr0 - fneg fr0 - fcmp/eq fr0, fr1 - bt .L2 - fail -.L2: - test_grs_a5a5 - assert_fpreg_i 1, fr0 - assert_fpreg_i 1, fr1 - assert_fpreg_i 1, fr2 - test_fpr_a5a5 fr3 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - -fneg_double: - set_grs_a5a5 - set_fprs_a5a5 - double_prec - # neg(0.0) = 0.0. - fldi0 fr0 - fldi0 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - fneg dr0 - fcmp/eq dr0, dr2 - bt .L10 - fail -.L10: - # neg(1.0) = fsub(0,1) - fldi1 fr0 - _s2d fr0, dr0 - fneg dr0 - fldi0 fr2 - fldi1 fr3 - single_prec - fsub fr3, fr2 - double_prec - _s2d fr2, dr2 - fcmp/eq dr0, dr2 - bt .L11 - fail -.L11: - # neg(neg(1.0)) = 1.0. - fldi1 fr0 - _s2d fr0, dr0 - fldi1 fr2 - _s2d fr2, dr2 - fneg dr2 - fneg dr2 - fcmp/eq dr0, dr2 - bt .L12 - fail -.L12: - test_grs_a5a5 - assert_dpreg_i 1, dr0 - assert_dpreg_i 1, dr2 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/fpchg.s b/sim/testsuite/sim/sh/fpchg.s deleted file mode 100644 index 47ba03b1c03..00000000000 --- a/sim/testsuite/sim/sh/fpchg.s +++ /dev/null @@ -1,30 +0,0 @@ -# sh testcase for fpchg -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start - set_grs_a5a5 - set_fprs_a5a5 - sts fpscr, r0 - assertreg0 0 - fpchg - sts fpscr, r0 - assertreg0 0x80000 - fpchg - sts fpscr, r0 - assertreg0 0 - fpchg - sts fpscr, r0 - assertreg0 0x80000 - fpchg - sts fpscr, r0 - assertreg0 0 - - set_greg 0xa5a5a5a5, r0 - test_grs_a5a5 - test_fprs_a5a5 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/frchg.s b/sim/testsuite/sim/sh/frchg.s deleted file mode 100644 index c5dc0992e5f..00000000000 --- a/sim/testsuite/sim/sh/frchg.s +++ /dev/null @@ -1,30 +0,0 @@ -# sh testcase for frchg -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start - set_grs_a5a5 - set_fprs_a5a5 - sts fpscr, r0 - assertreg0 0 - frchg - sts fpscr, r0 - assertreg0 0x200000 - frchg - sts fpscr, r0 - assertreg0 0 - frchg - sts fpscr, r0 - assertreg0 0x200000 - frchg - sts fpscr, r0 - assertreg0 0 - - set_greg 0xa5a5a5a5, r0 - test_grs_a5a5 - test_fprs_a5a5 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/fschg.s b/sim/testsuite/sim/sh/fschg.s deleted file mode 100644 index 7454787b1d6..00000000000 --- a/sim/testsuite/sim/sh/fschg.s +++ /dev/null @@ -1,29 +0,0 @@ -# sh testcase for fschg -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start - set_grs_a5a5 - set_fprs_a5a5 - sts fpscr, r0 - assertreg0 0 - fschg - sts fpscr, r0 - assertreg0 0x100000 - fschg - sts fpscr, r0 - assertreg0 0 - fschg - sts fpscr, r0 - assertreg0 0x100000 - fschg - sts fpscr, r0 - assertreg0 0 - - set_greg 0xa5a5a5a5 r0 - test_grs_a5a5 - test_fprs_a5a5 - pass - exit 0 diff --git a/sim/testsuite/sim/sh/fsqrt.s b/sim/testsuite/sim/sh/fsqrt.s deleted file mode 100644 index cb61bcf4085..00000000000 --- a/sim/testsuite/sim/sh/fsqrt.s +++ /dev/null @@ -1,120 +0,0 @@ -# sh testcase for fsqrt -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start -fsqrt_single: - set_grs_a5a5 - set_fprs_a5a5 - # sqrt(0.0) = 0.0. - fldi0 fr0 - fsqrt fr0 - fldi0 fr1 - fcmp/eq fr0, fr1 - bt .L0 - fail -.L0: - # sqrt(1.0) = 1.0. - fldi1 fr0 - fsqrt fr0 - fldi1 fr1 - fcmp/eq fr0, fr1 - bt .L1 - fail -.L1: - # sqrt(4.0) = 2.0 - fldi1 fr0 - # Double it. - fadd fr0, fr0 - # Double it again. - fadd fr0, fr0 - fsqrt fr0 - fldi1 fr1 - # Double it. - fadd fr1, fr1 - fcmp/eq fr0, fr1 - bt .L2 - fail -.L2: - test_grs_a5a5 - assert_fpreg_i 2, fr0 - assert_fpreg_i 2, fr1 - test_fpr_a5a5 fr2 - test_fpr_a5a5 fr3 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - -fsqrt_double: - double_prec - set_grs_a5a5 - set_fprs_a5a5 - # sqrt(0.0) = 0.0. - fldi0 fr0 - _s2d fr0, dr0 - fsqrt dr0 - fldi0 fr2 - _s2d fr2, dr2 - fcmp/eq dr0, dr2 - bt .L10 - fail -.L10: - # sqrt(1.0) = 1.0. - fldi1 fr0 - _s2d fr0, dr0 - fsqrt dr0 - fldi1 fr2 - _s2d fr2, dr2 - fcmp/eq dr0, dr2 - bt .L11 - fail -.L11: - # sqrt(4.0) = 2.0. - fldi1 fr0 - # Double it. - single_prec - fadd fr0, fr0 - # Double it again. - fadd fr0, fr0 - double_prec - _s2d fr0, dr0 - fsqrt dr0 - fldi1 fr2 - # Double it. - single_prec - fadd fr2, fr2 - double_prec - _s2d fr2, dr2 - fcmp/eq dr0, dr2 - bt .L12 - fail -.L12: - test_grs_a5a5 - assert_dpreg_i 2, dr0 - assert_dpreg_i 2, dr2 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/fsub.s b/sim/testsuite/sim/sh/fsub.s deleted file mode 100644 index dfe9172f57a..00000000000 --- a/sim/testsuite/sim/sh/fsub.s +++ /dev/null @@ -1,136 +0,0 @@ -# sh testcase for fsub -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start -fsub_single: - set_grs_a5a5 - set_fprs_a5a5 - # 0.0 - 0.0 = 0.0. - fldi0 fr0 - fldi0 fr1 - fsub fr0, fr1 - fldi0 fr2 - fcmp/eq fr1, fr2 - bt .L0 - fail -.L0: - # 1.0 - 0.0 = 1.0. - fldi0 fr0 - fldi1 fr1 - fsub fr0, fr1 - fldi1 fr2 - fcmp/eq fr1, fr2 - bt .L1 - fail -.L1: - # 1.0 - 1.0 = 0.0. - fldi1 fr0 - fldi1 fr1 - fsub fr0, fr1 - fldi0 fr2 - fcmp/eq fr1, fr2 - bt .L2 - fail -.L2: - # 0.0 - 1.0 = -1.0. - fldi1 fr0 - fldi0 fr1 - fsub fr0, fr1 - fldi1 fr2 - fneg fr2 - fcmp/eq fr1, fr2 - bt .L3 - fail -.L3: - test_grs_a5a5 - assert_fpreg_i 1, fr0 - assert_fpreg_i -1, fr1 - assert_fpreg_i -1, fr2 - test_fpr_a5a5 fr3 - test_fpr_a5a5 fr4 - test_fpr_a5a5 fr5 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - -fsub_double: - set_grs_a5a5 - set_fprs_a5a5 - double_prec - # 0.0 - 0.0 = 0.0. - fldi0 fr0 - fldi0 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - fsub dr0, dr2 - fldi0 fr4 - _s2d fr4, dr4 - fcmp/eq dr2, dr4 - bt .L10 - fail -.L10: - # 1.0 - 0.0 = 1.0. - fldi0 fr0 - fldi1 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - fsub dr0, dr2 - fldi1 fr4 - _s2d fr4, dr4 - fcmp/eq dr2, dr4 - bt .L11 - fail -.L11: - # 1.0 - 1.0 = 0.0. - fldi1 fr0 - fldi1 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - fsub dr0, dr2 - fldi0 fr4 - _s2d fr4, dr4 - fcmp/eq dr2, dr4 - bt .L12 - fail -.L12: - # 0.0 - 1.0 = -1.0. - fldi1 fr0 - fldi0 fr2 - _s2d fr0, dr0 - _s2d fr2, dr2 - fsub dr0, dr2 - fldi1 fr4 - single_prec - fneg fr4 - double_prec - _s2d fr4, dr4 - fcmp/eq dr2, dr4 - bt .L13 - fail -.L13: - test_grs_a5a5 - assert_dpreg_i 1, dr0 - assert_dpreg_i -1, dr2 - assert_dpreg_i -1, dr4 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - pass - exit 0 diff --git a/sim/testsuite/sim/sh/ftrc.s b/sim/testsuite/sim/sh/ftrc.s deleted file mode 100644 index 25e33be33ad..00000000000 --- a/sim/testsuite/sim/sh/ftrc.s +++ /dev/null @@ -1,156 +0,0 @@ -# sh testcase for ftrc -# mach: sh -# as(sh): -defsym sim_cpu=0 - - .include "testutils.inc" - - start -ftrc_single: - set_grs_a5a5 - set_fprs_a5a5 - # ftrc(0.0) = 0. - fldi0 fr0 - ftrc fr0, fpul - # check results. - mov #0, r0 - sts fpul, r1 - cmp/eq r0, r1 - bt .L0 - fail -.L0: - # ftrc(1.5) = 1. - fldi1 fr0 - fldi1 fr1 - fldi1 fr2 - # double it. - fadd fr2, fr2 - # form the fraction. - fdiv fr2, fr1 - fadd fr1, fr0 - # now we've got 1.5 in fr0. - ftrc fr0, fpul - # check results. - mov #1, r0 - sts fpul, r1 - cmp/eq r0, r1 - bt .L1 - fail -.L1: - # ftrc(-1.5) = -1. - fldi1 fr0 - fneg fr0 - fldi1 fr1 - fldi1 fr2 - # double it. - fadd fr2, fr2 - # form the fraction. - fdiv fr2, fr1 - fneg fr1 - # -1 + -0.5 = -1.5. - fadd fr1, fr0 - # now we've got 1.5 in fr0. - ftrc fr0, fpul - # check results. - mov #1, r0 - neg r0, r0 - sts fpul, r1 - cmp/eq r0, r1 - bt ftrc_double - fail - -ftrc_double: - double_prec - # ftrc(0.0) = 0. - fldi0 fr0 - _s2d fr0, dr0 - ftrc dr0, fpul - # check results. - mov #0, r0 - sts fpul, r1 - cmp/eq r0, r1 - bt .L10 - fail -.L10: - # ftrc(1.5) = 1. - fldi1 fr0 - fldi1 fr2 - fldi1 fr4 - # double it. - single_prec - fadd fr4, fr4 - # form 0.5. - fdiv fr4, fr2 - fadd fr2, fr0 - double_prec - # now we've got 1.5 in fr0, so do some single->double - # conversions and perform the ftrc. - _s2d fr0, dr0 - _s2d fr2, dr2 - _s2d fr4, dr4 - ftrc dr0, fpul - - # check results. - mov #1, r0 - sts fpul, r1 - cmp/eq r0, r1 - bt .L11 - fail -.L11: - # ftrc(-1.5) = -1. - fldi1 fr0 - fneg fr0 - fldi1 fr2 - fldi1 fr4 - single_prec - # double it. - fadd fr4, fr4 - # form the fraction. - fdiv fr4, fr2 - fneg fr2 - # -1 + -0.5 = -1.5. - fadd fr2, fr0 - double_prec - # now we've got 1.5 in fr0, so do some single->double - # conversions and perform the ftrc. - _s2d fr0, dr0 - _s2d fr2, dr2 - _s2d fr4, dr4 - ftrc dr0, fpul - - # check results. - mov #1, r0 - neg r0, r0 - sts fpul, r1 - cmp/eq r0, r1 - bt .L12 - fail -.L12: - assertreg0 -1 - assertreg -1, r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - assert_dpreg_i 2, dr4 - test_fpr_a5a5 fr6 - test_fpr_a5a5 fr7 - test_fpr_a5a5 fr8 - test_fpr_a5a5 fr9 - test_fpr_a5a5 fr10 - test_fpr_a5a5 fr11 - test_fpr_a5a5 fr12 - test_fpr_a5a5 fr13 - test_fpr_a5a5 fr14 - test_fpr_a5a5 fr15 - pass - exit 0 diff --git a/sim/testsuite/sim/sh/ldrc.s b/sim/testsuite/sim/sh/ldrc.s deleted file mode 100644 index 444131302f4..00000000000 --- a/sim/testsuite/sim/sh/ldrc.s +++ /dev/null @@ -1,118 +0,0 @@ -# sh testcase for ldrc, strc -# mach: shdsp -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -setrc_imm: - set_grs_a5a5 - # Test setrc - # - ldrs lstart - ldre lend - setrc #0xff - get_sr r1 - shlr16 r1 - set_greg 0xfff, r0 - and r0, r1 - assertreg 0xff, r1 - - stc rs, r0 ! rs unchanged - assertreg0 lstart - stc re, r0 ! re unchanged - assertreg0 lend - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - - test_grs_a5a5 - -setrc_reg: - set_grs_a5a5 - # Test setrc - # - ldrs lstart - ldre lend - set_greg 0xfff, r0 - setrc r0 - get_sr r1 - shlr16 r1 - set_greg 0xfff, r0 - and r0, r1 - assertreg 0xfff, r1 - - stc rs, r0 ! rs unchanged - assertreg0 lstart - stc re, r0 ! re unchanged - assertreg0 lend - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - - test_grs_a5a5 - - bra ldrc_imm - - .global lstart - .align 2 -lstart: nop - nop - nop - nop - .global lend - .align 2 -lend: nop - nop - nop - nop - -ldrc_imm: - set_grs_a5a5 - # Test ldrc - setrc #0x0 ! zero rc - ldrc #0xa5 - get_sr r1 - shlr16 r1 - set_greg 0xfff, r0 - and r0, r1 - assertreg 0xa5, r1 - stc rs, r0 ! rs unchanged - assertreg0 lstart - stc re, r0 - assertreg0 lend+1 ! bit 0 set in re - - # fix up re for next test - dt r0 ! Ugh! No DEC insn! - ldc r0, re - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - - test_grs_a5a5 - -ldrc_reg: - set_grs_a5a5 - # Test ldrc - setrc #0x0 ! zero rc - set_greg 0xa5a, r0 - ldrc r0 - get_sr r1 - shlr16 r1 - set_greg 0xfff, r0 - and r0, r1 - assertreg 0xa5a, r1 - stc rs, r0 ! rs unchanged - assertreg0 lstart - stc re, r0 - assertreg0 lend+1 ! bit 0 set in re - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - - test_grs_a5a5 - - pass - exit 0 - diff --git a/sim/testsuite/sim/sh/loop.s b/sim/testsuite/sim/sh/loop.s deleted file mode 100644 index 604051938e7..00000000000 --- a/sim/testsuite/sim/sh/loop.s +++ /dev/null @@ -1,311 +0,0 @@ -# sh testcase for loop control -# mach: shdsp -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start -loop1: - set_grs_a5a5 - - ldrs Loop1_start0+8 - ldre Loop1_start0+4 - setrc #5 -Loop1_start0: - add #1, r1 ! Before loop - # Loop should execute one instruction five times. -Loop1_begin: - add #1, r1 ! Within loop -Loop1_end: - add #2, r1 ! After loop - - # r1 = 0xa5a5a5a5 + 8 (five in loop, two after, one before) - assertreg 0xa5a5a5a5+8, r1 - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - test_grs_a5a5 - -loop2: - set_grs_a5a5 - - ldrs Loop2_start0+6 - ldre Loop2_start0+4 - setrc #5 -Loop2_start0: - add #1, r1 ! Before loop - # Loop should execute two instructions five times. -Loop2_begin: - add #1, r1 ! Within loop - add #1, r1 ! Within loop -Loop2_end: - add #3, r1 ! After loop - - # r1 = 0xa5a5a5a5 + 14 (ten in loop, three after, one before) - assertreg 0xa5a5a5a5+14, r1 - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - test_grs_a5a5 - -loop3: - set_grs_a5a5 - - ldrs Loop3_start0+4 - ldre Loop3_start0+4 - setrc #5 -Loop3_start0: - add #1, r1 ! Before loop - # Loop should execute three instructions five times. -Loop3_begin: - add #1, r1 ! Within loop - add #1, r1 ! Within loop - add #1, r1 ! Within loop -Loop3_end: - add #2, r1 ! After loop - - # r1 = 0xa5a5a5a5 + 18 (fifteen in loop, two after, one before) - assertreg 0xa5a5a5a5+18, r1 - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - test_grs_a5a5 - -loop4: - set_grs_a5a5 - - ldrs Loop4_begin - ldre Loop4_last3+4 - setrc #5 - add #1, r1 ! Before loop - # Loop should execute four instructions five times. -Loop4_begin: -Loop4_last3: - add #1, r1 ! Within loop -Loop4_last2: - add #1, r1 ! Within loop -Loop4_last1: - add #1, r1 ! Within loop -Loop4_last: - add #1, r1 ! Within loop -Loop4_end: - add #2, r1 ! After loop - - # r1 = 0xa5a5a5a5 + 23 (20 in loop, two after, one before) - assertreg 0xa5a5a5a5+23, r1 - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - test_grs_a5a5 - -loop5: - set_grs_a5a5 - - ldrs Loop5_begin - ldre Loop5_last3+4 - setrc #5 - add #1, r1 ! Before loop - # Loop should execute five instructions five times. -Loop5_begin: - add #1, r1 ! Within loop -Loop5_last3: - add #1, r1 ! Within loop -Loop5_last2: - add #1, r1 ! Within loop -Loop5_last1: - add #1, r1 ! Within loop -Loop5_last: - add #1, r1 ! Within loop -Loop5_end: - add #2, r1 ! After loop - - # r1 = 0xa5a5a5a5 + 28 (25 in loop, two after, one before) - assertreg 0xa5a5a5a5+28, r1 - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - test_grs_a5a5 - -loopn: - set_grs_a5a5 - - ldrs Loopn_begin - ldre Loopn_last3+4 - setrc #5 - add #1, r1 ! Before loop - # Loop should execute n instructions five times. -Loopn_begin: - add #1, r1 ! Within loop - add #1, r1 ! Within loop - add #1, r1 ! Within loop - add #1, r1 ! Within loop - add #1, r1 ! Within loop - add #1, r1 ! Within loop - add #1, r1 ! Within loop - add #1, r1 ! Within loop -Loopn_last3: - add #1, r1 ! Within loop -Loopn_last2: - add #1, r1 ! Within loop -Loopn_last1: - add #1, r1 ! Within loop -Loopn_last: - add #1, r1 ! Within loop -Loopn_end: - add #3, r1 ! After loop - - # r1 = 0xa5a5a5a5 + 64 (60 in loop, three after, one before) - assertreg 0xa5a5a5a5+64, r1 - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - test_grs_a5a5 - -loop1e: - set_grs_a5a5 - - ldrs Loop1e_begin - ldre Loop1e_last - ldrc #5 - add #1, r1 ! Before loop - # Loop should execute one instruction five times. -Loop1e_begin: -Loop1e_last: - add #1, r1 ! Within loop -Loop1e_end: - add #2, r1 ! After loop - - # r1 = 0xa5a5a5a5 + 8 (five in loop, two after, one before) - assertreg 0xa5a5a5a5+8, r1 - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - test_grs_a5a5 - -loop2e: - set_grs_a5a5 - - ldrs Loop2e_begin - ldre Loop2e_last - ldrc #5 - add #1, r1 ! Before loop - # Loop should execute two instructions five times. -Loop2e_begin: - add #1, r1 ! Within loop -Loop2e_last: - add #1, r1 ! Within loop -Loop2e_end: - add #2, r1 ! After loop - - # r1 = 0xa5a5a5a5 + 13 (ten in loop, two after, one before) - assertreg 0xa5a5a5a5+13, r1 - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - test_grs_a5a5 - -loop3e: - set_grs_a5a5 - - ldrs Loop3e_begin - ldre Loop3e_last - ldrc #5 - add #1, r1 ! Before loop - # Loop should execute three instructions five times. -Loop3e_begin: - add #1, r1 ! Within loop - add #1, r1 ! Within loop -Loop3e_last: - add #1, r1 ! Within loop -Loop3e_end: - add #2, r1 ! After loop - - # r1 = 0xa5a5a5a5 + 18 (fifteen in loop, two after, one before) - assertreg 0xa5a5a5a5+18, r1 - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - test_grs_a5a5 - -loop4e: - set_grs_a5a5 - - ldrs Loop4e_begin - ldre Loop4e_last - ldrc #5 - add #1, r1 ! Before loop - # Loop should execute four instructions five times. -Loop4e_begin: - add #1, r1 ! Within loop - add #1, r1 ! Within loop - add #1, r1 ! Within loop -Loop4e_last: - add #1, r1 ! Within loop -Loop4e_end: - add #2, r1 ! After loop - - # r1 = 0xa5a5a5a5 + 23 (twenty in loop, two after, one before) - assertreg 0xa5a5a5a5+23, r1 - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - test_grs_a5a5 - -loop5e: - set_grs_a5a5 - - ldrs Loop5e_begin - ldre Loop5e_last - ldrc #5 - add #1, r1 ! Before loop - # Loop should execute five instructions five times. -Loop5e_begin: - add #1, r1 ! Within loop - add #1, r1 ! Within loop - add #1, r1 ! Within loop - add #1, r1 ! Within loop -Loop5e_last: - add #1, r1 ! Within loop -Loop5e_end: - add #2, r1 ! After loop - - # r1 = 0xa5a5a5a5 + 28 (twenty five in loop, two after, one before) - assertreg 0xa5a5a5a5+28, r1 - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - test_grs_a5a5 - -loop_n_e: - set_grs_a5a5 - - ldrs Loop_n_e_begin - ldre Loop_n_e_last - ldrc #5 - add #1, r1 ! Before loop - # Loop should execute n instructions five times. -Loop_n_e_begin: - add #1, r1 ! Within loop - add #1, r1 ! Within loop - add #1, r1 ! Within loop - add #1, r1 ! Within loop - add #1, r1 ! Within loop - add #1, r1 ! Within loop - add #1, r1 ! Within loop - add #1, r1 ! Within loop -Loop_n_e_last: - add #1, r1 ! Within loop -Loop_n_e_end: - add #2, r1 ! After loop - - # r1 = 0xa5a5a5a5 + 48 (forty five in loop, two after, one before) - assertreg 0xa5a5a5a5+48, r1 - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - test_grs_a5a5 - - pass - - exit 0 - diff --git a/sim/testsuite/sim/sh/macl.s b/sim/testsuite/sim/sh/macl.s deleted file mode 100644 index 39b3b7d604b..00000000000 --- a/sim/testsuite/sim/sh/macl.s +++ /dev/null @@ -1,54 +0,0 @@ -# sh testcase for mac.l -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - # force S-bit clear - clrs - -init: - # Prime {MACL, MACH} to #1. - mov #1, r0 - dmulu.l r0, r0 - - # Set up addresses. - mov.l pfour00, r0 ! 85 - mov.l pfour12, r1 ! 17 - -test: - mac.l @r0+, @r1+ - -check: - # Check result. - assert_sreg 0, mach - assert_sreg 85*17+1, macl - - # Ensure post-increment occurred. - assertreg0 four00+4 - assertreg four12+4, r1 - -doubleinc: - mov.l pfour00, r0 - mac.l @r0+, @r0+ - assertreg0 four00+8 - - - pass - exit 0 - - .align 1 -four00: - .long 85 - .long 2 -four12: - .long 17 - .long 3 - - .align 2 -pfour00: - .long four00 -pfour12: - .long four12 diff --git a/sim/testsuite/sim/sh/macw.s b/sim/testsuite/sim/sh/macw.s deleted file mode 100644 index 7e3ebc07d7b..00000000000 --- a/sim/testsuite/sim/sh/macw.s +++ /dev/null @@ -1,56 +0,0 @@ -# sh testcase for mac.w -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - set_grs_a5a5 - - # Prime {MACL, MACH} to #1. - mov #1, r0 - dmulu.l r0, r0 - - # Set up addresses. - mov.l pfour00, r0 ! 85 - mov.l pfour12, r1 ! 17 - -test: - mac.w @r0+, @r1+ ! MAC = 85 * 17 + 1 - -check: - # Check result. - assert_sreg 0, mach - assert_sreg 85*17+1, macl - - # Ensure post-increment occurred. - assertreg0 four00+2 - assertreg four12+2, r1 - -doubleinc: - mov.l pfour00, r0 - mac.w @r0+, @r0+ - assertreg0 four00+4 - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - - test_grs_a5a5 - - pass - exit 0 - - .align 2 -four00: - .word 85 - .word 2 -four12: - .word 17 - .word 3 - - -pfour00: - .long four00 -pfour12: - .long four12 diff --git a/sim/testsuite/sim/sh/movi.s b/sim/testsuite/sim/sh/movi.s deleted file mode 100644 index b79f8d2131a..00000000000 --- a/sim/testsuite/sim/sh/movi.s +++ /dev/null @@ -1,35 +0,0 @@ -# sh testcase for mov <#imm> -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -mov_i_reg: # Test - set_grs_a5a5 - mov #-0x55, r1 - - assertreg 0xffffffab, r1 - - test_gr_a5a5 r0 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - pass - - exit 0 - - diff --git a/sim/testsuite/sim/sh/movli.s b/sim/testsuite/sim/sh/movli.s deleted file mode 100644 index eacd10358ba..00000000000 --- a/sim/testsuite/sim/sh/movli.s +++ /dev/null @@ -1,55 +0,0 @@ -# sh testcase for movli -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - .align 2 -x: .long 1 -y: .long 2 -z: .long 3 - - start - set_grs_a5a5 - mov.l xptr, r1 - mov.l yptr, r2 - # Move linked/conditional, x to y - movli.l @r1, r0 - movco.l r0, @r2 - - # Check result. - assertreg0 1 - mov.l yptr, r1 - mov.l @r1, r2 - assertreg 1, r2 - - # Now attempt an unlinked move of r0 to z - mov.l zptr, r1 - movco.l r0, @r1 - - # Check that z is unchanged. - mov.l zptr, r1 - mov.l @r1, r2 - assertreg 3, r2 - - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - pass - exit 0 - - .align 2 -xptr: .long x -yptr: .long y -zptr: .long z diff --git a/sim/testsuite/sim/sh/movua.s b/sim/testsuite/sim/sh/movua.s deleted file mode 100644 index e8620f0b429..00000000000 --- a/sim/testsuite/sim/sh/movua.s +++ /dev/null @@ -1,129 +0,0 @@ -# sh testcase for movua -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start -movua_1: - set_grs_a5a5 - mov.l srcp, r1 - movua.l @r1, r0 - assertreg0 0x00010203 - - add #1, r1 - movua.l @r1, r0 - assertreg0 0x01020304 - - add #1, r1 - movua.l @r1, r0 - assertreg0 0x02030405 - - add #1, r1 - movua.l @r1, r0 - assertreg0 0x03040506 - - add #1, r1 - movua.l @r1, r0 - assertreg0 0x04050607 - - add #1, r1 - movua.l @r1, r0 - assertreg0 0x05060708 - - add #1, r1 - movua.l @r1, r0 - assertreg0 0x06070809 - - add #1, r1 - movua.l @r1, r0 - assertreg0 0x0708090a - - add #1, r1 - movua.l @r1, r0 - assertreg0 0x08090a0b - - add #1, r1 - movua.l @r1, r0 - assertreg0 0x090a0b0c - - add #1, r1 - movua.l @r1, r0 - assertreg0 0x0a0b0c0d - - add #1, r1 - movua.l @r1, r0 - assertreg0 0x0b0c0d0e - - add #1, r1 - movua.l @r1, r0 - assertreg0 0x0c0d0e0f - - assertreg src+12, r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - bra movua_4: - nop - - .align 0 -src: .byte 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 - .align 2 -srcp: .long src - -movua_4: - set_grs_a5a5 - mov.l srcp2, r1 - movua.l @r1+, r0 - assertreg0 0x00010203 - assertreg src+4, r1 - - mov.l srcp2, r1 - add #1, r1 - movua.l @r1+, r0 - assertreg0 0x01020304 - assertreg src+5, r1 - - mov.l srcp2, r1 - add #2, r1 - movua.l @r1+, r0 - assertreg0 0x02030405 - assertreg src+6, r1 - - mov.l srcp2, r1 - add #3, r1 - movua.l @r1+, r0 - assertreg0 0x03040506 - assertreg src+7, r1 - - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - pass - exit 0 - -srcp2: .long src - diff --git a/sim/testsuite/sim/sh/movxy.s b/sim/testsuite/sim/sh/movxy.s deleted file mode 100644 index 7768ef96d50..00000000000 --- a/sim/testsuite/sim/sh/movxy.s +++ /dev/null @@ -1,1186 +0,0 @@ -# sh testcase for movxy -# mach: shdsp -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - .align 2 -src1: .word 1 -src2: .word 2 -src3: .word 3 -src4: .word 4 -src5: .word 5 -src6: .word 6 -src7: .word 7 -src8: .word 8 -src9: .word 9 - .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 - -dst1: .word 0 -dst2: .word 0 -dst3: .word 0 -dst4: .word 0 -dst5: .word 0 -dst6: .word 0 -dst7: .word 0 -dst8: .word 0 -dst9: .word 0 - .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 - - start -movxw_nopy: - set_grs_a5a5 - # load up pointers - mov.l srcp1, r4 - mov.l dstp1, r5 - - # perform moves - movx.w @r4, x0 - pcopy x0, a0 - movx.w a0, @r5 - - # verify pointers unchanged - mov.l srcp1, r0 - cmp/eq r0, r4 - bt .L0 - fail -.L0: - mov.l dstp1, r1 - cmp/eq r1, r5 - bt .L1 - fail -.L1: - # verify copied values - mov.w @r0, r0 - mov.w @r1, r1 - cmp/eq r0, r1 - bt .L2 - fail -.L2: - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - -movyw_nopx: - set_grs_a5a5 - # load up pointers - mov.l srcp2, r6 - mov.l dstp2, r7 - - # perform moves - movy.w @r6, y0 - pcopy y0, a0 - movy.w a0, @r7 - - # verify pointers unchanged - mov.l srcp2, r2 - cmp/eq r2, r6 - bt .L3 - fail -.L3: - mov.l dstp2, r3 - cmp/eq r3, r7 - bt .L4 - fail -.L4: - # verify copied values - mov.w @r2, r2 - mov.w @r3, r3 - cmp/eq r2, r3 - bt .L5 - fail -.L5: - test_gr_a5a5 r0 - test_gr_a5a5 r1 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - -movxw_movyw: - set_grs_a5a5 - # load up pointers - mov.l srcp3, r4 - mov.l dstp3, r5 - mov.l srcp4, r6 - mov.l dstp4, r7 - - # perform moves - movx.w @r4, x1 movy.w @r6, y1 - pcopy x1, a0 - pcopy y1, a1 - movx.w a0, @r5 movy.w a1, @r7 - - # verify pointers unchanged - mov.l srcp3, r0 - cmp/eq r0, r4 - bt .L6 - fail -.L6: - mov.l dstp3, r1 - cmp/eq r1, r5 - bt .L7 - fail -.L7: - mov.l srcp4, r2 - cmp/eq r2, r6 - bt .L8 - fail -.L8: - mov.l dstp4, r3 - cmp/eq r3, r7 - bt .L9 - fail -.L9: - # verify copied values - mov.w @r0, r0 - mov.w @r1, r1 - cmp/eq r0, r1 - bt .L10 - fail -.L10: - mov.w @r2, r2 - mov.w @r3, r3 - cmp/eq r2, r3 - bt .L11 - fail -.L11: - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - bra movxw_movyw_new - nop - - .align 2 -srcp1: .long src1 -srcp2: .long src2 -srcp3: .long src3 -srcp4: .long src4 -srcp5: .long src5 -srcp6: .long src6 -srcp7: .long src7 -srcp8: .long src8 -srcp9: .long src9 - -dstp1: .long dst1 -dstp2: .long dst2 -dstp3: .long dst3 -dstp4: .long dst4 -dstp5: .long dst5 -dstp6: .long dst6 -dstp7: .long dst7 -dstp8: .long dst8 -dstp9: .long dst9 - -movxw_movyw_new: - set_grs_a5a5 - # load up pointers - mov.l srcp5b, r0 - mov.l dstp5b, r1 - mov.l srcp6b, r2 - mov.l dstp6b, r3 - - # perform moves - movx.w @r0, x1 - movy.w @r2, y1 - movx.w x1, @r1 - movy.w y1, @r3 - - # verify pointers unchanged - mov.l srcp5b, r4 - cmp/eq r0, r4 - bt .L12 - fail - -.L12: - mov.l dstp5b, r5 - cmp/eq r1, r5 - bt .L13 - fail -.L13: - mov.l srcp6b, r6 - cmp/eq r2, r6 - bt .L14 - fail -.L14: - mov.l dstp6b, r7 - cmp/eq r3, r7 - bt .L15 - fail -.L15: - # verify copied values - mov.w @r0, r0 - mov.w @r1, r1 - cmp/eq r0, r1 - bt .L16 - fail -.L16: - mov.w @r2, r2 - mov.w @r3, r3 - cmp/eq r2, r3 - bt .L17 - fail -.L17: - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - mov.l srcp1b, r0 - mov.l dstp1b, r1 - mov.l srcp2b, r2 - mov.l dstp2b, r3 - mov.l srcp1b, r4 - mov.l dstp1b, r5 - mov.l srcp2b, r6 - mov.l dstp2b, r7 - mov #4, r8 - mov #4, r9 - bra .L18 - nop - - .align 2 -srcp1b: .long src1 -srcp2b: .long src2 -srcp3b: .long src3 -srcp4b: .long src4 -srcp5b: .long src5 -srcp6b: .long src6 -srcp7b: .long src7 -srcp8b: .long src8 -srcp9b: .long src9 - -dstp1b: .long dst1 -dstp2b: .long dst2 -dstp3b: .long dst3 -dstp4b: .long dst4 -dstp5b: .long dst5 -dstp6b: .long dst6 -dstp7b: .long dst7 -dstp8b: .long dst8 -dstp9b: .long dst9 - -.L18: - - # movx.w @Ax{}, Dx | nopy -movxwaxdx_nopy: - movx.w @r4,x0 ! .word 0xf004 - movx.w @r4,x1 ! .word 0xf084 - movx.w @r5,x0 ! .word 0xf204 - movx.w @r5,x1 ! .word 0xf284 - movx.w @r4+,x0 ! .word 0xf008 - movx.w @r4+,x1 ! .word 0xf088 - movx.w @r5+,x0 ! .word 0xf208 - movx.w @r5+,x1 ! .word 0xf288 - movx.w @r4+r8,x0 ! .word 0xf00c - movx.w @r4+r8,x1 ! .word 0xf08c - movx.w @r5+r8,x0 ! .word 0xf20c - movx.w @r5+r8,x1 ! .word 0xf28c - # movx.w Da, @Ax{} | nopy -movxwdaax_nopy: - movx.w a0,@r4 ! .word 0xf024 - movx.w a1,@r4 ! .word 0xf0a4 - movx.w a0,@r5 ! .word 0xf224 - movx.w a1,@r5 ! .word 0xf2a4 - movx.w a0,@r4+ ! .word 0xf028 - movx.w a1,@r4+ ! .word 0xf0a8 - movx.w a0,@r5+ ! .word 0xf228 - movx.w a1,@r5+ ! .word 0xf2a8 - movx.w a0,@r4+r8 ! .word 0xf02c - movx.w a1,@r4+r8 ! .word 0xf0ac - movx.w a0,@r5+r8 ! .word 0xf22c - movx.w a1,@r5+r8 ! .word 0xf2ac - # movy.w @Ay{}, Dy | nopx -movywaydy_nopx: - movy.w @r6,y0 ! .word 0xf001 - movy.w @r6,y1 ! .word 0xf041 - movy.w @r7,y0 ! .word 0xf101 - movy.w @r7,y1 ! .word 0xf141 - movy.w @r6+,y0 ! .word 0xf002 - movy.w @r6+,y1 ! .word 0xf042 - movy.w @r7+,y0 ! .word 0xf102 - movy.w @r7+,y1 ! .word 0xf142 - movy.w @r6+r9,y0 ! .word 0xf003 - movy.w @r6+r9,y1 ! .word 0xf043 - movy.w @r7+r9,y0 ! .word 0xf103 - movy.w @r7+r9,y1 ! .word 0xf143 - # movy.w Da, @Ay{} | nopx -movywdaay_nopx: - movy.w a0,@r6 ! .word 0xf011 - movy.w a1,@r6 ! .word 0xf051 - movy.w a0,@r7 ! .word 0xf111 - movy.w a1,@r7 ! .word 0xf151 - movy.w a0,@r6+ ! .word 0xf012 - movy.w a1,@r6+ ! .word 0xf052 - movy.w a0,@r7+ ! .word 0xf112 - movy.w a1,@r7+ ! .word 0xf152 - movy.w a0,@r6+r9 ! .word 0xf013 - movy.w a1,@r6+r9 ! .word 0xf053 - movy.w a0,@r7+r9 ! .word 0xf113 - movy.w a1,@r7+r9 ! .word 0xf153 - # movx {} || movy {} -movx_movy: - movx.w @r4,x0 movy.w @r6,y0 ! .word 0xf005 - movx.w @r4,x0 movy.w @r6,y1 ! .word 0xf045 - movx.w @r4,x1 movy.w @r6,y0 ! .word 0xf085 - movx.w @r4,x1 movy.w @r6,y1 ! .word 0xf0c5 - movx.w @r4,x0 movy.w @r7,y0 ! .word 0xf105 - movx.w @r4,x0 movy.w @r7,y1 ! .word 0xf145 - movx.w @r4,x1 movy.w @r7,y0 ! .word 0xf185 - movx.w @r4,x1 movy.w @r7,y1 ! .word 0xf1c5 - movx.w @r5,x0 movy.w @r6,y0 ! .word 0xf205 - movx.w @r5,x0 movy.w @r6,y1 ! .word 0xf245 - movx.w @r5,x1 movy.w @r6,y0 ! .word 0xf285 - movx.w @r5,x1 movy.w @r6,y1 ! .word 0xf2c5 - movx.w @r5,x0 movy.w @r7,y0 ! .word 0xf305 - movx.w @r5,x0 movy.w @r7,y1 ! .word 0xf345 - movx.w @r5,x1 movy.w @r7,y0 ! .word 0xf385 - movx.w @r5,x1 movy.w @r7,y1 ! .word 0xf3c5 - movx.w @r4,x0 movy.w @r6+,y0 ! .word 0xf006 - movx.w @r4,x0 movy.w @r6+,y1 ! .word 0xf046 - movx.w @r4,x1 movy.w @r6+,y0 ! .word 0xf086 - movx.w @r4,x1 movy.w @r6+,y1 ! .word 0xf0c6 - movx.w @r4,x0 movy.w @r7+,y0 ! .word 0xf106 - movx.w @r4,x0 movy.w @r7+,y1 ! .word 0xf146 - movx.w @r4,x1 movy.w @r7+,y0 ! .word 0xf186 - movx.w @r4,x1 movy.w @r7+,y1 ! .word 0xf1c6 - movx.w @r5,x0 movy.w @r6+,y0 ! .word 0xf206 - movx.w @r5,x0 movy.w @r6+,y1 ! .word 0xf246 - movx.w @r5,x1 movy.w @r6+,y0 ! .word 0xf286 - movx.w @r5,x1 movy.w @r6+,y1 ! .word 0xf2c6 - movx.w @r5,x0 movy.w @r7+,y0 ! .word 0xf306 - movx.w @r5,x0 movy.w @r7+,y1 ! .word 0xf346 - movx.w @r5,x1 movy.w @r7+,y0 ! .word 0xf386 - movx.w @r5,x1 movy.w @r7+,y1 ! .word 0xf3c6 - movx.w @r4,x0 movy.w @r6+r9,y0 ! .word 0xf007 - movx.w @r4,x0 movy.w @r6+r9,y1 ! .word 0xf047 - movx.w @r4,x1 movy.w @r6+r9,y0 ! .word 0xf087 - movx.w @r4,x1 movy.w @r6+r9,y1 ! .word 0xf0c7 - movx.w @r4,x0 movy.w @r7+r9,y0 ! .word 0xf107 - movx.w @r4,x0 movy.w @r7+r9,y1 ! .word 0xf147 - movx.w @r4,x1 movy.w @r7+r9,y0 ! .word 0xf187 - movx.w @r4,x1 movy.w @r7+r9,y1 ! .word 0xf1c7 - movx.w @r5,x0 movy.w @r6+r9,y0 ! .word 0xf207 - movx.w @r5,x0 movy.w @r6+r9,y1 ! .word 0xf247 - movx.w @r5,x1 movy.w @r6+r9,y0 ! .word 0xf287 - movx.w @r5,x1 movy.w @r6+r9,y1 ! .word 0xf2c7 - movx.w @r5,x0 movy.w @r7+r9,y0 ! .word 0xf307 - movx.w @r5,x0 movy.w @r7+r9,y1 ! .word 0xf347 - movx.w @r5,x1 movy.w @r7+r9,y0 ! .word 0xf387 - movx.w @r5,x1 movy.w @r7+r9,y1 ! .word 0xf3c7 - movx.w @r4+,x0 movy.w @r6,y0 ! .word 0xf009 - movx.w @r4+,x0 movy.w @r6,y1 ! .word 0xf049 - movx.w @r4+,x1 movy.w @r6,y0 ! .word 0xf089 - movx.w @r4+,x1 movy.w @r6,y1 ! .word 0xf0c9 - movx.w @r4+,x0 movy.w @r7,y0 ! .word 0xf109 - movx.w @r4+,x0 movy.w @r7,y1 ! .word 0xf149 - movx.w @r4+,x1 movy.w @r7,y0 ! .word 0xf189 - movx.w @r4+,x1 movy.w @r7,y1 ! .word 0xf1c9 - movx.w @r5+,x0 movy.w @r6,y0 ! .word 0xf209 - movx.w @r5+,x0 movy.w @r6,y1 ! .word 0xf249 - movx.w @r5+,x1 movy.w @r6,y0 ! .word 0xf289 - movx.w @r5+,x1 movy.w @r6,y1 ! .word 0xf2c9 - movx.w @r5+,x0 movy.w @r7,y0 ! .word 0xf309 - movx.w @r5+,x0 movy.w @r7,y1 ! .word 0xf349 - movx.w @r5+,x1 movy.w @r7,y0 ! .word 0xf389 - movx.w @r5+,x1 movy.w @r7,y1 ! .word 0xf3c9 - movx.w @r4+,x0 movy.w @r6+,y0 ! .word 0xf00a - movx.w @r4+,x0 movy.w @r6+,y1 ! .word 0xf04a - movx.w @r4+,x1 movy.w @r6+,y0 ! .word 0xf08a - movx.w @r4+,x1 movy.w @r6+,y1 ! .word 0xf0ca - movx.w @r4+,x0 movy.w @r7+,y0 ! .word 0xf10a - movx.w @r4+,x0 movy.w @r7+,y1 ! .word 0xf14a - movx.w @r4+,x1 movy.w @r7+,y0 ! .word 0xf18a - movx.w @r4+,x1 movy.w @r7+,y1 ! .word 0xf1ca - movx.w @r5+,x0 movy.w @r6+,y0 ! .word 0xf20a - movx.w @r5+,x0 movy.w @r6+,y1 ! .word 0xf24a - movx.w @r5+,x1 movy.w @r6+,y0 ! .word 0xf28a - movx.w @r5+,x1 movy.w @r6+,y1 ! .word 0xf2ca - movx.w @r5+,x0 movy.w @r7+,y0 ! .word 0xf30a - movx.w @r5+,x0 movy.w @r7+,y1 ! .word 0xf34a - movx.w @r5+,x1 movy.w @r7+,y0 ! .word 0xf38a - movx.w @r5+,x1 movy.w @r7+,y1 ! .word 0xf3ca - movx.w @r4+,x0 movy.w @r6+r9,y0 ! .word 0xf00b - movx.w @r4+,x0 movy.w @r6+r9,y1 ! .word 0xf04b - movx.w @r4+,x1 movy.w @r6+r9,y0 ! .word 0xf08b - movx.w @r4+,x1 movy.w @r6+r9,y1 ! .word 0xf0cb - movx.w @r4+,x0 movy.w @r7+r9,y0 ! .word 0xf10b - movx.w @r4+,x0 movy.w @r7+r9,y1 ! .word 0xf14b - movx.w @r4+,x1 movy.w @r7+r9,y0 ! .word 0xf18b - movx.w @r4+,x1 movy.w @r7+r9,y1 ! .word 0xf1cb - movx.w @r5+,x0 movy.w @r6+r9,y0 ! .word 0xf20b - movx.w @r5+,x0 movy.w @r6+r9,y1 ! .word 0xf24b - movx.w @r5+,x1 movy.w @r6+r9,y0 ! .word 0xf28b - movx.w @r5+,x1 movy.w @r6+r9,y1 ! .word 0xf2cb - movx.w @r5+,x0 movy.w @r7+r9,y0 ! .word 0xf30b - movx.w @r5+,x0 movy.w @r7+r9,y1 ! .word 0xf34b - movx.w @r5+,x1 movy.w @r7+r9,y0 ! .word 0xf38b - movx.w @r5+,x1 movy.w @r7+r9,y1 ! .word 0xf3cb - movx.w @r4+r8,x0 movy.w @r6,y0 ! .word 0xf00d - movx.w @r4+r8,x0 movy.w @r6,y1 ! .word 0xf04d - movx.w @r4+r8,x1 movy.w @r6,y0 ! .word 0xf08d - movx.w @r4+r8,x1 movy.w @r6,y1 ! .word 0xf0cd - movx.w @r4+r8,x0 movy.w @r7,y0 ! .word 0xf10d - movx.w @r4+r8,x0 movy.w @r7,y1 ! .word 0xf14d - movx.w @r4+r8,x1 movy.w @r7,y0 ! .word 0xf18d - movx.w @r4+r8,x1 movy.w @r7,y1 ! .word 0xf1cd - movx.w @r5+r8,x0 movy.w @r6,y0 ! .word 0xf20d - movx.w @r5+r8,x0 movy.w @r6,y1 ! .word 0xf24d - movx.w @r5+r8,x1 movy.w @r6,y0 ! .word 0xf28d - movx.w @r5+r8,x1 movy.w @r6,y1 ! .word 0xf2cd - movx.w @r5+r8,x0 movy.w @r7,y0 ! .word 0xf30d - movx.w @r5+r8,x0 movy.w @r7,y1 ! .word 0xf34d - movx.w @r5+r8,x1 movy.w @r7,y0 ! .word 0xf38d - movx.w @r5+r8,x1 movy.w @r7,y1 ! .word 0xf3cd - movx.w @r4+r8,x0 movy.w @r6+,y0 ! .word 0xf00e - movx.w @r4+r8,x0 movy.w @r6+,y1 ! .word 0xf04e - movx.w @r4+r8,x1 movy.w @r6+,y0 ! .word 0xf08e - movx.w @r4+r8,x1 movy.w @r6+,y1 ! .word 0xf0ce - movx.w @r4+r8,x0 movy.w @r7+,y0 ! .word 0xf10e - movx.w @r4+r8,x0 movy.w @r7+,y1 ! .word 0xf14e - movx.w @r4+r8,x1 movy.w @r7+,y0 ! .word 0xf18e - movx.w @r4+r8,x1 movy.w @r7+,y1 ! .word 0xf1ce - movx.w @r5+r8,x0 movy.w @r6+,y0 ! .word 0xf20e - movx.w @r5+r8,x0 movy.w @r6+,y1 ! .word 0xf24e - movx.w @r5+r8,x1 movy.w @r6+,y0 ! .word 0xf28e - movx.w @r5+r8,x1 movy.w @r6+,y1 ! .word 0xf2ce - movx.w @r5+r8,x0 movy.w @r7+,y0 ! .word 0xf30e - movx.w @r5+r8,x0 movy.w @r7+,y1 ! .word 0xf34e - movx.w @r5+r8,x1 movy.w @r7+,y0 ! .word 0xf38e - movx.w @r5+r8,x1 movy.w @r7+,y1 ! .word 0xf3ce - movx.w @r4+r8,x0 movy.w @r6+r9,y0 ! .word 0xf00f - movx.w @r4+r8,x0 movy.w @r6+r9,y1 ! .word 0xf04f - movx.w @r4+r8,x1 movy.w @r6+r9,y0 ! .word 0xf08f - movx.w @r4+r8,x1 movy.w @r6+r9,y1 ! .word 0xf0cf - movx.w @r4+r8,x0 movy.w @r7+r9,y0 ! .word 0xf10f - movx.w @r4+r8,x0 movy.w @r7+r9,y1 ! .word 0xf14f - movx.w @r4+r8,x1 movy.w @r7+r9,y0 ! .word 0xf18f - movx.w @r4+r8,x1 movy.w @r7+r9,y1 ! .word 0xf1cf - movx.w @r5+r8,x0 movy.w @r6+r9,y0 ! .word 0xf20f - movx.w @r5+r8,x0 movy.w @r6+r9,y1 ! .word 0xf24f - movx.w @r5+r8,x1 movy.w @r6+r9,y0 ! .word 0xf28f - movx.w @r5+r8,x1 movy.w @r6+r9,y1 ! .word 0xf2cf - movx.w @r5+r8,x0 movy.w @r7+r9,y0 ! .word 0xf30f - movx.w @r5+r8,x0 movy.w @r7+r9,y1 ! .word 0xf34f - movx.w @r5+r8,x1 movy.w @r7+r9,y0 ! .word 0xf38f - movx.w @r5+r8,x1 movy.w @r7+r9,y1 ! .word 0xf3cf - movx.w @r4,x0 movy.w a0,@r6 ! .word 0xf015 - movx.w @r4,x0 movy.w a1,@r6 ! .word 0xf055 - movx.w @r4,x1 movy.w a0,@r6 ! .word 0xf095 - movx.w @r4,x1 movy.w a1,@r6 ! .word 0xf0d5 - movx.w @r4,x0 movy.w a0,@r7 ! .word 0xf115 - movx.w @r4,x0 movy.w a1,@r7 ! .word 0xf155 - movx.w @r4,x1 movy.w a0,@r7 ! .word 0xf195 - movx.w @r4,x1 movy.w a1,@r7 ! .word 0xf1d5 - movx.w @r5,x0 movy.w a0,@r6 ! .word 0xf215 - movx.w @r5,x0 movy.w a1,@r6 ! .word 0xf255 - movx.w @r5,x1 movy.w a0,@r6 ! .word 0xf295 - movx.w @r5,x1 movy.w a1,@r6 ! .word 0xf2d5 - movx.w @r5,x0 movy.w a0,@r7 ! .word 0xf315 - movx.w @r5,x0 movy.w a1,@r7 ! .word 0xf355 - movx.w @r5,x1 movy.w a0,@r7 ! .word 0xf395 - movx.w @r5,x1 movy.w a1,@r7 ! .word 0xf3d5 - movx.w @r4,x0 movy.w a0,@r6+ ! .word 0xf016 - movx.w @r4,x0 movy.w a1,@r6+ ! .word 0xf056 - movx.w @r4,x1 movy.w a0,@r6+ ! .word 0xf096 - movx.w @r4,x1 movy.w a1,@r6+ ! .word 0xf0d6 - movx.w @r4,x0 movy.w a0,@r7+ ! .word 0xf116 - movx.w @r4,x0 movy.w a1,@r7+ ! .word 0xf156 - movx.w @r4,x1 movy.w a0,@r7+ ! .word 0xf196 - movx.w @r4,x1 movy.w a1,@r7+ ! .word 0xf1d6 - movx.w @r5,x0 movy.w a0,@r6+ ! .word 0xf216 - movx.w @r5,x0 movy.w a1,@r6+ ! .word 0xf256 - movx.w @r5,x1 movy.w a0,@r6+ ! .word 0xf296 - movx.w @r5,x1 movy.w a1,@r6+ ! .word 0xf2d6 - movx.w @r5,x0 movy.w a0,@r7+ ! .word 0xf316 - movx.w @r5,x0 movy.w a1,@r7+ ! .word 0xf356 - movx.w @r5,x1 movy.w a0,@r7+ ! .word 0xf396 - movx.w @r5,x1 movy.w a1,@r7+ ! .word 0xf3d6 - movx.w @r4,x0 movy.w a0,@r6+r9 ! .word 0xf017 - movx.w @r4,x0 movy.w a1,@r6+r9 ! .word 0xf057 - movx.w @r4,x1 movy.w a0,@r6+r9 ! .word 0xf097 - movx.w @r4,x1 movy.w a1,@r6+r9 ! .word 0xf0d7 - movx.w @r4,x0 movy.w a0,@r7+r9 ! .word 0xf117 - movx.w @r4,x0 movy.w a1,@r7+r9 ! .word 0xf157 - movx.w @r4,x1 movy.w a0,@r7+r9 ! .word 0xf197 - movx.w @r4,x1 movy.w a1,@r7+r9 ! .word 0xf1d7 - movx.w @r5,x0 movy.w a0,@r6+r9 ! .word 0xf217 - movx.w @r5,x0 movy.w a1,@r6+r9 ! .word 0xf257 - movx.w @r5,x1 movy.w a0,@r6+r9 ! .word 0xf297 - movx.w @r5,x1 movy.w a1,@r6+r9 ! .word 0xf2d7 - movx.w @r5,x0 movy.w a0,@r7+r9 ! .word 0xf317 - movx.w @r5,x0 movy.w a1,@r7+r9 ! .word 0xf357 - movx.w @r5,x1 movy.w a0,@r7+r9 ! .word 0xf397 - movx.w @r5,x1 movy.w a1,@r7+r9 ! .word 0xf3d7 - movx.w @r4+,x0 movy.w a0,@r6 ! .word 0xf019 - movx.w @r4+,x0 movy.w a1,@r6 ! .word 0xf059 - movx.w @r4+,x1 movy.w a0,@r6 ! .word 0xf099 - movx.w @r4+,x1 movy.w a1,@r6 ! .word 0xf0d9 - movx.w @r4+,x0 movy.w a0,@r7 ! .word 0xf119 - movx.w @r4+,x0 movy.w a1,@r7 ! .word 0xf159 - movx.w @r4+,x1 movy.w a0,@r7 ! .word 0xf199 - movx.w @r4+,x1 movy.w a1,@r7 ! .word 0xf1d9 - movx.w @r5+,x0 movy.w a0,@r6 ! .word 0xf219 - movx.w @r5+,x0 movy.w a1,@r6 ! .word 0xf259 - movx.w @r5+,x1 movy.w a0,@r6 ! .word 0xf299 - movx.w @r5+,x1 movy.w a1,@r6 ! .word 0xf2d9 - movx.w @r5+,x0 movy.w a0,@r7 ! .word 0xf319 - movx.w @r5+,x0 movy.w a1,@r7 ! .word 0xf359 - movx.w @r5+,x1 movy.w a0,@r7 ! .word 0xf399 - movx.w @r5+,x1 movy.w a1,@r7 ! .word 0xf3d9 - movx.w @r4+,x0 movy.w a0,@r6+ ! .word 0xf01a - movx.w @r4+,x0 movy.w a1,@r6+ ! .word 0xf05a - movx.w @r4+,x1 movy.w a0,@r6+ ! .word 0xf09a - movx.w @r4+,x1 movy.w a1,@r6+ ! .word 0xf0da - movx.w @r4+,x0 movy.w a0,@r7+ ! .word 0xf11a - movx.w @r4+,x0 movy.w a1,@r7+ ! .word 0xf15a - movx.w @r4+,x1 movy.w a0,@r7+ ! .word 0xf19a - movx.w @r4+,x1 movy.w a1,@r7+ ! .word 0xf1da - movx.w @r5+,x0 movy.w a0,@r6+ ! .word 0xf21a - movx.w @r5+,x0 movy.w a1,@r6+ ! .word 0xf25a - movx.w @r5+,x1 movy.w a0,@r6+ ! .word 0xf29a - movx.w @r5+,x1 movy.w a1,@r6+ ! .word 0xf2da - movx.w @r5+,x0 movy.w a0,@r7+ ! .word 0xf31a - movx.w @r5+,x0 movy.w a1,@r7+ ! .word 0xf35a - movx.w @r5+,x1 movy.w a0,@r7+ ! .word 0xf39a - movx.w @r5+,x1 movy.w a1,@r7+ ! .word 0xf3da - movx.w @r4+,x0 movy.w a0,@r6+r9 ! .word 0xf01b - movx.w @r4+,x0 movy.w a1,@r6+r9 ! .word 0xf05b - movx.w @r4+,x1 movy.w a0,@r6+r9 ! .word 0xf09b - movx.w @r4+,x1 movy.w a1,@r6+r9 ! .word 0xf0db - movx.w @r4+,x0 movy.w a0,@r7+r9 ! .word 0xf11b - movx.w @r4+,x0 movy.w a1,@r7+r9 ! .word 0xf15b - movx.w @r4+,x1 movy.w a0,@r7+r9 ! .word 0xf19b - movx.w @r4+,x1 movy.w a1,@r7+r9 ! .word 0xf1db - movx.w @r5+,x0 movy.w a0,@r6+r9 ! .word 0xf21b - movx.w @r5+,x0 movy.w a1,@r6+r9 ! .word 0xf25b - movx.w @r5+,x1 movy.w a0,@r6+r9 ! .word 0xf29b - movx.w @r5+,x1 movy.w a1,@r6+r9 ! .word 0xf2db - movx.w @r5+,x0 movy.w a0,@r7+r9 ! .word 0xf31b - movx.w @r5+,x0 movy.w a1,@r7+r9 ! .word 0xf35b - movx.w @r5+,x1 movy.w a0,@r7+r9 ! .word 0xf39b - movx.w @r5+,x1 movy.w a1,@r7+r9 ! .word 0xf3db - movx.w @r4+r8,x0 movy.w a0,@r6 ! .word 0xf01d - movx.w @r4+r8,x0 movy.w a1,@r6 ! .word 0xf05d - movx.w @r4+r8,x1 movy.w a0,@r6 ! .word 0xf09d - movx.w @r4+r8,x1 movy.w a1,@r6 ! .word 0xf0dd - movx.w @r4+r8,x0 movy.w a0,@r7 ! .word 0xf11d - movx.w @r4+r8,x0 movy.w a1,@r7 ! .word 0xf15d - movx.w @r4+r8,x1 movy.w a0,@r7 ! .word 0xf19d - movx.w @r4+r8,x1 movy.w a1,@r7 ! .word 0xf1dd - movx.w @r5+r8,x0 movy.w a0,@r6 ! .word 0xf21d - movx.w @r5+r8,x0 movy.w a1,@r6 ! .word 0xf25d - movx.w @r5+r8,x1 movy.w a0,@r6 ! .word 0xf29d - movx.w @r5+r8,x1 movy.w a1,@r6 ! .word 0xf2dd - movx.w @r5+r8,x0 movy.w a0,@r7 ! .word 0xf31d - movx.w @r5+r8,x0 movy.w a1,@r7 ! .word 0xf35d - movx.w @r5+r8,x1 movy.w a0,@r7 ! .word 0xf39d - movx.w @r5+r8,x1 movy.w a1,@r7 ! .word 0xf3dd - movx.w @r4+r8,x0 movy.w a0,@r6+ ! .word 0xf01e - movx.w @r4+r8,x0 movy.w a1,@r6+ ! .word 0xf05e - movx.w @r4+r8,x1 movy.w a0,@r6+ ! .word 0xf09e - movx.w @r4+r8,x1 movy.w a1,@r6+ ! .word 0xf0de - movx.w @r4+r8,x0 movy.w a0,@r7+ ! .word 0xf11e - movx.w @r4+r8,x0 movy.w a1,@r7+ ! .word 0xf15e - movx.w @r4+r8,x1 movy.w a0,@r7+ ! .word 0xf19e - movx.w @r4+r8,x1 movy.w a1,@r7+ ! .word 0xf1de - movx.w @r5+r8,x0 movy.w a0,@r6+ ! .word 0xf21e - movx.w @r5+r8,x0 movy.w a1,@r6+ ! .word 0xf25e - movx.w @r5+r8,x1 movy.w a0,@r6+ ! .word 0xf29e - movx.w @r5+r8,x1 movy.w a1,@r6+ ! .word 0xf2de - movx.w @r5+r8,x0 movy.w a0,@r7+ ! .word 0xf31e - movx.w @r5+r8,x0 movy.w a1,@r7+ ! .word 0xf35e - movx.w @r5+r8,x1 movy.w a0,@r7+ ! .word 0xf39e - movx.w @r5+r8,x1 movy.w a1,@r7+ ! .word 0xf3de - movx.w @r4+r8,x0 movy.w a0,@r6+r9 ! .word 0xf01f - movx.w @r4+r8,x0 movy.w a1,@r6+r9 ! .word 0xf05f - movx.w @r4+r8,x1 movy.w a0,@r6+r9 ! .word 0xf09f - movx.w @r4+r8,x1 movy.w a1,@r6+r9 ! .word 0xf0df - movx.w @r4+r8,x0 movy.w a0,@r7+r9 ! .word 0xf11f - movx.w @r4+r8,x0 movy.w a1,@r7+r9 ! .word 0xf15f - movx.w @r4+r8,x1 movy.w a0,@r7+r9 ! .word 0xf19f - movx.w @r4+r8,x1 movy.w a1,@r7+r9 ! .word 0xf1df - movx.w @r5+r8,x0 movy.w a0,@r6+r9 ! .word 0xf21f - movx.w @r5+r8,x0 movy.w a1,@r6+r9 ! .word 0xf25f - movx.w @r5+r8,x1 movy.w a0,@r6+r9 ! .word 0xf29f - movx.w @r5+r8,x1 movy.w a1,@r6+r9 ! .word 0xf2df - movx.w @r5+r8,x0 movy.w a0,@r7+r9 ! .word 0xf31f - movx.w @r5+r8,x0 movy.w a1,@r7+r9 ! .word 0xf35f - movx.w @r5+r8,x1 movy.w a0,@r7+r9 ! .word 0xf39f - movx.w @r5+r8,x1 movy.w a1,@r7+r9 ! .word 0xf3df - movx.w a0,@r4 movy.w @r6,y0 ! .word 0xf025 - movx.w a0,@r4 movy.w @r6,y1 ! .word 0xf065 - movx.w a1,@r4 movy.w @r6,y0 ! .word 0xf0a5 - movx.w a1,@r4 movy.w @r6,y1 ! .word 0xf0e5 - movx.w a0,@r4 movy.w @r7,y0 ! .word 0xf125 - movx.w a0,@r4 movy.w @r7,y1 ! .word 0xf165 - movx.w a1,@r4 movy.w @r7,y0 ! .word 0xf1a5 - movx.w a1,@r4 movy.w @r7,y1 ! .word 0xf1e5 - movx.w a0,@r5 movy.w @r6,y0 ! .word 0xf225 - movx.w a0,@r5 movy.w @r6,y1 ! .word 0xf265 - movx.w a1,@r5 movy.w @r6,y0 ! .word 0xf2a5 - movx.w a1,@r5 movy.w @r6,y1 ! .word 0xf2e5 - movx.w a0,@r5 movy.w @r7,y0 ! .word 0xf325 - movx.w a0,@r5 movy.w @r7,y1 ! .word 0xf365 - movx.w a0,@r5 movy.w @r7,y1 ! .word 0xf3a5 - movx.w a1,@r5 movy.w @r7,y1 ! .word 0xf3e5 - movx.w a0,@r4 movy.w @r6+,y0 ! .word 0xf026 - movx.w a0,@r4 movy.w @r6+,y1 ! .word 0xf066 - movx.w a1,@r4 movy.w @r6+,y0 ! .word 0xf0a6 - movx.w a1,@r4 movy.w @r6+,y1 ! .word 0xf0e6 - movx.w a0,@r4 movy.w @r7+,y0 ! .word 0xf126 - movx.w a0,@r4 movy.w @r7+,y1 ! .word 0xf166 - movx.w a1,@r4 movy.w @r7+,y0 ! .word 0xf1a6 - movx.w a1,@r4 movy.w @r7+,y1 ! .word 0xf1e6 - movx.w a0,@r5 movy.w @r6+,y0 ! .word 0xf226 - movx.w a0,@r5 movy.w @r6+,y1 ! .word 0xf266 - movx.w a1,@r5 movy.w @r6+,y0 ! .word 0xf2a6 - movx.w a1,@r5 movy.w @r6+,y1 ! .word 0xf2e6 - movx.w a0,@r5 movy.w @r7+,y0 ! .word 0xf326 - movx.w a0,@r5 movy.w @r7+,y1 ! .word 0xf366 - movx.w a1,@r5 movy.w @r7+,y0 ! .word 0xf3a6 - movx.w a1,@r5 movy.w @r7+,y1 ! .word 0xf3e6 - movx.w a0,@r4 movy.w @r6+r9,y0 ! .word 0xf027 - movx.w a0,@r4 movy.w @r6+r9,y1 ! .word 0xf067 - movx.w a1,@r4 movy.w @r6+r9,y0 ! .word 0xf0a7 - movx.w a1,@r4 movy.w @r6+r9,y1 ! .word 0xf0e7 - movx.w a0,@r4 movy.w @r7+r9,y0 ! .word 0xf127 - movx.w a0,@r4 movy.w @r7+r9,y1 ! .word 0xf167 - movx.w a1,@r4 movy.w @r7+r9,y0 ! .word 0xf1a7 - movx.w a1,@r4 movy.w @r7+r9,y1 ! .word 0xf1e7 - movx.w a0,@r5 movy.w @r6+r9,y0 ! .word 0xf227 - movx.w a0,@r5 movy.w @r6+r9,y1 ! .word 0xf267 - movx.w a1,@r5 movy.w @r6+r9,y0 ! .word 0xf2a7 - movx.w a1,@r5 movy.w @r6+r9,y1 ! .word 0xf2e7 - movx.w a0,@r5 movy.w @r7+r9,y0 ! .word 0xf327 - movx.w a0,@r5 movy.w @r7+r9,y1 ! .word 0xf367 - movx.w a1,@r5 movy.w @r7+r9,y0 ! .word 0xf3a7 - movx.w a1,@r5 movy.w @r7+r9,y1 ! .word 0xf3e7 - movx.w a0,@r4+ movy.w @r6,y0 ! .word 0xf029 - movx.w a0,@r4+ movy.w @r6,y1 ! .word 0xf069 - movx.w a1,@r4+ movy.w @r6,y0 ! .word 0xf0a9 - movx.w a1,@r4+ movy.w @r6,y1 ! .word 0xf0e9 - movx.w a0,@r4+ movy.w @r7,y0 ! .word 0xf129 - movx.w a0,@r4+ movy.w @r7,y1 ! .word 0xf169 - movx.w a1,@r4+ movy.w @r7,y0 ! .word 0xf1a9 - movx.w a1,@r4+ movy.w @r7,y1 ! .word 0xf1e9 - movx.w a0,@r5+ movy.w @r6,y0 ! .word 0xf229 - movx.w a0,@r5+ movy.w @r6,y1 ! .word 0xf269 - movx.w a1,@r5+ movy.w @r6,y0 ! .word 0xf2a9 - movx.w a1,@r5+ movy.w @r6,y1 ! .word 0xf2e9 - movx.w a0,@r5+ movy.w @r7,y0 ! .word 0xf329 - movx.w a0,@r5+ movy.w @r7,y1 ! .word 0xf369 - movx.w a1,@r5+ movy.w @r7,y0 ! .word 0xf3a9 - movx.w a1,@r5+ movy.w @r7,y1 ! .word 0xf3e9 - movx.w a0,@r4+ movy.w @r6+,y0 ! .word 0xf02a - movx.w a0,@r4+ movy.w @r6+,y1 ! .word 0xf06a - movx.w a1,@r4+ movy.w @r6+,y0 ! .word 0xf0aa - movx.w a1,@r4+ movy.w @r6+,y1 ! .word 0xf0ea - movx.w a0,@r4+ movy.w @r7+,y0 ! .word 0xf12a - movx.w a0,@r4+ movy.w @r7+,y1 ! .word 0xf16a - movx.w a1,@r4+ movy.w @r7+,y0 ! .word 0xf1aa - movx.w a1,@r4+ movy.w @r7+,y1 ! .word 0xf1ea - movx.w a0,@r5+ movy.w @r6+,y0 ! .word 0xf22a - movx.w a0,@r5+ movy.w @r6+,y1 ! .word 0xf26a - movx.w a1,@r5+ movy.w @r6+,y0 ! .word 0xf2aa - movx.w a1,@r5+ movy.w @r6+,y1 ! .word 0xf2ea - movx.w a0,@r5+ movy.w @r7+,y0 ! .word 0xf32a - movx.w a0,@r5+ movy.w @r7+,y1 ! .word 0xf36a - movx.w a1,@r5+ movy.w @r7+,y0 ! .word 0xf3aa - movx.w a1,@r5+ movy.w @r7+,y1 ! .word 0xf3ea - movx.w a0,@r4+ movy.w @r6+r9,y0 ! .word 0xf02b - movx.w a0,@r4+ movy.w @r6+r9,y1 ! .word 0xf06b - movx.w a1,@r4+ movy.w @r6+r9,y0 ! .word 0xf0ab - movx.w a1,@r4+ movy.w @r6+r9,y1 ! .word 0xf0eb - movx.w a0,@r4+ movy.w @r7+r9,y0 ! .word 0xf12b - movx.w a0,@r4+ movy.w @r7+r9,y1 ! .word 0xf16b - movx.w a1,@r4+ movy.w @r7+r9,y0 ! .word 0xf1ab - movx.w a1,@r4+ movy.w @r7+r9,y1 ! .word 0xf1eb - movx.w a0,@r5+ movy.w @r6+r9,y0 ! .word 0xf22b - movx.w a0,@r5+ movy.w @r6+r9,y1 ! .word 0xf26b - movx.w a1,@r5+ movy.w @r6+r9,y0 ! .word 0xf2ab - movx.w a1,@r5+ movy.w @r6+r9,y1 ! .word 0xf2eb - movx.w a0,@r5+ movy.w @r7+r9,y0 ! .word 0xf32b - movx.w a0,@r5+ movy.w @r7+r9,y1 ! .word 0xf36b - movx.w a1,@r5+ movy.w @r7+r9,y0 ! .word 0xf3ab - movx.w a1,@r5+ movy.w @r7+r9,y1 ! .word 0xf3eb - movx.w a0,@r4+r8 movy.w @r6,y0 ! .word 0xf02d - movx.w a0,@r4+r8 movy.w @r6,y1 ! .word 0xf06d - movx.w a1,@r4+r8 movy.w @r6,y0 ! .word 0xf0ad - movx.w a1,@r4+r8 movy.w @r6,y1 ! .word 0xf0ed - movx.w a0,@r4+r8 movy.w @r7,y0 ! .word 0xf12d - movx.w a0,@r4+r8 movy.w @r7,y1 ! .word 0xf16d - movx.w a1,@r4+r8 movy.w @r7,y0 ! .word 0xf1ad - movx.w a1,@r4+r8 movy.w @r7,y1 ! .word 0xf1ed - movx.w a0,@r5+r8 movy.w @r6,y0 ! .word 0xf22d - movx.w a0,@r5+r8 movy.w @r6,y1 ! .word 0xf26d - movx.w a1,@r5+r8 movy.w @r6,y0 ! .word 0xf2ad - movx.w a1,@r5+r8 movy.w @r6,y1 ! .word 0xf2ed - movx.w a0,@r5+r8 movy.w @r7,y0 ! .word 0xf32d - movx.w a0,@r5+r8 movy.w @r7,y1 ! .word 0xf36d - movx.w a1,@r5+r8 movy.w @r7,y0 ! .word 0xf3ad - movx.w a1,@r5+r8 movy.w @r7,y1 ! .word 0xf3ed - movx.w a0,@r4+r8 movy.w @r6+,y0 ! .word 0xf02e - movx.w a0,@r4+r8 movy.w @r6+,y1 ! .word 0xf06e - movx.w a1,@r4+r8 movy.w @r6+,y0 ! .word 0xf0ae - movx.w a1,@r4+r8 movy.w @r6+,y1 ! .word 0xf0ee - movx.w a0,@r4+r8 movy.w @r7+,y0 ! .word 0xf12e - movx.w a0,@r4+r8 movy.w @r7+,y1 ! .word 0xf16e - movx.w a1,@r4+r8 movy.w @r7+,y0 ! .word 0xf1ae - movx.w a1,@r4+r8 movy.w @r7+,y1 ! .word 0xf1ee - movx.w a0,@r5+r8 movy.w @r6+,y0 ! .word 0xf22e - movx.w a0,@r5+r8 movy.w @r6+,y1 ! .word 0xf26e - movx.w a1,@r5+r8 movy.w @r6+,y0 ! .word 0xf2ae - movx.w a1,@r5+r8 movy.w @r6+,y1 ! .word 0xf2ee - movx.w a0,@r5+r8 movy.w @r7+,y0 ! .word 0xf32e - movx.w a0,@r5+r8 movy.w @r7+,y1 ! .word 0xf36e - movx.w a1,@r5+r8 movy.w @r7+,y0 ! .word 0xf3ae - movx.w a1,@r5+r8 movy.w @r7+,y1 ! .word 0xf3ee - movx.w a0,@r4+r8 movy.w @r6+r9,y0 ! .word 0xf02f - movx.w a0,@r4+r8 movy.w @r6+r9,y1 ! .word 0xf06f - movx.w a1,@r4+r8 movy.w @r6+r9,y0 ! .word 0xf0af - movx.w a1,@r4+r8 movy.w @r6+r9,y1 ! .word 0xf0ef - movx.w a0,@r4+r8 movy.w @r7+r9,y0 ! .word 0xf12f - movx.w a0,@r4+r8 movy.w @r7+r9,y1 ! .word 0xf16f - movx.w a1,@r4+r8 movy.w @r7+r9,y0 ! .word 0xf1af - movx.w a1,@r4+r8 movy.w @r7+r9,y1 ! .word 0xf1ef - movx.w a0,@r5+r8 movy.w @r6+r9,y0 ! .word 0xf22f - movx.w a0,@r5+r8 movy.w @r6+r9,y1 ! .word 0xf26f - movx.w a1,@r5+r8 movy.w @r6+r9,y0 ! .word 0xf2af - movx.w a1,@r5+r8 movy.w @r6+r9,y1 ! .word 0xf2ef - movx.w a0,@r5+r8 movy.w @r7+r9,y0 ! .word 0xf32f - movx.w a0,@r5+r8 movy.w @r7+r9,y1 ! .word 0xf36f - movx.w a1,@r5+r8 movy.w @r7+r9,y0 ! .word 0xf3af - movx.w a1,@r5+r8 movy.w @r7+r9,y1 ! .word 0xf3ef - -movxwaxydxy: - movx.w @r4,x0 ! - movx.w @r4,y0 ! - movx.w @r4,x1 ! - movx.w @r4,y1 ! - movx.w @r0,x0 ! - movx.w @r0,y0 ! - movx.w @r0,x1 ! - movx.w @r0,y1 ! - movx.w @r5,x0 ! - movx.w @r5,y0 ! - movx.w @r5,x1 ! - movx.w @r5,y1 ! - movx.w @r1,x0 ! - movx.w @r1,y0 ! - movx.w @r1,x1 ! - movx.w @r1,y1 ! - movx.w @r4+,x0 ! - movx.w @r4+,y0 ! - movx.w @r4+,x1 ! - movx.w @r4+,y1 ! - movx.w @r0+,x0 ! - movx.w @r0+,y0 ! - movx.w @r0+,x1 ! - movx.w @r0+,y1 ! - movx.w @r5+,x0 ! - movx.w @r5+,y0 ! - movx.w @r5+,x1 ! - movx.w @r5+,y1 ! - movx.w @r1+,x0 ! - movx.w @r1+,y0 ! - movx.w @r1+,x1 ! - movx.w @r1+,y1 ! - movx.w @r4+r8,x0 ! - movx.w @r4+r8,y0 ! - movx.w @r4+r8,x1 ! - movx.w @r4+r8,y1 ! - movx.w @r0+r8,x0 ! - movx.w @r0+r8,y0 ! - movx.w @r0+r8,x1 ! - movx.w @r0+r8,y1 ! - movx.w @r5+r8,x0 ! - movx.w @r5+r8,y0 ! - movx.w @r5+r8,x1 ! - movx.w @r5+r8,y1 ! - movx.w @r1+r8,x0 ! - movx.w @r1+r8,y0 ! - movx.w @r1+r8,x1 ! - movx.w @r1+r8,y1 ! - -movxwdaxaxy: ! - movx.w a0,@r4 ! - movx.w x0,@r4 ! - movx.w a1,@r4 ! - movx.w x1,@r4 ! - movx.w a0,@r0 ! - movx.w x0,@r0 ! - movx.w a1,@r0 ! - movx.w x1,@r0 ! - movx.w a0,@r5 ! - movx.w x0,@r5 ! - movx.w a1,@r5 ! - movx.w x1,@r5 ! - movx.w a0,@r1 ! - movx.w x0,@r1 ! - movx.w a1,@r1 ! - movx.w x1,@r1 ! - movx.w a0,@r4+ ! - movx.w x0,@r4+ ! - movx.w a1,@r4+ ! - movx.w x1,@r4+ ! - movx.w a0,@r0+ ! - movx.w x0,@r0+ ! - movx.w a1,@r0+ ! - movx.w x1,@r0+ ! - movx.w a0,@r5+ ! - movx.w x0,@r5+ ! - movx.w a1,@r5+ ! - movx.w x1,@r5+ ! - movx.w a0,@r1+ ! - movx.w x0,@r1+ ! - movx.w a1,@r1+ ! - movx.w x1,@r1+ ! - movx.w a0,@r4+r8 ! - movx.w x0,@r4+r8 ! - movx.w a1,@r4+r8 ! - movx.w x1,@r4+r8 ! - movx.w a0,@r0+r8 ! - movx.w x0,@r0+r8 ! - movx.w a1,@r0+r8 ! - movx.w x1,@r0+r8 ! - movx.w a0,@r5+r8 ! - movx.w x0,@r5+r8 ! - movx.w a1,@r5+r8 ! - movx.w x1,@r5+r8 ! - movx.w a0,@r1+r8 ! - movx.w x0,@r1+r8 ! - movx.w a1,@r1+r8 ! - movx.w x1,@r1+r8 ! - -movywayxdyx: ! - movy.w @r6,y0 ! - movy.w @r6,y1 ! - movy.w @r6,x0 ! - movy.w @r6,x1 ! - movy.w @r7,y0 ! - movy.w @r7,y1 ! - movy.w @r7,x0 ! - movy.w @r7,x1 ! - movy.w @r2,y0 ! - movy.w @r2,y1 ! - movy.w @r2,x0 ! - movy.w @r2,x1 ! - movy.w @r3,y0 ! - movy.w @r3,y1 ! - movy.w @r3,x0 ! - movy.w @r3,x1 ! - movy.w @r6+,y0 ! - movy.w @r6+,y1 ! - movy.w @r6+,x0 ! - movy.w @r6+,x1 ! - movy.w @r7+,y0 ! - movy.w @r7+,y1 ! - movy.w @r7+,x0 ! - movy.w @r7+,x1 ! - movy.w @r2+,y0 ! - movy.w @r2+,y1 ! - movy.w @r2+,x0 ! - movy.w @r2+,x1 ! - movy.w @r3+,y0 ! - movy.w @r3+,y1 ! - movy.w @r3+,x0 ! - movy.w @r3+,x1 ! - movy.w @r6+r9,y0 ! - movy.w @r6+r9,y1 ! - movy.w @r6+r9,x0 ! - movy.w @r6+r9,x1 ! - movy.w @r7+r9,y0 ! - movy.w @r7+r9,y1 ! - movy.w @r7+r9,x0 ! - movy.w @r7+r9,x1 ! - movy.w @r2+r9,y0 ! - movy.w @r2+r9,y1 ! - movy.w @r2+r9,x0 ! - movy.w @r2+r9,x1 ! - movy.w @r3+r9,y0 ! - movy.w @r3+r9,y1 ! - movy.w @r3+r9,x0 ! - movy.w @r3+r9,x1 ! - -movywdayayx: - movy.w a0,@r6 - movy.w a1,@r6 - movy.w y0,@r6 - movy.w y1,@r6 - movy.w a0,@r7 - movy.w a1,@r7 - movy.w y0,@r7 - movy.w y1,@r7 - movy.w a0,@r2 - movy.w a1,@r2 - movy.w y0,@r2 - movy.w y1,@r2 - movy.w a0,@r3 - movy.w a1,@r3 - movy.w y0,@r3 - movy.w y1,@r3 - movy.w a0,@r6+ - movy.w a1,@r6+ - movy.w y0,@r6+ - movy.w y1,@r6+ - movy.w a0,@r7+ - movy.w a1,@r7+ - movy.w y0,@r7+ - movy.w y1,@r7+ - movy.w a0,@r2+ - movy.w a1,@r2+ - movy.w y0,@r2+ - movy.w y1,@r2+ - movy.w a0,@r3+ - movy.w a1,@r3+ - movy.w y0,@r3+ - movy.w y1,@r3+ - movy.w a0,@r6+r9 - movy.w a1,@r6+r9 - movy.w y0,@r6+r9 - movy.w y1,@r6+r9 - movy.w a0,@r7+r9 - movy.w a1,@r7+r9 - movy.w y0,@r7+r9 - movy.w y1,@r7+r9 - movy.w a0,@r2+r9 - movy.w a1,@r2+r9 - movy.w y0,@r2+r9 - movy.w y1,@r2+r9 - movy.w a0,@r3+r9 - movy.w a1,@r3+r9 - movy.w y0,@r3+r9 - movy.w y1,@r3+r9 - - mov r4, r0 - mov r4, r1 - mov r4, r2 - mov r4, r3 - mov r4, r5 - mov r4, r6 - mov r5, r7 - -movxlaxydxy: - movx.l @r4,x0 - movx.l @r4,y0 - movx.l @r4,x1 - movx.l @r4,y1 - movx.l @r0,x0 - movx.l @r0,y0 - movx.l @r0,x1 - movx.l @r0,y1 - movx.l @r5,x0 - movx.l @r5,y0 - movx.l @r5,x1 - movx.l @r5,y1 - movx.l @r1,x0 - movx.l @r1,y0 - movx.l @r1,x1 - movx.l @r1,y1 - movx.l @r4+,x0 - movx.l @r4+,y0 - movx.l @r4+,x1 - movx.l @r4+,y1 - movx.l @r0+,x0 - movx.l @r0+,y0 - movx.l @r0+,x1 - movx.l @r0+,y1 - movx.l @r5+,x0 - movx.l @r5+,y0 - movx.l @r5+,x1 - movx.l @r5+,y1 - movx.l @r1+,x0 - movx.l @r1+,y0 - movx.l @r1+,x1 - movx.l @r1+,y1 - movx.l @r4+r8,x0 - movx.l @r4+r8,y0 - movx.l @r4+r8,x1 - movx.l @r4+r8,y1 - movx.l @r0+r8,x0 - movx.l @r0+r8,y0 - movx.l @r0+r8,x1 - movx.l @r0+r8,y1 - movx.l @r5+r8,x0 - movx.l @r5+r8,y0 - movx.l @r5+r8,x1 - movx.l @r5+r8,y1 - movx.l @r1+r8,x0 - movx.l @r1+r8,y0 - movx.l @r1+r8,x1 - movx.l @r1+r8,y1 - -movxldaxaxy: - movx.l a0,@r4 - movx.l x0,@r4 - movx.l a1,@r4 - movx.l x1,@r4 - movx.l a0,@r0 - movx.l x0,@r0 - movx.l a1,@r0 - movx.l x1,@r0 - movx.l a0,@r5 - movx.l x0,@r5 - movx.l a1,@r5 - movx.l x1,@r5 - movx.l a0,@r1 - movx.l x0,@r1 - movx.l a1,@r1 - movx.l x1,@r1 - movx.l a0,@r4+ - movx.l x0,@r4+ - movx.l a1,@r4+ - movx.l x1,@r4+ - movx.l a0,@r0+ - movx.l x0,@r0+ - movx.l a1,@r0+ - movx.l x1,@r0+ - movx.l a0,@r5+ - movx.l x0,@r5+ - movx.l a1,@r5+ - movx.l x1,@r5+ - movx.l a0,@r1+ - movx.l x0,@r1+ - movx.l a1,@r1+ - movx.l x1,@r1+ - movx.l a0,@r4+r8 - movx.l x0,@r4+r8 - movx.l a1,@r4+r8 - movx.l x1,@r4+r8 - movx.l a0,@r0+r8 - movx.l x0,@r0+r8 - movx.l a1,@r0+r8 - movx.l x1,@r0+r8 - movx.l a0,@r5+r8 - movx.l x0,@r5+r8 - movx.l a1,@r5+r8 - movx.l x1,@r5+r8 - movx.l a0,@r1+r8 - movx.l x0,@r1+r8 - movx.l a1,@r1+r8 - movx.l x1,@r1+r8 - -movylayxdyx: - movy.l @r6,y0 - movy.l @r6,y1 - movy.l @r6,x0 - movy.l @r6,x1 - movy.l @r7,y0 - movy.l @r7,y1 - movy.l @r7,x0 - movy.l @r7,x1 - movy.l @r2,y0 - movy.l @r2,y1 - movy.l @r2,x0 - movy.l @r2,x1 - movy.l @r3,y0 - movy.l @r3,y1 - movy.l @r3,x0 - movy.l @r3,x1 - movy.l @r6+,y0 - movy.l @r6+,y1 - movy.l @r6+,x0 - movy.l @r6+,x1 - movy.l @r7+,y0 - movy.l @r7+,y1 - movy.l @r7+,x0 - movy.l @r7+,x1 - movy.l @r2+,y0 - movy.l @r2+,y1 - movy.l @r2+,x0 - movy.l @r2+,x1 - movy.l @r3+,y0 - movy.l @r3+,y1 - movy.l @r3+,x0 - movy.l @r3+,x1 - movy.l @r6+r9,y0 - movy.l @r6+r9,y1 - movy.l @r6+r9,x0 - movy.l @r6+r9,x1 - movy.l @r7+r9,y0 - movy.l @r7+r9,y1 - movy.l @r7+r9,x0 - movy.l @r7+r9,x1 - movy.l @r2+r9,y0 - movy.l @r2+r9,y1 - movy.l @r2+r9,x0 - movy.l @r2+r9,x1 - movy.l @r3+r9,y0 - movy.l @r3+r9,y1 - movy.l @r3+r9,x0 - movy.l @r3+r9,x1 - -movyldayayx: - movy.l a0,@r6 - movy.l a1,@r6 - movy.l y0,@r6 - movy.l y1,@r6 - movy.l a0,@r7 - movy.l a1,@r7 - movy.l y0,@r7 - movy.l y1,@r7 - movy.l a0,@r2 - movy.l a1,@r2 - movy.l y0,@r2 - movy.l y1,@r2 - movy.l a0,@r3 - movy.l a1,@r3 - movy.l y0,@r3 - movy.l y1,@r3 - movy.l a0,@r6+ - movy.l a1,@r6+ - movy.l y0,@r6+ - movy.l y1,@r6+ - movy.l a0,@r7+ - movy.l a1,@r7+ - movy.l y0,@r7+ - movy.l y1,@r7+ - movy.l a0,@r2+ - movy.l a1,@r2+ - movy.l y0,@r2+ - movy.l y1,@r2+ - movy.l a0,@r3+ - movy.l a1,@r3+ - movy.l y0,@r3+ - movy.l y1,@r3+ - movy.l a0,@r6+r9 - movy.l a1,@r6+r9 - movy.l y0,@r6+r9 - movy.l y1,@r6+r9 - movy.l a0,@r7+r9 - movy.l a1,@r7+r9 - movy.l y0,@r7+r9 - movy.l y1,@r7+r9 - movy.l a0,@r2+r9 - movy.l a1,@r2+r9 - movy.l y0,@r2+r9 - movy.l y1,@r2+r9 - movy.l a0,@r3+r9 - movy.l a1,@r3+r9 - movy.l y0,@r3+r9 - movy.l y1,@r3+r9 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/pabs.s b/sim/testsuite/sim/sh/pabs.s deleted file mode 100644 index 6a9e4f24226..00000000000 --- a/sim/testsuite/sim/sh/pabs.s +++ /dev/null @@ -1,54 +0,0 @@ -# sh testcase for pabs -# mach: shdsp -# as(shdsp): -defsym sim_cpu=1 -dsp - - # FIXME: opcode table ambiguity in ignored bits 4-7. - - .include "testutils.inc" - - start - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - pabs x0, x1 - pabs y0, y1 - assert_sreg 0x5a5a5a5b, x1 - assert_sreg 0x5a5a5a5b, y1 - pabs x1, x0 - pabs y1, y0 - assert_sreg 0x5a5a5a5b, x0 - assert_sreg 0x5a5a5a5b, y0 - - set_dcfalse - dct pabs a0, a0 - dct pabs m0, m0 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, m0 - set_dctrue - dct pabs a0, a0 - dct pabs m0, m0 - assert_sreg 0x5a5a5a5b, a0 - assert_sreg2 0x5a5a5a5b, m0 - - set_dctrue - dcf pabs a1, a1 - dcf pabs m1, m1 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg2 0xa5a5a5a5, m1 - set_dcfalse - dcf pabs a1, a1 - dcf pabs m1, m1 - assert_sreg2 0x5a5a5a5b, a1 - assert_sreg2 0x5a5a5a5b, m1 - - test_grs_a5a5 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/padd.s b/sim/testsuite/sim/sh/padd.s deleted file mode 100644 index 072935dcdf5..00000000000 --- a/sim/testsuite/sim/sh/padd.s +++ /dev/null @@ -1,54 +0,0 @@ -# sh testcase for padd -# mach: shdsp -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - padd x0, y0, a0 - assert_sreg 0x4b4b4b4a, a0 - - # 2 + 2 = 4 - mov #2, r0 - lds r0, x0 - lds r0, y0 - padd x0, y0, a0 - assert_sreg 4, a0 - - set_dcfalse - dct padd x0, y0, a1 - assert_sreg2 0xa5a5a5a5, a1 - set_dctrue - dct padd x0, y0, a1 - assert_sreg2 4, a1 - - set_dctrue - dcf padd x0, y0, m1 - assert_sreg2 0xa5a5a5a5, m1 - set_dcfalse - dcf padd x0, y0, m1 - assert_sreg2 4, m1 - - # padd / pmuls - - padd x0, y0, y0 pmuls x1, y1, m1 - assert_sreg 4, y0 - assert_sreg2 0x3fc838b2, m1 ! (int) 0xa5a5 x (int) 0xa5a5 x 2 - - set_greg 0xa5a5a5a5, r0 - test_grs_a5a5 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/paddc.s b/sim/testsuite/sim/sh/paddc.s deleted file mode 100644 index 0dd3b67b172..00000000000 --- a/sim/testsuite/sim/sh/paddc.s +++ /dev/null @@ -1,39 +0,0 @@ -# sh testcase for paddc -# mach: shdsp -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - # 2 + 2 = 4 - set_dcfalse - mov #2, r0 - lds r0, x0 - lds r0, y0 - paddc x0, y0, a0 - assert_sreg 4, a0 - - # 2 + 2 + carry = 5 - set_dctrue - paddc x0, y0, a1 - assert_sreg2 5, a1 - - set_greg 0xa5a5a5a5, r0 - test_grs_a5a5 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/pand.s b/sim/testsuite/sim/sh/pand.s deleted file mode 100644 index cddf05892cb..00000000000 --- a/sim/testsuite/sim/sh/pand.s +++ /dev/null @@ -1,48 +0,0 @@ -# sh testcase for pand -# mach: shdsp -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - pand x0, y0, a0 - assert_sreg 0xa5a50000, a0 - - # 0xa5a5a5a5 & 0x5a5a5a5a == 0 - set_greg 0x5a5a5a5a r0 - lds r0, x0 - pand x0, y0, a0 - assert_sreg 0, a0 - - set_dcfalse - dct pand x0, y0, m0 - assert_sreg2 0xa5a5a5a5, m0 - set_dctrue - dct pand x0, y0, m0 - assert_sreg2 0, m0 - - set_dctrue - dcf pand x0, y0, m1 - assert_sreg2 0xa5a5a5a5, m1 - set_dcfalse - dcf pand x0, y0, m1 - assert_sreg2 0, m1 - - set_greg 0xa5a5a5a5, r0 - test_grs_a5a5 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg2 0xa5a5a5a5, a1 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/pclr.s b/sim/testsuite/sim/sh/pclr.s deleted file mode 100644 index c396f832dee..00000000000 --- a/sim/testsuite/sim/sh/pclr.s +++ /dev/null @@ -1,65 +0,0 @@ -# sh testcase for pclr -# mach: shdsp -# as(shdsp): -defsym sim_cpu=1 -dsp - - # FIXME: opcode table ambiguity in ignored bits 4-7. - - .include "testutils.inc" - - start -pclr_cc: - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - assert_sreg 0xa5a5a5a5, x0 - pclr x0 - assert_sreg 0, x0 - - set_dcfalse - dct pclr x1 - assert_sreg 0xa5a5a5a5, x1 - set_dctrue - dct pclr x1 - assert_sreg 0, x1 - - set_dctrue - dcf pclr y0 - assert_sreg 0xa5a5a5a5, y0 - set_dcfalse - dcf pclr y0 - assert_sreg 0, y0 - - test_grs_a5a5 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - -pclr_pmuls: - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - pclr x0 pmuls y0, y1, a0 - - assert_sreg 0, x0 - assert_sreg 0x3fc838b2, a0 ! 0xa5a5 x 0xa5a5 - - test_grs_a5a5 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/pdec.s b/sim/testsuite/sim/sh/pdec.s deleted file mode 100644 index fa4b6a56e9c..00000000000 --- a/sim/testsuite/sim/sh/pdec.s +++ /dev/null @@ -1,110 +0,0 @@ -# sh testcase for pdec -# mach: shdsp -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -pdecx: - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - pdec x0, y0 - assert_sreg 0xa5a40000, y0 - - test_grs_a5a5 - assert_sreg 0xa5a5a5a5, x0 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - -pdecy: - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - pdec y0, x0 - assert_sreg 0xa5a40000, x0 - - test_grs_a5a5 - assert_sreg 0xa5a5a5a5, y0 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - -dct_pdecx: - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - set_dcfalse - dct pdec x0, y0 - assert_sreg 0xa5a5a5a5, y0 - set_dctrue - dct pdec x0, y0 - assert_sreg 0xa5a40000, y0 - - test_grs_a5a5 - assert_sreg 0xa5a5a5a5, x0 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - -dcf_pdecy: - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - set_dctrue - dcf pdec y0, x0 - assert_sreg 0xa5a5a5a5, x0 - set_dcfalse - dcf pdec y0, x0 - assert_sreg 0xa5a40000, x0 - - test_grs_a5a5 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y0 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/pdmsb.s b/sim/testsuite/sim/sh/pdmsb.s deleted file mode 100644 index 0cb78293265..00000000000 --- a/sim/testsuite/sim/sh/pdmsb.s +++ /dev/null @@ -1,230 +0,0 @@ -# sh testcase for pdmsb -# mach: shdsp -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - set_sreg 0x0, x0 -L0: pdmsb x0, x1 -# assert_sreg 31<<16, x1 - set_sreg 0x1, x0 -L1: pdmsb x0, x1 - assert_sreg 30<<16, x1 - set_sreg 0x3, x0 -L2: pdmsb x0, x1 - assert_sreg 29<<16, x1 - set_sreg 0x7, x0 -L3: pdmsb x0, x1 - assert_sreg 28<<16, x1 - set_sreg 0xf, x0 -L4: pdmsb x0, x1 - assert_sreg 27<<16, x1 - set_sreg 0x1f, x0 -L5: pdmsb x0, x1 - assert_sreg 26<<16, x1 - set_sreg 0x3f, x0 -L6: pdmsb x0, x1 - assert_sreg 25<<16, x1 - set_sreg 0x7f, x0 -L7: pdmsb x0, x1 - assert_sreg 24<<16, x1 - set_sreg 0xff, x0 -L8: pdmsb x0, x1 - assert_sreg 23<<16, x1 - - set_sreg 0x1ff, x0 -L9: pdmsb x0, x1 - assert_sreg 22<<16, x1 - set_sreg 0x3ff, x0 -L10: pdmsb x0, x1 - assert_sreg 21<<16, x1 - set_sreg 0x7ff, x0 -L11: pdmsb x0, x1 - assert_sreg 20<<16, x1 - set_sreg 0xfff, x0 -L12: pdmsb x0, x1 - assert_sreg 19<<16, x1 - set_sreg 0x1fff, x0 -L13: pdmsb x0, x1 - assert_sreg 18<<16, x1 - set_sreg 0x3fff, x0 -L14: pdmsb x0, x1 - assert_sreg 17<<16, x1 - set_sreg 0x7fff, x0 -L15: pdmsb x0, x1 - assert_sreg 16<<16, x1 - set_sreg 0xffff, x0 -L16: pdmsb x0, x1 - assert_sreg 15<<16, x1 - - set_sreg 0x1ffff, x0 -L17: pdmsb x0, x1 - assert_sreg 14<<16, x1 - set_sreg 0x3ffff, x0 -L18: pdmsb x0, x1 - assert_sreg 13<<16, x1 - set_sreg 0x7ffff, x0 -L19: pdmsb x0, x1 - assert_sreg 12<<16, x1 - set_sreg 0xfffff, x0 -L20: pdmsb x0, x1 - assert_sreg 11<<16, x1 - set_sreg 0x1fffff, x0 -L21: pdmsb x0, x1 - assert_sreg 10<<16, x1 - set_sreg 0x3fffff, x0 -L22: pdmsb x0, x1 - assert_sreg 9<<16, x1 - set_sreg 0x7fffff, x0 -L23: pdmsb x0, x1 - assert_sreg 8<<16, x1 - set_sreg 0xffffff, x0 -L24: pdmsb x0, x1 - assert_sreg 7<<16, x1 - - set_sreg 0x1ffffff, x0 -L25: pdmsb x0, x1 - assert_sreg 6<<16, x1 - set_sreg 0x3ffffff, x0 -L26: pdmsb x0, x1 - assert_sreg 5<<16, x1 - set_sreg 0x7ffffff, x0 -L27: pdmsb x0, x1 - assert_sreg 4<<16, x1 - set_sreg 0xfffffff, x0 -L28: pdmsb x0, x1 - assert_sreg 3<<16, x1 - set_sreg 0x1fffffff, x0 -L29: pdmsb x0, x1 - assert_sreg 2<<16, x1 - set_sreg 0x3fffffff, x0 -L30: pdmsb x0, x1 - assert_sreg 1<<16, x1 - set_sreg 0x7fffffff, x0 -L31: pdmsb x0, x1 - assert_sreg 0<<16, x1 - set_sreg 0xffffffff, x0 -L32: pdmsb x0, x1 -# assert_sreg 31<<16, x1 - - set_sreg 0xfffffffe, x0 -L33: pdmsb x0, x1 - assert_sreg 30<<16, x1 - set_sreg 0xfffffffc, x0 -L34: pdmsb x0, x1 - assert_sreg 29<<16, x1 - set_sreg 0xfffffff8, x0 -L35: pdmsb x0, x1 - assert_sreg 28<<16, x1 - set_sreg 0xfffffff0, x0 -L36: pdmsb x0, x1 - assert_sreg 27<<16, x1 - set_sreg 0xffffffe0, x0 -L37: pdmsb x0, x1 - assert_sreg 26<<16, x1 - set_sreg 0xffffffc0, x0 -L38: pdmsb x0, x1 - assert_sreg 25<<16, x1 - set_sreg 0xffffff80, x0 -L39: pdmsb x0, x1 - assert_sreg 24<<16, x1 - set_sreg 0xffffff00, x0 -L40: pdmsb x0, x1 - assert_sreg 23<<16, x1 - - set_sreg 0xfffffe00, x0 -L41: pdmsb x0, x1 - assert_sreg 22<<16, x1 - set_sreg 0xfffffc00, x0 -L42: pdmsb x0, x1 - assert_sreg 21<<16, x1 - set_sreg 0xfffff800, x0 -L43: pdmsb x0, x1 - assert_sreg 20<<16, x1 - set_sreg 0xfffff000, x0 -L44: pdmsb x0, x1 - assert_sreg 19<<16, x1 - set_sreg 0xffffe000, x0 -L45: pdmsb x0, x1 - assert_sreg 18<<16, x1 - set_sreg 0xffffc000, x0 -L46: pdmsb x0, x1 - assert_sreg 17<<16, x1 - set_sreg 0xffff8000, x0 -L47: pdmsb x0, x1 - assert_sreg 16<<16, x1 - set_sreg 0xffff0000, x0 -L48: pdmsb x0, x1 - assert_sreg 15<<16, x1 - - set_sreg 0xfffe0000, x0 -L49: pdmsb x0, x1 - assert_sreg 14<<16, x1 - set_sreg 0xfffc0000, x0 -L50: pdmsb x0, x1 - assert_sreg 13<<16, x1 - set_sreg 0xfff80000, x0 -L51: pdmsb x0, x1 - assert_sreg 12<<16, x1 - set_sreg 0xfff00000, x0 -L52: pdmsb x0, x1 - assert_sreg 11<<16, x1 - set_sreg 0xffe00000, x0 -L53: pdmsb x0, x1 - assert_sreg 10<<16, x1 - set_sreg 0xffc00000, x0 -L54: pdmsb x0, x1 - assert_sreg 9<<16, x1 - set_sreg 0xff800000, x0 -L55: pdmsb x0, x1 - assert_sreg 8<<16, x1 - set_sreg 0xff000000, x0 -L56: pdmsb x0, x1 - assert_sreg 7<<16, x1 - - set_sreg 0xfe000000, x0 -L57: pdmsb x0, x1 - assert_sreg 6<<16, x1 - set_sreg 0xfc000000, x0 -L58: pdmsb x0, x1 - assert_sreg 5<<16, x1 - set_sreg 0xf8000000, x0 -L59: pdmsb x0, x1 - assert_sreg 4<<16, x1 - set_sreg 0xf0000000, x0 -L60: pdmsb x0, x1 - assert_sreg 3<<16, x1 - set_sreg 0xe0000000, x0 -L61: pdmsb x0, x1 - assert_sreg 2<<16, x1 - set_sreg 0xc0000000, x0 -L62: pdmsb x0, x1 - assert_sreg 1<<16, x1 - set_sreg 0x80000000, x0 -L63: pdmsb x0, x1 - assert_sreg 0<<16, x1 - set_sreg 0x00000000, x0 -L64: pdmsb x0, x1 -# assert_sreg 31<<16, x1 - - test_grs_a5a5 - assert_sreg 0xa5a5a5a5, y0 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/pinc.s b/sim/testsuite/sim/sh/pinc.s deleted file mode 100644 index 0067bc00ebe..00000000000 --- a/sim/testsuite/sim/sh/pinc.s +++ /dev/null @@ -1,110 +0,0 @@ -# sh testcase for pinc -# mach: shdsp -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -pincx: - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - pinc x0, y0 - assert_sreg 0xa5a60000, y0 - - test_grs_a5a5 - assert_sreg 0xa5a5a5a5, x0 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - -pincy: - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - pinc y0, x0 - assert_sreg 0xa5a60000, x0 - - test_grs_a5a5 - assert_sreg 0xa5a5a5a5, y0 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - -dct_pincx: - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - set_dcfalse - dct pinc x0, y0 - assert_sreg 0xa5a5a5a5, y0 - set_dctrue - dct pinc x0, y0 - assert_sreg 0xa5a60000, y0 - - test_grs_a5a5 - assert_sreg 0xa5a5a5a5, x0 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - -dcf_pincy: - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - set_dctrue - dcf pinc y0, x0 - assert_sreg 0xa5a5a5a5, x0 - set_dcfalse - dcf pinc y0, x0 - assert_sreg 0xa5a60000, x0 - - test_grs_a5a5 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y0 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/pmuls.s b/sim/testsuite/sim/sh/pmuls.s deleted file mode 100644 index 4cff8787f4e..00000000000 --- a/sim/testsuite/sim/sh/pmuls.s +++ /dev/null @@ -1,33 +0,0 @@ -# sh testcase for pmuls -# mach: shdsp -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - # 2 x 2 = 8 (?) - # (I don't understand why the result is x2, - # but that's what it says in the manual...) - mov #2, r0 - shll16 r0 - lds r0, y0 - lds r0, y1 - pmuls y0, y1, a0 - - assert_sreg 8, a0 - - set_greg 0xa5a5a5a5, r0 - test_grs_a5a5 - pass - exit 0 - diff --git a/sim/testsuite/sim/sh/prnd.s b/sim/testsuite/sim/sh/prnd.s deleted file mode 100644 index 897d5b9ded9..00000000000 --- a/sim/testsuite/sim/sh/prnd.s +++ /dev/null @@ -1,90 +0,0 @@ -# sh testcase for prnd -# mach: shdsp -# as(shdsp): -defsym sim_cpu=1 -dsp - - # FIXME: opcode table ambiguity in ignored bits 4-7. - - .include "testutils.inc" - - start - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - # prnd(0xa5a5a5a5) = 0xa5a60000 - prnd x0, x0 - prnd y0, y0 - assert_sreg 0xa5a60000, x0 - assert_sreg 0xa5a60000, y0 - - # prnd(1) = 1 - mov #1, r0 - shll16 r0 - lds r0, x0 - pcopy x0, y0 - prnd x0, x0 - prnd y0, y0 - assert_sreg 0x10000, x0 - assert_sreg 0x10000, y0 - - # prnd(1.4999999) = 1 - mov #1, r0 - shll8 r0 - or #0x7f, r0 - shll8 r0 - or #0xff, r0 - lds r0, x0 - pcopy x0, y0 - prnd x0, x0 - prnd y0, y0 - assert_sreg 0x10000, x0 - assert_sreg 0x10000, y0 - - # prnd(1.5) = 2 - mov #1, r0 - shll8 r0 - or #0x80, r0 - shll8 r0 - lds r0, x0 - pcopy x0, y0 - prnd x0, x0 - prnd y0, y0 - assert_sreg 0x20000, x0 - assert_sreg 0x20000, y0 - - # dct prnd - set_dcfalse - dct prnd x0, x1 - dct prnd y0, y1 - assert_sreg2 0xa5a5a5a5, x1 - assert_sreg2 0xa5a5a5a5, y1 - set_dctrue - dct prnd x0, x1 - dct prnd y0, y1 - assert_sreg2 0x20000, x1 - assert_sreg2 0x20000, y1 - - # dcf prnd - set_dctrue - dcf prnd x0, m0 - dcf prnd y0, m1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - set_dcfalse - dcf prnd x0, m0 - dcf prnd y0, m1 - assert_sreg2 0x20000, m0 - assert_sreg2 0x20000, m1 - - set_greg 0xa5a5a5a5, r0 - test_grs_a5a5 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, a1 - pass - exit 0 diff --git a/sim/testsuite/sim/sh/pshai.s b/sim/testsuite/sim/sh/pshai.s deleted file mode 100644 index b2cdbbc81b8..00000000000 --- a/sim/testsuite/sim/sh/pshai.s +++ /dev/null @@ -1,200 +0,0 @@ -# sh testcase for psha -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -psha_imm: ! shift arithmetic, immediate operand - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - set_sreg 0x1, a0 - psha #0, a0 - assert_sreg 0x1, a0 - psha #-0, a0 - assert_sreg 0x1, a0 - - psha #1, a0 - assert_sreg 0x2, a0 - psha #-1, a0 - assert_sreg 0x1, a0 - - psha #2, a0 - assert_sreg 0x4, a0 - psha #-2, a0 - assert_sreg 0x1, a0 - - psha #3, a0 - assert_sreg 0x8, a0 - psha #-3, a0 - assert_sreg 0x1, a0 - - psha #4, a0 - assert_sreg 0x10, a0 - psha #-4, a0 - assert_sreg 0x1, a0 - - psha #5, a0 - assert_sreg 0x20, a0 - psha #-5, a0 - assert_sreg 0x1, a0 - - psha #6, a0 - assert_sreg 0x40, a0 - psha #-6, a0 - assert_sreg 0x1, a0 - - psha #7, a0 - assert_sreg 0x80, a0 - psha #-7, a0 - assert_sreg 0x1, a0 - - psha #8, a0 - assert_sreg 0x100, a0 - psha #-8, a0 - assert_sreg 0x1, a0 - - psha #9, a0 - assert_sreg 0x200, a0 - psha #-9, a0 - assert_sreg 0x1, a0 - - psha #10, a0 - assert_sreg 0x400, a0 - psha #-10, a0 - assert_sreg 0x1, a0 - - psha #11, a0 - assert_sreg 0x800, a0 - psha #-11, a0 - assert_sreg 0x1, a0 - - psha #12, a0 - assert_sreg 0x1000, a0 - psha #-12, a0 - assert_sreg 0x1, a0 - - psha #13, a0 - assert_sreg 0x2000, a0 - psha #-13, a0 - assert_sreg 0x1, a0 - - psha #14, a0 - assert_sreg 0x4000, a0 - psha #-14, a0 - assert_sreg 0x1, a0 - - psha #15, a0 - assert_sreg 0x8000, a0 - psha #-15, a0 - assert_sreg 0x1, a0 - - psha #16, a0 - assert_sreg 0x10000, a0 - psha #-16, a0 - assert_sreg 0x1, a0 - - psha #17, a0 - assert_sreg 0x20000, a0 - psha #-17, a0 - assert_sreg 0x1, a0 - - psha #18, a0 - assert_sreg 0x40000, a0 - psha #-18, a0 - assert_sreg 0x1, a0 - - psha #19, a0 - assert_sreg 0x80000, a0 - psha #-19, a0 - assert_sreg 0x1, a0 - - psha #20, a0 - assert_sreg 0x100000, a0 - psha #-20, a0 - assert_sreg 0x1, a0 - - psha #21, a0 - assert_sreg 0x200000, a0 - psha #-21, a0 - assert_sreg 0x1, a0 - - psha #22, a0 - assert_sreg 0x400000, a0 - psha #-22, a0 - assert_sreg 0x1, a0 - - psha #23, a0 - assert_sreg 0x800000, a0 - psha #-23, a0 - assert_sreg 0x1, a0 - - psha #24, a0 - assert_sreg 0x1000000, a0 - psha #-24, a0 - assert_sreg 0x1, a0 - - psha #25, a0 - assert_sreg 0x2000000, a0 - psha #-25, a0 - assert_sreg 0x1, a0 - - psha #26, a0 - assert_sreg 0x4000000, a0 - psha #-26, a0 - assert_sreg 0x1, a0 - - psha #27, a0 - assert_sreg 0x8000000, a0 - psha #-27, a0 - assert_sreg 0x1, a0 - - psha #28, a0 - assert_sreg 0x10000000, a0 - psha #-28, a0 - assert_sreg 0x1, a0 - - psha #29, a0 - assert_sreg 0x20000000, a0 - psha #-29, a0 - assert_sreg 0x1, a0 - - psha #30, a0 - assert_sreg 0x40000000, a0 - psha #-30, a0 - assert_sreg 0x1, a0 - - psha #31, a0 - assert_sreg 0x80000000, a0 - psha #-31, a0 - assert_sreg 0xffffffff, a0 - - psha #32, a0 - assert_sreg 0x00000000, a0 -# I don't grok what should happen here... -# psha #-32, a0 -# assert_sreg 0x0, a0 - - test_grs_a5a5 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg 0xa5a5a5a5, x0 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y0 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - - - pass - exit 0 - diff --git a/sim/testsuite/sim/sh/pshar.s b/sim/testsuite/sim/sh/pshar.s deleted file mode 100644 index 01c4b5fdef2..00000000000 --- a/sim/testsuite/sim/sh/pshar.s +++ /dev/null @@ -1,265 +0,0 @@ -# sh testcase for psha -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -psha_reg: ! shift arithmetic, register operand - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - set_sreg 0x1, x0 - set_sreg 0x0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x10000, y0 - psha x0, y0, x0 - assert_sreg 0x2, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x20000, y0 - psha x0, y0, x0 - assert_sreg 0x4, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x30000, y0 - psha x0, y0, x0 - assert_sreg 0x8, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x40000, y0 - psha x0, y0, x0 - assert_sreg 0x10, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x50000, y0 - psha x0, y0, x0 - assert_sreg 0x20, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x60000, y0 - psha x0, y0, x0 - assert_sreg 0x40, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x70000, y0 - psha x0, y0, x0 - assert_sreg 0x80, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x80000, y0 - psha x0, y0, x0 - assert_sreg 0x100, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x90000, y0 - psha x0, y0, x0 - assert_sreg 0x200, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0xa0000, y0 - psha x0, y0, x0 - assert_sreg 0x400, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0xb0000, y0 - psha x0, y0, x0 - assert_sreg 0x800, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0xc0000, y0 - psha x0, y0, x0 - assert_sreg 0x1000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0xd0000, y0 - psha x0, y0, x0 - assert_sreg 0x2000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0xe0000, y0 - psha x0, y0, x0 - assert_sreg 0x4000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0xf0000, y0 - psha x0, y0, x0 - assert_sreg 0x8000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x100000, y0 - psha x0, y0, x0 - assert_sreg 0x10000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x110000, y0 - psha x0, y0, x0 - assert_sreg 0x20000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x120000, y0 - psha x0, y0, x0 - assert_sreg 0x40000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x130000, y0 - psha x0, y0, x0 - assert_sreg 0x80000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x140000, y0 - psha x0, y0, x0 - assert_sreg 0x100000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x150000, y0 - psha x0, y0, x0 - assert_sreg 0x200000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x160000, y0 - psha x0, y0, x0 - assert_sreg 0x400000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x170000, y0 - psha x0, y0, x0 - assert_sreg 0x800000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x180000, y0 - psha x0, y0, x0 - assert_sreg 0x1000000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x190000, y0 - psha x0, y0, x0 - assert_sreg 0x2000000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x1a0000, y0 - psha x0, y0, x0 - assert_sreg 0x4000000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x1b0000, y0 - psha x0, y0, x0 - assert_sreg 0x8000000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x1c0000, y0 - psha x0, y0, x0 - assert_sreg 0x10000000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x1d0000, y0 - psha x0, y0, x0 - assert_sreg 0x20000000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x1e0000, y0 - psha x0, y0, x0 - assert_sreg 0x40000000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0x1, x0 - - set_sreg 0x1f0000, y0 - psha x0, y0, x0 - assert_sreg 0x80000000, x0 - pneg y0, y0 - psha x0, y0, x0 - assert_sreg 0xffffffff, x0 - - set_sreg 0x200000, y0 - psha x0, y0, x0 - assert_sreg 0x00000000, x0 -# I don't grok what should happen here... -# pneg y0, y0 -# psha x0, y0, x0 -# assert_sreg 0x0, x0 - - test_grs_a5a5 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - - - pass - exit 0 - diff --git a/sim/testsuite/sim/sh/pshli.s b/sim/testsuite/sim/sh/pshli.s deleted file mode 100644 index a6616e896ac..00000000000 --- a/sim/testsuite/sim/sh/pshli.s +++ /dev/null @@ -1,119 +0,0 @@ -# sh testcase for pshl -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -pshl_imm: ! shift logical, immediate operand - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - set_sreg 0x10000, a0 - pshl #0, a0 - assert_sreg 0x10000, a0 - pshl #-0, a0 - assert_sreg 0x10000, a0 - - pshl #1, a0 - assert_sreg 0x20000, a0 - pshl #-1, a0 - assert_sreg 0x10000, a0 - - pshl #2, a0 - assert_sreg 0x40000, a0 - pshl #-2, a0 - assert_sreg 0x10000, a0 - - pshl #3, a0 - assert_sreg 0x80000, a0 - pshl #-3, a0 - assert_sreg 0x10000, a0 - - pshl #4, a0 - assert_sreg 0x100000, a0 - pshl #-4, a0 - assert_sreg 0x10000, a0 - - pshl #5, a0 - assert_sreg 0x200000, a0 - pshl #-5, a0 - assert_sreg 0x10000, a0 - - pshl #6, a0 - assert_sreg 0x400000, a0 - pshl #-6, a0 - assert_sreg 0x10000, a0 - - pshl #7, a0 - assert_sreg 0x800000, a0 - pshl #-7, a0 - assert_sreg 0x10000, a0 - - pshl #8, a0 - assert_sreg 0x1000000, a0 - pshl #-8, a0 - assert_sreg 0x10000, a0 - - pshl #9, a0 - assert_sreg 0x2000000, a0 - pshl #-9, a0 - assert_sreg 0x10000, a0 - - pshl #10, a0 - assert_sreg 0x4000000, a0 - pshl #-10, a0 - assert_sreg 0x10000, a0 - - pshl #11, a0 - assert_sreg 0x8000000, a0 - pshl #-11, a0 - assert_sreg 0x10000, a0 - - pshl #12, a0 - assert_sreg 0x10000000, a0 - pshl #-12, a0 - assert_sreg 0x10000, a0 - - pshl #13, a0 - assert_sreg 0x20000000, a0 - pshl #-13, a0 - assert_sreg 0x10000, a0 - - pshl #14, a0 - assert_sreg 0x40000000, a0 - pshl #-14, a0 - assert_sreg 0x10000, a0 - - pshl #15, a0 - assert_sreg 0x80000000, a0 - pshl #-15, a0 - assert_sreg 0x10000, a0 - - pshl #16, a0 - assert_sreg 0x00000000, a0 - pshl #-16, a0 - assert_sreg 0x0, a0 - - test_grs_a5a5 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg 0xa5a5a5a5, x0 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y0 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - - - pass - exit 0 - diff --git a/sim/testsuite/sim/sh/pshlr.s b/sim/testsuite/sim/sh/pshlr.s deleted file mode 100644 index 36cb47f4188..00000000000 --- a/sim/testsuite/sim/sh/pshlr.s +++ /dev/null @@ -1,152 +0,0 @@ -# sh testcase for pshl -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -pshl_reg: ! shift arithmetic, register operand - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - set_sreg 0x10000, x0 - set_sreg 0x0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - - set_sreg 0x10000, y0 - pshl x0, y0, x0 - assert_sreg 0x20000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - - set_sreg 0x20000, y0 - pshl x0, y0, x0 - assert_sreg 0x40000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - - set_sreg 0x30000, y0 - pshl x0, y0, x0 - assert_sreg 0x80000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - - set_sreg 0x40000, y0 - pshl x0, y0, x0 - assert_sreg 0x100000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - - set_sreg 0x50000, y0 - pshl x0, y0, x0 - assert_sreg 0x200000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - - set_sreg 0x60000, y0 - pshl x0, y0, x0 - assert_sreg 0x400000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - - set_sreg 0x70000, y0 - pshl x0, y0, x0 - assert_sreg 0x800000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - - set_sreg 0x80000, y0 - pshl x0, y0, x0 - assert_sreg 0x1000000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - - set_sreg 0x90000, y0 - pshl x0, y0, x0 - assert_sreg 0x2000000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - - set_sreg 0xa0000, y0 - pshl x0, y0, x0 - assert_sreg 0x4000000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - - set_sreg 0xb0000, y0 - pshl x0, y0, x0 - assert_sreg 0x8000000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - - set_sreg 0xc0000, y0 - pshl x0, y0, x0 - assert_sreg 0x10000000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - - set_sreg 0xd0000, y0 - pshl x0, y0, x0 - assert_sreg 0x20000000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - - set_sreg 0xe0000, y0 - pshl x0, y0, x0 - assert_sreg 0x40000000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - - set_sreg 0xf0000, y0 - pshl x0, y0, x0 - assert_sreg 0x80000000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x10000, x0 - - set_sreg 0x100000, y0 - pshl x0, y0, x0 - assert_sreg 0x00000000, x0 - pneg y0, y0 - pshl x0, y0, x0 - assert_sreg 0x0, x0 - - test_grs_a5a5 - assert_sreg2 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - - - pass - exit 0 - diff --git a/sim/testsuite/sim/sh/psub.s b/sim/testsuite/sim/sh/psub.s deleted file mode 100644 index bcfd26e9514..00000000000 --- a/sim/testsuite/sim/sh/psub.s +++ /dev/null @@ -1,64 +0,0 @@ -# sh testcase for psub -# mach: shdsp -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - -psub_sx_sy: - # 0xa5a5a5a5 minus 0xa5a5a5a5 equals zero - psub x0, y0, a0 - assert_sreg 0, a0 - -psub_sy_sx: - # 100 - 25 = 75 - mov #100, r0 - mov #25, r1 - lds r0, y1 - lds r1, x1 - psub y1, x1, a0 - assert_sreg 75, a0 - -dct_psub: - # 100 - 25 = 75 - set_dcfalse - dct psub y1, x1, a1 - assert_sreg2 0xa5a5a5a5, a1 - set_dctrue - dct psub y1, x1, a1 - assert_sreg2 75, a1 - -dcf_psub: - # 25 - 100 = -75 - set_dctrue - dcf psub x1, y1, m1 - assert_sreg2 0xa5a5a5a5, m1 - set_dcfalse - dcf psub x1, y1, m1 - assert_sreg2 -75, m1 - -psub_pmuls: - # 25 - 100 = -75, and 2 x 2 = 8 (yes, eight, not four) - mov #2, r0 - shll16 r0 - lds r0, x0 - lds r0, y0 - psub x1, y1, a1 pmuls x0, y0, a0 - assert_sreg 8, a0 - assert_sreg2 -75, a1 - - set_greg 0xa5a5a5a5, r0 - set_greg 0xa5a5a5a5, r1 - test_grs_a5a5 - pass - exit 0 diff --git a/sim/testsuite/sim/sh/pswap.s b/sim/testsuite/sim/sh/pswap.s deleted file mode 100644 index 5bd6a5939cc..00000000000 --- a/sim/testsuite/sim/sh/pswap.s +++ /dev/null @@ -1,177 +0,0 @@ -# sh testcase for pswap -# mach: shdsp -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -pswapx: - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - set_greg 0xa5a57777, r0 - lds r0, x0 - pswap x0, y0 - assert_sreg 0x7777a5a5, y0 - - set_greg 0xa5a5a5a5, r0 - test_grs_a5a5 - assert_sreg 0xa5a57777, x0 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - -pswapy: - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - set_greg 0xa5a57777, r0 - lds r0, y0 - pswap y0, x0 - assert_sreg 0x7777a5a5, x0 - - set_greg 0xa5a5a5a5, r0 - test_grs_a5a5 - assert_sreg 0xa5a57777, y0 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - -pswapa: - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - set_greg 0xa5a57777, r0 - lds r0, a0 - pcopy a0, a1 - pswap a1, y0 - assert_sreg 0x7777a5a5, y0 - - set_greg 0xa5a5a5a5, r0 - test_grs_a5a5 - assert_sreg 0xa5a57777, a0 - assert_sreg2 0xa5a57777, a1 - assert_sreg 0xa5a5a5a5, x0 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - -pswapm: - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - set_greg 0xa5a57777, r0 - lds r0, a0 - pcopy a0, m1 - pswap m1, y0 - assert_sreg 0x7777a5a5, y0 - - set_greg 0xa5a5a5a5, r0 - test_grs_a5a5 - assert_sreg 0xa5a57777, a0 - assert_sreg2 0xa5a57777, m1 - assert_sreg 0xa5a5a5a5, x0 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg2 0xa5a5a5a5, m0 - - -dct_pswapx: - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - set_greg 0xa5a57777, r0 - lds r0, x0 - set_dcfalse - dct pswap x0, y0 - assert_sreg 0xa5a5a5a5, y0 - set_dctrue - dct pswap x0, y0 - assert_sreg 0x7777a5a5, y0 - - set_greg 0xa5a5a5a5, r0 - test_grs_a5a5 - assert_sreg 0xa5a57777, x0 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - -dcf_pswapy: - set_grs_a5a5 - lds r0, a0 - pcopy a0, a1 - lds r0, x0 - lds r0, x1 - lds r0, y0 - lds r0, y1 - pcopy x0, m0 - pcopy y1, m1 - - set_greg 0xa5a57777, r0 - lds r0, x0 - set_dctrue - dcf pswap x0, y0 - assert_sreg 0xa5a5a5a5, y0 - set_dcfalse - dcf pswap x0, y0 - assert_sreg 0x7777a5a5, y0 - - set_greg 0xa5a5a5a5, r0 - test_grs_a5a5 - assert_sreg 0xa5a57777, x0 - assert_sreg 0xa5a5a5a5, x1 - assert_sreg 0xa5a5a5a5, y1 - assert_sreg 0xa5a5a5a5, a0 - assert_sreg2 0xa5a5a5a5, a1 - assert_sreg2 0xa5a5a5a5, m0 - assert_sreg2 0xa5a5a5a5, m1 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/sett.s b/sim/testsuite/sim/sh/sett.s deleted file mode 100644 index fff2d2d4a6d..00000000000 --- a/sim/testsuite/sim/sh/sett.s +++ /dev/null @@ -1,65 +0,0 @@ -# sh testcase for sett, clrt, movt -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start -sett_1: set_grs_a5a5 - sett - bt .Lsett - nop - fail -.Lsett: - test_grs_a5a5 - -clrt_1: set_grs_a5a5 - clrt - bf .Lclrt - nop - fail -.Lclrt: - test_grs_a5a5 - -movt_1: set_grs_a5a5 - sett - movt r1 - test_gr_a5a5 r0 - assertreg 1, r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - -movt_2: set_grs_a5a5 - clrt - movt r1 - test_gr_a5a5 r0 - assertreg 0, r1 - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - pass - - exit 0 diff --git a/sim/testsuite/sim/sh/shll.s b/sim/testsuite/sim/sh/shll.s deleted file mode 100644 index ec2ea12d671..00000000000 --- a/sim/testsuite/sim/sh/shll.s +++ /dev/null @@ -1,91 +0,0 @@ -# sh testcase for shll -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -shll: - set_grs_a5a5 - mov #1, r1 - shll r1 - assertreg 2, r1 - shll r1 - assertreg 4, r1 - shll r1 - assertreg 8, r1 - shll r1 - assertreg 16, r1 - shll r1 - assertreg 32, r1 - shll r1 - assertreg 64, r1 - shll r1 - assertreg 0x80, r1 - shll r1 - assertreg 0x100, r1 - shll r1 - assertreg 0x200, r1 - shll r1 - assertreg 0x400, r1 - shll r1 - assertreg 0x800, r1 - shll r1 - assertreg 0x1000, r1 - shll r1 - assertreg 0x2000, r1 - shll r1 - assertreg 0x4000, r1 - shll r1 - assertreg 0x8000, r1 - shll r1 - assertreg 0x10000, r1 - shll r1 - assertreg 0x20000, r1 - shll r1 - assertreg 0x40000, r1 - shll r1 - assertreg 0x80000, r1 - shll r1 - assertreg 0x100000, r1 - shll r1 - assertreg 0x200000, r1 - shll r1 - assertreg 0x400000, r1 - shll r1 - assertreg 0x800000, r1 - shll r1 - assertreg 0x1000000, r1 - shll r1 - assertreg 0x2000000, r1 - shll r1 - assertreg 0x4000000, r1 - shll r1 - assertreg 0x8000000, r1 - shll r1 - assertreg 0x10000000, r1 - shll r1 - assertreg 0x20000000, r1 - shll r1 - assertreg 0x40000000, r1 - shll r1 - assertreg 0x80000000, r1 - shll r1 - assertreg 0, r1 - shll r1 - assertreg 0, r1 - - # another: - mov #1, r1 - shll r1 - shll r1 - shll r1 - assertreg 8, r1 - - set_greg 0xa5a5a5a5, r1 - test_grs_a5a5 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/shll16.s b/sim/testsuite/sim/sh/shll16.s deleted file mode 100644 index 4574835f8e3..00000000000 --- a/sim/testsuite/sim/sh/shll16.s +++ /dev/null @@ -1,46 +0,0 @@ -# sh testcase for shll16 -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -shll16: - set_grs_a5a5 - mov #0x18, r1 - shll16 r1 - assertreg 0x180000, r1 - shll16 r1 - assertreg 0, r1 - - # another: - mov #1, r1 - shll16 r1 - mov #1, r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - shll r7 - cmp/eq r1, r7 - bt okay - fail -okay: - set_greg 0xa5a5a5a5, r1 - set_greg 0xa5a5a5a5, r7 - test_grs_a5a5 - pass - exit 0 diff --git a/sim/testsuite/sim/sh/shll2.s b/sim/testsuite/sim/sh/shll2.s deleted file mode 100644 index 01a784c9390..00000000000 --- a/sim/testsuite/sim/sh/shll2.s +++ /dev/null @@ -1,51 +0,0 @@ -# sh testcase for shll2 -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -shll2: - set_grs_a5a5 - mov #1, r1 - shll2 r1 - assertreg 4, r1 - shll2 r1 - assertreg 16, r1 - shll2 r1 - assertreg 64, r1 - shll2 r1 - assertreg 0x100, r1 - shll2 r1 - assertreg 0x400, r1 - shll2 r1 - assertreg 0x1000, r1 - shll2 r1 - assertreg 0x4000, r1 - shll2 r1 - assertreg 0x10000, r1 - shll2 r1 - assertreg 0x40000, r1 - shll2 r1 - assertreg 0x100000, r1 - shll2 r1 - assertreg 0x400000, r1 - shll2 r1 - assertreg 0x1000000, r1 - shll2 r1 - assertreg 0x4000000, r1 - shll2 r1 - assertreg 0x10000000, r1 - shll2 r1 - assertreg 0x40000000, r1 - shll2 r1 - assertreg 0, r1 - - set_greg 0xa5a5a5a5, r1 - test_grs_a5a5 - - pass - exit 0 - diff --git a/sim/testsuite/sim/sh/shll8.s b/sim/testsuite/sim/sh/shll8.s deleted file mode 100644 index 71e241d1e6b..00000000000 --- a/sim/testsuite/sim/sh/shll8.s +++ /dev/null @@ -1,42 +0,0 @@ -# sh testcase for shll8 -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -shll8: - set_grs_a5a5 - mov #1, r1 - shll8 r1 - assertreg 0x100, r1 - shll8 r1 - assertreg 0x10000, r1 - shll8 r1 - assertreg 0x1000000, r1 - shll8 r1 - assertreg 0, r1 - - # another: - mov #1, r1 - shll8 r1 - mov #1, r2 - shll r2 - shll r2 - shll r2 - shll r2 - shll r2 - shll r2 - shll r2 - shll r2 - cmp/eq r1, r2 - bt okay - fail -okay: - set_greg 0xa5a5a5a5, r1 - set_greg 0xa5a5a5a5, r2 - test_grs_a5a5 - pass - exit 0 diff --git a/sim/testsuite/sim/sh/shlr.s b/sim/testsuite/sim/sh/shlr.s deleted file mode 100644 index 8755afb707f..00000000000 --- a/sim/testsuite/sim/sh/shlr.s +++ /dev/null @@ -1,42 +0,0 @@ -# sh testcase for shlr -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -shlr: - set_grs_a5a5 - mov #0, r0 - or #192, r0 - shlr r0 - assertreg0 96 - shlr r0 - assertreg0 48 - shlr r0 - assertreg0 24 - shlr r0 - assertreg0 12 - shlr r0 - assertreg0 6 - shlr r0 - assertreg0 3 - - # Make sure a bit is shifted into T. - shlr r0 - bf wrong - assertreg0 1 - # Ditto. - shlr r0 - bf wrong - assertreg0 0 - - set_greg 0xa5a5a5a5, r0 - test_grs_a5a5 - pass - exit 0 - -wrong: - fail diff --git a/sim/testsuite/sim/sh/shlr16.s b/sim/testsuite/sim/sh/shlr16.s deleted file mode 100644 index 1161c6666f9..00000000000 --- a/sim/testsuite/sim/sh/shlr16.s +++ /dev/null @@ -1,20 +0,0 @@ -# sh testcase for shlr16 -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -shrl16: - set_grs_a5a5 - shlr16 r0 - assertreg0 0xa5a5 - shlr16 r0 - assertreg0 0 - - set_greg 0xa5a5a5a5, r0 - test_grs_a5a5 - pass - exit 0 diff --git a/sim/testsuite/sim/sh/shlr2.s b/sim/testsuite/sim/sh/shlr2.s deleted file mode 100644 index ce554dd0f09..00000000000 --- a/sim/testsuite/sim/sh/shlr2.s +++ /dev/null @@ -1,48 +0,0 @@ -# sh testcase for shlr2 -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -shrl2: - set_grs_a5a5 - shlr2 r0 - assertreg0 0x29696969 - shlr2 r0 - assertreg0 0x0a5a5a5a - shlr2 r0 - assertreg0 0x02969696 - shlr2 r0 - assertreg0 0x00a5a5a5 - shlr2 r0 - assertreg0 0x00296969 - shlr2 r0 - assertreg0 0x000a5a5a - shlr2 r0 - assertreg0 0x00029696 - shlr2 r0 - assertreg0 0x0000a5a5 - shlr2 r0 - assertreg0 0x00002969 - shlr2 r0 - assertreg0 0x00000a5a - shlr2 r0 - assertreg0 0x00000296 - shlr2 r0 - assertreg0 0x000000a5 - shlr2 r0 - assertreg0 0x00000029 - shlr2 r0 - assertreg0 0x0000000a - shlr2 r0 - assertreg0 0x00000002 - shlr2 r0 - assertreg0 0 - - set_greg 0xa5a5a5a5 r0 - test_grs_a5a5 - pass - exit 0 diff --git a/sim/testsuite/sim/sh/shlr8.s b/sim/testsuite/sim/sh/shlr8.s deleted file mode 100644 index d609af119e3..00000000000 --- a/sim/testsuite/sim/sh/shlr8.s +++ /dev/null @@ -1,24 +0,0 @@ -# sh testcase for shlr8 -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -shrl8: - set_grs_a5a5 - shlr8 r0 - assertreg0 0xa5a5a5 - shlr8 r0 - assertreg0 0xa5a5 - shlr8 r0 - assertreg0 0xa5 - shlr8 r0 - assertreg0 0x0 - - set_greg 0xa5a5a5a5, r0 - test_grs_a5a5 - pass - exit 0 diff --git a/sim/testsuite/sim/sh/swap.s b/sim/testsuite/sim/sh/swap.s deleted file mode 100644 index 4dd6572695c..00000000000 --- a/sim/testsuite/sim/sh/swap.s +++ /dev/null @@ -1,59 +0,0 @@ -# sh testcase for swap -# mach: all -# as(sh): -defsym sim_cpu=0 -# as(shdsp): -defsym sim_cpu=1 -dsp - - .include "testutils.inc" - - start - -swapb: - set_grs_a5a5 - mov #0x5a, r0 - shll8 r0 - or #0xa5, r0 - assertreg0 0x5aa5 - - swap.b r0, r1 - assertreg 0xa55a, r1 - - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - -swapw: - set_grs_a5a5 - mov #0x5a, r0 - shll16 r0 - or #0xa5, r0 - assertreg0 0x5a00a5 - - swap.w r0, r1 - assertreg 0xa5005a, r1 - - test_gr_a5a5 r2 - test_gr_a5a5 r3 - test_gr_a5a5 r4 - test_gr_a5a5 r5 - test_gr_a5a5 r6 - test_gr_a5a5 r7 - test_gr_a5a5 r8 - test_gr_a5a5 r9 - test_gr_a5a5 r10 - test_gr_a5a5 r11 - test_gr_a5a5 r12 - test_gr_a5a5 r13 - test_gr_a5a5 r14 - - pass - exit 0 diff --git a/sim/testsuite/sim/sh/testutils.inc b/sim/testsuite/sim/sh/testutils.inc deleted file mode 100644 index 8d3895e2581..00000000000 --- a/sim/testsuite/sim/sh/testutils.inc +++ /dev/null @@ -1,591 +0,0 @@ -# Support macros for the sh assembly test cases. - - .equ no_dsp, 0 - .equ yes_dsp, 1 - - .section .rodata - .align 2 -_pass: .string "pass\n" -_fail: .string "fail\n" -_stack: .fill 128, 4, 0 -stackt: - - .macro push reg - mov.l \reg, @-r15 - .endm - - .macro pop reg - mov.l @r15+, \reg - .endm - - .macro start - .text - .align 1 - .global start -start: mov.l stackp, r15 - bra main - nop - .align 2 -stackp: .long stackt -mpass: - mov #4, r4 - mov #1, r5 - mov.l ppass, r6 - mov #5, r7 - trapa #34 - rts - nop -mfail: - mov #4, r4 - mov #1, r5 - mov.l pfail, r6 - mov #5, r7 - trapa #34 - mov #1, r5 -mexit: - mov #1, r4 - mov #0, r6 - mov #0, r7 - trapa #34 - .align 2 -ppass: .long _pass -pfail: .long _fail - -mtesta5: - push r0 - mov.l a5a5, r0 - cmp/eq r1, r0 - bf mfail - cmp/eq r2, r0 - bf mfail - cmp/eq r3, r0 - bf mfail - cmp/eq r4, r0 - bf mfail - cmp/eq r5, r0 - bf mfail - cmp/eq r6, r0 - bf mfail - cmp/eq r7, r0 - bf mfail - cmp/eq r8, r0 - bf mfail - cmp/eq r9, r0 - bf mfail - cmp/eq r10, r0 - bf mfail - cmp/eq r11, r0 - bf mfail - cmp/eq r12, r0 - bf mfail - cmp/eq r13, r0 - bf mfail - cmp/eq r14, r0 - bf mfail - # restore and check r0 - pop r0 - cmp/eq r0, r1 - bf mfail - # pass - rts - nop -.if (sim_cpu == no_dsp) -mtesta5_fp: - push r0 - flds fr0, fpul - sts fpul, r0 - push r0 - mov.l a5a5, r0 - lds r0, fpul - fsts fpul, fr0 - fcmp/eq fr1, fr0 - bf mfail - fcmp/eq fr2, fr0 - bf mfail - fcmp/eq fr3, fr0 - bf mfail - fcmp/eq fr4, fr0 - bf mfail - fcmp/eq fr5, fr0 - bf mfail - fcmp/eq fr6, fr0 - bf mfail - fcmp/eq fr7, fr0 - bf mfail - fcmp/eq fr8, fr0 - bf mfail - fcmp/eq fr9, fr0 - bf mfail - fcmp/eq fr10, fr0 - bf mfail - fcmp/eq fr11, fr0 - bf mfail - fcmp/eq fr12, fr0 - bf mfail - fcmp/eq fr13, fr0 - bf mfail - fcmp/eq fr14, fr0 - bf mfail - fcmp/eq fr15, fr0 - bf mfail - # restore and check fr0 - pop r0 - lds r0, fpul - fsts fpul, fr0 - fcmp/eq fr0, fr1 - bf mfail - # restore r0 and pass - pop r0 - rts - nop -.endif - -mseta5: - mov.l a5a5, r0 - mov.l a5a5, r1 - mov.l a5a5, r2 - mov.l a5a5, r3 - mov.l a5a5, r4 - mov.l a5a5, r5 - mov.l a5a5, r6 - mov.l a5a5, r7 - mov.l a5a5, r8 - mov.l a5a5, r9 - mov.l a5a5, r10 - mov.l a5a5, r11 - mov.l a5a5, r12 - mov.l a5a5, r13 - mov.l a5a5, r14 - rts - nop - -.if (sim_cpu == no_dsp) -mseta5_fp: - push r0 - mov.l a5a5, r0 - lds r0, fpul - fsts fpul, fr0 - fsts fpul, fr1 - fsts fpul, fr2 - fsts fpul, fr3 - fsts fpul, fr4 - fsts fpul, fr5 - fsts fpul, fr6 - fsts fpul, fr7 - fsts fpul, fr8 - fsts fpul, fr9 - fsts fpul, fr10 - fsts fpul, fr11 - fsts fpul, fr12 - fsts fpul, fr13 - fsts fpul, fr14 - fsts fpul, fr15 - pop r0 - rts - nop -.endif - - .align 2 -a5a5: .long 0xa5a5a5a5 -main: - .endm - - .macro exit val - mov #\val, r5 - bra mexit - nop - .endm - - .macro pass - bsr mpass - nop - .endm - - .macro fail - bra mfail - nop - .endm - - # Assert value of register (any general register but r0) - # Preserves r0 on stack, restores it on success. - .macro assertreg val reg - push r0 - mov.l .Larval\@, r0 - cmp/eq r0, \reg - bt .Lar\@ - fail - .align 2 -.Larval\@: - .long \val -.Lar\@: pop r0 - .endm - - # Assert value of register zero - # Preserves r1 on stack, restores it on success. - .macro assertreg0 val - push r1 - mov.l .Lazval\@, r1 - cmp/eq r1, r0 - bt .Laz\@ - fail - .align 2 -.Lazval\@: - .long \val -.Laz\@: pop r1 - .endm - - # Assert value of system register - # [mach, macl, pr, dsr, a0, x0, x1, y0, y1, ...] - .macro assert_sreg val reg - push r0 - sts \reg, r0 - assertreg0 \val - pop r0 - .endm - - # Assert value of system register that isn't directly stc-able - # [a1, m0, m1, ...] - .macro assert_sreg2 val reg - push r0 - sts a0, r0 - push r0 - pcopy \reg, a0 - sts a0, r0 - assertreg0 \val - pop r0 - lds r0, a0 - pop r0 - .endm - - # Assert value of control register - # [gbr, vbr, ssr, spc, sgr, dbr, r[0-7]_bank, sr, mod, re, rs, ...] - .macro assert_creg val reg - push r0 - stc \reg, r0 - assertreg0 \val - pop r0 - .endm - - # Assert integer value of fp register - # Preserves r0 on stack, restores it on success - # Assumes single-precision fp mode - .macro assert_fpreg_i val freg - push r0 - ftrc \freg, fpul - sts fpul, r0 - assertreg0 \val - pop r0 - .endm - - # Assert integer value of dp register - # Preserves r0 on stack, restores it on success - # Assumes double-precision fp mode - .macro assert_dpreg_i val dreg - push r0 - ftrc \dreg, fpul - sts fpul, r0 - assertreg0 \val - pop r0 - .endm - - # Assert hex value of fp register - # Preserves r0 on stack, restores it on success - # Assumes single-precision fp mode - .macro assert_fpreg_x val freg - push r0 - flds \freg, fpul - sts fpul, r0 - assertreg0 \val - pop r0 - .endm - - # Set FP bank 0 - # Saves and restores r0 and r1 - .macro bank0 - push r0 - push r1 - mov #32, r1 - shll16 r1 - not r1, r1 - sts fpscr, r0 - and r1, r0 - lds r0, fpscr - pop r1 - pop r0 - .endm - - # Set FP bank 1 - .macro bank1 - push r0 - push r1 - mov #32, r1 - shll16 r1 - sts fpscr, r0 - or r1, r0 - lds r0, fpscr - pop r1 - pop r0 - .endm - - # Set FP 32-bit xfer - .macro sz_32 - push r0 - push r1 - mov #16, r1 - shll16 r1 - not r1, r1 - sts fpscr, r0 - and r1, r0 - lds r0, fpscr - pop r1 - pop r0 - .endm - - # Set FP 64-bit xfer - .macro sz_64 - push r0 - push r1 - mov #16, r1 - shll16 r1 - sts fpscr, r0 - or r1, r0 - lds r0, fpscr - pop r1 - pop r0 - .endm - - # Set FP single precision - .macro single_prec - push r0 - push r1 - mov #8, r1 - shll16 r1 - not r1, r1 - sts fpscr, r0 - and r1, r0 - lds r0, fpscr - pop r1 - pop r0 - .endm - - # Set FP double precision - .macro double_prec - push r0 - push r1 - mov #8, r1 - shll16 r1 - sts fpscr, r0 - or r1, r0 - lds r0, fpscr - pop r1 - pop r0 - .endm - - .macro set_carry - sett - .endm - - .macro set_ovf - sett - .endm - - .macro clear_carry - clrt - .endm - - .macro clear_ovf - clrt - .endm - - # sets, clrs - - - .macro set_grs_a5a5 - bsr mseta5 - nop - .endm - - .macro set_greg val greg - mov.l gregval\@, \greg - bra set_greg\@ - nop - .align 2 -gregval\@: .long \val -set_greg\@: - .endm - - .macro set_fprs_a5a5 - bsr mseta5_fp - nop - .endm - - .macro test_grs_a5a5 - bsr mtesta5 - nop - .endm - - .macro test_fprs_a5a5 - bsr mtesta5_fp - nop - .endm - - .macro test_gr_a5a5 reg - assertreg 0xa5a5a5a5 \reg - .endm - - .macro test_fpr_a5a5 reg - assert_fpreg_x 0xa5a5a5a5 \reg - .endm - - .macro test_gr0_a5a5 - assertreg0 0xa5a5a5a5 - .endm - - # Perform a single to double precision floating point conversion. - # Assumes correct settings of fpscr. - .macro _s2d fpr dpr - flds \fpr, fpul - fcnvsd fpul, \dpr - .endm - - # Manipulate the status register - .macro set_sr val - push r0 - mov.l .Lsrval\@, r0 - ldc r0, sr - pop r0 - bra .Lsetsr\@ - nop - .align 2 -.Lsrval\@: - .long \val -.Lsetsr\@: - .endm - - .macro get_sr reg - stc sr, \reg - .endm - - .macro test_sr val - push r0 - get_sr r0 - assertreg0 \val - pop r0 - .endm - - .macro set_sr_bit val - push r0 - push r1 - get_sr r0 - mov.l .Lsrbitval\@, r1 - or r1, r0 - ldc r0, sr - pop r1 - pop r0 - bra .Lsrbit\@ - nop - .align 2 -.Lsrbitval\@: - .long \val -.Lsrbit\@: - .endm - - .macro test_sr_bit_set val - push r0 - push r1 - get_sr r0 - mov.l .Ltsbsval\@, r1 - tst r1, r0 - bf .Ltsbs\@ - fail - .align 2 -.Ltsbsval\@: - .long \val -.Ltsbs\@: - pop r1 - pop r0 - .endm - - .macro test_sr_bit_clear val - push r0 - push r1 - get_sr r0 - mov.l .Ltsbcval\@, r1 - not r0, r0 - tst r1, r0 - bf .Ltsbc\@ - fail - .align 2 -.Ltsbcval\@: - .long \val -.Ltsbc\@: - pop r1 - pop r0 - .endm - - # Set system registers - .macro set_sreg val reg - # [mach, macl, pr, dsr, a0, x0, x1, y0, y1, ...] - push r0 - mov.l .Lssrval\@, r0 - lds r0, \reg - pop r0 - bra .Lssr\@ - nop - .align 2 -.Lssrval\@: - .long \val -.Lssr\@: - .endm - - .macro set_sreg2 val reg - # [a1, m0, m1, ...] - push r0 - sts a0, r0 - push r0 - mov.l .Lssr2val\@, r0 - lds r0, a0 - pcopy a0, \reg - pop r0 - lds r0, a0 - pop r0 - bra .Lssr2_\@ - nop - .align 2 -.Lssr2val\@: - .long \val -.Lssr2_\@: - .endm - - - .macro set_creg val reg - # [gbr, vbr, ssr, spc, sgr, dbr... ] - push r0 - mov.l .Lscrval\@, r0 - ldc r0, \reg - pop r0 - bra .Lscr\@ - nop - .align 2 -.Lscrval\@: - .long \val -.Lscr\@: - .endm - - .macro set_dctrue - push r0 - sts dsr, r0 - or #1, r0 - lds r0, dsr - pop r0 - .endm - - .macro set_dcfalse - push r0 - sts dsr, r0 - not r0, r0 - or #1, r0 - not r0, r0 - lds r0, dsr - pop r0 - .endm diff --git a/sim/testsuite/sim/sh64/ChangeLog b/sim/testsuite/sim/sh64/ChangeLog new file mode 100644 index 00000000000..8bb2f764ae6 --- /dev/null +++ b/sim/testsuite/sim/sh64/ChangeLog @@ -0,0 +1,21 @@ +2001-01-06 Ben Elliston + + * misc/fr-dr.s: New test. + +2001-01-03 Ben Elliston + + * interwork.exp: Match .s files only. + +2000-12-06 Ben Elliston + + * interwork.exp: New test case. + +2000-11-16 Ben Elliston + + * allinsn.exp: Rename from this .. + * compact.exp: .. to this. + * media.exp: New test case. + +2000-11-13 Ben Elliston + + * allinsn.exp: New test case. diff --git a/sim/testsuite/sim/sh64/compact.exp b/sim/testsuite/sim/sh64/compact.exp new file mode 100644 index 00000000000..d3d482acf0f --- /dev/null +++ b/sim/testsuite/sim/sh64/compact.exp @@ -0,0 +1,19 @@ +# SHcompact testsuite. + +if [istarget sh64-*-*] { + # load support procs (none yet) + # load_lib cgen.exp + + # all machines + set all_machs "sh5" + + # The .cgs suffix is for "cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/compact/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/sim/sh64/compact/ChangeLog b/sim/testsuite/sim/sh64/compact/ChangeLog new file mode 100644 index 00000000000..99aaec1ff02 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/ChangeLog @@ -0,0 +1,26 @@ +2002-01-09 Ben Elliston + + * macl.cgs: For good measure, clear the S bit at startup. + +2001-01-11 Ben Elliston + + * fmov.cgs (f13b): Compare R0 with R1, not R2, when testing that + the source register was correctly post-incremented. + +2000-12-01 Ben Elliston + + * *.cgs (ld): Link tests with -m shelf32. + +2000-11-24 Ben Elliston + + * fmov.cgs: New test case. + * ftrv.cgs: Populate the matrix with meaningful values. + +2000-11-22 Ben Elliston + + * *.cgs (as): Assemble tests with -isa=shcompact. + +2000-11-16 Ben Elliston + + * *.cgs: New test cases. + diff --git a/sim/testsuite/sim/sh64/compact/add.cgs b/sim/testsuite/sim/sh64/compact/add.cgs new file mode 100644 index 00000000000..105e4849069 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/add.cgs @@ -0,0 +1,55 @@ +# sh testcase for add $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start +init: + # Initialise some registers with values which help us to verify + # that the correct source registers are used by the ADD instruction. + mov #0, r0 + mov #1, r1 + mov #2, r2 + mov #3, r3 + mov #5, r5 + mov #15, r15 + +add: + # 0 + 0 = 0. + add r0, r0 + assert r0, #0 + + # 0 + 1 = 1. + add r0, r1 + assert r1, #1 + + # 1 + 2 = 3. + add r1, r2 + assert r2, #3 + + # 3 + 5 = 8. + add r3, r5 + assert r5, #8 + + # 8 + 8 = 16. + add r5, r5 + assert r5, #16 + + # 15 + 1 = 16. + add r15, r1 + assert r1, #16 + +neg: + mov #1, r0 + neg r0, r0 + mov #2, r1 + add r0, r1 + assert r1, #1 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/addc.cgs b/sim/testsuite/sim/sh64/compact/addc.cgs new file mode 100644 index 00000000000..f6e46e1a969 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/addc.cgs @@ -0,0 +1,90 @@ +# sh testcase for addc $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + # Initialise some registers with values which help us to verify + # that the correct source registers are used by the ADDC instruction. + + .macro init + mov #0, r0 + mov #1, r1 + mov #2, r2 + mov #3, r3 + mov #5, r5 + mov #15, r15 + .endm + + start + + init +add: + clrt + addc r0, r0 + assert r0, #0 + clrt + addc r0, r1 + assert r1, #1 + clrt + addc r1, r2 + assert r2, #3 + clrt + addc r3, r5 + assert r5, #8 + clrt + addc r5, r5 + assert r5, #16 + clrt + addc r15, r1 + assert r1, #16 + + init +addt: + sett + addc r0, r0 + assert r0, #1 + sett + addc r0, r1 + assert r1, #3 + sett + addc r1, r2 + assert r2, #6 + sett + addc r3, r5 + assert r5, #9 + sett + addc r5, r5 + assert r5, #19 + sett + addc r15, r1 + assert r1, #19 + + bra next + nop + +wrong: + fail + +next: + init +large: + clrt + mov #1, r0 + neg r0, r0 + mov #2, r1 + addc r0, r1 + assert r1, #1 + + init +larget: + sett + mov #1, r0 + neg r0, r0 + mov #2, r1 + addc r0, r1 + assert r1, #2 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/compact/addi.cgs b/sim/testsuite/sim/sh64/compact/addi.cgs new file mode 100644 index 00000000000..7c96ddf76d5 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/addi.cgs @@ -0,0 +1,46 @@ +# sh testcase for add #$imm8, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start +init: + # Initialise some registers with values which help us to verify + # that the correct source registers are used by the ADD instruction. + mov #0, r0 + mov #1, r1 + mov #2, r2 + mov #3, r3 + mov #5, r5 + mov #15, r15 + +addi: + # 0 + 0 = 0. + add #0, r0 + assert r0, #0 + + # 0 + 1 = 1. + add #0, r1 + assert r1, #1 + + # 2 + 2 = 4. + add #2, r2 + assert r2, #4 + + # 120 + 5 = 125. + add #120, r5 + assert r5, #125 + +large: + mov #1, r0 + neg r0, r0 + add #2, r0 + assert r0, #1 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/addv.cgs b/sim/testsuite/sim/sh64/compact/addv.cgs new file mode 100644 index 00000000000..0267e5dfa00 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/addv.cgs @@ -0,0 +1,48 @@ +# sh testcase for addv $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start +zero: + mov #0, r0 + mov #0, r1 + addv r0, r1 + # Assert !T and #0. + bt wrong + assert r1, #0 + +one: + mov #0, r0 + mov #1, r1 + addv r0, r1 + # Assert !T and #1. + bt wrong + assert r1, #1 + +large: + # Produce MAXINT in R0. + mov #0, r0 + not r0, r0 + shlr r0 + + # Put #3 into R1. + mov #3, r1 + + # Add them and overflow. + addv r0, r1 + + # Assert T and overflowed value. + bf wrong + mov #1, r7 + rotr r7 + add #2, r7 + cmp/eq r1, r7 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/and.cgs b/sim/testsuite/sim/sh64/compact/and.cgs new file mode 100644 index 00000000000..e1452752ae0 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/and.cgs @@ -0,0 +1,33 @@ +# sh testcase for and $rm64, $rn64 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global and +and: + mov #1, r1 + mov #7, r2 + rotr r2 + rotr r2 + and r1, r2 + + # R1 & R2 = 1. + assert r2, #1 + +another: + mov #192, r1 + mov #0, r2 + and r1, r2 + + # R1 & R2 = 0. + assert r2, #0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/andb.cgs b/sim/testsuite/sim/sh64/compact/andb.cgs new file mode 100644 index 00000000000..77e628598b1 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/andb.cgs @@ -0,0 +1,24 @@ +# sh testcase for and.b #$imm8, @(r0, gbr) -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global orb +init: + # Init GBR and R0. + mov #30, r0 + ldc r0, gbr + mov #40, r0 + +orb: + and.b #255, @(r0, gbr) + and.b #170, @(r0, gbr) + and.b #255, @(r0, gbr) + and.b #0, @(r0, gbr) + +okay: + pass diff --git a/sim/testsuite/sim/sh64/compact/andi.cgs b/sim/testsuite/sim/sh64/compact/andi.cgs new file mode 100644 index 00000000000..32d71c5b477 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/andi.cgs @@ -0,0 +1,43 @@ +# sh testcase for and #$imm8, r0 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global andi +andi: + mov #0, r0 + or #255, r0 + and #0, r0 + assert r0, #0 + +large: + mov #0, r0 + or #255, r0 + shll8 r0 + or #255, r0 + shll8 r0 + or #255, r0 + shll8 r0 + or #255, r0 + +mask: + and #255, r0 + mov r0, r1 + mov #0, r0 + or #255, r0 + cmp/eq r0, r1 + bf wrong + +mask0: + and #0, r0 + assert r0, #0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/bf.cgs b/sim/testsuite/sim/sh64/compact/bf.cgs new file mode 100644 index 00000000000..5c361f94b89 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/bf.cgs @@ -0,0 +1,24 @@ +# sh testcase for bf $disp8 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global taken +taken: + clrt + bf ntaken + fail + .global ntaken +ntaken: + sett + bf bad + pass +bad: + fail + fail + fail + fail diff --git a/sim/testsuite/sim/sh64/compact/bfs.cgs b/sim/testsuite/sim/sh64/compact/bfs.cgs new file mode 100644 index 00000000000..3cad5f6fc73 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/bfs.cgs @@ -0,0 +1,28 @@ +# sh testcase for bf/s $disp8 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global taken +taken: + clrt + bf/s ntaken +slot1: + nop + fail + .global ntaken +ntaken: + sett + bf/s bad +slot2: + nop + pass +bad: + fail + fail + fail + fail diff --git a/sim/testsuite/sim/sh64/compact/bra.cgs b/sim/testsuite/sim/sh64/compact/bra.cgs new file mode 100644 index 00000000000..77c6da9bdde --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/bra.cgs @@ -0,0 +1,23 @@ +# sh testcase for bra $disp12 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global bra +bra: + bra okay +slot: + nop +bad: + fail + fail + fail + .global okay +okay: + pass + fail + diff --git a/sim/testsuite/sim/sh64/compact/braf.cgs b/sim/testsuite/sim/sh64/compact/braf.cgs new file mode 100644 index 00000000000..e761f6d0a6d --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/braf.cgs @@ -0,0 +1,24 @@ +# sh testcase for braf $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global braf +braf: + mov #4, r0 + braf r0 +slot: + nop +bad: + fail + fail +okay: + pass +alsobad: + fail + fail + fail diff --git a/sim/testsuite/sim/sh64/compact/brk.cgs b/sim/testsuite/sim/sh64/compact/brk.cgs new file mode 100644 index 00000000000..99080724565 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/brk.cgs @@ -0,0 +1,18 @@ +# sh testcase for brk -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + .global brk +brk: + # If we hit the breakpoint, the sim will stop. + pass + + # FIXME: breakpoint instruction. + # The SH4 assembler doesn't know about "brk". + .word 0x003b +bad: + fail diff --git a/sim/testsuite/sim/sh64/compact/bsr.cgs b/sim/testsuite/sim/sh64/compact/bsr.cgs new file mode 100644 index 00000000000..75a1a2b275e --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/bsr.cgs @@ -0,0 +1,21 @@ +# sh testcase for bsr $disp12 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global bsr +bsr: + bsr okay +slot: + nop +bad: + fail + fail +okay: + pass +alsobad: + fail diff --git a/sim/testsuite/sim/sh64/compact/bsrf.cgs b/sim/testsuite/sim/sh64/compact/bsrf.cgs new file mode 100644 index 00000000000..9360eaa88b0 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/bsrf.cgs @@ -0,0 +1,22 @@ +# sh testcase for bsrf $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +bsrf: + mov #4, r0 + bsrf r0 +slot: + nop +bad: + fail + fail +okay: + pass +alsobad: + fail + fail diff --git a/sim/testsuite/sim/sh64/compact/bt.cgs b/sim/testsuite/sim/sh64/compact/bt.cgs new file mode 100644 index 00000000000..65b9d61b885 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/bt.cgs @@ -0,0 +1,24 @@ +# sh testcase for bt $disp8 +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global taken +taken: + sett + bt ntaken + fail + .global ntaken +ntaken: + clrt + bt bad + pass +bad: + fail + fail + fail + fail diff --git a/sim/testsuite/sim/sh64/compact/bts.cgs b/sim/testsuite/sim/sh64/compact/bts.cgs new file mode 100644 index 00000000000..3d62e4d822c --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/bts.cgs @@ -0,0 +1,28 @@ +# sh testcase for bt/s $disp8 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global taken +taken: + sett + bt/s ntaken +slot1: + nop + fail + .global ntaken +ntaken: + clrt + bt/s bad +slot2: + nop + pass +bad: + fail + fail + fail + fail diff --git a/sim/testsuite/sim/sh64/compact/clrmac.cgs b/sim/testsuite/sim/sh64/compact/clrmac.cgs new file mode 100644 index 00000000000..482dc804d62 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/clrmac.cgs @@ -0,0 +1,13 @@ +# sh testcase for clrmac -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global clrmac +clrmac: + clrmac + pass diff --git a/sim/testsuite/sim/sh64/compact/clrs.cgs b/sim/testsuite/sim/sh64/compact/clrs.cgs new file mode 100644 index 00000000000..bed5fd5178e --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/clrs.cgs @@ -0,0 +1,14 @@ +# sh testcase for clrs -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global clrs +clrs: + clrs + # Somehow ensure that S is set. + pass diff --git a/sim/testsuite/sim/sh64/compact/clrt.cgs b/sim/testsuite/sim/sh64/compact/clrt.cgs new file mode 100644 index 00000000000..281c2f4243d --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/clrt.cgs @@ -0,0 +1,16 @@ +# sh testcase for clrt -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global clrt +clrt: + clrt + bt wrong + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/cmpeq.cgs b/sim/testsuite/sim/sh64/compact/cmpeq.cgs new file mode 100644 index 00000000000..3cc744cf7f7 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/cmpeq.cgs @@ -0,0 +1,52 @@ +# sh testcase for cmp/eq $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +zeroes: + mov #0, r1 + mov #0, r2 + cmp/eq r1, r2 + bf wrong + +zero1: + mov #0, r1 + mov #1, r2 + cmp/eq r1, r2 + bt wrong + +zero2: + mov #0, r2 + mov #1, r1 + cmp/eq r2, r1 + bt wrong + +equal: + mov #192, r1 + mov #192, r2 + cmp/eq r1, r2 + bf wrong + +noteq: + mov #192, r1 + mov #193, r2 + cmp/eq r1, r2 + bt wrong + +large: + mov #1, r1 + rotr r1 + mov #1, r2 + rotr r2 + cmp/eq r1, r2 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/cmpeqi.cgs b/sim/testsuite/sim/sh64/compact/cmpeqi.cgs new file mode 100644 index 00000000000..79900a0cecc --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/cmpeqi.cgs @@ -0,0 +1,39 @@ +# sh testcase for cmp/eq #$imm8, r0 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +zeroes: + mov #0, r0 + cmp/eq #0, r0 + bf wrong + +zero1: + mov #0, r0 + cmp/eq #1, r0 + bt wrong + +zero2: + mov #1, r0 + cmp/eq #0, r0 + bt wrong + +equal: + mov #192, r0 + cmp/eq #192, r0 + bf wrong + +sign: + mov #255, r0 + cmp/eq #255, r0 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/cmpge.cgs b/sim/testsuite/sim/sh64/compact/cmpge.cgs new file mode 100644 index 00000000000..9d4327e35cc --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/cmpge.cgs @@ -0,0 +1,69 @@ +# sh testcase for cmp/ge $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +zero: + mov #0, r0 + mov #0, r1 + cmp/ge r0, r1 + bf wrong + +onezero: + mov #1, r0 + mov #0, r1 + cmp/ge r0, r1 + bt wrong + +zeroone: + mov #0, r0 + mov #1, r1 + cmp/ge r0, r1 + bf wrong + +equal: + mov #192, r0 + mov #192, r1 + cmp/ge r0, r1 + bf wrong + +eqlarge: + mov #1, r0 + rotr r0 + add #85, r0 + mov #1, r1 + rotr r1 + add #85, r1 + cmp/ge r0, r1 + bf wrong + +large2: + mov #1, r0 + rotr r0 + add #85, r0 + mov #1, r1 + rotr r1 + add #84, r1 + cmp/ge r0, r1 + bt wrong + +large3: + mov #1, r0 + rotr r0 + add #84, r0 + mov #1, r1 + rotr r1 + add #85, r1 + cmp/ge r0, r1 + bf wrong + +okay: + pass + +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/cmpgt.cgs b/sim/testsuite/sim/sh64/compact/cmpgt.cgs new file mode 100644 index 00000000000..460ca65ae68 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/cmpgt.cgs @@ -0,0 +1,69 @@ +# sh testcase for cmp/gt $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +zero: + mov #0, r0 + mov #0, r1 + cmp/gt r0, r1 + bt wrong + +onezero: + mov #1, r0 + mov #0, r1 + cmp/gt r0, r1 + bt wrong + +zeroone: + mov #0, r0 + mov #1, r1 + cmp/gt r0, r1 + bf wrong + +equal: + mov #192, r0 + mov #192, r1 + cmp/gt r0, r1 + bt wrong + +eqlarge: + mov #1, r0 + rotr r0 + add #85, r0 + mov #1, r1 + rotr r1 + add #85, r1 + cmp/gt r0, r1 + bt wrong + +large2: + mov #1, r0 + rotr r0 + add #85, r0 + mov #1, r1 + rotr r1 + add #84, r1 + cmp/gt r0, r1 + bt wrong + +large3: + mov #1, r0 + rotr r0 + add #84, r0 + mov #1, r1 + rotr r1 + add #85, r1 + cmp/gt r0, r1 + bf wrong + +okay: + pass + +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/cmphi.cgs b/sim/testsuite/sim/sh64/compact/cmphi.cgs new file mode 100644 index 00000000000..efbcaa328cd --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/cmphi.cgs @@ -0,0 +1,68 @@ +# sh testcase for cmp/hi $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +zero: + mov #0, r0 + mov #0, r0 + cmp/hi r0, r1 + bt wrong + +equal: + mov #1, r0 + rotr r0 + add #3, r0 + + mov #1, r1 + rotr r1 + add #3, r1 + + cmp/hi r0, r1 + bt wrong + +gt: + mov #10, r0 + mov #12, r1 + cmp/hi r0, r1 + bf wrong + +lt: + mov #12, r0 + mov #10, r1 + cmp/hi r0, r1 + bt wrong + +gtneg: + mov #1, r0 + rotr r0 + add #1, r0 + + mov #1, r1 + rotr r1 + add #3, r1 + + cmp/hi r0, r1 + bf wrong + +ltneg: + mov #1, r0 + rotr r0 + add #3, r0 + + mov #1, r1 + rotr r1 + add #1, r1 + + cmp/hi r0, r1 + bt wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/cmphs.cgs b/sim/testsuite/sim/sh64/compact/cmphs.cgs new file mode 100644 index 00000000000..957f80c0245 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/cmphs.cgs @@ -0,0 +1,59 @@ +# sh testcase for cmp/hs $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +zero: + mov #0, r0 + mov #0, r0 + cmp/hs r0, r1 + +equal: + mov #1, r0 + rotr r0 + add #3, r0 + + mov #1, r1 + rotr r1 + add #3, r1 + + cmp/hs r0, r1 + +gt: + mov #10, r0 + mov #12, r1 + cmp/hs r0, r1 + +lt: + mov #12, r0 + mov #10, r1 + cmp/hs r0, r1 + +gtneg: + mov #1, r0 + rotr r0 + add #1, r0 + + mov #1, r1 + rotr r1 + add #3, r1 + + cmp/hs r0, r1 + +ltneg: + mov #1, r0 + rotr r0 + add #3, r0 + + mov #1, r1 + rotr r1 + add #1, r1 + + cmp/hs r0, r1 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/compact/cmppl.cgs b/sim/testsuite/sim/sh64/compact/cmppl.cgs new file mode 100644 index 00000000000..1c11377f34b --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/cmppl.cgs @@ -0,0 +1,37 @@ +# sh testcase for cmp/pl $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +zero: + mov #0, r0 + cmp/pl r0 + bt wrong + +plus: + mov #10, r0 + cmp/pl r0 + bf wrong + +minus: + mov #10, r0 + neg r0, r0 + cmp/pl r0 + bt wrong + +large: + mov #10, r0 + shll8 r0 + add #123, r0 + cmp/pl r0 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/cmppz.cgs b/sim/testsuite/sim/sh64/compact/cmppz.cgs new file mode 100644 index 00000000000..2e0bf48e827 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/cmppz.cgs @@ -0,0 +1,37 @@ +# sh testcase for cmp/pz $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +zero: + mov #0, r0 + cmp/pz r0 + bf wrong + +plus: + mov #10, r0 + cmp/pz r0 + bf wrong + +minus: + mov #10, r0 + neg r0, r0 + cmp/pz r0 + bt wrong + +large: + mov #10, r0 + shll8 r0 + add #123, r0 + cmp/pz r0 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/cmpstr.cgs b/sim/testsuite/sim/sh64/compact/cmpstr.cgs new file mode 100644 index 00000000000..70d90d33c20 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/cmpstr.cgs @@ -0,0 +1,148 @@ +# sh testcase for cmp/str $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + +.macro rot8 + rotr r0 + rotr r0 + rotr r0 + rotr r0 + rotr r0 + rotr r0 + rotr r0 + rotr r0 +.endm + + start + +# Use multiple "wrong" labels because this program is quite long. It's +# likely that some instructions will be too far away from the branch +# target to use PC-relative branches. + +match0: + # No bytes matching. + mov #1, r0 + neg r0, r0 + xor #170, r0 + rot8 + xor #170, r0 + rot8 + xor #170, r0 + rot8 + xor #170, r0 + rot8 + mov r0, r1 + mov #1, r0 + neg r0, r0 + xor #85, r0 + rot8 + xor #85, r0 + rot8 + xor #85, r0 + rot8 + xor #85, r0 + rot8 + cmp/str r0, r1 + bt wrong0 + + bra match1 + nop +wrong0: + fail + +match1: + # One byte matching. + mov #1, r0 + neg r0, r0 + xor #170, r0 + rot8 + xor #170, r0 + rot8 + xor #170, r0 + rot8 + mov r0, r1 + mov #1, r0 + neg r0, r0 + xor #85, r0 + rot8 + xor #85, r0 + rot8 + xor #85, r0 + rot8 + cmp/str r0, r1 + bf wrong1 + + bra match2 + nop +wrong1: + fail + +match2: + # Two bytes matching. + mov #1, r0 + neg r0, r0 + xor #170, r0 + rot8 + xor #170, r0 + rot8 + mov r0, r1 + mov #1, r0 + neg r0, r0 + xor #85, r0 + rot8 + xor #85, r0 + rot8 + cmp/str r0, r1 + bf wrong2 + + bra match3 + nop +wrong2: + fail + +byte0: +match3: + # One byte matching. + # This is also the test for byte 0. + mov #85, r0 + mov #85, r1 + cmp/str r0, r1 + bf wrong3 + +byte1: + # Match in byte position 1. + mov #85, r0 + shll8 r0 + mov #85, r1 + shll8 r1 + cmp/str r0, r1 + bf wrong3 + +byte2: + # Match in byte position 2. + mov #85, r0 + shll16 r0 + mov #85, r1 + shll16 r1 + cmp/str r0, r1 + bf wrong3 + +byte3: + # Match in byte position 3. + mov #85, r0 + shll16 r0 + shll8 r0 + mov #85, r1 + shll16 r1 + shll8 r1 + cmp/str r0, r1 + bf wrong3 + +okay: + pass +wrong3: + fail + diff --git a/sim/testsuite/sim/sh64/compact/div0s.cgs b/sim/testsuite/sim/sh64/compact/div0s.cgs new file mode 100644 index 00000000000..8cd6422bea8 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/div0s.cgs @@ -0,0 +1,52 @@ +# sh testcase for div0s $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start +init: + mov #0, r0 + mov #3, r1 + mov #4, r2 + neg r1, r3 + neg r2, r4 + +perm1: + div0s r0, r0 + bt wrong + div0s r0, r1 + bt wrong + div0s r1, r0 + bt wrong + +perm2: + div0s r0, r4 + bf wrong + div0s r4, r0 + bf wrong + +perm3: + div0s r1, r2 + bt wrong + div0s r2, r1 + bt wrong + +perm4: + div0s r3, r4 + bt wrong + div0s r4, r3 + bt wrong + +perm5: + div0s r1, r1 + bt wrong + div0s r3, r3 + bt wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/div0u.cgs b/sim/testsuite/sim/sh64/compact/div0u.cgs new file mode 100644 index 00000000000..02f8534d4c4 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/div0u.cgs @@ -0,0 +1,21 @@ +# sh testcase for div0u -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global div0u +div0u: + div0u + # Can't easily test Q and M (other than visually inspecting + # the simulator's trace output). + bt wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/div1.cgs b/sim/testsuite/sim/sh64/compact/div1.cgs new file mode 100644 index 00000000000..63a0e81cb12 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/div1.cgs @@ -0,0 +1,52 @@ +# sh testcase for div1 $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #10, r0 + mov #2, r1 + div0s r0,r1 + + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + div1 r0, r1 + + pass diff --git a/sim/testsuite/sim/sh64/compact/dmulsl.cgs b/sim/testsuite/sim/sh64/compact/dmulsl.cgs new file mode 100644 index 00000000000..081ce169955 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/dmulsl.cgs @@ -0,0 +1,115 @@ +# sh testcase for dmuls.l $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + mov #0, r0 + mov #0, r1 + dmuls.l r0, r1 + # check result + sts mach, r3 + sts macl, r4 + assert r3, #0 + assert r4, #0 + +test2: + mov #0, r0 + mov #5, r1 + dmuls.l r0, r1 + # check result + sts mach, r3 + sts macl, r4 + assert r3, #0 + assert r4, #0 + +test3: + mov #5, r0 + mov #0, r1 + dmuls.l r0, r1 + # check result + sts mach, r3 + sts macl, r4 + assert r3, #0 + assert r4, #0 + +test4: + mov #1, r0 + mov #5, r1 + dmuls.l r0, r1 + # check result + sts mach, r3 + sts macl, r4 + assert r3, #0 + assert r4, #5 + +test5: + mov #5, r0 + mov #1, r1 + dmuls.l r0, r1 + # check result + sts mach, r3 + sts macl, r4 + assert r3, #0 + assert r4, #5 + + bra test6 + nop + +wrong: + fail + +test6: + mov #2, r0 + mov #2, r1 + dmuls.l r0, r1 + # check result + sts mach, r3 + sts macl, r4 + assert r3, #0 + assert r4, #4 + +test7: + mov #1, r0 + neg r0, r0 + mov #2, r1 + dmuls.l r0, r1 + # check result + sts mach, r3 + sts macl, r4 + + mov #0, r8 + not r8, r9 + not r8, r10 + shll r10 + cmp/eq r3, r9 + bf wrong + cmp/eq r4, r10 + bf wrong + +test8: + mov #1, r0 + neg r0, r0 + mov #1, r1 + neg r1, r1 + dmuls.l r0, r1 + # check result + sts mach, r3 + sts macl, r4 + assert r3, #0 + assert r4, #1 + +test9: + mov #1, r0 + neg r0, r0 + shlr r0 + mov #1, r1 + neg r1, r1 + shlr r1 + dmuls.l r0, r1 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/compact/dmulul.cgs b/sim/testsuite/sim/sh64/compact/dmulul.cgs new file mode 100644 index 00000000000..b34b870269d --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/dmulul.cgs @@ -0,0 +1,53 @@ +# sh testcase for dmulu.l $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + mov #0, r0 + mov #0, r1 + dmulu.l r0, r1 + + mov #0, r0 + mov #5, r1 + dmulu.l r0, r1 + + mov #5, r0 + mov #0, r1 + dmulu.l r0, r1 + + mov #1, r0 + mov #5, r1 + dmulu.l r0, r1 + + mov #5, r0 + mov #1, r1 + dmulu.l r0, r1 + + mov #2, r0 + mov #2, r1 + dmulu.l r0, r1 + + mov #1, r0 + neg r0, r0 + mov #2, r1 + dmulu.l r0, r1 + + mov #1, r0 + neg r0, r0 + mov #1, r1 + neg r1, r1 + dmulu.l r0, r1 + + mov #1, r0 + neg r0, r0 + shlr r0 + mov #1, r1 + neg r1, r1 + shlr r1 + dmulu.l r0, r1 + + pass diff --git a/sim/testsuite/sim/sh64/compact/dt.cgs b/sim/testsuite/sim/sh64/compact/dt.cgs new file mode 100644 index 00000000000..38e91638bd9 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/dt.cgs @@ -0,0 +1,42 @@ +# sh testcase for dt $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global dt +dt: + mov #3, r0 + dt r0 + bt wrong + assert r0, #2 + + mov #1, r0 + dt r0 + bf wrong + assert r0, #0 + + mov #0, r0 + dt r0 + bt wrong + mov #0, r7 + not r7, r7 + cmp/eq r7, r0 + bf wrong + + mov #1, r0 + neg r0, r0 + dt r0 + mov #1, r7 + not r7, r7 + cmp/eq r7, r0 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/extsb.cgs b/sim/testsuite/sim/sh64/compact/extsb.cgs new file mode 100644 index 00000000000..90878020a28 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/extsb.cgs @@ -0,0 +1,29 @@ +# sh testcase for exts.b $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global extsb +extsb: + mov #42, r1 + exts.b r1, r2 + assert r2, #42 +signed: + mov #0, r0 + or #255, r0 + exts.b r0, r1 + mov #0, r7 + not r7, r7 + cmp/eq r1, r7 + bf wrong + +okay: + pass + +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/extsw.cgs b/sim/testsuite/sim/sh64/compact/extsw.cgs new file mode 100644 index 00000000000..d6257747df7 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/extsw.cgs @@ -0,0 +1,32 @@ +# sh testcase for exts.w $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global extsw +extsw: + mov #42, r1 + exts.w r1, r2 + assert r2, #42 + +another: + mov #0, r0 + or #255, r0 + shll8 r0 + exts.w r0, r1 + + mov #-1, r7 + shll8 r7 + cmp/eq r1, r7 + bf wrong + +okay: + pass + +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/extub.cgs b/sim/testsuite/sim/sh64/compact/extub.cgs new file mode 100644 index 00000000000..51c14ac4359 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/extub.cgs @@ -0,0 +1,31 @@ +# sh testcase for extu.b $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global extub +extub: + mov #42, r1 + extu.b r1, r2 + assert r2, #42 + +another: + mov #0, r0 + or #255, r0 + extu.b r0, r1 + + mov #0, r0 + or #255, r0 + cmp/eq r0, r1 + bf wrong + +okay: + pass + +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/extuw.cgs b/sim/testsuite/sim/sh64/compact/extuw.cgs new file mode 100644 index 00000000000..057afe7d949 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/extuw.cgs @@ -0,0 +1,31 @@ +# sh testcase for extu.w $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global extuw +extuw: + mov #42, r1 + extu.w r1, r2 + assert r2, #42 + +another: + mov #0, r0 + or #255, r0 + shll8 r0 + extu.w r0, r1 + mov #0, r0 + or #255, r0 + shll8 r0 + cmp/eq r0, r1 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/fabs.cgs b/sim/testsuite/sim/sh64/compact/fabs.cgs new file mode 100644 index 00000000000..6955fa2aa16 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fabs.cgs @@ -0,0 +1,88 @@ +# sh testcase for fabs -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + _clrpr + # fabs(0.0) = 0.0. + fldi0 fr0 + fabs fr0 + fldi0 fr1 + fcmp/eq fr0, fr1 + bf wrong + + # fabs(1.0) = 1.0. + fldi1 fr0 + fabs fr0 + fldi1 fr1 + fcmp/eq fr0, fr1 + bf wrong + + # fabs(-1.0) = 1.0. + fldi1 fr0 + fneg fr0 + fabs fr0 + fldi1 fr1 + fcmp/eq fr0, fr1 + bf wrong + + bra double + nop + +wrong: + fail + +double: + # double precision tests. + # fabs(0.0) = 0.0. + fldi0 fr0 + _s2d fr0, dr0 + _setpr + fabs dr0 + _clrpr + # check. + fldi0 fr2 + _s2d fr2, dr2 + _setpr + fcmp/eq dr0, dr2 + bf wrong + _clrpr + +one: + # fabs(1.0) = 1.0. + fldi1 fr0 + _s2d fr0, dr0 + _setpr + fabs dr0 + _clrpr + # check. + fldi1 fr2 + _s2d fr2, dr2 + _setpr + fcmp/eq dr0, dr2 + bf wrong2 + _clrpr + +minusone: + # fabs(-1.0) = 1.0. + fldi1 fr0 + fneg fr0 + _s2d fr0, dr0 + _setpr + fabs dr0 + _clrpr + # check. + fldi1 fr2 + _s2d fr2, dr2 + _setpr + fcmp/eq dr0, dr2 + bf wrong2 + _clrpr + +okay: + pass +wrong2: + fail diff --git a/sim/testsuite/sim/sh64/compact/fadd.cgs b/sim/testsuite/sim/sh64/compact/fadd.cgs new file mode 100644 index 00000000000..b00035308f8 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fadd.cgs @@ -0,0 +1,31 @@ +# sh testcase for fadd +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + _clrpr + + fldi1 fr0 + fldi1 fr1 + fadd fr0, fr1 + + fldi0 fr0 + fldi1 fr1 + fadd fr0, fr1 + + fldi1 fr0 + fldi0 fr1 + fadd fr0, fr1 + + _setpr +double: + fldi1 fr0 + fldi1 fr1 + _s2d fr0, dr4 + _s2d fr1, dr6 + fadd dr4, dr6 + + pass diff --git a/sim/testsuite/sim/sh64/compact/fcmpeq.cgs b/sim/testsuite/sim/sh64/compact/fcmpeq.cgs new file mode 100644 index 00000000000..151d5e5647a --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fcmpeq.cgs @@ -0,0 +1,88 @@ +# sh testcase for fcmpeq -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + # 1.0 == 1.0. + fldi1 fr0 + fldi1 fr1 + fcmp/eq fr0, fr1 + bf wrong + + # 0.0 != 1.0. + fldi0 fr0 + fldi1 fr1 + fcmp/eq fr0, fr1 + bt wrong + + # 1.0 != 0.0. + fldi1 fr0 + fldi0 fr1 + fcmp/eq fr0, fr1 + bt wrong + + # 2.0 != 1.0 + fldi1 fr0 + fadd fr0, fr0 + fldi1 fr1 + fcmp/eq fr0, fr1 + bt wrong + + bra double + # delay slot + nop + +wrong: + fail + +double: + # 1.0 == 1.0 + fldi1 fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + _setpr + fcmp/eq dr0, dr2 + bf wrong + _clrpr + + # 0.0 != 1.0 + fldi0 fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + _setpr + fcmp/eq dr0, dr2 + bt wrong + _clrpr + + # 1.0 != 0.0 + fldi1 fr0 + fldi0 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + _setpr + fcmp/eq dr0, dr2 + bt wrong2 + _clrpr + + # 2.0 != 1.0 + fldi1 fr0 + fadd fr0, fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + _setpr + fcmp/eq dr0, dr2 + bt wrong2 + _clrpr + +okay: + pass + +wrong2: + fail diff --git a/sim/testsuite/sim/sh64/compact/fcmpgt.cgs b/sim/testsuite/sim/sh64/compact/fcmpgt.cgs new file mode 100644 index 00000000000..931ae3e2e6c --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fcmpgt.cgs @@ -0,0 +1,95 @@ +# sh testcase for fcmpgt -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + # 1.0 !> 1.0. + fldi1 fr0 + fldi1 fr1 + fcmp/gt fr0, fr1 + bt wrong + + # 0.0 !> 1.0. + fldi0 fr0 + fldi1 fr1 + fcmp/gt fr0, fr1 + bf wrong + + # 1.0 > 0.0. + fldi1 fr0 + fldi0 fr1 + fcmp/gt fr0, fr1 + bt wrong + + # 2.0 > 1.0 + fldi1 fr0 + fadd fr0, fr0 + fldi1 fr1 + fcmp/gt fr0, fr1 + bt wrong + + bra double + nop + +wrong: + fail + +double: + # double precision tests. + # 1.0 !> 1.0. + fldi1 fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + _setpr + fcmp/gt dr0, dr2 + bt wrong2 + _clrpr + + # 0.0 !> 1.0. + fldi0 fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + _setpr + fcmp/gt dr0, dr2 + bf wrong2 + _clrpr + + bra next + nop + +wrong2: + fail + +next: + # 1.0 > 0.0. + fldi1 fr0 + fldi0 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + _setpr + fcmp/gt dr0, dr2 + bt wrong2 + _clrpr + + # 2.0 > 1.0. + fldi1 fr0 + fadd fr0, fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + _setpr + fcmp/gt dr0, dr2 + bt wrong2 + _clrpr + +okay: + pass + +wrong3: + fail diff --git a/sim/testsuite/sim/sh64/compact/fcnvds.cgs b/sim/testsuite/sim/sh64/compact/fcnvds.cgs new file mode 100644 index 00000000000..abf9e704ffb --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fcnvds.cgs @@ -0,0 +1,13 @@ +# sh testcase for fcnvds -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + _setpr + fcnvds dr0, fpul + _clrpr +okay: + pass diff --git a/sim/testsuite/sim/sh64/compact/fcnvsd.cgs b/sim/testsuite/sim/sh64/compact/fcnvsd.cgs new file mode 100644 index 00000000000..699bde55c6e --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fcnvsd.cgs @@ -0,0 +1,27 @@ +# sh testcase for fcnvsd -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + fldi1 fr0 + flds fr0, fpul + _setpr + fcnvsd fpul, dr2 + _clrpr + + # Convert back. + _setpr + fcnvds dr2, fpul + _clrpr + fsts fpul, fr1 + fcmp/eq fr0, fr1 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/fdiv.cgs b/sim/testsuite/sim/sh64/compact/fdiv.cgs new file mode 100644 index 00000000000..06d1e93a014 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fdiv.cgs @@ -0,0 +1,83 @@ +# sh testcase for fdiv -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + _clrpr + + # 1.0 / 0.0 should be INF + # (and not crash the sim). + fldi0 fr0 + fldi1 fr1 + fdiv fr0, fr1 + + # 0.0 / 1.0 == 0.0. + fldi0 fr0 + fldi1 fr1 + fdiv fr1, fr0 + fldi0 fr2 + fcmp/eq fr0, fr2 + bf wrong + + # 2.0 / 1.0 == 2.0. + fldi1 fr1 + fldi1 fr2 + fadd fr2, fr2 + fdiv fr1, fr2 + # Load 2.0 into fr3. + fldi1 fr3 + fadd fr3, fr3 + fcmp/eq fr2, fr3 + bf wrong + + # (1.0 / 2.0) + (1.0 / 2.0) == 1.0. + fldi1 fr1 + fldi1 fr2 + fadd fr2, fr2 + fdiv fr2, fr1 + # fr1 should contain 0.5. + fadd fr1, fr1 + # Load 1.0 into fr3. + fldi1 fr3 + # Compare fr1 with fr3. + fcmp/eq fr1, fr3 + bf wrong + + bra double + nop + +wrong: + fail + +double: + # double test + # (1.0 / 2.0) + (1.0 / 2.0) == 1.0. + fldi1 fr1 + _s2d fr1, dr6 + fldi1 fr2 + fadd fr2, fr2 + _s2d fr2, dr8 + _setpr + fdiv dr8, dr6 + # dr0 should contain 0.5. + # double it, expect 1.0. + fadd dr6, dr6 + _clrpr +foo: + # Load 1.0 into dr4. + fldi1 fr1 + _s2d fr1, dr10 + # Compare dr0 with dr10. + _setpr + fcmp/eq dr6, dr10 + bf wrong2 + _clrpr + +okay: + pass + +wrong2: + fail diff --git a/sim/testsuite/sim/sh64/compact/fipr.cgs b/sim/testsuite/sim/sh64/compact/fipr.cgs new file mode 100644 index 00000000000..092f0f6c066 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fipr.cgs @@ -0,0 +1,44 @@ +# sh testcase for fipr $fvm, $fvn +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start +initv1: + fldi1 fr0 + # Load 2 into fr2. + fldi1 fr1 + fadd fr1, fr1 + # Load 4 into fr2. + fldi1 fr2 + fadd fr2, fr2 + fadd fr2, fr2 + fldi0 fr3 + +initv2: + fldi1 fr8 + fldi0 fr9 + fldi1 fr10 + fldi0 fr11 + + fipr fv0, fv8 + + # Result will be in fr11. + fldi1 fr0 + fldi1 fr1 + # Two. + fadd fr1, fr0 + # Four. + fadd fr0, fr0 + # Five. + fadd fr1, fr0 + fcmp/eq fr0, fr11 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/fldi0.cgs b/sim/testsuite/sim/sh64/compact/fldi0.cgs new file mode 100644 index 00000000000..b0d35e4fb09 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fldi0.cgs @@ -0,0 +1,17 @@ +# sh testcase for fldi0 $frn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + fldi0 fr0 + fldi0 fr2 + fldi0 fr4 + fldi0 fr6 + fldi0 fr8 + fldi0 fr10 + fldi0 fr12 + fldi0 fr14 + pass diff --git a/sim/testsuite/sim/sh64/compact/fldi1.cgs b/sim/testsuite/sim/sh64/compact/fldi1.cgs new file mode 100644 index 00000000000..8bd5c521be2 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fldi1.cgs @@ -0,0 +1,17 @@ +# sh testcase for fldi1 $frn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + fldi1 fr1 + fldi1 fr3 + fldi1 fr5 + fldi1 fr7 + fldi1 fr9 + fldi1 fr11 + fldi1 fr13 + fldi1 fr15 + pass diff --git a/sim/testsuite/sim/sh64/compact/flds.cgs b/sim/testsuite/sim/sh64/compact/flds.cgs new file mode 100644 index 00000000000..797e7cba9ab --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/flds.cgs @@ -0,0 +1,26 @@ +# sh testcase for flds -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + fldi0 fr0 + flds fr0, fpul + fsts fpul, fr1 + fcmp/eq fr0, fr1 + bf wrong + + fldi1 fr0 + flds fr0, fpul + fsts fpul, fr1 + fcmp/eq fr0, fr1 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/float.cgs b/sim/testsuite/sim/sh64/compact/float.cgs new file mode 100644 index 00000000000..8532d7fd651 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/float.cgs @@ -0,0 +1,80 @@ +# sh testcase for float -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +pos: + mov #3, r0 + lds r0, fpul + float fpul, fr7 + + # Check the result. + fldi1 fr0 + fldi1 fr1 + fadd fr0, fr1 + fadd fr0, fr1 + fcmp/eq fr1, fr7 + bf wrong + +neg: + mov #3, r0 + neg r0, r0 + lds r0, fpul + float fpul, fr7 + + # Check the result. + fldi1 fr0 + fldi1 fr1 + fadd fr0, fr1 + fadd fr0, fr1 + fneg fr1 + fcmp/eq fr1, fr7 + bf wrong + + bra double + nop + +wrong: + fail + +double: + mov #3, r0 + lds r0, fpul + _setpr + float fpul, dr8 + _clrpr + # check the result. + fldi1 fr0 + fldi1 fr1 + fadd fr0, fr1 + fadd fr0, fr1 + _s2d fr1, dr2 + fcmp/eq dr2, dr8 + bf wrong + +dneg: + mov #3, r0 + neg r0, r0 + lds r0, fpul + _setpr + float fpul, dr8 + _clrpr + # check the result. + fldi1 fr0 + fldi1 fr1 + fadd fr0, fr1 + fadd fr0, fr1 + fneg fr1 + _s2d fr1, dr2 + fcmp/eq dr2, dr8 + bf wrong + +okay: + pass + +wrong2: + fail diff --git a/sim/testsuite/sim/sh64/compact/fmac.cgs b/sim/testsuite/sim/sh64/compact/fmac.cgs new file mode 100644 index 00000000000..dbf36ab78c8 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fmac.cgs @@ -0,0 +1,78 @@ +# sh testcase for fmac -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + # 0.0 * x + y = y. + + fldi0 fr0 + fldi1 fr1 + fldi1 fr2 + fmac fr0, fr1, fr2 + # check result. + fldi1 fr0 + fcmp/eq fr0, fr2 + bf wrong + + # x * y + 0.0 = x * y. + + fldi1 fr0 + fldi1 fr1 + fldi0 fr2 + # double it. + fadd fr1, fr2 + fmac fr0, fr1, fr2 + # check result. + fldi1 fr0 + fadd fr0, fr0 + fcmp/eq fr0, fr2 + bf wrong + + # x * 0.0 + y = y. + + fldi1 fr0 + fldi0 fr1 + fldi1 fr2 + fadd fr2, fr2 + fmac fr0, fr1, fr2 + # check result. + fldi1 fr0 + # double fr0. + fadd fr0, fr0 + fcmp/eq fr0, fr2 + bf wrong + + # x * 0.0 + 0.0 = 0.0 + + fldi1 fr0 + fadd fr0, fr0 + fldi0 fr1 + fldi0 fr2 + fmac fr0, fr1, fr2 + # check result. + fldi0 fr0 + fcmp/eq fr0, fr2 + bf wrong + + # 0.0 * x + 0.0 = 0.0. + + fldi0 fr0 + fldi1 fr1 + # double it. + fadd fr1, fr1 + fldi0 fr2 + fmac fr0, fr1, fr2 + # check result. + fldi0 fr0 + fcmp/eq fr0, fr2 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/fmov.cgs b/sim/testsuite/sim/sh64/compact/fmov.cgs new file mode 100644 index 00000000000..f4e1fde3c11 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fmov.cgs @@ -0,0 +1,273 @@ +# sh testcase for all fmov instructions +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + .macro init + fldi0 fr0 + fldi1 fr2 + .endm + + # Set the SZ (SiZe) bit in the fpscr. + .macro _setsz + sts fpscr, r7 + mov #16, r8 + shll16 r8 + or r8, r7 + lds r7, fpscr + .endm + + # Clear the SZ bit. + .macro _clrsz + sts fpscr, r7 + mov #16, r8 + shll16 r8 + not r8, r8 + and r8, r7 + lds r7, fpscr + .endm + start + +fmov1: # Test fr -> fr. + init + _clrpr + _clrsz + fmov fr0, fr10 + # Ensure fr0 and fr10 are now equal. + fcmp/eq fr0, fr10 + bt fmov2 + fail + +fmov2: # Test dr -> dr. + init + _setpr + _setsz + fmov dr0, dr2 + # Ensure dr0 and dr2 are now equal. + fcmp/eq dr0, dr2 + bt fmov3 + fail + +fmov3: # Test dr -> xd and xd -> dr. + init + _setsz + fmov dr0, xd0 + # Ensure dr0 and xd0 are now equal. + fmov xd0, dr2 + fcmp/eq dr0, dr2 + bt fmov4 + fail + +fmov4: # Test xd -> xd. + init + _setsz + _setpr + fmov dr0, xd0 + fmov xd0, xd2 + fmov xd2, dr2 + # Ensure dr0 and dr2 are now equal. + fcmp/eq dr0, dr2 + bt fmov5 + fail + +fmov5: # Test fr -> @rn and @rn -> fr. + init + _clrsz + _clrpr + mov #40, r0 + shll8 r0 + fmov fr0, @r0 + fmov @r0, fr1 + fcmp/eq fr0, fr1 + bt fmov6 + fail + +fmov6: # Test dr -> @rn and @rn -> dr. + init + _setsz + _setpr + mov #40, r0 + shll8 r0 + fmov dr0, @r0 + fmov @r0, dr2 + fcmp/eq dr0, dr2 + bt fmov7 + fail + +fmov7: # Test xd -> @rn and @rn -> xd. + init + _setsz + _setpr + mov #40, r0 + shll8 r0 + fmov dr0, xd0 + fmov xd0, @r0 + fmov @r0, xd2 + fmov xd2, dr2 + fcmp/eq dr0, dr2 + bt fmov8 + fail + +fmov8: # Test fr -> @-rn. + init + _clrsz + _clrpr + mov #40, r0 + shll8 r0 + # Preserve. + mov r0, r1 + fmov fr0, @-r0 + fmov @r0, fr2 + fcmp/eq fr0, fr2 + bt f8b + fail +f8b: # check pre-dec. + add #4, r0 + cmp/eq r0, r1 + bt fmov9 + fail + +fmov9: # Test dr -> @-rn. + init + _setsz + _setpr + mov #40, r0 + shll8 r0 + # Preserve r0. + mov r0, r1 + fmov dr0, @-r0 + fmov @r0, dr2 + fcmp/eq dr0, dr2 + bt f9b + fail +f9b: # check pre-dec. + add #8, r0 + cmp/eq r0, r1 + bt fmov10 + fail + +fmov10: # Test xd -> @-rn. + init + _setsz + _setpr + mov #40, r0 + shll8 r0 + # Preserve r0. + mov r0, r1 + fmov dr0, xd0 + fmov xd0, @-r0 + fmov @r0, xd2 + fmov xd2, dr2 + fcmp/eq dr0, dr2 + bt f10b + fail +f10b: # check pre-dec. + add #8, r0 + cmp/eq r0, r1 + bt fmov11 + fail + +fmov11: # Test @rn+ -> fr. + init + _clrsz + _clrpr + mov #40, r0 + shll8 r0 + # Preserve r0. + mov r0, r1 + fmov fr0, @r0 + fmov @r0+, fr2 + fcmp/eq fr0, fr2 + bt f11b + fail +f11b: # check post-inc. + add #4, r1 + cmp/eq r0, r1 + bt fmov12 + fail + +fmov12: # Test @rn+ -> dr. + init + _setsz + _setpr + mov #40, r0 + shll8 r0 + # preserve r0. + mov r0, r1 + fmov dr0, @r0 + fmov @r0+, dr2 + fcmp/eq dr0, dr2 + bt f12b + fail +f12b: # check post-inc. + add #8, r1 + cmp/eq r0, r1 + bt fmov13 + fail + +fmov13: # Test @rn -> xd. + init + _setsz + _setpr + mov #40, r0 + shll8 r0 + # Preserve r0. + mov r0, r1 + fmov dr0, xd0 + fmov xd0, @r0 + fmov @r0+, xd2 + fmov xd2, dr2 + fcmp/eq dr0, dr2 + bt f13b + fail +f13b: + add #8, r1 + cmp/eq r0, r1 + bt fmov14 + fail + +fmov14: # Test fr -> @(r0,rn), @(r0, rn) -> fr. + init + _clrsz + _clrpr + mov #40, r0 + shll8 r0 + mov #0, r1 + fmov fr0, @(r0, r1) + fmov @(r0, r1), fr1 + fcmp/eq fr0, fr1 + bt fmov15 + fail + +fmov15: # Test dr -> @(r0, rn), @(r0, rn) -> dr. + init + _setsz + _setpr + mov #40, r0 + shll8 r0 + mov #0, r1 + fmov dr0, @(r0, r1) + fmov @(r0, r1), dr2 + fcmp/eq dr0, dr2 + bt fmov16 + fail + +fmov16: # Test xd -> @(r0, rn), @(r0, rn) -> xd. + init + _setsz + _setpr + mov #40, r0 + shll8 r0 + mov #0, r1 + fmov dr0, xd0 + fmov xd0, @(r0, r1) + fmov @(r0, r1), xd2 + fmov xd2, dr2 + fcmp/eq dr0, dr2 + bt okay + fail + +okay: + pass diff --git a/sim/testsuite/sim/sh64/compact/fmul.cgs b/sim/testsuite/sim/sh64/compact/fmul.cgs new file mode 100644 index 00000000000..a1325d6395b --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fmul.cgs @@ -0,0 +1,121 @@ +# sh testcase for fmul -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + .macro init + fldi0 fr0 + fldi1 fr1 + fldi1 fr2 + fadd fr2, fr2 + fldi0 fr7 + fldi1 fr8 + .endm + + start + + # 0.0 * 0.0 = 0.0. + init + fmul fr0, fr0 + fcmp/eq fr7, fr0 + bf wrong + + # 0.0 * 1.0 = 0.0. + init + fmul fr1, fr0 + fcmp/eq fr7, fr0 + bf wrong + + # 1.0 * 0.0 = 0.0. + init + fmul fr0, fr1 + fcmp/eq fr7, fr1 + bf wrong + + # 1.0 * 1.0 = 1.0. + init + fmul fr1, fr1 + fcmp/eq fr8, fr1 + bf wrong + + # 2.0 * 1.0 = 2.0. + init + fmul fr2, fr1 + fcmp/eq fr2, fr1 + bf wrong + + bra double + nop + +wrong: + fail + + .macro dinit + fldi0 fr0 + fldi1 fr2 + fldi1 fr4 + fadd fr4, fr4 + fldi0 fr8 + fldi1 fr10 + _s2d fr0, dr0 + _s2d fr2, dr2 + _s2d fr4, dr4 + _s2d fr8, dr8 + _s2d fr10, dr10 + .endm + +double: + # 0.0 * 0.0 = 0.0. + dinit + _setpr + fmul dr0, dr0 + fcmp/eq dr8, dr0 + bf wrong + _clrpr + + # 0.0 * 1.0 = 0.0. + dinit + _setpr + fmul dr2, dr0 + fcmp/eq dr8, dr0 + bf wrong2 + _clrpr + + # 1.0 * 0.0 = 0.0. + dinit + _setpr + fmul dr0, dr2 + fcmp/eq dr8, dr2 + bf wrong2 + _clrpr + + bra next + nop + +wrong2: + fail + +next: + # 1.0 * 1.0 = 1.0. + dinit + _setpr + fmul dr2, dr2 + fcmp/eq dr10, dr2 + bf wrong3 + _clrpr + + # 2.0 * 1.0 = 2.0. + dinit + _setpr + fmul dr4, dr2 + fcmp/eq dr4, dr2 + bf wrong3 + _clrpr + +okay: + pass + +wrong3: + fail diff --git a/sim/testsuite/sim/sh64/compact/fneg.cgs b/sim/testsuite/sim/sh64/compact/fneg.cgs new file mode 100644 index 00000000000..71fc901fb6d --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fneg.cgs @@ -0,0 +1,83 @@ +# sh testcase for fneg -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + # neg(0.0) = 0.0. + fldi0 fr0 + fldi0 fr1 + fneg fr0 + fcmp/eq fr0, fr1 + bf wrong + + # neg(1.0) = fsub(0,1) + fldi1 fr0 + fneg fr0 + fldi0 fr1 + fldi1 fr2 + fsub fr2, fr1 + fcmp/eq fr0, fr1 + bf wrong + + # neg(neg(1.0)) = 1.0. + fldi1 fr0 + fldi1 fr1 + fneg fr0 + fneg fr0 + fcmp/eq fr0, fr1 + bf wrong + + bra double + nop + +wrong: + fail + +double: + # neg(0.0) = 0.0. + fldi0 fr0 + fldi0 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + _setpr + fneg dr0 + fcmp/eq dr0, dr2 + bf wrong2 + _clrpr + + # neg(1.0) = fsub(0,1) + fldi1 fr0 + _s2d fr0, dr0 + _setpr + fneg dr0 + _clrpr + fldi0 fr2 + fldi1 fr3 + fsub fr3, fr2 + _s2d fr2, dr2 + _setpr + fcmp/eq fr0, fr2 + bf wrong2 + _clrpr + + # neg(neg(1.0)) = 1.0. + fldi1 fr0 + _s2d fr0, dr0 + fldi1 fr2 + _s2d fr2, dr2 + _setpr + fneg dr0 + fneg dr2 + fcmp/eq dr0, dr2 + bf wrong2 + _clrpr + +okay: + pass + +wrong2: + fail diff --git a/sim/testsuite/sim/sh64/compact/frchg.cgs b/sim/testsuite/sim/sh64/compact/frchg.cgs new file mode 100644 index 00000000000..6f2e743fc37 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/frchg.cgs @@ -0,0 +1,13 @@ +# sh testcase for frchg +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + frchg + frchg + frchg + frchg + pass diff --git a/sim/testsuite/sim/sh64/compact/fschg.cgs b/sim/testsuite/sim/sh64/compact/fschg.cgs new file mode 100644 index 00000000000..54a1491962b --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fschg.cgs @@ -0,0 +1,13 @@ +# sh testcase for fschg +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + fschg + fschg + fschg + fschg + pass diff --git a/sim/testsuite/sim/sh64/compact/fsqrt.cgs b/sim/testsuite/sim/sh64/compact/fsqrt.cgs new file mode 100644 index 00000000000..933e112c903 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fsqrt.cgs @@ -0,0 +1,93 @@ +# sh testcase for fsqrt -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + # sqrt(0.0) = 0.0. + fldi0 fr0 + fsqrt fr0 + fldi0 fr1 + fcmp/eq fr0, fr1 + bf wrong + + # sqrt(1.0) = 1.0. + fldi1 fr0 + fsqrt fr0 + fldi1 fr1 + fcmp/eq fr0, fr1 + bf wrong + + # sqrt(4.0) = 2.0 + fldi1 fr0 + # Double it. + fadd fr0, fr0 + # Double it again. + fadd fr0, fr0 + fsqrt fr0 + fldi1 fr1 + # Double it. + fadd fr1, fr1 + fcmp/eq fr0, fr1 + bf wrong + + bra double + nop + +wrong: + fail + +double: + # sqrt(0.0) = 0.0. + fldi0 fr0 + _s2d fr0, dr0 + _setpr + fsqrt dr0 + _clrpr + fldi0 fr2 + _s2d fr2, dr2 + _setpr + fcmp/eq dr0, dr2 + bf wrong2 + _clrpr + + # sqrt(1.0) = 1.0. + fldi1 fr0 + _s2d fr0, dr0 + _setpr + fsqrt dr0 + _clrpr + fldi1 fr2 + _s2d fr2, dr2 + _setpr + fcmp/eq fr0, fr2 + bf wrong2 + _clrpr + + # sqrt(4.0) = 2.0. + fldi1 fr0 + # Double it. + fadd fr0, fr0 + # Double it again. + fadd fr0, fr0 + _s2d fr0, dr0 + _setpr + fsqrt dr0 + _clrpr + fldi1 fr2 + # Double it. + fadd fr2, fr2 + _s2d fr2, dr2 + _setpr + fcmp/eq fr0, fr2 + bf wrong2 + _clrpr + +okay: + pass + +wrong2: + fail diff --git a/sim/testsuite/sim/sh64/compact/fsts.cgs b/sim/testsuite/sim/sh64/compact/fsts.cgs new file mode 100644 index 00000000000..518533db094 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fsts.cgs @@ -0,0 +1,11 @@ +# sh testcase for fsts fpul, $frn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + fsts fpul, fr0 + fsts fpul, fr1 + pass diff --git a/sim/testsuite/sim/sh64/compact/fsub.cgs b/sim/testsuite/sim/sh64/compact/fsub.cgs new file mode 100644 index 00000000000..346d01ffcaa --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/fsub.cgs @@ -0,0 +1,120 @@ +# sh testcase for fmul -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + # 0.0 - 0.0 = 0.0. + fldi0 fr0 + fldi0 fr1 + fsub fr0, fr1 + fldi0 fr2 + fcmp/eq fr1, fr2 + bf wrong + + # 1.0 - 0.0 = 1.0. + fldi0 fr0 + fldi1 fr1 + fsub fr0, fr1 + fldi1 fr2 + fcmp/eq fr1, fr2 + bf wrong + + # 1.0 - 1.0 = 0.0. + fldi1 fr0 + fldi1 fr1 + fsub fr0, fr1 + fldi0 fr2 + fcmp/eq fr1, fr2 + bf wrong + + # 0.0 - 1.0 = -1.0. + fldi1 fr0 + fldi0 fr1 + fsub fr0, fr1 + fldi1 fr2 + fneg fr2 + fcmp/eq fr1, fr2 + bf wrong + + bra double + nop + +wrong: + fail + +double: + # 0.0 - 0.0 = 0.0. + fldi0 fr0 + fldi0 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + _setpr + fsub dr0, dr2 + _clrpr + fldi0 fr4 + _s2d fr4, dr4 + _setpr + fcmp/eq dr2, dr4 + bf wrong + _clrpr + +onezero: + # 1.0 - 0.0 = 1.0. + fldi0 fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + _setpr + fsub dr0, dr2 + _clrpr + fldi1 fr4 + _s2d fr4, dr4 + _setpr + fcmp/eq dr2, dr4 + bf wrong2 + _clrpr + +oneone: + # 1.0 - 1.0 = 0.0. + fldi1 fr0 + fldi1 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + _setpr + fsub dr0, dr2 + _clrpr + fldi0 fr4 + _s2d fr4, dr4 + _setpr + fcmp/eq dr2, dr4 + bf wrong2 + _clrpr + + bra zeroone + nop + +wrong2: + fail + +zeroone: + # 0.0 - 1.0 = -1.0. + fldi1 fr0 + fldi0 fr2 + _s2d fr0, dr0 + _s2d fr2, dr2 + _setpr + fsub dr0, dr2 + _clrpr + fldi1 fr4 + fneg fr4 + _s2d fr4, dr4 + _setpr + fcmp/eq dr2, dr4 + bf wrong2 + _clrpr + +okay: + pass diff --git a/sim/testsuite/sim/sh64/compact/ftrc.cgs b/sim/testsuite/sim/sh64/compact/ftrc.cgs new file mode 100644 index 00000000000..6a89744b33e --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/ftrc.cgs @@ -0,0 +1,132 @@ +# sh testcase for ftrc -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + # ftrc(0.0) = 0. + fldi0 fr0 + ftrc fr0, fpul + # check results. + mov #0, r0 + sts fpul, r1 + cmp/eq r0, r1 + bf wrong + + # ftrc(1.5) = 1. + fldi1 fr0 + fldi1 fr1 + fldi1 fr2 + # double it. + fadd fr2, fr2 + # form the fraction. + fdiv fr2, fr1 + fadd fr1, fr0 + # now we've got 1.5 in fr0. + ftrc fr0, fpul + # check results. + mov #1, r0 + sts fpul, r1 + cmp/eq r0, r1 + bf wrong + + # ftrc(-1.5) = -1. + fldi1 fr0 + fneg fr0 + fldi1 fr1 + fldi1 fr2 + # double it. + fadd fr2, fr2 + # form the fraction. + fdiv fr2, fr1 + fneg fr1 + # -1 + -0.5 = -1.5. + fadd fr1, fr0 + # now we've got 1.5 in fr0. + ftrc fr0, fpul + # check results. + mov #1, r0 + neg r0, r0 + sts fpul, r1 + cmp/eq r0, r1 + bf wrong + + bra double + nop + +wrong: + fail + +double: + # ftrc(0.0) = 0. + fldi0 fr0 + _s2d fr0, dr0 + _setpr + ftrc dr0, fpul + _clrpr + # check results. + mov #0, r0 + sts fpul, r1 + cmp/eq r0, r1 +foo: + bf wrong2 + + # ftrc(1.5) = 1. + fldi1 fr0 + fldi1 fr2 + fldi1 fr4 + # double it. + fadd fr4, fr4 + # form 0.5. + fdiv fr4, fr2 + fadd fr2, fr0 + # now we've got 1.5 in fr0, so do some single->double + # conversions and perform the ftrc. + _s2d fr0, dr0 + _s2d fr2, dr2 + _s2d fr4, dr4 + _setpr + ftrc dr0, fpul + _clrpr + + # check results. + mov #1, r0 + sts fpul, r1 + cmp/eq r0, r1 + bf wrong2 + + # ftrc(-1.5) = -1. + fldi1 fr0 + fneg fr0 + fldi1 fr2 + fldi1 fr4 + # double it. + fadd fr4, fr4 + # form the fraction. + fdiv fr4, fr2 + fneg fr2 + # -1 + -0.5 = -1.5. + fadd fr2, fr0 + # now we've got 1.5 in fr0, so do some single->double + # conversions and perform the ftrc. + _s2d fr0, dr0 + _s2d fr2, dr2 + _s2d fr4, dr4 + _setpr + ftrc dr0, fpul + _clrpr + + # check results. + mov #1, r0 + neg r0, r0 + sts fpul, r1 + cmp/eq r0, r1 + bf wrong2 + +okay: + pass +wrong2: + fail diff --git a/sim/testsuite/sim/sh64/compact/ftrv.cgs b/sim/testsuite/sim/sh64/compact/ftrv.cgs new file mode 100644 index 00000000000..9bdf806ba13 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/ftrv.cgs @@ -0,0 +1,74 @@ +# sh testcase for ftrv xmtrx, $fvn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + # set the fr bit in the fpscr + .macro _setfr + sts fpscr, r7 + mov #32, r8 + shll16 r8 + or r8, r7 + lds r7, fpscr + .endm + + # clear the fr bit + .macro _clrfr + sts fpscr, r7 + mov #32, r8 + shll16 r8 + not r8, r8 + and r8, r7 + lds r7, fpscr + .endm + + .macro incr old new + fldi1 \new + fadd \old, \new + .endm + + start + _setfr +popmtrx: + # 1.0. + fldi1 fr0 + # 2.0. + fldi1 fr1 + fadd fr1, fr1 + + incr fr1, fr2 + incr fr2, fr3 + incr fr3, fr4 + incr fr4, fr5 + incr fr5, fr6 + incr fr6, fr7 + incr fr7, fr8 + incr fr8, fr9 + incr fr9, fr10 + incr fr10, fr11 + incr fr11, fr12 + incr fr12, fr13 + incr fr13, fr14 + incr fr14, fr15 + +popvect: + # Swtich fp banks. + _clrfr + fldi1 fr4 + fldi1 fr5 + fadd fr5, fr5 + fldi1 fr6 + fadd fr5, fr6 + fldi1 fr7 + fadd fr6, fr7 + +ftrv: + # fr[4,7] should contain the results: + # { 30, 70, 110, 150 }. + ftrv xmtrx, fv4 + +okay: + pass + diff --git a/sim/testsuite/sim/sh64/compact/jmp.cgs b/sim/testsuite/sim/sh64/compact/jmp.cgs new file mode 100644 index 00000000000..e9e99401545 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/jmp.cgs @@ -0,0 +1,29 @@ +# sh testcase for jmp @$rn +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global jmp +jmp: + # Load 0x1010 into r0. + mov #1, r0 + shll8 r0 + shll2 r0 + shll2 r0 + add #16, r0 + jmp @r0 +slot: + nop +bad: + fail +okay: + pass +alsobad: + fail + fail + fail + diff --git a/sim/testsuite/sim/sh64/compact/jsr.cgs b/sim/testsuite/sim/sh64/compact/jsr.cgs new file mode 100644 index 00000000000..5ad7aefc931 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/jsr.cgs @@ -0,0 +1,29 @@ +# sh testcase for jsr @$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global jsr +jsr: + # Load 0x1010 into r0. + mov #1, r0 + shll8 r0 + shll2 r0 + shll2 r0 + add #16, r0 + jsr @r0 +slot: + nop +bad: + fail +okay: + pass +alsobad: + fail + fail + fail + diff --git a/sim/testsuite/sim/sh64/compact/ldc-gbr.cgs b/sim/testsuite/sim/sh64/compact/ldc-gbr.cgs new file mode 100644 index 00000000000..b19a3c194fe --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/ldc-gbr.cgs @@ -0,0 +1,22 @@ +# sh testcase for ldc $rn, gbr -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global ldc +ldc: + mov #40, r0 + shll8 r0 + ldc r0, gbr + stc gbr, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/ldcl-gbr.cgs b/sim/testsuite/sim/sh64/compact/ldcl-gbr.cgs new file mode 100644 index 00000000000..613e58e722c --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/ldcl-gbr.cgs @@ -0,0 +1,28 @@ +# sh testcase for ldc.l @${rn}+, gbr -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global ldcl +ldcl: + mov #40, r0 + shll8 r0 + # Preserve address. + mov r0, r1 + ldc.l @r0+, gbr + + # Add 4 to saved address (r1). + # Then compare with r0. + add #4, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/lds-fpscr.cgs b/sim/testsuite/sim/sh64/compact/lds-fpscr.cgs new file mode 100644 index 00000000000..2dce253375d --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/lds-fpscr.cgs @@ -0,0 +1,22 @@ +# sh testcase for lds $rn, fpscr -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global lds_fpscr +lds_fpscr: + mov #0, r0 + lds r0, fpscr +readback: + sts fpscr, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/lds-fpul.cgs b/sim/testsuite/sim/sh64/compact/lds-fpul.cgs new file mode 100644 index 00000000000..1a80a7032ea --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/lds-fpul.cgs @@ -0,0 +1,17 @@ +# sh testcase for lds $rn, fpul -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global lds_fpul +lds_fpul: + mov #63, r0 + shll8 r0 + add #128, r0 + shll16 r0 + lds r0, fpul + pass diff --git a/sim/testsuite/sim/sh64/compact/lds-mach.cgs b/sim/testsuite/sim/sh64/compact/lds-mach.cgs new file mode 100644 index 00000000000..1ffd6566c9a --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/lds-mach.cgs @@ -0,0 +1,23 @@ +# sh testcase for lds $rn, mach +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global lds_mach +lds_mach: + mov #41, r0 + shll8 r0 + lds r0, mach +readback: + sts mach, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/lds-macl.cgs b/sim/testsuite/sim/sh64/compact/lds-macl.cgs new file mode 100644 index 00000000000..f09315abbb6 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/lds-macl.cgs @@ -0,0 +1,23 @@ +# sh testcase for lds $rn, macl +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global lds_macl +lds_macl: + mov #42, r0 + shll8 r0 + lds r0, macl +readback: + sts macl, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/lds-pr.cgs b/sim/testsuite/sim/sh64/compact/lds-pr.cgs new file mode 100644 index 00000000000..97e3a650767 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/lds-pr.cgs @@ -0,0 +1,23 @@ +# sh testcase for lds $rn, pr +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global lds_pr +lds_pr: + mov #40, r0 + shll8 r0 + lds r0, pr +readback: + sts pr, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/ldsl-fpscr.cgs b/sim/testsuite/sim/sh64/compact/ldsl-fpscr.cgs new file mode 100644 index 00000000000..642f15dc527 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/ldsl-fpscr.cgs @@ -0,0 +1,43 @@ +# sh testcase for lds.l @${rn}+, fpscr -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + mov #40, r0 + shll8 r0 + # save address for later examination. + mov r0, r1 + + # Build up a distinctive bit pattern. + mov #1, r2 + shll8 r2 + add #12, r2 + shll8 r2 + add #85, r2 + shll8 r2 + add #170, r2 + # Store it in memory. + mov.l r2, @r0 + + lds.l @r0+, fpscr + +check: + # Read it back. + sts fpscr, r3 + cmp/eq r2, r3 + bf wrong + +inc: + # Test for proper post-increment. + add #4, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/ldsl-fpul.cgs b/sim/testsuite/sim/sh64/compact/ldsl-fpul.cgs new file mode 100644 index 00000000000..428a5b71816 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/ldsl-fpul.cgs @@ -0,0 +1,27 @@ +# sh testcase for lds.l @${rn}+, fpul -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global ldsl_fpul +ldsl_fpul: + mov #40, r0 + shll8 r0 + # remember the address. + mov r0, r1 + lds.l @r0+, fpul + + # ensure post increment occurred. + add #4, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/ldsl-mach.cgs b/sim/testsuite/sim/sh64/compact/ldsl-mach.cgs new file mode 100644 index 00000000000..f5ffdec8dce --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/ldsl-mach.cgs @@ -0,0 +1,26 @@ +# sh testcase for lds.l @${rn}+, mach -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global ldsl_mach +ldsl_mach: + mov #40, r0 + shll8 r0 + # save address for later examination. + mov r0, r1 + + lds.l @r0+, mach + + add #4, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/ldsl-macl.cgs b/sim/testsuite/sim/sh64/compact/ldsl-macl.cgs new file mode 100644 index 00000000000..4e21bf1942f --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/ldsl-macl.cgs @@ -0,0 +1,26 @@ +# sh testcase for lds.l @${rn}+, macl -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global ldsl_macl +ldsl_macl: + mov #40, r0 + shll8 r0 + # save address for later examination. + mov r0, r1 + + lds.l @r0+, macl + + add #4, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/ldsl-pr.cgs b/sim/testsuite/sim/sh64/compact/ldsl-pr.cgs new file mode 100644 index 00000000000..eb8ee531bd3 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/ldsl-pr.cgs @@ -0,0 +1,28 @@ +# sh testcase for lds.l @${rn}+, pr -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global ldsl_pr +ldsl_pr: + mov #40, r0 + shll8 r0 + # Preserve address. + mov r0, r1 + lds.l @r0+, pr + + # Add 4 to saved address (r1). + # Then compare with r0. + add #4, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/macl.cgs b/sim/testsuite/sim/sh64/compact/macl.cgs new file mode 100644 index 00000000000..ef2dfa6e929 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/macl.cgs @@ -0,0 +1,76 @@ +# sh testcase for mac.l @${rm}+, @${rn}+ +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + # force S-bit clear + clrs + + # Store some magic numbers in memory. + mov #40, r1 + shll8 r1 + mov #85, r0 + mov.l r0, @r1 + # Keep for later. + mov r1, r10 +store2: + mov #40, r1 + shll8 r1 + add #12, r1 + mov #17, r0 + mov.l r0, @r1 + # Keep for later. + mov r1, r11 + +init: + # Set up addresses. + mov #40, r1 + shll8 r1 + mov #40, r2 + shll8 r2 + add #12, r2 + + # Prime {MACL, MACH} to #1. + mov #1, r3 + dmulu.l r3, r3 + +test: + mac.l @r1+, @r2+ + +check: + # Check result. + sts mach, r5 + assert r5, #0 + + mov #5, r0 + shll8 r0 + or #166, r0 + sts macl, r6 + cmp/eq r6, r0 + bf wrong + + # Ensure post-increment occurred. + add #4, r10 + cmp/eq r10, r1 + bf wrong + + add #4, r11 + cmp/eq r11, r2 + bf wrong + +doubleinc: + mov #40, r0 + shll8 r0 + mov r0, r1 + mac.l @r0+, @r0+ + add #16, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/macw.cgs b/sim/testsuite/sim/sh64/compact/macw.cgs new file mode 100644 index 00000000000..f5935f7054d --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/macw.cgs @@ -0,0 +1,70 @@ +# sh testcase for mac.w @${rm}+, @${rn}+ +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + # Store some magic numbers in memory. + mov #40, r1 + shll8 r1 + mov #85, r0 + mov.l r0, @r1 + # Keep for later. + mov r1, r10 +store2: + mov #40, r1 + shll8 r1 + add #12, r1 + mov #17, r0 + mov.l r0, @r1 + # Keep for later. + mov r1, r11 + +init: + # Set up addresses. + mov #40, r1 + shll8 r1 + mov #40, r2 + shll8 r2 + add #12, r2 + + # Prime {MACL, MACH} to #1. + mov #1, r3 + dmulu.l r3, r3 + +test: + mac.w @r1+, @r2+ + +check: + # Check result. + sts mach, r5 + assert r5, #0 + + sts macl, r6 + assert r6, #1 + + # Ensure post-increment occurred. + add #2, r10 + cmp/eq r10, r1 + bf wrong + + add #2, r11 + cmp/eq r11, r2 + bf wrong + +doubleinc: + mov #40, r0 + shll8 r0 + mov r0, r1 + mac.w @r0+, @r0+ + add #8, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/mov.cgs b/sim/testsuite/sim/sh64/compact/mov.cgs new file mode 100644 index 00000000000..9442388384e --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/mov.cgs @@ -0,0 +1,40 @@ +# sh testcase for mov $rm64, $rn64 +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global mov +mov: + mov #1, r0 + rotr r0 + mov #0, r15 + mov #10, r0 + + mov r0, r1 + mov r1, r2 + mov r2, r3 + mov r3, r4 + mov r4, r5 + mov r5, r6 + mov r6, r7 + mov r7, r8 + mov r8, r9 + mov r9, r10 + mov r10, r11 + mov r11, r12 + mov r12, r13 + mov r13, r14 + mov r14, r15 + + cmp/eq r0, r15 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/mova.cgs b/sim/testsuite/sim/sh64/compact/mova.cgs new file mode 100644 index 00000000000..f555d66e093 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/mova.cgs @@ -0,0 +1,29 @@ +# sh testcase for mova @($imm8x4, pc), r0 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global mova +mova: + mova @(40, pc), r0 + mov #16, r1 + shll8 r1 + add #40, r1 + cmp/eq r0, r1 + bf wrong + mova @(12, pc), r0 + mov #16, r1 + shll8 r1 + add #24, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movb1.cgs b/sim/testsuite/sim/sh64/compact/movb1.cgs new file mode 100644 index 00000000000..8278e1bbeaa --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movb1.cgs @@ -0,0 +1,27 @@ +# sh testcase for mov.b $rm, @$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #55, r1 + mov #40, r2 + shll8 r2 + mov.b r1, @r2 + + # Load it back into r3. + mov #40, r2 + shll8 r2 + mov.b @r2, r3 + + # Make sure r1 and r3 match. + cmp/eq r1, r3 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movb10.cgs b/sim/testsuite/sim/sh64/compact/movb10.cgs new file mode 100644 index 00000000000..0ddb736f868 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movb10.cgs @@ -0,0 +1,25 @@ +# sh testcase for mov.b @($imm4, $rm), r0 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #30, r1 + shll8 r1 + # Store something there first. + mov #0, r0 + or #170, r0 + mov r0, r7 + mov.b r0, @(3, r1) + # Load it back. + mov.b @(3, r1), r0 + and #255, r0 + cmp/eq r0, r7 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movb2.cgs b/sim/testsuite/sim/sh64/compact/movb2.cgs new file mode 100644 index 00000000000..692c34fb648 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movb2.cgs @@ -0,0 +1,34 @@ +# sh testcase for mov.b $rm, @-$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #40, r1 + shll8 r1 + mov #55, r2 + + # Save ADDR, DATA. + mov r1, r7 + mov r2, r8 + + # Do the move. + mov.b r2, @-r1 + + # Load the value back into r3. + mov.b @r1, r3 + cmp/eq r2, r3 + bf wrong + + # Ensure that r1 has been decremented. + mov #1, r0 + sub r0, r7 + cmp/eq r7, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movb3.cgs b/sim/testsuite/sim/sh64/compact/movb3.cgs new file mode 100644 index 00000000000..6143562b8c1 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movb3.cgs @@ -0,0 +1,30 @@ +# sh testcase for mov.b $rm, @(r0,$rn) -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #40, r2 + shll8 r2 + mov #3, r1 + mov #0, r0 + or #170, r0 + mov r0, r3 + mov r2, r0 + mov.b r3, @(r0, r1) + + # Load the value back into a different register. + mov.b @(r0, r1), r4 + # Check the lowest order byte matches the stored value. + mov r4, r0 + and #255, r0 + cmp/eq r0, r3 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movb4.cgs b/sim/testsuite/sim/sh64/compact/movb4.cgs new file mode 100644 index 00000000000..d30a7a8641f --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movb4.cgs @@ -0,0 +1,28 @@ +# sh testcase for mov.b r0, @($imm8, gbr) -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #0, r0 + or #170, r0 + mov r0, r3 + mov #30, r2 + ldc r2, gbr + mov.b r0, @(40, gbr) + + # Load the value back into a different register. + mov.b @(40, gbr), r0 + # Check the lowest order byte matches the stored value. + and #255, r0 + cmp/eq r0, r3 + bf wrong + +okay: + pass + +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/movb5.cgs b/sim/testsuite/sim/sh64/compact/movb5.cgs new file mode 100644 index 00000000000..4f6795a8860 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movb5.cgs @@ -0,0 +1,25 @@ +# sh testcase for mov.b r0, @($imm4, rm) -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #0, r0 + or #170, r0 + mov r0, r3 + mov #30, r2 + mov.b r0, @(3, r2) + + # Load the value back into a different register. + mov.b @(3, r2), r0 + and #255, r0 + cmp/eq r3, r0 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/movb6.cgs b/sim/testsuite/sim/sh64/compact/movb6.cgs new file mode 100644 index 00000000000..9ddebde5ce4 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movb6.cgs @@ -0,0 +1,26 @@ +# sh testcase for mov.b @$rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #30, r2 + shll8 r2 + # Store something first. + mov #0, r0 + or #170, r0 + mov r0, r7 + mov.b r7, @r2 + # Load it back. + mov.b @r2, r1 + mov r1, r0 + and #255, r0 + cmp/eq r7, r0 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movb7.cgs b/sim/testsuite/sim/sh64/compact/movb7.cgs new file mode 100644 index 00000000000..f55a223436b --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movb7.cgs @@ -0,0 +1,35 @@ +# sh testcase for mov.b @${rm}+, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #30, r1 + shll8 r1 + # Store addr. + mov r1, r8 + + # Store something there first. + mov #0, r0 + or #170, r0 + mov r0, r7 + mov.b r7, @r1 + # Load it back. + mov.b @r1+, r2 + mov r2, r0 + and #255, r0 + cmp/eq r7, r0 + bf wrong + + # Test address for post-incrementing. + add #1, r8 + cmp/eq r8, r1 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/movb8.cgs b/sim/testsuite/sim/sh64/compact/movb8.cgs new file mode 100644 index 00000000000..883e4b357ed --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movb8.cgs @@ -0,0 +1,27 @@ +# sh testcase for mov.b @(r0, $rm), $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #30, r0 + shll8 r0 + mov #14, r1 + # Store something there first. + mov #0, r0 + or #170, r0 + mov r0, r7 + mov.b r7, @(r0, r1) + # Load it back. + mov.b @(r0, r1), r2 + mov r2, r0 + and #255, r0 + cmp/eq r0, r7 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movb9.cgs b/sim/testsuite/sim/sh64/compact/movb9.cgs new file mode 100644 index 00000000000..3ad1b46f2c0 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movb9.cgs @@ -0,0 +1,27 @@ +# sh testcase for mov.b @($imm8, gbr), r0 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #30, r0 + shll8 r0 + ldc r0, gbr + # Store something there first. + mov #0, r0 + or #170, r0 + mov r0, r7 + mov.b r0, @(3, gbr) + # Load it back. + mov.b @(3, gbr), r0 + and #255, r0 + cmp/eq r7, r0 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movcal.cgs b/sim/testsuite/sim/sh64/compact/movcal.cgs new file mode 100644 index 00000000000..7aac57e7f43 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movcal.cgs @@ -0,0 +1,28 @@ +# sh testcase for movca.l r0, @$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global movcal +movcal: + mov #1, r0 + rotr r0 + add #128, r0 + mov #40, r1 + shll8 r1 + movca.l r0, @r1 + + # Load the word back in. + mov.l @r1, r3 + cmp/eq r0, r3 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/movi.cgs b/sim/testsuite/sim/sh64/compact/movi.cgs new file mode 100644 index 00000000000..bc72c1b8e63 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movi.cgs @@ -0,0 +1,39 @@ +# sh testcase for mov #$imm8, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global movi +movi: + mov #0, r0 + cmp/eq #0, r0 + bf wrong + + mov #1, r0 + cmp/eq #1, r0 + bf wrong + + mov #255, r0 + cmp/eq #255, r0 + bf wrong + + mov #1, r15 + mov #1, r0 + cmp/eq r0, r15 + bf wrong + + mov #255, r15 + mov r15, r0 + cmp/eq r0, r15 + bf wrong + +okay: + pass + +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/movl1.cgs b/sim/testsuite/sim/sh64/compact/movl1.cgs new file mode 100644 index 00000000000..7d85c380f3e --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movl1.cgs @@ -0,0 +1,31 @@ +# sh testcase for mov.l $rm, @$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #30, r1 + shll8 r1 +init: + # Build up a distinctive bit pattern. + mov #1, r2 + shll8 r2 + add #12, r2 + shll8 r2 + add #85, r2 + shll8 r2 + add #170, r2 + + mov.l r2, @r1 + + # Load it back. + mov.l @r1, r3 + cmp/eq r2, r3 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movl10.cgs b/sim/testsuite/sim/sh64/compact/movl10.cgs new file mode 100644 index 00000000000..5e9cf2d2fbd --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movl10.cgs @@ -0,0 +1,34 @@ +# sh testcase for mov.l @($imm8x4, pc), $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +init: + # Build up a distinctive bit pattern. + mov #1, r2 + shll8 r2 + add #12, r2 + shll8 r2 + add #85, r2 + shll8 r2 + add #170, r2 + + # Store to memory. + mov #16, r1 + shll8 r1 + add #32, r1 + mov.l r2, @r1 +check: + # Read it back. + mov.l @(12, pc), r0 + cmp/eq r2, r0 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movl11.cgs b/sim/testsuite/sim/sh64/compact/movl11.cgs new file mode 100644 index 00000000000..32c763d8a2e --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movl11.cgs @@ -0,0 +1,32 @@ +# sh testcase for mov.l @($imm4x4, $rm), $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #30, r0 + shll8 r0 + # Build up a distinctive bit pattern. + mov #1, r2 + shll8 r2 + add #12, r2 + shll8 r2 + add #85, r2 + shll8 r2 + add #170, r2 + # Store something first. + mov.l r2, @(12, r0) + +check: + # Read it back. + mov.l @(12, r0), r1 + cmp/eq r2, r1 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/movl2.cgs b/sim/testsuite/sim/sh64/compact/movl2.cgs new file mode 100644 index 00000000000..bb550612cce --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movl2.cgs @@ -0,0 +1,43 @@ +# sh testcase for mov.l $rm, @-$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + mov #30, r1 + shll8 r1 + # Save address. + mov r1, r7 + +init: + # Build up a distinctive bit pattern. + mov #1, r2 + shll8 r2 + add #12, r2 + shll8 r2 + add #85, r2 + shll8 r2 + add #170, r2 + mov.l r2, @-r1 + +check: + # Compare the value loaded into another reg. + mov.l @r1, r3 + cmp/eq r2, r3 + bf wrong + +dec: + # Ensure address is decremented. + mov #4, r6 + sub r6, r7 + cmp/eq r1, r7 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movl3.cgs b/sim/testsuite/sim/sh64/compact/movl3.cgs new file mode 100644 index 00000000000..6205de7558d --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movl3.cgs @@ -0,0 +1,36 @@ +# sh testcase for mov.l $rm, @(r0, $rn) +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +setaddr: + mov #0, r0 + mov #30, r1 + shll8 r1 + +init: + # Build up a distinctive bit pattern. + mov #1, r2 + shll8 r2 + add #12, r2 + shll8 r2 + add #85, r2 + shll8 r2 + add #170, r2 + + mov.l r2, @(r0, r1) + +check: + # Load it back. + mov.l @(r0, r1), r3 + cmp/eq r2, r3 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movl4.cgs b/sim/testsuite/sim/sh64/compact/movl4.cgs new file mode 100644 index 00000000000..44440946365 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movl4.cgs @@ -0,0 +1,38 @@ +# sh testcase for mov.l r0, @($imm8x4, gbr) -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +setaddr: + mov #30, r1 + shll8 r1 + ldc r1, gbr + +init: + # Build up a distinctive bit pattern. + mov #1, r0 + shll8 r0 + add #12, r0 + shll8 r0 + add #85, r0 + shll8 r0 + add #170, r0 + # Preserve. + mov r0, r7 + + mov.l r0, @(4, gbr) +check: + # Load it back. + mov.l @(4, gbr), r0 + cmp/eq r0, r7 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/movl5.cgs b/sim/testsuite/sim/sh64/compact/movl5.cgs new file mode 100644 index 00000000000..897ebef2367 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movl5.cgs @@ -0,0 +1,37 @@ +# sh testcase for mov.l $rm, @($imm4x4, $rn) -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +setaddr: + mov #30, r1 + shll8 r1 + +init: + # Build up a distinctive bit pattern. + mov #1, r0 + shll8 r0 + add #12, r0 + shll8 r0 + add #85, r0 + shll8 r0 + add #170, r0 + # Preserve. + mov r0, r7 + + mov.l r0, @(4, r1) +check: + # Load it back. + mov.l @(4, r1), r0 + cmp/eq r7, r0 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movl6.cgs b/sim/testsuite/sim/sh64/compact/movl6.cgs new file mode 100644 index 00000000000..42f63b2a9ac --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movl6.cgs @@ -0,0 +1,25 @@ +# sh testcase for mov.l @$rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + mov #30, r0 + shll8 r0 + # Store something there first. + mov #170, r1 + mov.l r1, @r0 +check: + # Load it back. + mov.l @r0, r3 + cmp/eq r1, r3 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/movl7.cgs b/sim/testsuite/sim/sh64/compact/movl7.cgs new file mode 100644 index 00000000000..b6c12fc5515 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movl7.cgs @@ -0,0 +1,37 @@ +# sh testcase for mov.l @$rm+, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + mov #30, r0 + shll8 r0 + # Preserve address. + mov r0, r7 + # Store something first. + mov #170, r3 + mov.l r3, @r0 + + mov.l @r0+, r1 +check: + cmp/eq r1, r3 + bf wrong + + # Ensure address is post-incremented. + add #4, r7 + cmp/eq r7, r0 + bf wrong + +equal: + # Test rm = rn. + mov #30, r0 + shll8 r0 + mov.l @r0+, r0 + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movl8.cgs b/sim/testsuite/sim/sh64/compact/movl8.cgs new file mode 100644 index 00000000000..a6cd932d0a2 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movl8.cgs @@ -0,0 +1,24 @@ +# sh testcase for mov.l @(r0, $rm), $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #0, r0 + mov #30, r1 + shll8 r1 + # Store something there first. + mov #170, r3 + mov.l r3, @(r0, r1) +check: + # Load it back. + mov.l @(r0, r1), r2 + cmp/eq r2, r3 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movl9.cgs b/sim/testsuite/sim/sh64/compact/movl9.cgs new file mode 100644 index 00000000000..4fa07b069d8 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movl9.cgs @@ -0,0 +1,24 @@ +# sh testcase for mov.l @($imm8x4, gbr), r0 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #30, r1 + shll8 r1 + ldc r1, gbr + # Store something there first. + mov #170, r0 + mov r0, r7 + mov.l r0, @(12, gbr) +check: + # Load it back. + mov.l @(12, gbr), r0 + cmp/eq r0, r7 + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movt.cgs b/sim/testsuite/sim/sh64/compact/movt.cgs new file mode 100644 index 00000000000..45539810beb --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movt.cgs @@ -0,0 +1,28 @@ +# sh testcase for movt $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global movt +init: + sett + movt r1 + assert r1, #1 +clear: + clrt + movt r1 + assert r1, #0 +set: + sett + movt r1 + assert r1, #1 + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/movw1.cgs b/sim/testsuite/sim/sh64/compact/movw1.cgs new file mode 100644 index 00000000000..5d55a581ffd --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movw1.cgs @@ -0,0 +1,29 @@ +# sh testcase for mov.w $rm, @$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + mov #30, r1 + shll8 r1 +init: + # Build up a distinctive bit pattern. + mov #1, r2 + shll8 r2 + add #12, r2 + mov.w r2, @r1 +check: + # Read it back. + mov.w @r1, r3 + shll16 r2 + shll16 r3 + cmp/eq r2, r3 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movw10.cgs b/sim/testsuite/sim/sh64/compact/movw10.cgs new file mode 100644 index 00000000000..5bab9117e9e --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movw10.cgs @@ -0,0 +1,32 @@ +# sh testcase for mov.w @($imm8x2, pc), $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + # Build up a distinctive bit pattern. + mov #1, r2 + shll8 r2 + add #12, r2 + + # Store to memory. + mov #16, r1 + shll8 r1 + add #32, r1 + mov.w r2, @r1 + +check: + # Read it back. + mov.w @(18, pc), r0 + shll16 r0 + shll16 r2 + cmp/eq r0, r2 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movw11.cgs b/sim/testsuite/sim/sh64/compact/movw11.cgs new file mode 100644 index 00000000000..df739fa783d --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movw11.cgs @@ -0,0 +1,35 @@ +# sh testcase for mov.w @($imm4x2, $rm), r0 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #30, r1 + shll8 r1 + + # Build up a distinctive bit pattern. + mov #1, r0 + shll8 r0 + add #12, r0 + + # Preserve r0. + mov r0, r3 + + # Store something first. + mov.w r0, @(12, r1) + +check: + # Read it back. + mov.w @(12, r1), r0 + shll16 r0 + shll16 r3 + cmp/eq r0, r3 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/movw2.cgs b/sim/testsuite/sim/sh64/compact/movw2.cgs new file mode 100644 index 00000000000..27c29dc0292 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movw2.cgs @@ -0,0 +1,36 @@ +# sh testcase for mov.w $rm, @-$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + mov #30, r1 + shll8 r1 + # Preserve. + mov r1, r7 +init: + # Build up a distinctive bit pattern. + mov #1, r2 + shll8 r2 + add #12, r2 +store: + mov.w r2, @-r1 +check: + # Read it back. + mov.w @r1, r3 + shll16 r2 + shll16 r3 + cmp/eq r2, r3 + bf wrong +dec: + add #2, r1 + cmp/eq r7, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movw3.cgs b/sim/testsuite/sim/sh64/compact/movw3.cgs new file mode 100644 index 00000000000..d7b39c81506 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movw3.cgs @@ -0,0 +1,31 @@ +# sh testcase for mov.w $rm, @(r0, $rn) -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + mov #0, r0 + mov #30, r1 + shll8 r1 +init: + # Build up a distinctive bit pattern. + mov #1, r2 + shll8 r2 + add #12, r2 + mov.w r2, @(r0, r1) +check: + # Read it back. + mov.w @(r0, r1), r3 + shll16 r2 + shll16 r3 + cmp/eq r2, r3 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/movw4.cgs b/sim/testsuite/sim/sh64/compact/movw4.cgs new file mode 100644 index 00000000000..4853b5019bc --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movw4.cgs @@ -0,0 +1,31 @@ +# sh testcase for mov.w r0, @($imm8x2, gbr) -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + mov #30, r0 + shll8 r0 + ldc r0, gbr + +init: + # Build up a distinctive bit pattern. + mov #1, r0 + shll8 r0 + add #12, r0 + # Preserve r0. + mov r0, r7 + mov.w r0, @(12, gbr) +check: + mov.w @(12, gbr), r0 + cmp/eq r0, r7 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/movw5.cgs b/sim/testsuite/sim/sh64/compact/movw5.cgs new file mode 100644 index 00000000000..9b4f84f6516 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movw5.cgs @@ -0,0 +1,32 @@ +# sh testcase for mov.w r0, @($imm4x2, $rn) -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #30, r1 + shll8 r1 + +init: + # Build up a distinctive bit pattern. + mov #1, r0 + shll8 r0 + add #12, r0 + # Preserve. + mov r0, r7 +move: + mov.w r0, @(12, r1) +check: + mov.w @(12, r1), r0 + shll16 r0 + shll16 r7 + cmp/eq r0, r7 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/movw6.cgs b/sim/testsuite/sim/sh64/compact/movw6.cgs new file mode 100644 index 00000000000..758497c13e7 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movw6.cgs @@ -0,0 +1,30 @@ +# sh testcase for mov.w @$rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + mov #30, r0 + shll8 r0 + + # Store something first. + # Build up a distinctive bit pattern. + mov #1, r2 + shll8 r2 + add #12, r2 + mov.w r2, @r0 + +check: + # Read it back. + mov.w @r0, r1 + cmp/eq r1, r2 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/movw7.cgs b/sim/testsuite/sim/sh64/compact/movw7.cgs new file mode 100644 index 00000000000..45f5c098e4e --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movw7.cgs @@ -0,0 +1,36 @@ +# sh testcase for mov.w @${rm}+, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #30, r0 + shll8 r0 + # Preserve address. + mov r0, r7 + + # Store something first. + # Build up a distinctive bit pattern. + mov #1, r2 + shll8 r2 + add #12, r2 + mov.w r2, @r0 +check: + # Read it back. + mov.w @r0+, r3 + cmp/eq r2, r3 + bf wrong + +inc: + # Ensure address is post-incremented. + add #2, r7 + cmp/eq r0, r7 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/movw8.cgs b/sim/testsuite/sim/sh64/compact/movw8.cgs new file mode 100644 index 00000000000..0a7ce3f346c --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movw8.cgs @@ -0,0 +1,31 @@ +# sh testcase for mov.w @(r0, $rm), $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #30, r0 + shll8 r0 + mov #10, r1 + + # Store something first. + # Build up a distinctive bit pattern. + mov #1, r2 + shll8 r2 + add #12, r2 + + mov.w r2, @(r0, r1) +check: + # Read it back. + mov.w @(r0, r1), r3 + shll16 r2 + shll16 r3 + cmp/eq r2, r3 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/movw9.cgs b/sim/testsuite/sim/sh64/compact/movw9.cgs new file mode 100644 index 00000000000..1872f06afb6 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/movw9.cgs @@ -0,0 +1,33 @@ +# sh testcase for mov.w @($imm8x2, gbr), r0 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + mov #30, r0 + shll8 r0 + ldc r0, gbr + + # Store something first. + # Build up a distinctive bit pattern. + mov #1, r0 + shll8 r0 + add #12, r0 + # Preserve r0. + mov r0, r7 + mov.w r0, @(12, gbr) + +check: + # Load it back. + mov.w @(12, gbr), r0 + shll16 r0 + shll16 r7 + cmp/eq r0, r7 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/mull.cgs b/sim/testsuite/sim/sh64/compact/mull.cgs new file mode 100644 index 00000000000..921141aafd6 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/mull.cgs @@ -0,0 +1,64 @@ +# sh testcase for mul.l $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global mull +mull: + mov #3, r0 + mov #5, r1 + mul.l r0, r1 + + # Check the result. + sts macl, r3 + mov #15, r4 + cmp/eq r3, r4 + bf wrong + +lxs: + # Large * small. + mov #255, r0 + mov #0, r1 + mul.l r0, r1 + + # Check the result. + sts macl, r3 + mov #0, r4 + cmp/eq r3, r4 + bf wrong + +sxl: + # Small * large. + mov #0, r0 + mov #255, r1 + mul.l r0, r1 + + # Check the result. + sts macl, r3 + mov #0, r4 + cmp/eq r3, r4 + bf wrong + +lxl: + # Large * large. + mov #1, r0 + neg r0, r0 + mov #2, r1 + mul.l r0, r1 + + # Check the result. + sts macl, r3 + mov #2, r4 + neg r4, r4 + cmp/eq r3, r4 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/mulsw.cgs b/sim/testsuite/sim/sh64/compact/mulsw.cgs new file mode 100644 index 00000000000..05c8a3d384c --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/mulsw.cgs @@ -0,0 +1,91 @@ +# sh testcase for muls.w $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + sts mach, r7 + + .global mulsw +zero: + mov #0, r0 + mov #1, r1 + muls.w r0, r1 + + # Check the result. + sts macl, r3 + mov #0, r4 + cmp/eq r3, r4 + bf wrong + +sxs: + # Small * small. + mov #1, r0 + mov #2, r1 + muls.w r0, r1 + + # Check the result. + sts macl, r3 + mov #2, r4 + cmp/eq r3, r4 + bf wrong + +sxl: + # Small * large. + mov #1, r0 + mov #255, r1 + shll8 r1 + muls.w r0, r1 + + # Check the result. + sts macl, r3 + mov #0, r4 + not r4, r4 + shll8 r4 + cmp/eq r3, r4 + bf wrong + +lxs: + # Large * small. + mov #255, r0 + shll8 r0 + mov #1, r1 + muls.w r0, r1 + + # Check the result. + sts macl, r3 + mov #0, r4 + not r4, r4 + shll8 r4 + cmp/eq r3, r4 + bf wrong + +lxl: + # Large * large. + mov #255, r0 + shll8 r0 + mov #255, r1 + shll8 r1 + muls.w r0, r1 + + # Check the result. + sts macl, r3 + mov #1, r4 + shll16 r4 + cmp/eq r3, r4 + bf wrong + +invariant: + # Ensure MACH is invariant. + sts mach, r8 + cmp/eq r7, r8 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/muluw.cgs b/sim/testsuite/sim/sh64/compact/muluw.cgs new file mode 100644 index 00000000000..fa0a3343332 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/muluw.cgs @@ -0,0 +1,96 @@ +# sh testcase for mulu.w $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + sts mach, r7 + + .global mulsw +zero: + mov #0, r0 + mov #1, r1 + mulu.w r0, r1 + + # Check the result. + sts macl, r1 + mov #0, r0 + cmp/eq r0, r1 + bf wrong + +sxs: + # Small * small. + mov #1, r0 + mov #2, r1 + mulu.w r0, r1 + + # Check the result. + sts macl, r1 + mov #2, r0 + cmp/eq r0, r1 + bf wrong + +sxl: + # Small * large. + mov #1, r1 + mov #0, r0 + or #255, r0 + shll8 r0 + mulu.w r1, r0 + + # Check the result. + sts macl, r1 + mov #0, r0 + or #255, r0 + shll8 r0 + cmp/eq r0, r1 + bf wrong + +lxs: + # Large * small. + mov #0, r0 + or #255, r0 + shll8 r0 + mov #1, r1 + mulu.w r0, r1 + + # Check the result. + sts macl, r1 + mov #0, r0 + or #255, r0 + shll8 r0 + cmp/eq r0, r1 + bf wrong + +lxl: + # Large * large. + mov #0, r0 + or #255, r0 + shll8 r0 + mov r0, r1 + mulu.w r0, r1 + + # Check the result. + sts macl, r1 + mov #0, r0 + or #254, r0 + shll8 r0 + or #1, r0 + shll16 r0 + cmp/eq r0, r1 + bf wrong + +invariant: + # Ensure MACH is invariant. + sts mach, r8 + cmp/eq r7, r8 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/neg.cgs b/sim/testsuite/sim/sh64/compact/neg.cgs new file mode 100644 index 00000000000..b6f98d74060 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/neg.cgs @@ -0,0 +1,55 @@ +# sh testcase for neg $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + .macro signbit sign + shlr16 r1 + shlr8 r1 + shlr r1 + shlr r1 + shlr r1 + shlr r1 + shlr r1 + shlr r1 + shlr r1 + assert r1, \sign + .endm + start + + .global neg +neg: + mov #0, r0 + neg r0, r1 + signbit #0 + + mov #42, r0 + neg r0, r1 + signbit #1 + + mov #0, r0 + or #25, r0 + neg r0, r1 + signbit #1 + + # neg(0) is 0. + mov #0, r0 + neg r0, r1 + signbit #0 + + # neg(neg(x)) = x. + mov #42, r0 + neg r0, r1 + signbit #1 + mov #42, r0 + neg r0, r2 + neg r2, r1 + signbit #0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/negc.cgs b/sim/testsuite/sim/sh64/compact/negc.cgs new file mode 100644 index 00000000000..1f5547d9bab --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/negc.cgs @@ -0,0 +1,66 @@ +# sh testcase for negc $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + .macro signbit sign + mov r1, r2 + shlr16 r2 + shlr8 r2 + shlr r2 + shlr r2 + shlr r2 + shlr r2 + shlr r2 + shlr r2 + shlr r2 + assert r2, \sign + .endm + start + + .global negc +negc: + clrt + mov #1, r0 + negc r0, r1 + signbit #1 + +negc2: + sett + mov #1, r0 + negc r0, r1 + signbit #1 + +negc3: + clrt + mov #0, r0 + negc r0, r1 + signbit #0 + +negc4: + sett + mov #0, r0 + negc r0, r1 + signbit #1 + +negc5: + clrt + mov #0, r0 + or #255, r0 + negc r0, r1 + signbit #1 + +negc6: + sett + mov #0, r0 + or #255, r0 + negc r0, r1 + signbit #1 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/nop.cgs b/sim/testsuite/sim/sh64/compact/nop.cgs new file mode 100644 index 00000000000..8ce910c5abd --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/nop.cgs @@ -0,0 +1,13 @@ +# sh testcase for nop +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global nop +nop: + nop + pass diff --git a/sim/testsuite/sim/sh64/compact/not.cgs b/sim/testsuite/sim/sh64/compact/not.cgs new file mode 100644 index 00000000000..380808ddb57 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/not.cgs @@ -0,0 +1,47 @@ +# sh testcase for not $rm64, $rn64 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global not +not: + mov #0, r0 + or #192, r0 + not r0, r1 + + mov #0, r0 + or #255, r0 + shll8 r0 + or #255, r0 + shll8 r0 + or #255, r0 + shll8 r0 + or #63, r0 + + cmp/eq r0, r1 + bf wrong + +ones: + mov #0, r1 + not r1, r2 + + mov #0, r0 + or #255, r0 + shll8 r0 + or #255, r0 + shll8 r0 + or #255, r0 + shll8 r0 + or #255, r0 + cmp/eq r0, r2 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/ocbi.cgs b/sim/testsuite/sim/sh64/compact/ocbi.cgs new file mode 100644 index 00000000000..12fb2a116c4 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/ocbi.cgs @@ -0,0 +1,14 @@ +# sh testcase for ocbi @$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + .global ocbi +ocbi: + ocbi @r0 + ocbi @r1 + ocbi @r15 + pass diff --git a/sim/testsuite/sim/sh64/compact/ocbp.cgs b/sim/testsuite/sim/sh64/compact/ocbp.cgs new file mode 100644 index 00000000000..153aff2eade --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/ocbp.cgs @@ -0,0 +1,15 @@ +# sh testcase for ocbp @$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global ocbp +ocbp: + ocbp @r0 + ocbp @r1 + ocbp @r15 + pass diff --git a/sim/testsuite/sim/sh64/compact/ocbwb.cgs b/sim/testsuite/sim/sh64/compact/ocbwb.cgs new file mode 100644 index 00000000000..6b0a741cbca --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/ocbwb.cgs @@ -0,0 +1,15 @@ +# sh testcase for ocbwb @$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global ocbwb +ocbwb: + ocbwb @r0 + ocbwb @r1 + ocbwb @r15 + pass diff --git a/sim/testsuite/sim/sh64/compact/or.cgs b/sim/testsuite/sim/sh64/compact/or.cgs new file mode 100644 index 00000000000..a02eee39aaf --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/or.cgs @@ -0,0 +1,43 @@ +# sh testcase for or $rm64, $rn64 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global or +or: + mov #1, r0 + rotr r0 + mov #1, r1 + or r0, r1 + + mov #1, r7 + rotr r7 + add #1, r7 + cmp/eq r7, r1 + bf wrong + + .global or2 +or2: + mov #85, r0 + shll16 r0 + shll8 r0 + mov #85, r1 + shll8 r1 + or r0, r1 + + mov #85, r7 + shll16 r7 + add #85 ,r7 + shll8 r7 + cmp/eq r1, r7 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/orb.cgs b/sim/testsuite/sim/sh64/compact/orb.cgs new file mode 100644 index 00000000000..7e962f6fe69 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/orb.cgs @@ -0,0 +1,24 @@ +# sh testcase for or.b #$imm8, @(r0, gbr) -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global orb +init: + # Init GBR and R0. + mov #30, r0 + ldc r0, gbr + mov #40, r0 + +orb: + or.b #0, @(r0, gbr) + or.b #170, @(r0, gbr) + or.b #0, @(r0, gbr) + or.b #255, @(r0, gbr) + +okay: + pass diff --git a/sim/testsuite/sim/sh64/compact/ori.cgs b/sim/testsuite/sim/sh64/compact/ori.cgs new file mode 100644 index 00000000000..63a5fb58740 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/ori.cgs @@ -0,0 +1,40 @@ +# sh testcase for or #$imm8, r0 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global ori +ori: + mov #1, r0 + rotr r0 + or #1, r0 + + mov #1, r7 + rotr r7 + add #1, r7 + cmp/eq r0, r7 + bf wrong + + .global ori2 +ori2: + mov #85, r0 + shll16 r0 + shll8 r0 + or #85, r0 + + mov #85, r7 + shll16 r7 + shll8 r7 + add #85, r7 + cmp/eq r0, r7 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/pref.cgs b/sim/testsuite/sim/sh64/compact/pref.cgs new file mode 100644 index 00000000000..065e0932e6c --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/pref.cgs @@ -0,0 +1,15 @@ +# sh testcase for pref @$rn +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global pref +pref: + pref @r0 + pref @r1 + pref @r15 + pass diff --git a/sim/testsuite/sim/sh64/compact/rotcl.cgs b/sim/testsuite/sim/sh64/compact/rotcl.cgs new file mode 100644 index 00000000000..5e1a3b91137 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/rotcl.cgs @@ -0,0 +1,121 @@ +# sh testcase for rotcl $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global rotcl + +rotcl: + clrt + mov #1, r1 + rotcl r1 + assert r1, #2 + clrt + rotcl r1 + assert r1, #4 + clrt + rotcl r1 + assert r1, #8 + clrt + rotcl r1 + assert r1, #16 + clrt + rotcl r1 + assert r1, #32 + clrt + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + bf wrong + rotcl r1 + assert r1, #1 + + bra trotcl + nop + +wrong: + fail + +trotcl: + sett + mov #1, r1 + rotcl r1 + assert r1, #3 + clrt + rotcl r1 + assert r1, #6 + clrt + rotcl r1 + assert r1, #12 + clrt + rotcl r1 + assert r1, #24 + clrt + rotcl r1 + assert r1, #48 + clrt + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + rotcl r1 + bf wrong2 + assert r1, #1 + rotcl r1 + rotcl r1 + +okay: + pass +wrong2: + fail diff --git a/sim/testsuite/sim/sh64/compact/rotcr.cgs b/sim/testsuite/sim/sh64/compact/rotcr.cgs new file mode 100644 index 00000000000..b53300ec54f --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/rotcr.cgs @@ -0,0 +1,103 @@ +# sh testcase for rotcr $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global rotcr +rotcr: + clrt + mov #1, r1 + rotcr r1 + bf wrong + assert r1, #0 + sett + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + assert r1, #1 + rotcr r1 + bf wrong + +trotcr: + sett + mov #1, r1 + rotcr r1 + bf wrong + sett + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + rotcr r1 + bf wrong + assert r1, #1 + rotcr r1 + bf wrong + rotcr r1 + +okay: + pass +wrong: + fail + + diff --git a/sim/testsuite/sim/sh64/compact/rotl.cgs b/sim/testsuite/sim/sh64/compact/rotl.cgs new file mode 100644 index 00000000000..e292de7e437 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/rotl.cgs @@ -0,0 +1,62 @@ +# sh testcase for rotl $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global rotl +rotl: + mov #1, r1 + rotl r1 + assert r1, #2 + rotl r1 + assert r1, #4 + rotl r1 + assert r1, #8 + rotl r1 + assert r1, #16 + rotl r1 + assert r1, #32 + rotl r1 + assert r1, #64 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + rotl r1 + bf wrong + assert r1, #1 + rotl r1 + rotl r1 + rotl r1 + assert r1, #8 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/rotr.cgs b/sim/testsuite/sim/sh64/compact/rotr.cgs new file mode 100644 index 00000000000..7f80f993aea --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/rotr.cgs @@ -0,0 +1,55 @@ +# sh testcase for rotr $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global rotr +rotr: + mov #1, r1 + rotr r1 + bf wrong + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + rotr r1 + assert r1, #1 + rotr r1 + rotr r1 + rotr r1 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/rts.cgs b/sim/testsuite/sim/sh64/compact/rts.cgs new file mode 100644 index 00000000000..eeb8dce9332 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/rts.cgs @@ -0,0 +1,24 @@ +# sh testcase for rts -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global rts +rts: + bsr subroutine +slot: + nop +return: + pass + fail + +subroutine: + rts +rts_slot: + nop +bad: + fail diff --git a/sim/testsuite/sim/sh64/compact/sets.cgs b/sim/testsuite/sim/sh64/compact/sets.cgs new file mode 100644 index 00000000000..f031701d6ee --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/sets.cgs @@ -0,0 +1,13 @@ +# sh testcase for sets -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global sets +sets: + sets + pass diff --git a/sim/testsuite/sim/sh64/compact/sett.cgs b/sim/testsuite/sim/sh64/compact/sett.cgs new file mode 100644 index 00000000000..9ae8af536e7 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/sett.cgs @@ -0,0 +1,16 @@ +# sh testcase for sett -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global sett +sett: + sett + bf wrong + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/shad.cgs b/sim/testsuite/sim/sh64/compact/shad.cgs new file mode 100644 index 00000000000..340743d8f1f --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/shad.cgs @@ -0,0 +1,58 @@ +# sh testcase for shad $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global null +null: + mov #1, r0 + mov #0, r1 + shad r1, r0 + # no shift is performed. + assert r0, #1 + + .global gt0 +gt0: + mov #4, r0 + mov #3, r1 + shad r1, r0 + # shift left 3 bits. + assert r0, #32 + + .global lt0 +lt0: + mov #32, r0 + mov #3, r1 + neg r1, r1 + shad r1, r0 + # shift right 3 bits. + assert r0, #4 + + .global fillpos +fillpos: + mov #1, r0 + mov #1, r1 + rotr r1 + shad r1, r0 + # check result. + assert r0, #0 + + .global fillneg +fillneg: + mov #1, r0 + neg r0, r0 + mov #1, r1 + rotr r1 + shad r1, r0 + # check result. + not r0, r0 + assert r0, #0 + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/shal.cgs b/sim/testsuite/sim/sh64/compact/shal.cgs new file mode 100644 index 00000000000..dfea947e856 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/shal.cgs @@ -0,0 +1,57 @@ +# sh testcase for shal $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global shal +shal: + mov #1, r1 + shal r1 + assert r1, #2 + shal r1 + assert r1, #4 + shal r1 + assert r1, #8 + shal r1 + assert r1, #16 + shal r1 + assert r1, #32 + shal r1 + assert r1, #64 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + shal r1 + assert r1, #0 + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/shar.cgs b/sim/testsuite/sim/sh64/compact/shar.cgs new file mode 100644 index 00000000000..e3e92fca080 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/shar.cgs @@ -0,0 +1,40 @@ +# sh testcase for shar $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global shar +shar: + mov #0, r0 + or #192, r0 + shar r0 + bt wrong + shar r0 + bt wrong + shar r0 + bt wrong + shar r0 + bt wrong + shar r0 + bt wrong + shar r0 + bt wrong + shar r0 + bf wrong + shar r0 + bf wrong + shar r0 + bt wrong + shar r0 + bt wrong + assert r0, #0 + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/shld.cgs b/sim/testsuite/sim/sh64/compact/shld.cgs new file mode 100644 index 00000000000..32e4100259d --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/shld.cgs @@ -0,0 +1,48 @@ +# sh testcase for shld $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global null +null: + mov #1, r0 + mov #0, r1 + shld r1, r0 + # no shift is performed. + assert r0, #1 + + .global gt0 +gt0: + mov #4, r0 + mov #3, r1 + shld r1, r0 + # shift left 3 bits. + assert r0, #32 + + .global lt0 +lt0: + mov #32, r0 + mov #3, r1 + neg r1, r1 + shld r1, r0 + # shift right 3 bits. + assert r0, #4 + + .global fill +fill: + mov #1, r0 + rotr r0 + mov #1, r1 + rotr r1 + shld r1, r0 + assert r0, #0 + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/shll.cgs b/sim/testsuite/sim/sh64/compact/shll.cgs new file mode 100644 index 00000000000..882f2c2e1ef --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/shll.cgs @@ -0,0 +1,57 @@ +# sh testcase for shll $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global shll +shll: + mov #1, r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + shll r1 + assert r1, #0 +another: + mov #1, r1 + shll r1 + shll r1 + shll r1 + assert r1, #8 + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/shll16.cgs b/sim/testsuite/sim/sh64/compact/shll16.cgs new file mode 100644 index 00000000000..0637c3de706 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/shll16.cgs @@ -0,0 +1,44 @@ +# sh testcase for shll16 $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global shll16 +shll16: + mov #108, r1 + shll16 r1 + shll16 r1 + assert r1, #0 + +another: + mov #1, r1 + shll16 r1 + mov #1, r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + cmp/eq r1, r7 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/shll2.cgs b/sim/testsuite/sim/sh64/compact/shll2.cgs new file mode 100644 index 00000000000..6e28c664307 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/shll2.cgs @@ -0,0 +1,40 @@ +# sh testcase for shll2 $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global shll2 +shll2: + mov #1, r1 + shll2 r1 + shll2 r1 + shll2 r1 + shll2 r1 + shll2 r1 + shll2 r1 + shll2 r1 + shll2 r1 + shll2 r1 + shll2 r1 + shll2 r1 + shll2 r1 + shll2 r1 + shll2 r1 + shll2 r1 + shll2 r1 + assert r1, #0 + +another: + mov #1, r1 + shll2 r1 + assert r1, #4 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/shll8.cgs b/sim/testsuite/sim/sh64/compact/shll8.cgs new file mode 100644 index 00000000000..fe455ec753d --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/shll8.cgs @@ -0,0 +1,38 @@ +# sh testcase for shll8 $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global shll8 +shll8: + mov #1, r1 + shll8 r1 + shll8 r1 + shll8 r1 + shll8 r1 + assert r1, #0 + +another: + mov #1, r1 + shll8 r1 + mov #1, r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + shll r7 + cmp/eq r1, r7 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/shlr.cgs b/sim/testsuite/sim/sh64/compact/shlr.cgs new file mode 100644 index 00000000000..9d86461b959 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/shlr.cgs @@ -0,0 +1,33 @@ +# sh testcase for shlr $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global shlr +shlr: + mov #0, r0 + or #192, r0 + shlr r0 + shlr r0 + shlr r0 + shlr r0 + shlr r0 + shlr r0 + # Make sure a bit is shifted into T. + shlr r0 + bf wrong + # Ditto. + shlr r0 + bf wrong + shlr r0 + assert r0, #0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/shlr16.cgs b/sim/testsuite/sim/sh64/compact/shlr16.cgs new file mode 100644 index 00000000000..7bfc62788f3 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/shlr16.cgs @@ -0,0 +1,14 @@ +# sh testcase for shlr16 $rn +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global shrl16 +shrl16: + shlr16 r0 + + pass diff --git a/sim/testsuite/sim/sh64/compact/shlr2.cgs b/sim/testsuite/sim/sh64/compact/shlr2.cgs new file mode 100644 index 00000000000..6f085979443 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/shlr2.cgs @@ -0,0 +1,14 @@ +# sh testcase for shlr2 $rn +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global shrl2 +shrl2: + shlr2 r0 + + pass diff --git a/sim/testsuite/sim/sh64/compact/shlr8.cgs b/sim/testsuite/sim/sh64/compact/shlr8.cgs new file mode 100644 index 00000000000..82040b581b8 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/shlr8.cgs @@ -0,0 +1,14 @@ +# sh testcase for shlr8 $rn +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global shrl8 +shrl8: + shlr8 r0 + + pass diff --git a/sim/testsuite/sim/sh64/compact/stc-gbr.cgs b/sim/testsuite/sim/sh64/compact/stc-gbr.cgs new file mode 100644 index 00000000000..1b84008c9d2 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/stc-gbr.cgs @@ -0,0 +1,21 @@ +# sh testcase for stc gbr, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global stc_gbr +stc_gbr: + stc gbr, r1 + mov #42, r1 + ldc r1, gbr + stc gbr, r2 + cmp/eq r1, r2 + bf wrong +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/stcl-gbr.cgs b/sim/testsuite/sim/sh64/compact/stcl-gbr.cgs new file mode 100644 index 00000000000..3e74cc551de --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/stcl-gbr.cgs @@ -0,0 +1,27 @@ +# sh testcase for stc.l gbr, @-$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global stcl_gbr +stcl_gbr: + mov #42, r0 + ldc r0, gbr + mov #40, r0 + shll8 r0 + # save address + mov r0, r1 + stc.l gbr, @-r0 + + add #4, r0 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/sts-fpscr.cgs b/sim/testsuite/sim/sh64/compact/sts-fpscr.cgs new file mode 100644 index 00000000000..42724b44fff --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/sts-fpscr.cgs @@ -0,0 +1,23 @@ +# sh testcase for sts fpscr, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global sts_fpscr +sts_fpscr: + sts fpscr, r0 + mov #42, r0 + lds r0, fpscr + sts fpscr, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/sts-fpul.cgs b/sim/testsuite/sim/sh64/compact/sts-fpul.cgs new file mode 100644 index 00000000000..ddbdaf15fb2 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/sts-fpul.cgs @@ -0,0 +1,14 @@ +# sh testcase for sts fpul, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global sts_fpul +sts_fpul: + # This is properly exercised by the lds-fpul test case. + sts fpul, r1 + pass diff --git a/sim/testsuite/sim/sh64/compact/sts-mach.cgs b/sim/testsuite/sim/sh64/compact/sts-mach.cgs new file mode 100644 index 00000000000..4d34bc17aa8 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/sts-mach.cgs @@ -0,0 +1,22 @@ +# sh testcase for sts mach, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global sts_mach +sts_mach: + mov #42, r0 + lds r0, mach + sts mach, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/sts-macl.cgs b/sim/testsuite/sim/sh64/compact/sts-macl.cgs new file mode 100644 index 00000000000..b805f796e44 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/sts-macl.cgs @@ -0,0 +1,21 @@ +# sh testcase for sts macl, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global sts_macl +sts_macl: + mov #42, r0 + lds r0, macl + sts macl, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/sts-pr.cgs b/sim/testsuite/sim/sh64/compact/sts-pr.cgs new file mode 100644 index 00000000000..3e4f6ee880a --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/sts-pr.cgs @@ -0,0 +1,22 @@ +# sh testcase for sts pr, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global sts_pr +sts_pr: + mov #42, r0 + lds r0, pr + sts pr, r1 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/stsl-fpscr.cgs b/sim/testsuite/sim/sh64/compact/stsl-fpscr.cgs new file mode 100644 index 00000000000..032870dc189 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/stsl-fpscr.cgs @@ -0,0 +1,28 @@ +# sh testcase for sts.l fpscr, @-$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global stsl_fpscr +stsl_fpscr: + mov #40, r0 + shll8 r0 + # Preserve r0. + mov r0, r7 + sts.l fpscr, @-r0 + +check: + # Ensure r0 is decremented. + add #4, r0 + cmp/eq r0, r7 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/stsl-fpul.cgs b/sim/testsuite/sim/sh64/compact/stsl-fpul.cgs new file mode 100644 index 00000000000..89bd9e73849 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/stsl-fpul.cgs @@ -0,0 +1,27 @@ +# sh testcase for sts.l fpul, @-$rn -*- Asm -*_ +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global stsl_fpul +stsl_fpul: + mov #40, r0 + shll8 r0 + # Preserve r0. + mov r0, r7 + sts.l fpul, @-r0 + +dec: + # Check for proper pre-decrementing. + add #4, r0 + cmp/eq r0, r7 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/stsl-mach.cgs b/sim/testsuite/sim/sh64/compact/stsl-mach.cgs new file mode 100644 index 00000000000..e15bddece29 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/stsl-mach.cgs @@ -0,0 +1,42 @@ +# sh testcase for sts.l mach, @-$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global stsl_mach +stsl_mach: + # Build up a distinctive bit pattern. + mov #1, r0 + shll8 r0 + add #12, r0 + shll8 r0 + add #85, r0 + shll8 r0 + add #170, r0 + + lds r0, mach + mov #40, r2 + shll8 r2 + # Preserve r2. + mov r2, r7 + sts.l mach, @-r2 + + # check results. + mov.l @r2, r3 + cmp/eq r0, r3 + bf wrong + + # Ensure decrement occurred. + add #4, r2 + cmp/eq r2, r7 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/stsl-macl.cgs b/sim/testsuite/sim/sh64/compact/stsl-macl.cgs new file mode 100644 index 00000000000..854ef341552 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/stsl-macl.cgs @@ -0,0 +1,42 @@ +# sh testcase for sts.l macl, @-$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global stsl_macl +stsl_macl: + # Build up a distinctive bit pattern. + mov #1, r0 + shll8 r0 + add #12, r0 + shll8 r0 + add #85, r0 + shll8 r0 + add #170, r0 + + lds r0, macl + mov #40, r2 + shll8 r2 + # Preserve r2. + mov r2, r7 + sts.l macl, @-r2 + + # check results. + mov.l @r2, r3 + cmp/eq r0, r3 + bf wrong + + # Ensure decrement occurred. + add #4, r2 + cmp/eq r2, r7 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/stsl-pr.cgs b/sim/testsuite/sim/sh64/compact/stsl-pr.cgs new file mode 100644 index 00000000000..b519c9bb5bd --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/stsl-pr.cgs @@ -0,0 +1,42 @@ +# sh testcase for sts.l pr, @-$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global stsl_pr +stsl_pr: + # Build up a distinctive bit pattern. + mov #1, r0 + shll8 r0 + add #12, r0 + shll8 r0 + add #85, r0 + shll8 r0 + add #170, r0 + + lds r0, pr + mov #40, r2 + shll8 r2 + # Preserve r2. + mov r2, r7 + sts.l pr, @-r2 + + # check results. + mov.l @r2, r3 + cmp/eq r0, r3 + bf wrong + + # Ensure decrement occurred. + add #4, r2 + cmp/eq r2, r7 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/sub.cgs b/sim/testsuite/sim/sh64/compact/sub.cgs new file mode 100644 index 00000000000..3ba29f872aa --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/sub.cgs @@ -0,0 +1,68 @@ +# sh testcase for sub $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global sub1 +sub1: + # 0 - x. + mov #0, r0 + mov #3, r1 + sub r1, r0 + + mov #2, r7 + not r7, r7 + cmp/eq r7, r0 + bf wrong + + .global sub2 +sub2: + # x - 0. + mov #0, r0 + mov #3, r1 + sub r0, r1 + assert r1, #3 + + .global sub3 +sub3: + # x - y. + mov #4, r0 + mov #3, r1 + sub r0, r1 + + mov #0, r7 + not r7, r7 + cmp/eq r7, r1 + bf wrong + + .global sub4 +sub4: + # y - x. + mov #4, r0 + mov #3, r1 + sub r1, r0 + assert r0, #1 + + .global sub5 +sub5: + # y - y == 0 (where y are in two distinct registers). + mov #4, r0 + mov #4, r1 + sub r1, r0 + assert r0, #0 + + .global sub6 +sub6: + # y - y = 0 (where y is the same register). + mov #4, r1 + sub r1, r1 + assert r1, #0 + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/subc.cgs b/sim/testsuite/sim/sh64/compact/subc.cgs new file mode 100644 index 00000000000..cda1e84ae9d --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/subc.cgs @@ -0,0 +1,109 @@ +# sh testcase for subc $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start +zero: + mov #0, r0 + mov #0, r1 + clrt + subc r0, r1 + assert r1, #0 + +zerot: + mov #0, r0 + mov #0, r1 + sett + subc r0, r1 + # Invert all 1's to all 0's for ease of comparison. + not r1, r1 + assert r1, #0 + +null: + mov #0, r0 + mov #10, r1 + clrt + subc r0, r1 + assert r1, #10 + +nullt: + mov #0, r0 + mov #10, r1 + sett + subc r0, r1 + assert r1, #9 + +subc: + mov #10, r0 + mov #0, r1 + clrt + subc r0, r1 + # Again, invert .. + not r1, r1 + assert r1, #9 + +subct: + mov #10, r0 + mov #0, r1 + sett + subc r0, r1 + # Again, invert .. + not r1, r1 + assert r1, #10 + +subc2: + mov #10, r0 + mov #20, r1 + clrt + subc r0, r1 + assert r1, #10 + +subc2t: + mov #20, r0 + mov #10, r1 + sett + subc r0, r1 + # Again, invert .. + not r1, r1 + assert r1, #10 + +subc3: + mov #5, r0 + mov #5, r1 + clrt + subc r0, r1 + assert r1, #0 + +subc3t: + mov #5, r0 + mov #5, r1 + sett + subc r0, r1 + # Again, invert .. + not r1, r1 + assert r1, #0 + +large: + mov #2, r0 + mov #10, r1 + clrt + subc r1, r0 + # Again, invert .. + not r0, r0 + assert r0, #7 + +larget: + mov #2, r0 + mov #10, r1 + sett + subc r0, r1 + assert r1, #7 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/subv.cgs b/sim/testsuite/sim/sh64/compact/subv.cgs new file mode 100644 index 00000000000..ceb8c64e7fd --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/subv.cgs @@ -0,0 +1,55 @@ +# sh testcase for subv $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start +zero: + mov #0, r0 + mov #0, r1 + subv r0, r1 + bt wrong + assert r1, #0 + +one: + mov #10, r0 + mov #0, r1 + subv r0, r1 + bt wrong + not r1, r1 + assert r1, #9 + +large: + # Produce MAXINT in R0. + mov #0, r0 + not r0, r0 + shlr r0 + + # Put -3 into R1. + mov #3, r1 + neg r1, r1 + + # Subtract them and underflow. + subv r0, r1 + bf wrong + +another: + # Produce MAXINT in R0. + mov #0, r0 + not r0, r0 + shlr r0 + + # Put -3 into R1. + mov #3, r1 + neg r1, r1 + + # Subtract them and overflow. + subv r1, r0 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/swapb.cgs b/sim/testsuite/sim/sh64/compact/swapb.cgs new file mode 100644 index 00000000000..22f6f16a2e1 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/swapb.cgs @@ -0,0 +1,44 @@ +# sh testcase for swap.b $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +init: + # Build up a distinctive bit pattern. + mov #1, r0 + shll8 r0 + add #12, r0 + shll8 r0 + add #85, r0 + shll8 r0 + add #70, r0 + +test: + # Swap the lower two bytes into a different register. + swap.b r0, r1 + mov #1, r7 + shll8 r7 + add #12, r7 + shll8 r7 + add #70, r7 + shll8 r7 + add #85, r7 + cmp/eq r1, r7 + bf wrong + +swapback: + # Swap the lower two bytes into the same registers. + # R0 should now equal R1. + swap.b r1, r2 + cmp/eq r0, r2 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/swapw.cgs b/sim/testsuite/sim/sh64/compact/swapw.cgs new file mode 100644 index 00000000000..fa1ab697f27 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/swapw.cgs @@ -0,0 +1,43 @@ +# sh testcase for swap.w $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global swapw +swapw: + # Build up a characteristic bit pattern in R0. + mov #85, r0 + shll16 r0 + add #3, r0 + rotr r0 + rotr r0 + or #170, r0 + # Preserve for later. + mov r0, r8 + +test: + swap.w r0, r1 + mov #64, r0 + shll8 r0 + or #170, r0 + shll8 r0 + or #192, r0 + shll8 r0 + or #21, r0 + cmp/eq r1, r0 + bf wrong + +swapback: + swap.w r1, r2 + cmp/eq r2, r8 + bf wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/tasb.cgs b/sim/testsuite/sim/sh64/compact/tasb.cgs new file mode 100644 index 00000000000..cb7f61870d2 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/tasb.cgs @@ -0,0 +1,26 @@ +# sh testcase for tas.b @$rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +tasb1: + mov #40, r0 + shll8 r0 + tas.b @r0 + bf wrong + +tasb2: + mov #40, r0 + shll8 r0 + tas.b @r0 + bt wrong + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/testutils.inc b/sim/testsuite/sim/sh64/compact/testutils.inc new file mode 100644 index 00000000000..b1ad830578b --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/testutils.inc @@ -0,0 +1,49 @@ +# Support macros for the assembly test cases. + + .macro start + .text + .global start +start: + .endm + + # Perform a single to double precision floating point conversion. + .macro _s2d fpr dpr + flds \fpr, fpul + _setpr + fcnvsd fpul, \dpr + _clrpr + .endm + + # Set the PR (PRecision) bit in the FPSCR. + .macro _setpr + sts fpscr, r7 + mov #8, r8 + shll16 r8 + or r8, r7 + lds r7, fpscr + .endm + + # Clear the PR bit. + .macro _clrpr + sts fpscr, r7 + mov #8, r8 + shll16 r8 + not r8, r8 + and r8, r7 + lds r7, fpscr + .endm + + # nb: this macro clobbers R7. + .macro assert reg value + mov \value, r7 + cmp/eq \reg, r7 + bf wrong + .endm + + .macro pass + trapa #253 + .endm + + .macro fail + trapa #254 + .endm diff --git a/sim/testsuite/sim/sh64/compact/trapa.cgs b/sim/testsuite/sim/sh64/compact/trapa.cgs new file mode 100644 index 00000000000..24f8a6b13ba --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/trapa.cgs @@ -0,0 +1,13 @@ +# sh testcase for trapa #$imm8 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global trapa +trapa: + # pass is a macro for "trapa #253". + trapa #253 diff --git a/sim/testsuite/sim/sh64/compact/tst.cgs b/sim/testsuite/sim/sh64/compact/tst.cgs new file mode 100644 index 00000000000..a72b8a9a743 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/tst.cgs @@ -0,0 +1,62 @@ +# sh testcase for tst $rm, $rn +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global tst1 +tst1: + mov #0, r0 + mov #0, r1 + tst r0, r0 + bf wrong + +test2: + mov #0, r0 + mov #1, r1 + tst r0, r1 + bf wrong + +test3: + mov #0, r0 + mov #1, r1 + tst r1, r0 + bf wrong + +test4: + mov #1, r0 + mov #1, r1 + tst r0, r1 + bt wrong + +test5: + mov #1, r0 + rotr r0 + add #85, r0 + shll16 r0 + add #12, r0 + mov #1, r1 + rotr r1 + add #85, r1 + shll16 r1 + add #12, r1 + tst r0, r1 + bt wrong + +test6: + mov #1, r0 + rotr r0 + add #85, r0 + shll16 r0 + add #12, r0 + mov #1, r1 + tst r0, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/tstb.cgs b/sim/testsuite/sim/sh64/compact/tstb.cgs new file mode 100644 index 00000000000..1b3829b1d30 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/tstb.cgs @@ -0,0 +1,30 @@ +# sh testcase for tst.b #$imm8, @(r0, gbr) -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global orb +init: + # Init GBR and R0. + mov #30, r0 + ldc r0, gbr + mov #40, r0 + +orb: + tst.b #0, @(r0, gbr) + bf wrong + tst.b #170, @(r0, gbr) + bf wrong + tst.b #0, @(r0, gbr) + bf wrong + tst.b #255, @(r0, gbr) + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/compact/tsti.cgs b/sim/testsuite/sim/sh64/compact/tsti.cgs new file mode 100644 index 00000000000..e088029b470 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/tsti.cgs @@ -0,0 +1,32 @@ +# sh testcase for tst #$imm8, r0 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global tsti +tsti: + mov #0, r0 + tst #0, r0 + +tsti2: + mov #0, r0 + tst #1, r0 + +tsti3: + mov #1, r0 + tst #0, r0 + +tsti4: + mov #1, r0 + tst #1, r0 + +tsti5: + mov #255, r0 + tst #255, r0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/compact/xor.cgs b/sim/testsuite/sim/sh64/compact/xor.cgs new file mode 100644 index 00000000000..d158aaf3713 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/xor.cgs @@ -0,0 +1,70 @@ +# sh testcase for xor $rm64, $rn64 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global xor +xor: + # 0 (+) 1 = 1. + mov #0, r0 + mov #1, r1 + xor r0, r1 + assert r1, #1 + +xor2: + # 1 (+) 0 = 0. + mov #1, r0 + mov #0, r1 + xor r0, r1 + assert r1, #1 + +xor3: + # 0 (+) 0 = 0. + mov #0, r0 + mov #0, r1 + xor r0, r1 + assert r1, #0 + +xor4: + # 0 (+) 0 = 0. + mov #0, r0 + xor r0, r0 + assert r0, #0 + +xor5: + mov #0, r0 + or #85, r0 + shll16 r0 + or #170, r0 + mov r0, r1 + mov #0, r0 + or #85, r0 + shll16 r0 + or #170, r0 + xor r1, r0 + assert r0, #0 + +xor6: + mov #0, r0 + or #85, r0 + shll16 r0 + or #170, r0 + mov r0, r1 + mov #0, r0 + or #85, r0 + shll16 r0 + or #12, r0 + xor r0, r1 + mov #0, r0 + or #166, r0 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/xorb.cgs b/sim/testsuite/sim/sh64/compact/xorb.cgs new file mode 100644 index 00000000000..b31464b3c13 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/xorb.cgs @@ -0,0 +1,24 @@ +# sh testcase for xor.b #$imm8, @(r0, gbr) -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global orb +init: + # Init GBR and R0. + mov #30, r0 + ldc r0, gbr + mov #40, r0 + +orb: + xor.b #0, @(r0, gbr) + xor.b #170, @(r0, gbr) + xor.b #0, @(r0, gbr) + xor.b #255, @(r0, gbr) + +okay: + pass diff --git a/sim/testsuite/sim/sh64/compact/xori.cgs b/sim/testsuite/sim/sh64/compact/xori.cgs new file mode 100644 index 00000000000..732b9ec5c48 --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/xori.cgs @@ -0,0 +1,50 @@ +# sh testcase for xor #$imm8, r0 -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + + .global xori +xori: + # 0 (+) 1 = 1. + mov #0, r0 + xor #1, r0 + assert r0, #1 + +xori2: + # 1 (+) 0 = 1. + mov #1, r0 + xor #0, r0 + assert r0, #1 + +xori3: + # 1 (+) 1 = 0. + mov #1, r0 + xor #1, r0 + assert r0, #0 + +xori4: + # 255 (+) 255 = 0. + mov #0, r0 + or #255, r0 + xor #255, r0 + assert r0, #0 + +xori5: + # 0 (+) 255 = 255. + mov #0, r0 + xor #255, r0 + mov r0, r1 + + mov #0, r0 + or #255, r0 + cmp/eq r0, r1 + bf wrong + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/compact/xtrct.cgs b/sim/testsuite/sim/sh64/compact/xtrct.cgs new file mode 100644 index 00000000000..11dae7cbdec --- /dev/null +++ b/sim/testsuite/sim/sh64/compact/xtrct.cgs @@ -0,0 +1,46 @@ +# sh testcase for xtrct $rm, $rn -*- Asm -*- +# mach: all +# as: -isa=shcompact +# ld: -m shelf32 + + .include "compact/testutils.inc" + + start + +init: + mov #170, r0 + shll8 r0 + add #1, r0 + shll8 r0 + add #66, r0 + shll8 r0 + mov r0, r1 + + mov #85, r0 + shll8 r0 + add #2, r0 + shll8 r0 + add #42, r0 + shll8 r0 + add #3, r0 + +copy: + mov r0, r3 + mov r1, r4 + +xtrct: + xtrct r0, r1 + +check: + # Lower r3, upper r4. + shll16 r3 + shlr16 r4 + or r3, r4 + cmp/eq r1, r4 + bf wrong + +okay: + pass +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/interwork.exp b/sim/testsuite/sim/sh64/interwork.exp new file mode 100644 index 00000000000..acd19b3c90c --- /dev/null +++ b/sim/testsuite/sim/sh64/interwork.exp @@ -0,0 +1,20 @@ +# SH64 interworking testsuite. +# In particular, test parts of the instruction set that can be used +# for SHmedia/SHcompact instruction set mode switches. + +if [istarget sh64-*-*] { + # load support procs (none yet) + # load_lib cgen.exp + + # all machines + set all_machs "sh5" + + foreach src [lsort [glob -nocomplain $srcdir/$subdir/misc/*.s]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/sim/sh64/media.exp b/sim/testsuite/sim/sh64/media.exp new file mode 100644 index 00000000000..1a3d9f4c961 --- /dev/null +++ b/sim/testsuite/sim/sh64/media.exp @@ -0,0 +1,19 @@ +# SHmedia testsuite. + +if [istarget sh64-*-*] { + # load support procs (none yet) + # load_lib cgen.exp + + # all machines + set all_machs "sh5" + + # The .cgs suffix is for "cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/media/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/sim/sh64/media/ChangeLog b/sim/testsuite/sim/sh64/media/ChangeLog new file mode 100644 index 00000000000..e435dbe5278 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ChangeLog @@ -0,0 +1,102 @@ +2001-01-09 Ben Elliston + + * nsb.cgs: Test consecutive bits of zeros as well as ones. + * ptb.cgs: Clean up. + +2001-01-08 Ben Elliston + + * fcmpund.cgs, fcmpuns.cgs: Complete test cases. + * fcnvds.cgs, fcnvsd.cgs, fgetscr.cgs, fiprs.cgs: Ditto. + * floatld.cgs, floatls.cgs, floatqd.cgs, floatqs.cgs: Ditto. + * fmuld.cgs, fmuls.cgs, fputscr.cgs, fstxp.cgs: Ditto. + * fsubd.cgs, fsubs.cgs, ftrcdl.cgs, ftrcdq.cgs: Ditto. + * ftrcsl.cgs, ftrcsq.cgs, ftrvs.cgs: Ditto. + * ldhil.cgs, ldhiq.cgs, ldlol.cgs, ldloq.cgs: Ditto. + * mabsl.cgs, mabsw.cgs, maddl.cgs, maddsl.cgs: Ditto. + * maddsub.cgs, maddsw.cgs, maddw.cgs: Ditto. + * mcmpeqb.cgs, mcmpeql.cgs, mcmpeqw.cgs: Ditto. + * mcmpgtl.cgs, mcmpgtub.cgs, mcmpgtw.cgs: Ditto. + * mcmv.cgs, mcnvslw.cgs, mcnvswb.cgs, mcnvswub.cgs: Ditto. + * mmacfxwl.cgs, mmacnfx-wl.cgs: Ditto. + * mmulfxl.cgs, mmulfxrpw.cgs, mmulfxw.cgs: Ditto. + * mmulhiwl.cgs, mmull.cgs, mmullowl.cgs: Ditto. + * mmulsumwq.cgs, mmulw.cgs, movi.cgs: Ditto. + * mpermw.cgs, msadubq.cgs: Ditto. + * mshaldsl.cgs, mshaldsw.cgs: Ditto. + * mshardl.cgs, mshardsq.cgs, mshardw.cgs: Ditto. + * mshfhib.cgs, mshfhil.cgs, mshfhiw.cgs: Ditto. + * mshflob.cgs, mshflol.cgs, mshflow.cgs: Ditto. + * mshlldl.cgs, mshlldw.cgs, mshlrdl.cgs: Ditto. + * mshlrdw.cgs, msubl.cgs, msubsl.cgs: Ditto. + * msubsub.cgs, msubsw.cgs, msubw.cgs: Ditto. + * mulsl.cgs, mulul.cgs: Ditto. + * ptabs.cgs, ptb.cgs, ptrel.cgs: Ditto. + * shard.cgs, shardl.cgs, shari.cgs, sharil.cgs: Ditto. + * shlld.cgs, shlldl.cgs, shlli.cgs, shllil.cgs: Ditto. + * shlrd.cgs, shlrdl.cgs, shlri.cgs, shlril.cgs: Ditto. + * sthil.cgs, sthiq.cgs, swapq.cgs, trapa.cgs: Ditto. + + * testutils.inc (pass): Pass correct "syscall" number. + (fail): Ditto. + +2000-12-13 Ben Elliston + + * sub.cgs, subl.cgs: Complete test cases. + * ptrel.cgs: Likewise. + + * shori.cgs: Test for zero extension of immediate operand. + * fcmpged.cgs, fcmpges.cgs, fldd.cgs: Complete test cases. + * fldp.cgs, flds.cgs, fldxd.cgs, fldxp.cgs: Likewise. + * fldxs.cgs, fmacs.cgs, fnegd.cgs, fnegs.cgs: Likewise. + * fsqrtd.cgs, fsqrts.cgs, fstd.cgs, fstp.cgs: Likewise. + * fsts.cgs, fstxd.cgs, fstxs.cgs: Likewise. + +2000-12-12 Ben Elliston + + * testutils.inc (pass): Use simple syscall mechanism. + (fail): Likewise. + (_packb, _packw, _packl): New macros for packing slices. + + * stb.cgs, stq.cgs, stxb.cgs, stxq.cgs: Complete test cases. + * stl.cgs, stw.cgs, stxl.cgs, stxw.cgs: Likewise. + * ldl.cgs, ldq.cgs, ldub.cgs, lduw.cgs, ldw.cgs: Likewise. + * ldxb.cgs, ldxl.cgs, ldxq.cgs, ldxub.cgs: Likewise. + * ldxuw.cgs, ldxw.cgs, nsb.cgs, trapa.cgs: Likewise. + + * fcmpeqd.cgs, fcmpeqs.cgs, fcmpgtd.cgs: Complete test cases. + * fcmpgts.cgs, fdivd.cgs, fdivs.cgs, fmovd.cgs: Likewise. + * fmovdq.cgs, fmovqd.cgs, fmovls.cgs, fmovs.cgs: Likewise. + * fmovsl.cgs: Likewise. + +2000-12-11 Ben Elliston + + * fabss.cgs, fabsd.cgs, fadds.cgs, faddd.cgs: Complete test cases. + * getcfg.cgs, getcon.cgs, gettr.cgs, icbi.cgs: Likewise. + * prefi.cgs, pta.cgs, ptabs.cgs, ptb.cgs: Likewise. + * putcon.cgs, putcfg.cgs, rte.cgs: Likewise. + + * add.cgs, addi.cgs, addl.cgs, addil.cgs: Complete test cases. + * addl.cgs, addzl.cgs, alloco.cgs, and.cgs, andc.cgs: Likewise. + * andi.cgs, beq.cgs, beqi.cgs, bge.cgs, bgeu.cgs: Likewise. + * bgt.cgs, bgtu.cgs, blink.cgs, bne.cgs, bnei.cgs: Likewise. + * brk.cgs, byterev.cgs, cmpeq.cgs, cmpgt.cgs: Likewise. + * cmpgtu.cgs, cmveq.cgs, cmvne.cgs: Likewise. + +2000-12-07 Ben Elliston + + * mextr1.cgs, mextr2.cgs, mextr3.cgs: Complete test cases. + * mextr4.cgs, mextr5.cgs, mextr6.cgs, mextr7.cgs: Likewise. + +2000-12-05 Ben Elliston + + * nop.cgs, ocbi.cgs, ocbp.cgs, ocbwb.cgs: Complete test cases. + * or.cgs, ori.cgs, xor.cgs, xori.cgs: Ditto. + * sleep.cgs, synci.cgs, synco.cgs: Ditto. + +2000-11-22 Ben Elliston + + * *.cgs: Include "media/testutils.inc", not "testutils.inc" as + generated test cases do. Miscellaneous fixes. + + * testutils.inc: New file. + * *.cgs: Generate test cases. diff --git a/sim/testsuite/sim/sh64/media/add.cgs b/sim/testsuite/sim/sh64/media/add.cgs new file mode 100644 index 00000000000..9778e8fd62c --- /dev/null +++ b/sim/testsuite/sim/sh64/media/add.cgs @@ -0,0 +1,47 @@ +# sh testcase for add $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global add +init: + pta wrong, tr0 +add: + movi 10, r0 + movi 0, r1 + add r0, r1, r3 + movi 10, r4 + bne r3, r4, tr0 + +add0: + movi 1, r63 + add r63, r63, r1 + bnei r1, 0, tr0 + +add2: + movi 0, r0 + movi 10, r1 + add r0, r1, r3 + movi 10, r4 + bne r3, r4, tr0 + +add3: + movi 10, r1 + add r63, r1, r3 + movi 10, r4 + bne r3, r4, tr0 + +add4: + movi 10, r1 + add r1, r63, r3 + movi 10, r4 + bne r3, r4, tr0 + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/addi.cgs b/sim/testsuite/sim/sh64/media/addi.cgs new file mode 100644 index 00000000000..3d4b49f5995 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/addi.cgs @@ -0,0 +1,37 @@ +# sh testcase for addi $rm, $disp10, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +addi1: + movi 1, r0 + addi r0, 10, r0 + bnei r0, 11, tr0 + +addi2: + movi 10, r0 + addi r0, 1, r0 + bnei r0, 11, tr0 + +addi3: + movi 10, r0 + addi r0, -1, r0 + bnei r0, 9, tr0 + +addi4: + movi 20, r0 + addi r0, -2, r0 + bnei r0, 18, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/addil.cgs b/sim/testsuite/sim/sh64/media/addil.cgs new file mode 100644 index 00000000000..5c92e2733a6 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/addil.cgs @@ -0,0 +1,49 @@ +# sh testcase for addi.l $rm, $disp10, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +addil0: + movi 1, r63 + addi.l r63, 0, r1 + bnei r1, 0, tr0 + +addil1: + movi 10, r0 + addi.l r0, 0, r3 + bnei r3, 10, tr0 + +addil2: + movi 0, r0 + addi.l r0, 10, r2 + bnei r2, 10, tr0 + +addil3: + addi.l r63, 10, r1 + bnei r1, 10, tr0 + +addil4: + movi 10, r0 + addi.l r0, 0, r1 + bnei r1, 10, tr0 + +addil5: + # Ensure top 32-bits are discarded when adding. + movi 10, r0 + shlli r0, 32, r0 + addi r0, 10, r0 + addi.l r0, 10, r2 + bnei r2, 20, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/addl.cgs b/sim/testsuite/sim/sh64/media/addl.cgs new file mode 100644 index 00000000000..7f94b616206 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/addl.cgs @@ -0,0 +1,61 @@ +# sh testcase for add.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global addl +init: + pta wrong, tr0 + +addl0: + movi 1, r63 + add.l r63, r63, r1 + bnei r1, 0, tr0 + +addl1: + movi 10, r0 + movi 0, r1 + add.l r0, r1, r3 + movi 10, r4 + bne r3, r4, tr0 + +addl2: + movi 0, r0 + movi 10, r1 + add.l r0, r1, r2 + movi 10, r3 + bne r2, r3, tr0 + +addl3: + movi 10, r0 + add.l r63, r0, r1 + movi 10, r2 + bne r1, r2, tr0 + +addl4: + movi 10, r0 + add.l r0, r63, r1 + movi 10, r2 + bne r1, r2, tr0 + +addl5: + # Ensure top 32-bits are discarded when adding. + movi 10, r0 + shlli r0, 32, r0 + addi r0, 10, r0 + movi 10, r1 + shlli r1, 32, r1 + addi r1, 10, r1 + add.l r0, r1, r2 + movi 20, r3 + bne r2, r3, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/addzl.cgs b/sim/testsuite/sim/sh64/media/addzl.cgs new file mode 100644 index 00000000000..b7917d377a6 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/addzl.cgs @@ -0,0 +1,39 @@ +# sh testcase for addz.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +addzl1: + movi 1, r0 + movi 2, r1 + addz.l r0, r1, r2 + bnei r2, 3, tr0 + +addzl2: + movi 1, r0 + shlli r0, 32, r0 + addi r0, 2, r0 + movi 1, r1 + shlli r1, 32, r1 + addi r1, 2, r1 + addz.l r0, r1, r2 + bnei r2, 4, tr0 + +addzl3: + movi 1, r0 + shlli r0, 31, r0 + addi r0, 2, r0 + movi 2, r1 + addz.l r0, r1, r2 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/alloco.cgs b/sim/testsuite/sim/sh64/media/alloco.cgs new file mode 100644 index 00000000000..5f27359c3b6 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/alloco.cgs @@ -0,0 +1,10 @@ +# sh testcase for alloco $rm, $disp6x32 -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + alloco r0, 32 + pass diff --git a/sim/testsuite/sim/sh64/media/and.cgs b/sim/testsuite/sim/sh64/media/and.cgs new file mode 100644 index 00000000000..c2d42339bcf --- /dev/null +++ b/sim/testsuite/sim/sh64/media/and.cgs @@ -0,0 +1,68 @@ +# sh testcase for and $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +and0: + # 0 and 0 is 0. + movi 0, r0 + movi 0, r1 + and r0, r1, r2 + bnei r2, 0, tr0 + +and1: + # 0 and 1 is 0. + movi 0, r0 + movi 1, r1 + and r0, r1, r2 + bnei r2, 0, tr0 + +and2: + # 1 and 0 is 0. + movi 1, r0 + movi 0, r1 + and r0, r1, r2 + bnei r2, 0, tr0 + +and3: + # 1 and 1 is 1. + movi 1, r0 + movi 1, r1 + and r0, r1, r2 + bnei r2, 1, tr0 + +and4: + movi 1, r0 + shlli r0, 63, r0 + movi 1, r1 + shlli r1, 63, r1 + and r0, r1, r2 + # Check it. + movi 1, r3 + shlli r3, 63, r3 + bne r2, r3, tr0 + +and5: + movi 1, r0 + shlli r0, 63, r0 + movi 1, r1 + shlli r1, 63, r1 + ori r1, 1, r1 + and r0, r1, r2 + # Check it. + movi 1, r3 + shlli r1, 63, r1 + bne r1, r2, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/andc.cgs b/sim/testsuite/sim/sh64/media/andc.cgs new file mode 100644 index 00000000000..60b50ace465 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/andc.cgs @@ -0,0 +1,50 @@ +# sh testcase for andc $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +andc1: + # X . !X = 0. + movi 3, r0 + movi 3, r1 + andc r0, r1, r2 + bnei r2, 0, tr0 + +andc2: + # X . 0 = X. + movi 3, r0 + movi 0, r1 + andc r0, r1, r2 + bnei r2, 3, tr0 + +andc3: + # wide X . 0 = wide X. + movi 0x1020, r0 + shlli r0, 8, r0 + ori r0, 0x30, r0 + shlli r0, 8, r0 + ori r0, 0x40, r0 + shlli r0, 8, r0 + ori r0, 0x50, r0 + shlli r0, 8, r0 + ori r0, 0x60, r0 + shlli r0, 8, r0 + ori r0, 0x70, r0 + shlli r0, 8, r0 + ori r0, 0x80, r0 + movi 0, r1 + andc r0, r1, r2 + bne r0, r2, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/andi.cgs b/sim/testsuite/sim/sh64/media/andi.cgs new file mode 100644 index 00000000000..decfc2fc2ec --- /dev/null +++ b/sim/testsuite/sim/sh64/media/andi.cgs @@ -0,0 +1,46 @@ +# sh testcase for andi $rm, $disp10, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +andi0: + # 0 and 0 is 0. + movi 0, r0 + andi r0, 0, r2 + bnei r2, 0, tr0 + +and1: + # 0 and 1 is 0. + movi 0, r0 + andi r0, 1, r2 + bnei r2, 0, tr0 + +and2: + # 1 and 0 is 0. + movi 1, r0 + andi r0, 0, r2 + bnei r2, 0, tr0 + +and3: + # 1 and 1 is 1. + movi 1, r0 + andi r0, 1, r2 + bnei r2, 1, tr0 + +and4: + movi 15, r0 + andi r0, 3, r2 + bnei r2, 3, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/beq.cgs b/sim/testsuite/sim/sh64/media/beq.cgs new file mode 100644 index 00000000000..6f96ffdf00f --- /dev/null +++ b/sim/testsuite/sim/sh64/media/beq.cgs @@ -0,0 +1,52 @@ +# sh testcase for beq$likely $rm, $rn, $tra -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global beq +init: + # Load up the branch target registers. + pta beq2, tr0 + pta beq3, tr1 + pta wrong, tr2 + +beq1: + # Compare r0 with itself. + # Always true, so branch likely. + movi 1, r0 + beq/l r0, r0, tr0 + # We should branch over this. + fail + +beq2: + # Ensure high order bits are compared, too. + movi 1, r0 + shlli r0, 35, r0 + addi r0, 10, r0 + movi 1, r1 + shlli r1, 35, r1 + addi r1, 10, r1 + beq r0, r1, tr1 + # We should branch over this, too. + fail + +beq3: + movi 1, r0 + shlli r0, 35, r0 + addi r0, 10, r0 + movi 2, r1 + shlli r1, 35, r1 + addi r1, 9, r1 + # Unlikely we'll branch! + beq/u r0, r1, tr2 + # We should proceed to pass here. + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/beqi.cgs b/sim/testsuite/sim/sh64/media/beqi.cgs new file mode 100644 index 00000000000..c2b4ea8acf5 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/beqi.cgs @@ -0,0 +1,40 @@ +# sh testcase for beqi$likely $rm, $imm6, $tra -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global beqi +init: + # Load up the branch target registers. + pta beqi2, tr0 + pta beqi3, tr1 + pta wrong, tr2 + +beqi1: + # Always true, so branch likely. + movi 1, r0 + beqi/l r0, 1, tr0 + # We should branch over this. + fail + +beqi2: + movi 22, r3 + beqi r3, 22, tr1 + # We should branch over this. + fail + +beqi3: + movi 27, r7 + # We shouldn't branch here. + beqi/u r7, 23, tr2 + # We should proceed to pass here. + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/bge.cgs b/sim/testsuite/sim/sh64/media/bge.cgs new file mode 100644 index 00000000000..832ff06ac21 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/bge.cgs @@ -0,0 +1,40 @@ +# sh testcase for bge$likely $rm, $rn, $tra -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global bge +init: + pta bge2, tr0 + pta bge3, tr1 + pta wrong, tr2 + movi 0, r0 + +bge1: + # Compare r0 with itself. + bge/l r0, r0, tr0 + # We should branch here. + fail + +bge2: + movi 1, r1 + movi 1, r2 + bge r1, r2, tr1 + # We should branch here. + fail + +bge3: + movi -1, r1 + movi 1, r2 + bge r1, r2, tr2 + # We should not branch here. + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/bgeu.cgs b/sim/testsuite/sim/sh64/media/bgeu.cgs new file mode 100644 index 00000000000..da469d0e4ae --- /dev/null +++ b/sim/testsuite/sim/sh64/media/bgeu.cgs @@ -0,0 +1,47 @@ +# sh testcase for bgeu$likely $rm, $rn, $tra -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global bgeu +init: + movi 0, r0 + +bgeu1: + # Compare r0 with itself. + pta bgeu2, tr0 + bgeu/l r0, r0, tr0 + # We should branch here. + fail + +bgeu2: + movi 1, r1 + movi 1, r2 + pta bge3, tr0 + bgeu r1, r2, tr0 + # We should branch here. + fail + +bge3: + movi -1, r1 + movi 1, r2 + # We SHOULD branch here. + pta bge4, tr0 + bgeu r1, r2, tr0 + fail + +bge4: + movi 1, r1 + movi -1, r2 + # We should not branch here. + pta wrong, tr0 + bgeu r1, r2, tr0 +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/bgt.cgs b/sim/testsuite/sim/sh64/media/bgt.cgs new file mode 100644 index 00000000000..8866635b818 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/bgt.cgs @@ -0,0 +1,32 @@ +# sh testcase for bgt$likely $rm, $rn, $tra -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + +init: + pta wrong, tr0 + +bgt1: + movi 1, r0 + movi -1, r1 + bgt r1, r0, tr0 + +bgt2: + bgt r0, r0, tr0 + +bgt3: + pta okay, tr1 + movi -1, r0 + movi 1, r1 + bgt r0, r1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/bgtu.cgs b/sim/testsuite/sim/sh64/media/bgtu.cgs new file mode 100644 index 00000000000..3cc02696e75 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/bgtu.cgs @@ -0,0 +1,36 @@ +# sh testcase for bgtu$likely $rm, $rn, $tra -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + +init: + pta wrong, tr0 + +bgtu1: + movi 1, r0 + movi -1, r1 + pta bgt2, tr1 + bgtu r1, r0, tr1 + fail + +bgt2: + bgtu r0, r0, tr0 + +bgt3: + pta okay, tr1 + movi -1, r0 + movi 1, r1 + pta okay, tr1 + bgtu r0, r1, tr1 + fail + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/blink.cgs b/sim/testsuite/sim/sh64/media/blink.cgs new file mode 100644 index 00000000000..000d1f597f2 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/blink.cgs @@ -0,0 +1,17 @@ +# sh testcase for blink $trb, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +blink: + pta target, tr0 + gettr tr0, r1 + ptabs r1, tr0 + blink tr0, r0 + fail + +target: + pass diff --git a/sim/testsuite/sim/sh64/media/bne.cgs b/sim/testsuite/sim/sh64/media/bne.cgs new file mode 100644 index 00000000000..f574147e3de --- /dev/null +++ b/sim/testsuite/sim/sh64/media/bne.cgs @@ -0,0 +1,23 @@ +# sh testcase for bne$likely $rm, $rn, $tra -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + movi 1, r0 + pta wrong, tr0 + pta okay, tr1 + +bne1: + bne r63, r63, tr0 +bne2: + bne r0, r63, tr1 +bad: + fail +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/bnei.cgs b/sim/testsuite/sim/sh64/media/bnei.cgs new file mode 100644 index 00000000000..5ce33991c0d --- /dev/null +++ b/sim/testsuite/sim/sh64/media/bnei.cgs @@ -0,0 +1,23 @@ +# sh testcase for bnei$likely $rm, $imm6, $tra -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + movi 1, r0 + pta wrong, tr0 + pta okay, tr1 + +bnei1: + bnei r63, 0, tr0 +bnei2: + bnei r0, 3, tr1 +bad: + fail +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/brk.cgs b/sim/testsuite/sim/sh64/media/brk.cgs new file mode 100644 index 00000000000..073641443ec --- /dev/null +++ b/sim/testsuite/sim/sh64/media/brk.cgs @@ -0,0 +1,11 @@ +# sh testcase for brk -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + # brk will cause the sim to trap, so avoid it. + pass + brk diff --git a/sim/testsuite/sim/sh64/media/byterev.cgs b/sim/testsuite/sim/sh64/media/byterev.cgs new file mode 100644 index 00000000000..d97c3adb7b0 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/byterev.cgs @@ -0,0 +1,67 @@ +# sh testcase for byterev $rm, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + pta wrong, tr0 +init: + # Put a distinctive pattern in r0. + movi 10, r0 + shlli r0, 8, r0 + ori r0, 20, r0 + shlli r0, 8, r0 + ori r0, 30, r0 + shlli r0, 8, r0 + ori r0, 40, r0 + shlli r0, 8, r0 + ori r0, 50, r0 + shlli r0, 8, r0 + ori r0, 60, r0 + shlli r0, 8, r0 + ori r0, 70, r0 + shlli r0, 8, r0 + ori r0, 80, r0 + +byterev: + byterev r0, r1 + +check: + andi r1, 255, r2 + movi 10, r3 + bne r2, r3, tr0 + shlri r1, 8, r1 + andi r1, 255, r2 + movi 20, r3 + bne r2, r3, tr0 + shlri r1, 8, r1 + andi r1, 255, r2 + movi 30, r3 + bne r2, r3, tr0 + shlri r1, 8, r1 + andi r1, 255, r2 + movi 40, r3 + bne r2, r3, tr0 + shlri r1, 8, r1 + andi r1, 255, r2 + movi 50, r3 + bne r2, r3, tr0 + shlri r1, 8, r1 + andi r1, 255, r2 + movi 60, r3 + bne r2, r3, tr0 + shlri r1, 8, r1 + andi r1, 255, r2 + movi 70, r3 + bne r2, r3, tr0 + shlri r1, 8, r1 + andi r1, 255, r2 + movi 80, r3 + bne r2, r3, tr0 + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/cmpeq.cgs b/sim/testsuite/sim/sh64/media/cmpeq.cgs new file mode 100644 index 00000000000..78f51f4a65d --- /dev/null +++ b/sim/testsuite/sim/sh64/media/cmpeq.cgs @@ -0,0 +1,42 @@ +# sh testcase for cmpeq $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + movi 0, r0 + movi 1, r1 + movi 2, r2 + movi 2, r3 + movi 3, r4 + +cmpeq1: + cmpeq r2, r2, r7 + bne r7, r1, tr0 + +cmpeq2: + cmpeq r2, r3, r7 + bne r7, r1, tr0 + +cmpeq3: + cmpeq r2, r4, r7 + bne r7, r0, tr0 + +cmpeq4: + movi 1, r2 + shlli r2, 63, r2 + movi 1, r3 + shlli r3, 63, r3 + cmpeq r2, r3, r7 + bne r7, r1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/cmpgt.cgs b/sim/testsuite/sim/sh64/media/cmpgt.cgs new file mode 100644 index 00000000000..e4a971bd5ee --- /dev/null +++ b/sim/testsuite/sim/sh64/media/cmpgt.cgs @@ -0,0 +1,43 @@ +# sh testcase for cmpgt $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + movi 0, r0 + movi 1, r1 + movi 2, r2 + movi 2, r3 + movi 3, r4 + +cmpgt1: + cmpgt r2, r2, r7 + bne r7, r0, tr0 + +cmpgt2: + cmpgt r2, r3, r7 + bne r7, r0, tr0 + +cmpgt3: + cmpgt r4, r2, r7 + bne r7, r1, tr0 + +cmpgt4: + movi 1, r2 + shlli r2, 63, r2 + movi 1, r3 + shlli r3, 63, r3 + addi r3, 1, r3 + cmpgt r3, r2, r7 + bne r7, r1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/cmpgtu.cgs b/sim/testsuite/sim/sh64/media/cmpgtu.cgs new file mode 100644 index 00000000000..b896dfcb9fd --- /dev/null +++ b/sim/testsuite/sim/sh64/media/cmpgtu.cgs @@ -0,0 +1,43 @@ +# sh testcase for cmpgtu $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + movi 0, r0 + movi 1, r1 + movi 2, r2 + movi 2, r3 + movi 3, r4 + +cmpgt1: + cmpgtu r2, r2, r7 + bne r7, r0, tr0 + +cmpgt2: + cmpgtu r2, r3, r7 + bne r7, r0, tr0 + +cmpgt3: + cmpgtu r4, r2, r7 + bne r7, r1, tr0 + +cmpgt4: + movi 1, r2 + shlli r2, 63, r2 + movi 1, r3 + shlli r3, 63, r3 + addi r3, 1, r3 + cmpgtu r3, r2, r7 + bne r7, r1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/cmveq.cgs b/sim/testsuite/sim/sh64/media/cmveq.cgs new file mode 100644 index 00000000000..0f49733de36 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/cmveq.cgs @@ -0,0 +1,32 @@ +# sh testcase for cmveq $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + + movi 0, r0 + movi 1, r1 + movi 2, r2 + movi 21, r3 + +cmveq: + # Zap r7. + movi 0, r7 + + cmveq r0, r2, r7 + bne r2, r7, tr0 + + cmveq r1, r3, r7 + # Make sure r7 is still equal to r2. + bne r2, r7, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/cmvne.cgs b/sim/testsuite/sim/sh64/media/cmvne.cgs new file mode 100644 index 00000000000..909179afc76 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/cmvne.cgs @@ -0,0 +1,32 @@ +# sh testcase for cmvne $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + + movi 0, r0 + movi 1, r1 + movi 2, r2 + movi 21, r3 + +cmvne: + # Zap r7. + movi 0, r7 + + cmvne r1, r2, r7 + bne r2, r7, tr0 + + cmvne r0, r3, r7 + # Make sure r7 is still equal to r2. + bne r2, r7, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fabsd.cgs b/sim/testsuite/sim/sh64/media/fabsd.cgs new file mode 100644 index 00000000000..47060fcc44b --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fabsd.cgs @@ -0,0 +1,39 @@ +# sh testcase for fabs.d $drgh, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + movi 0, r0 + movi 1, r1 + +fabs0: + # Ensure fabs(-1) = 1. + fmov.ls r0, fr7 + float.ld fr7, dr0 + fmov.ls r1, fr7 + float.ld fr7, dr2 + fsub.d dr0, dr2, dr4 + fabs.d dr4, dr6 + fcmpeq.d dr6, dr2, r7 + bnei r7, 1, tr0 + +fabs1: + # Ensure fabs(1) = 1. + fmov.ls r0, fr7 + float.ld fr7, dr0 + fmov.ls r1, fr7 + float.ld fr7, dr2 + fabs.d dr2, dr4 + fcmpeq.d dr2, dr4, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fabss.cgs b/sim/testsuite/sim/sh64/media/fabss.cgs new file mode 100644 index 00000000000..dd9aec7e640 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fabss.cgs @@ -0,0 +1,39 @@ +# sh testcase for fabs.s $frgh, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + movi 0, r0 + movi 1, r1 + +fabs0: + # Ensure fabs(-1) = 1. + fmov.ls r0, fr7 + float.ls fr7, fr0 + fmov.ls r1, fr7 + float.ls fr7, fr1 + fsub.s fr0, fr1, fr2 + fabs.s fr2, fr3 + fcmpeq.s fr3, fr1, r7 + bnei r7, 1, tr0 + +fabs1: + # Ensure fabs(1) = 1. + fmov.ls r0, fr7 + float.ls fr7, fr0 + fmov.ls r1, fr7 + float.ls fr7, fr1 + fabs.s fr1, fr2 + fcmpeq.s fr1, fr2, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/faddd.cgs b/sim/testsuite/sim/sh64/media/faddd.cgs new file mode 100644 index 00000000000..096f8528946 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/faddd.cgs @@ -0,0 +1,33 @@ +# sh testcase for fadd.d $drg, $drh, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + movi 2, r0 + movi 3, r1 + +fadd0: + # Add 2 and 3. + fmov.ls r0, fr7 + float.ld fr7, dr0 + fmov.ls r1, fr7 + float.ld fr7, dr2 + fadd.d dr0, dr2, dr4 + # Check to make sure we got 5. + movi 5, r2 + fmov.ls r2, fr7 + float.ld fr7, dr6 + fcmpeq.d dr4, dr6, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fadds.cgs b/sim/testsuite/sim/sh64/media/fadds.cgs new file mode 100644 index 00000000000..fb93979c737 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fadds.cgs @@ -0,0 +1,34 @@ +# sh testcase for fadd.s $frg, $frh, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global fadds +init: + pta wrong, tr0 + movi 2, r0 + movi 3, r1 + +fadd0: + # Add 2 and 3. + fmov.ls r0, fr7 + float.ls fr7, fr0 + fmov.ls r1, fr7 + float.ls fr7, fr1 + fadd.s fr0, fr1, fr2 + # Check to make sure we got 5. + movi 5, r2 + fmov.ls r2, fr7 + float.ls fr7, fr3 + fcmpeq.s fr2, fr3, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fcmpeqd.cgs b/sim/testsuite/sim/sh64/media/fcmpeqd.cgs new file mode 100644 index 00000000000..c19356476f9 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fcmpeqd.cgs @@ -0,0 +1,36 @@ +# sh testcase for fcmpeq.d $drg, $drh, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +fcmpeq1: + movi 1, r0 + fmov.ls r0, fr0 + fmov.ls r0, fr1 + float.ld fr0, dr2 + float.ld fr1, dr4 + fcmpeq.d dr2, dr2, r7 + bnei r7, 1, tr0 + +fcmpeq2: + movi 1, r0 + fmov.ls r0, fr0 + movi 2, r1 + fmov.ls r1, fr1 + float.ld fr0, dr4 + float.ld fr1, dr6 + fcmpeq.d dr4, dr6, r7 + bnei r7, 0, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fcmpeqs.cgs b/sim/testsuite/sim/sh64/media/fcmpeqs.cgs new file mode 100644 index 00000000000..216894d7d20 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fcmpeqs.cgs @@ -0,0 +1,36 @@ +# sh testcase for fcmpeq.s $frg, $frh, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +fcmpeq1: + movi 1, r0 + fmov.ls r0, fr0 + fmov.ls r0, fr1 + float.ls fr0, fr2 + float.ls fr1, fr3 + fcmpeq.s fr2, fr3, r7 + bnei r7, 1, tr0 + +fcmpeq2: + movi 1, r0 + fmov.ls r0, fr0 + movi 2, r1 + fmov.ls r1, fr1 + float.ls fr0, fr2 + float.ls fr1, fr3 + fcmpeq.s fr2, fr3, r7 + bnei r7, 0, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fcmpged.cgs b/sim/testsuite/sim/sh64/media/fcmpged.cgs new file mode 100644 index 00000000000..52496cc6b14 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fcmpged.cgs @@ -0,0 +1,46 @@ +# sh testcase for fcmpge.d $drg, $drh, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +fcmpge1: # 2 = 2. + movi 2, r0 + fmov.ls r0, fr0 + fmov.ls r0, fr1 + float.ld fr0, dr2 + float.ld fr1, dr4 + fcmpge.d dr2, dr4, r7 + bnei r7, 1, tr0 + +fcmpge2: # 4 > 2. + movi 4, r0 + fmov.ls r0, fr0 + movi 2, r0 + fmov.ls r0, fr1 + float.ld fr0, dr2 + float.ld fr1, dr4 + fcmpge.d dr2, dr4, r7 + bnei r7, 1, tr0 + +fcmpge3: # 2 < 4. + movi 2, r0 + fmov.ls r0, fr0 + movi 4, r0 + fmov.ls r0, fr1 + float.ld fr0, dr2 + float.ld fr1, dr4 + fcmpge.d dr2, dr4, r7 + bnei r7, 0, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fcmpges.cgs b/sim/testsuite/sim/sh64/media/fcmpges.cgs new file mode 100644 index 00000000000..2dd0a35fd27 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fcmpges.cgs @@ -0,0 +1,46 @@ +# sh testcase for fcmpge.s $frg, $frh, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +fcmpge1: # 2 = 2. + movi 2, r0 + fmov.ls r0, fr0 + fmov.ls r0, fr1 + float.ls fr0, fr2 + float.ls fr1, fr3 + fcmpge.s fr2, fr3, r7 + bnei r7, 1, tr0 + +fcmpge2: # 3 > 2. + movi 3, r0 + fmov.ls r0, fr0 + movi 2, r0 + fmov.ls r0, fr1 + float.ls fr0, fr2 + float.ls fr1, fr3 + fcmpge.s fr2, fr3, r7 + bnei r7, 1, tr0 + +fcmpge3: # 2 < 3. + movi 2, r0 + fmov.ls r0, fr0 + movi 3, r0 + fmov.ls r0, fr1 + float.ls fr0, fr2 + float.ls fr1, fr3 + fcmpge.s fr2, fr3, r7 + bnei r7, 0, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fcmpgtd.cgs b/sim/testsuite/sim/sh64/media/fcmpgtd.cgs new file mode 100644 index 00000000000..aec952097de --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fcmpgtd.cgs @@ -0,0 +1,36 @@ +# sh testcase for fcmpgt.d $drg, $drh, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +fcmpgt1: + movi 2, r0 + fmov.qd r0, dr0 + movi 1, r1 + fmov.qd r1, dr2 + float.qd dr0, dr4 + float.qd dr2, dr6 + fcmpgt.d dr4, dr6, r7 + bnei r7, 1, tr0 + +fcmpgt2: + movi 1, r0 + fmov.qd r0, dr0 + fmov.qd r0, dr2 + float.qd dr0, dr4 + float.qd dr2, dr6 + fcmpgt.d dr4, dr6, r7 + bnei r7, 0, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fcmpgts.cgs b/sim/testsuite/sim/sh64/media/fcmpgts.cgs new file mode 100644 index 00000000000..893bbcbf60b --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fcmpgts.cgs @@ -0,0 +1,36 @@ +# sh testcase for fcmpgt.s $frg, $frh, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +fcmpgt1: + movi 2, r0 + fmov.ls r0, fr0 + movi 1, r1 + fmov.ls r1, fr1 + float.ls fr0, fr2 + float.ls fr1, fr3 + fcmpgt.s fr2, fr3, r7 + bnei r7, 1, tr0 + +fcmpgt2: + movi 1, r0 + fmov.ls r0, fr0 + fmov.ls r0, fr1 + float.ls fr0, fr2 + float.ls fr1, fr3 + fcmpgt.s fr2, fr3, r7 + bnei r7, 0, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fcmpund.cgs b/sim/testsuite/sim/sh64/media/fcmpund.cgs new file mode 100644 index 00000000000..b87fb8d9fb6 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fcmpund.cgs @@ -0,0 +1,26 @@ +# sh testcase for fcmpun.d $drg, $drh, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +fcmpund: + movi 0, r0 + movi 1, r1 + fmov.qd r0, dr0 + float.qd dr0, dr0 + fmov.qd r1, dr2 + float.qd dr2, dr2 + fcmpun.d dr0, dr2, r7 + bnei r7, 0, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fcmpuns.cgs b/sim/testsuite/sim/sh64/media/fcmpuns.cgs new file mode 100644 index 00000000000..6c2ed96b4a3 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fcmpuns.cgs @@ -0,0 +1,26 @@ +# sh testcase for fcmpun.s $frg, $frh, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +fcmpuns: + movi 0, r0 + movi 1, r1 + fmov.ls r0, fr0 + float.ls fr0, fr0 + fmov.ls r1, fr1 + float.ls fr1, fr1 + fcmpun.s fr0, fr1, r7 + bnei r7, 0, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fcnvds.cgs b/sim/testsuite/sim/sh64/media/fcnvds.cgs new file mode 100644 index 00000000000..aa6c993fb85 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fcnvds.cgs @@ -0,0 +1,27 @@ +# sh testcase for fcnv.ds $drgh, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +fcnvds: + movi 9, r0 + fmov.qd r0, dr0 + float.qd dr0, dr0 + fcnv.ds dr0, fr3 + movi 9, r0 + fmov.ls r0, fr4 + float.ls fr4, fr4 + fcmpeq.s fr3, fr4, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fcnvsd.cgs b/sim/testsuite/sim/sh64/media/fcnvsd.cgs new file mode 100644 index 00000000000..6c2396fe815 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fcnvsd.cgs @@ -0,0 +1,27 @@ +# sh testcase for fcnv.sd $frgh, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +fcnvsd: + movi 9, r0 + fmov.ls r0, fr0 + float.ls fr0, fr0 + fcnv.sd fr0, dr2 + movi 9, r0 + fmov.qd r0, dr4 + float.qd dr4, dr4 + fcmpeq.d dr2, dr4, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fdivd.cgs b/sim/testsuite/sim/sh64/media/fdivd.cgs new file mode 100644 index 00000000000..62401c6b47e --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fdivd.cgs @@ -0,0 +1,39 @@ +# sh testcase for fdiv.d $drg, $drh, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +fdivd1: + movi 1, r0 + fmov.qd r0, dr0 + float.qd dr0, dr0 + movi 2, r1 + fmov.qd r1, dr2 + float.qd dr2, dr2 + fdiv.d dr0, dr2, dr4 + +fdvid2: + movi 6, r0 + fmov.qd r0, dr0 + float.qd dr0, dr0 + movi 2, r1 + fmov.qd r1, dr2 + float.qd dr2, dr2 + fdiv.d dr0, dr2, dr4 + movi 3, r3 + fmov.qd r3, dr6 + float.qd dr6, dr6 + fcmpeq.d dr4, dr6, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fdivs.cgs b/sim/testsuite/sim/sh64/media/fdivs.cgs new file mode 100644 index 00000000000..9b20f686b92 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fdivs.cgs @@ -0,0 +1,39 @@ +# sh testcase for fdiv.s $frg, $frh, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +fdivs1: + movi 1, r0 + fmov.ls r0, fr0 + float.ls fr0, fr0 + movi 2, r1 + fmov.ls r1, fr1 + float.ls fr1, fr1 + fdiv.s fr0, fr1, fr2 + +fdvis2: + movi 6, r0 + fmov.ls r0, fr0 + float.ls fr0, fr0 + movi 2, r1 + fmov.ls r1, fr1 + float.ls fr1, fr1 + fdiv.s fr0, fr1, fr2 + movi 3, r3 + fmov.ls r3, fr3 + float.ls fr3, fr3 + fcmpeq.s fr2, fr3, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fgetscr.cgs b/sim/testsuite/sim/sh64/media/fgetscr.cgs new file mode 100644 index 00000000000..6aa227480ce --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fgetscr.cgs @@ -0,0 +1,14 @@ +# sh testcase for fgetscr $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global fgetscr +fgetscr: + fgetscr fr0 + + pass diff --git a/sim/testsuite/sim/sh64/media/fiprs.cgs b/sim/testsuite/sim/sh64/media/fiprs.cgs new file mode 100644 index 00000000000..fef62d11c7c --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fiprs.cgs @@ -0,0 +1,42 @@ +# sh testcase for fipr.s $fvg, $fvh, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + .macro _load val, fpreg + # This macro clobbers r0. + movi \val, r0 + fmov.ls r0, \fpreg + float.ls \fpreg, \fpreg + .endm + + start + + .global fiprs +init: + pta wrong, tr0 + + _load 1, fr0 + _load 2, fr1 + _load 3, fr2 + _load 4, fr3 + _load 1, fr4 + _load 2, fr5 + _load 3, fr6 + _load 4, fr7 + +fiprs: + fipr.s fv0, fv4, fr9 + +check: + _load 30, fr10 + fcmpeq.s fr9, fr10, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fldd.cgs b/sim/testsuite/sim/sh64/media/fldd.cgs new file mode 100644 index 00000000000..ded2a9fe8f5 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fldd.cgs @@ -0,0 +1,13 @@ +# sh testcase for fld.d $rm, $disp10x8, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + movi 0x2800, r0 + fld.d r0, 0, dr0 + fld.d r0, 8, dr0 + fld.d r0, -8, dr0 + pass diff --git a/sim/testsuite/sim/sh64/media/fldp.cgs b/sim/testsuite/sim/sh64/media/fldp.cgs new file mode 100644 index 00000000000..8727110378c --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fldp.cgs @@ -0,0 +1,16 @@ +# sh testcase for fld.p $rm, $disp10x8, $fpf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + movi 0x2800, r0 + +fldp: + fld.p r0, 0, fp0 + fld.p r0, 8, fp2 + fld.p r0, -8, fp4 + pass diff --git a/sim/testsuite/sim/sh64/media/flds.cgs b/sim/testsuite/sim/sh64/media/flds.cgs new file mode 100644 index 00000000000..75d5e961e26 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/flds.cgs @@ -0,0 +1,13 @@ +# sh testcase for fld.s $rm, $disp10x4, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + movi 0x2800, r0 + fld.s r0, 0, fr0 + fld.s r0, 4, fr0 + fld.s r0, -4, fr0 + pass diff --git a/sim/testsuite/sim/sh64/media/fldxd.cgs b/sim/testsuite/sim/sh64/media/fldxd.cgs new file mode 100644 index 00000000000..63cb56bb06f --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fldxd.cgs @@ -0,0 +1,16 @@ +# sh testcase for fldx.d $rm, $rn, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + movi 0x2800, r0 + movi 0, r1 + fldx.d r0, r1, dr0 + movi 8, r1 + fldx.d r0, r1, dr0 + movi -8, r1 + fldx.d r0, r1, dr0 + pass diff --git a/sim/testsuite/sim/sh64/media/fldxp.cgs b/sim/testsuite/sim/sh64/media/fldxp.cgs new file mode 100644 index 00000000000..3d929c6fef8 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fldxp.cgs @@ -0,0 +1,22 @@ +# sh testcase for fldx.p $rm, $rn, $fpf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + movi 0x2800, r0 + +fldxp: + movi 0, r1 + fldx.p r0, r1, fp0 + + movi 8, r1 + fldx.p r0, r1, fp2 + + movi -8, r1 + fldx.p r0, r1, fp4 + + pass diff --git a/sim/testsuite/sim/sh64/media/fldxs.cgs b/sim/testsuite/sim/sh64/media/fldxs.cgs new file mode 100644 index 00000000000..10feb3e54a9 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fldxs.cgs @@ -0,0 +1,16 @@ +# sh testcase for fldx.s $rm, $rn, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + movi 0x2800, r0 + movi 0, r1 + fldx.s r0, r1, fr0 + movi 4, r1 + fldx.s r0, r1, fr0 + movi -4, r1 + fldx.s r0, r1, fr0 + pass diff --git a/sim/testsuite/sim/sh64/media/floatld.cgs b/sim/testsuite/sim/sh64/media/floatld.cgs new file mode 100644 index 00000000000..31f6111061b --- /dev/null +++ b/sim/testsuite/sim/sh64/media/floatld.cgs @@ -0,0 +1,12 @@ +# sh testcase for float.ld $frgh, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + movi 1, r0 + fmov.ls r0, fr0 + float.ld fr0, dr0 + pass diff --git a/sim/testsuite/sim/sh64/media/floatls.cgs b/sim/testsuite/sim/sh64/media/floatls.cgs new file mode 100644 index 00000000000..4c8fb992798 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/floatls.cgs @@ -0,0 +1,12 @@ +# sh testcase for float.ls $frgh, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + movi 1, r0 + fmov.ls r0, fr0 + float.ls fr0, fr0 + pass diff --git a/sim/testsuite/sim/sh64/media/floatqd.cgs b/sim/testsuite/sim/sh64/media/floatqd.cgs new file mode 100644 index 00000000000..ea5ddd9e49a --- /dev/null +++ b/sim/testsuite/sim/sh64/media/floatqd.cgs @@ -0,0 +1,12 @@ +# sh testcase for float.qd $drgh, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + movi 1, r0 + fmov.qd r0, dr0 + float.qd dr0, dr2 + pass diff --git a/sim/testsuite/sim/sh64/media/floatqs.cgs b/sim/testsuite/sim/sh64/media/floatqs.cgs new file mode 100644 index 00000000000..fcf35e29548 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/floatqs.cgs @@ -0,0 +1,12 @@ +# sh testcase for float.qs $drgh, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + movi 1, r0 + fmov.qd r0, dr0 + float.qs dr0, fr1 + pass diff --git a/sim/testsuite/sim/sh64/media/fmacs.cgs b/sim/testsuite/sim/sh64/media/fmacs.cgs new file mode 100644 index 00000000000..62219c5fafd --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fmacs.cgs @@ -0,0 +1,39 @@ +# sh testcase for fmac.s $frg, $frh, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +fmacs: + movi 2, r0 + fmov.ls r0, fr0 + float.ls fr0, fr0 + + movi 3, r1 + fmov.ls r1, fr1 + float.ls fr1, fr1 + + movi 4, r2 + fmov.ls r2, fr2 + float.ls fr2, fr2 + + fmac.s fr0, fr1, fr2 + + movi 10, r3 + fmov.ls r3, fr3 + float.ls fr3, fr3 + + fcmpeq.s fr2, fr3, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fmovd.cgs b/sim/testsuite/sim/sh64/media/fmovd.cgs new file mode 100644 index 00000000000..03c05ad1776 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fmovd.cgs @@ -0,0 +1,24 @@ +# sh testcase for fmov.d $drgh, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +fmovd: + movi 4, r0 + fmov.qd r0, dr0 + float.qd dr0, dr2 + fmov.d dr2, dr4 + fcmpeq.d dr2, dr4, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fmovdq.cgs b/sim/testsuite/sim/sh64/media/fmovdq.cgs new file mode 100644 index 00000000000..ff5c3fe9302 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fmovdq.cgs @@ -0,0 +1,23 @@ +# sh testcase for fmov.dq $drgh, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +fmovdq: + movi 4, r0 + fmov.qd r0, dr0 + fmov.dq dr0, r1 + bne r0, r1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fmovls.cgs b/sim/testsuite/sim/sh64/media/fmovls.cgs new file mode 100644 index 00000000000..850ec33d160 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fmovls.cgs @@ -0,0 +1,26 @@ +# sh testcase for fmov.ls $rm, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +fmovls0: + movi 0, r0 + fmov.ls r0, fr0 + +fmovls1: + movi 1, r1 + fmov.ls r1, fr1 + +upper: + movi 1, r2 + shlli r2, 63, r2 + ori r2, 3, r2 + # Bit 63 should be ignored. + fmov.ls r2, fr2 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/fmovqd.cgs b/sim/testsuite/sim/sh64/media/fmovqd.cgs new file mode 100644 index 00000000000..64eac72b3df --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fmovqd.cgs @@ -0,0 +1,22 @@ +# sh testcase for fmov.qd $rm, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +fmovdq: + movi 4, r0 + fmov.qd r0, dr0 + fmov.dq dr0, r1 + bne r0, r1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fmovs.cgs b/sim/testsuite/sim/sh64/media/fmovs.cgs new file mode 100644 index 00000000000..f126aa5a41c --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fmovs.cgs @@ -0,0 +1,24 @@ +# sh testcase for fmov.s $frgh, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +fmovs: + movi 8, r0 + fmov.ls r0, fr7 + float.ls fr7, fr0 + fmov.s fr0, fr1 + fcmpeq.s fr0, fr1, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fmovsl.cgs b/sim/testsuite/sim/sh64/media/fmovsl.cgs new file mode 100644 index 00000000000..7dfdab1d145 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fmovsl.cgs @@ -0,0 +1,21 @@ +# sh testcase for fmov.sl $frgh, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +fmovsl: + pta wrong, tr0 + movi 9, r0 + fmov.ls r0, fr0 + fmov.sl fr0, r1 + bne r0, r1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fmuld.cgs b/sim/testsuite/sim/sh64/media/fmuld.cgs new file mode 100644 index 00000000000..2ad67cdc532 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fmuld.cgs @@ -0,0 +1,30 @@ +# sh testcase for fmul.d $drg, $drh, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +fmuld1: + movi 2, r0 + fmov.qd r0, dr0 + float.qd dr0, dr0 + movi 3, r1 + fmov.qd r1, dr2 + float.qd dr2, dr2 + fmul.d dr0, dr2, dr4 + movi 6, r2 + fmov.qd r2, dr6 + float.qd dr6, dr6 + fcmpeq.d dr4, dr6, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fmuls.cgs b/sim/testsuite/sim/sh64/media/fmuls.cgs new file mode 100644 index 00000000000..4b8875f0c59 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fmuls.cgs @@ -0,0 +1,31 @@ +# sh testcase for fmul.s $frg, $frh, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +fmuls1: + movi 2, r0 + fmov.ls r0, fr0 + float.ls fr0, fr0 + movi 3, r1 + fmov.ls r1, fr1 + float.ls fr1, fr1 + fmul.s fr0, fr1, fr2 + movi 6, r2 + fmov.ls r2, fr3 + float.ls fr3, fr3 + fcmpeq.s fr2, fr3, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fnegd.cgs b/sim/testsuite/sim/sh64/media/fnegd.cgs new file mode 100644 index 00000000000..67b381345b6 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fnegd.cgs @@ -0,0 +1,35 @@ +# sh testcase for fneg.d $drgh, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + movi 0, r0 + movi 1, r1 + +fnegd0: + # Ensure fnegd(0) = 0. + fmov.ls r0, fr7 + float.ld fr7, dr0 + fneg.d dr0, dr2 + fcmpeq.d dr0, dr2, r7 + bnei r7, 1, tr0 + +fnegd1: + # Ensure fnegd(fnegd(1)) = 1. + fmov.ls r1, fr7 + float.ld fr7, dr0 + fneg.d dr0, dr2 + fneg.d dr2, dr4 + fcmpeq.d dr0, dr4, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fnegs.cgs b/sim/testsuite/sim/sh64/media/fnegs.cgs new file mode 100644 index 00000000000..9ad625a1f1f --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fnegs.cgs @@ -0,0 +1,35 @@ +# sh testcase for fneg.s $frgh, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + movi 0, r0 + movi 1, r1 + +fnegs0: + # Ensure fnegs(0) = 0. + fmov.ls r0, fr7 + float.ls fr7, fr0 + fneg.s fr0, fr1 + fcmpeq.s fr0, fr1, r7 + bnei r7, 1, tr0 + +fnegs1: + # Ensure fnegs(fnegs(1)) = 1. + fmov.ls r1, fr7 + float.ls fr7, fr0 + fneg.s fr0, fr1 + fneg.s fr1, fr2 + fcmpeq.s fr0, fr2, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fputscr.cgs b/sim/testsuite/sim/sh64/media/fputscr.cgs new file mode 100644 index 00000000000..28d2e7230ee --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fputscr.cgs @@ -0,0 +1,14 @@ +# sh testcase for fputscr $frgh -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global fputscr +fputscr: + fputscr fr0 + + pass diff --git a/sim/testsuite/sim/sh64/media/fsqrtd.cgs b/sim/testsuite/sim/sh64/media/fsqrtd.cgs new file mode 100644 index 00000000000..ae6120002e0 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fsqrtd.cgs @@ -0,0 +1,27 @@ +# sh testcase for fsqrt.d $frgh, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + movi 9, r0 + fmov.ls r0, fr7 + float.ld fr7, dr0 + movi 3, r1 + fmov.ls r1, fr7 + float.ld fr7, dr2 + +fsqrtd: + fsqrt.d dr0, dr4 + fcmpeq.d dr2, dr4, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fsqrts.cgs b/sim/testsuite/sim/sh64/media/fsqrts.cgs new file mode 100644 index 00000000000..f1183933159 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fsqrts.cgs @@ -0,0 +1,27 @@ +# sh testcase for fsqrt.s $frgh, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + movi 9, r0 + fmov.ls r0, fr7 + float.ls fr7, fr0 + movi 3, r1 + fmov.ls r1, fr7 + float.ls fr7, fr2 + +fsqrts: + fsqrt.s fr0, fr1 + fcmpeq.s fr1, fr2, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fstd.cgs b/sim/testsuite/sim/sh64/media/fstd.cgs new file mode 100644 index 00000000000..16ab5b6672c --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fstd.cgs @@ -0,0 +1,34 @@ +# sh testcase for fst.d $rm, $disp10x8, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global fstd +fstd: + movi 0x1020, r0 + shlli r0, 8, r0 + ori r0, 0x30, r0 + shlli r0, 8, r0 + ori r0, 0x40, r0 + shlli r0, 8, r0 + ori r0, 0x50, r0 + shlli r0, 8, r0 + ori r0, 0x60, r0 + shlli r0, 8, r0 + ori r0, 0x70, r0 + shlli r0, 8, r0 + ori r0, 0x80, r0 + # Set target address. + movi 0x2800, r1 + fmov.qd r0, dr0 + + fst.d r1, 0, dr0 + fst.d r1, 8, dr0 + fst.d r1, -8, dr0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/fstp.cgs b/sim/testsuite/sim/sh64/media/fstp.cgs new file mode 100644 index 00000000000..e0c396ac59a --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fstp.cgs @@ -0,0 +1,14 @@ +# sh testcase for fst.p $rm, $disp10x8, $fpf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global fstp +fstp: + fst.p r0, 0, fp0 + + pass diff --git a/sim/testsuite/sim/sh64/media/fsts.cgs b/sim/testsuite/sim/sh64/media/fsts.cgs new file mode 100644 index 00000000000..fb692cf274c --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fsts.cgs @@ -0,0 +1,34 @@ +# sh testcase for fst.s $rm, $disp10x4, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global fsts +fsts: + movi 0x1020, r0 + shlli r0, 8, r0 + ori r0, 0x30, r0 + shlli r0, 8, r0 + ori r0, 0x40, r0 + shlli r0, 8, r0 + ori r0, 0x50, r0 + shlli r0, 8, r0 + ori r0, 0x60, r0 + shlli r0, 8, r0 + ori r0, 0x70, r0 + shlli r0, 8, r0 + ori r0, 0x80, r0 + # Set target address. + movi 0x2800, r1 + fmov.ls r0, fr0 + + fst.s r1, 0, fr0 + fst.s r1, 4, fr0 + fst.s r1, -4, fr0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/fstxd.cgs b/sim/testsuite/sim/sh64/media/fstxd.cgs new file mode 100644 index 00000000000..10f6c1436b5 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fstxd.cgs @@ -0,0 +1,31 @@ +# sh testcase for fstx.d $rm, $rn, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global fstxd +fstxd: + movi 0x1020, r0 + shlli r0, 8, r0 + ori r0, 0x30, r0 + shlli r0, 8, r0 + ori r0, 0x40, r0 + shlli r0, 8, r0 + ori r0, 0x50, r0 + shlli r0, 8, r0 + ori r0, 0x60, r0 + shlli r0, 8, r0 + ori r0, 0x70, r0 + shlli r0, 8, r0 + ori r0, 0x80, r0 + fmov.qd r0, dr0 + movi 0x2800, r1 + movi -8, r2 + fstx.d r1, r2, dr0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/fstxp.cgs b/sim/testsuite/sim/sh64/media/fstxp.cgs new file mode 100644 index 00000000000..1829f58eb25 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fstxp.cgs @@ -0,0 +1,14 @@ +# sh testcase for fstx.p $rm, $rn, $fpf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global fstxp +fstxp: + fstx.p r0, r0, fp0 + + pass diff --git a/sim/testsuite/sim/sh64/media/fstxs.cgs b/sim/testsuite/sim/sh64/media/fstxs.cgs new file mode 100644 index 00000000000..0b4ff96dba9 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fstxs.cgs @@ -0,0 +1,30 @@ +# sh testcase for fstx.s $rm, $rn, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + .global fstxs +fstxs: + movi 0x1020, r0 + shlli r0, 8, r0 + ori r0, 0x30, r0 + shlli r0, 8, r0 + ori r0, 0x40, r0 + shlli r0, 8, r0 + ori r0, 0x50, r0 + shlli r0, 8, r0 + ori r0, 0x60, r0 + shlli r0, 8, r0 + ori r0, 0x70, r0 + shlli r0, 8, r0 + ori r0, 0x80, r0 + fmov.ls r0, fr0 + movi 0x2800, r1 + movi -8, r2 + fstx.s r1, r2, fr0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/fsubd.cgs b/sim/testsuite/sim/sh64/media/fsubd.cgs new file mode 100644 index 00000000000..93dc421b01f --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fsubd.cgs @@ -0,0 +1,36 @@ +# sh testcase for fsub.d $drg, $drh, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global fsubd +init: + pta wrong, tr0 + +fsubd: + movi 9, r0 + fmov.qd r0, dr0 + float.qd dr0, dr0 + + movi 3, r0 + fmov.qd r0, dr2 + float.qd dr2, dr2 + + fsub.d dr0, dr2, dr4 + + movi 6, r0 + fmov.qd r0, dr6 + float.qd dr6, dr6 + + fcmpeq.d dr4, dr6, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/fsubs.cgs b/sim/testsuite/sim/sh64/media/fsubs.cgs new file mode 100644 index 00000000000..b009f094054 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/fsubs.cgs @@ -0,0 +1,36 @@ +# sh testcase for fsub.s $frg, $frh, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global fsubs +init: + pta wrong, tr0 + +fsubs: + movi 9, r0 + fmov.ls r0, fr0 + float.ls fr0, fr0 + + movi 3, r0 + fmov.ls r0, fr1 + float.ls fr1, fr1 + + fsub.s fr0, fr1, fr2 + + movi 6, r0 + fmov.ls r0, fr3 + float.ls fr3, fr3 + + fcmpeq.s fr2, fr3, r7 + bnei r7, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/ftrcdl.cgs b/sim/testsuite/sim/sh64/media/ftrcdl.cgs new file mode 100644 index 00000000000..3aafb83dca3 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ftrcdl.cgs @@ -0,0 +1,26 @@ +# sh testcase for ftrc.dl $drgh, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global ftrcdl +init: + pta wrong, tr0 + +ftrcdl: + movi -9, r0 + fmov.qd r0, dr0 + float.qd dr0, dr0 + ftrc.dl dr0, fr0 + fmov.sl fr0, r1 + bne r0, r1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/ftrcdq.cgs b/sim/testsuite/sim/sh64/media/ftrcdq.cgs new file mode 100644 index 00000000000..6cd63fb029e --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ftrcdq.cgs @@ -0,0 +1,24 @@ +# sh testcase for ftrc.dq $drgh, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +ftrcdq: + movi -9, r0 + fmov.qd r0, dr0 + float.qd dr0, dr0 + ftrc.dq dr0, dr2 + fmov.dq dr2, r1 + bne r0, r1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/ftrcsl.cgs b/sim/testsuite/sim/sh64/media/ftrcsl.cgs new file mode 100644 index 00000000000..9fd7faebd1a --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ftrcsl.cgs @@ -0,0 +1,26 @@ +# sh testcase for ftrc.sl $frgh, $frf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global ftrcsl +init: + pta wrong, tr0 + +ftrcsl: + movi -9, r0 + fmov.ls r0, fr0 + float.ls fr0, fr0 + ftrc.sl fr0, fr1 + fmov.sl fr1, r1 + bne r0, r1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/ftrcsq.cgs b/sim/testsuite/sim/sh64/media/ftrcsq.cgs new file mode 100644 index 00000000000..8f19d595e10 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ftrcsq.cgs @@ -0,0 +1,25 @@ +# sh testcase for ftrc.sq $frgh, $drf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +ftrcsq: + movi -9, r0 + fmov.ls r0, fr0 + float.ls fr0, fr0 + ftrc.sq fr0, dr2 + fmov.dq dr2, r1 + bne r0, r1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/ftrvs.cgs b/sim/testsuite/sim/sh64/media/ftrvs.cgs new file mode 100644 index 00000000000..be7a75ad885 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ftrvs.cgs @@ -0,0 +1,67 @@ +# sh testcase for ftrv.s $mtrxg, $fvh, $fvf -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + .macro _load val, fpreg + # This macro clobbers r0. + movi \val, r0 + fmov.ls r0, \fpreg + float.ls \fpreg, \fpreg + .endm + + start + +init: + pta wrong, tr0 + + _load 1, fr0 + _load 2, fr4 + _load 3, fr8 + _load 4, fr12 + _load 5, fr1 + _load 6, fr5 + _load 7, fr9 + _load 8, fr13 + _load 9, fr2 + _load 10, fr6 + _load 11, fr10 + _load 12, fr14 + _load 13, fr3 + _load 14, fr7 + _load 15, fr11 + _load 16, fr15 + + _load 1, fr16 + _load 2, fr17 + _load 3, fr18 + _load 4, fr19 + +ftrvs: + ftrv.s mtrx0, fv16, fv20 + +check: + _load 30, fr0 + _load 70, fr1 + _load 110, fr2 + _load 150, fr3 + + fcmpeq.s fr0, fr20, r0 + bnei r0, 1, tr0 + + fcmpeq.s fr1, fr21, r0 + bnei r0, 1, tr0 + + fcmpeq.s fr2, fr22, r0 + bnei r0, 1, tr0 + + fcmpeq.s fr3, fr23, r0 + bnei r0, 1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/getcfg.cgs b/sim/testsuite/sim/sh64/media/getcfg.cgs new file mode 100644 index 00000000000..d151739846e --- /dev/null +++ b/sim/testsuite/sim/sh64/media/getcfg.cgs @@ -0,0 +1,10 @@ +# sh testcase for getcfg $rm, $disp6, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + getcfg r0, 0, r0 + pass diff --git a/sim/testsuite/sim/sh64/media/getcon.cgs b/sim/testsuite/sim/sh64/media/getcon.cgs new file mode 100644 index 00000000000..8eeb43cd5b0 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/getcon.cgs @@ -0,0 +1,29 @@ +# sh testcase for getcon $crk, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +getcon1: + movi 22, r0 + putcon r0, cr0 + getcon cr0, r1 + bne r0, r1, tr0 + +getcon2: + movi 12, r0 + shlli r0, 35, r0 + putcon r0, cr20 + getcon cr20, r20 + bne r0, r20, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/gettr.cgs b/sim/testsuite/sim/sh64/media/gettr.cgs new file mode 100644 index 00000000000..8840a361bb0 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/gettr.cgs @@ -0,0 +1,48 @@ +# sh testcase for gettr $trb, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + # tr0 is reserved. + # don't use it anywhere else in this test. + pta wrong, tr0 + +gettr1: + # Put garbage in r1, r2. + movi 20, r1 + movi 30, r2 + + pta foo, tr1 + pta foo, tr2 + +check1: + gettr tr1, r1 + gettr tr2, r2 + bne r1, r2, tr0 + +gettr2: + # Put garbage in r3, r4. + movi 21, r3 + movi 42, r4 + +check2: + pta foo, tr1 + gettr tr1, r2 + ptabs r2, tr2 + gettr tr2, r3 + ptabs r3, tr3 + gettr tr3, r4 + bne r2, r4, tr0 + +okay: + pass + +wrong: + fail + +foo: + nop diff --git a/sim/testsuite/sim/sh64/media/icbi.cgs b/sim/testsuite/sim/sh64/media/icbi.cgs new file mode 100644 index 00000000000..9ba18452ef6 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/icbi.cgs @@ -0,0 +1,10 @@ +# sh testcase for icbi $rm, $disp6x32 -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + icbi r0, 0 + pass diff --git a/sim/testsuite/sim/sh64/media/ldb.cgs b/sim/testsuite/sim/sh64/media/ldb.cgs new file mode 100644 index 00000000000..fad1e6e15ee --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ldb.cgs @@ -0,0 +1,21 @@ +# sh testcase for ld.b $rm, $disp10, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + movi 20, r3 + shlli r3, 8, r3 + +ldb1: + ld.b r3, 0, r0 +ldb2: + ld.b r3, -1, r0 +ldb3: + ld.b r3, 1, r0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/ldhil.cgs b/sim/testsuite/sim/sh64/media/ldhil.cgs new file mode 100644 index 00000000000..4323985ea49 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ldhil.cgs @@ -0,0 +1,14 @@ +# sh testcase for ldhi.l $rm, $disp6, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global ldhil +ldhil: + ldhi.l r0, 0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/ldhiq.cgs b/sim/testsuite/sim/sh64/media/ldhiq.cgs new file mode 100644 index 00000000000..c34a952bba7 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ldhiq.cgs @@ -0,0 +1,14 @@ +# sh testcase for ldhi.q $rm, $disp6, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global ldhiq +ldhiq: + ldhi.q r0, 0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/ldl.cgs b/sim/testsuite/sim/sh64/media/ldl.cgs new file mode 100644 index 00000000000..b8b8725dee1 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ldl.cgs @@ -0,0 +1,21 @@ +# sh testcase for ld.l $rm, $disp10x4, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + movi 20, r3 + shlli r3, 8, r3 + +ldl1: + ld.l r3, 0, r0 +ldl2: + ld.l r3, -4, r0 +ldl3: + ld.l r3, 4, r0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/ldlol.cgs b/sim/testsuite/sim/sh64/media/ldlol.cgs new file mode 100644 index 00000000000..8204f40ebf4 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ldlol.cgs @@ -0,0 +1,14 @@ +# sh testcase for ldlo.l $rm, $disp6, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global ldlol +ldlol: + ldlo.l r0, 0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/ldloq.cgs b/sim/testsuite/sim/sh64/media/ldloq.cgs new file mode 100644 index 00000000000..0cf128e2013 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ldloq.cgs @@ -0,0 +1,14 @@ +# sh testcase for ldlo.q $rm, $disp6, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global ldloq +ldloq: + ldlo.q r0, 0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/ldq.cgs b/sim/testsuite/sim/sh64/media/ldq.cgs new file mode 100644 index 00000000000..cacc076bb90 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ldq.cgs @@ -0,0 +1,21 @@ +# sh testcase for ld.q $rm, $disp10x8, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + movi 20, r3 + shlli r3, 8, r3 + +ldl1: + ld.q r3, 0, r0 +ldl2: + ld.q r3, -8, r0 +ldl3: + ld.q r3, 8, r0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/ldub.cgs b/sim/testsuite/sim/sh64/media/ldub.cgs new file mode 100644 index 00000000000..825ce642e31 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ldub.cgs @@ -0,0 +1,22 @@ +# sh testcase for ld.ub $rm, $disp10, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + movi 20, r3 + shlli r3, 8, r3 + +ldub1: + ld.ub r3, 0, r0 +ldub2: + ld.ub r3, -1, r0 +ldub3: + ld.ub r3, 1, r0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/lduw.cgs b/sim/testsuite/sim/sh64/media/lduw.cgs new file mode 100644 index 00000000000..a329802e22b --- /dev/null +++ b/sim/testsuite/sim/sh64/media/lduw.cgs @@ -0,0 +1,22 @@ +# sh testcase for ld.uw $rm, $disp10, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + movi 20, r3 + shlli r3, 8, r3 + +lduw1: + ld.uw r3, 0, r0 +lduw2: + ld.uw r3, -2, r0 +lduw3: + ld.uw r3, 2, r0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/ldw.cgs b/sim/testsuite/sim/sh64/media/ldw.cgs new file mode 100644 index 00000000000..d39405515a9 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ldw.cgs @@ -0,0 +1,21 @@ +# sh testcase for ld.w $rm, $disp10, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + movi 20, r3 + shlli r3, 8, r3 + +ldw1: + ld.w r3, 0, r0 +ldw2: + ld.w r3, -2, r0 +ldw3: + ld.w r3, 2, r0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/ldxb.cgs b/sim/testsuite/sim/sh64/media/ldxb.cgs new file mode 100644 index 00000000000..36038df8da4 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ldxb.cgs @@ -0,0 +1,28 @@ +# sh testcase for ldx.b $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +ldxb1: + movi 20, r3 + shlli r3, 8, r3 + movi 0, r4 + ldx.b r3, r4, r0 + +ldxb2: + movi 20, r3 + shlli r3, 8, r3 + movi 1, r4 + ldx.b r3, r4, r0 + +ldxb3: + movi 20, r3 + shlli r3, 8, r3 + movi -1, r4 + ldx.b r3, r4, r0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/ldxl.cgs b/sim/testsuite/sim/sh64/media/ldxl.cgs new file mode 100644 index 00000000000..0596e9f325b --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ldxl.cgs @@ -0,0 +1,28 @@ +# sh testcase for ldx.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +ldxl1: + movi 20, r3 + shlli r3, 8, r3 + movi 0, r4 + ldx.l r3, r4, r0 + +ldxl2: + movi 20, r3 + shlli r3, 8, r3 + movi 4, r4 + ldx.l r3, r4, r0 + +ldxl3: + movi 20, r3 + shlli r3, 8, r3 + movi -4, r4 + ldx.l r3, r4, r0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/ldxq.cgs b/sim/testsuite/sim/sh64/media/ldxq.cgs new file mode 100644 index 00000000000..1247f220562 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ldxq.cgs @@ -0,0 +1,28 @@ +# sh testcase for ldx.q $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +ldxq1: + movi 20, r3 + shlli r3, 8, r3 + movi 0, r4 + ldx.q r3, r4, r0 + +ldxq2: + movi 20, r3 + shlli r3, 8, r3 + movi 8, r4 + ldx.q r3, r4, r0 + +ldxq3: + movi 20, r3 + shlli r3, 8, r3 + movi -8, r4 + ldx.q r3, r4, r0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/ldxub.cgs b/sim/testsuite/sim/sh64/media/ldxub.cgs new file mode 100644 index 00000000000..e863a3bfccf --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ldxub.cgs @@ -0,0 +1,28 @@ +# sh testcase for ldx.ub $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +ldxub1: + movi 20, r3 + shlli r3, 8, r3 + movi 0, r4 + ldx.ub r3, r4, r0 + +ldxub2: + movi 20, r3 + shlli r3, 8, r3 + movi 1, r4 + ldx.ub r3, r4, r0 + +ldxub3: + movi 20, r3 + shlli r3, 8, r3 + movi -1, r4 + ldx.ub r3, r4, r0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/ldxuw.cgs b/sim/testsuite/sim/sh64/media/ldxuw.cgs new file mode 100644 index 00000000000..282812db895 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ldxuw.cgs @@ -0,0 +1,29 @@ +# sh testcase for ldx.uw $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +ldxuw1: + movi 20, r3 + shlli r3, 8, r3 + movi 0, r4 + ldx.uw r3, r4, r0 + +ldxuw2: + movi 20, r3 + shlli r3, 8, r3 + movi 2, r4 + ldx.uw r3, r4, r0 + +ldxuw3: + movi 20, r3 + shlli r3, 8, r3 + movi -2, r4 + ldx.uw r3, r4, r0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/ldxw.cgs b/sim/testsuite/sim/sh64/media/ldxw.cgs new file mode 100644 index 00000000000..d377fef6177 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ldxw.cgs @@ -0,0 +1,29 @@ +# sh testcase for ldx.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +ldxw1: + movi 20, r3 + shlli r3, 8, r3 + movi 0, r4 + ldx.w r3, r4, r0 + +ldxw2: + movi 20, r3 + shlli r3, 8, r3 + movi 2, r4 + ldx.w r3, r4, r0 + +ldxw3: + movi 20, r3 + shlli r3, 8, r3 + movi -2, r4 + ldx.w r3, r4, r0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/mabsl.cgs b/sim/testsuite/sim/sh64/media/mabsl.cgs new file mode 100644 index 00000000000..a8af663ea12 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mabsl.cgs @@ -0,0 +1,39 @@ +# sh testcase for mabs.l $rm, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mabsl +init: + pta wrong, tr0 + +mabsl1: + # Pack { 1 3 } into R0. + _packl 1, 3, r0 + + mabs.l r0, r1 + + # Test for { 1 3 } in R0. + _packl 1, 3, r2 + bne r0, r2, tr0 + +mabsl2: + # Pack { -1, -1 } into R0. + _packl 1, 1, r0 + + # Set the left sign bit. + movi 1, r1 + shlli r1, 63, r1 + or r0, r1, r0 + + mabs.l r0, r2 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/mabsw.cgs b/sim/testsuite/sim/sh64/media/mabsw.cgs new file mode 100644 index 00000000000..f4e980a19c6 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mabsw.cgs @@ -0,0 +1,38 @@ +# sh testcase for mabs.w $rm, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +mabsw1: + # Pack { 1 3 5 7 } into R0. + _packw 1, 3, 5, 7, r0 + + mabs.l r0, r1 + + # Test for { 1 3 5 7 } in R0. + _packw 1, 3, 5, 7, r2 + bne r0, r2, tr0 + +mabsw2: + # Pack { -1, -1, -1, -1 } into R0. + _packw 1, 1, 1, 1, r0 + + # Set the left sign bit + movi 1, r1 + shlli r1, 63, r1 + or r0, r1, r0 + + mabs.w r0, r2 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/maddl.cgs b/sim/testsuite/sim/sh64/media/maddl.cgs new file mode 100644 index 00000000000..4bdf5463866 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/maddl.cgs @@ -0,0 +1,29 @@ +# sh testcase for madd.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +maddl: + # Load { 1 2 } into r0. + _packl 1, 2, r0 + # Load { 3 4 } into r1. + _packl 3, 4, r1 + + # Add slices to produce { 4 6 }. + madd.l r0, r1, r2 + + _packl 4, 6, r3 + bne r2, r3, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/maddsl.cgs b/sim/testsuite/sim/sh64/media/maddsl.cgs new file mode 100644 index 00000000000..3977275dc89 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/maddsl.cgs @@ -0,0 +1,14 @@ +# sh testcase for madds.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global maddsl +maddsl: + madds.l r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/maddsub.cgs b/sim/testsuite/sim/sh64/media/maddsub.cgs new file mode 100644 index 00000000000..a55f927a3e1 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/maddsub.cgs @@ -0,0 +1,14 @@ +# sh testcase for madds.ub $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global maddsub +maddsub: + madds.ub r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/maddsw.cgs b/sim/testsuite/sim/sh64/media/maddsw.cgs new file mode 100644 index 00000000000..45a774ed2fc --- /dev/null +++ b/sim/testsuite/sim/sh64/media/maddsw.cgs @@ -0,0 +1,14 @@ +# sh testcase for madds.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global maddsw +maddsw: + madds.w r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/maddw.cgs b/sim/testsuite/sim/sh64/media/maddw.cgs new file mode 100644 index 00000000000..b220ef4aee6 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/maddw.cgs @@ -0,0 +1,29 @@ +# sh testcase for madd.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +maddw: + # Load { 1 2 3 4 } into R0. + _packw 1, 2, 3, 4, r0 + + # Load { 3 4 5 6 } into R1. + _packw 3, 4, 5, 6, r1 + + # Add slices to produce { 4 6 8 10 }. + madd.w r0, r1, r2 + + _packw 4, 6, 8, 10, r3 + bne r2, r3, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/mcmpeqb.cgs b/sim/testsuite/sim/sh64/media/mcmpeqb.cgs new file mode 100644 index 00000000000..d7af6fa5f58 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mcmpeqb.cgs @@ -0,0 +1,14 @@ +# sh testcase for mcmpeq.b $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mcmpeqb +mcmpeqb: + mcmpeq.b r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mcmpeql.cgs b/sim/testsuite/sim/sh64/media/mcmpeql.cgs new file mode 100644 index 00000000000..2851e80fc5e --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mcmpeql.cgs @@ -0,0 +1,14 @@ +# sh testcase for mcmpeq.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mcmpeql +mcmpeql: + mcmpeq.l r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mcmpeqw.cgs b/sim/testsuite/sim/sh64/media/mcmpeqw.cgs new file mode 100644 index 00000000000..085df84eeb9 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mcmpeqw.cgs @@ -0,0 +1,14 @@ +# sh testcase for mcmpeq.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mcmpeqw +mcmpeqw: + mcmpeq.w r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mcmpgtl.cgs b/sim/testsuite/sim/sh64/media/mcmpgtl.cgs new file mode 100644 index 00000000000..2ace0480506 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mcmpgtl.cgs @@ -0,0 +1,14 @@ +# sh testcase for mcmpgt.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mcmpgtl +mcmpgtl: + mcmpgt.l r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mcmpgtub.cgs b/sim/testsuite/sim/sh64/media/mcmpgtub.cgs new file mode 100644 index 00000000000..540ce966092 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mcmpgtub.cgs @@ -0,0 +1,14 @@ +# sh testcase for mcmpgt.ub $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mcmpgtub +mcmpgtub: + mcmpgt.ub r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mcmpgtw.cgs b/sim/testsuite/sim/sh64/media/mcmpgtw.cgs new file mode 100644 index 00000000000..83274512d5e --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mcmpgtw.cgs @@ -0,0 +1,14 @@ +# sh testcase for mcmpgt.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mcmpgtw +mcmpgtw: + mcmpgt.w r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mcmv.cgs b/sim/testsuite/sim/sh64/media/mcmv.cgs new file mode 100644 index 00000000000..c1f59aa4f88 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mcmv.cgs @@ -0,0 +1,14 @@ +# sh testcase for mcmv $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mcmv +mcmv: + mcmv r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mcnvslw.cgs b/sim/testsuite/sim/sh64/media/mcnvslw.cgs new file mode 100644 index 00000000000..005108b7669 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mcnvslw.cgs @@ -0,0 +1,14 @@ +# sh testcase for mcnvs.lw $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mcnvslw +mcnvslw: + mcnvs.lw r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mcnvswb.cgs b/sim/testsuite/sim/sh64/media/mcnvswb.cgs new file mode 100644 index 00000000000..0d25920f310 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mcnvswb.cgs @@ -0,0 +1,14 @@ +# sh testcase for mcnvs.wb $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mcnvswb +mcnvswb: + mcnvs.wb r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mcnvswub.cgs b/sim/testsuite/sim/sh64/media/mcnvswub.cgs new file mode 100644 index 00000000000..2fc74466dd0 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mcnvswub.cgs @@ -0,0 +1,14 @@ +# sh testcase for mcnvs.wub $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mcnvswub +mcnvswub: + mcnvs.wub r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mextr1.cgs b/sim/testsuite/sim/sh64/media/mextr1.cgs new file mode 100644 index 00000000000..b2cb3c3ff29 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mextr1.cgs @@ -0,0 +1,67 @@ +# sh testcase for mextr1 $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + # Put a distinguised bit pattern in R0. + movi 0x1020, r0 + shlli r0, 8, r0 + ori r0, 0x30, r0 + shlli r0, 8, r0 + ori r0, 0x40, r0 + shlli r0, 8, r0 + ori r0, 0x50, r0 + shlli r0, 8, r0 + ori r0, 0x60, r0 + shlli r0, 8, r0 + ori r0, 0x70, r0 + shlli r0, 8, r0 + ori r0, 0x80, r0 + + # Put another distinguished bit pattern in R1. + movi 0x1525, r1 + shlli r1, 8, r1 + ori r1, 0x35, r1 + shlli r1, 8, r1 + ori r1, 0x45, r1 + shlli r1, 8, r1 + ori r1, 0x55, r1 + shlli r1, 8, r1 + ori r1, 0x65, r1 + shlli r1, 8, r1 + ori r1, 0x75, r1 + shlli r1, 8, r1 + ori r1, 0x85, r1 + +mextr1: + mextr1 r0, r1, r2 + +check: + # Put the result in R3. + movi 0x2535, r3 + shlli r3, 8, r3 + ori r3, 0x45, r3 + shlli r3, 8, r3 + ori r3, 0x55, r3 + shlli r3, 8, r3 + ori r3, 0x65, r3 + shlli r3, 8, r3 + ori r3, 0x75, r3 + shlli r3, 8, r3 + ori r3, 0x85, r3 + shlli r3, 8, r3 + ori r3, 0x10, r3 + + pta wrong, tr0 + bne r2, r3, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/mextr2.cgs b/sim/testsuite/sim/sh64/media/mextr2.cgs new file mode 100644 index 00000000000..cf136be8176 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mextr2.cgs @@ -0,0 +1,67 @@ +# sh testcase for mextr2 $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + # Put a distinguised bit pattern in R0. + movi 0x1020, r0 + shlli r0, 8, r0 + ori r0, 0x30, r0 + shlli r0, 8, r0 + ori r0, 0x40, r0 + shlli r0, 8, r0 + ori r0, 0x50, r0 + shlli r0, 8, r0 + ori r0, 0x60, r0 + shlli r0, 8, r0 + ori r0, 0x70, r0 + shlli r0, 8, r0 + ori r0, 0x80, r0 + + # Put another distinguished bit pattern in R1. + movi 0x1525, r1 + shlli r1, 8, r1 + ori r1, 0x35, r1 + shlli r1, 8, r1 + ori r1, 0x45, r1 + shlli r1, 8, r1 + ori r1, 0x55, r1 + shlli r1, 8, r1 + ori r1, 0x65, r1 + shlli r1, 8, r1 + ori r1, 0x75, r1 + shlli r1, 8, r1 + ori r1, 0x85, r1 + +mextr2: + mextr2 r0, r1, r2 + +check: + # Put the result in R3. + movi 0x3545, r3 + shlli r3, 8, r3 + ori r3, 0x55, r3 + shlli r3, 8, r3 + ori r3, 0x65, r3 + shlli r3, 8, r3 + ori r3, 0x75, r3 + shlli r3, 8, r3 + ori r3, 0x85, r3 + shlli r3, 8, r3 + ori r3, 0x10, r3 + shlli r3, 8, r3 + ori r3, 0x20, r3 + + pta wrong, tr0 + bne r2, r3, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/mextr3.cgs b/sim/testsuite/sim/sh64/media/mextr3.cgs new file mode 100644 index 00000000000..b8d60a447bc --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mextr3.cgs @@ -0,0 +1,67 @@ +# sh testcase for mextr3 $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + # Put a distinguised bit pattern in R0. + movi 0x1020, r0 + shlli r0, 8, r0 + ori r0, 0x30, r0 + shlli r0, 8, r0 + ori r0, 0x40, r0 + shlli r0, 8, r0 + ori r0, 0x50, r0 + shlli r0, 8, r0 + ori r0, 0x60, r0 + shlli r0, 8, r0 + ori r0, 0x70, r0 + shlli r0, 8, r0 + ori r0, 0x80, r0 + + # Put another distinguished bit pattern in R1. + movi 0x1525, r1 + shlli r1, 8, r1 + ori r1, 0x35, r1 + shlli r1, 8, r1 + ori r1, 0x45, r1 + shlli r1, 8, r1 + ori r1, 0x55, r1 + shlli r1, 8, r1 + ori r1, 0x65, r1 + shlli r1, 8, r1 + ori r1, 0x75, r1 + shlli r1, 8, r1 + ori r1, 0x85, r1 + +mextr3: + mextr3 r0, r1, r2 + +check: + # Put the result in R3. + movi 0x4555, r3 + shlli r3, 8, r3 + ori r3, 0x65, r3 + shlli r3, 8, r3 + ori r3, 0x75, r3 + shlli r3, 8, r3 + ori r3, 0x85, r3 + shlli r3, 8, r3 + ori r3, 0x10, r3 + shlli r3, 8, r3 + ori r3, 0x20, r3 + shlli r3, 8, r3 + ori r3, 0x30, r3 + + pta wrong, tr0 + bne r2, r3, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/mextr4.cgs b/sim/testsuite/sim/sh64/media/mextr4.cgs new file mode 100644 index 00000000000..e9ebff9be7b --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mextr4.cgs @@ -0,0 +1,67 @@ +# sh testcase for mextr4 $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + # Put a distinguised bit pattern in R0. + movi 0x1020, r0 + shlli r0, 8, r0 + ori r0, 0x30, r0 + shlli r0, 8, r0 + ori r0, 0x40, r0 + shlli r0, 8, r0 + ori r0, 0x50, r0 + shlli r0, 8, r0 + ori r0, 0x60, r0 + shlli r0, 8, r0 + ori r0, 0x70, r0 + shlli r0, 8, r0 + ori r0, 0x80, r0 + + # Put another distinguished bit pattern in R1. + movi 0x1525, r1 + shlli r1, 8, r1 + ori r1, 0x35, r1 + shlli r1, 8, r1 + ori r1, 0x45, r1 + shlli r1, 8, r1 + ori r1, 0x55, r1 + shlli r1, 8, r1 + ori r1, 0x65, r1 + shlli r1, 8, r1 + ori r1, 0x75, r1 + shlli r1, 8, r1 + ori r1, 0x85, r1 + +mextr4: + mextr4 r0, r1, r2 + +check: + # Put the result in R3. + movi 0x5565, r3 + shlli r3, 8, r3 + ori r3, 0x75, r3 + shlli r3, 8, r3 + ori r3, 0x85, r3 + shlli r3, 8, r3 + ori r3, 0x10, r3 + shlli r3, 8, r3 + ori r3, 0x20, r3 + shlli r3, 8, r3 + ori r3, 0x30, r3 + shlli r3, 8, r3 + ori r3, 0x40, r3 + + pta wrong, tr0 + bne r2, r3, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/mextr5.cgs b/sim/testsuite/sim/sh64/media/mextr5.cgs new file mode 100644 index 00000000000..c61a0c89f52 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mextr5.cgs @@ -0,0 +1,67 @@ +# sh testcase for mextr5 $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + # Put a distinguised bit pattern in R0. + movi 0x1020, r0 + shlli r0, 8, r0 + ori r0, 0x30, r0 + shlli r0, 8, r0 + ori r0, 0x40, r0 + shlli r0, 8, r0 + ori r0, 0x50, r0 + shlli r0, 8, r0 + ori r0, 0x60, r0 + shlli r0, 8, r0 + ori r0, 0x70, r0 + shlli r0, 8, r0 + ori r0, 0x80, r0 + + # Put another distinguished bit pattern in R1. + movi 0x1525, r1 + shlli r1, 8, r1 + ori r1, 0x35, r1 + shlli r1, 8, r1 + ori r1, 0x45, r1 + shlli r1, 8, r1 + ori r1, 0x55, r1 + shlli r1, 8, r1 + ori r1, 0x65, r1 + shlli r1, 8, r1 + ori r1, 0x75, r1 + shlli r1, 8, r1 + ori r1, 0x85, r1 + +mextr5: + mextr5 r0, r1, r2 + +check: + # Put the result in R3. + movi 0x6575, r3 + shlli r3, 8, r3 + ori r3, 0x85, r3 + shlli r3, 8, r3 + ori r3, 0x10, r3 + shlli r3, 8, r3 + ori r3, 0x20, r3 + shlli r3, 8, r3 + ori r3, 0x30, r3 + shlli r3, 8, r3 + ori r3, 0x40, r3 + shlli r3, 8, r3 + ori r3, 0x50, r3 + + pta wrong, tr0 + bne r2, r3, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/mextr6.cgs b/sim/testsuite/sim/sh64/media/mextr6.cgs new file mode 100644 index 00000000000..5c6c7f60c79 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mextr6.cgs @@ -0,0 +1,67 @@ +# sh testcase for mextr6 $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + # Put a distinguised bit pattern in R0. + movi 0x1020, r0 + shlli r0, 8, r0 + ori r0, 0x30, r0 + shlli r0, 8, r0 + ori r0, 0x40, r0 + shlli r0, 8, r0 + ori r0, 0x50, r0 + shlli r0, 8, r0 + ori r0, 0x60, r0 + shlli r0, 8, r0 + ori r0, 0x70, r0 + shlli r0, 8, r0 + ori r0, 0x80, r0 + + # Put another distinguished bit pattern in R1. + movi 0x1525, r1 + shlli r1, 8, r1 + ori r1, 0x35, r1 + shlli r1, 8, r1 + ori r1, 0x45, r1 + shlli r1, 8, r1 + ori r1, 0x55, r1 + shlli r1, 8, r1 + ori r1, 0x65, r1 + shlli r1, 8, r1 + ori r1, 0x75, r1 + shlli r1, 8, r1 + ori r1, 0x85, r1 + +mextr6: + mextr6 r0, r1, r2 + +check: + # Put the result in R3. + movi 0x7585, r3 + shlli r3, 8, r3 + ori r3, 0x10, r3 + shlli r3, 8, r3 + ori r3, 0x20, r3 + shlli r3, 8, r3 + ori r3, 0x30, r3 + shlli r3, 8, r3 + ori r3, 0x40, r3 + shlli r3, 8, r3 + ori r3, 0x50, r3 + shlli r3, 8, r3 + ori r3, 0x60, r3 + + pta wrong, tr0 + bne r2, r3, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/mextr7.cgs b/sim/testsuite/sim/sh64/media/mextr7.cgs new file mode 100644 index 00000000000..e05ec7f9ab3 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mextr7.cgs @@ -0,0 +1,67 @@ +# sh testcase for mextr7 $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + # Put a distinguised bit pattern in R0. + movi 0x1020, r0 + shlli r0, 8, r0 + ori r0, 0x30, r0 + shlli r0, 8, r0 + ori r0, 0x40, r0 + shlli r0, 8, r0 + ori r0, 0x50, r0 + shlli r0, 8, r0 + ori r0, 0x60, r0 + shlli r0, 8, r0 + ori r0, 0x70, r0 + shlli r0, 8, r0 + ori r0, 0x80, r0 + + # Put another distinguished bit pattern in R1. + movi 0x1525, r1 + shlli r1, 8, r1 + ori r1, 0x35, r1 + shlli r1, 8, r1 + ori r1, 0x45, r1 + shlli r1, 8, r1 + ori r1, 0x55, r1 + shlli r1, 8, r1 + ori r1, 0x65, r1 + shlli r1, 8, r1 + ori r1, 0x75, r1 + shlli r1, 8, r1 + ori r1, 0x85, r1 + +mextr7: + mextr7 r0, r1, r2 + +check: + # Put the result in R3. + movi 0x8510, r3 + shlli r3, 8, r3 + ori r3, 0x20, r3 + shlli r3, 8, r3 + ori r3, 0x30, r3 + shlli r3, 8, r3 + ori r3, 0x40, r3 + shlli r3, 8, r3 + ori r3, 0x50, r3 + shlli r3, 8, r3 + ori r3, 0x60, r3 + shlli r3, 8, r3 + ori r3, 0x70, r3 + + pta wrong, tr0 + bne r2, r3, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/mmacfxwl.cgs b/sim/testsuite/sim/sh64/media/mmacfxwl.cgs new file mode 100644 index 00000000000..dd2d9a41ae7 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mmacfxwl.cgs @@ -0,0 +1,14 @@ +# sh testcase for mmacfx.wl $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mmacfxwl +mmacfxwl: + mmacfx.wl r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mmacnfx-wl.cgs b/sim/testsuite/sim/sh64/media/mmacnfx-wl.cgs new file mode 100644 index 00000000000..ba634d207a3 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mmacnfx-wl.cgs @@ -0,0 +1,14 @@ +# sh testcase for mmacnfx.wl $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mmacnfx_wl +mmacnfx_wl: + mmacnfx.wl r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mmulfxl.cgs b/sim/testsuite/sim/sh64/media/mmulfxl.cgs new file mode 100644 index 00000000000..7d2d1a63268 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mmulfxl.cgs @@ -0,0 +1,14 @@ +# sh testcase for mmulfx.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mmulfxl +mmulfxl: + mmulfx.l r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mmulfxrpw.cgs b/sim/testsuite/sim/sh64/media/mmulfxrpw.cgs new file mode 100644 index 00000000000..13fdcc71d0e --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mmulfxrpw.cgs @@ -0,0 +1,14 @@ +# sh testcase for mmulfxrp.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mmulfxrpw +mmulfxrpw: + mmulfxrp.w r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mmulfxw.cgs b/sim/testsuite/sim/sh64/media/mmulfxw.cgs new file mode 100644 index 00000000000..e2a66a7c11d --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mmulfxw.cgs @@ -0,0 +1,14 @@ +# sh testcase for mmulfx.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mmulfxw +mmulfxw: + mmulfx.w r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mmulhiwl.cgs b/sim/testsuite/sim/sh64/media/mmulhiwl.cgs new file mode 100644 index 00000000000..1a41ac59286 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mmulhiwl.cgs @@ -0,0 +1,14 @@ +# sh testcase for mmulhi.wl $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mmulhiwl +mmulhiwl: + mmulhi.wl r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mmull.cgs b/sim/testsuite/sim/sh64/media/mmull.cgs new file mode 100644 index 00000000000..b3ed9df3f35 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mmull.cgs @@ -0,0 +1,14 @@ +# sh testcase for mmul.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mmull +mmull: + mmul.l r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mmullowl.cgs b/sim/testsuite/sim/sh64/media/mmullowl.cgs new file mode 100644 index 00000000000..b50ccfcb5dd --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mmullowl.cgs @@ -0,0 +1,14 @@ +# sh testcase for mmullo.wl $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mmullowl +mmullowl: + mmullo.wl r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mmulsumwq.cgs b/sim/testsuite/sim/sh64/media/mmulsumwq.cgs new file mode 100644 index 00000000000..344710b0e98 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mmulsumwq.cgs @@ -0,0 +1,14 @@ +# sh testcase for mmulsum.wq $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mmulsumwq +mmulsumwq: + mmulsum.wq r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mmulw.cgs b/sim/testsuite/sim/sh64/media/mmulw.cgs new file mode 100644 index 00000000000..675c620fadc --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mmulw.cgs @@ -0,0 +1,14 @@ +# sh testcase for mmul.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mmulw +mmulw: + mmul.w r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/movi.cgs b/sim/testsuite/sim/sh64/media/movi.cgs new file mode 100644 index 00000000000..a01bcae84df --- /dev/null +++ b/sim/testsuite/sim/sh64/media/movi.cgs @@ -0,0 +1,29 @@ +# sh testcase for movi $imm16, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +movi0: + movi 0, r0 + bnei r0, 0, tr0 +movi1: + movi 1, r0 + bnei r0, 1, tr0 +movi2: + movi 23, r0 + bnei r0, 23, tr0 +movn: + movi -1, r0 + addi r0, 1, r0 + bnei r0, 0, tr0 + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/mpermw.cgs b/sim/testsuite/sim/sh64/media/mpermw.cgs new file mode 100644 index 00000000000..3b6741e8107 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mpermw.cgs @@ -0,0 +1,51 @@ +# sh testcase for mperm.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + movi 27, r1 + movi 0x1020, r0 + shlli r0, 8, r0 + ori r0, 0x30, r0 + shlli r0, 8, r0 + ori r0, 0x40, r0 + shlli r0, 8, r0 + ori r0, 0x50, r0 + shlli r0, 8, r0 + ori r0, 0x60, r0 + shlli r0, 8, r0 + ori r0, 0x70, r0 + shlli r0, 8, r0 + ori r0, 0x80, r0 + +mpermw: + mperm.w r0, r1, r2 + +check: + # Expect 0x7080506030401020. + movi 0x7080, r0 + shlli r0, 8, r0 + ori r0, 0x50, r0 + shlli r0, 8, r0 + ori r0, 0x60, r0 + shlli r0, 8, r0 + ori r0, 0x30, r0 + shlli r0, 8, r0 + ori r0, 0x40, r0 + shlli r0, 8, r0 + ori r0, 0x10, r0 + shlli r0, 8, r0 + ori r0, 0x20, r0 + + bne r0, r2, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/msadubq.cgs b/sim/testsuite/sim/sh64/media/msadubq.cgs new file mode 100644 index 00000000000..4361883b870 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/msadubq.cgs @@ -0,0 +1,14 @@ +# sh testcase for msad.ubq $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global msadubq +msadubq: + msad.ubq r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mshaldsl.cgs b/sim/testsuite/sim/sh64/media/mshaldsl.cgs new file mode 100644 index 00000000000..1dd86ec6bb6 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mshaldsl.cgs @@ -0,0 +1,14 @@ +# sh testcase for mshalds.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mshaldsl +mshaldsl: + mshalds.l r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mshaldsw.cgs b/sim/testsuite/sim/sh64/media/mshaldsw.cgs new file mode 100644 index 00000000000..7ab6797e9a6 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mshaldsw.cgs @@ -0,0 +1,14 @@ +# sh testcase for mshalds.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mshaldsw +mshaldsw: + mshalds.w r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mshardl.cgs b/sim/testsuite/sim/sh64/media/mshardl.cgs new file mode 100644 index 00000000000..0dc102e337a --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mshardl.cgs @@ -0,0 +1,14 @@ +# sh testcase for mshard.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mshardl +mshardl: + mshard.l r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mshardsq.cgs b/sim/testsuite/sim/sh64/media/mshardsq.cgs new file mode 100644 index 00000000000..5f29afb8b1b --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mshardsq.cgs @@ -0,0 +1,14 @@ +# sh testcase for mshards.q $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mshardsq +mshardsq: + mshards.q r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mshardw.cgs b/sim/testsuite/sim/sh64/media/mshardw.cgs new file mode 100644 index 00000000000..ecc7004febd --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mshardw.cgs @@ -0,0 +1,14 @@ +# sh testcase for mshard.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mshardw +mshardw: + mshard.w r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mshfhib.cgs b/sim/testsuite/sim/sh64/media/mshfhib.cgs new file mode 100644 index 00000000000..b7b245e79ae --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mshfhib.cgs @@ -0,0 +1,14 @@ +# sh testcase for mshfhi.b $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mshfhib +mshfhib: + mshfhi.b r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mshfhil.cgs b/sim/testsuite/sim/sh64/media/mshfhil.cgs new file mode 100644 index 00000000000..2fab7ae1fd9 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mshfhil.cgs @@ -0,0 +1,14 @@ +# sh testcase for mshfhi.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mshfhil +mshfhil: + mshfhi.l r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mshfhiw.cgs b/sim/testsuite/sim/sh64/media/mshfhiw.cgs new file mode 100644 index 00000000000..03111413cf1 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mshfhiw.cgs @@ -0,0 +1,14 @@ +# sh testcase for mshfhi.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mshfhiw +mshfhiw: + mshfhi.w r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mshflob.cgs b/sim/testsuite/sim/sh64/media/mshflob.cgs new file mode 100644 index 00000000000..400e81a0598 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mshflob.cgs @@ -0,0 +1,14 @@ +# sh testcase for mshflo.b $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mshflob +mshflob: + mshflo.b r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mshflol.cgs b/sim/testsuite/sim/sh64/media/mshflol.cgs new file mode 100644 index 00000000000..2fbdf894e60 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mshflol.cgs @@ -0,0 +1,14 @@ +# sh testcase for mshflo.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mshflol +mshflol: + mshflo.l r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mshflow.cgs b/sim/testsuite/sim/sh64/media/mshflow.cgs new file mode 100644 index 00000000000..542eb042c52 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mshflow.cgs @@ -0,0 +1,14 @@ +# sh testcase for mshflo.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mshflow +mshflow: + mshflo.w r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mshlldl.cgs b/sim/testsuite/sim/sh64/media/mshlldl.cgs new file mode 100644 index 00000000000..2a17c33002e --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mshlldl.cgs @@ -0,0 +1,14 @@ +# sh testcase for mshlld.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mshlldl +mshlldl: + mshlld.l r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mshlldw.cgs b/sim/testsuite/sim/sh64/media/mshlldw.cgs new file mode 100644 index 00000000000..e4afe3d732a --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mshlldw.cgs @@ -0,0 +1,14 @@ +# sh testcase for mshlld.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mshlldw +mshlldw: + mshlld.w r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mshlrdl.cgs b/sim/testsuite/sim/sh64/media/mshlrdl.cgs new file mode 100644 index 00000000000..89e70772b7f --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mshlrdl.cgs @@ -0,0 +1,14 @@ +# sh testcase for mshlrd.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mshlrdl +mshlrdl: + mshlrd.l r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mshlrdw.cgs b/sim/testsuite/sim/sh64/media/mshlrdw.cgs new file mode 100644 index 00000000000..4cbf2807f9c --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mshlrdw.cgs @@ -0,0 +1,14 @@ +# sh testcase for mshlrd.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mshlrdw +mshlrdw: + mshlrd.w r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/msubl.cgs b/sim/testsuite/sim/sh64/media/msubl.cgs new file mode 100644 index 00000000000..87151fad728 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/msubl.cgs @@ -0,0 +1,14 @@ +# sh testcase for msub.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global msubl +msubl: + msub.l r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/msubsl.cgs b/sim/testsuite/sim/sh64/media/msubsl.cgs new file mode 100644 index 00000000000..014422ed8f3 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/msubsl.cgs @@ -0,0 +1,14 @@ +# sh testcase for msubs.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global msubsl +msubsl: + msubs.l r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/msubsub.cgs b/sim/testsuite/sim/sh64/media/msubsub.cgs new file mode 100644 index 00000000000..c92c77ee72e --- /dev/null +++ b/sim/testsuite/sim/sh64/media/msubsub.cgs @@ -0,0 +1,14 @@ +# sh testcase for msubs.ub $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global msubsub +msubsub: + msubs.ub r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/msubsw.cgs b/sim/testsuite/sim/sh64/media/msubsw.cgs new file mode 100644 index 00000000000..83b76a1b4b3 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/msubsw.cgs @@ -0,0 +1,14 @@ +# sh testcase for msubs.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global msubsw +msubsw: + msubs.w r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/msubw.cgs b/sim/testsuite/sim/sh64/media/msubw.cgs new file mode 100644 index 00000000000..9d5e639f240 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/msubw.cgs @@ -0,0 +1,14 @@ +# sh testcase for msub.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global msubw +msubw: + msub.w r0, r0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/mulsl.cgs b/sim/testsuite/sim/sh64/media/mulsl.cgs new file mode 100644 index 00000000000..d65c80cadf2 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mulsl.cgs @@ -0,0 +1,54 @@ +# sh testcase for muls.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mulsl +init: + pta wrong, tr0 + +mulsl1: + movi 0, r0 + muls.l r0, r0, r1 + bnei r1, 0, tr0 + +mulsl2: + movi 0, r0 + movi 1, r1 + muls.l r0, r1, r2 + bnei r2, 0, tr0 + +mulsl3: + movi 1, r0 + movi 0, r1 + muls.l r0, r1, r2 + bnei r2, 0, tr0 + +mulsl4: + movi 1, r0 + movi 1, r1 + muls.l r0, r1, r2 + bnei r2, 1, tr0 + +mulsl5: + movi 2, r0 + movi 9, r1 + muls.l r0, r1, r2 + bnei r2, 18, tr0 + +mulsl6: + movi 2, r0 + movi -9, r1 + muls.l r0, r1, r2 + bnei r2, -18, tr0 + +okay: + pass + +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/media/mulul.cgs b/sim/testsuite/sim/sh64/media/mulul.cgs new file mode 100644 index 00000000000..b795cf79ec0 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/mulul.cgs @@ -0,0 +1,54 @@ +# sh testcase for mulu.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global mulul +init: + pta wrong, tr0 + +mulul1: + movi 0, r0 + mulu.l r0, r0, r1 + bnei r1, 0, tr0 + +mulul2: + movi 0, r0 + movi 1, r1 + mulu.l r0, r1, r2 + bnei r2, 0, tr0 + +mulul3: + movi 1, r0 + movi 0, r1 + mulu.l r0, r1, r2 + bnei r2, 0, tr0 + +mulul4: + movi 1, r0 + movi 1, r1 + mulu.l r0, r1, r2 + bnei r2, 1, tr0 + +mulul5: + movi 2, r0 + movi 9, r1 + mulu.l r0, r1, r2 + bnei r2, 18, tr0 + +mulul6: + movi 2, r0 + movi -9, r1 + mulu.l r0, r1, r2 + beqi r2, -18, tr0 + +okay: + pass + +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/media/nop.cgs b/sim/testsuite/sim/sh64/media/nop.cgs new file mode 100644 index 00000000000..a0e57530542 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/nop.cgs @@ -0,0 +1,10 @@ +# sh testcase for nop -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + nop + pass diff --git a/sim/testsuite/sim/sh64/media/nsb.cgs b/sim/testsuite/sim/sh64/media/nsb.cgs new file mode 100644 index 00000000000..8b3cffef4a8 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/nsb.cgs @@ -0,0 +1,66 @@ +# sh testcase for nsb $rm, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +nsb0: + movi 0, r0 + nsb r0, r1 +check0: + movi 63, r4 + bne r1, r4, tr0 + +nsb1: + # set up a loop target reg. + pta again1, tr1 + # r4 holds the loop count. + movi 62, r4 + movi 1, r0 +again1: + nsb r0, r1 + bne r1, r4, tr0 + # okay? go around again. + shlli r0, 1, r0 + addi r4, -1, r4 + bnei r4, 0, tr1 + +nsb2: + # set up a loop target reg. + pta again2, tr1 + # r4 holds the loop count. + movi 63, r4 + movi -1, r0 +again2: + nsb r0, r1 + bne r1, r4, tr0 + # okay? go around again. + shlli r0, 1, r0 + addi r4, -1, r4 + bnei r4, 0, tr1 + +nsb3: + movi 1, r0 + shlli r0, 63, r0 + nsb r0, r1 +check3: + movi 0, r4 + bne r1, r4, tr0 + +nsb4: + movi 7, r0 + shlli r0, 61, r0 + nsb r0, r1 +check4: + movi 2, r4 + bne r1, r4, tr0 + +okay: + pass +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/ocbi.cgs b/sim/testsuite/sim/sh64/media/ocbi.cgs new file mode 100644 index 00000000000..b210216e3db --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ocbi.cgs @@ -0,0 +1,10 @@ +# sh testcase for ocbi $rm, $disp6x32 -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + ocbi r0, 0 + pass diff --git a/sim/testsuite/sim/sh64/media/ocbp.cgs b/sim/testsuite/sim/sh64/media/ocbp.cgs new file mode 100644 index 00000000000..9158c6f4518 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ocbp.cgs @@ -0,0 +1,10 @@ +# sh testcase for ocbp $rm, $disp6x32 -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + ocbp r0, 0 + pass diff --git a/sim/testsuite/sim/sh64/media/ocbwb.cgs b/sim/testsuite/sim/sh64/media/ocbwb.cgs new file mode 100644 index 00000000000..6addabcf461 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ocbwb.cgs @@ -0,0 +1,10 @@ +# sh testcase for ocbwb $rm, $disp6x32 -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + ocbwb r0, 0 + pass diff --git a/sim/testsuite/sim/sh64/media/or.cgs b/sim/testsuite/sim/sh64/media/or.cgs new file mode 100644 index 00000000000..e06759225ba --- /dev/null +++ b/sim/testsuite/sim/sh64/media/or.cgs @@ -0,0 +1,44 @@ +# sh testcase for or $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +or1: + movi 0, r0 + or r0, r0, r1 + bnei r1, 0, tr0 + +or2: + movi 0, r0 + movi 1, r1 + or r0, r1, r2 + bnei r2, 1, tr0 + +or3: + movi 1, r0 + movi 0, r1 + or r0, r1, r2 + bnei r2, 1, tr0 + +or4: + movi 1, r0 + or r0, r0, r1 + bnei r1, 1, tr0 + +or5: + movi 1, r0 + shlli r0, 63, r0 + movi 1, r1 + or r0, r1, r2 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/ori.cgs b/sim/testsuite/sim/sh64/media/ori.cgs new file mode 100644 index 00000000000..7b2554227da --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ori.cgs @@ -0,0 +1,41 @@ +# sh testcase for ori $rm, $imm10, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +or1: + movi 0, r0 + ori r0, 0, r1 + bnei r1, 0, tr0 + +or2: + movi 0, r0 + ori r0, 1, r2 + bnei r2, 1, tr0 + +or3: + movi 1, r0 + ori r0, 0, r2 + bnei r2, 1, tr0 + +or4: + movi 1, r0 + ori r0, 1, r1 + bnei r1, 1, tr0 + +or5: + movi 1, r0 + shlli r0, 63, r0 + ori r0, 1, r2 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/prefi.cgs b/sim/testsuite/sim/sh64/media/prefi.cgs new file mode 100644 index 00000000000..68d7bfe29a4 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/prefi.cgs @@ -0,0 +1,10 @@ +# sh testcase for prefi $rm, $disp6x32 -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + prefi r0, 0 + pass diff --git a/sim/testsuite/sim/sh64/media/pta.cgs b/sim/testsuite/sim/sh64/media/pta.cgs new file mode 100644 index 00000000000..9f6484a8d4c --- /dev/null +++ b/sim/testsuite/sim/sh64/media/pta.cgs @@ -0,0 +1,26 @@ +# sh testcase for pta$likely $disp16, $tra -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +pta0: + pta foo, tr0 +pta1: + pta/l bar, tr1 +pta2: + pta/u baz, tr2 + movi 0, r0 + bnei r0, 1, tr2 + fail + +foo: +bar: +baz: + pass + fail + fail + fail + fail diff --git a/sim/testsuite/sim/sh64/media/ptabs.cgs b/sim/testsuite/sim/sh64/media/ptabs.cgs new file mode 100644 index 00000000000..0c01f838eb8 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ptabs.cgs @@ -0,0 +1,25 @@ +# sh testcase for ptabs$likely $rn, $tra -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global ptabs +ptabs: + movi 16, r0 + shlli r0, 8, r0 + # Add one to stay in SHmedia mode. + addi r0, 29, r0 + ptabs r0, tr0 + + # Now jump. + beqi r63, 0, tr0 + +wrong: + fail + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/ptb.cgs b/sim/testsuite/sim/sh64/media/ptb.cgs new file mode 100644 index 00000000000..129d6260439 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ptb.cgs @@ -0,0 +1,29 @@ +# sh testcase for ptb$likely $disp16, $tra -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +ptb0: + ptb foo, tr0 +ptb: + ptb/l bar, tr1 +ptb2: + ptb/u baz, tr2 + movi 0, r0 + bnei r0, 1, tr2 + fail + +.mode SHcompact + +foo: +bar: +baz: + trapa #253 + trapa #254 + trapa #254 + trapa #254 + trapa #254 diff --git a/sim/testsuite/sim/sh64/media/ptrel.cgs b/sim/testsuite/sim/sh64/media/ptrel.cgs new file mode 100644 index 00000000000..7e5f19b1b9c --- /dev/null +++ b/sim/testsuite/sim/sh64/media/ptrel.cgs @@ -0,0 +1,22 @@ +# sh testcase for ptrel$likely $rn, $tra -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + # Add one to stay in SHmedia mode. + movi 53, r0 + ptrel r0, tr0 + movi 0, r0 + # Always branch. + bnei r0, 1, tr0 + fail + fail + fail + fail + fail + pass + fail + fail diff --git a/sim/testsuite/sim/sh64/media/putcfg.cgs b/sim/testsuite/sim/sh64/media/putcfg.cgs new file mode 100644 index 00000000000..85385754a48 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/putcfg.cgs @@ -0,0 +1,10 @@ +# sh testcase for putcfg $rm, $disp6, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + putcfg r0, 0, r0 + pass diff --git a/sim/testsuite/sim/sh64/media/putcon.cgs b/sim/testsuite/sim/sh64/media/putcon.cgs new file mode 100644 index 00000000000..39dfc036280 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/putcon.cgs @@ -0,0 +1,30 @@ +# sh testcase for putcon $rm, $crj -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +putcon1: + movi 22, r0 + putcon r0, cr0 + getcon cr0, r1 + bne r0, r1, tr0 + +putcon2: + movi 12, r0 + shlli r0, 35, r0 + putcon r0, cr20 + getcon cr20, r20 + bne r0, r20, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/rte.cgs b/sim/testsuite/sim/sh64/media/rte.cgs new file mode 100644 index 00000000000..e80f08541cc --- /dev/null +++ b/sim/testsuite/sim/sh64/media/rte.cgs @@ -0,0 +1,11 @@ +# sh testcase for rte -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + # Unimplemented. + rte + pass diff --git a/sim/testsuite/sim/sh64/media/shard.cgs b/sim/testsuite/sim/sh64/media/shard.cgs new file mode 100644 index 00000000000..029e52902a2 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/shard.cgs @@ -0,0 +1,30 @@ +# sh testcase for shard $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +shard1: + movi 128, r0 + movi 3, r1 + shard r0, r1, r2 + bnei r2, 16, tr0 + +shard2: + movi -4, r0 + movi 2, r1 + shard r0, r1, r2 + addi r2, 1, r2 + bnei r2, 0, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/shardl.cgs b/sim/testsuite/sim/sh64/media/shardl.cgs new file mode 100644 index 00000000000..d9acaa54f69 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/shardl.cgs @@ -0,0 +1,45 @@ +# sh testcase for shard.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +shardl1: + movi 0x1020, r0 + shlli r0, 8, r0 + ori r0, 0x30, r0 + shlli r0, 8, r0 + ori r0, 0x40, r0 + shlli r0, 8, r0 + ori r0, 0x50, r0 + shlli r0, 8, r0 + ori r0, 0x60, r0 + shlli r0, 8, r0 + ori r0, 0x70, r0 + shlli r0, 8, r0 + ori r0, 0x80, r0 + + movi 1, r1 + shard.l r0, r1, r0 + shard.l r0, r1, r0 + shard.l r0, r1, r0 + shard.l r0, r1, r0 + shard.l r0, r1, r0 + shard.l r0, r1, r0 + shard.l r0, r1, r0 + shard.l r0, r1, r0 + movi 20, r1 + shard.l r0, r1, r0 + bnei r0, 5, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/shari.cgs b/sim/testsuite/sim/sh64/media/shari.cgs new file mode 100644 index 00000000000..3d3a650fb0c --- /dev/null +++ b/sim/testsuite/sim/sh64/media/shari.cgs @@ -0,0 +1,28 @@ +# sh testcase for shari $rm, $imm, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +shari1: + movi 128, r0 + shari r0, 3, r2 + bnei r2, 16, tr0 + +shari2: + movi -4, r0 + shari r0, 2, r2 + addi r2, 1, r2 + bnei r2, 0, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/sharil.cgs b/sim/testsuite/sim/sh64/media/sharil.cgs new file mode 100644 index 00000000000..be946e0c84d --- /dev/null +++ b/sim/testsuite/sim/sh64/media/sharil.cgs @@ -0,0 +1,45 @@ +# sh testcase for shari.l $rm, $imm6, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +sharil1: + movi 0x1020, r0 + shlli r0, 8, r0 + ori r0, 0x30, r0 + shlli r0, 8, r0 + ori r0, 0x40, r0 + shlli r0, 8, r0 + ori r0, 0x50, r0 + shlli r0, 8, r0 + ori r0, 0x60, r0 + shlli r0, 8, r0 + ori r0, 0x70, r0 + shlli r0, 8, r0 + ori r0, 0x80, r0 + + movi 1, r1 + shari.l r0, 1, r0 + shari.l r0, 1, r0 + shari.l r0, 1, r0 + shari.l r0, 1, r0 + shari.l r0, 1, r0 + shari.l r0, 1, r0 + shari.l r0, 1, r0 + shari.l r0, 1, r0 + shari.l r0, 20, r0 + bnei r0, 5, tr0 + +okay: + pass + +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/media/shlld.cgs b/sim/testsuite/sim/sh64/media/shlld.cgs new file mode 100644 index 00000000000..05d2da4cd68 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/shlld.cgs @@ -0,0 +1,36 @@ +# sh testcase for shlld $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +shlld1: + movi 1, r0 + movi 5, r1 + shlld r0, r1, r2 + movi 32, r7 + bne r2, r7, tr0 + +shlld2: + movi 2, r1 + shlld r2, r1, r3 + movi 128, r7 + bne r3, r7, tr0 + +shlld3: + movi 32, r1 + shlld r0, r1, r7 + shlld r7, r1, r2 + bnei r2, 0, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/shlldl.cgs b/sim/testsuite/sim/sh64/media/shlldl.cgs new file mode 100644 index 00000000000..3d37f53a76b --- /dev/null +++ b/sim/testsuite/sim/sh64/media/shlldl.cgs @@ -0,0 +1,34 @@ +# sh testcase for shlld.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +shlldl1: + movi 1, r0 + shlli r0, 32, r0 + ori r0, 1, r0 + movi 1, r1 + shlli r1, 7, r1 + ori r1, 3, r1 + + shlld.l r0, r1, r2 + +check1: + bnei r2, 8, tr0 + +shlldl2: + movi 1, r0 + movi 31, r1 + shlld.l r0, r1, r2 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/shlli.cgs b/sim/testsuite/sim/sh64/media/shlli.cgs new file mode 100644 index 00000000000..9ab331c0930 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/shlli.cgs @@ -0,0 +1,30 @@ +# sh testcase for shlli $rm, $imm6, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +shlli: + movi 1, r0 + shlli r0, 3, r0 + bnei r0, 8, tr0 + +shlli2: + shlli r0, 3, r0 + +shlli3: + # Shift all bits out of sight. + shlli r0, 63, r0 + bnei r0, 0, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/shllil.cgs b/sim/testsuite/sim/sh64/media/shllil.cgs new file mode 100644 index 00000000000..347acd64084 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/shllil.cgs @@ -0,0 +1,14 @@ +# sh testcase for shlli.l $rm, $imm6, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global shllil +shllil: + shlli.l r0, 0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/shlrd.cgs b/sim/testsuite/sim/sh64/media/shlrd.cgs new file mode 100644 index 00000000000..56f10bf1c0e --- /dev/null +++ b/sim/testsuite/sim/sh64/media/shlrd.cgs @@ -0,0 +1,30 @@ +# sh testcase for shlrd $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +shlrd1: + movi 128, r0 + movi 3, r1 + shlrd r0, r1, r2 + bnei r2, 16, tr0 + +shlrd2: + movi -4, r0 + movi 2, r1 + shlrd r0, r1, r2 + addi r2, 1, r2 + beqi r2, 0, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/shlrdl.cgs b/sim/testsuite/sim/sh64/media/shlrdl.cgs new file mode 100644 index 00000000000..32b20c0a3cd --- /dev/null +++ b/sim/testsuite/sim/sh64/media/shlrdl.cgs @@ -0,0 +1,37 @@ +# sh testcase for shlrd.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +shlrdl1: + movi 1, r0 + shlli r0, 32, r0 + ori r0, 8, r0 + movi 1, r1 + shlli r1, 7, r1 + ori r1, 3, r1 + + shlrd.l r0, r1, r2 + +check1: + bnei r2, 1, tr0 + +shlrdl2: + movi 1, r0 + shlli r0, 31, r0 + movi 31, r1 + shlld.l r0, r1, r2 + bnei r2, 0, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/shlri.cgs b/sim/testsuite/sim/sh64/media/shlri.cgs new file mode 100644 index 00000000000..488cac9aec8 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/shlri.cgs @@ -0,0 +1,28 @@ +# sh testcase for shlri $rm, $imm, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +shlri1: + movi 128, r0 + shlri r0, 3, r2 + bnei r2, 16, tr0 + +shlri2: + movi -4, r0 + shlri r0, 2, r2 + addi r2, 1, r2 + beqi r2, 0, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/shlril.cgs b/sim/testsuite/sim/sh64/media/shlril.cgs new file mode 100644 index 00000000000..bb1b2a6eaf0 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/shlril.cgs @@ -0,0 +1,14 @@ +# sh testcase for shlri.l $rm, $imm6, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global shlril +shlril: + shlri.l r0, 0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/shori.cgs b/sim/testsuite/sim/sh64/media/shori.cgs new file mode 100644 index 00000000000..5f02b7d2c5f --- /dev/null +++ b/sim/testsuite/sim/sh64/media/shori.cgs @@ -0,0 +1,35 @@ +# sh testcase for shori $imm16, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +shori1: + movi 1, r0 + shori 7, r0 + # check it. + andi r0, 15, r7 + bnei r7, 7, tr0 + shlri r0, 16, r0 + bnei r0, 1, tr0 + +shori2: + # Test for zero extension bug reported by + # Alexandre Oliva . + movi 0, r0 + shori 65535, r0 + # check it. + movi 0xffff, r1 + bne r0, r1, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/sleep.cgs b/sim/testsuite/sim/sh64/media/sleep.cgs new file mode 100644 index 00000000000..b4c35ee8f96 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/sleep.cgs @@ -0,0 +1,10 @@ +# sh testcase for sleep -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + sleep + pass diff --git a/sim/testsuite/sim/sh64/media/stb.cgs b/sim/testsuite/sim/sh64/media/stb.cgs new file mode 100644 index 00000000000..09de47b14a9 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/stb.cgs @@ -0,0 +1,26 @@ +# sh testcase for st.b $rm, $disp10, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + movi -1, r7 + xori r7, 13, r7 + movi 40, r0 + shlli r0, 8, r0 + +stb1: + st.b r0, 0, r7 + +stb2: + st.b r0, 1, r7 + +stb3: + st.b r0, -1, r7 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/sthil.cgs b/sim/testsuite/sim/sh64/media/sthil.cgs new file mode 100644 index 00000000000..cfee28444f8 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/sthil.cgs @@ -0,0 +1,55 @@ +# sh testcase for sthi.l $rm, $disp6, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + + movi 40, r0 + shlli r0, 8, r0 + + movi 0x1020, r1 + shlli r1, 8, r1 + addi r1, 0x30, r1 + shlli r1, 8, r1 + addi r1, 0x40, r1 + shlli r1, 8, r1 + addi r1, 0x50, r1 + shlli r1, 8, r1 + addi r1, 0x60, r1 + shlli r1, 8, r1 + addi r1, 0x70, r1 + shlli r1, 8, r1 + addi r1, 0x80, r1 + +sthil1: + sthi.l r0, 0, r1 + +sthil2: + sthi.l r0, 1, r1 + +sthil3: + sthi.l r0, 2, r1 + +sthil4: + sthi.l r0, 3, r1 + +sthil5: + sthi.l r0, -1, r1 + +sthil6: + sthi.l r0, -2, r1 + +sthil7: + sthi.l r0, -3, r1 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/sthiq.cgs b/sim/testsuite/sim/sh64/media/sthiq.cgs new file mode 100644 index 00000000000..6310d43e5ad --- /dev/null +++ b/sim/testsuite/sim/sh64/media/sthiq.cgs @@ -0,0 +1,79 @@ +# sh testcase for sthi.q $rm, $disp6, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + + movi 40, r0 + shlli r0, 8, r0 + + movi 0x1020, r1 + shlli r1, 8, r1 + addi r1, 0x30, r1 + shlli r1, 8, r1 + addi r1, 0x40, r1 + shlli r1, 8, r1 + addi r1, 0x50, r1 + shlli r1, 8, r1 + addi r1, 0x60, r1 + shlli r1, 8, r1 + addi r1, 0x70, r1 + shlli r1, 8, r1 + addi r1, 0x80, r1 + +sthiq1: + sthi.q r0, 0, r1 + +sthiq2: + sthi.q r0, 1, r1 + +sthiq3: + sthi.q r0, 2, r1 + +sthiq4: + sthi.q r0, 3, r1 + +sthiq5: + sthi.q r0, 4, r1 + +sthiq6: + sthi.q r0, 5, r1 + +sthiq7: + sthi.q r0, 6, r1 + +sthiq8: + sthi.q r0, 7, r1 + +sthiq9: + sthi.q r0, -1, r1 + +sthiq10: + sthi.q r0, -2, r1 + +sthiq11: + sthi.q r0, -3, r1 + +sthiq12: + sthi.q r0, -4, r1 + +sthiq13: + sthi.q r0, -5, r1 + +sthiq14: + sthi.q r0, -6, r1 + +sthiq15: + sthi.q r0, -7, r1 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/stl.cgs b/sim/testsuite/sim/sh64/media/stl.cgs new file mode 100644 index 00000000000..8737e354c5b --- /dev/null +++ b/sim/testsuite/sim/sh64/media/stl.cgs @@ -0,0 +1,26 @@ +# sh testcase for st.l $rm, $disp10, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + movi -1, r7 + xori r7, 13, r7 + movi 40, r0 + shlli r0, 8, r0 + +stl1: + st.l r0, 0, r7 + +stl2: + st.l r0, 4, r7 + +stl3: + st.l r0, -4, r7 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/stlol.cgs b/sim/testsuite/sim/sh64/media/stlol.cgs new file mode 100644 index 00000000000..f2d90552509 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/stlol.cgs @@ -0,0 +1,14 @@ +# sh testcase for stlo.l $rm, $disp6, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global stlol +stlol: + stlo.l r0, 0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/stloq.cgs b/sim/testsuite/sim/sh64/media/stloq.cgs new file mode 100644 index 00000000000..35c84c255cc --- /dev/null +++ b/sim/testsuite/sim/sh64/media/stloq.cgs @@ -0,0 +1,14 @@ +# sh testcase for stlo.q $rm, $disp6, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + + .global stloq +stloq: + stlo.q r0, 0, r0 + + pass diff --git a/sim/testsuite/sim/sh64/media/stq.cgs b/sim/testsuite/sim/sh64/media/stq.cgs new file mode 100644 index 00000000000..e1af7956b84 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/stq.cgs @@ -0,0 +1,26 @@ +# sh testcase for st.q $rm, $disp10, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + movi -1, r7 + xori r7, 13, r7 + movi 40, r0 + shlli r0, 8, r0 + +stq1: + st.q r0, 0, r7 + +stq2: + st.q r0, 8, r7 + +stq3: + st.q r0, -8, r7 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/stw.cgs b/sim/testsuite/sim/sh64/media/stw.cgs new file mode 100644 index 00000000000..2446aa62795 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/stw.cgs @@ -0,0 +1,26 @@ +# sh testcase for st.q $rm, $disp10, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + movi -1, r7 + xori r7, 13, r7 + movi 40, r0 + shlli r0, 8, r0 + +stw1: + st.w r0, 0, r7 + +stw2: + st.w r0, 2, r7 + +stw3: + st.w r0, -2, r7 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/stxb.cgs b/sim/testsuite/sim/sh64/media/stxb.cgs new file mode 100644 index 00000000000..8ab2ae31d23 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/stxb.cgs @@ -0,0 +1,29 @@ +# sh testcase for stx.b $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + movi -1, r7 + xori r7, 13, r7 + movi 40, r0 + shlli r0, 8, r0 + +stxb1: + movi 0, r1 + stx.b r0, r1, r7 + +stxb2: + movi 1, r1 + stx.b r0, r1, r7 + +stxb3: + movi -1, r1 + stx.b r0, r1, r7 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/stxl.cgs b/sim/testsuite/sim/sh64/media/stxl.cgs new file mode 100644 index 00000000000..8ed2e366ab3 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/stxl.cgs @@ -0,0 +1,29 @@ +# sh testcase for stx.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + movi -1, r7 + xori r7, 13, r7 + movi 40, r0 + shlli r0, 8, r0 + +stxl1: + movi 0, r1 + stx.l r0, r1, r7 + +stxl2: + movi 4, r1 + stx.l r0, r1, r7 + +stxl3: + movi -4, r1 + stx.l r0, r1, r7 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/stxq.cgs b/sim/testsuite/sim/sh64/media/stxq.cgs new file mode 100644 index 00000000000..10759fd4414 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/stxq.cgs @@ -0,0 +1,29 @@ +# sh testcase for stx.q $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + movi -1, r7 + xori r7, 13, r7 + movi 40, r0 + shlli r0, 8, r0 + +stxq1: + movi 0, r1 + stx.q r0, r1, r7 + +stxq2: + movi 8, r1 + stx.q r0, r1, r7 + +stxq3: + movi -8, r1 + stx.q r0, r1, r7 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/stxw.cgs b/sim/testsuite/sim/sh64/media/stxw.cgs new file mode 100644 index 00000000000..d03981146a2 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/stxw.cgs @@ -0,0 +1,29 @@ +# sh testcase for stx.w $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + movi -1, r7 + xori r7, 13, r7 + movi 40, r0 + shlli r0, 8, r0 + +stxw1: + movi 0, r1 + stx.w r0, r1, r7 + +stxw2: + movi 2, r1 + stx.w r0, r1, r7 + +stxw3: + movi -2, r1 + stx.w r0, r1, r7 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/sub.cgs b/sim/testsuite/sim/sh64/media/sub.cgs new file mode 100644 index 00000000000..e5e7530100b --- /dev/null +++ b/sim/testsuite/sim/sh64/media/sub.cgs @@ -0,0 +1,42 @@ +# sh testcase for sub $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + movi 0, r0 + movi 1, r1 + +sub1: + # 0 - 0 = 0. + sub r0, r0, r2 + bnei r2, 0, tr0 + +sub2: + # 1 - 0 = 1. + sub r1, r0, r2 + bnei r2, 1, tr0 + +sub3: + # 0 - 1 = -1. + sub r0, r1, r2 + addi r2, 1, r2 + bnei r2, 0, tr0 + +sub4: + # 5 - 2 = 3. + movi 5, r0 + movi 2, r1 + sub r0, r1, r2 + bnei r2, 3, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/subl.cgs b/sim/testsuite/sim/sh64/media/subl.cgs new file mode 100644 index 00000000000..98abe59f666 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/subl.cgs @@ -0,0 +1,38 @@ +# sh testcase for sub.l $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + +init: + pta wrong, tr0 + +subl1: + # Test that the top 32 bits are ignored. + movi 1, r0 + shlli r0, 32, r0 + ori r0, 7, r0 + + movi 1, r1 + shlli r1, 32, r1 + ori r1, 2, r1 + + sub.l r0, r1, r2 + bnei r2, 5, tr0 + +subl2: + # Test that 0 - 1 is sign extended. + movi 0, r0 + movi 1, r1 + sub.l r0, r1, r2 + addi r2, 1, r2 + bnei r2, 0, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/media/swapq.cgs b/sim/testsuite/sim/sh64/media/swapq.cgs new file mode 100644 index 00000000000..6f168b1ff48 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/swapq.cgs @@ -0,0 +1,36 @@ +# sh testcase for swap.q $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + movi 10, r0 + shlli r0, 8, r0 + ori r0, 20, r0 + shlli r0, 8, r0 + ori r0, 30, r0 + shlli r0, 8, r0 + ori r0, 40, r0 + shlli r0, 8, r0 + ori r0, 50, r0 + shlli r0, 8, r0 + ori r0, 60, r0 + shlli r0, 8, r0 + ori r0, 70, r0 + shlli r0, 8, r0 + ori r0, 80, r0 + + # Set up two address operands. + + movi 40, r1 + shlli r1, 8, r1 + movi 8, r2 + +swapq: + swap.q r1, r2, r0 + +okay: + pass diff --git a/sim/testsuite/sim/sh64/media/synci.cgs b/sim/testsuite/sim/sh64/media/synci.cgs new file mode 100644 index 00000000000..65e06213a50 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/synci.cgs @@ -0,0 +1,10 @@ +# sh testcase for synci -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + synci + pass diff --git a/sim/testsuite/sim/sh64/media/synco.cgs b/sim/testsuite/sim/sh64/media/synco.cgs new file mode 100644 index 00000000000..2db6df343d4 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/synco.cgs @@ -0,0 +1,10 @@ +# sh testcase for synco -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + synco + pass diff --git a/sim/testsuite/sim/sh64/media/testutils.inc b/sim/testsuite/sim/sh64/media/testutils.inc new file mode 100644 index 00000000000..d3b383a1efb --- /dev/null +++ b/sim/testsuite/sim/sh64/media/testutils.inc @@ -0,0 +1,51 @@ +# Support macros for the assembly test cases. + + .macro start + .text + .global start +start: + .endm + + .macro pass + movi 253, r0 + trapa r0 + .endm + + .macro fail + movi 254, r0 + trapa r0 + .endm + + .macro _packb v1 v2 v3 v4 v5 v6 v7 v8 reg + movi \v1, \reg + shlli \reg, 8, \reg + addi \reg, \v2, \reg + shlli \reg, 8, \reg + addi \reg, \v3, \reg + shlli \reg, 8, \reg + addi \reg, \v4, \reg + shlli \reg, 8, \reg + addi \reg, \v5, \reg + shlli \reg, 8, \reg + addi \reg, \v6, \reg + shlli \reg, 8, \reg + addi \reg, \v7, \reg + shlli \reg, 8, \reg + addi \reg, \v8, \reg + .endm + + .macro _packw v1 v2 v3 v4 reg + movi \v1, \reg + shlli \reg, 16, \reg + addi \reg, \v2, \reg + shlli \reg, 16, \reg + addi \reg, \v3, \reg + shlli \reg, 16, \reg + addi \reg, \v4, \reg + .endm + + .macro _packl v1 v2 reg + movi \v1, \reg + shlli \reg, 32, \reg + addi \reg, \v2, \reg + .endm diff --git a/sim/testsuite/sim/sh64/media/trapa.cgs b/sim/testsuite/sim/sh64/media/trapa.cgs new file mode 100644 index 00000000000..c961bac73ba --- /dev/null +++ b/sim/testsuite/sim/sh64/media/trapa.cgs @@ -0,0 +1,11 @@ +# sh testcase for trapa $rm -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start + # This performs a trap to emit "pass". + movi 253, r0 + trapa r0 diff --git a/sim/testsuite/sim/sh64/media/xor.cgs b/sim/testsuite/sim/sh64/media/xor.cgs new file mode 100644 index 00000000000..80278f0a3e0 --- /dev/null +++ b/sim/testsuite/sim/sh64/media/xor.cgs @@ -0,0 +1,54 @@ +# sh testcase for xor $rm, $rn, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +xor1: + # 0 xor 0 = 0. + movi 0, r0 + movi 0, r1 + xor r0, r1, r2 + bnei r2, 0, tr0 + +xor2: + # 0 xor 1 = 1. + movi 0, r0 + movi 1, r1 + xor r0, r1, r2 + bnei r2, 1, tr0 + +xor3: + # 1 xor 0 = 1. + movi 1, r0 + movi 0, r1 + xor r0, r1, r2 + bnei r2, 1, tr0 + +xor4: + # 1 xor 1 = 0. + movi 1, r0 + movi 1, r1 + xor r0, r1, r2 + bnei r2, 0, tr0 + +xor5: + movi 1, r0 + shlli r0, 63, r0 + ori r0, 1, r0 + movi 3, r1 + xor r0, r1, r2 + andi r2, 255, r2 + bnei r2, 2, tr0 + +okay: + pass + +wrong: + fail + diff --git a/sim/testsuite/sim/sh64/media/xori.cgs b/sim/testsuite/sim/sh64/media/xori.cgs new file mode 100644 index 00000000000..0d4d96a779d --- /dev/null +++ b/sim/testsuite/sim/sh64/media/xori.cgs @@ -0,0 +1,48 @@ +# sh testcase for xori $rm, $imm6, $rd -*- Asm -*- +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + + .include "media/testutils.inc" + + start +init: + pta wrong, tr0 + +xori1: + # 0 xor 0 = 0. + movi 0, r0 + xori r0, 0, r2 + bnei r2, 0, tr0 + +xori2: + # 0 xor 1 = 1. + movi 0, r0 + xori r0, 1, r2 + bnei r2, 1, tr0 + +xori3: + # 1 xor 0 = 1. + movi 1, r0 + xori r0, 0, r2 + bnei r2, 1, tr0 + +xori4: + # 1 xor 1 = 0. + movi 1, r0 + xori r0, 1, r2 + bnei r2, 0, tr0 + +xori5: + movi 1, r0 + shlli r0, 63, r0 + ori r0, 1, r0 + xori r0, 3, r2 + andi r2, 255, r2 + bnei r2, 2, tr0 + +okay: + pass + +wrong: + fail diff --git a/sim/testsuite/sim/sh64/misc/fr-dr.s b/sim/testsuite/sim/sh64/misc/fr-dr.s new file mode 100644 index 00000000000..52f0e136638 --- /dev/null +++ b/sim/testsuite/sim/sh64/misc/fr-dr.s @@ -0,0 +1,22 @@ +# sh testcase for floating point register shared state (see below). +# mach: all +# as: -isa=shmedia +# ld: -m shelf64 + +# (fr, dr, fp, fv amd mtrx provide different views of the same architecrual state). +# Hitachi SH-5 CPU volume 1, p. 15. + + .include "media/testutils.inc" + + start + + movi 42, r0 + fmov.ls r0, fr12 + # save this reg. + fmov.s fr12, fr14 + + movi 42, r0 + fmov.qd r0, dr12 + +okay: + pass -- 2.47.3