From 2f08bcee12ea0d2a232be465f3f73578d1f8636a Mon Sep 17 00:00:00 2001 From: Sasha Levin Date: Fri, 12 Mar 2021 23:07:13 -0500 Subject: [PATCH] Fixes for 5.4 Signed-off-by: Sasha Levin --- ...psr_nzcv-instead-of-r15-as-mrc-opera.patch | 89 ++++ ...ce-sun-solaris-style-flag-on-section.patch | 435 ++++++++++++++++++ ...ce-the-sole-use-of-a-symbol-with-its.patch | 54 +++ ...fpu-assembler-directives-instead-of-.patch | 127 +++++ ...fp-assembler-mnemonics-in-register-l.patch | 104 +++++ ...vfp-assembler-mnemonics-if-available.patch | 191 ++++++++ ...ig-cpu_big_endian-depends-on-ld_is_l.patch | 39 ++ ...iwmmxt.s-support-clang-s-integrated-.patch | 214 +++++++++ .../arm-omap2-drop-unnecessary-adrl.patch | 43 ++ ...-ce-define-fpu-before-fpu-registers-.patch | 56 +++ ...6-neon-avoid-adrl-pseudo-instruction.patch | 78 ++++ ...2-neon-avoid-adrl-pseudo-instruction.patch | 78 ++++ ...config-based-compiler-checks-for-cry.patch | 185 ++++++++ ...add-support-for-the-new-lightspeed-c.patch | 61 +++ ...irq-code-to-minimize-hw-race-conditi.patch | 65 +++ ...e-cacheline-to-minimize-hw-race-cond.patch | 46 ++ .../i40e-fix-memory-leak-in-i40e_probe.patch | 39 ++ ...on-t-wait-for-responses-to-commands-.patch | 97 ++++ ...x-performance-counter-initialization.patch | 117 +++++ queue-5.4/kbuild-add-config_ld_is_lld.patch | 44 ++ ...rt-for-as-instr-to-be-used-in-kconfi.patch | 48 ++ queue-5.4/kbuild-clamp-sublevel-to-255.patch | 52 +++ ...-race-condition-between-msdc_request.patch | 85 ++++ ...a-resource-leak-in-an-error-handling.patch | 37 ++ ...ix-pci_register_io_range-memory-leak.patch | 81 ++++ ...-missing-of_node_put-to-fix-referenc.patch | 66 +++ ...x-race-in-installing-chained-irq-han.patch | 50 ++ ...atform-olpc-fix-probe-error-handling.patch | 60 +++ ...tack-trace-not-displaying-final-fram.patch | 113 +++++ ...handling-of-unrecoverable-system-res.patch | 41 ++ ...powerpc-pci-add-ppc_md.discover_phbs.patch | 90 ++++ ...ord-counter-overflow-always-if-sampl.patch | 80 ++++ ...escan_cpus-move-cpumask-away-from-st.patch | 36 ++ ...x-iscsi_prep_scsi_cmd_pdu-error-hand.patch | 50 ++ ...-add-cmd-length-set-before-cmd-compl.patch | 77 ++++ ...-prevent-underflow-for-service-actio.patch | 102 ++++ queue-5.4/series | 41 ++ ...it-memblock-allocation-to-low-memory.patch | 42 ++ ..._validate_flags-to-validate-adi-flag.patch | 108 +++++ ...purious-and-overrun-interrupts-visib.patch | 60 +++ ...erflow-value-setting-risk-in-vm_tabl.patch | 73 +++ ...ix-silent-aed-taglocation-corruption.patch | 53 +++ 42 files changed, 3607 insertions(+) create mode 100644 queue-5.4/arm-8929-1-use-apsr_nzcv-instead-of-r15-as-mrc-opera.patch create mode 100644 queue-5.4/arm-8933-1-replace-sun-solaris-style-flag-on-section.patch create mode 100644 queue-5.4/arm-8971-1-replace-the-sole-use-of-a-symbol-with-its.patch create mode 100644 queue-5.4/arm-8989-1-use-.fpu-assembler-directives-instead-of-.patch create mode 100644 queue-5.4/arm-8990-1-use-vfp-assembler-mnemonics-in-register-l.patch create mode 100644 queue-5.4/arm-8991-1-use-vfp-assembler-mnemonics-if-available.patch create mode 100644 queue-5.4/arm-9025-1-kconfig-cpu_big_endian-depends-on-ld_is_l.patch create mode 100644 queue-5.4/arm-9029-1-make-iwmmxt.s-support-clang-s-integrated-.patch create mode 100644 queue-5.4/arm-omap2-drop-unnecessary-adrl.patch create mode 100644 queue-5.4/crypto-arm-ghash-ce-define-fpu-before-fpu-registers-.patch create mode 100644 queue-5.4/crypto-arm-sha256-neon-avoid-adrl-pseudo-instruction.patch create mode 100644 queue-5.4/crypto-arm-sha512-neon-avoid-adrl-pseudo-instruction.patch create mode 100644 queue-5.4/crypto-arm-use-kconfig-based-compiler-checks-for-cry.patch create mode 100644 queue-5.4/hid-logitech-dj-add-support-for-the-new-lightspeed-c.patch create mode 100644 queue-5.4/i2c-rcar-faster-irq-code-to-minimize-hw-race-conditi.patch create mode 100644 queue-5.4/i2c-rcar-optimize-cacheline-to-minimize-hw-race-cond.patch create mode 100644 queue-5.4/i40e-fix-memory-leak-in-i40e_probe.patch create mode 100644 queue-5.4/input-applespi-don-t-wait-for-responses-to-commands-.patch create mode 100644 queue-5.4/iommu-amd-fix-performance-counter-initialization.patch create mode 100644 queue-5.4/kbuild-add-config_ld_is_lld.patch create mode 100644 queue-5.4/kbuild-add-support-for-as-instr-to-be-used-in-kconfi.patch create mode 100644 queue-5.4/kbuild-clamp-sublevel-to-255.patch create mode 100644 queue-5.4/mmc-mediatek-fix-race-condition-between-msdc_request.patch create mode 100644 queue-5.4/mmc-mxs-mmc-fix-a-resource-leak-in-an-error-handling.patch create mode 100644 queue-5.4/pci-fix-pci_register_io_range-memory-leak.patch create mode 100644 queue-5.4/pci-mediatek-add-missing-of_node_put-to-fix-referenc.patch create mode 100644 queue-5.4/pci-xgene-msi-fix-race-in-installing-chained-irq-han.patch create mode 100644 queue-5.4/platform-olpc-fix-probe-error-handling.patch create mode 100644 queue-5.4/powerpc-64-fix-stack-trace-not-displaying-final-fram.patch create mode 100644 queue-5.4/powerpc-improve-handling-of-unrecoverable-system-res.patch create mode 100644 queue-5.4/powerpc-pci-add-ppc_md.discover_phbs.patch create mode 100644 queue-5.4/powerpc-perf-record-counter-overflow-always-if-sampl.patch create mode 100644 queue-5.4/s390-smp-__smp_rescan_cpus-move-cpumask-away-from-st.patch create mode 100644 queue-5.4/scsi-libiscsi-fix-iscsi_prep_scsi_cmd_pdu-error-hand.patch create mode 100644 queue-5.4/scsi-target-core-add-cmd-length-set-before-cmd-compl.patch create mode 100644 queue-5.4/scsi-target-core-prevent-underflow-for-service-actio.patch create mode 100644 queue-5.4/sparc32-limit-memblock-allocation-to-low-memory.patch create mode 100644 queue-5.4/sparc64-use-arch_validate_flags-to-validate-adi-flag.patch create mode 100644 queue-5.4/spi-stm32-make-spurious-and-overrun-interrupts-visib.patch create mode 100644 queue-5.4/sysctl.c-fix-underflow-value-setting-risk-in-vm_tabl.patch create mode 100644 queue-5.4/udf-fix-silent-aed-taglocation-corruption.patch diff --git a/queue-5.4/arm-8929-1-use-apsr_nzcv-instead-of-r15-as-mrc-opera.patch b/queue-5.4/arm-8929-1-use-apsr_nzcv-instead-of-r15-as-mrc-opera.patch new file mode 100644 index 00000000000..6737dfdbcaa --- /dev/null +++ b/queue-5.4/arm-8929-1-use-apsr_nzcv-instead-of-r15-as-mrc-opera.patch @@ -0,0 +1,89 @@ +From 69b6a376f0e52ebd9075607992c6c979d7fe95e0 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 3 Nov 2019 19:22:06 +0100 +Subject: ARM: 8929/1: use APSR_nzcv instead of r15 as mrc operand + +From: Stefan Agner + +commit 9f1984c6ae30e2a379751339ce3375a21099b5d4 upstream. + +LLVM's integrated assembler does not accept r15 as mrc operand. + arch/arm/boot/compressed/head.S:1267:16: error: operand must be a register in range [r0, r14] or apsr_nzcv + 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache + ^ + +Use APSR_nzcv instead of r15. The GNU assembler supports this +syntax since binutils 2.21 [0]. + +[0] https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commit;h=db472d6ff0f438a21b357249a9b48e4b74498076 + +Signed-off-by: Stefan Agner +Signed-off-by: Russell King +Signed-off-by: Nick Desaulniers +Signed-off-by: Sasha Levin +--- + arch/arm/boot/compressed/head.S | 2 +- + arch/arm/mm/proc-arm1026.S | 4 ++-- + arch/arm/mm/proc-arm926.S | 4 ++-- + 3 files changed, 5 insertions(+), 5 deletions(-) + +diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S +index cbe126297f54..ff80252f1980 100644 +--- a/arch/arm/boot/compressed/head.S ++++ b/arch/arm/boot/compressed/head.S +@@ -1273,7 +1273,7 @@ iflush: + __armv5tej_mmu_cache_flush: + tst r4, #1 + movne pc, lr +-1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache ++1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate D cache + bne 1b + mcr p15, 0, r0, c7, c5, 0 @ flush I cache + mcr p15, 0, r0, c7, c10, 4 @ drain WB +diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S +index ac5afde12f35..e927187157d7 100644 +--- a/arch/arm/mm/proc-arm1026.S ++++ b/arch/arm/mm/proc-arm1026.S +@@ -138,7 +138,7 @@ ENTRY(arm1026_flush_kern_cache_all) + mov ip, #0 + __flush_whole_cache: + #ifndef CONFIG_CPU_DCACHE_DISABLE +-1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate ++1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test, clean, invalidate + bne 1b + #endif + tst r2, #VM_EXEC +@@ -363,7 +363,7 @@ ENTRY(cpu_arm1026_switch_mm) + #ifdef CONFIG_MMU + mov r1, #0 + #ifndef CONFIG_CPU_DCACHE_DISABLE +-1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate ++1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test, clean, invalidate + bne 1b + #endif + #ifndef CONFIG_CPU_ICACHE_DISABLE +diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S +index f3cd08f353f0..4ef89e1d1127 100644 +--- a/arch/arm/mm/proc-arm926.S ++++ b/arch/arm/mm/proc-arm926.S +@@ -131,7 +131,7 @@ __flush_whole_cache: + #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH + mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache + #else +-1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate ++1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate + bne 1b + #endif + tst r2, #VM_EXEC +@@ -358,7 +358,7 @@ ENTRY(cpu_arm926_switch_mm) + mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache + #else + @ && 'Clean & Invalidate whole DCache' +-1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate ++1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate + bne 1b + #endif + mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache +-- +2.30.1 + diff --git a/queue-5.4/arm-8933-1-replace-sun-solaris-style-flag-on-section.patch b/queue-5.4/arm-8933-1-replace-sun-solaris-style-flag-on-section.patch new file mode 100644 index 00000000000..837f4f02b25 --- /dev/null +++ b/queue-5.4/arm-8933-1-replace-sun-solaris-style-flag-on-section.patch @@ -0,0 +1,435 @@ +From 9591e2abfa3733d280d5306d3bfcc233064ac6f3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 4 Nov 2019 19:31:45 +0100 +Subject: ARM: 8933/1: replace Sun/Solaris style flag on section directive + +From: Nick Desaulniers + +commit 790756c7e0229dedc83bf058ac69633045b1000e upstream. + +It looks like a section directive was using "Solaris style" to declare +the section flags. Replace this with the GNU style so that Clang's +integrated assembler can assemble this directive. + +The modified instances were identified via: +$ ag \.section | grep # + +Link: https://ftp.gnu.org/old-gnu/Manuals/gas-2.9.1/html_chapter/as_7.html#SEC119 +Link: https://github.com/ClangBuiltLinux/linux/issues/744 +Link: https://bugs.llvm.org/show_bug.cgi?id=43759 +Link: https://reviews.llvm.org/D69296 + +Acked-by: Nicolas Pitre +Reviewed-by: Ard Biesheuvel +Reviewed-by: Stefan Agner +Signed-off-by: Nick Desaulniers +Suggested-by: Fangrui Song +Suggested-by: Jian Cai +Suggested-by: Peter Smith +Signed-off-by: Russell King +Signed-off-by: Sasha Levin +--- + arch/arm/boot/bootp/init.S | 2 +- + arch/arm/boot/compressed/big-endian.S | 2 +- + arch/arm/boot/compressed/head.S | 2 +- + arch/arm/boot/compressed/piggy.S | 2 +- + arch/arm/mm/proc-arm1020.S | 2 +- + arch/arm/mm/proc-arm1020e.S | 2 +- + arch/arm/mm/proc-arm1022.S | 2 +- + arch/arm/mm/proc-arm1026.S | 2 +- + arch/arm/mm/proc-arm720.S | 2 +- + arch/arm/mm/proc-arm740.S | 2 +- + arch/arm/mm/proc-arm7tdmi.S | 2 +- + arch/arm/mm/proc-arm920.S | 2 +- + arch/arm/mm/proc-arm922.S | 2 +- + arch/arm/mm/proc-arm925.S | 2 +- + arch/arm/mm/proc-arm926.S | 2 +- + arch/arm/mm/proc-arm940.S | 2 +- + arch/arm/mm/proc-arm946.S | 2 +- + arch/arm/mm/proc-arm9tdmi.S | 2 +- + arch/arm/mm/proc-fa526.S | 2 +- + arch/arm/mm/proc-feroceon.S | 2 +- + arch/arm/mm/proc-mohawk.S | 2 +- + arch/arm/mm/proc-sa110.S | 2 +- + arch/arm/mm/proc-sa1100.S | 2 +- + arch/arm/mm/proc-v6.S | 2 +- + arch/arm/mm/proc-v7.S | 2 +- + arch/arm/mm/proc-v7m.S | 4 ++-- + arch/arm/mm/proc-xsc3.S | 2 +- + arch/arm/mm/proc-xscale.S | 2 +- + 28 files changed, 29 insertions(+), 29 deletions(-) + +diff --git a/arch/arm/boot/bootp/init.S b/arch/arm/boot/bootp/init.S +index 5c476bd2b4ce..b562da2f7040 100644 +--- a/arch/arm/boot/bootp/init.S ++++ b/arch/arm/boot/bootp/init.S +@@ -13,7 +13,7 @@ + * size immediately following the kernel, we could build this into + * a binary blob, and concatenate the zImage using the cat command. + */ +- .section .start,#alloc,#execinstr ++ .section .start, "ax" + .type _start, #function + .globl _start + +diff --git a/arch/arm/boot/compressed/big-endian.S b/arch/arm/boot/compressed/big-endian.S +index 88e2a88d324b..0e092c36da2f 100644 +--- a/arch/arm/boot/compressed/big-endian.S ++++ b/arch/arm/boot/compressed/big-endian.S +@@ -6,7 +6,7 @@ + * Author: Nicolas Pitre + */ + +- .section ".start", #alloc, #execinstr ++ .section ".start", "ax" + + mrc p15, 0, r0, c1, c0, 0 @ read control reg + orr r0, r0, #(1 << 7) @ enable big endian mode +diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S +index ff80252f1980..56a0275ceebf 100644 +--- a/arch/arm/boot/compressed/head.S ++++ b/arch/arm/boot/compressed/head.S +@@ -140,7 +140,7 @@ + #endif + .endm + +- .section ".start", #alloc, #execinstr ++ .section ".start", "ax" + /* + * sort out different calling conventions + */ +diff --git a/arch/arm/boot/compressed/piggy.S b/arch/arm/boot/compressed/piggy.S +index 0284f84dcf38..27577644ee72 100644 +--- a/arch/arm/boot/compressed/piggy.S ++++ b/arch/arm/boot/compressed/piggy.S +@@ -1,5 +1,5 @@ + /* SPDX-License-Identifier: GPL-2.0 */ +- .section .piggydata,#alloc ++ .section .piggydata, "a" + .globl input_data + input_data: + .incbin "arch/arm/boot/compressed/piggy_data" +diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S +index 4fa5371bc662..2785da387c91 100644 +--- a/arch/arm/mm/proc-arm1020.S ++++ b/arch/arm/mm/proc-arm1020.S +@@ -491,7 +491,7 @@ cpu_arm1020_name: + + .align + +- .section ".proc.info.init", #alloc ++ .section ".proc.info.init", "a" + + .type __arm1020_proc_info,#object + __arm1020_proc_info: +diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S +index 5d8a8339e09a..e9ea237ed785 100644 +--- a/arch/arm/mm/proc-arm1020e.S ++++ b/arch/arm/mm/proc-arm1020e.S +@@ -449,7 +449,7 @@ arm1020e_crval: + + .align + +- .section ".proc.info.init", #alloc ++ .section ".proc.info.init", "a" + + .type __arm1020e_proc_info,#object + __arm1020e_proc_info: +diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S +index b3dd95c345e4..920c279e7879 100644 +--- a/arch/arm/mm/proc-arm1022.S ++++ b/arch/arm/mm/proc-arm1022.S +@@ -443,7 +443,7 @@ arm1022_crval: + + .align + +- .section ".proc.info.init", #alloc ++ .section ".proc.info.init", "a" + + .type __arm1022_proc_info,#object + __arm1022_proc_info: +diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S +index e927187157d7..0bdf25a95b10 100644 +--- a/arch/arm/mm/proc-arm1026.S ++++ b/arch/arm/mm/proc-arm1026.S +@@ -437,7 +437,7 @@ arm1026_crval: + string cpu_arm1026_name, "ARM1026EJ-S" + .align + +- .section ".proc.info.init", #alloc ++ .section ".proc.info.init", "a" + + .type __arm1026_proc_info,#object + __arm1026_proc_info: +diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S +index c99d24363f32..39361e196d61 100644 +--- a/arch/arm/mm/proc-arm720.S ++++ b/arch/arm/mm/proc-arm720.S +@@ -172,7 +172,7 @@ arm720_crval: + * See for a definition of this structure. + */ + +- .section ".proc.info.init", #alloc ++ .section ".proc.info.init", "a" + + .macro arm720_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cpu_flush:req + .type __\name\()_proc_info,#object +diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S +index 1b4a3838393f..1a94bbf6e53f 100644 +--- a/arch/arm/mm/proc-arm740.S ++++ b/arch/arm/mm/proc-arm740.S +@@ -128,7 +128,7 @@ __arm740_setup: + + .align + +- .section ".proc.info.init", #alloc ++ .section ".proc.info.init", "a" + .type __arm740_proc_info,#object + __arm740_proc_info: + .long 0x41807400 +diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S +index 17a4687065c7..52b66cf0259e 100644 +--- a/arch/arm/mm/proc-arm7tdmi.S ++++ b/arch/arm/mm/proc-arm7tdmi.S +@@ -72,7 +72,7 @@ __arm7tdmi_setup: + + .align + +- .section ".proc.info.init", #alloc ++ .section ".proc.info.init", "a" + + .macro arm7tdmi_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, \ + extra_hwcaps=0 +diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S +index 298c76b47749..31ac8acc34dc 100644 +--- a/arch/arm/mm/proc-arm920.S ++++ b/arch/arm/mm/proc-arm920.S +@@ -434,7 +434,7 @@ arm920_crval: + + .align + +- .section ".proc.info.init", #alloc ++ .section ".proc.info.init", "a" + + .type __arm920_proc_info,#object + __arm920_proc_info: +diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S +index 824be3a0bc23..ca2c7ca8af21 100644 +--- a/arch/arm/mm/proc-arm922.S ++++ b/arch/arm/mm/proc-arm922.S +@@ -412,7 +412,7 @@ arm922_crval: + + .align + +- .section ".proc.info.init", #alloc ++ .section ".proc.info.init", "a" + + .type __arm922_proc_info,#object + __arm922_proc_info: +diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S +index d40cff8f102c..a381a0c9f109 100644 +--- a/arch/arm/mm/proc-arm925.S ++++ b/arch/arm/mm/proc-arm925.S +@@ -477,7 +477,7 @@ arm925_crval: + + .align + +- .section ".proc.info.init", #alloc ++ .section ".proc.info.init", "a" + + .macro arm925_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache + .type __\name\()_proc_info,#object +diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S +index 4ef89e1d1127..1ba253c2bce1 100644 +--- a/arch/arm/mm/proc-arm926.S ++++ b/arch/arm/mm/proc-arm926.S +@@ -460,7 +460,7 @@ arm926_crval: + + .align + +- .section ".proc.info.init", #alloc ++ .section ".proc.info.init", "a" + + .type __arm926_proc_info,#object + __arm926_proc_info: +diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S +index 1c26d991386d..4b8a00220cc9 100644 +--- a/arch/arm/mm/proc-arm940.S ++++ b/arch/arm/mm/proc-arm940.S +@@ -340,7 +340,7 @@ __arm940_setup: + + .align + +- .section ".proc.info.init", #alloc ++ .section ".proc.info.init", "a" + + .type __arm940_proc_info,#object + __arm940_proc_info: +diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S +index 2dc1c75a4fd4..555becf9c758 100644 +--- a/arch/arm/mm/proc-arm946.S ++++ b/arch/arm/mm/proc-arm946.S +@@ -395,7 +395,7 @@ __arm946_setup: + + .align + +- .section ".proc.info.init", #alloc ++ .section ".proc.info.init", "a" + .type __arm946_proc_info,#object + __arm946_proc_info: + .long 0x41009460 +diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S +index 913c06e590af..ef517530130b 100644 +--- a/arch/arm/mm/proc-arm9tdmi.S ++++ b/arch/arm/mm/proc-arm9tdmi.S +@@ -66,7 +66,7 @@ __arm9tdmi_setup: + + .align + +- .section ".proc.info.init", #alloc ++ .section ".proc.info.init", "a" + + .macro arm9tdmi_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req + .type __\name\()_proc_info, #object +diff --git a/arch/arm/mm/proc-fa526.S b/arch/arm/mm/proc-fa526.S +index 8120b6f4dbb8..dddf833fe000 100644 +--- a/arch/arm/mm/proc-fa526.S ++++ b/arch/arm/mm/proc-fa526.S +@@ -185,7 +185,7 @@ fa526_cr1_set: + + .align + +- .section ".proc.info.init", #alloc ++ .section ".proc.info.init", "a" + + .type __fa526_proc_info,#object + __fa526_proc_info: +diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S +index bb6dc34d42a3..b12b76bc8d30 100644 +--- a/arch/arm/mm/proc-feroceon.S ++++ b/arch/arm/mm/proc-feroceon.S +@@ -571,7 +571,7 @@ feroceon_crval: + + .align + +- .section ".proc.info.init", #alloc ++ .section ".proc.info.init", "a" + + .macro feroceon_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache:req + .type __\name\()_proc_info,#object +diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S +index f08308578885..d47d6c5cee63 100644 +--- a/arch/arm/mm/proc-mohawk.S ++++ b/arch/arm/mm/proc-mohawk.S +@@ -416,7 +416,7 @@ mohawk_crval: + + .align + +- .section ".proc.info.init", #alloc ++ .section ".proc.info.init", "a" + + .type __88sv331x_proc_info,#object + __88sv331x_proc_info: +diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S +index d5bc5d702563..baba503ba816 100644 +--- a/arch/arm/mm/proc-sa110.S ++++ b/arch/arm/mm/proc-sa110.S +@@ -196,7 +196,7 @@ sa110_crval: + + .align + +- .section ".proc.info.init", #alloc ++ .section ".proc.info.init", "a" + + .type __sa110_proc_info,#object + __sa110_proc_info: +diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S +index be7b611c76c7..75ebacc8e4e5 100644 +--- a/arch/arm/mm/proc-sa1100.S ++++ b/arch/arm/mm/proc-sa1100.S +@@ -239,7 +239,7 @@ sa1100_crval: + + .align + +- .section ".proc.info.init", #alloc ++ .section ".proc.info.init", "a" + + .macro sa1100_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req + .type __\name\()_proc_info,#object +diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S +index c1c85eb3484f..1dd0d5ca27da 100644 +--- a/arch/arm/mm/proc-v6.S ++++ b/arch/arm/mm/proc-v6.S +@@ -261,7 +261,7 @@ v6_crval: + string cpu_elf_name, "v6" + .align + +- .section ".proc.info.init", #alloc ++ .section ".proc.info.init", "a" + + /* + * Match any ARMv6 processor core. +diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S +index c4e8006a1a8c..48e0ef6f0dcc 100644 +--- a/arch/arm/mm/proc-v7.S ++++ b/arch/arm/mm/proc-v7.S +@@ -644,7 +644,7 @@ __v7_setup_stack: + string cpu_elf_name, "v7" + .align + +- .section ".proc.info.init", #alloc ++ .section ".proc.info.init", "a" + + /* + * Standard v7 proc info content +diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S +index 1a49d503eafc..84459c1d31b8 100644 +--- a/arch/arm/mm/proc-v7m.S ++++ b/arch/arm/mm/proc-v7m.S +@@ -93,7 +93,7 @@ ENTRY(cpu_cm7_proc_fin) + ret lr + ENDPROC(cpu_cm7_proc_fin) + +- .section ".init.text", #alloc, #execinstr ++ .section ".init.text", "ax" + + __v7m_cm7_setup: + mov r8, #(V7M_SCB_CCR_DC | V7M_SCB_CCR_IC| V7M_SCB_CCR_BP) +@@ -177,7 +177,7 @@ ENDPROC(__v7m_setup) + string cpu_elf_name "v7m" + string cpu_v7m_name "ARMv7-M" + +- .section ".proc.info.init", #alloc ++ .section ".proc.info.init", "a" + + .macro __v7m_proc name, initfunc, cache_fns = nop_cache_fns, hwcaps = 0, proc_fns = v7m_processor_functions + .long 0 /* proc_info_list.__cpu_mm_mmu_flags */ +diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S +index 1ac0fbbe9f12..42eaecc43cfe 100644 +--- a/arch/arm/mm/proc-xsc3.S ++++ b/arch/arm/mm/proc-xsc3.S +@@ -496,7 +496,7 @@ xsc3_crval: + + .align + +- .section ".proc.info.init", #alloc ++ .section ".proc.info.init", "a" + + .macro xsc3_proc_info name:req, cpu_val:req, cpu_mask:req + .type __\name\()_proc_info,#object +diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S +index bdb2b7749b03..18ac5a1f8922 100644 +--- a/arch/arm/mm/proc-xscale.S ++++ b/arch/arm/mm/proc-xscale.S +@@ -610,7 +610,7 @@ xscale_crval: + + .align + +- .section ".proc.info.init", #alloc ++ .section ".proc.info.init", "a" + + .macro xscale_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache + .type __\name\()_proc_info,#object +-- +2.30.1 + diff --git a/queue-5.4/arm-8971-1-replace-the-sole-use-of-a-symbol-with-its.patch b/queue-5.4/arm-8971-1-replace-the-sole-use-of-a-symbol-with-its.patch new file mode 100644 index 00000000000..30ac8ac0349 --- /dev/null +++ b/queue-5.4/arm-8971-1-replace-the-sole-use-of-a-symbol-with-its.patch @@ -0,0 +1,54 @@ +From e792b100c7cc6944af2b5094304c6a8a2b760418 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 29 Apr 2020 01:20:11 +0100 +Subject: ARM: 8971/1: replace the sole use of a symbol with its definition + +From: Jian Cai + +commit a780e485b5768e78aef087502499714901b68cc4 upstream. + +ALT_UP_B macro sets symbol up_b_offset via .equ to an expression +involving another symbol. The macro gets expanded twice when +arch/arm/kernel/sleep.S is assembled, creating a scenario where +up_b_offset is set to another expression involving symbols while its +current value is based on symbols. LLVM integrated assembler does not +allow such cases, and based on the documentation of binutils, "Values +that are based on expressions involving other symbols are allowed, but +some targets may restrict this to only being done once per assembly", so +it may be better to avoid such cases as it is not clearly stated which +targets should support or disallow them. The fix in this case is simple, +as up_b_offset has only one use, so we can replace the use with the +definition and get rid of up_b_offset. + + Link:https://github.com/ClangBuiltLinux/linux/issues/920 + + Reviewed-by: Stefan Agner + +Reviewed-by: Nick Desaulniers +Signed-off-by: Jian Cai +Signed-off-by: Russell King +Signed-off-by: Nick Desaulniers +Signed-off-by: Sasha Levin +--- + arch/arm/include/asm/assembler.h | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h +index 3546d294d55f..feac2c8b86f2 100644 +--- a/arch/arm/include/asm/assembler.h ++++ b/arch/arm/include/asm/assembler.h +@@ -269,10 +269,9 @@ + .endif ;\ + .popsection + #define ALT_UP_B(label) \ +- .equ up_b_offset, label - 9998b ;\ + .pushsection ".alt.smp.init", "a" ;\ + .long 9998b ;\ +- W(b) . + up_b_offset ;\ ++ W(b) . + (label - 9998b) ;\ + .popsection + #else + #define ALT_SMP(instr...) +-- +2.30.1 + diff --git a/queue-5.4/arm-8989-1-use-.fpu-assembler-directives-instead-of-.patch b/queue-5.4/arm-8989-1-use-.fpu-assembler-directives-instead-of-.patch new file mode 100644 index 00000000000..fb735b74b05 --- /dev/null +++ b/queue-5.4/arm-8989-1-use-.fpu-assembler-directives-instead-of-.patch @@ -0,0 +1,127 @@ +From f188b443e1858b2d1b1d57e82d0eeafcf76e469d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 9 Jul 2020 11:17:36 +0100 +Subject: ARM: 8989/1: use .fpu assembler directives instead of assembler + arguments + +From: Stefan Agner + +commit a6c30873ee4a5cc0549c1973668156381ab2c1c4 upstream. + +Explicit FPU selection has been introduced in commit 1a6be26d5b1a +("[ARM] Enable VFP to be built when non-VFP capable CPUs are selected") +to make use of assembler mnemonics for VFP instructions. + +However, clang currently does not support passing assembler flags +like this and errors out with: +clang-10: error: the clang compiler does not support '-Wa,-mfpu=softvfp+vfp' + +Make use of the .fpu assembler directives to select the floating point +hardware selectively. Also use the new unified assembler language +mnemonics. This allows to build these procedures with Clang. + +Link: https://github.com/ClangBuiltLinux/linux/issues/762 + +Signed-off-by: Stefan Agner +Signed-off-by: Russell King +Signed-off-by: Nick Desaulniers +Signed-off-by: Sasha Levin +--- + arch/arm/vfp/Makefile | 2 -- + arch/arm/vfp/vfphw.S | 30 ++++++++++++++++++++---------- + 2 files changed, 20 insertions(+), 12 deletions(-) + +diff --git a/arch/arm/vfp/Makefile b/arch/arm/vfp/Makefile +index 9975b63ac3b0..749901a72d6d 100644 +--- a/arch/arm/vfp/Makefile ++++ b/arch/arm/vfp/Makefile +@@ -8,6 +8,4 @@ + # ccflags-y := -DDEBUG + # asflags-y := -DDEBUG + +-KBUILD_AFLAGS :=$(KBUILD_AFLAGS:-msoft-float=-Wa,-mfpu=softvfp+vfp -mfloat-abi=soft) +- + obj-y += vfpmodule.o entry.o vfphw.o vfpsingle.o vfpdouble.o +diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S +index b2e560290860..29ed36b99d1d 100644 +--- a/arch/arm/vfp/vfphw.S ++++ b/arch/arm/vfp/vfphw.S +@@ -258,11 +258,14 @@ vfp_current_hw_state_address: + + ENTRY(vfp_get_float) + tbl_branch r0, r3, #3 ++ .fpu vfpv2 + .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 +-1: mrc p10, 0, r0, c\dr, c0, 0 @ fmrs r0, s0 ++1: vmov r0, s\dr + ret lr + .org 1b + 8 +-1: mrc p10, 0, r0, c\dr, c0, 4 @ fmrs r0, s1 ++ .endr ++ .irp dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 ++1: vmov r0, s\dr + ret lr + .org 1b + 8 + .endr +@@ -270,11 +273,14 @@ ENDPROC(vfp_get_float) + + ENTRY(vfp_put_float) + tbl_branch r1, r3, #3 ++ .fpu vfpv2 + .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 +-1: mcr p10, 0, r0, c\dr, c0, 0 @ fmsr r0, s0 ++1: vmov s\dr, r0 + ret lr + .org 1b + 8 +-1: mcr p10, 0, r0, c\dr, c0, 4 @ fmsr r0, s1 ++ .endr ++ .irp dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 ++1: vmov s\dr, r0 + ret lr + .org 1b + 8 + .endr +@@ -282,15 +288,17 @@ ENDPROC(vfp_put_float) + + ENTRY(vfp_get_double) + tbl_branch r0, r3, #3 ++ .fpu vfpv2 + .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 +-1: fmrrd r0, r1, d\dr ++1: vmov r0, r1, d\dr + ret lr + .org 1b + 8 + .endr + #ifdef CONFIG_VFPv3 + @ d16 - d31 registers +- .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 +-1: mrrc p11, 3, r0, r1, c\dr @ fmrrd r0, r1, d\dr ++ .fpu vfpv3 ++ .irp dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 ++1: vmov r0, r1, d\dr + ret lr + .org 1b + 8 + .endr +@@ -304,15 +312,17 @@ ENDPROC(vfp_get_double) + + ENTRY(vfp_put_double) + tbl_branch r2, r3, #3 ++ .fpu vfpv2 + .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 +-1: fmdrr d\dr, r0, r1 ++1: vmov d\dr, r0, r1 + ret lr + .org 1b + 8 + .endr + #ifdef CONFIG_VFPv3 ++ .fpu vfpv3 + @ d16 - d31 registers +- .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 +-1: mcrr p11, 3, r0, r1, c\dr @ fmdrr r0, r1, d\dr ++ .irp dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 ++1: vmov d\dr, r0, r1 + ret lr + .org 1b + 8 + .endr +-- +2.30.1 + diff --git a/queue-5.4/arm-8990-1-use-vfp-assembler-mnemonics-in-register-l.patch b/queue-5.4/arm-8990-1-use-vfp-assembler-mnemonics-in-register-l.patch new file mode 100644 index 00000000000..ad75cf46d69 --- /dev/null +++ b/queue-5.4/arm-8990-1-use-vfp-assembler-mnemonics-in-register-l.patch @@ -0,0 +1,104 @@ +From dc9a1d3f5f7a9ccc20e367dcf333c920361e8056 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 9 Jul 2020 11:19:17 +0100 +Subject: ARM: 8990/1: use VFP assembler mnemonics in register load/store + macros + +From: Stefan Agner + +commit ee440336e5ef977c397afdb72cbf9c6b8effc8ea upstream. + +The integrated assembler of Clang 10 and earlier do not allow to access +the VFP registers through the coprocessor load/store instructions: +:4:6: error: invalid operand for instruction + LDC p11, cr0, [r10],#32*4 @ FLDMIAD r10!, {d0-d15} + ^ + +This has been addressed with Clang 11 [0]. However, to support earlier +versions of Clang and for better readability use of VFP assembler +mnemonics still is preferred. + +Replace the coprocessor load/store instructions with explicit assembler +mnemonics to accessing the floating point coprocessor registers. Use +assembler directives to select the appropriate FPU version. + +This allows to build these macros with GNU assembler as well as with +Clang's built-in assembler. + +[0] https://reviews.llvm.org/D59733 + +Link: https://github.com/ClangBuiltLinux/linux/issues/905 + +Signed-off-by: Stefan Agner +Signed-off-by: Russell King +Signed-off-by: Nick Desaulniers +Signed-off-by: Sasha Levin +--- + arch/arm/include/asm/vfpmacros.h | 19 +++++++++++-------- + 1 file changed, 11 insertions(+), 8 deletions(-) + +diff --git a/arch/arm/include/asm/vfpmacros.h b/arch/arm/include/asm/vfpmacros.h +index 628c336e8e3b..947ee5395e1f 100644 +--- a/arch/arm/include/asm/vfpmacros.h ++++ b/arch/arm/include/asm/vfpmacros.h +@@ -19,23 +19,25 @@ + + @ read all the working registers back into the VFP + .macro VFPFLDMIA, base, tmp ++ .fpu vfpv2 + #if __LINUX_ARM_ARCH__ < 6 +- LDC p11, cr0, [\base],#33*4 @ FLDMIAX \base!, {d0-d15} ++ fldmiax \base!, {d0-d15} + #else +- LDC p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d0-d15} ++ vldmia \base!, {d0-d15} + #endif + #ifdef CONFIG_VFPv3 ++ .fpu vfpv3 + #if __LINUX_ARM_ARCH__ <= 6 + ldr \tmp, =elf_hwcap @ may not have MVFR regs + ldr \tmp, [\tmp, #0] + tst \tmp, #HWCAP_VFPD32 +- ldclne p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31} ++ vldmiane \base!, {d16-d31} + addeq \base, \base, #32*4 @ step over unused register space + #else + VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0 + and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field + cmp \tmp, #2 @ 32 x 64bit registers? +- ldcleq p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31} ++ vldmiaeq \base!, {d16-d31} + addne \base, \base, #32*4 @ step over unused register space + #endif + #endif +@@ -44,22 +46,23 @@ + @ write all the working registers out of the VFP + .macro VFPFSTMIA, base, tmp + #if __LINUX_ARM_ARCH__ < 6 +- STC p11, cr0, [\base],#33*4 @ FSTMIAX \base!, {d0-d15} ++ fstmiax \base!, {d0-d15} + #else +- STC p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d0-d15} ++ vstmia \base!, {d0-d15} + #endif + #ifdef CONFIG_VFPv3 ++ .fpu vfpv3 + #if __LINUX_ARM_ARCH__ <= 6 + ldr \tmp, =elf_hwcap @ may not have MVFR regs + ldr \tmp, [\tmp, #0] + tst \tmp, #HWCAP_VFPD32 +- stclne p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31} ++ vstmiane \base!, {d16-d31} + addeq \base, \base, #32*4 @ step over unused register space + #else + VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0 + and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field + cmp \tmp, #2 @ 32 x 64bit registers? +- stcleq p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31} ++ vstmiaeq \base!, {d16-d31} + addne \base, \base, #32*4 @ step over unused register space + #endif + #endif +-- +2.30.1 + diff --git a/queue-5.4/arm-8991-1-use-vfp-assembler-mnemonics-if-available.patch b/queue-5.4/arm-8991-1-use-vfp-assembler-mnemonics-if-available.patch new file mode 100644 index 00000000000..49b1d44525e --- /dev/null +++ b/queue-5.4/arm-8991-1-use-vfp-assembler-mnemonics-if-available.patch @@ -0,0 +1,191 @@ +From a79eb256aae53ac001edefe986c2264c003f3dcf Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 9 Jul 2020 11:21:27 +0100 +Subject: ARM: 8991/1: use VFP assembler mnemonics if available + +From: Stefan Agner + +commit 2cbd1cc3dcd3e84be1fc1987da24b190ddf24a70 upstream. + +The integrated assembler of Clang 10 and earlier do not allow to access +the VFP registers through the coprocessor load/store instructions: +arch/arm/vfp/vfpmodule.c:342:2: error: invalid operand for instruction + fmxr(FPEXC, fpexc & ~(FPEXC_EX|FPEXC_DEX|FPEXC_FP2V|FPEXC_VV|FPEXC_TRAP_MASK)); + ^ +arch/arm/vfp/vfpinstr.h:79:6: note: expanded from macro 'fmxr' + asm("mcr p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmxr " #_vfp_ ", %0" + ^ +:1:6: note: instantiated into assembly here + mcr p10, 7, r0, cr8, cr0, 0 @ fmxr FPEXC, r0 + ^ + +This has been addressed with Clang 11 [0]. However, to support earlier +versions of Clang and for better readability use of VFP assembler +mnemonics still is preferred. + +Ideally we would replace this code with the unified assembler language +mnemonics vmrs/vmsr on call sites along with .fpu assembler directives. +The GNU assembler supports the .fpu directive at least since 2.17 (when +documentation has been added). Since Linux requires binutils 2.21 it is +safe to use .fpu directive. However, binutils does not allow to use +FPINST or FPINST2 as an argument to vmrs/vmsr instructions up to +binutils 2.24 (see binutils commit 16d02dc907c5): +arch/arm/vfp/vfphw.S: Assembler messages: +arch/arm/vfp/vfphw.S:162: Error: operand 0 must be FPSID or FPSCR pr FPEXC -- `vmsr FPINST,r6' +arch/arm/vfp/vfphw.S:165: Error: operand 0 must be FPSID or FPSCR pr FPEXC -- `vmsr FPINST2,r8' +arch/arm/vfp/vfphw.S:235: Error: operand 1 must be a VFP extension System Register -- `vmrs r3,FPINST' +arch/arm/vfp/vfphw.S:238: Error: operand 1 must be a VFP extension System Register -- `vmrs r12,FPINST2' + +Use as-instr in Kconfig to check if FPINST/FPINST2 can be used. If they +can be used make use of .fpu directives and UAL VFP mnemonics for +register access. + +This allows to build vfpmodule.c with Clang and its integrated assembler. + +[0] https://reviews.llvm.org/D59733 + +Link: https://github.com/ClangBuiltLinux/linux/issues/905 + +Signed-off-by: Stefan Agner +Signed-off-by: Russell King +[nd: adjusted hunk from arch/arm/Kconfig due to missing + commit 8a90a3228b6a ("arm: Unplug KVM from the build system")] +Signed-off-by: Nick Desaulniers +Signed-off-by: Sasha Levin +--- + arch/arm/Kconfig | 1 + + arch/arm/Kconfig.assembler | 6 ++++++ + arch/arm/include/asm/vfp.h | 2 ++ + arch/arm/include/asm/vfpmacros.h | 12 +++++++++++- + arch/arm/vfp/vfphw.S | 1 + + arch/arm/vfp/vfpinstr.h | 23 +++++++++++++++++++---- + 6 files changed, 40 insertions(+), 5 deletions(-) + create mode 100644 arch/arm/Kconfig.assembler + +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index 9aa88715f196..d5c1dbdccf02 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -2097,3 +2097,4 @@ source "arch/arm/crypto/Kconfig" + endif + + source "arch/arm/kvm/Kconfig" ++source "arch/arm/Kconfig.assembler" +diff --git a/arch/arm/Kconfig.assembler b/arch/arm/Kconfig.assembler +new file mode 100644 +index 000000000000..5cb31aae1188 +--- /dev/null ++++ b/arch/arm/Kconfig.assembler +@@ -0,0 +1,6 @@ ++# SPDX-License-Identifier: GPL-2.0 ++ ++config AS_VFP_VMRS_FPINST ++ def_bool $(as-instr,.fpu vfpv2\nvmrs r0$(comma)FPINST) ++ help ++ Supported by binutils >= 2.24 and LLVM integrated assembler. +diff --git a/arch/arm/include/asm/vfp.h b/arch/arm/include/asm/vfp.h +index 7157d2a30a49..19928bfb4f9c 100644 +--- a/arch/arm/include/asm/vfp.h ++++ b/arch/arm/include/asm/vfp.h +@@ -9,6 +9,7 @@ + #ifndef __ASM_VFP_H + #define __ASM_VFP_H + ++#ifndef CONFIG_AS_VFP_VMRS_FPINST + #define FPSID cr0 + #define FPSCR cr1 + #define MVFR1 cr6 +@@ -16,6 +17,7 @@ + #define FPEXC cr8 + #define FPINST cr9 + #define FPINST2 cr10 ++#endif + + /* FPSID bits */ + #define FPSID_IMPLEMENTER_BIT (24) +diff --git a/arch/arm/include/asm/vfpmacros.h b/arch/arm/include/asm/vfpmacros.h +index 947ee5395e1f..ba0d4cb5377e 100644 +--- a/arch/arm/include/asm/vfpmacros.h ++++ b/arch/arm/include/asm/vfpmacros.h +@@ -8,7 +8,16 @@ + + #include + +-@ Macros to allow building with old toolkits (with no VFP support) ++#ifdef CONFIG_AS_VFP_VMRS_FPINST ++ .macro VFPFMRX, rd, sysreg, cond ++ vmrs\cond \rd, \sysreg ++ .endm ++ ++ .macro VFPFMXR, sysreg, rd, cond ++ vmsr\cond \sysreg, \rd ++ .endm ++#else ++ @ Macros to allow building with old toolkits (with no VFP support) + .macro VFPFMRX, rd, sysreg, cond + MRC\cond p10, 7, \rd, \sysreg, cr0, 0 @ FMRX \rd, \sysreg + .endm +@@ -16,6 +25,7 @@ + .macro VFPFMXR, sysreg, rd, cond + MCR\cond p10, 7, \rd, \sysreg, cr0, 0 @ FMXR \sysreg, \rd + .endm ++#endif + + @ read all the working registers back into the VFP + .macro VFPFLDMIA, base, tmp +diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S +index 29ed36b99d1d..4fcff9f59947 100644 +--- a/arch/arm/vfp/vfphw.S ++++ b/arch/arm/vfp/vfphw.S +@@ -78,6 +78,7 @@ + ENTRY(vfp_support_entry) + DBGSTR3 "instr %08x pc %08x state %p", r0, r2, r10 + ++ .fpu vfpv2 + ldr r3, [sp, #S_PSR] @ Neither lazy restore nor FP exceptions + and r3, r3, #MODE_MASK @ are supported in kernel mode + teq r3, #USR_MODE +diff --git a/arch/arm/vfp/vfpinstr.h b/arch/arm/vfp/vfpinstr.h +index 38dc154e39ff..3c7938fd40aa 100644 +--- a/arch/arm/vfp/vfpinstr.h ++++ b/arch/arm/vfp/vfpinstr.h +@@ -62,10 +62,23 @@ + #define FPSCR_C (1 << 29) + #define FPSCR_V (1 << 28) + +-/* +- * Since we aren't building with -mfpu=vfp, we need to code +- * these instructions using their MRC/MCR equivalents. +- */ ++#ifdef CONFIG_AS_VFP_VMRS_FPINST ++ ++#define fmrx(_vfp_) ({ \ ++ u32 __v; \ ++ asm(".fpu vfpv2\n" \ ++ "vmrs %0, " #_vfp_ \ ++ : "=r" (__v) : : "cc"); \ ++ __v; \ ++ }) ++ ++#define fmxr(_vfp_,_var_) \ ++ asm(".fpu vfpv2\n" \ ++ "vmsr " #_vfp_ ", %0" \ ++ : : "r" (_var_) : "cc") ++ ++#else ++ + #define vfpreg(_vfp_) #_vfp_ + + #define fmrx(_vfp_) ({ \ +@@ -79,6 +92,8 @@ + asm("mcr p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmxr " #_vfp_ ", %0" \ + : : "r" (_var_) : "cc") + ++#endif ++ + u32 vfp_single_cpdo(u32 inst, u32 fpscr); + u32 vfp_single_cprt(u32 inst, u32 fpscr, struct pt_regs *regs); + +-- +2.30.1 + diff --git a/queue-5.4/arm-9025-1-kconfig-cpu_big_endian-depends-on-ld_is_l.patch b/queue-5.4/arm-9025-1-kconfig-cpu_big_endian-depends-on-ld_is_l.patch new file mode 100644 index 00000000000..b57150a54dd --- /dev/null +++ b/queue-5.4/arm-9025-1-kconfig-cpu_big_endian-depends-on-ld_is_l.patch @@ -0,0 +1,39 @@ +From f39562cefbbf70d5689474ef63a8834cff4d7e21 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 17 Nov 2020 00:46:39 +0100 +Subject: ARM: 9025/1: Kconfig: CPU_BIG_ENDIAN depends on !LD_IS_LLD + +From: Nick Desaulniers + +commit 28187dc8ebd938d574edfc6d9e0f9c51c21ff3f4 upstream. + +LLD does not yet support any big endian architectures. Make this config +non-selectable when using LLD until LLD is fixed. + +Link: https://github.com/ClangBuiltLinux/linux/issues/965 + +Signed-off-by: Nick Desaulniers +Tested-by: Nathan Chancellor +Reviewed-by: Nathan Chancellor +Reported-by: kbuild test robot +Signed-off-by: Russell King +Signed-off-by: Sasha Levin +--- + arch/arm/mm/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig +index 0ab3a86b1f52..3888d21bcf97 100644 +--- a/arch/arm/mm/Kconfig ++++ b/arch/arm/mm/Kconfig +@@ -743,6 +743,7 @@ config SWP_EMULATE + config CPU_BIG_ENDIAN + bool "Build big-endian kernel" + depends on ARCH_SUPPORTS_BIG_ENDIAN ++ depends on !LD_IS_LLD + help + Say Y if you plan on running a kernel in big-endian mode. + Note that your board must be properly built and your board +-- +2.30.1 + diff --git a/queue-5.4/arm-9029-1-make-iwmmxt.s-support-clang-s-integrated-.patch b/queue-5.4/arm-9029-1-make-iwmmxt.s-support-clang-s-integrated-.patch new file mode 100644 index 00000000000..bf7c6b24283 --- /dev/null +++ b/queue-5.4/arm-9029-1-make-iwmmxt.s-support-clang-s-integrated-.patch @@ -0,0 +1,214 @@ +From 9bbe914b9e35319f4e06054c016c1fab0829521b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 17 Nov 2020 23:11:36 +0100 +Subject: ARM: 9029/1: Make iwmmxt.S support Clang's integrated assembler + +From: Jian Cai + +commit 3c9f5708b7aed6a963e2aefccbd1854802de163e upstream. + +This patch replaces 6 IWMMXT instructions Clang's integrated assembler +does not support in iwmmxt.S using macros, while making sure GNU +assembler still emit the same instructions. This should be easier than +providing full IWMMXT support in Clang. This is one of the last bits of +kernel code that could be compiled but not assembled with clang. Once +all of it works with IAS, we no longer need to special-case 32-bit Arm +in Kbuild, or turn off CONFIG_IWMMXT when build-testing. + +"Intel Wireless MMX Technology - Developer Guide - August, 2002" should +be referenced for the encoding schemes of these extensions. + +Link: https://github.com/ClangBuiltLinux/linux/issues/975 + +Suggested-by: Nick Desaulniers +Suggested-by: Ard Biesheuvel +Acked-by: Ard Biesheuvel +Reviewed-by: Nick Desaulniers +Tested-by: Nick Desaulniers +Signed-off-by: Jian Cai +Signed-off-by: Russell King +Signed-off-by: Nick Desaulniers +Signed-off-by: Sasha Levin +--- + arch/arm/kernel/iwmmxt.S | 89 ++++++++++++++++++++-------------------- + arch/arm/kernel/iwmmxt.h | 47 +++++++++++++++++++++ + 2 files changed, 92 insertions(+), 44 deletions(-) + create mode 100644 arch/arm/kernel/iwmmxt.h + +diff --git a/arch/arm/kernel/iwmmxt.S b/arch/arm/kernel/iwmmxt.S +index 0dcae787b004..d2b4ac06e4ed 100644 +--- a/arch/arm/kernel/iwmmxt.S ++++ b/arch/arm/kernel/iwmmxt.S +@@ -16,6 +16,7 @@ + #include + #include + #include ++#include "iwmmxt.h" + + #if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B) + #define PJ4(code...) code +@@ -113,33 +114,33 @@ concan_save: + + concan_dump: + +- wstrw wCSSF, [r1, #MMX_WCSSF] +- wstrw wCASF, [r1, #MMX_WCASF] +- wstrw wCGR0, [r1, #MMX_WCGR0] +- wstrw wCGR1, [r1, #MMX_WCGR1] +- wstrw wCGR2, [r1, #MMX_WCGR2] +- wstrw wCGR3, [r1, #MMX_WCGR3] ++ wstrw wCSSF, r1, MMX_WCSSF ++ wstrw wCASF, r1, MMX_WCASF ++ wstrw wCGR0, r1, MMX_WCGR0 ++ wstrw wCGR1, r1, MMX_WCGR1 ++ wstrw wCGR2, r1, MMX_WCGR2 ++ wstrw wCGR3, r1, MMX_WCGR3 + + 1: @ MUP? wRn + tst r2, #0x2 + beq 2f + +- wstrd wR0, [r1, #MMX_WR0] +- wstrd wR1, [r1, #MMX_WR1] +- wstrd wR2, [r1, #MMX_WR2] +- wstrd wR3, [r1, #MMX_WR3] +- wstrd wR4, [r1, #MMX_WR4] +- wstrd wR5, [r1, #MMX_WR5] +- wstrd wR6, [r1, #MMX_WR6] +- wstrd wR7, [r1, #MMX_WR7] +- wstrd wR8, [r1, #MMX_WR8] +- wstrd wR9, [r1, #MMX_WR9] +- wstrd wR10, [r1, #MMX_WR10] +- wstrd wR11, [r1, #MMX_WR11] +- wstrd wR12, [r1, #MMX_WR12] +- wstrd wR13, [r1, #MMX_WR13] +- wstrd wR14, [r1, #MMX_WR14] +- wstrd wR15, [r1, #MMX_WR15] ++ wstrd wR0, r1, MMX_WR0 ++ wstrd wR1, r1, MMX_WR1 ++ wstrd wR2, r1, MMX_WR2 ++ wstrd wR3, r1, MMX_WR3 ++ wstrd wR4, r1, MMX_WR4 ++ wstrd wR5, r1, MMX_WR5 ++ wstrd wR6, r1, MMX_WR6 ++ wstrd wR7, r1, MMX_WR7 ++ wstrd wR8, r1, MMX_WR8 ++ wstrd wR9, r1, MMX_WR9 ++ wstrd wR10, r1, MMX_WR10 ++ wstrd wR11, r1, MMX_WR11 ++ wstrd wR12, r1, MMX_WR12 ++ wstrd wR13, r1, MMX_WR13 ++ wstrd wR14, r1, MMX_WR14 ++ wstrd wR15, r1, MMX_WR15 + + 2: teq r0, #0 @ anything to load? + reteq lr @ if not, return +@@ -147,30 +148,30 @@ concan_dump: + concan_load: + + @ Load wRn +- wldrd wR0, [r0, #MMX_WR0] +- wldrd wR1, [r0, #MMX_WR1] +- wldrd wR2, [r0, #MMX_WR2] +- wldrd wR3, [r0, #MMX_WR3] +- wldrd wR4, [r0, #MMX_WR4] +- wldrd wR5, [r0, #MMX_WR5] +- wldrd wR6, [r0, #MMX_WR6] +- wldrd wR7, [r0, #MMX_WR7] +- wldrd wR8, [r0, #MMX_WR8] +- wldrd wR9, [r0, #MMX_WR9] +- wldrd wR10, [r0, #MMX_WR10] +- wldrd wR11, [r0, #MMX_WR11] +- wldrd wR12, [r0, #MMX_WR12] +- wldrd wR13, [r0, #MMX_WR13] +- wldrd wR14, [r0, #MMX_WR14] +- wldrd wR15, [r0, #MMX_WR15] ++ wldrd wR0, r0, MMX_WR0 ++ wldrd wR1, r0, MMX_WR1 ++ wldrd wR2, r0, MMX_WR2 ++ wldrd wR3, r0, MMX_WR3 ++ wldrd wR4, r0, MMX_WR4 ++ wldrd wR5, r0, MMX_WR5 ++ wldrd wR6, r0, MMX_WR6 ++ wldrd wR7, r0, MMX_WR7 ++ wldrd wR8, r0, MMX_WR8 ++ wldrd wR9, r0, MMX_WR9 ++ wldrd wR10, r0, MMX_WR10 ++ wldrd wR11, r0, MMX_WR11 ++ wldrd wR12, r0, MMX_WR12 ++ wldrd wR13, r0, MMX_WR13 ++ wldrd wR14, r0, MMX_WR14 ++ wldrd wR15, r0, MMX_WR15 + + @ Load wCx +- wldrw wCSSF, [r0, #MMX_WCSSF] +- wldrw wCASF, [r0, #MMX_WCASF] +- wldrw wCGR0, [r0, #MMX_WCGR0] +- wldrw wCGR1, [r0, #MMX_WCGR1] +- wldrw wCGR2, [r0, #MMX_WCGR2] +- wldrw wCGR3, [r0, #MMX_WCGR3] ++ wldrw wCSSF, r0, MMX_WCSSF ++ wldrw wCASF, r0, MMX_WCASF ++ wldrw wCGR0, r0, MMX_WCGR0 ++ wldrw wCGR1, r0, MMX_WCGR1 ++ wldrw wCGR2, r0, MMX_WCGR2 ++ wldrw wCGR3, r0, MMX_WCGR3 + + @ clear CUP/MUP (only if r1 != 0) + teq r1, #0 +diff --git a/arch/arm/kernel/iwmmxt.h b/arch/arm/kernel/iwmmxt.h +new file mode 100644 +index 000000000000..fb627286f5bb +--- /dev/null ++++ b/arch/arm/kernel/iwmmxt.h +@@ -0,0 +1,47 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++ ++#ifndef __IWMMXT_H__ ++#define __IWMMXT_H__ ++ ++.irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 ++.set .LwR\b, \b ++.set .Lr\b, \b ++.endr ++ ++.set .LwCSSF, 0x2 ++.set .LwCASF, 0x3 ++.set .LwCGR0, 0x8 ++.set .LwCGR1, 0x9 ++.set .LwCGR2, 0xa ++.set .LwCGR3, 0xb ++ ++.macro wldrd, reg:req, base:req, offset:req ++.inst 0xedd00100 | (.L\reg << 12) | (.L\base << 16) | (\offset >> 2) ++.endm ++ ++.macro wldrw, reg:req, base:req, offset:req ++.inst 0xfd900100 | (.L\reg << 12) | (.L\base << 16) | (\offset >> 2) ++.endm ++ ++.macro wstrd, reg:req, base:req, offset:req ++.inst 0xedc00100 | (.L\reg << 12) | (.L\base << 16) | (\offset >> 2) ++.endm ++ ++.macro wstrw, reg:req, base:req, offset:req ++.inst 0xfd800100 | (.L\reg << 12) | (.L\base << 16) | (\offset >> 2) ++.endm ++ ++#ifdef __clang__ ++ ++#define wCon c1 ++ ++.macro tmrc, dest:req, control:req ++mrc p1, 0, \dest, \control, c0, 0 ++.endm ++ ++.macro tmcr, control:req, src:req ++mcr p1, 0, \src, \control, c0, 0 ++.endm ++#endif ++ ++#endif +-- +2.30.1 + diff --git a/queue-5.4/arm-omap2-drop-unnecessary-adrl.patch b/queue-5.4/arm-omap2-drop-unnecessary-adrl.patch new file mode 100644 index 00000000000..74a902c8e6b --- /dev/null +++ b/queue-5.4/arm-omap2-drop-unnecessary-adrl.patch @@ -0,0 +1,43 @@ +From 26dea6e752254a301ac8048825811584fe419143 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 29 Mar 2020 22:33:14 +0200 +Subject: ARM: OMAP2+: drop unnecessary adrl + +From: Stefan Agner + +commit d85d5247885ef2e8192287b895c2e381fa931b0b upstream. + +The adrl instruction has been introduced with commit dd31394779aa ("ARM: +omap3: Thumb-2 compatibility for sleep34xx.S"), back when this assembly +file was considerably longer. Today adr seems to have enough reach, even +when inserting about 60 instructions between the use site and the label. +Replace adrl with conventional adr instruction. + +This allows to build this file using Clang's integrated assembler (which +does not support the adrl pseudo instruction). + +Link: https://github.com/ClangBuiltLinux/linux/issues/430 +Signed-off-by: Stefan Agner +Signed-off-by: Tony Lindgren +Signed-off-by: Nick Desaulniers +Signed-off-by: Sasha Levin +--- + arch/arm/mach-omap2/sleep34xx.S | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S +index ac1324c6453b..c4e97d35c310 100644 +--- a/arch/arm/mach-omap2/sleep34xx.S ++++ b/arch/arm/mach-omap2/sleep34xx.S +@@ -72,7 +72,7 @@ ENTRY(enable_omap3630_toggle_l2_on_restore) + stmfd sp!, {lr} @ save registers on stack + /* Setup so that we will disable and enable l2 */ + mov r1, #0x1 +- adrl r3, l2dis_3630_offset @ may be too distant for plain adr ++ adr r3, l2dis_3630_offset + ldr r2, [r3] @ value for offset + str r1, [r2, r3] @ write to l2dis_3630 + ldmfd sp!, {pc} @ restore regs and return +-- +2.30.1 + diff --git a/queue-5.4/crypto-arm-ghash-ce-define-fpu-before-fpu-registers-.patch b/queue-5.4/crypto-arm-ghash-ce-define-fpu-before-fpu-registers-.patch new file mode 100644 index 00000000000..1551d52d115 --- /dev/null +++ b/queue-5.4/crypto-arm-ghash-ce-define-fpu-before-fpu-registers-.patch @@ -0,0 +1,56 @@ +From 5ba239ae2c4aba42052d6d20e8961a5a283b19fc Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 2 Mar 2020 00:37:14 +0100 +Subject: crypto: arm/ghash-ce - define fpu before fpu registers are referenced + +From: Stefan Agner + +commit 7548bf8c17d84607c106bd45d81834afd95a2edb upstream. + +Building ARMv7 with Clang's integrated assembler leads to errors such +as: +arch/arm/crypto/ghash-ce-core.S:34:11: error: register name expected + t3l .req d16 + ^ + +Since no FPU has selected yet Clang considers d16 not a valid register. +Moving the FPU directive on-top allows Clang to parse the registers and +allows to successfully build this file with Clang's integrated assembler. + +Signed-off-by: Stefan Agner +Reviewed-by: Nick Desaulniers +Tested-by: Nick Desaulniers +Acked-by: Ard Biesheuvel +Signed-off-by: Herbert Xu +Signed-off-by: Nick Desaulniers +Signed-off-by: Sasha Levin +--- + arch/arm/crypto/ghash-ce-core.S | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/crypto/ghash-ce-core.S b/arch/arm/crypto/ghash-ce-core.S +index 534c9647726d..9f51e3fa4526 100644 +--- a/arch/arm/crypto/ghash-ce-core.S ++++ b/arch/arm/crypto/ghash-ce-core.S +@@ -8,6 +8,9 @@ + #include + #include + ++ .arch armv8-a ++ .fpu crypto-neon-fp-armv8 ++ + SHASH .req q0 + T1 .req q1 + XL .req q2 +@@ -88,8 +91,6 @@ + T3_H .req d17 + + .text +- .arch armv8-a +- .fpu crypto-neon-fp-armv8 + + .macro __pmull_p64, rd, rn, rm, b1, b2, b3, b4 + vmull.p64 \rd, \rn, \rm +-- +2.30.1 + diff --git a/queue-5.4/crypto-arm-sha256-neon-avoid-adrl-pseudo-instruction.patch b/queue-5.4/crypto-arm-sha256-neon-avoid-adrl-pseudo-instruction.patch new file mode 100644 index 00000000000..e333d32483b --- /dev/null +++ b/queue-5.4/crypto-arm-sha256-neon-avoid-adrl-pseudo-instruction.patch @@ -0,0 +1,78 @@ +From acfa070a91d36f40e89ebc4ebf968445fada0d13 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 16 Sep 2020 09:14:17 +0300 +Subject: crypto: arm/sha256-neon - avoid ADRL pseudo instruction + +From: Ard Biesheuvel + +commit 54781938ec342cadbe2d76669ef8d3294d909974 upstream. + +The ADRL pseudo instruction is not an architectural construct, but a +convenience macro that was supported by the ARM proprietary assembler +and adopted by binutils GAS as well, but only when assembling in 32-bit +ARM mode. Therefore, it can only be used in assembler code that is known +to assemble in ARM mode only, but as it turns out, the Clang assembler +does not implement ADRL at all, and so it is better to get rid of it +entirely. + +So replace the ADRL instruction with a ADR instruction that refers to +a nearer symbol, and apply the delta explicitly using an additional +instruction. + +Signed-off-by: Ard Biesheuvel +Tested-by: Nick Desaulniers +Signed-off-by: Herbert Xu +Signed-off-by: Nick Desaulniers +Signed-off-by: Sasha Levin +--- + arch/arm/crypto/sha256-armv4.pl | 4 ++-- + arch/arm/crypto/sha256-core.S_shipped | 4 ++-- + 2 files changed, 4 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/crypto/sha256-armv4.pl b/arch/arm/crypto/sha256-armv4.pl +index a03cf4dfb781..d927483985c2 100644 +--- a/arch/arm/crypto/sha256-armv4.pl ++++ b/arch/arm/crypto/sha256-armv4.pl +@@ -175,7 +175,6 @@ $code=<<___; + #else + .syntax unified + # ifdef __thumb2__ +-# define adrl adr + .thumb + # else + .code 32 +@@ -471,7 +470,8 @@ sha256_block_data_order_neon: + stmdb sp!,{r4-r12,lr} + + sub $H,sp,#16*4+16 +- adrl $Ktbl,K256 ++ adr $Ktbl,.Lsha256_block_data_order ++ sub $Ktbl,$Ktbl,#.Lsha256_block_data_order-K256 + bic $H,$H,#15 @ align for 128-bit stores + mov $t2,sp + mov sp,$H @ alloca +diff --git a/arch/arm/crypto/sha256-core.S_shipped b/arch/arm/crypto/sha256-core.S_shipped +index 054aae0edfce..9deb515f3c9f 100644 +--- a/arch/arm/crypto/sha256-core.S_shipped ++++ b/arch/arm/crypto/sha256-core.S_shipped +@@ -56,7 +56,6 @@ + #else + .syntax unified + # ifdef __thumb2__ +-# define adrl adr + .thumb + # else + .code 32 +@@ -1885,7 +1884,8 @@ sha256_block_data_order_neon: + stmdb sp!,{r4-r12,lr} + + sub r11,sp,#16*4+16 +- adrl r14,K256 ++ adr r14,.Lsha256_block_data_order ++ sub r14,r14,#.Lsha256_block_data_order-K256 + bic r11,r11,#15 @ align for 128-bit stores + mov r12,sp + mov sp,r11 @ alloca +-- +2.30.1 + diff --git a/queue-5.4/crypto-arm-sha512-neon-avoid-adrl-pseudo-instruction.patch b/queue-5.4/crypto-arm-sha512-neon-avoid-adrl-pseudo-instruction.patch new file mode 100644 index 00000000000..5dc6939f7ba --- /dev/null +++ b/queue-5.4/crypto-arm-sha512-neon-avoid-adrl-pseudo-instruction.patch @@ -0,0 +1,78 @@ +From c85bb4a6db7b320982c0d605b6601f8fbeb5de56 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 16 Sep 2020 09:14:18 +0300 +Subject: crypto: arm/sha512-neon - avoid ADRL pseudo instruction + +From: Ard Biesheuvel + +commit 0f5e8323777bfc1c1d2cba71242db6a361de03b6 upstream. + +The ADRL pseudo instruction is not an architectural construct, but a +convenience macro that was supported by the ARM proprietary assembler +and adopted by binutils GAS as well, but only when assembling in 32-bit +ARM mode. Therefore, it can only be used in assembler code that is known +to assemble in ARM mode only, but as it turns out, the Clang assembler +does not implement ADRL at all, and so it is better to get rid of it +entirely. + +So replace the ADRL instruction with a ADR instruction that refers to +a nearer symbol, and apply the delta explicitly using an additional +instruction. + +Signed-off-by: Ard Biesheuvel +Tested-by: Nick Desaulniers +Signed-off-by: Herbert Xu +Signed-off-by: Nick Desaulniers +Signed-off-by: Sasha Levin +--- + arch/arm/crypto/sha512-armv4.pl | 4 ++-- + arch/arm/crypto/sha512-core.S_shipped | 4 ++-- + 2 files changed, 4 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/crypto/sha512-armv4.pl b/arch/arm/crypto/sha512-armv4.pl +index 788c17b56ecc..2a0bdf7dd87c 100644 +--- a/arch/arm/crypto/sha512-armv4.pl ++++ b/arch/arm/crypto/sha512-armv4.pl +@@ -212,7 +212,6 @@ $code=<<___; + #else + .syntax unified + # ifdef __thumb2__ +-# define adrl adr + .thumb + # else + .code 32 +@@ -602,7 +601,8 @@ sha512_block_data_order_neon: + dmb @ errata #451034 on early Cortex A8 + add $len,$inp,$len,lsl#7 @ len to point at the end of inp + VFP_ABI_PUSH +- adrl $Ktbl,K512 ++ adr $Ktbl,.Lsha512_block_data_order ++ sub $Ktbl,$Ktbl,.Lsha512_block_data_order-K512 + vldmia $ctx,{$A-$H} @ load context + .Loop_neon: + ___ +diff --git a/arch/arm/crypto/sha512-core.S_shipped b/arch/arm/crypto/sha512-core.S_shipped +index 710ea309769e..cf5a7a70ff00 100644 +--- a/arch/arm/crypto/sha512-core.S_shipped ++++ b/arch/arm/crypto/sha512-core.S_shipped +@@ -79,7 +79,6 @@ + #else + .syntax unified + # ifdef __thumb2__ +-# define adrl adr + .thumb + # else + .code 32 +@@ -543,7 +542,8 @@ sha512_block_data_order_neon: + dmb @ errata #451034 on early Cortex A8 + add r2,r1,r2,lsl#7 @ len to point at the end of inp + VFP_ABI_PUSH +- adrl r3,K512 ++ adr r3,.Lsha512_block_data_order ++ sub r3,r3,.Lsha512_block_data_order-K512 + vldmia r0,{d16-d23} @ load context + .Loop_neon: + vshr.u64 d24,d20,#14 @ 0 +-- +2.30.1 + diff --git a/queue-5.4/crypto-arm-use-kconfig-based-compiler-checks-for-cry.patch b/queue-5.4/crypto-arm-use-kconfig-based-compiler-checks-for-cry.patch new file mode 100644 index 00000000000..6eb36bc2e71 --- /dev/null +++ b/queue-5.4/crypto-arm-use-kconfig-based-compiler-checks-for-cry.patch @@ -0,0 +1,185 @@ +From ec3968c84f05ac61019b43b02c1423ff222120fa Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 11 Oct 2019 11:08:00 +0200 +Subject: crypto: arm - use Kconfig based compiler checks for crypto opcodes + +From: Ard Biesheuvel + +commit b4d0c0aad57ac3bd1b5141bac5ab1ab1d5e442b3 upstream. + +Instead of allowing the Crypto Extensions algorithms to be selected when +using a toolchain that does not support them, and complain about it at +build time, use the information we have about the compiler to prevent +them from being selected in the first place. Users that are stuck with +a GCC version <4.8 are unlikely to care about these routines anyway, and +it cleans up the Makefile considerably. + +While at it, add explicit 'armv8-a' CPU specifiers to the code that uses +the 'crypto-neon-fp-armv8' FPU specifier so we don't regress Clang, which +will complain about this in version 10 and later. + +Signed-off-by: Ard Biesheuvel +Signed-off-by: Herbert Xu +Signed-off-by: Nick Desaulniers +Signed-off-by: Sasha Levin +--- + arch/arm/crypto/Kconfig | 14 +++++++------ + arch/arm/crypto/Makefile | 32 ++++++----------------------- + arch/arm/crypto/crct10dif-ce-core.S | 2 +- + arch/arm/crypto/ghash-ce-core.S | 1 + + arch/arm/crypto/sha1-ce-core.S | 1 + + arch/arm/crypto/sha2-ce-core.S | 1 + + 6 files changed, 18 insertions(+), 33 deletions(-) + +diff --git a/arch/arm/crypto/Kconfig b/arch/arm/crypto/Kconfig +index 043b0b18bf7e..f747caea10ff 100644 +--- a/arch/arm/crypto/Kconfig ++++ b/arch/arm/crypto/Kconfig +@@ -30,7 +30,7 @@ config CRYPTO_SHA1_ARM_NEON + + config CRYPTO_SHA1_ARM_CE + tristate "SHA1 digest algorithm (ARM v8 Crypto Extensions)" +- depends on KERNEL_MODE_NEON ++ depends on KERNEL_MODE_NEON && (CC_IS_CLANG || GCC_VERSION >= 40800) + select CRYPTO_SHA1_ARM + select CRYPTO_HASH + help +@@ -39,7 +39,7 @@ config CRYPTO_SHA1_ARM_CE + + config CRYPTO_SHA2_ARM_CE + tristate "SHA-224/256 digest algorithm (ARM v8 Crypto Extensions)" +- depends on KERNEL_MODE_NEON ++ depends on KERNEL_MODE_NEON && (CC_IS_CLANG || GCC_VERSION >= 40800) + select CRYPTO_SHA256_ARM + select CRYPTO_HASH + help +@@ -96,7 +96,7 @@ config CRYPTO_AES_ARM_BS + + config CRYPTO_AES_ARM_CE + tristate "Accelerated AES using ARMv8 Crypto Extensions" +- depends on KERNEL_MODE_NEON ++ depends on KERNEL_MODE_NEON && (CC_IS_CLANG || GCC_VERSION >= 40800) + select CRYPTO_BLKCIPHER + select CRYPTO_LIB_AES + select CRYPTO_SIMD +@@ -106,7 +106,7 @@ config CRYPTO_AES_ARM_CE + + config CRYPTO_GHASH_ARM_CE + tristate "PMULL-accelerated GHASH using NEON/ARMv8 Crypto Extensions" +- depends on KERNEL_MODE_NEON ++ depends on KERNEL_MODE_NEON && (CC_IS_CLANG || GCC_VERSION >= 40800) + select CRYPTO_HASH + select CRYPTO_CRYPTD + select CRYPTO_GF128MUL +@@ -118,12 +118,14 @@ config CRYPTO_GHASH_ARM_CE + + config CRYPTO_CRCT10DIF_ARM_CE + tristate "CRCT10DIF digest algorithm using PMULL instructions" +- depends on KERNEL_MODE_NEON && CRC_T10DIF ++ depends on KERNEL_MODE_NEON && (CC_IS_CLANG || GCC_VERSION >= 40800) ++ depends on CRC_T10DIF + select CRYPTO_HASH + + config CRYPTO_CRC32_ARM_CE + tristate "CRC32(C) digest algorithm using CRC and/or PMULL instructions" +- depends on KERNEL_MODE_NEON && CRC32 ++ depends on KERNEL_MODE_NEON && (CC_IS_CLANG || GCC_VERSION >= 40800) ++ depends on CRC32 + select CRYPTO_HASH + + config CRYPTO_CHACHA20_NEON +diff --git a/arch/arm/crypto/Makefile b/arch/arm/crypto/Makefile +index 4180f3a13512..c0d36771a693 100644 +--- a/arch/arm/crypto/Makefile ++++ b/arch/arm/crypto/Makefile +@@ -12,32 +12,12 @@ obj-$(CONFIG_CRYPTO_SHA512_ARM) += sha512-arm.o + obj-$(CONFIG_CRYPTO_CHACHA20_NEON) += chacha-neon.o + obj-$(CONFIG_CRYPTO_NHPOLY1305_NEON) += nhpoly1305-neon.o + +-ce-obj-$(CONFIG_CRYPTO_AES_ARM_CE) += aes-arm-ce.o +-ce-obj-$(CONFIG_CRYPTO_SHA1_ARM_CE) += sha1-arm-ce.o +-ce-obj-$(CONFIG_CRYPTO_SHA2_ARM_CE) += sha2-arm-ce.o +-ce-obj-$(CONFIG_CRYPTO_GHASH_ARM_CE) += ghash-arm-ce.o +-ce-obj-$(CONFIG_CRYPTO_CRCT10DIF_ARM_CE) += crct10dif-arm-ce.o +-crc-obj-$(CONFIG_CRYPTO_CRC32_ARM_CE) += crc32-arm-ce.o +- +-ifneq ($(crc-obj-y)$(crc-obj-m),) +-ifeq ($(call as-instr,.arch armv8-a\n.arch_extension crc,y,n),y) +-ce-obj-y += $(crc-obj-y) +-ce-obj-m += $(crc-obj-m) +-else +-$(warning These CRC Extensions modules need binutils 2.23 or higher) +-$(warning $(crc-obj-y) $(crc-obj-m)) +-endif +-endif +- +-ifneq ($(ce-obj-y)$(ce-obj-m),) +-ifeq ($(call as-instr,.fpu crypto-neon-fp-armv8,y,n),y) +-obj-y += $(ce-obj-y) +-obj-m += $(ce-obj-m) +-else +-$(warning These ARMv8 Crypto Extensions modules need binutils 2.23 or higher) +-$(warning $(ce-obj-y) $(ce-obj-m)) +-endif +-endif ++obj-$(CONFIG_CRYPTO_AES_ARM_CE) += aes-arm-ce.o ++obj-$(CONFIG_CRYPTO_SHA1_ARM_CE) += sha1-arm-ce.o ++obj-$(CONFIG_CRYPTO_SHA2_ARM_CE) += sha2-arm-ce.o ++obj-$(CONFIG_CRYPTO_GHASH_ARM_CE) += ghash-arm-ce.o ++obj-$(CONFIG_CRYPTO_CRCT10DIF_ARM_CE) += crct10dif-arm-ce.o ++obj-$(CONFIG_CRYPTO_CRC32_ARM_CE) += crc32-arm-ce.o + + aes-arm-y := aes-cipher-core.o aes-cipher-glue.o + aes-arm-bs-y := aes-neonbs-core.o aes-neonbs-glue.o +diff --git a/arch/arm/crypto/crct10dif-ce-core.S b/arch/arm/crypto/crct10dif-ce-core.S +index 86be258a803f..46c02c518a30 100644 +--- a/arch/arm/crypto/crct10dif-ce-core.S ++++ b/arch/arm/crypto/crct10dif-ce-core.S +@@ -72,7 +72,7 @@ + #endif + + .text +- .arch armv7-a ++ .arch armv8-a + .fpu crypto-neon-fp-armv8 + + init_crc .req r0 +diff --git a/arch/arm/crypto/ghash-ce-core.S b/arch/arm/crypto/ghash-ce-core.S +index c47fe81abcb0..534c9647726d 100644 +--- a/arch/arm/crypto/ghash-ce-core.S ++++ b/arch/arm/crypto/ghash-ce-core.S +@@ -88,6 +88,7 @@ + T3_H .req d17 + + .text ++ .arch armv8-a + .fpu crypto-neon-fp-armv8 + + .macro __pmull_p64, rd, rn, rm, b1, b2, b3, b4 +diff --git a/arch/arm/crypto/sha1-ce-core.S b/arch/arm/crypto/sha1-ce-core.S +index 49a74a441aec..8a702e051738 100644 +--- a/arch/arm/crypto/sha1-ce-core.S ++++ b/arch/arm/crypto/sha1-ce-core.S +@@ -10,6 +10,7 @@ + #include + + .text ++ .arch armv8-a + .fpu crypto-neon-fp-armv8 + + k0 .req q0 +diff --git a/arch/arm/crypto/sha2-ce-core.S b/arch/arm/crypto/sha2-ce-core.S +index 4ad517577e23..b6369d2440a1 100644 +--- a/arch/arm/crypto/sha2-ce-core.S ++++ b/arch/arm/crypto/sha2-ce-core.S +@@ -10,6 +10,7 @@ + #include + + .text ++ .arch armv8-a + .fpu crypto-neon-fp-armv8 + + k0 .req q7 +-- +2.30.1 + diff --git a/queue-5.4/hid-logitech-dj-add-support-for-the-new-lightspeed-c.patch b/queue-5.4/hid-logitech-dj-add-support-for-the-new-lightspeed-c.patch new file mode 100644 index 00000000000..dbe71d125ae --- /dev/null +++ b/queue-5.4/hid-logitech-dj-add-support-for-the-new-lightspeed-c.patch @@ -0,0 +1,61 @@ +From f61b6cb619611ff9a8d6e5b544e5884b165bfc21 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 23 Jan 2021 18:02:20 +0000 +Subject: HID: logitech-dj: add support for the new lightspeed connection + iteration +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Filipe Laíns + +[ Upstream commit fab3a95654eea01d6b0204995be8b7492a00d001 ] + +This new connection type is the new iteration of the Lightspeed +connection and will probably be used in some of the newer gaming +devices. It is currently use in the G Pro X Superlight. + +This patch should be backported to older versions, as currently the +driver will panic when seing the unsupported connection. This isn't +an issue when using the receiver that came with the device, as Logitech +has been using different PIDs when they change the connection type, but +is an issue when using a generic receiver (well, generic Lightspeed +receiver), which is the case of the one in the Powerplay mat. Currently, +the only generic Ligthspeed receiver we support, and the only one that +exists AFAIK, is ther Powerplay. + +As it stands, the driver will panic when seeing a G Pro X Superlight +connected to the Powerplay receiver and won't send any input events to +userspace! The kernel will warn about this so the issue should be easy +to identify, but it is still very worrying how hard it will fail :( + +[915977.398471] logitech-djreceiver 0003:046D:C53A.0107: unusable device of type UNKNOWN (0x0f) connected on slot 1 + +Signed-off-by: Filipe Laíns +Signed-off-by: Jiri Kosina +Signed-off-by: Sasha Levin +--- + drivers/hid/hid-logitech-dj.c | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/drivers/hid/hid-logitech-dj.c b/drivers/hid/hid-logitech-dj.c +index 86001cfbdb6f..b499ac37dc7b 100644 +--- a/drivers/hid/hid-logitech-dj.c ++++ b/drivers/hid/hid-logitech-dj.c +@@ -995,7 +995,12 @@ static void logi_hidpp_recv_queue_notif(struct hid_device *hdev, + workitem.reports_supported |= STD_KEYBOARD; + break; + case 0x0d: +- device_type = "eQUAD Lightspeed 1_1"; ++ device_type = "eQUAD Lightspeed 1.1"; ++ logi_hidpp_dev_conn_notif_equad(hdev, hidpp_report, &workitem); ++ workitem.reports_supported |= STD_KEYBOARD; ++ break; ++ case 0x0f: ++ device_type = "eQUAD Lightspeed 1.2"; + logi_hidpp_dev_conn_notif_equad(hdev, hidpp_report, &workitem); + workitem.reports_supported |= STD_KEYBOARD; + break; +-- +2.30.1 + diff --git a/queue-5.4/i2c-rcar-faster-irq-code-to-minimize-hw-race-conditi.patch b/queue-5.4/i2c-rcar-faster-irq-code-to-minimize-hw-race-conditi.patch new file mode 100644 index 00000000000..0f0fb9fa9e9 --- /dev/null +++ b/queue-5.4/i2c-rcar-faster-irq-code-to-minimize-hw-race-conditi.patch @@ -0,0 +1,65 @@ +From 13dd450690f75fce4c23dc076c6b9649e50c4015 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 23 Dec 2020 18:21:51 +0100 +Subject: i2c: rcar: faster irq code to minimize HW race condition +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Wolfram Sang + +[ Upstream commit c7b514ec979e23a08c411f3d8ed39c7922751422 ] + +To avoid the HW race condition on R-Car Gen2 and earlier, we need to +write to ICMCR as soon as possible in the interrupt handler. We can +improve this by writing a static value instead of masking out bits. + +Signed-off-by: Wolfram Sang +Reviewed-by: Niklas Söderlund +Signed-off-by: Wolfram Sang +Signed-off-by: Sasha Levin +--- + drivers/i2c/busses/i2c-rcar.c | 11 ++++------- + 1 file changed, 4 insertions(+), 7 deletions(-) + +diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c +index 9c162a01a584..9d54ae935524 100644 +--- a/drivers/i2c/busses/i2c-rcar.c ++++ b/drivers/i2c/busses/i2c-rcar.c +@@ -89,7 +89,6 @@ + + #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG) + #define RCAR_BUS_PHASE_DATA (MDBS | MIE) +-#define RCAR_BUS_MASK_DATA (~(ESG | FSB) & 0xFF) + #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB) + + #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE) +@@ -616,7 +615,7 @@ static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv) + /* + * This driver has a lock-free design because there are IP cores (at least + * R-Car Gen2) which have an inherent race condition in their hardware design. +- * There, we need to clear RCAR_BUS_MASK_DATA bits as soon as possible after ++ * There, we need to switch to RCAR_BUS_PHASE_DATA as soon as possible after + * the interrupt was generated, otherwise an unwanted repeated message gets + * generated. It turned out that taking a spinlock at the beginning of the ISR + * was already causing repeated messages. Thus, this driver was converted to +@@ -625,13 +624,11 @@ static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv) + static irqreturn_t rcar_i2c_irq(int irq, void *ptr) + { + struct rcar_i2c_priv *priv = ptr; +- u32 msr, val; ++ u32 msr; + + /* Clear START or STOP immediately, except for REPSTART after read */ +- if (likely(!(priv->flags & ID_P_REP_AFTER_RD))) { +- val = rcar_i2c_read(priv, ICMCR); +- rcar_i2c_write(priv, ICMCR, val & RCAR_BUS_MASK_DATA); +- } ++ if (likely(!(priv->flags & ID_P_REP_AFTER_RD))) ++ rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA); + + msr = rcar_i2c_read(priv, ICMSR); + +-- +2.30.1 + diff --git a/queue-5.4/i2c-rcar-optimize-cacheline-to-minimize-hw-race-cond.patch b/queue-5.4/i2c-rcar-optimize-cacheline-to-minimize-hw-race-cond.patch new file mode 100644 index 00000000000..6290d97a6e5 --- /dev/null +++ b/queue-5.4/i2c-rcar-optimize-cacheline-to-minimize-hw-race-cond.patch @@ -0,0 +1,46 @@ +From 09430c46223cf6ef4bc9d3c77868a4d60baaa7f4 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 23 Dec 2020 18:21:52 +0100 +Subject: i2c: rcar: optimize cacheline to minimize HW race condition +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Wolfram Sang + +[ Upstream commit 25c2e0fb5fefb8d7847214cf114d94c7aad8e9ce ] + +'flags' and 'io' are needed first, so they should be at the beginning of +the private struct. + +Signed-off-by: Wolfram Sang +Reviewed-by: Niklas Söderlund +Signed-off-by: Wolfram Sang +Signed-off-by: Sasha Levin +--- + drivers/i2c/busses/i2c-rcar.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c +index 9d54ae935524..d0c4b3019e41 100644 +--- a/drivers/i2c/busses/i2c-rcar.c ++++ b/drivers/i2c/busses/i2c-rcar.c +@@ -116,6 +116,7 @@ enum rcar_i2c_type { + }; + + struct rcar_i2c_priv { ++ u32 flags; + void __iomem *io; + struct i2c_adapter adap; + struct i2c_msg *msg; +@@ -126,7 +127,6 @@ struct rcar_i2c_priv { + + int pos; + u32 icccr; +- u32 flags; + u8 recovery_icmcr; /* protected by adapter lock */ + enum rcar_i2c_type devtype; + struct i2c_client *slave; +-- +2.30.1 + diff --git a/queue-5.4/i40e-fix-memory-leak-in-i40e_probe.patch b/queue-5.4/i40e-fix-memory-leak-in-i40e_probe.patch new file mode 100644 index 00000000000..4f340614b09 --- /dev/null +++ b/queue-5.4/i40e-fix-memory-leak-in-i40e_probe.patch @@ -0,0 +1,39 @@ +From 7193aea4d2aa82025affedc084efaec9497d3da7 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 30 Oct 2020 07:14:30 +0000 +Subject: i40e: Fix memory leak in i40e_probe + +From: Keita Suzuki + +[ Upstream commit 58cab46c622d6324e47bd1c533693c94498e4172 ] + +Struct i40e_veb is allocated in function i40e_setup_pf_switch, and +stored to an array field veb inside struct i40e_pf. However when +i40e_setup_misc_vector fails, this memory leaks. + +Fix this by calling exit and teardown functions. + +Signed-off-by: Keita Suzuki +Tested-by: Tony Brelinski +Signed-off-by: Tony Nguyen +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/intel/i40e/i40e_main.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c +index 0604b5aaad86..58211590229b 100644 +--- a/drivers/net/ethernet/intel/i40e/i40e_main.c ++++ b/drivers/net/ethernet/intel/i40e/i40e_main.c +@@ -15142,6 +15142,8 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent) + if (err) { + dev_info(&pdev->dev, + "setup of misc vector failed: %d\n", err); ++ i40e_cloud_filter_exit(pf); ++ i40e_fdir_teardown(pf); + goto err_vsis; + } + } +-- +2.30.1 + diff --git a/queue-5.4/input-applespi-don-t-wait-for-responses-to-commands-.patch b/queue-5.4/input-applespi-don-t-wait-for-responses-to-commands-.patch new file mode 100644 index 00000000000..4043832824b --- /dev/null +++ b/queue-5.4/input-applespi-don-t-wait-for-responses-to-commands-.patch @@ -0,0 +1,97 @@ +From 68ecdf1e489cdca22a8e8dc4afe6874baaf2539b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 19 Feb 2021 11:10:51 -0800 +Subject: Input: applespi - don't wait for responses to commands indefinitely. +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ronald Tschalär + +[ Upstream commit 0ce1ac23149c6da939a5926c098c270c58c317a0 ] + +The response to a command may never arrive or it may be corrupted (and +hence dropped) for some reason. While exceedingly rare, when it did +happen it blocked all further commands. One way to fix this was to +do a suspend/resume. However, recovering automatically seems like a +nicer option. Hence this puts a time limit (1 sec) on how long we're +willing to wait for a response, after which we assume it got lost. + +Signed-off-by: Ronald Tschalär +Link: https://lore.kernel.org/r/20210217190718.11035-1-ronald@innovation.ch +Signed-off-by: Dmitry Torokhov +Signed-off-by: Sasha Levin +--- + drivers/input/keyboard/applespi.c | 21 +++++++++++++++------ + 1 file changed, 15 insertions(+), 6 deletions(-) + +diff --git a/drivers/input/keyboard/applespi.c b/drivers/input/keyboard/applespi.c +index d38398526965..a4b7422de534 100644 +--- a/drivers/input/keyboard/applespi.c ++++ b/drivers/input/keyboard/applespi.c +@@ -48,6 +48,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -400,7 +401,7 @@ struct applespi_data { + unsigned int cmd_msg_cntr; + /* lock to protect the above parameters and flags below */ + spinlock_t cmd_msg_lock; +- bool cmd_msg_queued; ++ ktime_t cmd_msg_queued; + enum applespi_evt_type cmd_evt_type; + + struct led_classdev backlight_info; +@@ -716,7 +717,7 @@ static void applespi_msg_complete(struct applespi_data *applespi, + wake_up_all(&applespi->drain_complete); + + if (is_write_msg) { +- applespi->cmd_msg_queued = false; ++ applespi->cmd_msg_queued = 0; + applespi_send_cmd_msg(applespi); + } + +@@ -758,8 +759,16 @@ static int applespi_send_cmd_msg(struct applespi_data *applespi) + return 0; + + /* check whether send is in progress */ +- if (applespi->cmd_msg_queued) +- return 0; ++ if (applespi->cmd_msg_queued) { ++ if (ktime_ms_delta(ktime_get(), applespi->cmd_msg_queued) < 1000) ++ return 0; ++ ++ dev_warn(&applespi->spi->dev, "Command %d timed out\n", ++ applespi->cmd_evt_type); ++ ++ applespi->cmd_msg_queued = 0; ++ applespi->write_active = false; ++ } + + /* set up packet */ + memset(packet, 0, APPLESPI_PACKET_SIZE); +@@ -856,7 +865,7 @@ static int applespi_send_cmd_msg(struct applespi_data *applespi) + return sts; + } + +- applespi->cmd_msg_queued = true; ++ applespi->cmd_msg_queued = ktime_get_coarse(); + applespi->write_active = true; + + return 0; +@@ -1908,7 +1917,7 @@ static int __maybe_unused applespi_resume(struct device *dev) + applespi->drain = false; + applespi->have_cl_led_on = false; + applespi->have_bl_level = 0; +- applespi->cmd_msg_queued = false; ++ applespi->cmd_msg_queued = 0; + applespi->read_active = false; + applespi->write_active = false; + +-- +2.30.1 + diff --git a/queue-5.4/iommu-amd-fix-performance-counter-initialization.patch b/queue-5.4/iommu-amd-fix-performance-counter-initialization.patch new file mode 100644 index 00000000000..6dea0e05c5b --- /dev/null +++ b/queue-5.4/iommu-amd-fix-performance-counter-initialization.patch @@ -0,0 +1,117 @@ +From 88732b1312315cc55b545707eefaa2ec1c69baa8 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 8 Feb 2021 06:27:12 -0600 +Subject: iommu/amd: Fix performance counter initialization + +From: Suravee Suthikulpanit + +[ Upstream commit 6778ff5b21bd8e78c8bd547fd66437cf2657fd9b ] + +Certain AMD platforms enable power gating feature for IOMMU PMC, +which prevents the IOMMU driver from updating the counter while +trying to validate the PMC functionality in the init_iommu_perf_ctr(). +This results in disabling PMC support and the following error message: + + "AMD-Vi: Unable to read/write to IOMMU perf counter" + +To workaround this issue, disable power gating temporarily by programming +the counter source to non-zero value while validating the counter, +and restore the prior state afterward. + +Signed-off-by: Suravee Suthikulpanit +Tested-by: Tj (Elloe Linux) +Link: https://lore.kernel.org/r/20210208122712.5048-1-suravee.suthikulpanit@amd.com +Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=201753 +Signed-off-by: Joerg Roedel +Signed-off-by: Sasha Levin +--- + drivers/iommu/amd_iommu_init.c | 45 +++++++++++++++++++++++++--------- + 1 file changed, 34 insertions(+), 11 deletions(-) + +diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c +index 31d7e2d4f304..ad714ff375f8 100644 +--- a/drivers/iommu/amd_iommu_init.c ++++ b/drivers/iommu/amd_iommu_init.c +@@ -12,6 +12,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -253,6 +254,8 @@ static enum iommu_init_state init_state = IOMMU_START_STATE; + static int amd_iommu_enable_interrupts(void); + static int __init iommu_go_to_state(enum iommu_init_state state); + static void init_device_table_dma(void); ++static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, ++ u8 fxn, u64 *value, bool is_write); + + static bool amd_iommu_pre_enabled = true; + +@@ -1672,13 +1675,11 @@ static int __init init_iommu_all(struct acpi_table_header *table) + return 0; + } + +-static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, +- u8 fxn, u64 *value, bool is_write); +- +-static void init_iommu_perf_ctr(struct amd_iommu *iommu) ++static void __init init_iommu_perf_ctr(struct amd_iommu *iommu) + { ++ int retry; + struct pci_dev *pdev = iommu->dev; +- u64 val = 0xabcd, val2 = 0, save_reg = 0; ++ u64 val = 0xabcd, val2 = 0, save_reg, save_src; + + if (!iommu_feature(iommu, FEATURE_PC)) + return; +@@ -1686,17 +1687,39 @@ static void init_iommu_perf_ctr(struct amd_iommu *iommu) + amd_iommu_pc_present = true; + + /* save the value to restore, if writable */ +- if (iommu_pc_get_set_reg(iommu, 0, 0, 0, &save_reg, false)) ++ if (iommu_pc_get_set_reg(iommu, 0, 0, 0, &save_reg, false) || ++ iommu_pc_get_set_reg(iommu, 0, 0, 8, &save_src, false)) + goto pc_false; + +- /* Check if the performance counters can be written to */ +- if ((iommu_pc_get_set_reg(iommu, 0, 0, 0, &val, true)) || +- (iommu_pc_get_set_reg(iommu, 0, 0, 0, &val2, false)) || +- (val != val2)) ++ /* ++ * Disable power gating by programing the performance counter ++ * source to 20 (i.e. counts the reads and writes from/to IOMMU ++ * Reserved Register [MMIO Offset 1FF8h] that are ignored.), ++ * which never get incremented during this init phase. ++ * (Note: The event is also deprecated.) ++ */ ++ val = 20; ++ if (iommu_pc_get_set_reg(iommu, 0, 0, 8, &val, true)) + goto pc_false; + ++ /* Check if the performance counters can be written to */ ++ val = 0xabcd; ++ for (retry = 5; retry; retry--) { ++ if (iommu_pc_get_set_reg(iommu, 0, 0, 0, &val, true) || ++ iommu_pc_get_set_reg(iommu, 0, 0, 0, &val2, false) || ++ val2) ++ break; ++ ++ /* Wait about 20 msec for power gating to disable and retry. */ ++ msleep(20); ++ } ++ + /* restore */ +- if (iommu_pc_get_set_reg(iommu, 0, 0, 0, &save_reg, true)) ++ if (iommu_pc_get_set_reg(iommu, 0, 0, 0, &save_reg, true) || ++ iommu_pc_get_set_reg(iommu, 0, 0, 8, &save_src, true)) ++ goto pc_false; ++ ++ if (val != val2) + goto pc_false; + + pci_info(pdev, "IOMMU performance counters supported\n"); +-- +2.30.1 + diff --git a/queue-5.4/kbuild-add-config_ld_is_lld.patch b/queue-5.4/kbuild-add-config_ld_is_lld.patch new file mode 100644 index 00000000000..5c0601209c4 --- /dev/null +++ b/queue-5.4/kbuild-add-config_ld_is_lld.patch @@ -0,0 +1,44 @@ +From 5de501e293dd49d22c5a9337e69916f596daed5f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 28 Apr 2020 15:14:15 -0700 +Subject: kbuild: add CONFIG_LD_IS_LLD + +From: Sami Tolvanen + +commit b744b43f79cc758127042e71f9ad7b1afda30f84 upstream. + +Similarly to the CC_IS_CLANG config, add LD_IS_LLD to avoid GNU ld +specific logic such as ld-version or ld-ifversion and gain the +ability to select potential features that depend on the linker at +configuration time such as LTO. + +Signed-off-by: Sami Tolvanen +Acked-by: Masahiro Yamada +[nc: Reword commit message] +Signed-off-by: Nathan Chancellor +Tested-by: Sedat Dilek +Reviewed-by: Sedat Dilek +Signed-off-by: Thomas Bogendoerfer +Signed-off-by: Nick Desaulniers +Signed-off-by: Sasha Levin +--- + init/Kconfig | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/init/Kconfig b/init/Kconfig +index 96fc45d1b686..d74f152e6b98 100644 +--- a/init/Kconfig ++++ b/init/Kconfig +@@ -20,6 +20,9 @@ config GCC_VERSION + config CC_IS_CLANG + def_bool $(success,$(CC) --version | head -n 1 | grep -q clang) + ++config LD_IS_LLD ++ def_bool $(success,$(LD) -v | head -n 1 | grep -q LLD) ++ + config CLANG_VERSION + int + default $(shell,$(srctree)/scripts/clang-version.sh $(CC)) +-- +2.30.1 + diff --git a/queue-5.4/kbuild-add-support-for-as-instr-to-be-used-in-kconfi.patch b/queue-5.4/kbuild-add-support-for-as-instr-to-be-used-in-kconfi.patch new file mode 100644 index 00000000000..6b7516590b4 --- /dev/null +++ b/queue-5.4/kbuild-add-support-for-as-instr-to-be-used-in-kconfi.patch @@ -0,0 +1,48 @@ +From bf93523f4e8c53e0b8db390fb77fab769975b8b7 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 15 Jan 2020 11:30:07 +0000 +Subject: kbuild: Add support for 'as-instr' to be used in Kconfig files + +From: Catalin Marinas + +commit 42d519e3d0c071161d0a1c36e95a3743b113c590 upstream. + +Similar to 'cc-option' or 'ld-option', it is occasionally necessary to +check whether the assembler supports certain ISA extensions. In the +arm64 code we currently do this in Makefile with an additional define: + +lseinstr := $(call as-instr,.arch_extension lse,-DCONFIG_AS_LSE=1) + +Add the 'as-instr' option so that it can be used in Kconfig directly: + + def_bool $(as-instr,.arch_extension lse) + +Acked-by: Masahiro Yamada +Reviewed-by: Vladimir Murzin +Tested-by: Vladimir Murzin +Signed-off-by: Catalin Marinas +Signed-off-by: Will Deacon +Signed-off-by: Nick Desaulniers +Signed-off-by: Sasha Levin +--- + scripts/Kconfig.include | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/scripts/Kconfig.include b/scripts/Kconfig.include +index 77a69ba9cd19..496d11c92c97 100644 +--- a/scripts/Kconfig.include ++++ b/scripts/Kconfig.include +@@ -31,6 +31,10 @@ cc-option = $(success,$(CC) -Werror $(CLANG_FLAGS) $(1) -S -x c /dev/null -o /de + # Return y if the linker supports , n otherwise + ld-option = $(success,$(LD) -v $(1)) + ++# $(as-instr,) ++# Return y if the assembler supports , n otherwise ++as-instr = $(success,printf "%b\n" "$(1)" | $(CC) $(CLANG_FLAGS) -c -x assembler -o /dev/null -) ++ + # check if $(CC) and $(LD) exist + $(error-if,$(failure,command -v $(CC)),compiler '$(CC)' not found) + $(error-if,$(failure,command -v $(LD)),linker '$(LD)' not found) +-- +2.30.1 + diff --git a/queue-5.4/kbuild-clamp-sublevel-to-255.patch b/queue-5.4/kbuild-clamp-sublevel-to-255.patch new file mode 100644 index 00000000000..0c9a313ace6 --- /dev/null +++ b/queue-5.4/kbuild-clamp-sublevel-to-255.patch @@ -0,0 +1,52 @@ +From c31a699421e23526bd9a584dc0bdb51eeec001a3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 5 Feb 2021 22:50:32 -0500 +Subject: kbuild: clamp SUBLEVEL to 255 + +[ Upstream commit 9b82f13e7ef316cdc0a8858f1349f4defce3f9e0 ] + +Right now if SUBLEVEL becomes larger than 255 it will overflow into the +territory of PATCHLEVEL, causing havoc in userspace that tests for +specific kernel version. + +While userspace code tests for MAJOR and PATCHLEVEL, it doesn't test +SUBLEVEL at any point as ABI changes don't happen in the context of +stable tree. + +Thus, to avoid overflows, simply clamp SUBLEVEL to it's maximum value in +the context of LINUX_VERSION_CODE. This does not affect "make +kernelversion" and such. + +Signed-off-by: Sasha Levin +Signed-off-by: Masahiro Yamada +Signed-off-by: Sasha Levin +--- + Makefile | 12 +++++++++--- + 1 file changed, 9 insertions(+), 3 deletions(-) + +diff --git a/Makefile b/Makefile +index e27d031f3241..00be167f9b13 100644 +--- a/Makefile ++++ b/Makefile +@@ -1175,9 +1175,15 @@ define filechk_utsrelease.h + endef + + define filechk_version.h +- echo \#define LINUX_VERSION_CODE $(shell \ +- expr $(VERSION) \* 65536 + 0$(PATCHLEVEL) \* 256 + 0$(SUBLEVEL)); \ +- echo '#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))' ++ if [ $(SUBLEVEL) -gt 255 ]; then \ ++ echo \#define LINUX_VERSION_CODE $(shell \ ++ expr $(VERSION) \* 65536 + 0$(PATCHLEVEL) \* 256 + 255); \ ++ else \ ++ echo \#define LINUX_VERSION_CODE $(shell \ ++ expr $(VERSION) \* 65536 + 0$(PATCHLEVEL) \* 256 + $(SUBLEVEL)); \ ++ fi; \ ++ echo '#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + \ ++ ((c) > 255 ? 255 : (c)))' + endef + + $(version_h): FORCE +-- +2.30.1 + diff --git a/queue-5.4/mmc-mediatek-fix-race-condition-between-msdc_request.patch b/queue-5.4/mmc-mediatek-fix-race-condition-between-msdc_request.patch new file mode 100644 index 00000000000..02af1518dfb --- /dev/null +++ b/queue-5.4/mmc-mediatek-fix-race-condition-between-msdc_request.patch @@ -0,0 +1,85 @@ +From 0d134c94ba771eba4edfe0d073aca1087fc9eea0 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 18 Dec 2020 15:16:11 +0800 +Subject: mmc: mediatek: fix race condition between msdc_request_timeout and + irq + +From: Chaotian Jing + +[ Upstream commit 0354ca6edd464a2cf332f390581977b8699ed081 ] + +when get request SW timeout, if CMD/DAT xfer done irq coming right now, +then there is race between the msdc_request_timeout work and irq handler, +and the host->cmd and host->data may set to NULL in irq handler. also, +current flow ensure that only one path can go to msdc_request_done(), so +no need check the return value of cancel_delayed_work(). + +Signed-off-by: Chaotian Jing +Link: https://lore.kernel.org/r/20201218071611.12276-1-chaotian.jing@mediatek.com +Signed-off-by: Ulf Hansson +Signed-off-by: Sasha Levin +--- + drivers/mmc/host/mtk-sd.c | 18 ++++++++++-------- + 1 file changed, 10 insertions(+), 8 deletions(-) + +diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c +index 9d47a2bd2546..1254a5650cff 100644 +--- a/drivers/mmc/host/mtk-sd.c ++++ b/drivers/mmc/host/mtk-sd.c +@@ -1020,13 +1020,13 @@ static void msdc_track_cmd_data(struct msdc_host *host, + static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) + { + unsigned long flags; +- bool ret; + +- ret = cancel_delayed_work(&host->req_timeout); +- if (!ret) { +- /* delay work already running */ +- return; +- } ++ /* ++ * No need check the return value of cancel_delayed_work, as only ONE ++ * path will go here! ++ */ ++ cancel_delayed_work(&host->req_timeout); ++ + spin_lock_irqsave(&host->lock, flags); + host->mrq = NULL; + spin_unlock_irqrestore(&host->lock, flags); +@@ -1046,7 +1046,7 @@ static bool msdc_cmd_done(struct msdc_host *host, int events, + bool done = false; + bool sbc_error; + unsigned long flags; +- u32 *rsp = cmd->resp; ++ u32 *rsp; + + if (mrq->sbc && cmd == mrq->cmd && + (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR +@@ -1067,6 +1067,7 @@ static bool msdc_cmd_done(struct msdc_host *host, int events, + + if (done) + return true; ++ rsp = cmd->resp; + + sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); + +@@ -1254,7 +1255,7 @@ static void msdc_data_xfer_next(struct msdc_host *host, + static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, + struct mmc_request *mrq, struct mmc_data *data) + { +- struct mmc_command *stop = data->stop; ++ struct mmc_command *stop; + unsigned long flags; + bool done; + unsigned int check_data = events & +@@ -1270,6 +1271,7 @@ static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, + + if (done) + return true; ++ stop = data->stop; + + if (check_data || (stop && stop->error)) { + dev_dbg(host->dev, "DMA status: 0x%8X\n", +-- +2.30.1 + diff --git a/queue-5.4/mmc-mxs-mmc-fix-a-resource-leak-in-an-error-handling.patch b/queue-5.4/mmc-mxs-mmc-fix-a-resource-leak-in-an-error-handling.patch new file mode 100644 index 00000000000..1c663f8aee0 --- /dev/null +++ b/queue-5.4/mmc-mxs-mmc-fix-a-resource-leak-in-an-error-handling.patch @@ -0,0 +1,37 @@ +From 1a3bd1f3c51edd55ba5947db98ee8bb1ae02fc9b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 8 Dec 2020 21:35:27 +0100 +Subject: mmc: mxs-mmc: Fix a resource leak in an error handling path in + 'mxs_mmc_probe()' + +From: Christophe JAILLET + +[ Upstream commit 0bb7e560f821c7770973a94e346654c4bdccd42c ] + +If 'mmc_of_parse()' fails, we must undo the previous 'dma_request_chan()' +call. + +Signed-off-by: Christophe JAILLET +Link: https://lore.kernel.org/r/20201208203527.49262-1-christophe.jaillet@wanadoo.fr +Signed-off-by: Ulf Hansson +Signed-off-by: Sasha Levin +--- + drivers/mmc/host/mxs-mmc.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/mmc/host/mxs-mmc.c b/drivers/mmc/host/mxs-mmc.c +index 4031217d21c3..52054931c350 100644 +--- a/drivers/mmc/host/mxs-mmc.c ++++ b/drivers/mmc/host/mxs-mmc.c +@@ -644,7 +644,7 @@ static int mxs_mmc_probe(struct platform_device *pdev) + + ret = mmc_of_parse(mmc); + if (ret) +- goto out_clk_disable; ++ goto out_free_dma; + + mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; + +-- +2.30.1 + diff --git a/queue-5.4/pci-fix-pci_register_io_range-memory-leak.patch b/queue-5.4/pci-fix-pci_register_io_range-memory-leak.patch new file mode 100644 index 00000000000..f24f129eada --- /dev/null +++ b/queue-5.4/pci-fix-pci_register_io_range-memory-leak.patch @@ -0,0 +1,81 @@ +From 52f83d014fa891b286aa3596fec271f6e8eaec91 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 2 Feb 2021 11:03:32 +0100 +Subject: PCI: Fix pci_register_io_range() memory leak + +From: Geert Uytterhoeven + +[ Upstream commit f6bda644fa3a7070621c3bf12cd657f69a42f170 ] + +Kmemleak reports: + + unreferenced object 0xc328de40 (size 64): + comm "kworker/1:1", pid 21, jiffies 4294938212 (age 1484.670s) + hex dump (first 32 bytes): + 00 00 00 00 00 00 00 00 e0 d8 fc eb 00 00 00 00 ................ + 00 00 10 fe 00 00 00 00 00 00 00 00 00 00 00 00 ................ + + backtrace: + [] pci_register_io_range+0x3c/0x80 + [<2c7f139e>] of_pci_range_to_resource+0x48/0xc0 + [] devm_of_pci_get_host_bridge_resources.constprop.0+0x2ac/0x3ac + [] devm_of_pci_bridge_init+0x60/0x1b8 + [] devm_pci_alloc_host_bridge+0x54/0x64 + [] rcar_pcie_probe+0x2c/0x644 + +In case a PCI host driver's probe is deferred, the same I/O range may be +allocated again, and be ignored, causing a memory leak. + +Fix this by (a) letting logic_pio_register_range() return -EEXIST if the +passed range already exists, so pci_register_io_range() will free it, and +by (b) making pci_register_io_range() not consider -EEXIST an error +condition. + +Link: https://lore.kernel.org/r/20210202100332.829047-1-geert+renesas@glider.be +Signed-off-by: Geert Uytterhoeven +Signed-off-by: Bjorn Helgaas +Signed-off-by: Sasha Levin +--- + drivers/pci/pci.c | 4 ++++ + lib/logic_pio.c | 3 +++ + 2 files changed, 7 insertions(+) + +diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c +index 9add26438be5..3c3bc9f58498 100644 +--- a/drivers/pci/pci.c ++++ b/drivers/pci/pci.c +@@ -3903,6 +3903,10 @@ int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, + ret = logic_pio_register_range(range); + if (ret) + kfree(range); ++ ++ /* Ignore duplicates due to deferred probing */ ++ if (ret == -EEXIST) ++ ret = 0; + #endif + + return ret; +diff --git a/lib/logic_pio.c b/lib/logic_pio.c +index 905027574e5d..774bb02fff10 100644 +--- a/lib/logic_pio.c ++++ b/lib/logic_pio.c +@@ -27,6 +27,8 @@ static DEFINE_MUTEX(io_range_mutex); + * @new_range: pointer to the IO range to be registered. + * + * Returns 0 on success, the error code in case of failure. ++ * If the range already exists, -EEXIST will be returned, which should be ++ * considered a success. + * + * Register a new IO range node in the IO range list. + */ +@@ -49,6 +51,7 @@ int logic_pio_register_range(struct logic_pio_hwaddr *new_range) + list_for_each_entry(range, &io_range_list, list) { + if (range->fwnode == new_range->fwnode) { + /* range already there */ ++ ret = -EEXIST; + goto end_register; + } + if (range->flags == LOGIC_PIO_CPU_MMIO && +-- +2.30.1 + diff --git a/queue-5.4/pci-mediatek-add-missing-of_node_put-to-fix-referenc.patch b/queue-5.4/pci-mediatek-add-missing-of_node_put-to-fix-referenc.patch new file mode 100644 index 00000000000..34287639f16 --- /dev/null +++ b/queue-5.4/pci-mediatek-add-missing-of_node_put-to-fix-referenc.patch @@ -0,0 +1,66 @@ +From 4d5363b9d9f3f0852145d9d3c8dad70af60c8ed5 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 20 Jan 2021 18:48:10 +0000 +Subject: PCI: mediatek: Add missing of_node_put() to fix reference leak +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Krzysztof Wilczyński + +[ Upstream commit 42814c438aac79746d310f413a27d5b0b959c5de ] + +The for_each_available_child_of_node helper internally makes use of the +of_get_next_available_child() which performs an of_node_get() on each +iteration when searching for next available child node. + +Should an available child node be found, then it would return a device +node pointer with reference count incremented, thus early return from +the middle of the loop requires an explicit of_node_put() to prevent +reference count leak. + +To stop the reference leak, explicitly call of_node_put() before +returning after an error occurred. + +Link: https://lore.kernel.org/r/20210120184810.3068794-1-kw@linux.com +Signed-off-by: Krzysztof Wilczyński +Signed-off-by: Lorenzo Pieralisi +Signed-off-by: Sasha Levin +--- + drivers/pci/controller/pcie-mediatek.c | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c +index 626a7c352dfd..728a59655825 100644 +--- a/drivers/pci/controller/pcie-mediatek.c ++++ b/drivers/pci/controller/pcie-mediatek.c +@@ -1063,14 +1063,14 @@ static int mtk_pcie_setup(struct mtk_pcie *pcie) + err = of_pci_get_devfn(child); + if (err < 0) { + dev_err(dev, "failed to parse devfn: %d\n", err); +- return err; ++ goto error_put_node; + } + + slot = PCI_SLOT(err); + + err = mtk_pcie_parse_port(pcie, child, slot); + if (err) +- return err; ++ goto error_put_node; + } + + err = mtk_pcie_subsys_powerup(pcie); +@@ -1086,6 +1086,9 @@ static int mtk_pcie_setup(struct mtk_pcie *pcie) + mtk_pcie_subsys_powerdown(pcie); + + return 0; ++error_put_node: ++ of_node_put(child); ++ return err; + } + + static int mtk_pcie_probe(struct platform_device *pdev) +-- +2.30.1 + diff --git a/queue-5.4/pci-xgene-msi-fix-race-in-installing-chained-irq-han.patch b/queue-5.4/pci-xgene-msi-fix-race-in-installing-chained-irq-han.patch new file mode 100644 index 00000000000..d2ee96c1a8e --- /dev/null +++ b/queue-5.4/pci-xgene-msi-fix-race-in-installing-chained-irq-han.patch @@ -0,0 +1,50 @@ +From 9d067c588d0326ebdad766d27a2f5d471a8e9dab Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 15 Jan 2021 22:24:35 +0100 +Subject: PCI: xgene-msi: Fix race in installing chained irq handler + +From: Martin Kaiser + +[ Upstream commit a93c00e5f975f23592895b7e83f35de2d36b7633 ] + +Fix a race where a pending interrupt could be received and the handler +called before the handler's data has been setup, by converting to +irq_set_chained_handler_and_data(). + +See also 2cf5a03cb29d ("PCI/keystone: Fix race in installing chained IRQ +handler"). + +Based on the mail discussion, it seems ok to drop the error handling. + +Link: https://lore.kernel.org/r/20210115212435.19940-3-martin@kaiser.cx +Signed-off-by: Martin Kaiser +Signed-off-by: Lorenzo Pieralisi +Signed-off-by: Sasha Levin +--- + drivers/pci/controller/pci-xgene-msi.c | 10 +++------- + 1 file changed, 3 insertions(+), 7 deletions(-) + +diff --git a/drivers/pci/controller/pci-xgene-msi.c b/drivers/pci/controller/pci-xgene-msi.c +index f4c02da84e59..0bfa5065b440 100644 +--- a/drivers/pci/controller/pci-xgene-msi.c ++++ b/drivers/pci/controller/pci-xgene-msi.c +@@ -384,13 +384,9 @@ static int xgene_msi_hwirq_alloc(unsigned int cpu) + if (!msi_group->gic_irq) + continue; + +- irq_set_chained_handler(msi_group->gic_irq, +- xgene_msi_isr); +- err = irq_set_handler_data(msi_group->gic_irq, msi_group); +- if (err) { +- pr_err("failed to register GIC IRQ handler\n"); +- return -EINVAL; +- } ++ irq_set_chained_handler_and_data(msi_group->gic_irq, ++ xgene_msi_isr, msi_group); ++ + /* + * Statically allocate MSI GIC IRQs to each CPU core. + * With 8-core X-Gene v1, 2 MSI GIC IRQs are allocated +-- +2.30.1 + diff --git a/queue-5.4/platform-olpc-fix-probe-error-handling.patch b/queue-5.4/platform-olpc-fix-probe-error-handling.patch new file mode 100644 index 00000000000..0947f4e89f7 --- /dev/null +++ b/queue-5.4/platform-olpc-fix-probe-error-handling.patch @@ -0,0 +1,60 @@ +From 232f1d681e9e22185014f9c802aaf9d5da959cb2 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 26 Jan 2021 08:37:38 +0100 +Subject: Platform: OLPC: Fix probe error handling + +From: Lubomir Rintel + +[ Upstream commit cec551ea0d41c679ed11d758e1a386e20285b29d ] + +Reset ec_priv if probe ends unsuccessfully. + +Signed-off-by: Lubomir Rintel +Link: https://lore.kernel.org/r/20210126073740.10232-2-lkundrak@v3.sk +Reviewed-by: Hans de Goede +Signed-off-by: Hans de Goede +Signed-off-by: Sasha Levin +--- + drivers/platform/olpc/olpc-ec.c | 15 ++++++++------- + 1 file changed, 8 insertions(+), 7 deletions(-) + +diff --git a/drivers/platform/olpc/olpc-ec.c b/drivers/platform/olpc/olpc-ec.c +index f64b82824db2..2db7113383fd 100644 +--- a/drivers/platform/olpc/olpc-ec.c ++++ b/drivers/platform/olpc/olpc-ec.c +@@ -426,11 +426,8 @@ static int olpc_ec_probe(struct platform_device *pdev) + + /* get the EC revision */ + err = olpc_ec_cmd(EC_FIRMWARE_REV, NULL, 0, &ec->version, 1); +- if (err) { +- ec_priv = NULL; +- kfree(ec); +- return err; +- } ++ if (err) ++ goto error; + + config.dev = pdev->dev.parent; + config.driver_data = ec; +@@ -440,12 +437,16 @@ static int olpc_ec_probe(struct platform_device *pdev) + if (IS_ERR(ec->dcon_rdev)) { + dev_err(&pdev->dev, "failed to register DCON regulator\n"); + err = PTR_ERR(ec->dcon_rdev); +- kfree(ec); +- return err; ++ goto error; + } + + ec->dbgfs_dir = olpc_ec_setup_debugfs(); + ++ return 0; ++ ++error: ++ ec_priv = NULL; ++ kfree(ec); + return err; + } + +-- +2.30.1 + diff --git a/queue-5.4/powerpc-64-fix-stack-trace-not-displaying-final-fram.patch b/queue-5.4/powerpc-64-fix-stack-trace-not-displaying-final-fram.patch new file mode 100644 index 00000000000..daa876a5813 --- /dev/null +++ b/queue-5.4/powerpc-64-fix-stack-trace-not-displaying-final-fram.patch @@ -0,0 +1,113 @@ +From 2f6038c5d406e80ccc8851c855e508e13e989b76 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 10 Feb 2021 00:59:20 +1100 +Subject: powerpc/64: Fix stack trace not displaying final frame + +From: Michael Ellerman + +[ Upstream commit e3de1e291fa58a1ab0f471a4b458eff2514e4b5f ] + +In commit bf13718bc57a ("powerpc: show registers when unwinding +interrupt frames") we changed our stack dumping logic to show the full +registers whenever we find an interrupt frame on the stack. + +However we didn't notice that on 64-bit this doesn't show the final +frame, ie. the interrupt that brought us in from userspace, whereas on +32-bit it does. + +That is due to confusion about the size of that last frame. The code +in show_stack() calls validate_sp(), passing it STACK_INT_FRAME_SIZE +to check the sp is at least that far below the top of the stack. + +However on 64-bit that size is too large for the final frame, because +it includes the red zone, but we don't allocate a red zone for the +first frame. + +So add a new define that encodes the correct size for 32-bit and +64-bit, and use it in show_stack(). + +This results in the full trace being shown on 64-bit, eg: + + sysrq: Trigger a crash + Kernel panic - not syncing: sysrq triggered crash + CPU: 0 PID: 83 Comm: sh Not tainted 5.11.0-rc2-gcc-8.2.0-00188-g571abcb96b10-dirty #649 + Call Trace: + [c00000000a1c3ac0] [c000000000897b70] dump_stack+0xc4/0x114 (unreliable) + [c00000000a1c3b00] [c00000000014334c] panic+0x178/0x41c + [c00000000a1c3ba0] [c00000000094e600] sysrq_handle_crash+0x40/0x50 + [c00000000a1c3c00] [c00000000094ef98] __handle_sysrq+0xd8/0x210 + [c00000000a1c3ca0] [c00000000094f820] write_sysrq_trigger+0x100/0x188 + [c00000000a1c3ce0] [c0000000005559dc] proc_reg_write+0x10c/0x1b0 + [c00000000a1c3d10] [c000000000479950] vfs_write+0xf0/0x360 + [c00000000a1c3d60] [c000000000479d9c] ksys_write+0x7c/0x140 + [c00000000a1c3db0] [c00000000002bf5c] system_call_exception+0x19c/0x2c0 + [c00000000a1c3e10] [c00000000000d35c] system_call_common+0xec/0x278 + --- interrupt: c00 at 0x7fff9fbab428 + NIP: 00007fff9fbab428 LR: 000000001000b724 CTR: 0000000000000000 + REGS: c00000000a1c3e80 TRAP: 0c00 Not tainted (5.11.0-rc2-gcc-8.2.0-00188-g571abcb96b10-dirty) + MSR: 900000000280f033 CR: 22002884 XER: 00000000 + IRQMASK: 0 + GPR00: 0000000000000004 00007fffc3cb8960 00007fff9fc59900 0000000000000001 + GPR04: 000000002a4b32d0 0000000000000002 0000000000000063 0000000000000063 + GPR08: 000000002a4b32d0 0000000000000000 0000000000000000 0000000000000000 + GPR12: 0000000000000000 00007fff9fcca9a0 0000000000000000 0000000000000000 + GPR16: 0000000000000000 0000000000000000 0000000000000000 00000000100b8fd0 + GPR20: 000000002a4b3485 00000000100b8f90 0000000000000000 0000000000000000 + GPR24: 000000002a4b0440 00000000100e77b8 0000000000000020 000000002a4b32d0 + GPR28: 0000000000000001 0000000000000002 000000002a4b32d0 0000000000000001 + NIP [00007fff9fbab428] 0x7fff9fbab428 + LR [000000001000b724] 0x1000b724 + --- interrupt: c00 + +Signed-off-by: Michael Ellerman +Link: https://lore.kernel.org/r/20210209141627.2898485-1-mpe@ellerman.id.au +Signed-off-by: Sasha Levin +--- + arch/powerpc/include/asm/ptrace.h | 3 +++ + arch/powerpc/kernel/asm-offsets.c | 2 +- + arch/powerpc/kernel/process.c | 2 +- + 3 files changed, 5 insertions(+), 2 deletions(-) + +diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/ptrace.h +index c41220f4aad9..5a424f867c82 100644 +--- a/arch/powerpc/include/asm/ptrace.h ++++ b/arch/powerpc/include/asm/ptrace.h +@@ -62,6 +62,9 @@ struct pt_regs + }; + #endif + ++ ++#define STACK_FRAME_WITH_PT_REGS (STACK_FRAME_OVERHEAD + sizeof(struct pt_regs)) ++ + #ifdef __powerpc64__ + + /* +diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c +index 5c0a1e17219b..af399675248e 100644 +--- a/arch/powerpc/kernel/asm-offsets.c ++++ b/arch/powerpc/kernel/asm-offsets.c +@@ -285,7 +285,7 @@ int main(void) + + /* Interrupt register frame */ + DEFINE(INT_FRAME_SIZE, STACK_INT_FRAME_SIZE); +- DEFINE(SWITCH_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs)); ++ DEFINE(SWITCH_FRAME_SIZE, STACK_FRAME_WITH_PT_REGS); + STACK_PT_REGS_OFFSET(GPR0, gpr[0]); + STACK_PT_REGS_OFFSET(GPR1, gpr[1]); + STACK_PT_REGS_OFFSET(GPR2, gpr[2]); +diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c +index bd0c258a1d5d..c94bba9142e7 100644 +--- a/arch/powerpc/kernel/process.c ++++ b/arch/powerpc/kernel/process.c +@@ -2081,7 +2081,7 @@ void show_stack(struct task_struct *tsk, unsigned long *stack) + * See if this is an exception frame. + * We look for the "regshere" marker in the current frame. + */ +- if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE) ++ if (validate_sp(sp, tsk, STACK_FRAME_WITH_PT_REGS) + && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) { + struct pt_regs *regs = (struct pt_regs *) + (sp + STACK_FRAME_OVERHEAD); +-- +2.30.1 + diff --git a/queue-5.4/powerpc-improve-handling-of-unrecoverable-system-res.patch b/queue-5.4/powerpc-improve-handling-of-unrecoverable-system-res.patch new file mode 100644 index 00000000000..3a00cd71310 --- /dev/null +++ b/queue-5.4/powerpc-improve-handling-of-unrecoverable-system-res.patch @@ -0,0 +1,41 @@ +From f0ab916262c3b74972507e75460664d73dd72e25 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 30 Jan 2021 23:08:35 +1000 +Subject: powerpc: improve handling of unrecoverable system reset + +From: Nicholas Piggin + +[ Upstream commit 11cb0a25f71818ca7ab4856548ecfd83c169aa4d ] + +If an unrecoverable system reset hits in process context, the system +does not have to panic. Similar to machine check, call nmi_exit() +before die(). + +Signed-off-by: Nicholas Piggin +Signed-off-by: Michael Ellerman +Link: https://lore.kernel.org/r/20210130130852.2952424-26-npiggin@gmail.com +Signed-off-by: Sasha Levin +--- + arch/powerpc/kernel/traps.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c +index 206032c9b545..ecfa460f66d1 100644 +--- a/arch/powerpc/kernel/traps.c ++++ b/arch/powerpc/kernel/traps.c +@@ -513,8 +513,11 @@ void system_reset_exception(struct pt_regs *regs) + die("Unrecoverable nested System Reset", regs, SIGABRT); + #endif + /* Must die if the interrupt is not recoverable */ +- if (!(regs->msr & MSR_RI)) ++ if (!(regs->msr & MSR_RI)) { ++ /* For the reason explained in die_mce, nmi_exit before die */ ++ nmi_exit(); + die("Unrecoverable System Reset", regs, SIGABRT); ++ } + + if (saved_hsrrs) { + mtspr(SPRN_HSRR0, hsrr0); +-- +2.30.1 + diff --git a/queue-5.4/powerpc-pci-add-ppc_md.discover_phbs.patch b/queue-5.4/powerpc-pci-add-ppc_md.discover_phbs.patch new file mode 100644 index 00000000000..e1104886012 --- /dev/null +++ b/queue-5.4/powerpc-pci-add-ppc_md.discover_phbs.patch @@ -0,0 +1,90 @@ +From 4f6ab940338f9de4b3169428879e284cdb0f06a2 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 3 Nov 2020 15:35:06 +1100 +Subject: powerpc/pci: Add ppc_md.discover_phbs() + +From: Oliver O'Halloran + +[ Upstream commit 5537fcb319d016ce387f818dd774179bc03217f5 ] + +On many powerpc platforms the discovery and initalisation of +pci_controllers (PHBs) happens inside of setup_arch(). This is very early +in boot (pre-initcalls) and means that we're initialising the PHB long +before many basic kernel services (slab allocator, debugfs, a real ioremap) +are available. + +On PowerNV this causes an additional problem since we map the PHB registers +with ioremap(). As of commit d538aadc2718 ("powerpc/ioremap: warn on early +use of ioremap()") a warning is printed because we're using the "incorrect" +API to setup and MMIO mapping in searly boot. The kernel does provide +early_ioremap(), but that is not intended to create long-lived MMIO +mappings and a seperate warning is printed by generic code if +early_ioremap() mappings are "leaked." + +This is all fixable with dumb hacks like using early_ioremap() to setup +the initial mapping then replacing it with a real ioremap later on in +boot, but it does raise the question: Why the hell are we setting up the +PHB's this early in boot? + +The old and wise claim it's due to "hysterical rasins." Aside from amused +grapes there doesn't appear to be any real reason to maintain the current +behaviour. Already most of the newer embedded platforms perform PHB +discovery in an arch_initcall and between the end of setup_arch() and the +start of initcalls none of the generic kernel code does anything PCI +related. On powerpc scanning PHBs occurs in a subsys_initcall so it should +be possible to move the PHB discovery to a core, postcore or arch initcall. + +This patch adds the ppc_md.discover_phbs hook and a core_initcall stub that +calls it. The core_initcalls are the earliest to be called so this will +any possibly issues with dependency between initcalls. This isn't just an +academic issue either since on pseries and PowerNV EEH init occurs in an +arch_initcall and depends on the pci_controllers being available, similarly +the creation of pci_dns occurs at core_initcall_sync (i.e. between core and +postcore initcalls). These problems need to be addressed seperately. + +Reported-by: kernel test robot +Signed-off-by: Oliver O'Halloran +[mpe: Make discover_phbs() static] +Signed-off-by: Michael Ellerman +Link: https://lore.kernel.org/r/20201103043523.916109-1-oohall@gmail.com +Signed-off-by: Sasha Levin +--- + arch/powerpc/include/asm/machdep.h | 3 +++ + arch/powerpc/kernel/pci-common.c | 10 ++++++++++ + 2 files changed, 13 insertions(+) + +diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h +index 7bcb64444a39..f71c361dc356 100644 +--- a/arch/powerpc/include/asm/machdep.h ++++ b/arch/powerpc/include/asm/machdep.h +@@ -59,6 +59,9 @@ struct machdep_calls { + int (*pcibios_root_bridge_prepare)(struct pci_host_bridge + *bridge); + ++ /* finds all the pci_controllers present at boot */ ++ void (*discover_phbs)(void); ++ + /* To setup PHBs when using automatic OF platform driver for PCI */ + int (*pci_setup_phb)(struct pci_controller *host); + +diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c +index 1c448cf25506..a2c258a8d736 100644 +--- a/arch/powerpc/kernel/pci-common.c ++++ b/arch/powerpc/kernel/pci-common.c +@@ -1669,3 +1669,13 @@ static void fixup_hide_host_resource_fsl(struct pci_dev *dev) + } + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl); + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl); ++ ++ ++static int __init discover_phbs(void) ++{ ++ if (ppc_md.discover_phbs) ++ ppc_md.discover_phbs(); ++ ++ return 0; ++} ++core_initcall(discover_phbs); +-- +2.30.1 + diff --git a/queue-5.4/powerpc-perf-record-counter-overflow-always-if-sampl.patch b/queue-5.4/powerpc-perf-record-counter-overflow-always-if-sampl.patch new file mode 100644 index 00000000000..c4e6ef11060 --- /dev/null +++ b/queue-5.4/powerpc-perf-record-counter-overflow-always-if-sampl.patch @@ -0,0 +1,80 @@ +From b707d4736b3a528f957208345ffc0f69976b0ff9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 5 Feb 2021 04:14:52 -0500 +Subject: powerpc/perf: Record counter overflow always if SAMPLE_IP is unset + +From: Athira Rajeev + +[ Upstream commit d137845c973147a22622cc76c7b0bc16f6206323 ] + +While sampling for marked events, currently we record the sample only +if the SIAR valid bit of Sampled Instruction Event Register (SIER) is +set. SIAR_VALID bit is used for fetching the instruction address from +Sampled Instruction Address Register(SIAR). But there are some +usecases, where the user is interested only in the PMU stats at each +counter overflow and the exact IP of the overflow event is not +required. Dropping SIAR invalid samples will fail to record some of +the counter overflows in such cases. + +Example of such usecase is dumping the PMU stats (event counts) after +some regular amount of instructions/events from the userspace (ex: via +ptrace). Here counter overflow is indicated to userspace via signal +handler, and captured by monitoring and enabling I/O signaling on the +event file descriptor. In these cases, we expect to get +sample/overflow indication after each specified sample_period. + +Perf event attribute will not have PERF_SAMPLE_IP set in the +sample_type if exact IP of the overflow event is not requested. So +while profiling if SAMPLE_IP is not set, just record the counter +overflow irrespective of SIAR_VALID check. + +Suggested-by: Michael Ellerman +Signed-off-by: Athira Rajeev +[mpe: Reflow comment and if formatting] +Signed-off-by: Michael Ellerman +Link: https://lore.kernel.org/r/1612516492-1428-1-git-send-email-atrajeev@linux.vnet.ibm.com +Signed-off-by: Sasha Levin +--- + arch/powerpc/perf/core-book3s.c | 19 +++++++++++++++---- + 1 file changed, 15 insertions(+), 4 deletions(-) + +diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c +index 02fc75ddcbb3..6f013e418834 100644 +--- a/arch/powerpc/perf/core-book3s.c ++++ b/arch/powerpc/perf/core-book3s.c +@@ -2077,7 +2077,17 @@ static void record_and_restart(struct perf_event *event, unsigned long val, + left += period; + if (left <= 0) + left = period; +- record = siar_valid(regs); ++ ++ /* ++ * If address is not requested in the sample via ++ * PERF_SAMPLE_IP, just record that sample irrespective ++ * of SIAR valid check. ++ */ ++ if (event->attr.sample_type & PERF_SAMPLE_IP) ++ record = siar_valid(regs); ++ else ++ record = 1; ++ + event->hw.last_period = event->hw.sample_period; + } + if (left < 0x80000000LL) +@@ -2095,9 +2105,10 @@ static void record_and_restart(struct perf_event *event, unsigned long val, + * MMCR2. Check attr.exclude_kernel and address to drop the sample in + * these cases. + */ +- if (event->attr.exclude_kernel && record) +- if (is_kernel_addr(mfspr(SPRN_SIAR))) +- record = 0; ++ if (event->attr.exclude_kernel && ++ (event->attr.sample_type & PERF_SAMPLE_IP) && ++ is_kernel_addr(mfspr(SPRN_SIAR))) ++ record = 0; + + /* + * Finally record data if requested. +-- +2.30.1 + diff --git a/queue-5.4/s390-smp-__smp_rescan_cpus-move-cpumask-away-from-st.patch b/queue-5.4/s390-smp-__smp_rescan_cpus-move-cpumask-away-from-st.patch new file mode 100644 index 00000000000..0b2f6ef0a31 --- /dev/null +++ b/queue-5.4/s390-smp-__smp_rescan_cpus-move-cpumask-away-from-st.patch @@ -0,0 +1,36 @@ +From 69ff458703017f54ad50cf5621644cf69338300d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 17 Feb 2021 07:13:02 +0100 +Subject: s390/smp: __smp_rescan_cpus() - move cpumask away from stack + +From: Heiko Carstens + +[ Upstream commit 62c8dca9e194326802b43c60763f856d782b225c ] + +Avoid a potentially large stack frame and overflow by making +"cpumask_t avail" a static variable. There is no concurrent +access due to the existing locking. + +Signed-off-by: Heiko Carstens +Signed-off-by: Vasily Gorbik +Signed-off-by: Sasha Levin +--- + arch/s390/kernel/smp.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c +index 659d99af9156..8c51462f13fd 100644 +--- a/arch/s390/kernel/smp.c ++++ b/arch/s390/kernel/smp.c +@@ -765,7 +765,7 @@ static int smp_add_core(struct sclp_core_entry *core, cpumask_t *avail, + static int __smp_rescan_cpus(struct sclp_core_info *info, bool early) + { + struct sclp_core_entry *core; +- cpumask_t avail; ++ static cpumask_t avail; + bool configured; + u16 core_id; + int nr, i; +-- +2.30.1 + diff --git a/queue-5.4/scsi-libiscsi-fix-iscsi_prep_scsi_cmd_pdu-error-hand.patch b/queue-5.4/scsi-libiscsi-fix-iscsi_prep_scsi_cmd_pdu-error-hand.patch new file mode 100644 index 00000000000..886f8540d60 --- /dev/null +++ b/queue-5.4/scsi-libiscsi-fix-iscsi_prep_scsi_cmd_pdu-error-hand.patch @@ -0,0 +1,50 @@ +From 5b44b9745a26e833c50a8053ce45fcd341a62b6b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 6 Feb 2021 22:46:00 -0600 +Subject: scsi: libiscsi: Fix iscsi_prep_scsi_cmd_pdu() error handling + +From: Mike Christie + +[ Upstream commit d28d48c699779973ab9a3bd0e5acfa112bd4fdef ] + +If iscsi_prep_scsi_cmd_pdu() fails we try to add it back to the cmdqueue, +but we leave it partially setup. We don't have functions that can undo the +pdu and init task setup. We only have cleanup_task which can clean up both +parts. So this has us just fail the cmd and go through the standard cleanup +routine and then have the SCSI midlayer retry it like is done when it fails +in the queuecommand path. + +Link: https://lore.kernel.org/r/20210207044608.27585-2-michael.christie@oracle.com +Reviewed-by: Lee Duncan +Signed-off-by: Mike Christie +Signed-off-by: Martin K. Petersen +Signed-off-by: Sasha Levin +--- + drivers/scsi/libiscsi.c | 11 +++-------- + 1 file changed, 3 insertions(+), 8 deletions(-) + +diff --git a/drivers/scsi/libiscsi.c b/drivers/scsi/libiscsi.c +index a14057c67a12..c5b7d18513b6 100644 +--- a/drivers/scsi/libiscsi.c ++++ b/drivers/scsi/libiscsi.c +@@ -1532,14 +1532,9 @@ static int iscsi_data_xmit(struct iscsi_conn *conn) + } + rc = iscsi_prep_scsi_cmd_pdu(conn->task); + if (rc) { +- if (rc == -ENOMEM || rc == -EACCES) { +- spin_lock_bh(&conn->taskqueuelock); +- list_add_tail(&conn->task->running, +- &conn->cmdqueue); +- conn->task = NULL; +- spin_unlock_bh(&conn->taskqueuelock); +- goto done; +- } else ++ if (rc == -ENOMEM || rc == -EACCES) ++ fail_scsi_task(conn->task, DID_IMM_RETRY); ++ else + fail_scsi_task(conn->task, DID_ABORT); + spin_lock_bh(&conn->taskqueuelock); + continue; +-- +2.30.1 + diff --git a/queue-5.4/scsi-target-core-add-cmd-length-set-before-cmd-compl.patch b/queue-5.4/scsi-target-core-add-cmd-length-set-before-cmd-compl.patch new file mode 100644 index 00000000000..b0daec47b49 --- /dev/null +++ b/queue-5.4/scsi-target-core-add-cmd-length-set-before-cmd-compl.patch @@ -0,0 +1,77 @@ +From 0ef25170fa0c83e6c43a8554705b90bbe761e540 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 9 Feb 2021 10:22:01 +0300 +Subject: scsi: target: core: Add cmd length set before cmd complete + +From: Aleksandr Miloserdov + +[ Upstream commit 1c73e0c5e54d5f7d77f422a10b03ebe61eaed5ad ] + +TCM doesn't properly handle underflow case for service actions. One way to +prevent it is to always complete command with +target_complete_cmd_with_length(), however it requires access to data_sg, +which is not always available. + +This change introduces target_set_cmd_data_length() function which allows +to set command data length before completing it. + +Link: https://lore.kernel.org/r/20210209072202.41154-2-a.miloserdov@yadro.com +Reviewed-by: Roman Bolshakov +Reviewed-by: Bodo Stroesser +Signed-off-by: Aleksandr Miloserdov +Signed-off-by: Martin K. Petersen +Signed-off-by: Sasha Levin +--- + drivers/target/target_core_transport.c | 15 +++++++++++---- + include/target/target_core_backend.h | 1 + + 2 files changed, 12 insertions(+), 4 deletions(-) + +diff --git a/drivers/target/target_core_transport.c b/drivers/target/target_core_transport.c +index b1f4be055f83..a16835c0bb1d 100644 +--- a/drivers/target/target_core_transport.c ++++ b/drivers/target/target_core_transport.c +@@ -873,11 +873,9 @@ void target_complete_cmd(struct se_cmd *cmd, u8 scsi_status) + } + EXPORT_SYMBOL(target_complete_cmd); + +-void target_complete_cmd_with_length(struct se_cmd *cmd, u8 scsi_status, int length) ++void target_set_cmd_data_length(struct se_cmd *cmd, int length) + { +- if ((scsi_status == SAM_STAT_GOOD || +- cmd->se_cmd_flags & SCF_TREAT_READ_AS_NORMAL) && +- length < cmd->data_length) { ++ if (length < cmd->data_length) { + if (cmd->se_cmd_flags & SCF_UNDERFLOW_BIT) { + cmd->residual_count += cmd->data_length - length; + } else { +@@ -887,6 +885,15 @@ void target_complete_cmd_with_length(struct se_cmd *cmd, u8 scsi_status, int len + + cmd->data_length = length; + } ++} ++EXPORT_SYMBOL(target_set_cmd_data_length); ++ ++void target_complete_cmd_with_length(struct se_cmd *cmd, u8 scsi_status, int length) ++{ ++ if (scsi_status == SAM_STAT_GOOD || ++ cmd->se_cmd_flags & SCF_TREAT_READ_AS_NORMAL) { ++ target_set_cmd_data_length(cmd, length); ++ } + + target_complete_cmd(cmd, scsi_status); + } +diff --git a/include/target/target_core_backend.h b/include/target/target_core_backend.h +index 51b6f50eabee..0deeff9b4496 100644 +--- a/include/target/target_core_backend.h ++++ b/include/target/target_core_backend.h +@@ -69,6 +69,7 @@ int transport_backend_register(const struct target_backend_ops *); + void target_backend_unregister(const struct target_backend_ops *); + + void target_complete_cmd(struct se_cmd *, u8); ++void target_set_cmd_data_length(struct se_cmd *, int); + void target_complete_cmd_with_length(struct se_cmd *, u8, int); + + void transport_copy_sense_to_cmd(struct se_cmd *, unsigned char *); +-- +2.30.1 + diff --git a/queue-5.4/scsi-target-core-prevent-underflow-for-service-actio.patch b/queue-5.4/scsi-target-core-prevent-underflow-for-service-actio.patch new file mode 100644 index 00000000000..1cfddf639a5 --- /dev/null +++ b/queue-5.4/scsi-target-core-prevent-underflow-for-service-actio.patch @@ -0,0 +1,102 @@ +From b9b33eb267122ee3a9831bced17e0102d725782b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 9 Feb 2021 10:22:02 +0300 +Subject: scsi: target: core: Prevent underflow for service actions + +From: Aleksandr Miloserdov + +[ Upstream commit 14d24e2cc77411301e906a8cf41884739de192de ] + +TCM buffer length doesn't necessarily equal 8 + ADDITIONAL LENGTH which +might be considered an underflow in case of Data-In size being greater than +8 + ADDITIONAL LENGTH. So truncate buffer length to prevent underflow. + +Link: https://lore.kernel.org/r/20210209072202.41154-3-a.miloserdov@yadro.com +Reviewed-by: Roman Bolshakov +Reviewed-by: Bodo Stroesser +Signed-off-by: Aleksandr Miloserdov +Signed-off-by: Martin K. Petersen +Signed-off-by: Sasha Levin +--- + drivers/target/target_core_pr.c | 15 +++++++++++---- + 1 file changed, 11 insertions(+), 4 deletions(-) + +diff --git a/drivers/target/target_core_pr.c b/drivers/target/target_core_pr.c +index 5e931690e697..51e690ab4d29 100644 +--- a/drivers/target/target_core_pr.c ++++ b/drivers/target/target_core_pr.c +@@ -3731,6 +3731,7 @@ core_scsi3_pri_read_keys(struct se_cmd *cmd) + spin_unlock(&dev->t10_pr.registration_lock); + + put_unaligned_be32(add_len, &buf[4]); ++ target_set_cmd_data_length(cmd, 8 + add_len); + + transport_kunmap_data_sg(cmd); + +@@ -3749,7 +3750,7 @@ core_scsi3_pri_read_reservation(struct se_cmd *cmd) + struct t10_pr_registration *pr_reg; + unsigned char *buf; + u64 pr_res_key; +- u32 add_len = 16; /* Hardcoded to 16 when a reservation is held. */ ++ u32 add_len = 0; + + if (cmd->data_length < 8) { + pr_err("PRIN SA READ_RESERVATIONS SCSI Data Length: %u" +@@ -3767,8 +3768,9 @@ core_scsi3_pri_read_reservation(struct se_cmd *cmd) + pr_reg = dev->dev_pr_res_holder; + if (pr_reg) { + /* +- * Set the hardcoded Additional Length ++ * Set the Additional Length to 16 when a reservation is held + */ ++ add_len = 16; + put_unaligned_be32(add_len, &buf[4]); + + if (cmd->data_length < 22) +@@ -3804,6 +3806,8 @@ core_scsi3_pri_read_reservation(struct se_cmd *cmd) + (pr_reg->pr_res_type & 0x0f); + } + ++ target_set_cmd_data_length(cmd, 8 + add_len); ++ + err: + spin_unlock(&dev->dev_reservation_lock); + transport_kunmap_data_sg(cmd); +@@ -3822,7 +3826,7 @@ core_scsi3_pri_report_capabilities(struct se_cmd *cmd) + struct se_device *dev = cmd->se_dev; + struct t10_reservation *pr_tmpl = &dev->t10_pr; + unsigned char *buf; +- u16 add_len = 8; /* Hardcoded to 8. */ ++ u16 len = 8; /* Hardcoded to 8. */ + + if (cmd->data_length < 6) { + pr_err("PRIN SA REPORT_CAPABILITIES SCSI Data Length:" +@@ -3834,7 +3838,7 @@ core_scsi3_pri_report_capabilities(struct se_cmd *cmd) + if (!buf) + return TCM_LOGICAL_UNIT_COMMUNICATION_FAILURE; + +- put_unaligned_be16(add_len, &buf[0]); ++ put_unaligned_be16(len, &buf[0]); + buf[2] |= 0x10; /* CRH: Compatible Reservation Hanlding bit. */ + buf[2] |= 0x08; /* SIP_C: Specify Initiator Ports Capable bit */ + buf[2] |= 0x04; /* ATP_C: All Target Ports Capable bit */ +@@ -3863,6 +3867,8 @@ core_scsi3_pri_report_capabilities(struct se_cmd *cmd) + buf[4] |= 0x02; /* PR_TYPE_WRITE_EXCLUSIVE */ + buf[5] |= 0x01; /* PR_TYPE_EXCLUSIVE_ACCESS_ALLREG */ + ++ target_set_cmd_data_length(cmd, len); ++ + transport_kunmap_data_sg(cmd); + + return 0; +@@ -4023,6 +4029,7 @@ core_scsi3_pri_read_full_status(struct se_cmd *cmd) + * Set ADDITIONAL_LENGTH + */ + put_unaligned_be32(add_len, &buf[4]); ++ target_set_cmd_data_length(cmd, 8 + add_len); + + transport_kunmap_data_sg(cmd); + +-- +2.30.1 + diff --git a/queue-5.4/series b/queue-5.4/series index 0a383c848e5..050b2952f6d 100644 --- a/queue-5.4/series +++ b/queue-5.4/series @@ -62,3 +62,44 @@ net-hns3-fix-error-mask-definition-of-flow-director.patch mips-kernel-reserve-exception-base-early-to-prevent-.patch net-enetc-initialize-rfs-rss-memories-for-unused-por.patch net-phy-fix-save-wrong-speed-and-duplex-problem-if-a.patch +i2c-rcar-faster-irq-code-to-minimize-hw-race-conditi.patch +i2c-rcar-optimize-cacheline-to-minimize-hw-race-cond.patch +udf-fix-silent-aed-taglocation-corruption.patch +mmc-mxs-mmc-fix-a-resource-leak-in-an-error-handling.patch +mmc-mediatek-fix-race-condition-between-msdc_request.patch +platform-olpc-fix-probe-error-handling.patch +powerpc-pci-add-ppc_md.discover_phbs.patch +spi-stm32-make-spurious-and-overrun-interrupts-visib.patch +powerpc-improve-handling-of-unrecoverable-system-res.patch +powerpc-perf-record-counter-overflow-always-if-sampl.patch +hid-logitech-dj-add-support-for-the-new-lightspeed-c.patch +powerpc-64-fix-stack-trace-not-displaying-final-fram.patch +iommu-amd-fix-performance-counter-initialization.patch +sparc32-limit-memblock-allocation-to-low-memory.patch +sparc64-use-arch_validate_flags-to-validate-adi-flag.patch +input-applespi-don-t-wait-for-responses-to-commands-.patch +pci-xgene-msi-fix-race-in-installing-chained-irq-han.patch +pci-mediatek-add-missing-of_node_put-to-fix-referenc.patch +kbuild-clamp-sublevel-to-255.patch +pci-fix-pci_register_io_range-memory-leak.patch +i40e-fix-memory-leak-in-i40e_probe.patch +s390-smp-__smp_rescan_cpus-move-cpumask-away-from-st.patch +sysctl.c-fix-underflow-value-setting-risk-in-vm_tabl.patch +scsi-libiscsi-fix-iscsi_prep_scsi_cmd_pdu-error-hand.patch +scsi-target-core-add-cmd-length-set-before-cmd-compl.patch +scsi-target-core-prevent-underflow-for-service-actio.patch +crypto-arm-use-kconfig-based-compiler-checks-for-cry.patch +arm-8929-1-use-apsr_nzcv-instead-of-r15-as-mrc-opera.patch +arm-8933-1-replace-sun-solaris-style-flag-on-section.patch +kbuild-add-support-for-as-instr-to-be-used-in-kconfi.patch +crypto-arm-ghash-ce-define-fpu-before-fpu-registers-.patch +arm-omap2-drop-unnecessary-adrl.patch +arm-8971-1-replace-the-sole-use-of-a-symbol-with-its.patch +kbuild-add-config_ld_is_lld.patch +arm-8989-1-use-.fpu-assembler-directives-instead-of-.patch +arm-8990-1-use-vfp-assembler-mnemonics-in-register-l.patch +arm-8991-1-use-vfp-assembler-mnemonics-if-available.patch +crypto-arm-sha256-neon-avoid-adrl-pseudo-instruction.patch +crypto-arm-sha512-neon-avoid-adrl-pseudo-instruction.patch +arm-9025-1-kconfig-cpu_big_endian-depends-on-ld_is_l.patch +arm-9029-1-make-iwmmxt.s-support-clang-s-integrated-.patch diff --git a/queue-5.4/sparc32-limit-memblock-allocation-to-low-memory.patch b/queue-5.4/sparc32-limit-memblock-allocation-to-low-memory.patch new file mode 100644 index 00000000000..8050ce0a912 --- /dev/null +++ b/queue-5.4/sparc32-limit-memblock-allocation-to-low-memory.patch @@ -0,0 +1,42 @@ +From 12359d1fc668e6818cb3f135749be2b59b5bc8f2 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 5 Feb 2021 14:20:31 +0100 +Subject: sparc32: Limit memblock allocation to low memory + +From: Andreas Larsson + +[ Upstream commit bda166930c37604ffa93f2425426af6921ec575a ] + +Commit cca079ef8ac29a7c02192d2bad2ffe4c0c5ffdd0 changed sparc32 to use +memblocks instead of bootmem, but also made high memory available via +memblock allocation which does not work together with e.g. phys_to_virt +and can lead to kernel panic. + +This changes back to only low memory being allocatable in the early +stages, now using memblock allocation. + +Signed-off-by: Andreas Larsson +Acked-by: Mike Rapoport +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + arch/sparc/mm/init_32.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/arch/sparc/mm/init_32.c b/arch/sparc/mm/init_32.c +index 906eda1158b4..40dd6cb4a413 100644 +--- a/arch/sparc/mm/init_32.c ++++ b/arch/sparc/mm/init_32.c +@@ -197,6 +197,9 @@ unsigned long __init bootmem_init(unsigned long *pages_avail) + size = memblock_phys_mem_size() - memblock_reserved_size(); + *pages_avail = (size >> PAGE_SHIFT) - high_pages; + ++ /* Only allow low memory to be allocated via memblock allocation */ ++ memblock_set_current_limit(max_low_pfn << PAGE_SHIFT); ++ + return max_pfn; + } + +-- +2.30.1 + diff --git a/queue-5.4/sparc64-use-arch_validate_flags-to-validate-adi-flag.patch b/queue-5.4/sparc64-use-arch_validate_flags-to-validate-adi-flag.patch new file mode 100644 index 00000000000..179ece1117d --- /dev/null +++ b/queue-5.4/sparc64-use-arch_validate_flags-to-validate-adi-flag.patch @@ -0,0 +1,108 @@ +From f9598c79106684445ed54a39180bbb9f05e0a610 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 23 Oct 2020 11:56:11 -0600 +Subject: sparc64: Use arch_validate_flags() to validate ADI flag + +From: Khalid Aziz + +[ Upstream commit 147d8622f2a26ef34beacc60e1ed8b66c2fa457f ] + +When userspace calls mprotect() to enable ADI on an address range, +do_mprotect_pkey() calls arch_validate_prot() to validate new +protection flags. arch_validate_prot() for sparc looks at the first +VMA associated with address range to verify if ADI can indeed be +enabled on this address range. This has two issues - (1) Address +range might cover multiple VMAs while arch_validate_prot() looks at +only the first VMA, (2) arch_validate_prot() peeks at VMA without +holding mmap lock which can result in race condition. + +arch_validate_flags() from commit c462ac288f2c ("mm: Introduce +arch_validate_flags()") allows for VMA flags to be validated for all +VMAs that cover the address range given by user while holding mmap +lock. This patch updates sparc code to move the VMA check from +arch_validate_prot() to arch_validate_flags() to fix above two +issues. + +Suggested-by: Jann Horn +Suggested-by: Christoph Hellwig +Suggested-by: Catalin Marinas +Signed-off-by: Khalid Aziz +Reviewed-by: Catalin Marinas +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + arch/sparc/include/asm/mman.h | 54 +++++++++++++++++++---------------- + 1 file changed, 29 insertions(+), 25 deletions(-) + +diff --git a/arch/sparc/include/asm/mman.h b/arch/sparc/include/asm/mman.h +index f94532f25db1..274217e7ed70 100644 +--- a/arch/sparc/include/asm/mman.h ++++ b/arch/sparc/include/asm/mman.h +@@ -57,35 +57,39 @@ static inline int sparc_validate_prot(unsigned long prot, unsigned long addr) + { + if (prot & ~(PROT_READ | PROT_WRITE | PROT_EXEC | PROT_SEM | PROT_ADI)) + return 0; +- if (prot & PROT_ADI) { +- if (!adi_capable()) +- return 0; ++ return 1; ++} + +- if (addr) { +- struct vm_area_struct *vma; ++#define arch_validate_flags(vm_flags) arch_validate_flags(vm_flags) ++/* arch_validate_flags() - Ensure combination of flags is valid for a ++ * VMA. ++ */ ++static inline bool arch_validate_flags(unsigned long vm_flags) ++{ ++ /* If ADI is being enabled on this VMA, check for ADI ++ * capability on the platform and ensure VMA is suitable ++ * for ADI ++ */ ++ if (vm_flags & VM_SPARC_ADI) { ++ if (!adi_capable()) ++ return false; + +- vma = find_vma(current->mm, addr); +- if (vma) { +- /* ADI can not be enabled on PFN +- * mapped pages +- */ +- if (vma->vm_flags & (VM_PFNMAP | VM_MIXEDMAP)) +- return 0; ++ /* ADI can not be enabled on PFN mapped pages */ ++ if (vm_flags & (VM_PFNMAP | VM_MIXEDMAP)) ++ return false; + +- /* Mergeable pages can become unmergeable +- * if ADI is enabled on them even if they +- * have identical data on them. This can be +- * because ADI enabled pages with identical +- * data may still not have identical ADI +- * tags on them. Disallow ADI on mergeable +- * pages. +- */ +- if (vma->vm_flags & VM_MERGEABLE) +- return 0; +- } +- } ++ /* Mergeable pages can become unmergeable ++ * if ADI is enabled on them even if they ++ * have identical data on them. This can be ++ * because ADI enabled pages with identical ++ * data may still not have identical ADI ++ * tags on them. Disallow ADI on mergeable ++ * pages. ++ */ ++ if (vm_flags & VM_MERGEABLE) ++ return false; + } +- return 1; ++ return true; + } + #endif /* CONFIG_SPARC64 */ + +-- +2.30.1 + diff --git a/queue-5.4/spi-stm32-make-spurious-and-overrun-interrupts-visib.patch b/queue-5.4/spi-stm32-make-spurious-and-overrun-interrupts-visib.patch new file mode 100644 index 00000000000..789c31ffb0c --- /dev/null +++ b/queue-5.4/spi-stm32-make-spurious-and-overrun-interrupts-visib.patch @@ -0,0 +1,60 @@ +From 89281917693719025c694d6c3cc6487f5e3e398e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 5 Feb 2021 19:59:32 +0100 +Subject: spi: stm32: make spurious and overrun interrupts visible + +From: Alain Volmat + +[ Upstream commit c64e7efe46b7de21937ef4b3594d9b1fc74f07df ] + +We do not expect to receive spurious interrupts so rise a warning +if it happens. + +RX overrun is an error condition that signals a corrupted RX +stream both in dma and in irq modes. Report the error and +abort the transfer in either cases. + +Signed-off-by: Alain Volmat +Link: https://lore.kernel.org/r/1612551572-495-9-git-send-email-alain.volmat@foss.st.com +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + drivers/spi/spi-stm32.c | 15 ++++----------- + 1 file changed, 4 insertions(+), 11 deletions(-) + +diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c +index 8622cf9d3f64..9e7a6de3c43d 100644 +--- a/drivers/spi/spi-stm32.c ++++ b/drivers/spi/spi-stm32.c +@@ -924,8 +924,8 @@ static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id) + mask |= STM32H7_SPI_SR_RXP; + + if (!(sr & mask)) { +- dev_dbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n", +- sr, ier); ++ dev_warn(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n", ++ sr, ier); + spin_unlock_irqrestore(&spi->lock, flags); + return IRQ_NONE; + } +@@ -952,15 +952,8 @@ static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id) + } + + if (sr & STM32H7_SPI_SR_OVR) { +- dev_warn(spi->dev, "Overrun: received value discarded\n"); +- if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) +- stm32h7_spi_read_rxfifo(spi, false); +- /* +- * If overrun is detected while using DMA, it means that +- * something went wrong, so stop the current transfer +- */ +- if (spi->cur_usedma) +- end = true; ++ dev_err(spi->dev, "Overrun: RX data lost\n"); ++ end = true; + } + + if (sr & STM32H7_SPI_SR_EOT) { +-- +2.30.1 + diff --git a/queue-5.4/sysctl.c-fix-underflow-value-setting-risk-in-vm_tabl.patch b/queue-5.4/sysctl.c-fix-underflow-value-setting-risk-in-vm_tabl.patch new file mode 100644 index 00000000000..3d2e5afb455 --- /dev/null +++ b/queue-5.4/sysctl.c-fix-underflow-value-setting-risk-in-vm_tabl.patch @@ -0,0 +1,73 @@ +From 7cb6138e36f39f0f9aea6327028bd67583aa5ed3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 25 Feb 2021 17:20:53 -0800 +Subject: sysctl.c: fix underflow value setting risk in vm_table + +From: Lin Feng + +[ Upstream commit 3b3376f222e3ab58367d9dd405cafd09d5e37b7c ] + +Apart from subsystem specific .proc_handler handler, all ctl_tables with +extra1 and extra2 members set should use proc_dointvec_minmax instead of +proc_dointvec, or the limit set in extra* never work and potentially echo +underflow values(negative numbers) is likely make system unstable. + +Especially vfs_cache_pressure and zone_reclaim_mode, -1 is apparently not +a valid value, but we can set to them. And then kernel may crash. + +# echo -1 > /proc/sys/vm/vfs_cache_pressure + +Link: https://lkml.kernel.org/r/20201223105535.2875-1-linf@wangsu.com +Signed-off-by: Lin Feng +Cc: Alexey Dobriyan +Cc: "Eric W. Biederman" +Signed-off-by: Andrew Morton +Signed-off-by: Linus Torvalds +Signed-off-by: Sasha Levin +--- + kernel/sysctl.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/kernel/sysctl.c b/kernel/sysctl.c +index 70665934d53e..eae6a078619f 100644 +--- a/kernel/sysctl.c ++++ b/kernel/sysctl.c +@@ -1563,7 +1563,7 @@ static struct ctl_table vm_table[] = { + .data = &block_dump, + .maxlen = sizeof(block_dump), + .mode = 0644, +- .proc_handler = proc_dointvec, ++ .proc_handler = proc_dointvec_minmax, + .extra1 = SYSCTL_ZERO, + }, + { +@@ -1571,7 +1571,7 @@ static struct ctl_table vm_table[] = { + .data = &sysctl_vfs_cache_pressure, + .maxlen = sizeof(sysctl_vfs_cache_pressure), + .mode = 0644, +- .proc_handler = proc_dointvec, ++ .proc_handler = proc_dointvec_minmax, + .extra1 = SYSCTL_ZERO, + }, + #if defined(HAVE_ARCH_PICK_MMAP_LAYOUT) || \ +@@ -1581,7 +1581,7 @@ static struct ctl_table vm_table[] = { + .data = &sysctl_legacy_va_layout, + .maxlen = sizeof(sysctl_legacy_va_layout), + .mode = 0644, +- .proc_handler = proc_dointvec, ++ .proc_handler = proc_dointvec_minmax, + .extra1 = SYSCTL_ZERO, + }, + #endif +@@ -1591,7 +1591,7 @@ static struct ctl_table vm_table[] = { + .data = &node_reclaim_mode, + .maxlen = sizeof(node_reclaim_mode), + .mode = 0644, +- .proc_handler = proc_dointvec, ++ .proc_handler = proc_dointvec_minmax, + .extra1 = SYSCTL_ZERO, + }, + { +-- +2.30.1 + diff --git a/queue-5.4/udf-fix-silent-aed-taglocation-corruption.patch b/queue-5.4/udf-fix-silent-aed-taglocation-corruption.patch new file mode 100644 index 00000000000..acf318df23a --- /dev/null +++ b/queue-5.4/udf-fix-silent-aed-taglocation-corruption.patch @@ -0,0 +1,53 @@ +From 157e0da99cd45cbd330a7ef7829899364eddeaa7 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 7 Jan 2021 17:41:16 -0600 +Subject: udf: fix silent AED tagLocation corruption + +From: Steven J. Magnani + +[ Upstream commit 63c9e47a1642fc817654a1bc18a6ec4bbcc0f056 ] + +When extending a file, udf_do_extend_file() may enter following empty +indirect extent. At the end of udf_do_extend_file() we revert prev_epos +to point to the last written extent. However if we end up not adding any +further extent in udf_do_extend_file(), the reverting points prev_epos +into the header area of the AED and following updates of the extents +(in udf_update_extents()) will corrupt the header. + +Make sure that we do not follow indirect extent if we are not going to +add any more extents so that returning back to the last written extent +works correctly. + +Link: https://lore.kernel.org/r/20210107234116.6190-2-magnani@ieee.org +Signed-off-by: Steven J. Magnani +Signed-off-by: Jan Kara +Signed-off-by: Sasha Levin +--- + fs/udf/inode.c | 9 ++++++--- + 1 file changed, 6 insertions(+), 3 deletions(-) + +diff --git a/fs/udf/inode.c b/fs/udf/inode.c +index 97a192eb9949..507f8f910327 100644 +--- a/fs/udf/inode.c ++++ b/fs/udf/inode.c +@@ -547,11 +547,14 @@ static int udf_do_extend_file(struct inode *inode, + + udf_write_aext(inode, last_pos, &last_ext->extLocation, + last_ext->extLength, 1); ++ + /* +- * We've rewritten the last extent but there may be empty +- * indirect extent after it - enter it. ++ * We've rewritten the last extent. If we are going to add ++ * more extents, we may need to enter possible following ++ * empty indirect extent. + */ +- udf_next_aext(inode, last_pos, &tmploc, &tmplen, 0); ++ if (new_block_bytes || prealloc_len) ++ udf_next_aext(inode, last_pos, &tmploc, &tmplen, 0); + } + + /* Managed to do everything necessary? */ +-- +2.30.1 + -- 2.47.3