From 31d12caeb7c99bab8483e10c5e540902d024f7df Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Fri, 26 May 2023 20:27:38 +0100 Subject: [PATCH] drop x86-mm-avoid-incomplete-global-invlpg-flushes.patch from a bunch of queues --- queue-4.14/series | 1 - ...oid-incomplete-global-invlpg-flushes.patch | 85 ------------------- queue-4.19/series | 1 - ...oid-incomplete-global-invlpg-flushes.patch | 85 ------------------- queue-5.10/series | 1 - ...oid-incomplete-global-invlpg-flushes.patch | 85 ------------------- queue-5.15/series | 1 - ...oid-incomplete-global-invlpg-flushes.patch | 85 ------------------- queue-5.4/series | 1 - ...oid-incomplete-global-invlpg-flushes.patch | 85 ------------------- 10 files changed, 430 deletions(-) delete mode 100644 queue-4.14/x86-mm-avoid-incomplete-global-invlpg-flushes.patch delete mode 100644 queue-4.19/x86-mm-avoid-incomplete-global-invlpg-flushes.patch delete mode 100644 queue-5.10/x86-mm-avoid-incomplete-global-invlpg-flushes.patch delete mode 100644 queue-5.15/x86-mm-avoid-incomplete-global-invlpg-flushes.patch delete mode 100644 queue-5.4/x86-mm-avoid-incomplete-global-invlpg-flushes.patch diff --git a/queue-4.14/series b/queue-4.14/series index 7ac53535841..61363cf230f 100644 --- a/queue-4.14/series +++ b/queue-4.14/series @@ -55,7 +55,6 @@ netfilter-nf_tables-bogus-ebusy-in-helper-removal-from-transaction.patch spi-spi-fsl-spi-automatically-adapt-bits-per-word-in-cpu-mode.patch spi-fsl-spi-re-organise-transfer-bits_per_word-adaptation.patch spi-fsl-cpm-use-16-bit-mode-for-large-transfers-with-even-size.patch -x86-mm-avoid-incomplete-global-invlpg-flushes.patch alsa-hda-fix-unhandled-register-update-during-auto-suspend-period.patch m68k-move-signal-frame-following-exception-on-68020-030.patch parisc-allow-to-reboot-machine-after-system-halt.patch diff --git a/queue-4.14/x86-mm-avoid-incomplete-global-invlpg-flushes.patch b/queue-4.14/x86-mm-avoid-incomplete-global-invlpg-flushes.patch deleted file mode 100644 index cfcb1d29066..00000000000 --- a/queue-4.14/x86-mm-avoid-incomplete-global-invlpg-flushes.patch +++ /dev/null @@ -1,85 +0,0 @@ -From ce0b15d11ad837fbacc5356941712218e38a0a83 Mon Sep 17 00:00:00 2001 -From: Dave Hansen -Date: Tue, 16 May 2023 12:24:25 -0700 -Subject: x86/mm: Avoid incomplete Global INVLPG flushes - -From: Dave Hansen - -commit ce0b15d11ad837fbacc5356941712218e38a0a83 upstream. - -The INVLPG instruction is used to invalidate TLB entries for a -specified virtual address. When PCIDs are enabled, INVLPG is supposed -to invalidate TLB entries for the specified address for both the -current PCID *and* Global entries. (Note: Only kernel mappings set -Global=1.) - -Unfortunately, some INVLPG implementations can leave Global -translations unflushed when PCIDs are enabled. - -As a workaround, never enable PCIDs on affected processors. - -I expect there to eventually be microcode mitigations to replace this -software workaround. However, the exact version numbers where that -will happen are not known today. Once the version numbers are set in -stone, the processor list can be tweaked to only disable PCIDs on -affected processors with affected microcode. - -Note: if anyone wants a quick fix that doesn't require patching, just -stick 'nopcid' on your kernel command-line. - -Signed-off-by: Dave Hansen -Reviewed-by: Thomas Gleixner -Cc: stable@vger.kernel.org -Signed-off-by: Greg Kroah-Hartman ---- - arch/x86/mm/init.c | 25 +++++++++++++++++++++++++ - 1 file changed, 25 insertions(+) - ---- a/arch/x86/mm/init.c -+++ b/arch/x86/mm/init.c -@@ -8,6 +8,7 @@ - #include - - #include -+#include - #include - #include - #include -@@ -199,6 +200,24 @@ static void __init probe_page_size_mask( - } - } - -+#define INTEL_MATCH(_model) { .vendor = X86_VENDOR_INTEL, \ -+ .family = 6, \ -+ .model = _model, \ -+ } -+/* -+ * INVLPG may not properly flush Global entries -+ * on these CPUs when PCIDs are enabled. -+ */ -+static const struct x86_cpu_id invlpg_miss_ids[] = { -+ INTEL_MATCH(INTEL_FAM6_ALDERLAKE ), -+ INTEL_MATCH(INTEL_FAM6_ALDERLAKE_L ), -+ INTEL_MATCH(INTEL_FAM6_ALDERLAKE_N ), -+ INTEL_MATCH(INTEL_FAM6_RAPTORLAKE ), -+ INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_P), -+ INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_S), -+ {} -+}; -+ - static void setup_pcid(void) - { - if (!IS_ENABLED(CONFIG_X86_64)) -@@ -207,6 +226,12 @@ static void setup_pcid(void) - if (!boot_cpu_has(X86_FEATURE_PCID)) - return; - -+ if (x86_match_cpu(invlpg_miss_ids)) { -+ pr_info("Incomplete global flushes, disabling PCID"); -+ setup_clear_cpu_cap(X86_FEATURE_PCID); -+ return; -+ } -+ - if (boot_cpu_has(X86_FEATURE_PGE)) { - /* - * This can't be cr4_set_bits_and_update_boot() -- the diff --git a/queue-4.19/series b/queue-4.19/series index a3f2cdbe8c8..5f236dc7dcd 100644 --- a/queue-4.19/series +++ b/queue-4.19/series @@ -103,7 +103,6 @@ s390-qdio-fix-do_sqbs-inline-assembly-constraint.patch spi-spi-fsl-spi-automatically-adapt-bits-per-word-in-cpu-mode.patch spi-fsl-spi-re-organise-transfer-bits_per_word-adaptation.patch spi-fsl-cpm-use-16-bit-mode-for-large-transfers-with-even-size.patch -x86-mm-avoid-incomplete-global-invlpg-flushes.patch alsa-hda-ca0132-add-quirk-for-evga-x299-dark.patch alsa-hda-fix-unhandled-register-update-during-auto-suspend-period.patch m68k-move-signal-frame-following-exception-on-68020-030.patch diff --git a/queue-4.19/x86-mm-avoid-incomplete-global-invlpg-flushes.patch b/queue-4.19/x86-mm-avoid-incomplete-global-invlpg-flushes.patch deleted file mode 100644 index b9576408b58..00000000000 --- a/queue-4.19/x86-mm-avoid-incomplete-global-invlpg-flushes.patch +++ /dev/null @@ -1,85 +0,0 @@ -From ce0b15d11ad837fbacc5356941712218e38a0a83 Mon Sep 17 00:00:00 2001 -From: Dave Hansen -Date: Tue, 16 May 2023 12:24:25 -0700 -Subject: x86/mm: Avoid incomplete Global INVLPG flushes - -From: Dave Hansen - -commit ce0b15d11ad837fbacc5356941712218e38a0a83 upstream. - -The INVLPG instruction is used to invalidate TLB entries for a -specified virtual address. When PCIDs are enabled, INVLPG is supposed -to invalidate TLB entries for the specified address for both the -current PCID *and* Global entries. (Note: Only kernel mappings set -Global=1.) - -Unfortunately, some INVLPG implementations can leave Global -translations unflushed when PCIDs are enabled. - -As a workaround, never enable PCIDs on affected processors. - -I expect there to eventually be microcode mitigations to replace this -software workaround. However, the exact version numbers where that -will happen are not known today. Once the version numbers are set in -stone, the processor list can be tweaked to only disable PCIDs on -affected processors with affected microcode. - -Note: if anyone wants a quick fix that doesn't require patching, just -stick 'nopcid' on your kernel command-line. - -Signed-off-by: Dave Hansen -Reviewed-by: Thomas Gleixner -Cc: stable@vger.kernel.org -Signed-off-by: Greg Kroah-Hartman ---- - arch/x86/mm/init.c | 25 +++++++++++++++++++++++++ - 1 file changed, 25 insertions(+) - ---- a/arch/x86/mm/init.c -+++ b/arch/x86/mm/init.c -@@ -9,6 +9,7 @@ - #include - - #include -+#include - #include - #include - #include -@@ -207,6 +208,24 @@ static void __init probe_page_size_mask( - } - } - -+#define INTEL_MATCH(_model) { .vendor = X86_VENDOR_INTEL, \ -+ .family = 6, \ -+ .model = _model, \ -+ } -+/* -+ * INVLPG may not properly flush Global entries -+ * on these CPUs when PCIDs are enabled. -+ */ -+static const struct x86_cpu_id invlpg_miss_ids[] = { -+ INTEL_MATCH(INTEL_FAM6_ALDERLAKE ), -+ INTEL_MATCH(INTEL_FAM6_ALDERLAKE_L ), -+ INTEL_MATCH(INTEL_FAM6_ALDERLAKE_N ), -+ INTEL_MATCH(INTEL_FAM6_RAPTORLAKE ), -+ INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_P), -+ INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_S), -+ {} -+}; -+ - static void setup_pcid(void) - { - if (!IS_ENABLED(CONFIG_X86_64)) -@@ -215,6 +234,12 @@ static void setup_pcid(void) - if (!boot_cpu_has(X86_FEATURE_PCID)) - return; - -+ if (x86_match_cpu(invlpg_miss_ids)) { -+ pr_info("Incomplete global flushes, disabling PCID"); -+ setup_clear_cpu_cap(X86_FEATURE_PCID); -+ return; -+ } -+ - if (boot_cpu_has(X86_FEATURE_PGE)) { - /* - * This can't be cr4_set_bits_and_update_boot() -- the diff --git a/queue-5.10/series b/queue-5.10/series index b9e0912bb8c..cb00c585934 100644 --- a/queue-5.10/series +++ b/queue-5.10/series @@ -165,7 +165,6 @@ act_mirred-use-the-backlog-for-nested-calls-to-mirred-ingress.patch spi-fsl-spi-re-organise-transfer-bits_per_word-adaptation.patch spi-fsl-cpm-use-16-bit-mode-for-large-transfers-with-even-size.patch ocfs2-switch-to-security_inode_init_security.patch -x86-mm-avoid-incomplete-global-invlpg-flushes.patch alsa-hda-ca0132-add-quirk-for-evga-x299-dark.patch alsa-hda-fix-unhandled-register-update-during-auto-suspend-period.patch alsa-hda-realtek-enable-headset-onlenovo-m70-m90.patch diff --git a/queue-5.10/x86-mm-avoid-incomplete-global-invlpg-flushes.patch b/queue-5.10/x86-mm-avoid-incomplete-global-invlpg-flushes.patch deleted file mode 100644 index 972d93c9c0f..00000000000 --- a/queue-5.10/x86-mm-avoid-incomplete-global-invlpg-flushes.patch +++ /dev/null @@ -1,85 +0,0 @@ -From ce0b15d11ad837fbacc5356941712218e38a0a83 Mon Sep 17 00:00:00 2001 -From: Dave Hansen -Date: Tue, 16 May 2023 12:24:25 -0700 -Subject: x86/mm: Avoid incomplete Global INVLPG flushes - -From: Dave Hansen - -commit ce0b15d11ad837fbacc5356941712218e38a0a83 upstream. - -The INVLPG instruction is used to invalidate TLB entries for a -specified virtual address. When PCIDs are enabled, INVLPG is supposed -to invalidate TLB entries for the specified address for both the -current PCID *and* Global entries. (Note: Only kernel mappings set -Global=1.) - -Unfortunately, some INVLPG implementations can leave Global -translations unflushed when PCIDs are enabled. - -As a workaround, never enable PCIDs on affected processors. - -I expect there to eventually be microcode mitigations to replace this -software workaround. However, the exact version numbers where that -will happen are not known today. Once the version numbers are set in -stone, the processor list can be tweaked to only disable PCIDs on -affected processors with affected microcode. - -Note: if anyone wants a quick fix that doesn't require patching, just -stick 'nopcid' on your kernel command-line. - -Signed-off-by: Dave Hansen -Reviewed-by: Thomas Gleixner -Cc: stable@vger.kernel.org -Signed-off-by: Greg Kroah-Hartman ---- - arch/x86/mm/init.c | 25 +++++++++++++++++++++++++ - 1 file changed, 25 insertions(+) - ---- a/arch/x86/mm/init.c -+++ b/arch/x86/mm/init.c -@@ -9,6 +9,7 @@ - #include - - #include -+#include - #include - #include - #include -@@ -254,6 +255,24 @@ static void __init probe_page_size_mask( - } - } - -+#define INTEL_MATCH(_model) { .vendor = X86_VENDOR_INTEL, \ -+ .family = 6, \ -+ .model = _model, \ -+ } -+/* -+ * INVLPG may not properly flush Global entries -+ * on these CPUs when PCIDs are enabled. -+ */ -+static const struct x86_cpu_id invlpg_miss_ids[] = { -+ INTEL_MATCH(INTEL_FAM6_ALDERLAKE ), -+ INTEL_MATCH(INTEL_FAM6_ALDERLAKE_L ), -+ INTEL_MATCH(INTEL_FAM6_ALDERLAKE_N ), -+ INTEL_MATCH(INTEL_FAM6_RAPTORLAKE ), -+ INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_P), -+ INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_S), -+ {} -+}; -+ - static void setup_pcid(void) - { - if (!IS_ENABLED(CONFIG_X86_64)) -@@ -262,6 +281,12 @@ static void setup_pcid(void) - if (!boot_cpu_has(X86_FEATURE_PCID)) - return; - -+ if (x86_match_cpu(invlpg_miss_ids)) { -+ pr_info("Incomplete global flushes, disabling PCID"); -+ setup_clear_cpu_cap(X86_FEATURE_PCID); -+ return; -+ } -+ - if (boot_cpu_has(X86_FEATURE_PGE)) { - /* - * This can't be cr4_set_bits_and_update_boot() -- the diff --git a/queue-5.15/series b/queue-5.15/series index 46603427eaa..607604f589e 100644 --- a/queue-5.15/series +++ b/queue-5.15/series @@ -8,7 +8,6 @@ spi-fsl-spi-re-organise-transfer-bits_per_word-adaptation.patch spi-fsl-cpm-use-16-bit-mode-for-large-transfers-with-even-size.patch ocfs2-switch-to-security_inode_init_security.patch arm64-also-reset-kasan-tag-if-page-is-not-pg_mte_tagged.patch -x86-mm-avoid-incomplete-global-invlpg-flushes.patch alsa-hda-ca0132-add-quirk-for-evga-x299-dark.patch alsa-hda-fix-unhandled-register-update-during-auto-suspend-period.patch alsa-hda-realtek-enable-headset-onlenovo-m70-m90.patch diff --git a/queue-5.15/x86-mm-avoid-incomplete-global-invlpg-flushes.patch b/queue-5.15/x86-mm-avoid-incomplete-global-invlpg-flushes.patch deleted file mode 100644 index ef71ba8aa95..00000000000 --- a/queue-5.15/x86-mm-avoid-incomplete-global-invlpg-flushes.patch +++ /dev/null @@ -1,85 +0,0 @@ -From ce0b15d11ad837fbacc5356941712218e38a0a83 Mon Sep 17 00:00:00 2001 -From: Dave Hansen -Date: Tue, 16 May 2023 12:24:25 -0700 -Subject: x86/mm: Avoid incomplete Global INVLPG flushes - -From: Dave Hansen - -commit ce0b15d11ad837fbacc5356941712218e38a0a83 upstream. - -The INVLPG instruction is used to invalidate TLB entries for a -specified virtual address. When PCIDs are enabled, INVLPG is supposed -to invalidate TLB entries for the specified address for both the -current PCID *and* Global entries. (Note: Only kernel mappings set -Global=1.) - -Unfortunately, some INVLPG implementations can leave Global -translations unflushed when PCIDs are enabled. - -As a workaround, never enable PCIDs on affected processors. - -I expect there to eventually be microcode mitigations to replace this -software workaround. However, the exact version numbers where that -will happen are not known today. Once the version numbers are set in -stone, the processor list can be tweaked to only disable PCIDs on -affected processors with affected microcode. - -Note: if anyone wants a quick fix that doesn't require patching, just -stick 'nopcid' on your kernel command-line. - -Signed-off-by: Dave Hansen -Reviewed-by: Thomas Gleixner -Cc: stable@vger.kernel.org -Signed-off-by: Greg Kroah-Hartman ---- - arch/x86/mm/init.c | 25 +++++++++++++++++++++++++ - 1 file changed, 25 insertions(+) - ---- a/arch/x86/mm/init.c -+++ b/arch/x86/mm/init.c -@@ -9,6 +9,7 @@ - #include - - #include -+#include - #include - #include - #include -@@ -261,6 +262,24 @@ static void __init probe_page_size_mask( - } - } - -+#define INTEL_MATCH(_model) { .vendor = X86_VENDOR_INTEL, \ -+ .family = 6, \ -+ .model = _model, \ -+ } -+/* -+ * INVLPG may not properly flush Global entries -+ * on these CPUs when PCIDs are enabled. -+ */ -+static const struct x86_cpu_id invlpg_miss_ids[] = { -+ INTEL_MATCH(INTEL_FAM6_ALDERLAKE ), -+ INTEL_MATCH(INTEL_FAM6_ALDERLAKE_L ), -+ INTEL_MATCH(INTEL_FAM6_ALDERLAKE_N ), -+ INTEL_MATCH(INTEL_FAM6_RAPTORLAKE ), -+ INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_P), -+ INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_S), -+ {} -+}; -+ - static void setup_pcid(void) - { - if (!IS_ENABLED(CONFIG_X86_64)) -@@ -269,6 +288,12 @@ static void setup_pcid(void) - if (!boot_cpu_has(X86_FEATURE_PCID)) - return; - -+ if (x86_match_cpu(invlpg_miss_ids)) { -+ pr_info("Incomplete global flushes, disabling PCID"); -+ setup_clear_cpu_cap(X86_FEATURE_PCID); -+ return; -+ } -+ - if (boot_cpu_has(X86_FEATURE_PGE)) { - /* - * This can't be cr4_set_bits_and_update_boot() -- the diff --git a/queue-5.4/series b/queue-5.4/series index 2237985f4e8..dc855a65c27 100644 --- a/queue-5.4/series +++ b/queue-5.4/series @@ -124,7 +124,6 @@ watchdog-sp5100_tco-immediately-trigger-upon-starting.patch spi-fsl-spi-re-organise-transfer-bits_per_word-adaptation.patch spi-fsl-cpm-use-16-bit-mode-for-large-transfers-with-even-size.patch mt76-mt7615-fix-build-with-older-compilers.patch -x86-mm-avoid-incomplete-global-invlpg-flushes.patch alsa-hda-ca0132-add-quirk-for-evga-x299-dark.patch alsa-hda-fix-unhandled-register-update-during-auto-suspend-period.patch alsa-hda-realtek-enable-headset-onlenovo-m70-m90.patch diff --git a/queue-5.4/x86-mm-avoid-incomplete-global-invlpg-flushes.patch b/queue-5.4/x86-mm-avoid-incomplete-global-invlpg-flushes.patch deleted file mode 100644 index fa989204da3..00000000000 --- a/queue-5.4/x86-mm-avoid-incomplete-global-invlpg-flushes.patch +++ /dev/null @@ -1,85 +0,0 @@ -From ce0b15d11ad837fbacc5356941712218e38a0a83 Mon Sep 17 00:00:00 2001 -From: Dave Hansen -Date: Tue, 16 May 2023 12:24:25 -0700 -Subject: x86/mm: Avoid incomplete Global INVLPG flushes - -From: Dave Hansen - -commit ce0b15d11ad837fbacc5356941712218e38a0a83 upstream. - -The INVLPG instruction is used to invalidate TLB entries for a -specified virtual address. When PCIDs are enabled, INVLPG is supposed -to invalidate TLB entries for the specified address for both the -current PCID *and* Global entries. (Note: Only kernel mappings set -Global=1.) - -Unfortunately, some INVLPG implementations can leave Global -translations unflushed when PCIDs are enabled. - -As a workaround, never enable PCIDs on affected processors. - -I expect there to eventually be microcode mitigations to replace this -software workaround. However, the exact version numbers where that -will happen are not known today. Once the version numbers are set in -stone, the processor list can be tweaked to only disable PCIDs on -affected processors with affected microcode. - -Note: if anyone wants a quick fix that doesn't require patching, just -stick 'nopcid' on your kernel command-line. - -Signed-off-by: Dave Hansen -Reviewed-by: Thomas Gleixner -Cc: stable@vger.kernel.org -Signed-off-by: Greg Kroah-Hartman ---- - arch/x86/mm/init.c | 25 +++++++++++++++++++++++++ - 1 file changed, 25 insertions(+) - ---- a/arch/x86/mm/init.c -+++ b/arch/x86/mm/init.c -@@ -9,6 +9,7 @@ - #include - - #include -+#include - #include - #include - #include -@@ -208,6 +209,24 @@ static void __init probe_page_size_mask( - } - } - -+#define INTEL_MATCH(_model) { .vendor = X86_VENDOR_INTEL, \ -+ .family = 6, \ -+ .model = _model, \ -+ } -+/* -+ * INVLPG may not properly flush Global entries -+ * on these CPUs when PCIDs are enabled. -+ */ -+static const struct x86_cpu_id invlpg_miss_ids[] = { -+ INTEL_MATCH(INTEL_FAM6_ALDERLAKE ), -+ INTEL_MATCH(INTEL_FAM6_ALDERLAKE_L ), -+ INTEL_MATCH(INTEL_FAM6_ALDERLAKE_N ), -+ INTEL_MATCH(INTEL_FAM6_RAPTORLAKE ), -+ INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_P), -+ INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_S), -+ {} -+}; -+ - static void setup_pcid(void) - { - if (!IS_ENABLED(CONFIG_X86_64)) -@@ -216,6 +235,12 @@ static void setup_pcid(void) - if (!boot_cpu_has(X86_FEATURE_PCID)) - return; - -+ if (x86_match_cpu(invlpg_miss_ids)) { -+ pr_info("Incomplete global flushes, disabling PCID"); -+ setup_clear_cpu_cap(X86_FEATURE_PCID); -+ return; -+ } -+ - if (boot_cpu_has(X86_FEATURE_PGE)) { - /* - * This can't be cr4_set_bits_and_update_boot() -- the -- 2.47.3