From 3586ee221dcaa492ff85a65c4ddb89e883b3e9af Mon Sep 17 00:00:00 2001
From: ktkachov <ktkachov@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Tue, 9 Jun 2015 08:15:23 +0000
Subject: [PATCH] [GCC, ARM] armv8 linux toolchain asan testcase fail due to
 stl missing conditional code

On behalf of Shiva Chen

2015-06-09  Shiva Chen  <shiva0217@gmail.com>

	* sync.md (atomic_load<mode>): Add conditional code for lda/ldr
	(atomic_store<mode>): Likewise.

2015-06-09  Shiva Chen  <shiva0217@gmail.com>

	* gcc.target/arm/stl-cond.c: New test.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@224269 138bc75d-0d04-0410-961f-82ee72b054a4
---
 gcc/ChangeLog                           |  5 +++++
 gcc/config/arm/sync.md                  | 14 ++++++++------
 gcc/testsuite/ChangeLog                 |  4 ++++
 gcc/testsuite/gcc.target/arm/stl-cond.c | 19 +++++++++++++++++++
 4 files changed, 36 insertions(+), 6 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/arm/stl-cond.c

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4af34951803f..95a6df4e3fa0 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2015-06-09  Shiva Chen  <shiva0217@gmail.com>
+
+	* sync.md (atomic_load<mode>): Add conditional code for lda/ldr
+	(atomic_store<mode>): Likewise.
+
 2015-06-09  Richard Biener  <rguenther@suse.de>
 
 	* cfgloop.c (get_loop_body_in_bfs_order): Fix assert.
diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md
index 44cda61d2738..75dd52ea3aa9 100644
--- a/gcc/config/arm/sync.md
+++ b/gcc/config/arm/sync.md
@@ -75,11 +75,12 @@
   {
     enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
     if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_release (model))
-      return \"ldr<sync_sfx>\\t%0, %1\";
+      return \"ldr%(<sync_sfx>%)\\t%0, %1\";
     else
-      return \"lda<sync_sfx>\\t%0, %1\";
+      return \"lda<sync_sfx>%?\\t%0, %1\";
   }
-)
+  [(set_attr "predicable" "yes")
+   (set_attr "predicable_short_it" "no")])
 
 (define_insn "atomic_store<mode>"
   [(set (match_operand:QHSI 0 "memory_operand" "=Q")
@@ -91,11 +92,12 @@
   {
     enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
     if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_acquire (model))
-      return \"str<sync_sfx>\t%1, %0\";
+      return \"str%(<sync_sfx>%)\t%1, %0\";
     else
-      return \"stl<sync_sfx>\t%1, %0\";
+      return \"stl<sync_sfx>%?\t%1, %0\";
   }
-)
+  [(set_attr "predicable" "yes")
+   (set_attr "predicable_short_it" "no")])
 
 ;; Note that ldrd and vldr are *not* guaranteed to be single-copy atomic,
 ;; even for a 64-bit aligned address.  Instead we use a ldrexd unparied
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 5c21d29fcd87..a51682a38010 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2015-06-09  Shiva Chen  <shiva0217@gmail.com>
+
+	* gcc.target/arm/stl-cond.c: New test.
+
 2015-06-09  Richard Biener  <rguenther@suse.de>
 
 	PR middle-end/66413
diff --git a/gcc/testsuite/gcc.target/arm/stl-cond.c b/gcc/testsuite/gcc.target/arm/stl-cond.c
new file mode 100644
index 000000000000..de14bb580b82
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/stl-cond.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arm_ok } */ 
+/* { dg-require-effective-target arm_arch_v8a_ok } */
+/* { dg-options "-O2 -marm" } */
+/* { dg-add-options arm_arch_v8a } */
+
+struct backtrace_state
+{
+  int threaded;
+  int lock_alloc;
+};
+
+void foo (struct backtrace_state *state)
+{
+  if (state->threaded)
+    __sync_lock_release (&state->lock_alloc);
+}
+
+/* { dg-final { scan-assembler "stlne" } } */
-- 
2.47.3