From 39012b09a2be22a9222970efbdb65e0f71d158df Mon Sep 17 00:00:00 2001 From: Alexander Ivchenko Date: Mon, 18 Aug 2014 11:02:31 +0000 Subject: [PATCH] i386.c: Rename ufloatv8siv8df_mask to ufloatv8siv8df2_mask. gcc/ * config/i386/i386.c: Rename ufloatv8siv8df_mask to ufloatv8siv8df2_mask. * config/i386/i386.md (define_code_iterator any_float): New. (define_code_attr floatsuffix): New. * config/i386/sse.md (define_mode_iterator VF1_128_256VL): New. (define_mode_iterator VF2_512_256VL): New. (define_insn "float2"): Remove unnecessary TARGET check. (define_insn "ufloatv8siv8df"): Delete. (define_insn "float2"): New. (define_mode_attr qq2pssuff): New. (define_mode_attr sselongvecmode): New. (define_mode_attr sselongvecmodelower): New. (define_mode_attr sseintvecmode3): New. (define_insn "float2"): New. (define_insn "*floatv2div2sf2"): New. (define_insn "floatv2div2sf2_mask"): New. (define_insn "ufloat2"): New. (define_insn "ufloatv2siv2df2"): New. Co-Authored-By: Andrey Turetskiy Co-Authored-By: Anna Tikhonova Co-Authored-By: Ilya Tocar Co-Authored-By: Ilya Verbin Co-Authored-By: Kirill Yukhin Co-Authored-By: Maxim Kuznetsov Co-Authored-By: Michael Zolotukhin From-SVN: r214091 --- gcc/ChangeLog | 32 ++++++++++++++ gcc/config/i386/i386.c | 2 +- gcc/config/i386/i386.md | 4 ++ gcc/config/i386/sse.md | 93 +++++++++++++++++++++++++++++++++++++---- 4 files changed, 123 insertions(+), 8 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5076b9d240bb..2dee41267f05 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,35 @@ +2014-08-18 Alexander Ivchenko + Maxim Kuznetsov + Anna Tikhonova + Ilya Tocar + Andrey Turetskiy + Ilya Verbin + Kirill Yukhin + Michael Zolotukhin + + * config/i386/i386.c: Rename ufloatv8siv8df_mask to ufloatv8siv8df2_mask. + * config/i386/i386.md + (define_code_iterator any_float): New. + (define_code_attr floatsuffix): New. + * config/i386/sse.md + (define_mode_iterator VF1_128_256VL): New. + (define_mode_iterator VF2_512_256VL): New. + (define_insn "float2"): Remove unnecessary + TARGET check. + (define_insn "ufloatv8siv8df"): Delete. + (define_insn "float2"): + New. + (define_mode_attr qq2pssuff): New. + (define_mode_attr sselongvecmode): New. + (define_mode_attr sselongvecmodelower): New. + (define_mode_attr sseintvecmode3): New. + (define_insn "float2"): + New. + (define_insn "*floatv2div2sf2"): New. + (define_insn "floatv2div2sf2_mask"): New. + (define_insn "ufloat2"): New. + (define_insn "ufloatv2siv2df2"): New. + 2014-08-18 Alexander Ivchenko Maxim Kuznetsov Anna Tikhonova diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index de2f4494e5d4..cc4b0c7fe3a0 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -30048,7 +30048,7 @@ static const struct builtin_description bdesc_args[] = { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI }, { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI }, { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtps2ph512_mask, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_HI }, - { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv8siv8df_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI }, + { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv8siv8df2_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI }, { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT }, { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI }, { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expanddf512_maskz", IX86_BUILTIN_EXPANDPD512Z, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI }, diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 39fb23079e1b..9bb7e164e281 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -882,6 +882,10 @@ (define_code_iterator any_fix [fix unsigned_fix]) (define_code_attr fixsuffix [(fix "") (unsigned_fix "u")]) +;; Used in signed and unsigned float. +(define_code_iterator any_float [float unsigned_float]) +(define_code_attr floatsuffix [(float "") (unsigned_float "u")]) + ;; All integer modes. (define_mode_iterator SWI1248x [QI HI SI DI]) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 141c4319b7d0..4dd2af92266c 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -205,6 +205,9 @@ (define_mode_iterator VF1_128_256 [(V8SF "TARGET_AVX") V4SF]) +(define_mode_iterator VF1_128_256VL + [V8SF (V4SF "TARGET_AVX512VL")]) + ;; All DFmode vector float modes (define_mode_iterator VF2 [(V8DF "TARGET_AVX512F") (V4DF "TARGET_AVX") V2DF]) @@ -214,7 +217,10 @@ [(V4DF "TARGET_AVX") V2DF]) (define_mode_iterator VF2_512_256 - [(V8DF "TARGET_AVX512F") (V4DF "TARGET_AVX")]) + [(V8DF "TARGET_AVX512F") V4DF]) + +(define_mode_iterator VF2_512_256VL + [V8DF (V4DF "TARGET_AVX512VL")]) ;; All 128bit vector float modes (define_mode_iterator VF_128 @@ -4096,15 +4102,88 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "")]) -(define_insn "ufloatv8siv8df" - [(set (match_operand:V8DF 0 "register_operand" "=v") - (unsigned_float:V8DF - (match_operand:V8SI 1 "nonimmediate_operand" "vm")))] - "TARGET_AVX512F" +(define_insn "float2" + [(set (match_operand:VF2_AVX512VL 0 "register_operand" "=v") + (any_float:VF2_AVX512VL + (match_operand: 1 "nonimmediate_operand" "vm")))] + "TARGET_AVX512DQ" + "vcvtqq2pd\t{%1, %0|%0, %1}" + [(set_attr "type" "ssecvt") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +;; For float insn patterns +(define_mode_attr qq2pssuff + [(V8SF "") (V4SF "{y}")]) + +(define_mode_attr sselongvecmode + [(V8SF "V8DI") (V4SF "V4DI")]) + +(define_mode_attr sselongvecmodelower + [(V8SF "v8di") (V4SF "v4di")]) + +(define_mode_attr sseintvecmode3 + [(V8SF "XI") (V4SF "OI") + (V8DF "OI") (V4DF "TI")]) + +(define_insn "float2" + [(set (match_operand:VF1_128_256VL 0 "register_operand" "=v") + (any_float:VF1_128_256VL + (match_operand: 1 "nonimmediate_operand" "")))] + "TARGET_AVX512DQ && " + "vcvtqq2ps\t{%1, %0|%0, %1}" + [(set_attr "type" "ssecvt") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "*floatv2div2sf2" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (vec_concat:V4SF + (any_float:V2SF (match_operand:V2DI 1 "nonimmediate_operand" "vm")) + (const_vector:V2SF [(const_int 0) (const_int 0)])))] + "TARGET_AVX512DQ && TARGET_AVX512VL" + "vcvtqq2ps{x}\t{%1, %0|%0, %1}" + [(set_attr "type" "ssecvt") + (set_attr "prefix" "evex") + (set_attr "mode" "V4SF")]) + +(define_insn "floatv2div2sf2_mask" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (vec_concat:V4SF + (vec_merge:V2SF + (any_float:V2SF (match_operand:V2DI 1 "nonimmediate_operand" "vm")) + (vec_select:V2SF + (match_operand:V4SF 2 "vector_move_operand" "0C") + (parallel [(const_int 0) (const_int 1)])) + (match_operand:QI 3 "register_operand" "Yk")) + (const_vector:V2SF [(const_int 0) (const_int 0)])))] + "TARGET_AVX512DQ && TARGET_AVX512VL" + "vcvtqq2ps{x}\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" + [(set_attr "type" "ssecvt") + (set_attr "prefix" "evex") + (set_attr "mode" "V4SF")]) + +(define_insn "ufloat2" + [(set (match_operand:VF2_512_256VL 0 "register_operand" "=v") + (unsigned_float:VF2_512_256VL + (match_operand: 1 "nonimmediate_operand" "vm")))] + "TARGET_AVX512F" + "vcvtudq2pd\t{%1, %0|%0, %1}" + [(set_attr "type" "ssecvt") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "ufloatv2siv2df2" + [(set (match_operand:V2DF 0 "register_operand" "=v") + (unsigned_float:V2DF + (vec_select:V2SI + (match_operand:V4SI 1 "nonimmediate_operand" "vm") + (parallel [(const_int 0) (const_int 1)]))))] + "TARGET_AVX512VL" "vcvtudq2pd\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") - (set_attr "mode" "V8DF")]) + (set_attr "mode" "V2DF")]) (define_insn "avx512f_cvtdq2pd512_2" [(set (match_operand:V8DF 0 "register_operand" "=v") -- 2.47.3