From 39ba61813bd35969e94f8a355167d61ce2cd1fab Mon Sep 17 00:00:00 2001 From: Mike Looijmans Date: Fri, 29 Jul 2016 10:07:57 +0200 Subject: [PATCH] xilinx_zynqmp_zcu102: Set QSPI clock divisor to "9" The zynqmp_qspi driver assumes that the QSPI clock runs at 166666666 Hz, set the divisor such that this is true. The IOPLL runs at 1500, so a divisor of 0x0c would results in 125MHz. The optimal divisor for the zcu102 would be "7", which would run the clock at 214MHz and could thus generate almost 108MHz which is the max clock rate for the flash chips on the board. Signed-off-by: Mike Looijmans Acked-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- board/xilinx/zynqmp/xilinx_zynqmp_zcu102/psu_init_gpl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/xilinx/zynqmp/xilinx_zynqmp_zcu102/psu_init_gpl.c b/board/xilinx/zynqmp/xilinx_zynqmp_zcu102/psu_init_gpl.c index b6e84046412..388b94ca25d 100644 --- a/board/xilinx/zynqmp/xilinx_zynqmp_zcu102/psu_init_gpl.c +++ b/board/xilinx/zynqmp/xilinx_zynqmp_zcu102/psu_init_gpl.c @@ -1078,7 +1078,7 @@ unsigned long psu_clock_init_data() { PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1 0x1 6 bit divider - PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0 0xc + PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0 0x9 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) @@ -1093,7 +1093,7 @@ unsigned long psu_clock_init_data() { | 0x0000000CU << CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT | 0x00000000U << CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_QSPI_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010C00U); + PSU_Mask_Write (CRL_APB_QSPI_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010900U); /*############################################################################################################################ */ /*Register : SDIO0_REF_CTRL @ 0XFF5E006C

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