From 3b9878b20e90ce7c8c752b889eb5a2a0a764725d Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Thu, 20 Jul 2023 20:28:20 +0200 Subject: [PATCH] 6.1-stable patches added patches: drm-amd-pm-add-abnormal-fan-detection-for-smu-13.0.0.patch drm-amd-pm-revise-the-aspm-settings-for-thunderbolt-attached-scenario.patch drm-amdgpu-add-the-fan-abnormal-detection-feature.patch drm-amdgpu-fix-minmax-warning.patch drm-amdgpu-sdma4-set-align-mask-to-255.patch f2fs-fix-deadlock-in-i_xattr_sem-and-inode-page-lock.patch f2fs-fix-the-wrong-condition-to-determine-atomic-context.patch pinctrl-amd-add-z-state-wake-control-bits.patch --- ...bnormal-fan-detection-for-smu-13.0.0.patch | 29 ++++++ ...gs-for-thunderbolt-attached-scenario.patch | 47 ++++++++++ ...d-the-fan-abnormal-detection-feature.patch | 88 ++++++++++++++++++ queue-6.1/drm-amdgpu-fix-minmax-warning.patch | 46 ++++++++++ ...m-amdgpu-sdma4-set-align-mask-to-255.patch | 49 ++++++++++ ...k-in-i_xattr_sem-and-inode-page-lock.patch | 89 +++++++++++++++++++ ...ondition-to-determine-atomic-context.patch | 31 +++++++ ...rl-amd-add-z-state-wake-control-bits.patch | 57 ++++++++++++ queue-6.1/series | 8 ++ 9 files changed, 444 insertions(+) create mode 100644 queue-6.1/drm-amd-pm-add-abnormal-fan-detection-for-smu-13.0.0.patch create mode 100644 queue-6.1/drm-amd-pm-revise-the-aspm-settings-for-thunderbolt-attached-scenario.patch create mode 100644 queue-6.1/drm-amdgpu-add-the-fan-abnormal-detection-feature.patch create mode 100644 queue-6.1/drm-amdgpu-fix-minmax-warning.patch create mode 100644 queue-6.1/drm-amdgpu-sdma4-set-align-mask-to-255.patch create mode 100644 queue-6.1/f2fs-fix-deadlock-in-i_xattr_sem-and-inode-page-lock.patch create mode 100644 queue-6.1/f2fs-fix-the-wrong-condition-to-determine-atomic-context.patch create mode 100644 queue-6.1/pinctrl-amd-add-z-state-wake-control-bits.patch diff --git a/queue-6.1/drm-amd-pm-add-abnormal-fan-detection-for-smu-13.0.0.patch b/queue-6.1/drm-amd-pm-add-abnormal-fan-detection-for-smu-13.0.0.patch new file mode 100644 index 00000000000..94dfeea2c16 --- /dev/null +++ b/queue-6.1/drm-amd-pm-add-abnormal-fan-detection-for-smu-13.0.0.patch @@ -0,0 +1,29 @@ +From 2da0036ea99bccb27f7fe3cf2aa2900860e9be46 Mon Sep 17 00:00:00 2001 +From: Kenneth Feng +Date: Tue, 20 Jun 2023 11:41:40 +0800 +Subject: drm/amd/pm: add abnormal fan detection for smu 13.0.0 + +From: Kenneth Feng + +commit 2da0036ea99bccb27f7fe3cf2aa2900860e9be46 upstream. + +add abnormal fan detection for smu 13.0.0 + +Signed-off-by: Kenneth Feng +Reviewed-by: Evan Quan +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +@@ -1281,6 +1281,7 @@ static int smu_v13_0_0_get_thermal_tempe + range->mem_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)* + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + range->software_shutdown_temp = powerplay_table->software_shutdown_temp; ++ range->software_shutdown_temp_offset = pptable->SkuTable.FanAbnormalTempLimitOffset; + + return 0; + } diff --git a/queue-6.1/drm-amd-pm-revise-the-aspm-settings-for-thunderbolt-attached-scenario.patch b/queue-6.1/drm-amd-pm-revise-the-aspm-settings-for-thunderbolt-attached-scenario.patch new file mode 100644 index 00000000000..4f9039f24d7 --- /dev/null +++ b/queue-6.1/drm-amd-pm-revise-the-aspm-settings-for-thunderbolt-attached-scenario.patch @@ -0,0 +1,47 @@ +From fd21987274463a439c074b8f3c93d3b132e4c031 Mon Sep 17 00:00:00 2001 +From: Evan Quan +Date: Thu, 15 Jun 2023 10:56:55 +0800 +Subject: drm/amd/pm: revise the ASPM settings for thunderbolt attached scenario + +From: Evan Quan + +commit fd21987274463a439c074b8f3c93d3b132e4c031 upstream. + +Also, correct the comment for NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT +as 0x0000000E stands for 400ms instead of 4ms. + +Signed-off-by: Evan Quan +Reviewed-by: Alex Deucher +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 11 +++++++---- + 1 file changed, 7 insertions(+), 4 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c ++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c +@@ -346,7 +346,7 @@ static void nbio_v2_3_init_registers(str + + #define NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT 0x00000000 // off by default, no gains over L1 + #define NAVI10_PCIE__LC_L1_INACTIVITY_DEFAULT 0x00000009 // 1=1us, 9=1ms +-#define NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT 0x0000000E // 4ms ++#define NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT 0x0000000E // 400ms + + static void nbio_v2_3_enable_aspm(struct amdgpu_device *adev, + bool enable) +@@ -479,9 +479,12 @@ static void nbio_v2_3_program_aspm(struc + WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5, data); + + def = data = RREG32_PCIE(smnPCIE_LC_CNTL); +- data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; +- data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; +- data |= 0x1 << PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT; ++ data |= NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT; ++ if (pci_is_thunderbolt_attached(adev->pdev)) ++ data |= NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; ++ else ++ data |= NAVI10_PCIE__LC_L1_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; ++ data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; + if (def != data) + WREG32_PCIE(smnPCIE_LC_CNTL, data); + diff --git a/queue-6.1/drm-amdgpu-add-the-fan-abnormal-detection-feature.patch b/queue-6.1/drm-amdgpu-add-the-fan-abnormal-detection-feature.patch new file mode 100644 index 00000000000..c4a15f4d80a --- /dev/null +++ b/queue-6.1/drm-amdgpu-add-the-fan-abnormal-detection-feature.patch @@ -0,0 +1,88 @@ +From ef5fca9f7294509ee5013af9e879edc5837c1d6c Mon Sep 17 00:00:00 2001 +From: lyndonli +Date: Mon, 21 Nov 2022 09:10:20 +0800 +Subject: drm/amdgpu: add the fan abnormal detection feature + +From: lyndonli + +commit ef5fca9f7294509ee5013af9e879edc5837c1d6c upstream. + +Update the SW CTF limit from existing register +when there's a fan failure detected via SMU interrupt. + +Signed-off-by: lyndonli +Reviewed-by: Hawking Zhang +Reviewed-by: Kenneth Feng +Reviewed-by: Evan Quan +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 1 + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 28 +++++++++++++++++++ + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 1 + 3 files changed, 30 insertions(+) + +--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h ++++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +@@ -168,6 +168,7 @@ struct smu_temperature_range { + int mem_crit_max; + int mem_emergency_max; + int software_shutdown_temp; ++ int software_shutdown_temp_offset; + }; + + struct smu_state_validation_block { +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +@@ -1381,6 +1381,7 @@ static int smu_v13_0_irq_process(struct + */ + uint32_t ctxid = entry->src_data[0]; + uint32_t data; ++ uint32_t high; + + if (client_id == SOC15_IH_CLIENTID_THM) { + switch (src_id) { +@@ -1437,6 +1438,33 @@ static int smu_v13_0_irq_process(struct + schedule_work(&smu->throttling_logging_work); + + break; ++ case 0x8: ++ high = smu->thermal_range.software_shutdown_temp + ++ smu->thermal_range.software_shutdown_temp_offset; ++ high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP, high); ++ dev_emerg(adev->dev, "Reduce soft CTF limit to %d (by an offset %d)\n", ++ high, ++ smu->thermal_range.software_shutdown_temp_offset); ++ ++ data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL); ++ data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL, ++ DIG_THERM_INTH, ++ (high & 0xff)); ++ data = data & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); ++ WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, data); ++ break; ++ case 0x9: ++ high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP, ++ smu->thermal_range.software_shutdown_temp); ++ dev_emerg(adev->dev, "Recover soft CTF limit to %d\n", high); ++ ++ data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL); ++ data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL, ++ DIG_THERM_INTH, ++ (high & 0xff)); ++ data = data & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); ++ WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, data); ++ break; + } + } + } +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +@@ -1288,6 +1288,7 @@ static int smu_v13_0_7_get_thermal_tempe + range->mem_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)* + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + range->software_shutdown_temp = powerplay_table->software_shutdown_temp; ++ range->software_shutdown_temp_offset = pptable->SkuTable.FanAbnormalTempLimitOffset; + + return 0; + } diff --git a/queue-6.1/drm-amdgpu-fix-minmax-warning.patch b/queue-6.1/drm-amdgpu-fix-minmax-warning.patch new file mode 100644 index 00000000000..07faa1d289b --- /dev/null +++ b/queue-6.1/drm-amdgpu-fix-minmax-warning.patch @@ -0,0 +1,46 @@ +From abd51738fe754a684ec44b7a9eca1981e1704ad9 Mon Sep 17 00:00:00 2001 +From: Luben Tuikov +Date: Mon, 21 Nov 2022 12:18:36 -0500 +Subject: drm/amdgpu: Fix minmax warning + +From: Luben Tuikov + +commit abd51738fe754a684ec44b7a9eca1981e1704ad9 upstream. + +Fix minmax warning by using min_t() macro and explicitly specifying +the assignment type. + +Cc: Alex Deucher +Signed-off-by: Luben Tuikov +Reviewed-by: Alex Deucher +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 9 ++++++--- + 1 file changed, 6 insertions(+), 3 deletions(-) + +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +@@ -1441,7 +1441,9 @@ static int smu_v13_0_irq_process(struct + case 0x8: + high = smu->thermal_range.software_shutdown_temp + + smu->thermal_range.software_shutdown_temp_offset; +- high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP, high); ++ high = min_t(typeof(high), ++ SMU_THERMAL_MAXIMUM_ALERT_TEMP, ++ high); + dev_emerg(adev->dev, "Reduce soft CTF limit to %d (by an offset %d)\n", + high, + smu->thermal_range.software_shutdown_temp_offset); +@@ -1454,8 +1456,9 @@ static int smu_v13_0_irq_process(struct + WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, data); + break; + case 0x9: +- high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP, +- smu->thermal_range.software_shutdown_temp); ++ high = min_t(typeof(high), ++ SMU_THERMAL_MAXIMUM_ALERT_TEMP, ++ smu->thermal_range.software_shutdown_temp); + dev_emerg(adev->dev, "Recover soft CTF limit to %d\n", high); + + data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL); diff --git a/queue-6.1/drm-amdgpu-sdma4-set-align-mask-to-255.patch b/queue-6.1/drm-amdgpu-sdma4-set-align-mask-to-255.patch new file mode 100644 index 00000000000..f9d6b2e5c95 --- /dev/null +++ b/queue-6.1/drm-amdgpu-sdma4-set-align-mask-to-255.patch @@ -0,0 +1,49 @@ +From e5df16d9428f5c6d2d0b1eff244d6c330ba9ef3a Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Wed, 7 Jun 2023 12:14:00 -0400 +Subject: drm/amdgpu/sdma4: set align mask to 255 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Alex Deucher + +commit e5df16d9428f5c6d2d0b1eff244d6c330ba9ef3a upstream. + +The wptr needs to be incremented at at least 64 dword intervals, +use 256 to align with windows. This should fix potential hangs +with unaligned updates. + +Reviewed-by: Felix Kuehling +Reviewed-by: Aaron Liu +Reviewed-by: Christian König +Signed-off-by: Alex Deucher +(cherry picked from commit e5df16d9428f5c6d2d0b1eff244d6c330ba9ef3a) +The path `drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c` doesn't exist in +6.1.y, only modify the file that does exist. +Signed-off-by: Mario Limonciello +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +@@ -2330,7 +2330,7 @@ const struct amd_ip_funcs sdma_v4_0_ip_f + + static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { + .type = AMDGPU_RING_TYPE_SDMA, +- .align_mask = 0xf, ++ .align_mask = 0xff, + .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), + .support_64bit_ptrs = true, + .secure_submission_supported = true, +@@ -2400,7 +2400,7 @@ static const struct amdgpu_ring_funcs sd + + static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = { + .type = AMDGPU_RING_TYPE_SDMA, +- .align_mask = 0xf, ++ .align_mask = 0xff, + .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), + .support_64bit_ptrs = true, + .secure_submission_supported = true, diff --git a/queue-6.1/f2fs-fix-deadlock-in-i_xattr_sem-and-inode-page-lock.patch b/queue-6.1/f2fs-fix-deadlock-in-i_xattr_sem-and-inode-page-lock.patch new file mode 100644 index 00000000000..bdefd3b75da --- /dev/null +++ b/queue-6.1/f2fs-fix-deadlock-in-i_xattr_sem-and-inode-page-lock.patch @@ -0,0 +1,89 @@ +From 5eda1ad1aaffdfebdecf7a164e586060a210f74f Mon Sep 17 00:00:00 2001 +From: Jaegeuk Kim +Date: Wed, 28 Jun 2023 01:00:56 -0700 +Subject: f2fs: fix deadlock in i_xattr_sem and inode page lock + +From: Jaegeuk Kim + +commit 5eda1ad1aaffdfebdecf7a164e586060a210f74f upstream. + +Thread #1: + +[122554.641906][ T92] f2fs_getxattr+0xd4/0x5fc + -> waiting for f2fs_down_read(&F2FS_I(inode)->i_xattr_sem); + +[122554.641927][ T92] __f2fs_get_acl+0x50/0x284 +[122554.641948][ T92] f2fs_init_acl+0x84/0x54c +[122554.641969][ T92] f2fs_init_inode_metadata+0x460/0x5f0 +[122554.641990][ T92] f2fs_add_inline_entry+0x11c/0x350 + -> Locked dir->inode_page by f2fs_get_node_page() + +[122554.642009][ T92] f2fs_do_add_link+0x100/0x1e4 +[122554.642025][ T92] f2fs_create+0xf4/0x22c +[122554.642047][ T92] vfs_create+0x130/0x1f4 + +Thread #2: + +[123996.386358][ T92] __get_node_page+0x8c/0x504 + -> waiting for dir->inode_page lock + +[123996.386383][ T92] read_all_xattrs+0x11c/0x1f4 +[123996.386405][ T92] __f2fs_setxattr+0xcc/0x528 +[123996.386424][ T92] f2fs_setxattr+0x158/0x1f4 + -> f2fs_down_write(&F2FS_I(inode)->i_xattr_sem); + +[123996.386443][ T92] __f2fs_set_acl+0x328/0x430 +[123996.386618][ T92] f2fs_set_acl+0x38/0x50 +[123996.386642][ T92] posix_acl_chmod+0xc8/0x1c8 +[123996.386669][ T92] f2fs_setattr+0x5e0/0x6bc +[123996.386689][ T92] notify_change+0x4d8/0x580 +[123996.386717][ T92] chmod_common+0xd8/0x184 +[123996.386748][ T92] do_fchmodat+0x60/0x124 +[123996.386766][ T92] __arm64_sys_fchmodat+0x28/0x3c + +Cc: +Fixes: 27161f13e3c3 "f2fs: avoid race in between read xattr & write xattr" +Reviewed-by: Chao Yu +Signed-off-by: Jaegeuk Kim +Signed-off-by: Greg Kroah-Hartman +--- + fs/f2fs/dir.c | 9 ++++++++- + fs/f2fs/xattr.c | 6 ++++-- + 2 files changed, 12 insertions(+), 3 deletions(-) + +--- a/fs/f2fs/dir.c ++++ b/fs/f2fs/dir.c +@@ -806,8 +806,15 @@ int f2fs_add_dentry(struct inode *dir, c + { + int err = -EAGAIN; + +- if (f2fs_has_inline_dentry(dir)) ++ if (f2fs_has_inline_dentry(dir)) { ++ /* ++ * Should get i_xattr_sem to keep the lock order: ++ * i_xattr_sem -> inode_page lock used by f2fs_setxattr. ++ */ ++ f2fs_down_read(&F2FS_I(dir)->i_xattr_sem); + err = f2fs_add_inline_entry(dir, fname, inode, ino, mode); ++ f2fs_up_read(&F2FS_I(dir)->i_xattr_sem); ++ } + if (err == -EAGAIN) + err = f2fs_add_regular_entry(dir, fname, inode, ino, mode); + +--- a/fs/f2fs/xattr.c ++++ b/fs/f2fs/xattr.c +@@ -527,10 +527,12 @@ int f2fs_getxattr(struct inode *inode, i + if (len > F2FS_NAME_LEN) + return -ERANGE; + +- f2fs_down_read(&F2FS_I(inode)->i_xattr_sem); ++ if (!ipage) ++ f2fs_down_read(&F2FS_I(inode)->i_xattr_sem); + error = lookup_all_xattrs(inode, ipage, index, len, name, + &entry, &base_addr, &base_size, &is_inline); +- f2fs_up_read(&F2FS_I(inode)->i_xattr_sem); ++ if (!ipage) ++ f2fs_up_read(&F2FS_I(inode)->i_xattr_sem); + if (error) + return error; + diff --git a/queue-6.1/f2fs-fix-the-wrong-condition-to-determine-atomic-context.patch b/queue-6.1/f2fs-fix-the-wrong-condition-to-determine-atomic-context.patch new file mode 100644 index 00000000000..e6f185e4ebb --- /dev/null +++ b/queue-6.1/f2fs-fix-the-wrong-condition-to-determine-atomic-context.patch @@ -0,0 +1,31 @@ +From 633c8b9409f564ce4b7f7944c595ffac27ed1ff4 Mon Sep 17 00:00:00 2001 +From: Jaegeuk Kim +Date: Fri, 5 May 2023 12:16:54 -0700 +Subject: f2fs: fix the wrong condition to determine atomic context + +From: Jaegeuk Kim + +commit 633c8b9409f564ce4b7f7944c595ffac27ed1ff4 upstream. + +Should use !in_task for irq context. + +Cc: stable@vger.kernel.org +Fixes: 1aa161e43106 ("f2fs: fix scheduling while atomic in decompression path") +Reviewed-by: Chao Yu +Signed-off-by: Jaegeuk Kim +Signed-off-by: Greg Kroah-Hartman +--- + fs/f2fs/compress.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/fs/f2fs/compress.c ++++ b/fs/f2fs/compress.c +@@ -764,7 +764,7 @@ void f2fs_decompress_cluster(struct deco + ret = -EFSCORRUPTED; + + /* Avoid f2fs_commit_super in irq context */ +- if (in_task) ++ if (!in_task) + f2fs_save_errors(sbi, ERROR_FAIL_DECOMPRESSION); + else + f2fs_handle_error(sbi, ERROR_FAIL_DECOMPRESSION); diff --git a/queue-6.1/pinctrl-amd-add-z-state-wake-control-bits.patch b/queue-6.1/pinctrl-amd-add-z-state-wake-control-bits.patch new file mode 100644 index 00000000000..27d5721461e --- /dev/null +++ b/queue-6.1/pinctrl-amd-add-z-state-wake-control-bits.patch @@ -0,0 +1,57 @@ +From df72b4a692b60d3e5d99d9ef662b2d03c44bb9c0 Mon Sep 17 00:00:00 2001 +From: Basavaraj Natikar +Date: Thu, 8 Dec 2022 15:07:04 +0530 +Subject: pinctrl: amd: Add Z-state wake control bits + +From: Basavaraj Natikar + +commit df72b4a692b60d3e5d99d9ef662b2d03c44bb9c0 upstream. + +GPIO registers include Bit 27 for WakeCntrlZ used to enable wake in +Z state. Hence add Z-state wake control bits to debugfs output to +debug and analyze Z-states problems. + +Signed-off-by: Basavaraj Natikar +Suggested-by: Mario Limonciello +Tested-by: Guruvendra Punugupati +Link: https://lore.kernel.org/r/20221208093704.1151928-1-Basavaraj.Natikar@amd.com +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pinctrl/pinctrl-amd.c | 7 +++++++ + drivers/pinctrl/pinctrl-amd.h | 1 + + 2 files changed, 8 insertions(+) + +--- a/drivers/pinctrl/pinctrl-amd.c ++++ b/drivers/pinctrl/pinctrl-amd.c +@@ -218,6 +218,7 @@ static void amd_gpio_dbg_show(struct seq + char *orientation; + char debounce_value[40]; + char *debounce_enable; ++ char *wake_cntrlz; + + for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { + unsigned int time = 0; +@@ -305,6 +306,12 @@ static void amd_gpio_dbg_show(struct seq + wake_cntrl2 = " ∅"; + seq_printf(s, "S4/S5 %s| ", wake_cntrl2); + ++ if (pin_reg & BIT(WAKECNTRL_Z_OFF)) ++ wake_cntrlz = "⏰"; ++ else ++ wake_cntrlz = " ∅"; ++ seq_printf(s, "Z %s| ", wake_cntrlz); ++ + if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { + pull_up_enable = "+"; + if (pin_reg & BIT(PULL_UP_SEL_OFF)) +--- a/drivers/pinctrl/pinctrl-amd.h ++++ b/drivers/pinctrl/pinctrl-amd.h +@@ -42,6 +42,7 @@ + #define OUTPUT_ENABLE_OFF 23 + #define SW_CNTRL_IN_OFF 24 + #define SW_CNTRL_EN_OFF 25 ++#define WAKECNTRL_Z_OFF 27 + #define INTERRUPT_STS_OFF 28 + #define WAKE_STS_OFF 29 + diff --git a/queue-6.1/series b/queue-6.1/series index 3a77e048e85..cb4d4d84e15 100644 --- a/queue-6.1/series +++ b/queue-6.1/series @@ -67,3 +67,11 @@ ovl-let-helper-ovl_i_path_real-return-the-realinode.patch ovl-fix-null-pointer-dereference-in-ovl_get_acl_rcu.patch cifs-fix-session-state-check-in-smb2_find_smb_ses.patch drm-client-send-hotplug-event-after-registering-a-client.patch +drm-amdgpu-sdma4-set-align-mask-to-255.patch +drm-amd-pm-revise-the-aspm-settings-for-thunderbolt-attached-scenario.patch +drm-amdgpu-add-the-fan-abnormal-detection-feature.patch +drm-amdgpu-fix-minmax-warning.patch +drm-amd-pm-add-abnormal-fan-detection-for-smu-13.0.0.patch +f2fs-fix-the-wrong-condition-to-determine-atomic-context.patch +f2fs-fix-deadlock-in-i_xattr_sem-and-inode-page-lock.patch +pinctrl-amd-add-z-state-wake-control-bits.patch -- 2.47.3