From 40ded2d12b5d999866c2bc4122683355bb17c831 Mon Sep 17 00:00:00 2001 From: Jan Remmet Date: Wed, 10 Sep 2025 08:17:39 +0200 Subject: [PATCH] arm64: dts: imx8mm-phycore-som: optimize drive strengh Reduce ENET pin drive strength from X6 to X4 to optimize signal quality and reduce potential signal integrity issues. Signed-off-by: Jan Remmet Reviewed-by: Teresa Remmet Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi index 672baba4c8d05..921a7f58fd41d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi @@ -340,10 +340,10 @@ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16 - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16 + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x12 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x12 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x12 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x12 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x10 >; }; -- 2.47.3