From 4686f263f68af93b5f3db4eac939c73d85f11192 Mon Sep 17 00:00:00 2001 From: Vipul Kumar Date: Wed, 9 May 2018 19:10:31 +0530 Subject: [PATCH] cmd: zynqrsa: Added support to load non-encrypted bitstream zynqrsa programs the PL when a partition includes an authenticated and encrypted bitstream. However, if the partition is only authenticated there is no PL programming operation because there was no support to load only authenticated bitstream. This patch added support to load only authenticated bitstream. Signed-off-by: Vipul Kumar Signed-off-by: Michal Simek --- cmd/zynq_rsa.c | 5 +++-- drivers/fpga/zynqpl.c | 20 ++++++++++++-------- include/zynqpl.h | 2 +- 3 files changed, 16 insertions(+), 11 deletions(-) diff --git a/cmd/zynq_rsa.c b/cmd/zynq_rsa.c index 2b89cce4d89..e0df5a2338f 100644 --- a/cmd/zynq_rsa.c +++ b/cmd/zynq_rsa.c @@ -548,7 +548,7 @@ static int do_zynq_verify_image(cmd_tbl_t *cmdtp, int flag, int argc, debug("Authentication Done\r\n"); } - if (encrypt_part_flag) { + if (encrypt_part_flag || signed_part_flag) { debug("DECRYPTION \r\n"); part_dst_addr = part_load_addr; @@ -568,7 +568,8 @@ static int do_zynq_verify_image(cmd_tbl_t *cmdtp, int flag, int argc, part_img_len, part_dst_addr, part_data_len, - bstype); + bstype, + encrypt_part_flag); if (status != 0) { printf("DECRYPTION_FAIL\r\n"); return -1; diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index e9e23065491..a4a6fd0a82d 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -507,7 +507,7 @@ struct xilinx_fpga_op zynq_op = { * place it back the decrypted image into dstaddr. */ int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen, - u8 bstype) + u8 bstype, bool encrypt_part_flag) { u32 isr_status, ts; @@ -517,10 +517,13 @@ int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen, return FPGA_FAIL; } - /* Check AES engine is enabled */ - if (!(readl(&devcfg_base->ctrl) & DEVCFG_CTRL_PCFG_AES_EN_MASK)) { - printf("%s: AES engine is not enabled\n", __func__); - return FPGA_FAIL; + if (encrypt_part_flag) { + /* Check AES engine is enabled */ + if (!(readl(&devcfg_base->ctrl) & + DEVCFG_CTRL_PCFG_AES_EN_MASK)) { + printf("%s: AES engine is not enabled\n", __func__); + return FPGA_FAIL; + } } if (zynq_dma_xfer_init(bstype)) { @@ -528,8 +531,9 @@ int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen, return FPGA_FAIL; } - writel((readl(&devcfg_base->ctrl) | DEVCFG_CTRL_PCAP_RATE_EN_MASK), - &devcfg_base->ctrl); + if (encrypt_part_flag) + writel((readl(&devcfg_base->ctrl) | + DEVCFG_CTRL_PCAP_RATE_EN_MASK), &devcfg_base->ctrl); debug("%s: Source = 0x%08X\n", __func__, (u32)srcaddr); debug("%s: Size = %zu\n", __func__, srclen); @@ -633,7 +637,7 @@ static int do_zynq_decrypt_image(cmd_tbl_t *cmdtp, int flag, int argc, dstlen = roundup(dstlen, 4); status = zynq_decrypt_load(srcaddr, srclen >> 2, dstaddr, dstlen >> 2, - imgtype); + imgtype, true); if (status != 0) return -1; diff --git a/include/zynqpl.h b/include/zynqpl.h index c9d9f0ff2f2..2b704552be3 100644 --- a/include/zynqpl.h +++ b/include/zynqpl.h @@ -14,7 +14,7 @@ #ifdef CONFIG_CMD_ZYNQ_AES extern int zynq_decrypt_load(u32 srcaddr, u32 dstaddr, u32 srclen, u32 dstlen, - u8 bstype); + u8 bstype, bool encrypt_part_flag); #endif #if defined(CONFIG_FPGA_ZYNQPL) extern struct xilinx_fpga_op zynq_op; -- 2.47.3