From 47f3a30d83a6862a795b9bd35ec84b5c7c94beac Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Wed, 23 Apr 2014 09:49:01 +0200
Subject: [PATCH] ARM: ultrascale: Enable GEM

ARM64 doesn't support MMU regions with DCACHE off.
Qemu doesn't support caches.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
 .../include/asm/arch-ultrascale/hardware.h    |  5 ++++
 .../include/asm/arch-ultrascale/sys_proto.h   | 17 ++++++++++++
 board/xilinx/ultrascale/ultrascale.c          | 26 +++++++++++++++++++
 drivers/net/zynq_gem.c                        |  4 +++
 4 files changed, 52 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-ultrascale/sys_proto.h

diff --git a/arch/arm/include/asm/arch-ultrascale/hardware.h b/arch/arm/include/asm/arch-ultrascale/hardware.h
index 7893e86e9fc..5ebf8b87ba4 100644
--- a/arch/arm/include/asm/arch-ultrascale/hardware.h
+++ b/arch/arm/include/asm/arch-ultrascale/hardware.h
@@ -15,4 +15,9 @@
 #define ZYNQ_SERIAL_BASEADDR0	0xFF000000
 #define ZYNQ_SERIAL_BASEADDR1	0xFF001000
 
+#define ZYNQ_GEM_BASEADDR0	0xFF009000
+#define ZYNQ_GEM_BASEADDR1	0xFF00A000
+#define ZYNQ_GEM_BASEADDR2	0xFF00B000
+#define ZYNQ_GEM_BASEADDR3	0xFF00C000
+
 #endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-ultrascale/sys_proto.h b/arch/arm/include/asm/arch-ultrascale/sys_proto.h
new file mode 100644
index 00000000000..534eec2c027
--- /dev/null
+++ b/arch/arm/include/asm/arch-ultrascale/sys_proto.h
@@ -0,0 +1,17 @@
+/*
+ * (C) Copyright 2014 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_SYS_PROTO_H
+#define _ASM_ARCH_SYS_PROTO_H
+
+/* Setup clk for network */
+static inline void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
+{
+}
+
+
+#endif /* _ASM_ARCH_SYS_PROTO_H */
diff --git a/board/xilinx/ultrascale/ultrascale.c b/board/xilinx/ultrascale/ultrascale.c
index e1264efd819..b759b59bd7a 100644
--- a/board/xilinx/ultrascale/ultrascale.c
+++ b/board/xilinx/ultrascale/ultrascale.c
@@ -6,6 +6,7 @@
  */
 
 #include <common.h>
+#include <netdev.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -29,3 +30,28 @@ int timer_init(void)
 void reset_cpu(ulong addr)
 {
 }
+
+int board_eth_init(bd_t *bis)
+{
+	u32 ret = 0;
+
+#if defined(CONFIG_ZYNQ_GEM)
+# if defined(CONFIG_ZYNQ_GEM0)
+	ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
+						CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
+# endif
+# if defined(CONFIG_ZYNQ_GEM1)
+	ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
+						CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
+# endif
+# if defined(CONFIG_ZYNQ_GEM2)
+	ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR2,
+						CONFIG_ZYNQ_GEM_PHY_ADDR2, 0);
+# endif
+# if defined(CONFIG_ZYNQ_GEM3)
+	ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR3,
+						CONFIG_ZYNQ_GEM_PHY_ADDR3, 0);
+# endif
+#endif
+	return ret;
+}
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 480888cf659..bdfeafe3fdd 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -510,8 +510,12 @@ int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
 	memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
 
 	/* Align bd_space to 1MB */
+#ifdef __XILINX_ULTRASCALE_H
+	bd_space = memalign(1 << 20, BD_SPACE);
+#else
 	bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
 	mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE, DCACHE_OFF);
+#endif
 
 	/* Initialize the bd spaces for tx and rx bd's */
 	priv->tx_bd = (struct emac_bd *)bd_space;
-- 
2.47.3