From 4b58bbcfbecf0c7ebd2fd3a9a4322d562e484925 Mon Sep 17 00:00:00 2001 From: Sasha Levin Date: Sun, 11 Aug 2024 21:09:17 -0400 Subject: [PATCH] Fixes for 4.19 Signed-off-by: Sasha Levin --- queue-4.19/arm64-add-neoverse-v2-part.patch | 45 ++++ ...t-for-sb-barrier-and-patch-in-over-d.patch | 186 ++++++++++++++ ...-force-hwcap-to-be-based-on-the-sysr.patch | 101 ++++++++ ...-cputype-add-cortex-a720-definitions.patch | 52 ++++ ...-cputype-add-cortex-a725-definitions.patch | 54 ++++ ...4-cputype-add-cortex-x1c-definitions.patch | 54 ++++ ...64-cputype-add-cortex-x3-definitions.patch | 52 ++++ ...64-cputype-add-cortex-x4-definitions.patch | 53 ++++ ...-cputype-add-cortex-x925-definitions.patch | 52 ++++ ...-cputype-add-neoverse-v3-definitions.patch | 53 ++++ ...-workaround-for-arm-errata-3194386-a.patch | 213 ++++++++++++++++ ...and-speculative-ssbs-workaround-agai.patch | 195 ++++++++++++++ ...a-expand-speculative-ssbs-workaround.patch | 153 +++++++++++ ...-unify-speculative-ssbs-errata-logic.patch | 136 ++++++++++ ...e-unused-declaring-of-bpf_kprobe_ove.patch | 39 +++ ...ong-unit-use-in-ext4_mb_find_by_goal.patch | 39 +++ ...us-don-t-filter-out-duplicate-alerts.patch | 60 +++++ ...bus-improve-handling-of-stuck-alerts.patch | 123 +++++++++ ...lert-notifications-to-all-devices-if.patch | 106 ++++++++ queue-4.19/series | 26 ++ .../spi-fsl-lpspi-remove-unneeded-array.patch | 55 ++++ ...i-add-i.mx8-boards-support-for-lpspi.patch | 132 ++++++++++ .../spi-lpspi-add-slave-mode-support.patch | 230 +++++++++++++++++ ...e-error-info-of-transfer-speed-setti.patch | 74 ++++++ ...termark-change-with-send-data-length.patch | 66 +++++ ...i-replace-all-master-with-controller.patch | 241 ++++++++++++++++++ ...spi-fsl-lpspi-fix-scldiv-calculation.patch | 57 +++++ 27 files changed, 2647 insertions(+) create mode 100644 queue-4.19/arm64-add-neoverse-v2-part.patch create mode 100644 queue-4.19/arm64-add-support-for-sb-barrier-and-patch-in-over-d.patch create mode 100644 queue-4.19/arm64-cpufeature-force-hwcap-to-be-based-on-the-sysr.patch create mode 100644 queue-4.19/arm64-cputype-add-cortex-a720-definitions.patch create mode 100644 queue-4.19/arm64-cputype-add-cortex-a725-definitions.patch create mode 100644 queue-4.19/arm64-cputype-add-cortex-x1c-definitions.patch create mode 100644 queue-4.19/arm64-cputype-add-cortex-x3-definitions.patch create mode 100644 queue-4.19/arm64-cputype-add-cortex-x4-definitions.patch create mode 100644 queue-4.19/arm64-cputype-add-cortex-x925-definitions.patch create mode 100644 queue-4.19/arm64-cputype-add-neoverse-v3-definitions.patch create mode 100644 queue-4.19/arm64-errata-add-workaround-for-arm-errata-3194386-a.patch create mode 100644 queue-4.19/arm64-errata-expand-speculative-ssbs-workaround-agai.patch create mode 100644 queue-4.19/arm64-errata-expand-speculative-ssbs-workaround.patch create mode 100644 queue-4.19/arm64-errata-unify-speculative-ssbs-errata-logic.patch create mode 100644 queue-4.19/bpf-kprobe-remove-unused-declaring-of-bpf_kprobe_ove.patch create mode 100644 queue-4.19/ext4-fix-wrong-unit-use-in-ext4_mb_find_by_goal.patch create mode 100644 queue-4.19/i2c-smbus-don-t-filter-out-duplicate-alerts.patch create mode 100644 queue-4.19/i2c-smbus-improve-handling-of-stuck-alerts.patch create mode 100644 queue-4.19/i2c-smbus-send-alert-notifications-to-all-devices-if.patch create mode 100644 queue-4.19/spi-fsl-lpspi-remove-unneeded-array.patch create mode 100644 queue-4.19/spi-lpspi-add-i.mx8-boards-support-for-lpspi.patch create mode 100644 queue-4.19/spi-lpspi-add-slave-mode-support.patch create mode 100644 queue-4.19/spi-lpspi-add-the-error-info-of-transfer-speed-setti.patch create mode 100644 queue-4.19/spi-lpspi-let-watermark-change-with-send-data-length.patch create mode 100644 queue-4.19/spi-lpspi-replace-all-master-with-controller.patch create mode 100644 queue-4.19/spi-spi-fsl-lpspi-fix-scldiv-calculation.patch diff --git a/queue-4.19/arm64-add-neoverse-v2-part.patch b/queue-4.19/arm64-add-neoverse-v2-part.patch new file mode 100644 index 00000000000..38215fd21c3 --- /dev/null +++ b/queue-4.19/arm64-add-neoverse-v2-part.patch @@ -0,0 +1,45 @@ +From 73915c37b9d233a1b69e8edb9e0f53efe89d0ba8 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:43:45 +0100 +Subject: arm64: Add Neoverse-V2 part + +From: Besar Wicaksono + +[ Upstream commit f4d9d9dcc70b96b5e5d7801bd5fbf8491b07b13d ] + +Add the part number and MIDR for Neoverse-V2 + +Signed-off-by: Besar Wicaksono +Reviewed-by: James Clark +Link: https://lore.kernel.org/r/20240109192310.16234-2-bwicaksono@nvidia.com +Signed-off-by: Will Deacon +[ Mark: trivial backport ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index 50368f9622139..0e4c0675f7461 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -89,6 +89,7 @@ + #define ARM_CPU_PART_CORTEX_X2 0xD48 + #define ARM_CPU_PART_NEOVERSE_N2 0xD49 + #define ARM_CPU_PART_CORTEX_A78C 0xD4B ++#define ARM_CPU_PART_NEOVERSE_V2 0xD4F + + #define APM_CPU_PART_POTENZA 0x000 + +@@ -125,6 +126,7 @@ + #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) + #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) + #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) ++#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) + #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) + #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) + #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) +-- +2.43.0 + diff --git a/queue-4.19/arm64-add-support-for-sb-barrier-and-patch-in-over-d.patch b/queue-4.19/arm64-add-support-for-sb-barrier-and-patch-in-over-d.patch new file mode 100644 index 00000000000..d1d569ca93d --- /dev/null +++ b/queue-4.19/arm64-add-support-for-sb-barrier-and-patch-in-over-d.patch @@ -0,0 +1,186 @@ +From 567c3d2a998036a09a05c96310527a5983ed2f38 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:43:43 +0100 +Subject: arm64: Add support for SB barrier and patch in over DSB; ISB + sequences + +From: Will Deacon + +[ Upstream commit bd4fb6d270bc423a9a4098108784f7f9254c4e6d ] + +We currently use a DSB; ISB sequence to inhibit speculation in set_fs(). +Whilst this works for current CPUs, future CPUs may implement a new SB +barrier instruction which acts as an architected speculation barrier. + +On CPUs that support it, patch in an SB; NOP sequence over the DSB; ISB +sequence and advertise the presence of the new instruction to userspace. + +Signed-off-by: Will Deacon +[ Mark: fixup conflicts ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/assembler.h | 13 +++++++++++++ + arch/arm64/include/asm/barrier.h | 4 ++++ + arch/arm64/include/asm/cpucaps.h | 3 ++- + arch/arm64/include/asm/sysreg.h | 6 ++++++ + arch/arm64/include/asm/uaccess.h | 3 +-- + arch/arm64/include/uapi/asm/hwcap.h | 1 + + arch/arm64/kernel/cpufeature.c | 12 ++++++++++++ + arch/arm64/kernel/cpuinfo.c | 1 + + 8 files changed, 40 insertions(+), 3 deletions(-) + +diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h +index fc3d26c954a40..efabe6c476aa0 100644 +--- a/arch/arm64/include/asm/assembler.h ++++ b/arch/arm64/include/asm/assembler.h +@@ -133,6 +133,19 @@ + hint #22 + .endm + ++/* ++ * Speculation barrier ++ */ ++ .macro sb ++alternative_if_not ARM64_HAS_SB ++ dsb nsh ++ isb ++alternative_else ++ SB_BARRIER_INSN ++ nop ++alternative_endif ++ .endm ++ + /* + * Sanitise a 64-bit bounded index wrt speculation, returning zero if out + * of bounds. +diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h +index 822a9192c5511..f66bb04fdf2dd 100644 +--- a/arch/arm64/include/asm/barrier.h ++++ b/arch/arm64/include/asm/barrier.h +@@ -34,6 +34,10 @@ + #define psb_csync() asm volatile("hint #17" : : : "memory") + #define csdb() asm volatile("hint #20" : : : "memory") + ++#define spec_bar() asm volatile(ALTERNATIVE("dsb nsh\nisb\n", \ ++ SB_BARRIER_INSN"nop\n", \ ++ ARM64_HAS_SB)) ++ + #define mb() dsb(sy) + #define rmb() dsb(ld) + #define wmb() dsb(st) +diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h +index 61fd28522d74f..a7e2378df3d1c 100644 +--- a/arch/arm64/include/asm/cpucaps.h ++++ b/arch/arm64/include/asm/cpucaps.h +@@ -56,7 +56,8 @@ + #define ARM64_WORKAROUND_1542419 35 + #define ARM64_SPECTRE_BHB 36 + #define ARM64_WORKAROUND_1742098 37 ++#define ARM64_HAS_SB 38 + +-#define ARM64_NCAPS 38 ++#define ARM64_NCAPS 39 + + #endif /* __ASM_CPUCAPS_H */ +diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h +index 0a8342de5796a..8f015c20f3e0e 100644 +--- a/arch/arm64/include/asm/sysreg.h ++++ b/arch/arm64/include/asm/sysreg.h +@@ -97,6 +97,11 @@ + #define SET_PSTATE_SSBS(x) __emit_inst(0xd5000000 | REG_PSTATE_SSBS_IMM | \ + (!!x)<<8 | 0x1f) + ++#define __SYS_BARRIER_INSN(CRm, op2, Rt) \ ++ __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f)) ++ ++#define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31) ++ + #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2) + #define SYS_DC_IGSW sys_insn(1, 0, 7, 6, 4) + #define SYS_DC_IGDSW sys_insn(1, 0, 7, 6, 6) +@@ -528,6 +533,7 @@ + #define ID_AA64ISAR0_AES_SHIFT 4 + + /* id_aa64isar1 */ ++#define ID_AA64ISAR1_SB_SHIFT 36 + #define ID_AA64ISAR1_LRCPC_SHIFT 20 + #define ID_AA64ISAR1_FCMA_SHIFT 16 + #define ID_AA64ISAR1_JSCVT_SHIFT 12 +diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h +index e66b0fca99c2f..3c3bf4171f3b6 100644 +--- a/arch/arm64/include/asm/uaccess.h ++++ b/arch/arm64/include/asm/uaccess.h +@@ -46,8 +46,7 @@ static inline void set_fs(mm_segment_t fs) + * Prevent a mispredicted conditional call to set_fs from forwarding + * the wrong address limit to access_ok under speculation. + */ +- dsb(nsh); +- isb(); ++ spec_bar(); + + /* On user-mode return, check fs is correct */ + set_thread_flag(TIF_FSCHECK); +diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h +index 2bcd6e4f34740..7784f7cba16cf 100644 +--- a/arch/arm64/include/uapi/asm/hwcap.h ++++ b/arch/arm64/include/uapi/asm/hwcap.h +@@ -49,5 +49,6 @@ + #define HWCAP_ILRCPC (1 << 26) + #define HWCAP_FLAGM (1 << 27) + #define HWCAP_SSBS (1 << 28) ++#define HWCAP_SB (1 << 29) + + #endif /* _UAPI__ASM_HWCAP_H */ +diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c +index d7e73a7963d1b..3f6a2187d0911 100644 +--- a/arch/arm64/kernel/cpufeature.c ++++ b/arch/arm64/kernel/cpufeature.c +@@ -144,6 +144,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { + }; + + static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { ++ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0), +@@ -1361,6 +1362,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = { + .cpu_enable = cpu_enable_ssbs, + }, + #endif ++ { ++ .desc = "Speculation barrier (SB)", ++ .capability = ARM64_HAS_SB, ++ .type = ARM64_CPUCAP_SYSTEM_FEATURE, ++ .matches = has_cpuid_feature, ++ .sys_reg = SYS_ID_AA64ISAR1_EL1, ++ .field_pos = ID_AA64ISAR1_SB_SHIFT, ++ .sign = FTR_UNSIGNED, ++ .min_field_value = 1, ++ }, + {}, + }; + +@@ -1415,6 +1426,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { + HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA), + HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC), + HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ILRCPC), ++ HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SB), + HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_USCAT), + #ifdef CONFIG_ARM64_SVE + HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, HWCAP_SVE), +diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c +index 36bd58d8ca11f..9d013e7106a99 100644 +--- a/arch/arm64/kernel/cpuinfo.c ++++ b/arch/arm64/kernel/cpuinfo.c +@@ -82,6 +82,7 @@ static const char *const hwcap_str[] = { + "ilrcpc", + "flagm", + "ssbs", ++ "sb", + NULL + }; + +-- +2.43.0 + diff --git a/queue-4.19/arm64-cpufeature-force-hwcap-to-be-based-on-the-sysr.patch b/queue-4.19/arm64-cpufeature-force-hwcap-to-be-based-on-the-sysr.patch new file mode 100644 index 00000000000..c125be665a9 --- /dev/null +++ b/queue-4.19/arm64-cpufeature-force-hwcap-to-be-based-on-the-sysr.patch @@ -0,0 +1,101 @@ +From 1a11a0d0c9dbdc78d08f8a8a92979220ff81e6a2 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:43:44 +0100 +Subject: arm64: cpufeature: Force HWCAP to be based on the sysreg visible to + user-space + +From: James Morse + +[ Upstream commit 237405ebef580a7352a52129b2465c117145eafa ] + +arm64 advertises hardware features to user-space via HWCAPs, and by +emulating access to the CPUs id registers. The cpufeature code has a +sanitised system-wide view of an id register, and a sanitised user-space +view of an id register, where some features use their 'safe' value +instead of the hardware value. + +It is currently possible for a HWCAP to be advertised where the user-space +view of the id register does not show the feature as supported. +Erratum workaround need to remove both the HWCAP, and the feature from +the user-space view of the id register. This involves duplicating the +code, and spreading it over cpufeature.c and cpu_errata.c. + +Make the HWCAP code use the user-space view of id registers. This ensures +the values never diverge, and allows erratum workaround to remove HWCAP +by modifying the user-space view of the id register. + +Signed-off-by: James Morse +Reviewed-by: Suzuki K Poulose +Link: https://lore.kernel.org/r/20220909165938.3931307-2-james.morse@arm.com +Signed-off-by: Catalin Marinas +[ Mark: fixup lack of 'width' parameter, whitespace conflict ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/kernel/cpufeature.c | 37 ++++++++++++++++++++++++++-------- + 1 file changed, 29 insertions(+), 8 deletions(-) + +diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c +index 3f6a2187d0911..094a74b2efa79 100644 +--- a/arch/arm64/kernel/cpufeature.c ++++ b/arch/arm64/kernel/cpufeature.c +@@ -827,17 +827,39 @@ feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) + return val >= entry->min_field_value; + } + +-static bool +-has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) ++static u64 ++read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope) + { +- u64 val; +- + WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); + if (scope == SCOPE_SYSTEM) +- val = read_sanitised_ftr_reg(entry->sys_reg); ++ return read_sanitised_ftr_reg(entry->sys_reg); + else +- val = __read_sysreg_by_encoding(entry->sys_reg); ++ return __read_sysreg_by_encoding(entry->sys_reg); ++} ++ ++static bool ++has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) ++{ ++ int mask; ++ struct arm64_ftr_reg *regp; ++ u64 val = read_scoped_sysreg(entry, scope); ++ ++ regp = get_arm64_ftr_reg(entry->sys_reg); ++ if (!regp) ++ return false; ++ ++ mask = cpuid_feature_extract_unsigned_field(regp->user_mask, ++ entry->field_pos); ++ if (!mask) ++ return false; ++ ++ return feature_matches(val, entry); ++} + ++static bool ++has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) ++{ ++ u64 val = read_scoped_sysreg(entry, scope); + return feature_matches(val, entry); + } + +@@ -1375,9 +1397,8 @@ static const struct arm64_cpu_capabilities arm64_features[] = { + {}, + }; + +- + #define HWCAP_CPUID_MATCH(reg, field, s, min_value) \ +- .matches = has_cpuid_feature, \ ++ .matches = has_user_cpuid_feature, \ + .sys_reg = reg, \ + .field_pos = field, \ + .sign = s, \ +-- +2.43.0 + diff --git a/queue-4.19/arm64-cputype-add-cortex-a720-definitions.patch b/queue-4.19/arm64-cputype-add-cortex-a720-definitions.patch new file mode 100644 index 00000000000..467c4d27f59 --- /dev/null +++ b/queue-4.19/arm64-cputype-add-cortex-a720-definitions.patch @@ -0,0 +1,52 @@ +From c5b3487f750f4065bae8debe09d50d33e8e14251 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:43:50 +0100 +Subject: arm64: cputype: Add Cortex-A720 definitions + +From: Mark Rutland + +[ Upstream commit add332c40328cf06fe35e4b3cde8ec315c4629e5 ] + +Add cputype definitions for Cortex-A720. These will be used for errata +detection in subsequent patches. + +These values can be found in Table A-186 ("MIDR_EL1 bit descriptions") +in issue 0002-05 of the Cortex-A720 TRM, which can be found at: + + https://developer.arm.com/documentation/102530/0002/?lang=en + +Signed-off-by: Mark Rutland +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240603111812.1514101-3-mark.rutland@arm.com +Signed-off-by: Catalin Marinas +[ Mark: trivial backport ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index a89d6baecbede..f63c5500937d7 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -91,6 +91,7 @@ + #define ARM_CPU_PART_CORTEX_A78C 0xD4B + #define ARM_CPU_PART_CORTEX_X3 0xD4E + #define ARM_CPU_PART_NEOVERSE_V2 0xD4F ++#define ARM_CPU_PART_CORTEX_A720 0xD81 + #define ARM_CPU_PART_CORTEX_X4 0xD82 + #define ARM_CPU_PART_NEOVERSE_V3 0xD84 + +@@ -131,6 +132,7 @@ + #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) + #define MIDR_CORTEX_X3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X3) + #define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) ++#define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720) + #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4) + #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3) + #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) +-- +2.43.0 + diff --git a/queue-4.19/arm64-cputype-add-cortex-a725-definitions.patch b/queue-4.19/arm64-cputype-add-cortex-a725-definitions.patch new file mode 100644 index 00000000000..4a2296d41a8 --- /dev/null +++ b/queue-4.19/arm64-cputype-add-cortex-a725-definitions.patch @@ -0,0 +1,54 @@ +From e6f8969a5cdaf9ccf1ec0bfab53f271a61d852b8 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:43:55 +0100 +Subject: arm64: cputype: Add Cortex-A725 definitions + +From: Mark Rutland + +[ Upstream commit 9ef54a384526911095db465e77acc1cb5266b32c ] + +Add cputype definitions for Cortex-A725. These will be used for errata +detection in subsequent patches. + +These values can be found in the Cortex-A725 TRM: + + https://developer.arm.com/documentation/107652/0001/ + +... in table A-247 ("MIDR_EL1 bit descriptions"). + +Signed-off-by: Mark Rutland +Cc: James Morse +Cc: Will Deacon +Reviewed-by: Anshuman Khandual +Link: https://lore.kernel.org/r/20240801101803.1982459-3-mark.rutland@arm.com +Signed-off-by: Catalin Marinas +[ Mark: trivial backport ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index ad054869acf6b..f8be4d7ecde28 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -96,6 +96,7 @@ + #define ARM_CPU_PART_CORTEX_X4 0xD82 + #define ARM_CPU_PART_NEOVERSE_V3 0xD84 + #define ARM_CPU_PART_CORTEX_X925 0xD85 ++#define ARM_CPU_PART_CORTEX_A725 0xD87 + + #define APM_CPU_PART_POTENZA 0x000 + +@@ -139,6 +140,7 @@ + #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4) + #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3) + #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925) ++#define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725) + #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) + #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) + #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) +-- +2.43.0 + diff --git a/queue-4.19/arm64-cputype-add-cortex-x1c-definitions.patch b/queue-4.19/arm64-cputype-add-cortex-x1c-definitions.patch new file mode 100644 index 00000000000..259e1517f3a --- /dev/null +++ b/queue-4.19/arm64-cputype-add-cortex-x1c-definitions.patch @@ -0,0 +1,54 @@ +From 73328340d421408c02b524e48f02cc2b527cce4f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:43:54 +0100 +Subject: arm64: cputype: Add Cortex-X1C definitions + +From: Mark Rutland + +[ Upstream commit 58d245e03c324d083a0ec3b9ab8ebd46ec9848d7 ] + +Add cputype definitions for Cortex-X1C. These will be used for errata +detection in subsequent patches. + +These values can be found in the Cortex-X1C TRM: + + https://developer.arm.com/documentation/101968/0002/ + +... in section B2.107 ("MIDR_EL1, Main ID Register, EL1"). + +Signed-off-by: Mark Rutland +Cc: James Morse +Cc: Will Deacon +Reviewed-by: Anshuman Khandual +Link: https://lore.kernel.org/r/20240801101803.1982459-2-mark.rutland@arm.com +Signed-off-by: Catalin Marinas +[ Mark: trivial backport ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index 304e634c64a05..ad054869acf6b 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -89,6 +89,7 @@ + #define ARM_CPU_PART_CORTEX_X2 0xD48 + #define ARM_CPU_PART_NEOVERSE_N2 0xD49 + #define ARM_CPU_PART_CORTEX_A78C 0xD4B ++#define ARM_CPU_PART_CORTEX_X1C 0xD4C + #define ARM_CPU_PART_CORTEX_X3 0xD4E + #define ARM_CPU_PART_NEOVERSE_V2 0xD4F + #define ARM_CPU_PART_CORTEX_A720 0xD81 +@@ -131,6 +132,7 @@ + #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) + #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) + #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) ++#define MIDR_CORTEX_X1C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1C) + #define MIDR_CORTEX_X3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X3) + #define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) + #define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720) +-- +2.43.0 + diff --git a/queue-4.19/arm64-cputype-add-cortex-x3-definitions.patch b/queue-4.19/arm64-cputype-add-cortex-x3-definitions.patch new file mode 100644 index 00000000000..5c928ea6460 --- /dev/null +++ b/queue-4.19/arm64-cputype-add-cortex-x3-definitions.patch @@ -0,0 +1,52 @@ +From 7ed574c0de6d5dc64e2e5c20244b10ff71d96d80 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:43:49 +0100 +Subject: arm64: cputype: Add Cortex-X3 definitions + +From: Mark Rutland + +[ Upstream commit be5a6f238700f38b534456608588723fba96c5ab ] + +Add cputype definitions for Cortex-X3. These will be used for errata +detection in subsequent patches. + +These values can be found in Table A-263 ("MIDR_EL1 bit descriptions") +in issue 07 of the Cortex-X3 TRM, which can be found at: + + https://developer.arm.com/documentation/101593/0102/?lang=en + +Signed-off-by: Mark Rutland +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240603111812.1514101-2-mark.rutland@arm.com +Signed-off-by: Catalin Marinas +[ Mark: trivial backport ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index 9b44a59195889..a89d6baecbede 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -89,6 +89,7 @@ + #define ARM_CPU_PART_CORTEX_X2 0xD48 + #define ARM_CPU_PART_NEOVERSE_N2 0xD49 + #define ARM_CPU_PART_CORTEX_A78C 0xD4B ++#define ARM_CPU_PART_CORTEX_X3 0xD4E + #define ARM_CPU_PART_NEOVERSE_V2 0xD4F + #define ARM_CPU_PART_CORTEX_X4 0xD82 + #define ARM_CPU_PART_NEOVERSE_V3 0xD84 +@@ -128,6 +129,7 @@ + #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) + #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) + #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) ++#define MIDR_CORTEX_X3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X3) + #define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) + #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4) + #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3) +-- +2.43.0 + diff --git a/queue-4.19/arm64-cputype-add-cortex-x4-definitions.patch b/queue-4.19/arm64-cputype-add-cortex-x4-definitions.patch new file mode 100644 index 00000000000..d02b702c1e8 --- /dev/null +++ b/queue-4.19/arm64-cputype-add-cortex-x4-definitions.patch @@ -0,0 +1,53 @@ +From 96ddf8b4c6ac1111d27d3b11ac374d140397ffd8 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:43:46 +0100 +Subject: arm64: cputype: Add Cortex-X4 definitions + +From: Mark Rutland + +[ Upstream commit 02a0a04676fa7796d9cbc9eb5ca120aaa194d2dd ] + +Add cputype definitions for Cortex-X4. These will be used for errata +detection in subsequent patches. + +These values can be found in Table B-249 ("MIDR_EL1 bit descriptions") +in issue 0002-05 of the Cortex-X4 TRM, which can be found at: + + https://developer.arm.com/documentation/102484/0002/?lang=en + +Signed-off-by: Mark Rutland +Cc: Catalin Marinas +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240508081400.235362-3-mark.rutland@arm.com +Signed-off-by: Will Deacon +[ Mark: fix conflict (dealt with upstream via a later merge) ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index 0e4c0675f7461..89f9c1f5a6305 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -90,6 +90,7 @@ + #define ARM_CPU_PART_NEOVERSE_N2 0xD49 + #define ARM_CPU_PART_CORTEX_A78C 0xD4B + #define ARM_CPU_PART_NEOVERSE_V2 0xD4F ++#define ARM_CPU_PART_CORTEX_X4 0xD82 + + #define APM_CPU_PART_POTENZA 0x000 + +@@ -127,6 +128,7 @@ + #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) + #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) + #define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) ++#define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4) + #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) + #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) + #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) +-- +2.43.0 + diff --git a/queue-4.19/arm64-cputype-add-cortex-x925-definitions.patch b/queue-4.19/arm64-cputype-add-cortex-x925-definitions.patch new file mode 100644 index 00000000000..1ced9271049 --- /dev/null +++ b/queue-4.19/arm64-cputype-add-cortex-x925-definitions.patch @@ -0,0 +1,52 @@ +From c69d813ff655f507d5c1f0df58a6ccba8ffb18ee Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:43:51 +0100 +Subject: arm64: cputype: Add Cortex-X925 definitions + +From: Mark Rutland + +[ Upstream commit fd2ff5f0b320f418288e7a1f919f648fbc8a0dfc ] + +Add cputype definitions for Cortex-X925. These will be used for errata +detection in subsequent patches. + +These values can be found in Table A-285 ("MIDR_EL1 bit descriptions") +in issue 0001-05 of the Cortex-X925 TRM, which can be found at: + + https://developer.arm.com/documentation/102807/0001/?lang=en + +Signed-off-by: Mark Rutland +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240603111812.1514101-4-mark.rutland@arm.com +Signed-off-by: Catalin Marinas +[ Mark: trivial backport ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index f63c5500937d7..304e634c64a05 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -94,6 +94,7 @@ + #define ARM_CPU_PART_CORTEX_A720 0xD81 + #define ARM_CPU_PART_CORTEX_X4 0xD82 + #define ARM_CPU_PART_NEOVERSE_V3 0xD84 ++#define ARM_CPU_PART_CORTEX_X925 0xD85 + + #define APM_CPU_PART_POTENZA 0x000 + +@@ -135,6 +136,7 @@ + #define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720) + #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4) + #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3) ++#define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925) + #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) + #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) + #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) +-- +2.43.0 + diff --git a/queue-4.19/arm64-cputype-add-neoverse-v3-definitions.patch b/queue-4.19/arm64-cputype-add-neoverse-v3-definitions.patch new file mode 100644 index 00000000000..6a6d8ba966e --- /dev/null +++ b/queue-4.19/arm64-cputype-add-neoverse-v3-definitions.patch @@ -0,0 +1,53 @@ +From f8ce65fb173bc72ea170b3611eb1cbf1c635dd2c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:43:47 +0100 +Subject: arm64: cputype: Add Neoverse-V3 definitions + +From: Mark Rutland + +[ Upstream commit 0ce85db6c2141b7ffb95709d76fc55a27ff3cdc1 ] + +Add cputype definitions for Neoverse-V3. These will be used for errata +detection in subsequent patches. + +These values can be found in Table B-249 ("MIDR_EL1 bit descriptions") +in issue 0001-04 of the Neoverse-V3 TRM, which can be found at: + + https://developer.arm.com/documentation/107734/0001/?lang=en + +Signed-off-by: Mark Rutland +Cc: Catalin Marinas +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240508081400.235362-4-mark.rutland@arm.com +Signed-off-by: Will Deacon +[ Mark: trivial backport ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index 89f9c1f5a6305..9b44a59195889 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -91,6 +91,7 @@ + #define ARM_CPU_PART_CORTEX_A78C 0xD4B + #define ARM_CPU_PART_NEOVERSE_V2 0xD4F + #define ARM_CPU_PART_CORTEX_X4 0xD82 ++#define ARM_CPU_PART_NEOVERSE_V3 0xD84 + + #define APM_CPU_PART_POTENZA 0x000 + +@@ -129,6 +130,7 @@ + #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) + #define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) + #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4) ++#define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3) + #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) + #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) + #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) +-- +2.43.0 + diff --git a/queue-4.19/arm64-errata-add-workaround-for-arm-errata-3194386-a.patch b/queue-4.19/arm64-errata-add-workaround-for-arm-errata-3194386-a.patch new file mode 100644 index 00000000000..98286d82204 --- /dev/null +++ b/queue-4.19/arm64-errata-add-workaround-for-arm-errata-3194386-a.patch @@ -0,0 +1,213 @@ +From 480aacf57a668eaaf89cc615f886463aa808ef2d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:43:48 +0100 +Subject: arm64: errata: Add workaround for Arm errata 3194386 and 3312417 + +From: Mark Rutland + +[ Upstream commit 7187bb7d0b5c7dfa18ca82e9e5c75e13861b1d88 ] + +Cortex-X4 and Neoverse-V3 suffer from errata whereby an MSR to the SSBS +special-purpose register does not affect subsequent speculative +instructions, permitting speculative store bypassing for a window of +time. This is described in their Software Developer Errata Notice (SDEN) +documents: + +* Cortex-X4 SDEN v8.0, erratum 3194386: + https://developer.arm.com/documentation/SDEN-2432808/0800/ + +* Neoverse-V3 SDEN v6.0, erratum 3312417: + https://developer.arm.com/documentation/SDEN-2891958/0600/ + +To workaround these errata, it is necessary to place a speculation +barrier (SB) after MSR to the SSBS special-purpose register. This patch +adds the requisite SB after writes to SSBS within the kernel, and hides +the presence of SSBS from EL0 such that userspace software which cares +about SSBS will manipulate this via prctl(PR_GET_SPECULATION_CTRL, ...). + +Signed-off-by: Mark Rutland +Cc: Catalin Marinas +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240508081400.235362-5-mark.rutland@arm.com +Signed-off-by: Will Deacon +[ Mark: fix conflicts & renames, drop unneeded cpucaps.h, fold in user_feature_fixup() ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + Documentation/arm64/silicon-errata.txt | 2 ++ + arch/arm64/Kconfig | 41 ++++++++++++++++++++++++++ + arch/arm64/include/asm/cpucaps.h | 3 +- + arch/arm64/kernel/cpu_errata.c | 31 +++++++++++++++++++ + arch/arm64/kernel/cpufeature.c | 12 ++++++++ + 5 files changed, 88 insertions(+), 1 deletion(-) + +diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt +index 5329e3e00e04f..e242e96648ed7 100644 +--- a/Documentation/arm64/silicon-errata.txt ++++ b/Documentation/arm64/silicon-errata.txt +@@ -61,7 +61,9 @@ stable kernels. + | ARM | Cortex-A73 | #858921 | ARM64_ERRATUM_858921 | + | ARM | Cortex-A55 | #1024718 | ARM64_ERRATUM_1024718 | + | ARM | Cortex-A76 | #1463225 | ARM64_ERRATUM_1463225 | ++| ARM | Cortex-X4 | #3194386 | ARM64_ERRATUM_3194386 | + | ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 | ++| ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3312417 | + | ARM | MMU-500 | #841119,#826419 | N/A | + | | | | | + | Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 | +diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig +index e16f0d45b47ac..2816ee3bfd989 100644 +--- a/arch/arm64/Kconfig ++++ b/arch/arm64/Kconfig +@@ -531,6 +531,47 @@ config ARM64_ERRATUM_1742098 + + If unsure, say Y. + ++config ARM64_WORKAROUND_SPECULATIVE_SSBS ++ bool ++ ++config ARM64_ERRATUM_3194386 ++ bool "Cortex-X4: 3194386: workaround for MSR SSBS not self-synchronizing" ++ select ARM64_WORKAROUND_SPECULATIVE_SSBS ++ default y ++ help ++ This option adds the workaround for ARM Cortex-X4 erratum 3194386. ++ ++ On affected cores "MSR SSBS, #0" instructions may not affect ++ subsequent speculative instructions, which may permit unexepected ++ speculative store bypassing. ++ ++ Work around this problem by placing a speculation barrier after ++ kernel changes to SSBS. The presence of the SSBS special-purpose ++ register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such ++ that userspace will use the PR_SPEC_STORE_BYPASS prctl to change ++ SSBS. ++ ++ If unsure, say Y. ++ ++config ARM64_ERRATUM_3312417 ++ bool "Neoverse-V3: 3312417: workaround for MSR SSBS not self-synchronizing" ++ select ARM64_WORKAROUND_SPECULATIVE_SSBS ++ default y ++ help ++ This option adds the workaround for ARM Neoverse-V3 erratum 3312417. ++ ++ On affected cores "MSR SSBS, #0" instructions may not affect ++ subsequent speculative instructions, which may permit unexepected ++ speculative store bypassing. ++ ++ Work around this problem by placing a speculation barrier after ++ kernel changes to SSBS. The presence of the SSBS special-purpose ++ register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such ++ that userspace will use the PR_SPEC_STORE_BYPASS prctl to change ++ SSBS. ++ ++ If unsure, say Y. ++ + config CAVIUM_ERRATUM_22375 + bool "Cavium erratum 22375, 24313" + default y +diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h +index a7e2378df3d1c..3588caa7e2f71 100644 +--- a/arch/arm64/include/asm/cpucaps.h ++++ b/arch/arm64/include/asm/cpucaps.h +@@ -57,7 +57,8 @@ + #define ARM64_SPECTRE_BHB 36 + #define ARM64_WORKAROUND_1742098 37 + #define ARM64_HAS_SB 38 ++#define ARM64_WORKAROUND_SPECULATIVE_SSBS 39 + +-#define ARM64_NCAPS 39 ++#define ARM64_NCAPS 40 + + #endif /* __ASM_CPUCAPS_H */ +diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c +index 7edb587fec55d..667ee52e8cb0f 100644 +--- a/arch/arm64/kernel/cpu_errata.c ++++ b/arch/arm64/kernel/cpu_errata.c +@@ -344,6 +344,19 @@ void arm64_set_ssbd_mitigation(bool state) + asm volatile(SET_PSTATE_SSBS(0)); + else + asm volatile(SET_PSTATE_SSBS(1)); ++ ++ /* ++ * SSBS is self-synchronizing and is intended to affect ++ * subsequent speculative instructions, but some CPUs can ++ * speculate with a stale value of SSBS. ++ * ++ * Mitigate this with an unconditional speculation barrier, as ++ * CPUs could mis-speculate branches and bypass a conditional ++ * barrier. ++ */ ++ if (IS_ENABLED(CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS)) ++ spec_bar(); ++ + return; + } + +@@ -694,6 +707,17 @@ static struct midr_range broken_aarch32_aes[] = { + }; + #endif + ++#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS ++static const struct midr_range erratum_spec_ssbs_list[] = { ++#ifdef CONFIG_ARM64_ERRATUM_3194386 ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_X4), ++#endif ++#ifdef CONFIG_ARM64_ERRATUM_3312417 ++ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), ++#endif ++ {} ++}; ++#endif + + const struct arm64_cpu_capabilities arm64_errata[] = { + #if defined(CONFIG_ARM64_ERRATUM_826319) || \ +@@ -903,6 +927,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { + CAP_MIDR_RANGE_LIST(broken_aarch32_aes), + .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, + }, ++#endif ++#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS ++ { ++ .desc = "ARM errata 3194386, 3312417", ++ .capability = ARM64_WORKAROUND_SPECULATIVE_SSBS, ++ ERRATA_MIDR_RANGE_LIST(erratum_spec_ssbs_list), ++ }, + #endif + { + } +diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c +index 094a74b2efa79..e548f4bf3dcd6 100644 +--- a/arch/arm64/kernel/cpufeature.c ++++ b/arch/arm64/kernel/cpufeature.c +@@ -1178,6 +1178,17 @@ static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused) + } + #endif /* CONFIG_ARM64_SSBD */ + ++static void user_feature_fixup(void) ++{ ++ if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_SSBS)) { ++ struct arm64_ftr_reg *regp; ++ ++ regp = get_arm64_ftr_reg(SYS_ID_AA64PFR1_EL1); ++ if (regp) ++ regp->user_mask &= ~GENMASK(7, 4); /* SSBS */ ++ } ++} ++ + static void elf_hwcap_fixup(void) + { + #ifdef CONFIG_ARM64_ERRATUM_1742098 +@@ -1842,6 +1853,7 @@ void __init setup_cpu_features(void) + + setup_system_capabilities(); + mark_const_caps_ready(); ++ user_feature_fixup(); + setup_elf_hwcaps(arm64_elf_hwcaps); + + if (system_supports_32bit_el0()) { +-- +2.43.0 + diff --git a/queue-4.19/arm64-errata-expand-speculative-ssbs-workaround-agai.patch b/queue-4.19/arm64-errata-expand-speculative-ssbs-workaround-agai.patch new file mode 100644 index 00000000000..7e7289dfa2d --- /dev/null +++ b/queue-4.19/arm64-errata-expand-speculative-ssbs-workaround-agai.patch @@ -0,0 +1,195 @@ +From 118f88465b41729b1f742b4ab98949972cc8370c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:43:56 +0100 +Subject: arm64: errata: Expand speculative SSBS workaround (again) + +From: Mark Rutland + +[ Upstream commit b0672bbe133ebb6f7be21fce1d742d52f25bcdc7 ] + +A number of Arm Ltd CPUs suffer from errata whereby an MSR to the SSBS +special-purpose register does not affect subsequent speculative +instructions, permitting speculative store bypassing for a window of +time. + +We worked around this for a number of CPUs in commits: + +* 7187bb7d0b5c7dfa ("arm64: errata: Add workaround for Arm errata 3194386 and 3312417") +* 75b3c43eab594bfb ("arm64: errata: Expand speculative SSBS workaround") + +Since then, similar errata have been published for a number of other Arm +Ltd CPUs, for which the same mitigation is sufficient. This is described +in their respective Software Developer Errata Notice (SDEN) documents: + +* Cortex-A76 (MP052) SDEN v31.0, erratum 3324349 + https://developer.arm.com/documentation/SDEN-885749/3100/ + +* Cortex-A77 (MP074) SDEN v19.0, erratum 3324348 + https://developer.arm.com/documentation/SDEN-1152370/1900/ + +* Cortex-A78 (MP102) SDEN v21.0, erratum 3324344 + https://developer.arm.com/documentation/SDEN-1401784/2100/ + +* Cortex-A78C (MP138) SDEN v16.0, erratum 3324346 + https://developer.arm.com/documentation/SDEN-1707916/1600/ + +* Cortex-A78C (MP154) SDEN v10.0, erratum 3324347 + https://developer.arm.com/documentation/SDEN-2004089/1000/ + +* Cortex-A725 (MP190) SDEN v5.0, erratum 3456106 + https://developer.arm.com/documentation/SDEN-2832921/0500/ + +* Cortex-X1 (MP077) SDEN v21.0, erratum 3324344 + https://developer.arm.com/documentation/SDEN-1401782/2100/ + +* Cortex-X1C (MP136) SDEN v16.0, erratum 3324346 + https://developer.arm.com/documentation/SDEN-1707914/1600/ + +* Neoverse-N1 (MP050) SDEN v32.0, erratum 3324349 + https://developer.arm.com/documentation/SDEN-885747/3200/ + +* Neoverse-V1 (MP076) SDEN v19.0, erratum 3324341 + https://developer.arm.com/documentation/SDEN-1401781/1900/ + +Note that due to the manner in which Arm develops IP and tracks errata, +some CPUs share a common erratum number and some CPUs have multiple +erratum numbers for the same HW issue. + +On parts without SB, it is necessary to use ISB for the workaround. The +spec_bar() macro used in the mitigation will expand to a "DSB SY; ISB" +sequence in this case, which is sufficient on all affected parts. + +Enable the existing mitigation by adding the relevant MIDRs to +erratum_spec_ssbs_list. The list is sorted alphanumerically (involving +moving Neoverse-V3 after Neoverse-V2) so that this is easy to audit and +potentially extend again in future. The Kconfig text is also updated to +clarify the set of affected parts and the mitigation. + +Signed-off-by: Mark Rutland +Cc: James Morse +Cc: Will Deacon +Reviewed-by: Anshuman Khandual +Acked-by: Will Deacon +Link: https://lore.kernel.org/r/20240801101803.1982459-4-mark.rutland@arm.com +Signed-off-by: Catalin Marinas +[ Mark: fix conflicts in silicon-errata.rst ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + Documentation/arm64/silicon-errata.txt | 9 +++++++++ + arch/arm64/Kconfig | 22 ++++++++++++++++------ + arch/arm64/kernel/cpu_errata.c | 11 ++++++++++- + 3 files changed, 35 insertions(+), 7 deletions(-) + +diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt +index 8e978776f799e..eab3b0cf0dbe9 100644 +--- a/Documentation/arm64/silicon-errata.txt ++++ b/Documentation/arm64/silicon-errata.txt +@@ -61,14 +61,23 @@ stable kernels. + | ARM | Cortex-A73 | #858921 | ARM64_ERRATUM_858921 | + | ARM | Cortex-A55 | #1024718 | ARM64_ERRATUM_1024718 | + | ARM | Cortex-A76 | #1463225 | ARM64_ERRATUM_1463225 | ++| ARM | Cortex-A76 | #3324349 | ARM64_ERRATUM_3194386 | ++| ARM | Cortex-A77 | #3324348 | ARM64_ERRATUM_3194386 | ++| ARM | Cortex-A78 | #3324344 | ARM64_ERRATUM_3194386 | ++| ARM | Cortex-A78C | #3324346,3324347| ARM64_ERRATUM_3194386 | + | ARM | Cortex-A710 | #3324338 | ARM64_ERRATUM_3194386 | + | ARM | Cortex-A720 | #3456091 | ARM64_ERRATUM_3194386 | ++| ARM | Cortex-A725 | #3456106 | ARM64_ERRATUM_3194386 | ++| ARM | Cortex-X1 | #3324344 | ARM64_ERRATUM_3194386 | ++| ARM | Cortex-X1C | #3324346 | ARM64_ERRATUM_3194386 | + | ARM | Cortex-X2 | #3324338 | ARM64_ERRATUM_3194386 | + | ARM | Cortex-X3 | #3324335 | ARM64_ERRATUM_3194386 | + | ARM | Cortex-X4 | #3194386 | ARM64_ERRATUM_3194386 | + | ARM | Cortex-X925 | #3324334 | ARM64_ERRATUM_3194386 | + | ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 | ++| ARM | Neoverse-N1 | #3324349 | ARM64_ERRATUM_3194386 | + | ARM | Neoverse-N2 | #3324339 | ARM64_ERRATUM_3194386 | ++| ARM | Neoverse-V1 | #3324341 | ARM64_ERRATUM_3194386 | + | ARM | Neoverse-V2 | #3324336 | ARM64_ERRATUM_3194386 | + | ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3194386 | + | ARM | MMU-500 | #841119,#826419 | N/A | +diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig +index a46fe8d14e56d..15c7a2b6e491e 100644 +--- a/arch/arm64/Kconfig ++++ b/arch/arm64/Kconfig +@@ -532,18 +532,28 @@ config ARM64_ERRATUM_1742098 + If unsure, say Y. + + config ARM64_ERRATUM_3194386 +- bool "Cortex-{A720,X4,X925}/Neoverse-V3: workaround for MSR SSBS not self-synchronizing" ++ bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing" + default y + help + This option adds the workaround for the following errata: + ++ * ARM Cortex-A76 erratum 3324349 ++ * ARM Cortex-A77 erratum 3324348 ++ * ARM Cortex-A78 erratum 3324344 ++ * ARM Cortex-A78C erratum 3324346 ++ * ARM Cortex-A78C erratum 3324347 + * ARM Cortex-A710 erratam 3324338 + * ARM Cortex-A720 erratum 3456091 ++ * ARM Cortex-A725 erratum 3456106 ++ * ARM Cortex-X1 erratum 3324344 ++ * ARM Cortex-X1C erratum 3324346 + * ARM Cortex-X2 erratum 3324338 + * ARM Cortex-X3 erratum 3324335 + * ARM Cortex-X4 erratum 3194386 + * ARM Cortex-X925 erratum 3324334 ++ * ARM Neoverse-N1 erratum 3324349 + * ARM Neoverse N2 erratum 3324339 ++ * ARM Neoverse-V1 erratum 3324341 + * ARM Neoverse V2 erratum 3324336 + * ARM Neoverse-V3 erratum 3312417 + +@@ -551,11 +561,11 @@ config ARM64_ERRATUM_3194386 + subsequent speculative instructions, which may permit unexepected + speculative store bypassing. + +- Work around this problem by placing a speculation barrier after +- kernel changes to SSBS. The presence of the SSBS special-purpose +- register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such +- that userspace will use the PR_SPEC_STORE_BYPASS prctl to change +- SSBS. ++ Work around this problem by placing a Speculation Barrier (SB) or ++ Instruction Synchronization Barrier (ISB) after kernel changes to ++ SSBS. The presence of the SSBS special-purpose register is hidden ++ from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace ++ will use the PR_SPEC_STORE_BYPASS prctl to change SSBS. + + If unsure, say Y. + +diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c +index 487bab3948f8f..e87f8d60075d7 100644 +--- a/arch/arm64/kernel/cpu_errata.c ++++ b/arch/arm64/kernel/cpu_errata.c +@@ -709,15 +709,24 @@ static struct midr_range broken_aarch32_aes[] = { + + #ifdef CONFIG_ARM64_ERRATUM_3194386 + static const struct midr_range erratum_spec_ssbs_list[] = { ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_A76), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_A77), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_A78), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A720), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_A725), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_X1), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C), + MIDR_ALL_VERSIONS(MIDR_CORTEX_X2), + MIDR_ALL_VERSIONS(MIDR_CORTEX_X3), + MIDR_ALL_VERSIONS(MIDR_CORTEX_X4), + MIDR_ALL_VERSIONS(MIDR_CORTEX_X925), ++ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), +- MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), ++ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2), ++ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), + {} + }; + #endif +-- +2.43.0 + diff --git a/queue-4.19/arm64-errata-expand-speculative-ssbs-workaround.patch b/queue-4.19/arm64-errata-expand-speculative-ssbs-workaround.patch new file mode 100644 index 00000000000..f5914d8266b --- /dev/null +++ b/queue-4.19/arm64-errata-expand-speculative-ssbs-workaround.patch @@ -0,0 +1,153 @@ +From 3d3fbebd78b22e0e32557049c5f37594236a4daf Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:43:53 +0100 +Subject: arm64: errata: Expand speculative SSBS workaround + +From: Mark Rutland + +[ Upstream commit 75b3c43eab594bfbd8184ec8ee1a6b820950819a ] + +A number of Arm Ltd CPUs suffer from errata whereby an MSR to the SSBS +special-purpose register does not affect subsequent speculative +instructions, permitting speculative store bypassing for a window of +time. + +We worked around this for Cortex-X4 and Neoverse-V3, in commit: + + 7187bb7d0b5c7dfa ("arm64: errata: Add workaround for Arm errata 3194386 and 3312417") + +... as per their Software Developer Errata Notice (SDEN) documents: + +* Cortex-X4 SDEN v8.0, erratum 3194386: + https://developer.arm.com/documentation/SDEN-2432808/0800/ + +* Neoverse-V3 SDEN v6.0, erratum 3312417: + https://developer.arm.com/documentation/SDEN-2891958/0600/ + +Since then, similar errata have been published for a number of other Arm Ltd +CPUs, for which the mitigation is the same. This is described in their +respective SDEN documents: + +* Cortex-A710 SDEN v19.0, errataum 3324338 + https://developer.arm.com/documentation/SDEN-1775101/1900/?lang=en + +* Cortex-A720 SDEN v11.0, erratum 3456091 + https://developer.arm.com/documentation/SDEN-2439421/1100/?lang=en + +* Cortex-X2 SDEN v19.0, erratum 3324338 + https://developer.arm.com/documentation/SDEN-1775100/1900/?lang=en + +* Cortex-X3 SDEN v14.0, erratum 3324335 + https://developer.arm.com/documentation/SDEN-2055130/1400/?lang=en + +* Cortex-X925 SDEN v8.0, erratum 3324334 + https://developer.arm.com/documentation/109108/800/?lang=en + +* Neoverse-N2 SDEN v17.0, erratum 3324339 + https://developer.arm.com/documentation/SDEN-1982442/1700/?lang=en + +* Neoverse-V2 SDEN v9.0, erratum 3324336 + https://developer.arm.com/documentation/SDEN-2332927/900/?lang=en + +Note that due to shared design lineage, some CPUs share the same erratum +number. + +Add these to the existing mitigation under CONFIG_ARM64_ERRATUM_3194386. +As listing all of the erratum IDs in the runtime description would be +unwieldy, this is reduced to: + + "SSBS not fully self-synchronizing" + +... matching the description of the errata in all of the SDENs. + +Signed-off-by: Mark Rutland +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240603111812.1514101-6-mark.rutland@arm.com +Signed-off-by: Catalin Marinas +[ Mark: fix conflicts and renames ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + Documentation/arm64/silicon-errata.txt | 7 +++++++ + arch/arm64/Kconfig | 9 ++++++++- + arch/arm64/kernel/cpu_errata.c | 9 ++++++++- + 3 files changed, 23 insertions(+), 2 deletions(-) + +diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt +index c7bdac13e3071..8e978776f799e 100644 +--- a/Documentation/arm64/silicon-errata.txt ++++ b/Documentation/arm64/silicon-errata.txt +@@ -61,8 +61,15 @@ stable kernels. + | ARM | Cortex-A73 | #858921 | ARM64_ERRATUM_858921 | + | ARM | Cortex-A55 | #1024718 | ARM64_ERRATUM_1024718 | + | ARM | Cortex-A76 | #1463225 | ARM64_ERRATUM_1463225 | ++| ARM | Cortex-A710 | #3324338 | ARM64_ERRATUM_3194386 | ++| ARM | Cortex-A720 | #3456091 | ARM64_ERRATUM_3194386 | ++| ARM | Cortex-X2 | #3324338 | ARM64_ERRATUM_3194386 | ++| ARM | Cortex-X3 | #3324335 | ARM64_ERRATUM_3194386 | + | ARM | Cortex-X4 | #3194386 | ARM64_ERRATUM_3194386 | ++| ARM | Cortex-X925 | #3324334 | ARM64_ERRATUM_3194386 | + | ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 | ++| ARM | Neoverse-N2 | #3324339 | ARM64_ERRATUM_3194386 | ++| ARM | Neoverse-V2 | #3324336 | ARM64_ERRATUM_3194386 | + | ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3194386 | + | ARM | MMU-500 | #841119,#826419 | N/A | + | | | | | +diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig +index 747d055627362..a46fe8d14e56d 100644 +--- a/arch/arm64/Kconfig ++++ b/arch/arm64/Kconfig +@@ -532,12 +532,19 @@ config ARM64_ERRATUM_1742098 + If unsure, say Y. + + config ARM64_ERRATUM_3194386 +- bool "Cortex-X4/Neoverse-V3: workaround for MSR SSBS not self-synchronizing" ++ bool "Cortex-{A720,X4,X925}/Neoverse-V3: workaround for MSR SSBS not self-synchronizing" + default y + help + This option adds the workaround for the following errata: + ++ * ARM Cortex-A710 erratam 3324338 ++ * ARM Cortex-A720 erratum 3456091 ++ * ARM Cortex-X2 erratum 3324338 ++ * ARM Cortex-X3 erratum 3324335 + * ARM Cortex-X4 erratum 3194386 ++ * ARM Cortex-X925 erratum 3324334 ++ * ARM Neoverse N2 erratum 3324339 ++ * ARM Neoverse V2 erratum 3324336 + * ARM Neoverse-V3 erratum 3312417 + + On affected cores "MSR SSBS, #0" instructions may not affect +diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c +index 61d3929fafae4..487bab3948f8f 100644 +--- a/arch/arm64/kernel/cpu_errata.c ++++ b/arch/arm64/kernel/cpu_errata.c +@@ -709,8 +709,15 @@ static struct midr_range broken_aarch32_aes[] = { + + #ifdef CONFIG_ARM64_ERRATUM_3194386 + static const struct midr_range erratum_spec_ssbs_list[] = { ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_A720), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_X2), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_X3), + MIDR_ALL_VERSIONS(MIDR_CORTEX_X4), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_X925), ++ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), ++ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2), + {} + }; + #endif +@@ -926,7 +933,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = { + #endif + #ifdef CONFIG_ARM64_ERRATUM_3194386 + { +- .desc = "ARM errata 3194386, 3312417", ++ .desc = "SSBS not fully self-synchronizing", + .capability = ARM64_WORKAROUND_SPECULATIVE_SSBS, + ERRATA_MIDR_RANGE_LIST(erratum_spec_ssbs_list), + }, +-- +2.43.0 + diff --git a/queue-4.19/arm64-errata-unify-speculative-ssbs-errata-logic.patch b/queue-4.19/arm64-errata-unify-speculative-ssbs-errata-logic.patch new file mode 100644 index 00000000000..0587ab4e2d8 --- /dev/null +++ b/queue-4.19/arm64-errata-unify-speculative-ssbs-errata-logic.patch @@ -0,0 +1,136 @@ +From 3e387b92ed32c31fc793389def470ae11711b5b3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Aug 2024 11:43:52 +0100 +Subject: arm64: errata: Unify speculative SSBS errata logic + +From: Mark Rutland + +[ Upstream commit ec768766608092087dfb5c1fc45a16a6f524dee2 ] + +Cortex-X4 erratum 3194386 and Neoverse-V3 erratum 3312417 are identical, +with duplicate Kconfig text and some unsightly ifdeffery. While we try +to share code behind CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS, having +separate options results in a fair amount of boilerplate code, and this +will only get worse as we expand the set of affected CPUs. + +To reduce this boilerplate, unify the two behind a common Kconfig +option. This removes the duplicate text and Kconfig logic, and removes +the need for the intermediate ARM64_WORKAROUND_SPECULATIVE_SSBS option. +The set of affected CPUs is described as a list so that this can easily +be extended. + +I've used ARM64_ERRATUM_3194386 (matching the Neoverse-V3 erratum ID) as +the common option, matching the way we use ARM64_ERRATUM_1319367 to +cover Cortex-A57 erratum 1319537 and Cortex-A72 erratum 1319367. + +Signed-off-by: Mark Rutland +Cc: James Morse +Cc: Will Deacon +Link: https://lore.kernel.org/r/20240603111812.1514101-5-mark.rutland@arm.com +Signed-off-by: Catalin Marinas +[ Mark: fix conflicts & renames, drop unneeded cpucaps.h ] +Signed-off-by: Mark Rutland +Signed-off-by: Sasha Levin +--- + Documentation/arm64/silicon-errata.txt | 2 +- + arch/arm64/Kconfig | 28 ++++---------------------- + arch/arm64/kernel/cpu_errata.c | 10 +++------ + 3 files changed, 8 insertions(+), 32 deletions(-) + +diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt +index e242e96648ed7..c7bdac13e3071 100644 +--- a/Documentation/arm64/silicon-errata.txt ++++ b/Documentation/arm64/silicon-errata.txt +@@ -63,7 +63,7 @@ stable kernels. + | ARM | Cortex-A76 | #1463225 | ARM64_ERRATUM_1463225 | + | ARM | Cortex-X4 | #3194386 | ARM64_ERRATUM_3194386 | + | ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 | +-| ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3312417 | ++| ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3194386 | + | ARM | MMU-500 | #841119,#826419 | N/A | + | | | | | + | Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 | +diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig +index 2816ee3bfd989..747d055627362 100644 +--- a/arch/arm64/Kconfig ++++ b/arch/arm64/Kconfig +@@ -531,34 +531,14 @@ config ARM64_ERRATUM_1742098 + + If unsure, say Y. + +-config ARM64_WORKAROUND_SPECULATIVE_SSBS +- bool +- + config ARM64_ERRATUM_3194386 +- bool "Cortex-X4: 3194386: workaround for MSR SSBS not self-synchronizing" +- select ARM64_WORKAROUND_SPECULATIVE_SSBS ++ bool "Cortex-X4/Neoverse-V3: workaround for MSR SSBS not self-synchronizing" + default y + help +- This option adds the workaround for ARM Cortex-X4 erratum 3194386. +- +- On affected cores "MSR SSBS, #0" instructions may not affect +- subsequent speculative instructions, which may permit unexepected +- speculative store bypassing. +- +- Work around this problem by placing a speculation barrier after +- kernel changes to SSBS. The presence of the SSBS special-purpose +- register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such +- that userspace will use the PR_SPEC_STORE_BYPASS prctl to change +- SSBS. ++ This option adds the workaround for the following errata: + +- If unsure, say Y. +- +-config ARM64_ERRATUM_3312417 +- bool "Neoverse-V3: 3312417: workaround for MSR SSBS not self-synchronizing" +- select ARM64_WORKAROUND_SPECULATIVE_SSBS +- default y +- help +- This option adds the workaround for ARM Neoverse-V3 erratum 3312417. ++ * ARM Cortex-X4 erratum 3194386 ++ * ARM Neoverse-V3 erratum 3312417 + + On affected cores "MSR SSBS, #0" instructions may not affect + subsequent speculative instructions, which may permit unexepected +diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c +index 667ee52e8cb0f..61d3929fafae4 100644 +--- a/arch/arm64/kernel/cpu_errata.c ++++ b/arch/arm64/kernel/cpu_errata.c +@@ -354,7 +354,7 @@ void arm64_set_ssbd_mitigation(bool state) + * CPUs could mis-speculate branches and bypass a conditional + * barrier. + */ +- if (IS_ENABLED(CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS)) ++ if (IS_ENABLED(CONFIG_ARM64_ERRATUM_3194386)) + spec_bar(); + + return; +@@ -707,14 +707,10 @@ static struct midr_range broken_aarch32_aes[] = { + }; + #endif + +-#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS +-static const struct midr_range erratum_spec_ssbs_list[] = { + #ifdef CONFIG_ARM64_ERRATUM_3194386 ++static const struct midr_range erratum_spec_ssbs_list[] = { + MIDR_ALL_VERSIONS(MIDR_CORTEX_X4), +-#endif +-#ifdef CONFIG_ARM64_ERRATUM_3312417 + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), +-#endif + {} + }; + #endif +@@ -928,7 +924,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = { + .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, + }, + #endif +-#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS ++#ifdef CONFIG_ARM64_ERRATUM_3194386 + { + .desc = "ARM errata 3194386, 3312417", + .capability = ARM64_WORKAROUND_SPECULATIVE_SSBS, +-- +2.43.0 + diff --git a/queue-4.19/bpf-kprobe-remove-unused-declaring-of-bpf_kprobe_ove.patch b/queue-4.19/bpf-kprobe-remove-unused-declaring-of-bpf_kprobe_ove.patch new file mode 100644 index 00000000000..639e437d262 --- /dev/null +++ b/queue-4.19/bpf-kprobe-remove-unused-declaring-of-bpf_kprobe_ove.patch @@ -0,0 +1,39 @@ +From 1e8f40b055399fd17c195b8ce8087b015be1fe11 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 5 Aug 2024 14:01:21 +0900 +Subject: bpf: kprobe: remove unused declaring of bpf_kprobe_override + +From: Menglong Dong + +[ Upstream commit 0e8b53979ac86eddb3fd76264025a70071a25574 ] + +After the commit 66665ad2f102 ("tracing/kprobe: bpf: Compare instruction +pointer with original one"), "bpf_kprobe_override" is not used anywhere +anymore, and we can remove it now. + +Link: https://lore.kernel.org/all/20240710085939.11520-1-dongml2@chinatelecom.cn/ + +Fixes: 66665ad2f102 ("tracing/kprobe: bpf: Compare instruction pointer with original one") +Signed-off-by: Menglong Dong +Acked-by: Jiri Olsa +Signed-off-by: Masami Hiramatsu (Google) +Signed-off-by: Sasha Levin +--- + include/linux/trace_events.h | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/include/linux/trace_events.h b/include/linux/trace_events.h +index f4077379420fa..f0f7b348fe5e0 100644 +--- a/include/linux/trace_events.h ++++ b/include/linux/trace_events.h +@@ -560,7 +560,6 @@ do { \ + struct perf_event; + + DECLARE_PER_CPU(struct pt_regs, perf_trace_regs); +-DECLARE_PER_CPU(int, bpf_kprobe_override); + + extern int perf_trace_init(struct perf_event *event); + extern void perf_trace_destroy(struct perf_event *event); +-- +2.43.0 + diff --git a/queue-4.19/ext4-fix-wrong-unit-use-in-ext4_mb_find_by_goal.patch b/queue-4.19/ext4-fix-wrong-unit-use-in-ext4_mb_find_by_goal.patch new file mode 100644 index 00000000000..a400dcbc491 --- /dev/null +++ b/queue-4.19/ext4-fix-wrong-unit-use-in-ext4_mb_find_by_goal.patch @@ -0,0 +1,39 @@ +From eca99e049c0762485326f2691d60ed0f15bdb628 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 3 Jun 2023 23:03:11 +0800 +Subject: ext4: fix wrong unit use in ext4_mb_find_by_goal + +From: Kemeng Shi + +[ Upstream commit 99c515e3a860576ba90c11acbc1d6488dfca6463 ] + +We need start in block unit while fe_start is in cluster unit. Use +ext4_grp_offs_to_block helper to convert fe_start to get start in +block unit. + +Signed-off-by: Kemeng Shi +Reviewed-by: Ojaswin Mujoo +Link: https://lore.kernel.org/r/20230603150327.3596033-4-shikemeng@huaweicloud.com +Signed-off-by: Theodore Ts'o +Signed-off-by: Sasha Levin +--- + fs/ext4/mballoc.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c +index 5af5ad53e0ada..5dcc3cad5c7d3 100644 +--- a/fs/ext4/mballoc.c ++++ b/fs/ext4/mballoc.c +@@ -1850,8 +1850,7 @@ int ext4_mb_find_by_goal(struct ext4_allocation_context *ac, + if (max >= ac->ac_g_ex.fe_len && ac->ac_g_ex.fe_len == sbi->s_stripe) { + ext4_fsblk_t start; + +- start = ext4_group_first_block_no(ac->ac_sb, e4b->bd_group) + +- ex.fe_start; ++ start = ext4_grp_offs_to_block(ac->ac_sb, &ex); + /* use do_div to get remainder (would be 64-bit modulo) */ + if (do_div(start, sbi->s_stripe) == 0) { + ac->ac_found++; +-- +2.43.0 + diff --git a/queue-4.19/i2c-smbus-don-t-filter-out-duplicate-alerts.patch b/queue-4.19/i2c-smbus-don-t-filter-out-duplicate-alerts.patch new file mode 100644 index 00000000000..8e59065077b --- /dev/null +++ b/queue-4.19/i2c-smbus-don-t-filter-out-duplicate-alerts.patch @@ -0,0 +1,60 @@ +From f084d76ff7fa701d975904d1d6d7f7a04a555107 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 21 Nov 2019 10:10:51 +0100 +Subject: i2c: smbus: Don't filter out duplicate alerts + +From: Corey Minyard + +[ Upstream commit dca0dd28fa5e0a1ec41a623dbaf667601fc62331 ] + +Getting the same alert twice in a row is legal and normal, +especially on a fast device (like running in qemu). Kind of +like interrupts. So don't report duplicate alerts, and deliver +them normally. + +[JD: Fixed subject] + +Signed-off-by: Corey Minyard +Signed-off-by: Jean Delvare +Reviewed-by: Benjamin Tissoires +Signed-off-by: Wolfram Sang +Stable-dep-of: f6c29f710c1f ("i2c: smbus: Send alert notifications to all devices if source not found") +Signed-off-by: Sasha Levin +--- + drivers/i2c/i2c-smbus.c | 7 ------- + 1 file changed, 7 deletions(-) + +diff --git a/drivers/i2c/i2c-smbus.c b/drivers/i2c/i2c-smbus.c +index 5a1dd7f13bacb..46d7399e2ebe9 100644 +--- a/drivers/i2c/i2c-smbus.c ++++ b/drivers/i2c/i2c-smbus.c +@@ -75,7 +75,6 @@ static irqreturn_t smbus_alert(int irq, void *d) + { + struct i2c_smbus_alert *alert = d; + struct i2c_client *ara; +- unsigned short prev_addr = 0; /* Not a valid address */ + + ara = alert->ara; + +@@ -99,18 +98,12 @@ static irqreturn_t smbus_alert(int irq, void *d) + data.addr = status >> 1; + data.type = I2C_PROTOCOL_SMBUS_ALERT; + +- if (data.addr == prev_addr) { +- dev_warn(&ara->dev, "Duplicate SMBALERT# from dev " +- "0x%02x, skipping\n", data.addr); +- break; +- } + dev_dbg(&ara->dev, "SMBALERT# from dev 0x%02x, flag %d\n", + data.addr, data.data); + + /* Notify driver for the device which issued the alert */ + device_for_each_child(&ara->adapter->dev, &data, + smbus_do_alert); +- prev_addr = data.addr; + } + + return IRQ_HANDLED; +-- +2.43.0 + diff --git a/queue-4.19/i2c-smbus-improve-handling-of-stuck-alerts.patch b/queue-4.19/i2c-smbus-improve-handling-of-stuck-alerts.patch new file mode 100644 index 00000000000..40198c2194c --- /dev/null +++ b/queue-4.19/i2c-smbus-improve-handling-of-stuck-alerts.patch @@ -0,0 +1,123 @@ +From 09f0b4ceb25ca9b18668892be54b2b82b821f68f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 10 Jan 2022 09:28:56 -0800 +Subject: i2c: smbus: Improve handling of stuck alerts + +From: Guenter Roeck + +[ Upstream commit 37c526f00bc1c4f847fc800085f8f009d2e11be6 ] + +The following messages were observed while testing alert functionality +on systems with multiple I2C devices on a single bus if alert was active +on more than one chip. + +smbus_alert 3-000c: SMBALERT# from dev 0x0c, flag 0 +smbus_alert 3-000c: no driver alert()! + +and: + +smbus_alert 3-000c: SMBALERT# from dev 0x28, flag 0 + +Once it starts, this message repeats forever at high rate. There is no +device at any of the reported addresses. + +Analysis shows that this is seen if multiple devices have the alert pin +active. Apparently some devices do not support SMBus arbitration correctly. +They keep sending address bits after detecting an address collision and +handle the collision not at all or too late. +Specifically, address 0x0c is seen with ADT7461A at address 0x4c and +ADM1021 at address 0x18 if alert is active on both chips. Address 0x28 is +seen with ADT7483 at address 0x2a and ADT7461 at address 0x4c if alert is +active on both chips. + +Once the system is in bad state (alert is set by more than one chip), +it often only recovers by power cycling. + +To reduce the impact of this problem, abort the endless loop in +smbus_alert() if the same address is read more than once and not +handled by a driver. + +Fixes: b5527a7766f0 ("i2c: Add SMBus alert support") +Signed-off-by: Guenter Roeck +[wsa: it also fixed an interrupt storm in one of my experiments] +Tested-by: Wolfram Sang +[wsa: rebased, moved a comment as well, improved the 'invalid' value] +Signed-off-by: Wolfram Sang +Stable-dep-of: f6c29f710c1f ("i2c: smbus: Send alert notifications to all devices if source not found") +Signed-off-by: Sasha Levin +--- + drivers/i2c/i2c-smbus.c | 32 +++++++++++++++++++++++++------- + 1 file changed, 25 insertions(+), 7 deletions(-) + +diff --git a/drivers/i2c/i2c-smbus.c b/drivers/i2c/i2c-smbus.c +index 46d7399e2ebe9..ac2a5c2a7f8d8 100644 +--- a/drivers/i2c/i2c-smbus.c ++++ b/drivers/i2c/i2c-smbus.c +@@ -42,6 +42,7 @@ static int smbus_do_alert(struct device *dev, void *addrp) + struct i2c_client *client = i2c_verify_client(dev); + struct alert_data *data = addrp; + struct i2c_driver *driver; ++ int ret; + + if (!client || client->addr != data->addr) + return 0; +@@ -55,16 +56,21 @@ static int smbus_do_alert(struct device *dev, void *addrp) + device_lock(dev); + if (client->dev.driver) { + driver = to_i2c_driver(client->dev.driver); +- if (driver->alert) ++ if (driver->alert) { ++ /* Stop iterating after we find the device */ + driver->alert(client, data->type, data->data); +- else ++ ret = -EBUSY; ++ } else { + dev_warn(&client->dev, "no driver alert()!\n"); +- } else ++ ret = -EOPNOTSUPP; ++ } ++ } else { + dev_dbg(&client->dev, "alert with no driver\n"); ++ ret = -ENODEV; ++ } + device_unlock(dev); + +- /* Stop iterating after we find the device */ +- return -EBUSY; ++ return ret; + } + + /* +@@ -75,6 +81,7 @@ static irqreturn_t smbus_alert(int irq, void *d) + { + struct i2c_smbus_alert *alert = d; + struct i2c_client *ara; ++ unsigned short prev_addr = I2C_CLIENT_END; /* Not a valid address */ + + ara = alert->ara; + +@@ -102,8 +109,19 @@ static irqreturn_t smbus_alert(int irq, void *d) + data.addr, data.data); + + /* Notify driver for the device which issued the alert */ +- device_for_each_child(&ara->adapter->dev, &data, +- smbus_do_alert); ++ status = device_for_each_child(&ara->adapter->dev, &data, ++ smbus_do_alert); ++ /* ++ * If we read the same address more than once, and the alert ++ * was not handled by a driver, it won't do any good to repeat ++ * the loop because it will never terminate. ++ * Bail out in this case. ++ * Note: This assumes that a driver with alert handler handles ++ * the alert properly and clears it if necessary. ++ */ ++ if (data.addr == prev_addr && status != -EBUSY) ++ break; ++ prev_addr = data.addr; + } + + return IRQ_HANDLED; +-- +2.43.0 + diff --git a/queue-4.19/i2c-smbus-send-alert-notifications-to-all-devices-if.patch b/queue-4.19/i2c-smbus-send-alert-notifications-to-all-devices-if.patch new file mode 100644 index 00000000000..f7d6aad2dcb --- /dev/null +++ b/queue-4.19/i2c-smbus-send-alert-notifications-to-all-devices-if.patch @@ -0,0 +1,106 @@ +From 39f0af3be24389b3a3f20a9beaa3051f58e5f9b9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 30 Jul 2024 07:19:41 -0700 +Subject: i2c: smbus: Send alert notifications to all devices if source not + found + +From: Guenter Roeck + +[ Upstream commit f6c29f710c1ff2590109f83be3e212b86c01e0f3 ] + +If a SMBus alert is received and the originating device is not found, +the reason may be that the address reported on the SMBus alert address +is corrupted, for example because multiple devices asserted alert and +do not correctly implement SMBus arbitration. + +If this happens, call alert handlers on all devices connected to the +given I2C bus, in the hope that this cleans up the situation. + +This change reliably fixed the problem on a system with multiple devices +on a single bus. Example log where the device on address 0x18 (ADM1021) +and on address 0x4c (ADT7461A) both had the alert line asserted: + +smbus_alert 3-000c: SMBALERT# from dev 0x0c, flag 0 +smbus_alert 3-000c: no driver alert()! +smbus_alert 3-000c: SMBALERT# from dev 0x0c, flag 0 +smbus_alert 3-000c: no driver alert()! +lm90 3-0018: temp1 out of range, please check! +lm90 3-0018: Disabling ALERT# +lm90 3-0029: Everything OK +lm90 3-002a: Everything OK +lm90 3-004c: temp1 out of range, please check! +lm90 3-004c: temp2 out of range, please check! +lm90 3-004c: Disabling ALERT# + +Fixes: b5527a7766f0 ("i2c: Add SMBus alert support") +Signed-off-by: Guenter Roeck +[wsa: fixed a typo in the commit message] +Signed-off-by: Wolfram Sang +Signed-off-by: Sasha Levin +--- + drivers/i2c/i2c-smbus.c | 38 +++++++++++++++++++++++++++++++++++--- + 1 file changed, 35 insertions(+), 3 deletions(-) + +diff --git a/drivers/i2c/i2c-smbus.c b/drivers/i2c/i2c-smbus.c +index ac2a5c2a7f8d8..0e9c2943194c8 100644 +--- a/drivers/i2c/i2c-smbus.c ++++ b/drivers/i2c/i2c-smbus.c +@@ -73,6 +73,32 @@ static int smbus_do_alert(struct device *dev, void *addrp) + return ret; + } + ++/* Same as above, but call back all drivers with alert handler */ ++ ++static int smbus_do_alert_force(struct device *dev, void *addrp) ++{ ++ struct i2c_client *client = i2c_verify_client(dev); ++ struct alert_data *data = addrp; ++ struct i2c_driver *driver; ++ ++ if (!client || (client->flags & I2C_CLIENT_TEN)) ++ return 0; ++ ++ /* ++ * Drivers should either disable alerts, or provide at least ++ * a minimal handler. Lock so the driver won't change. ++ */ ++ device_lock(dev); ++ if (client->dev.driver) { ++ driver = to_i2c_driver(client->dev.driver); ++ if (driver->alert) ++ driver->alert(client, data->type, data->data); ++ } ++ device_unlock(dev); ++ ++ return 0; ++} ++ + /* + * The alert IRQ handler needs to hand work off to a task which can issue + * SMBus calls, because those sleeping calls can't be made in IRQ context. +@@ -114,13 +140,19 @@ static irqreturn_t smbus_alert(int irq, void *d) + /* + * If we read the same address more than once, and the alert + * was not handled by a driver, it won't do any good to repeat +- * the loop because it will never terminate. +- * Bail out in this case. ++ * the loop because it will never terminate. Try again, this ++ * time calling the alert handlers of all devices connected to ++ * the bus, and abort the loop afterwards. If this helps, we ++ * are all set. If it doesn't, there is nothing else we can do, ++ * so we might as well abort the loop. + * Note: This assumes that a driver with alert handler handles + * the alert properly and clears it if necessary. + */ +- if (data.addr == prev_addr && status != -EBUSY) ++ if (data.addr == prev_addr && status != -EBUSY) { ++ device_for_each_child(&ara->adapter->dev, &data, ++ smbus_do_alert_force); + break; ++ } + prev_addr = data.addr; + } + +-- +2.43.0 + diff --git a/queue-4.19/series b/queue-4.19/series index 90f16a3e0d9..84893b39a31 100644 --- a/queue-4.19/series +++ b/queue-4.19/series @@ -143,3 +143,29 @@ media-uvcvideo-fix-the-bandwdith-quirk-on-usb-3.x.patch jbd2-avoid-memleak-in-jbd2_journal_write_metadata_bu.patch s390-sclp-prevent-release-of-buffer-in-i-o.patch sunrpc-fix-a-race-to-wake-a-sync-task.patch +ext4-fix-wrong-unit-use-in-ext4_mb_find_by_goal.patch +arm64-add-support-for-sb-barrier-and-patch-in-over-d.patch +arm64-cpufeature-force-hwcap-to-be-based-on-the-sysr.patch +arm64-add-neoverse-v2-part.patch +arm64-cputype-add-cortex-x4-definitions.patch +arm64-cputype-add-neoverse-v3-definitions.patch +arm64-errata-add-workaround-for-arm-errata-3194386-a.patch +arm64-cputype-add-cortex-x3-definitions.patch +arm64-cputype-add-cortex-a720-definitions.patch +arm64-cputype-add-cortex-x925-definitions.patch +arm64-errata-unify-speculative-ssbs-errata-logic.patch +arm64-errata-expand-speculative-ssbs-workaround.patch +arm64-cputype-add-cortex-x1c-definitions.patch +arm64-cputype-add-cortex-a725-definitions.patch +arm64-errata-expand-speculative-ssbs-workaround-agai.patch +i2c-smbus-don-t-filter-out-duplicate-alerts.patch +i2c-smbus-improve-handling-of-stuck-alerts.patch +i2c-smbus-send-alert-notifications-to-all-devices-if.patch +bpf-kprobe-remove-unused-declaring-of-bpf_kprobe_ove.patch +spi-lpspi-replace-all-master-with-controller.patch +spi-lpspi-add-slave-mode-support.patch +spi-lpspi-let-watermark-change-with-send-data-length.patch +spi-lpspi-add-i.mx8-boards-support-for-lpspi.patch +spi-lpspi-add-the-error-info-of-transfer-speed-setti.patch +spi-fsl-lpspi-remove-unneeded-array.patch +spi-spi-fsl-lpspi-fix-scldiv-calculation.patch diff --git a/queue-4.19/spi-fsl-lpspi-remove-unneeded-array.patch b/queue-4.19/spi-fsl-lpspi-remove-unneeded-array.patch new file mode 100644 index 00000000000..27093416149 --- /dev/null +++ b/queue-4.19/spi-fsl-lpspi-remove-unneeded-array.patch @@ -0,0 +1,55 @@ +From 8e35b44bf822ae49a6b0e1e14c72b35ec39c7ae2 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 20 Feb 2020 14:11:48 +0000 +Subject: spi: fsl-lpspi: remove unneeded array + +From: Oleksandr Suvorov + +[ Upstream commit 2fa98705a9289c758b6154a22174aa8d4041a285 ] + +- replace the array with the shift operation +- remove the extra comparing operation. + +Signed-off-by: Oleksandr Suvorov +Link: https://lore.kernel.org/r/20200220141143.3902922-2-oleksandr.suvorov@toradex.com +Signed-off-by: Mark Brown +Stable-dep-of: 730bbfaf7d48 ("spi: spi-fsl-lpspi: Fix scldiv calculation") +Signed-off-by: Sasha Levin +--- + drivers/spi/spi-fsl-lpspi.c | 7 ++----- + 1 file changed, 2 insertions(+), 5 deletions(-) + +diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c +index 8e1f6ee0a7993..21c8866ebbd12 100644 +--- a/drivers/spi/spi-fsl-lpspi.c ++++ b/drivers/spi/spi-fsl-lpspi.c +@@ -67,8 +67,6 @@ + #define TCR_RXMSK BIT(19) + #define TCR_TXMSK BIT(18) + +-static int clkdivs[] = {1, 2, 4, 8, 16, 32, 64, 128}; +- + struct lpspi_config { + u8 bpw; + u8 chip_select; +@@ -271,15 +269,14 @@ static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi) + } + + for (prescale = 0; prescale < 8; prescale++) { +- scldiv = perclk_rate / +- (clkdivs[prescale] * config.speed_hz) - 2; ++ scldiv = perclk_rate / config.speed_hz / (1 << prescale) - 2; + if (scldiv < 256) { + fsl_lpspi->config.prescale = prescale; + break; + } + } + +- if (prescale == 8 && scldiv >= 256) ++ if (scldiv >= 256) + return -EINVAL; + + writel(scldiv | (scldiv << 8) | ((scldiv >> 1) << 16), +-- +2.43.0 + diff --git a/queue-4.19/spi-lpspi-add-i.mx8-boards-support-for-lpspi.patch b/queue-4.19/spi-lpspi-add-i.mx8-boards-support-for-lpspi.patch new file mode 100644 index 00000000000..8498350555c --- /dev/null +++ b/queue-4.19/spi-lpspi-add-i.mx8-boards-support-for-lpspi.patch @@ -0,0 +1,132 @@ +From 163caa86c87c2b3b445a22a05c2ea894e5696991 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 6 Mar 2019 06:30:34 +0000 +Subject: spi: lpspi: Add i.MX8 boards support for lpspi + +From: Clark Wang + +[ Upstream commit f5e5afdb0e56e81123e02b6a64dd32adc19a90d4 ] + +Add both ipg and per clock for lpspi to support i.MX8QM/QXP boards. + +Signed-off-by: Clark Wang +Signed-off-by: Mark Brown +Stable-dep-of: 730bbfaf7d48 ("spi: spi-fsl-lpspi: Fix scldiv calculation") +Signed-off-by: Sasha Levin +--- + drivers/spi/spi-fsl-lpspi.c | 52 +++++++++++++++++++++++++++++-------- + 1 file changed, 41 insertions(+), 11 deletions(-) + +diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c +index 08dcc3c22e883..5802f188051b8 100644 +--- a/drivers/spi/spi-fsl-lpspi.c ++++ b/drivers/spi/spi-fsl-lpspi.c +@@ -80,7 +80,8 @@ struct lpspi_config { + struct fsl_lpspi_data { + struct device *dev; + void __iomem *base; +- struct clk *clk; ++ struct clk *clk_ipg; ++ struct clk *clk_per; + bool is_slave; + + void *rx_buf; +@@ -147,8 +148,19 @@ static int lpspi_prepare_xfer_hardware(struct spi_controller *controller) + { + struct fsl_lpspi_data *fsl_lpspi = + spi_controller_get_devdata(controller); ++ int ret; ++ ++ ret = clk_prepare_enable(fsl_lpspi->clk_ipg); ++ if (ret) ++ return ret; ++ ++ ret = clk_prepare_enable(fsl_lpspi->clk_per); ++ if (ret) { ++ clk_disable_unprepare(fsl_lpspi->clk_ipg); ++ return ret; ++ } + +- return clk_prepare_enable(fsl_lpspi->clk); ++ return 0; + } + + static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller) +@@ -156,7 +168,8 @@ static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller) + struct fsl_lpspi_data *fsl_lpspi = + spi_controller_get_devdata(controller); + +- clk_disable_unprepare(fsl_lpspi->clk); ++ clk_disable_unprepare(fsl_lpspi->clk_ipg); ++ clk_disable_unprepare(fsl_lpspi->clk_per); + + return 0; + } +@@ -249,7 +262,7 @@ static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi) + unsigned int perclk_rate, scldiv; + u8 prescale; + +- perclk_rate = clk_get_rate(fsl_lpspi->clk); ++ perclk_rate = clk_get_rate(fsl_lpspi->clk_per); + for (prescale = 0; prescale < 8; prescale++) { + scldiv = perclk_rate / + (clkdivs[prescale] * config.speed_hz) - 2; +@@ -522,15 +535,30 @@ static int fsl_lpspi_probe(struct platform_device *pdev) + goto out_controller_put; + } + +- fsl_lpspi->clk = devm_clk_get(&pdev->dev, "ipg"); +- if (IS_ERR(fsl_lpspi->clk)) { +- ret = PTR_ERR(fsl_lpspi->clk); ++ fsl_lpspi->clk_per = devm_clk_get(&pdev->dev, "per"); ++ if (IS_ERR(fsl_lpspi->clk_per)) { ++ ret = PTR_ERR(fsl_lpspi->clk_per); ++ goto out_controller_put; ++ } ++ ++ fsl_lpspi->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); ++ if (IS_ERR(fsl_lpspi->clk_ipg)) { ++ ret = PTR_ERR(fsl_lpspi->clk_ipg); ++ goto out_controller_put; ++ } ++ ++ ret = clk_prepare_enable(fsl_lpspi->clk_ipg); ++ if (ret) { ++ dev_err(&pdev->dev, ++ "can't enable lpspi ipg clock, ret=%d\n", ret); + goto out_controller_put; + } + +- ret = clk_prepare_enable(fsl_lpspi->clk); ++ ret = clk_prepare_enable(fsl_lpspi->clk_per); + if (ret) { +- dev_err(&pdev->dev, "can't enable lpspi clock, ret=%d\n", ret); ++ dev_err(&pdev->dev, ++ "can't enable lpspi per clock, ret=%d\n", ret); ++ clk_disable_unprepare(fsl_lpspi->clk_ipg); + goto out_controller_put; + } + +@@ -538,7 +566,8 @@ static int fsl_lpspi_probe(struct platform_device *pdev) + fsl_lpspi->txfifosize = 1 << (temp & 0x0f); + fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f); + +- clk_disable_unprepare(fsl_lpspi->clk); ++ clk_disable_unprepare(fsl_lpspi->clk_per); ++ clk_disable_unprepare(fsl_lpspi->clk_ipg); + + ret = devm_spi_register_controller(&pdev->dev, controller); + if (ret < 0) { +@@ -560,7 +589,8 @@ static int fsl_lpspi_remove(struct platform_device *pdev) + struct fsl_lpspi_data *fsl_lpspi = + spi_controller_get_devdata(controller); + +- clk_disable_unprepare(fsl_lpspi->clk); ++ clk_disable_unprepare(fsl_lpspi->clk_per); ++ clk_disable_unprepare(fsl_lpspi->clk_ipg); + + return 0; + } +-- +2.43.0 + diff --git a/queue-4.19/spi-lpspi-add-slave-mode-support.patch b/queue-4.19/spi-lpspi-add-slave-mode-support.patch new file mode 100644 index 00000000000..eec53f0de61 --- /dev/null +++ b/queue-4.19/spi-lpspi-add-slave-mode-support.patch @@ -0,0 +1,230 @@ +From 90d89afbea93b5ffe1f1fe5365256ecbdff2d5e5 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 7 Dec 2018 02:50:36 +0000 +Subject: spi: lpspi: Add slave mode support + +From: Clark Wang + +[ Upstream commit bcd87317aae26b9ac497cbc1232783aaea1aeed4 ] + +Add slave mode support to the fsl-lpspi driver, only in PIO mode. + +For now, there are some limitations for slave mode transmission: +1. The stale data in RXFIFO will be dropped when the Slave does any new + transfer. +2. One transfer can be finished only after all transfer->len data been + transferred to master device +3. Slave device only accepts transfer->len data. Any data longer than + this from master device will be dropped. Any data shorter than this + from master will cause LPSPI to stuck due to mentioned limitation 2. +4. Only PIO transfer is supported in Slave Mode. + +Wire connection: +GND, SCK, MISO(to MISO of slave), MOSI(to MOSI of slave), SCS + +Signed-off-by: Clark Wang +Signed-off-by: Mark Brown +Stable-dep-of: 730bbfaf7d48 ("spi: spi-fsl-lpspi: Fix scldiv calculation") +Signed-off-by: Sasha Levin +--- + drivers/spi/spi-fsl-lpspi.c | 107 ++++++++++++++++++++++++++---------- + 1 file changed, 79 insertions(+), 28 deletions(-) + +diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c +index 725d6ac5f814d..cbf165e7bd17b 100644 +--- a/drivers/spi/spi-fsl-lpspi.c ++++ b/drivers/spi/spi-fsl-lpspi.c +@@ -55,6 +55,7 @@ + #define IER_RDIE BIT(1) + #define IER_TDIE BIT(0) + #define CFGR1_PCSCFG BIT(27) ++#define CFGR1_PINCFG (BIT(24)|BIT(25)) + #define CFGR1_PCSPOL BIT(8) + #define CFGR1_NOSTALL BIT(3) + #define CFGR1_MASTER BIT(0) +@@ -80,6 +81,7 @@ struct fsl_lpspi_data { + struct device *dev; + void __iomem *base; + struct clk *clk; ++ bool is_slave; + + void *rx_buf; + const void *tx_buf; +@@ -92,6 +94,8 @@ struct fsl_lpspi_data { + + struct lpspi_config config; + struct completion xfer_done; ++ ++ bool slave_aborted; + }; + + static const struct of_device_id fsl_lpspi_dt_ids[] = { +@@ -206,21 +210,22 @@ static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi, + u32 temp = 0; + + temp |= fsl_lpspi->config.bpw - 1; +- temp |= fsl_lpspi->config.prescale << 27; + temp |= (fsl_lpspi->config.mode & 0x3) << 30; +- temp |= (fsl_lpspi->config.chip_select & 0x3) << 24; +- +- /* +- * Set TCR_CONT will keep SS asserted after current transfer. +- * For the first transfer, clear TCR_CONTC to assert SS. +- * For subsequent transfer, set TCR_CONTC to keep SS asserted. +- */ +- temp |= TCR_CONT; +- if (is_first_xfer) +- temp &= ~TCR_CONTC; +- else +- temp |= TCR_CONTC; +- ++ if (!fsl_lpspi->is_slave) { ++ temp |= fsl_lpspi->config.prescale << 27; ++ temp |= (fsl_lpspi->config.chip_select & 0x3) << 24; ++ ++ /* ++ * Set TCR_CONT will keep SS asserted after current transfer. ++ * For the first transfer, clear TCR_CONTC to assert SS. ++ * For subsequent transfer, set TCR_CONTC to keep SS asserted. ++ */ ++ temp |= TCR_CONT; ++ if (is_first_xfer) ++ temp &= ~TCR_CONTC; ++ else ++ temp |= TCR_CONTC; ++ } + writel(temp, fsl_lpspi->base + IMX7ULP_TCR); + + dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp); +@@ -273,13 +278,18 @@ static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi) + writel(temp, fsl_lpspi->base + IMX7ULP_CR); + writel(0, fsl_lpspi->base + IMX7ULP_CR); + +- ret = fsl_lpspi_set_bitrate(fsl_lpspi); +- if (ret) +- return ret; ++ if (!fsl_lpspi->is_slave) { ++ ret = fsl_lpspi_set_bitrate(fsl_lpspi); ++ if (ret) ++ return ret; ++ } + + fsl_lpspi_set_watermark(fsl_lpspi); + +- temp = CFGR1_PCSCFG | CFGR1_MASTER; ++ if (!fsl_lpspi->is_slave) ++ temp = CFGR1_MASTER; ++ else ++ temp = CFGR1_PINCFG; + if (fsl_lpspi->config.mode & SPI_CS_HIGH) + temp |= CFGR1_PCSPOL; + writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1); +@@ -322,6 +332,37 @@ static void fsl_lpspi_setup_transfer(struct spi_device *spi, + fsl_lpspi_config(fsl_lpspi); + } + ++static int fsl_lpspi_slave_abort(struct spi_controller *controller) ++{ ++ struct fsl_lpspi_data *fsl_lpspi = ++ spi_controller_get_devdata(controller); ++ ++ fsl_lpspi->slave_aborted = true; ++ complete(&fsl_lpspi->xfer_done); ++ return 0; ++} ++ ++static int fsl_lpspi_wait_for_completion(struct spi_controller *controller) ++{ ++ struct fsl_lpspi_data *fsl_lpspi = ++ spi_controller_get_devdata(controller); ++ ++ if (fsl_lpspi->is_slave) { ++ if (wait_for_completion_interruptible(&fsl_lpspi->xfer_done) || ++ fsl_lpspi->slave_aborted) { ++ dev_dbg(fsl_lpspi->dev, "interrupted\n"); ++ return -EINTR; ++ } ++ } else { ++ if (!wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ)) { ++ dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n"); ++ return -ETIMEDOUT; ++ } ++ } ++ ++ return 0; ++} ++ + static int fsl_lpspi_transfer_one(struct spi_controller *controller, + struct spi_device *spi, + struct spi_transfer *t) +@@ -335,13 +376,13 @@ static int fsl_lpspi_transfer_one(struct spi_controller *controller, + fsl_lpspi->remain = t->len; + + reinit_completion(&fsl_lpspi->xfer_done); ++ fsl_lpspi->slave_aborted = false; ++ + fsl_lpspi_write_tx_fifo(fsl_lpspi); + +- ret = wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ); +- if (!ret) { +- dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n"); +- return -ETIMEDOUT; +- } ++ ret = fsl_lpspi_wait_for_completion(controller); ++ if (ret) ++ return ret; + + ret = fsl_lpspi_txfifo_empty(fsl_lpspi); + if (ret) +@@ -380,10 +421,12 @@ static int fsl_lpspi_transfer_one_msg(struct spi_controller *controller, + } + + complete: +- /* de-assert SS, then finalize current message */ +- temp = readl(fsl_lpspi->base + IMX7ULP_TCR); +- temp &= ~TCR_CONTC; +- writel(temp, fsl_lpspi->base + IMX7ULP_TCR); ++ if (!fsl_lpspi->is_slave) { ++ /* de-assert SS, then finalize current message */ ++ temp = readl(fsl_lpspi->base + IMX7ULP_TCR); ++ temp &= ~TCR_CONTC; ++ writel(temp, fsl_lpspi->base + IMX7ULP_TCR); ++ } + + msg->status = ret; + spi_finalize_current_message(controller); +@@ -421,8 +464,13 @@ static int fsl_lpspi_probe(struct platform_device *pdev) + int ret, irq; + u32 temp; + +- controller = spi_alloc_master(&pdev->dev, ++ if (of_property_read_bool((&pdev->dev)->of_node, "spi-slave")) ++ controller = spi_alloc_slave(&pdev->dev, ++ sizeof(struct fsl_lpspi_data)); ++ else ++ controller = spi_alloc_master(&pdev->dev, + sizeof(struct fsl_lpspi_data)); ++ + if (!controller) + return -ENOMEM; + +@@ -433,6 +481,8 @@ static int fsl_lpspi_probe(struct platform_device *pdev) + + fsl_lpspi = spi_controller_get_devdata(controller); + fsl_lpspi->dev = &pdev->dev; ++ fsl_lpspi->is_slave = of_property_read_bool((&pdev->dev)->of_node, ++ "spi-slave"); + + controller->transfer_one_message = fsl_lpspi_transfer_one_msg; + controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware; +@@ -441,6 +491,7 @@ static int fsl_lpspi_probe(struct platform_device *pdev) + controller->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX; + controller->dev.of_node = pdev->dev.of_node; + controller->bus_num = pdev->id; ++ controller->slave_abort = fsl_lpspi_slave_abort; + + init_completion(&fsl_lpspi->xfer_done); + +-- +2.43.0 + diff --git a/queue-4.19/spi-lpspi-add-the-error-info-of-transfer-speed-setti.patch b/queue-4.19/spi-lpspi-add-the-error-info-of-transfer-speed-setti.patch new file mode 100644 index 00000000000..8f701db6c15 --- /dev/null +++ b/queue-4.19/spi-lpspi-add-the-error-info-of-transfer-speed-setti.patch @@ -0,0 +1,74 @@ +From cf722d480a821551eaf48d68c2ee45ea698b1b0d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 6 Mar 2019 06:30:41 +0000 +Subject: spi: lpspi: add the error info of transfer speed setting + +From: Clark Wang + +[ Upstream commit 77736a98b859e2c64aebbd0f90b2ce4b17682396 ] + +Add a error info when set a speed which greater than half of per-clk of +spi module. + +The minimum SCK period is 2 cycles(CCR[SCKDIV]). So the maximum transfer +speed is half of spi per-clk. + +Signed-off-by: Clark Wang +Signed-off-by: Mark Brown +Stable-dep-of: 730bbfaf7d48 ("spi: spi-fsl-lpspi: Fix scldiv calculation") +Signed-off-by: Sasha Levin +--- + drivers/spi/spi-fsl-lpspi.c | 16 +++++++++++++--- + 1 file changed, 13 insertions(+), 3 deletions(-) + +diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c +index 5802f188051b8..8e1f6ee0a7993 100644 +--- a/drivers/spi/spi-fsl-lpspi.c ++++ b/drivers/spi/spi-fsl-lpspi.c +@@ -263,6 +263,13 @@ static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi) + u8 prescale; + + perclk_rate = clk_get_rate(fsl_lpspi->clk_per); ++ ++ if (config.speed_hz > perclk_rate / 2) { ++ dev_err(fsl_lpspi->dev, ++ "per-clk should be at least two times of transfer speed"); ++ return -EINVAL; ++ } ++ + for (prescale = 0; prescale < 8; prescale++) { + scldiv = perclk_rate / + (clkdivs[prescale] * config.speed_hz) - 2; +@@ -316,7 +323,7 @@ static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi) + return 0; + } + +-static void fsl_lpspi_setup_transfer(struct spi_device *spi, ++static int fsl_lpspi_setup_transfer(struct spi_device *spi, + struct spi_transfer *t) + { + struct fsl_lpspi_data *fsl_lpspi = +@@ -349,7 +356,7 @@ static void fsl_lpspi_setup_transfer(struct spi_device *spi, + else + fsl_lpspi->watermark = fsl_lpspi->txfifosize; + +- fsl_lpspi_config(fsl_lpspi); ++ return fsl_lpspi_config(fsl_lpspi); + } + + static int fsl_lpspi_slave_abort(struct spi_controller *controller) +@@ -428,7 +435,10 @@ static int fsl_lpspi_transfer_one_msg(struct spi_controller *controller, + msg->actual_length = 0; + + list_for_each_entry(xfer, &msg->transfers, transfer_list) { +- fsl_lpspi_setup_transfer(spi, xfer); ++ ret = fsl_lpspi_setup_transfer(spi, xfer); ++ if (ret < 0) ++ goto complete; ++ + fsl_lpspi_set_cmd(fsl_lpspi, is_first_xfer); + + is_first_xfer = false; +-- +2.43.0 + diff --git a/queue-4.19/spi-lpspi-let-watermark-change-with-send-data-length.patch b/queue-4.19/spi-lpspi-let-watermark-change-with-send-data-length.patch new file mode 100644 index 00000000000..bc552b69645 --- /dev/null +++ b/queue-4.19/spi-lpspi-let-watermark-change-with-send-data-length.patch @@ -0,0 +1,66 @@ +From 4d829d95ea8b938bb97c0cfc0c5c42569577162e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 7 Dec 2018 02:50:38 +0000 +Subject: spi: lpspi: Let watermark change with send data length + +From: Clark Wang + +[ Upstream commit cf86874bb9bdb99ba3620428b59b0408fbc703d0 ] + +Configure watermark to change with the length of the sent data. +Support LPSPI sending message shorter than tx/rxfifosize. + +Signed-off-by: Clark Wang +Signed-off-by: Mark Brown +Stable-dep-of: 730bbfaf7d48 ("spi: spi-fsl-lpspi: Fix scldiv calculation") +Signed-off-by: Sasha Levin +--- + drivers/spi/spi-fsl-lpspi.c | 11 +++++++++-- + 1 file changed, 9 insertions(+), 2 deletions(-) + +diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c +index cbf165e7bd17b..08dcc3c22e883 100644 +--- a/drivers/spi/spi-fsl-lpspi.c ++++ b/drivers/spi/spi-fsl-lpspi.c +@@ -89,6 +89,7 @@ struct fsl_lpspi_data { + void (*rx)(struct fsl_lpspi_data *); + + u32 remain; ++ u8 watermark; + u8 txfifosize; + u8 rxfifosize; + +@@ -235,7 +236,7 @@ static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi) + { + u32 temp; + +- temp = fsl_lpspi->txfifosize >> 1 | (fsl_lpspi->rxfifosize >> 1) << 16; ++ temp = fsl_lpspi->watermark >> 1 | (fsl_lpspi->watermark >> 1) << 16; + + writel(temp, fsl_lpspi->base + IMX7ULP_FCR); + +@@ -261,7 +262,8 @@ static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi) + if (prescale == 8 && scldiv >= 256) + return -EINVAL; + +- writel(scldiv, fsl_lpspi->base + IMX7ULP_CCR); ++ writel(scldiv | (scldiv << 8) | ((scldiv >> 1) << 16), ++ fsl_lpspi->base + IMX7ULP_CCR); + + dev_dbg(fsl_lpspi->dev, "perclk=%d, speed=%d, prescale =%d, scldiv=%d\n", + perclk_rate, config.speed_hz, prescale, scldiv); +@@ -329,6 +331,11 @@ static void fsl_lpspi_setup_transfer(struct spi_device *spi, + fsl_lpspi->tx = fsl_lpspi_buf_tx_u32; + } + ++ if (t->len <= fsl_lpspi->txfifosize) ++ fsl_lpspi->watermark = t->len; ++ else ++ fsl_lpspi->watermark = fsl_lpspi->txfifosize; ++ + fsl_lpspi_config(fsl_lpspi); + } + +-- +2.43.0 + diff --git a/queue-4.19/spi-lpspi-replace-all-master-with-controller.patch b/queue-4.19/spi-lpspi-replace-all-master-with-controller.patch new file mode 100644 index 00000000000..4b0b9cf700c --- /dev/null +++ b/queue-4.19/spi-lpspi-replace-all-master-with-controller.patch @@ -0,0 +1,241 @@ +From faa72b5eb3b34418d4404a9de7c122c3a8363382 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 7 Dec 2018 02:50:34 +0000 +Subject: spi: lpspi: Replace all "master" with "controller" + +From: Clark Wang + +[ Upstream commit 07d71557494c05b0651def1651bf6d7e7f47bbbb ] + +In order to enable the slave mode and make the code more readable, +replace all related structure names and object names which is +named "master" with "controller". + +Signed-off-by: Clark Wang +Signed-off-by: Mark Brown +Stable-dep-of: 730bbfaf7d48 ("spi: spi-fsl-lpspi: Fix scldiv calculation") +Signed-off-by: Sasha Levin +--- + drivers/spi/spi-fsl-lpspi.c | 84 ++++++++++++++++++++----------------- + 1 file changed, 46 insertions(+), 38 deletions(-) + +diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c +index 51670976faa35..725d6ac5f814d 100644 +--- a/drivers/spi/spi-fsl-lpspi.c ++++ b/drivers/spi/spi-fsl-lpspi.c +@@ -3,6 +3,7 @@ + // Freescale i.MX7ULP LPSPI driver + // + // Copyright 2016 Freescale Semiconductor, Inc. ++// Copyright 2018 NXP Semiconductors + + #include + #include +@@ -137,16 +138,18 @@ static void fsl_lpspi_intctrl(struct fsl_lpspi_data *fsl_lpspi, + writel(enable, fsl_lpspi->base + IMX7ULP_IER); + } + +-static int lpspi_prepare_xfer_hardware(struct spi_master *master) ++static int lpspi_prepare_xfer_hardware(struct spi_controller *controller) + { +- struct fsl_lpspi_data *fsl_lpspi = spi_master_get_devdata(master); ++ struct fsl_lpspi_data *fsl_lpspi = ++ spi_controller_get_devdata(controller); + + return clk_prepare_enable(fsl_lpspi->clk); + } + +-static int lpspi_unprepare_xfer_hardware(struct spi_master *master) ++static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller) + { +- struct fsl_lpspi_data *fsl_lpspi = spi_master_get_devdata(master); ++ struct fsl_lpspi_data *fsl_lpspi = ++ spi_controller_get_devdata(controller); + + clk_disable_unprepare(fsl_lpspi->clk); + +@@ -291,7 +294,8 @@ static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi) + static void fsl_lpspi_setup_transfer(struct spi_device *spi, + struct spi_transfer *t) + { +- struct fsl_lpspi_data *fsl_lpspi = spi_master_get_devdata(spi->master); ++ struct fsl_lpspi_data *fsl_lpspi = ++ spi_controller_get_devdata(spi->controller); + + fsl_lpspi->config.mode = spi->mode; + fsl_lpspi->config.bpw = t ? t->bits_per_word : spi->bits_per_word; +@@ -318,11 +322,12 @@ static void fsl_lpspi_setup_transfer(struct spi_device *spi, + fsl_lpspi_config(fsl_lpspi); + } + +-static int fsl_lpspi_transfer_one(struct spi_master *master, ++static int fsl_lpspi_transfer_one(struct spi_controller *controller, + struct spi_device *spi, + struct spi_transfer *t) + { +- struct fsl_lpspi_data *fsl_lpspi = spi_master_get_devdata(master); ++ struct fsl_lpspi_data *fsl_lpspi = ++ spi_controller_get_devdata(controller); + int ret; + + fsl_lpspi->tx_buf = t->tx_buf; +@@ -347,10 +352,11 @@ static int fsl_lpspi_transfer_one(struct spi_master *master, + return 0; + } + +-static int fsl_lpspi_transfer_one_msg(struct spi_master *master, ++static int fsl_lpspi_transfer_one_msg(struct spi_controller *controller, + struct spi_message *msg) + { +- struct fsl_lpspi_data *fsl_lpspi = spi_master_get_devdata(master); ++ struct fsl_lpspi_data *fsl_lpspi = ++ spi_controller_get_devdata(controller); + struct spi_device *spi = msg->spi; + struct spi_transfer *xfer; + bool is_first_xfer = true; +@@ -366,7 +372,7 @@ static int fsl_lpspi_transfer_one_msg(struct spi_master *master, + + is_first_xfer = false; + +- ret = fsl_lpspi_transfer_one(master, spi, xfer); ++ ret = fsl_lpspi_transfer_one(controller, spi, xfer); + if (ret < 0) + goto complete; + +@@ -380,7 +386,7 @@ static int fsl_lpspi_transfer_one_msg(struct spi_master *master, + writel(temp, fsl_lpspi->base + IMX7ULP_TCR); + + msg->status = ret; +- spi_finalize_current_message(master); ++ spi_finalize_current_message(controller); + + return ret; + } +@@ -410,30 +416,31 @@ static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id) + static int fsl_lpspi_probe(struct platform_device *pdev) + { + struct fsl_lpspi_data *fsl_lpspi; +- struct spi_master *master; ++ struct spi_controller *controller; + struct resource *res; + int ret, irq; + u32 temp; + +- master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_lpspi_data)); +- if (!master) ++ controller = spi_alloc_master(&pdev->dev, ++ sizeof(struct fsl_lpspi_data)); ++ if (!controller) + return -ENOMEM; + +- platform_set_drvdata(pdev, master); ++ platform_set_drvdata(pdev, controller); + +- master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32); +- master->bus_num = pdev->id; ++ controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32); ++ controller->bus_num = pdev->id; + +- fsl_lpspi = spi_master_get_devdata(master); ++ fsl_lpspi = spi_controller_get_devdata(controller); + fsl_lpspi->dev = &pdev->dev; + +- master->transfer_one_message = fsl_lpspi_transfer_one_msg; +- master->prepare_transfer_hardware = lpspi_prepare_xfer_hardware; +- master->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware; +- master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; +- master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX; +- master->dev.of_node = pdev->dev.of_node; +- master->bus_num = pdev->id; ++ controller->transfer_one_message = fsl_lpspi_transfer_one_msg; ++ controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware; ++ controller->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware; ++ controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; ++ controller->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX; ++ controller->dev.of_node = pdev->dev.of_node; ++ controller->bus_num = pdev->id; + + init_completion(&fsl_lpspi->xfer_done); + +@@ -441,32 +448,32 @@ static int fsl_lpspi_probe(struct platform_device *pdev) + fsl_lpspi->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(fsl_lpspi->base)) { + ret = PTR_ERR(fsl_lpspi->base); +- goto out_master_put; ++ goto out_controller_put; + } + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + ret = irq; +- goto out_master_put; ++ goto out_controller_put; + } + + ret = devm_request_irq(&pdev->dev, irq, fsl_lpspi_isr, 0, + dev_name(&pdev->dev), fsl_lpspi); + if (ret) { + dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret); +- goto out_master_put; ++ goto out_controller_put; + } + + fsl_lpspi->clk = devm_clk_get(&pdev->dev, "ipg"); + if (IS_ERR(fsl_lpspi->clk)) { + ret = PTR_ERR(fsl_lpspi->clk); +- goto out_master_put; ++ goto out_controller_put; + } + + ret = clk_prepare_enable(fsl_lpspi->clk); + if (ret) { + dev_err(&pdev->dev, "can't enable lpspi clock, ret=%d\n", ret); +- goto out_master_put; ++ goto out_controller_put; + } + + temp = readl(fsl_lpspi->base + IMX7ULP_PARAM); +@@ -475,24 +482,25 @@ static int fsl_lpspi_probe(struct platform_device *pdev) + + clk_disable_unprepare(fsl_lpspi->clk); + +- ret = devm_spi_register_master(&pdev->dev, master); ++ ret = devm_spi_register_controller(&pdev->dev, controller); + if (ret < 0) { +- dev_err(&pdev->dev, "spi_register_master error.\n"); +- goto out_master_put; ++ dev_err(&pdev->dev, "spi_register_controller error.\n"); ++ goto out_controller_put; + } + + return 0; + +-out_master_put: +- spi_master_put(master); ++out_controller_put: ++ spi_controller_put(controller); + + return ret; + } + + static int fsl_lpspi_remove(struct platform_device *pdev) + { +- struct spi_master *master = platform_get_drvdata(pdev); +- struct fsl_lpspi_data *fsl_lpspi = spi_master_get_devdata(master); ++ struct spi_controller *controller = platform_get_drvdata(pdev); ++ struct fsl_lpspi_data *fsl_lpspi = ++ spi_controller_get_devdata(controller); + + clk_disable_unprepare(fsl_lpspi->clk); + +@@ -509,6 +517,6 @@ static struct platform_driver fsl_lpspi_driver = { + }; + module_platform_driver(fsl_lpspi_driver); + +-MODULE_DESCRIPTION("LPSPI Master Controller driver"); ++MODULE_DESCRIPTION("LPSPI Controller driver"); + MODULE_AUTHOR("Gao Pan "); + MODULE_LICENSE("GPL"); +-- +2.43.0 + diff --git a/queue-4.19/spi-spi-fsl-lpspi-fix-scldiv-calculation.patch b/queue-4.19/spi-spi-fsl-lpspi-fix-scldiv-calculation.patch new file mode 100644 index 00000000000..c3dad39673d --- /dev/null +++ b/queue-4.19/spi-spi-fsl-lpspi-fix-scldiv-calculation.patch @@ -0,0 +1,57 @@ +From d4c3a4ff3e45075e57767945c14ecb2c8c88cc73 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 4 Aug 2024 13:36:11 +0200 +Subject: spi: spi-fsl-lpspi: Fix scldiv calculation + +From: Stefan Wahren + +[ Upstream commit 730bbfaf7d4890bd99e637db7767dc68cfeb24e7 ] + +The effective SPI clock frequency should never exceed speed_hz +otherwise this might result in undefined behavior of the SPI device. + +Currently the scldiv calculation could violate this constraint. +For the example parameters perclk_rate = 24 MHz and speed_hz = 7 MHz, +the function fsl_lpspi_set_bitrate will determine perscale = 0 and +scldiv = 1, which is a effective SPI clock of 8 MHz. + +So fix this by rounding up the quotient of perclk_rate and speed_hz. +While this never change within the loop, we can pull this out. + +Fixes: 5314987de5e5 ("spi: imx: add lpspi bus driver") +Signed-off-by: Stefan Wahren +Link: https://patch.msgid.link/20240804113611.83613-1-wahrenst@gmx.net +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +--- + drivers/spi/spi-fsl-lpspi.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c +index 21c8866ebbd12..695034e076c5e 100644 +--- a/drivers/spi/spi-fsl-lpspi.c ++++ b/drivers/spi/spi-fsl-lpspi.c +@@ -257,7 +257,7 @@ static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi) + static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi) + { + struct lpspi_config config = fsl_lpspi->config; +- unsigned int perclk_rate, scldiv; ++ unsigned int perclk_rate, scldiv, div; + u8 prescale; + + perclk_rate = clk_get_rate(fsl_lpspi->clk_per); +@@ -268,8 +268,10 @@ static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi) + return -EINVAL; + } + ++ div = DIV_ROUND_UP(perclk_rate, config.speed_hz); ++ + for (prescale = 0; prescale < 8; prescale++) { +- scldiv = perclk_rate / config.speed_hz / (1 << prescale) - 2; ++ scldiv = div / (1 << prescale) - 2; + if (scldiv < 256) { + fsl_lpspi->config.prescale = prescale; + break; +-- +2.43.0 + -- 2.47.3