From 4f97774ac2ee37d29adfd9732009729e1cbf7bdf Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 20 Aug 2025 11:49:23 +0200 Subject: [PATCH] arm64: dts: qcom: sm8550: add PPI interrupt partitions for the ARM PMUs The PMUs shares the same per-cpu (PPI) interrupt, so declare the proper interrupt partition maps and use the 4th interrupt cell to pass the partition phandle for each ARM PMU node. Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20250820-topic-sm8550-upstream-pmu-ppi-4-cells-v1-2-a8915672e996@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 2ebe02e2ca8c0..1b7fbbdba2df9 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -399,22 +399,22 @@ pmu-a510 { compatible = "arm,cortex-a510-pmu"; - interrupts = ; + interrupts = ; }; pmu-a710 { compatible = "arm,cortex-a710-pmu"; - interrupts = ; + interrupts = ; }; pmu-a715 { compatible = "arm,cortex-a715-pmu"; - interrupts = ; + interrupts = ; }; pmu-x3 { compatible = "arm,cortex-x3-pmu"; - interrupts = ; + interrupts = ; }; psci { @@ -5066,6 +5066,24 @@ #address-cells = <2>; #size-cells = <2>; + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 &cpu2>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu3 &cpu4>; + }; + + ppi_cluster2: interrupt-partition-2 { + affinity = <&cpu5 &cpu6>; + }; + + ppi_cluster3: interrupt-partition-3 { + affinity = <&cpu7>; + }; + }; + gic_its: msi-controller@17140000 { compatible = "arm,gic-v3-its"; reg = <0 0x17140000 0 0x20000>; -- 2.47.3