From 5a0b53d7f2da5f6f746971e26db424c36a379ddb Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Thu, 27 Jul 2023 13:02:19 +0200 Subject: [PATCH] 6.4-stable patches added patches: drm-amd-align-smu11-smu_msg_overridepcieparameters-implementation-with-smu13.patch drm-amd-move-helper-for-dynamic-speed-switch-check-out-of-smu13.patch platform-x86-amd-pmf-notify-os-power-slider-update.patch platform-x86-amd-pmf-reduce-verbosity-of-apmf_get_system_params.patch r8169-revert-2ab19de62d67-r8169-remove-aspm-restrictions-now-that-aspm-is-disabled-during-napi-poll.patch series --- ...parameters-implementation-with-smu13.patch | 137 ++++++++++ ...amic-speed-switch-check-out-of-smu13.patch | 99 ++++++++ ...md-pmf-notify-os-power-slider-update.patch | 234 ++++++++++++++++++ ...-verbosity-of-apmf_get_system_params.patch | 33 +++ ...at-aspm-is-disabled-during-napi-poll.patch | 83 +++++++ queue-6.4/series | 5 + 6 files changed, 591 insertions(+) create mode 100644 queue-6.4/drm-amd-align-smu11-smu_msg_overridepcieparameters-implementation-with-smu13.patch create mode 100644 queue-6.4/drm-amd-move-helper-for-dynamic-speed-switch-check-out-of-smu13.patch create mode 100644 queue-6.4/platform-x86-amd-pmf-notify-os-power-slider-update.patch create mode 100644 queue-6.4/platform-x86-amd-pmf-reduce-verbosity-of-apmf_get_system_params.patch create mode 100644 queue-6.4/r8169-revert-2ab19de62d67-r8169-remove-aspm-restrictions-now-that-aspm-is-disabled-during-napi-poll.patch create mode 100644 queue-6.4/series diff --git a/queue-6.4/drm-amd-align-smu11-smu_msg_overridepcieparameters-implementation-with-smu13.patch b/queue-6.4/drm-amd-align-smu11-smu_msg_overridepcieparameters-implementation-with-smu13.patch new file mode 100644 index 00000000000..194c3dc5591 --- /dev/null +++ b/queue-6.4/drm-amd-align-smu11-smu_msg_overridepcieparameters-implementation-with-smu13.patch @@ -0,0 +1,137 @@ +From e701156ccc6c7a5f104a968dda74cd6434178712 Mon Sep 17 00:00:00 2001 +From: Mario Limonciello +Date: Fri, 7 Jul 2023 21:26:09 -0500 +Subject: drm/amd: Align SMU11 SMU_MSG_OverridePcieParameters implementation with SMU13 + +From: Mario Limonciello + +commit e701156ccc6c7a5f104a968dda74cd6434178712 upstream. + +SMU13 overrides dynamic PCIe lane width and dynamic speed by when on +certain hosts. commit 38e4ced80479 ("drm/amd/pm: conditionally disable +pcie lane switching for some sienna_cichlid SKUs") worked around this +issue by setting up certain SKUs to set up certain limits, but the same +fundamental problem with those hosts affects all SMU11 implmentations +as well, so align the SMU11 and SMU13 driver handling. + +Signed-off-by: Mario Limonciello +Reviewed-by: Evan Quan +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org # 6.1.x +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 93 +++------------- + 1 file changed, 20 insertions(+), 73 deletions(-) + +--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +@@ -2081,89 +2081,36 @@ static int sienna_cichlid_display_disabl + return ret; + } + +-static void sienna_cichlid_get_override_pcie_settings(struct smu_context *smu, +- uint32_t *gen_speed_override, +- uint32_t *lane_width_override) +-{ +- struct amdgpu_device *adev = smu->adev; +- +- *gen_speed_override = 0xff; +- *lane_width_override = 0xff; +- +- switch (adev->pdev->device) { +- case 0x73A0: +- case 0x73A1: +- case 0x73A2: +- case 0x73A3: +- case 0x73AB: +- case 0x73AE: +- /* Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 */ +- *lane_width_override = 6; +- break; +- case 0x73E0: +- case 0x73E1: +- case 0x73E3: +- *lane_width_override = 4; +- break; +- case 0x7420: +- case 0x7421: +- case 0x7422: +- case 0x7423: +- case 0x7424: +- *lane_width_override = 3; +- break; +- default: +- break; +- } +-} +- +-#define MAX(a, b) ((a) > (b) ? (a) : (b)) +- + static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu, + uint32_t pcie_gen_cap, + uint32_t pcie_width_cap) + { + struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; + struct smu_11_0_pcie_table *pcie_table = &dpm_context->dpm_tables.pcie_table; +- uint32_t gen_speed_override, lane_width_override; +- uint8_t *table_member1, *table_member2; +- uint32_t min_gen_speed, max_gen_speed; +- uint32_t min_lane_width, max_lane_width; +- uint32_t smu_pcie_arg; ++ u32 smu_pcie_arg; + int ret, i; + +- GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1); +- GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2); +- +- sienna_cichlid_get_override_pcie_settings(smu, +- &gen_speed_override, +- &lane_width_override); +- +- /* PCIE gen speed override */ +- if (gen_speed_override != 0xff) { +- min_gen_speed = MIN(pcie_gen_cap, gen_speed_override); +- max_gen_speed = MIN(pcie_gen_cap, gen_speed_override); +- } else { +- min_gen_speed = MAX(0, table_member1[0]); +- max_gen_speed = MIN(pcie_gen_cap, table_member1[1]); +- min_gen_speed = min_gen_speed > max_gen_speed ? +- max_gen_speed : min_gen_speed; +- } +- pcie_table->pcie_gen[0] = min_gen_speed; +- pcie_table->pcie_gen[1] = max_gen_speed; +- +- /* PCIE lane width override */ +- if (lane_width_override != 0xff) { +- min_lane_width = MIN(pcie_width_cap, lane_width_override); +- max_lane_width = MIN(pcie_width_cap, lane_width_override); ++ /* PCIE gen speed and lane width override */ ++ if (!amdgpu_device_pcie_dynamic_switching_supported()) { ++ if (pcie_table->pcie_gen[NUM_LINK_LEVELS - 1] < pcie_gen_cap) ++ pcie_gen_cap = pcie_table->pcie_gen[NUM_LINK_LEVELS - 1]; ++ ++ if (pcie_table->pcie_lane[NUM_LINK_LEVELS - 1] < pcie_width_cap) ++ pcie_width_cap = pcie_table->pcie_lane[NUM_LINK_LEVELS - 1]; ++ ++ /* Force all levels to use the same settings */ ++ for (i = 0; i < NUM_LINK_LEVELS; i++) { ++ pcie_table->pcie_gen[i] = pcie_gen_cap; ++ pcie_table->pcie_lane[i] = pcie_width_cap; ++ } + } else { +- min_lane_width = MAX(1, table_member2[0]); +- max_lane_width = MIN(pcie_width_cap, table_member2[1]); +- min_lane_width = min_lane_width > max_lane_width ? +- max_lane_width : min_lane_width; ++ for (i = 0; i < NUM_LINK_LEVELS; i++) { ++ if (pcie_table->pcie_gen[i] > pcie_gen_cap) ++ pcie_table->pcie_gen[i] = pcie_gen_cap; ++ if (pcie_table->pcie_lane[i] > pcie_width_cap) ++ pcie_table->pcie_lane[i] = pcie_width_cap; ++ } + } +- pcie_table->pcie_lane[0] = min_lane_width; +- pcie_table->pcie_lane[1] = max_lane_width; + + for (i = 0; i < NUM_LINK_LEVELS; i++) { + smu_pcie_arg = (i << 16 | diff --git a/queue-6.4/drm-amd-move-helper-for-dynamic-speed-switch-check-out-of-smu13.patch b/queue-6.4/drm-amd-move-helper-for-dynamic-speed-switch-check-out-of-smu13.patch new file mode 100644 index 00000000000..d92b1cdc0bf --- /dev/null +++ b/queue-6.4/drm-amd-move-helper-for-dynamic-speed-switch-check-out-of-smu13.patch @@ -0,0 +1,99 @@ +From 188623076d0f1a500583d392b6187056bf7cc71a Mon Sep 17 00:00:00 2001 +From: Mario Limonciello +Date: Fri, 7 Jul 2023 21:26:08 -0500 +Subject: drm/amd: Move helper for dynamic speed switch check out of smu13 + +From: Mario Limonciello + +commit 188623076d0f1a500583d392b6187056bf7cc71a upstream. + +This helper is used for checking if the connected host supports +the feature, it can be moved into generic code to be used by other +smu implementations as well. + +Signed-off-by: Mario Limonciello +Reviewed-by: Evan Quan +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org # 6.1.x +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 19 +++++++++++++++++++ + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 21 +-------------------- + 3 files changed, 21 insertions(+), 20 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +@@ -1246,6 +1246,7 @@ int amdgpu_device_gpu_recover(struct amd + void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); + int amdgpu_device_pci_reset(struct amdgpu_device *adev); + bool amdgpu_device_need_post(struct amdgpu_device *adev); ++bool amdgpu_device_pcie_dynamic_switching_supported(void); + bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); + bool amdgpu_device_aspm_support_quirk(void); + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +@@ -1352,6 +1352,25 @@ bool amdgpu_device_need_post(struct amdg + return true; + } + ++/* ++ * Intel hosts such as Raptor Lake and Sapphire Rapids don't support dynamic ++ * speed switching. Until we have confirmation from Intel that a specific host ++ * supports it, it's safer that we keep it disabled for all. ++ * ++ * https://edc.intel.com/content/www/us/en/design/products/platforms/details/raptor-lake-s/13th-generation-core-processors-datasheet-volume-1-of-2/005/pci-express-support/ ++ * https://gitlab.freedesktop.org/drm/amd/-/issues/2663 ++ */ ++bool amdgpu_device_pcie_dynamic_switching_supported(void) ++{ ++#if IS_ENABLED(CONFIG_X86) ++ struct cpuinfo_x86 *c = &cpu_data(0); ++ ++ if (c->x86_vendor == X86_VENDOR_INTEL) ++ return false; ++#endif ++ return true; ++} ++ + /** + * amdgpu_device_should_use_aspm - check if the device should program ASPM + * +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +@@ -2454,25 +2454,6 @@ int smu_v13_0_mode1_reset(struct smu_con + return ret; + } + +-/* +- * Intel hosts such as Raptor Lake and Sapphire Rapids don't support dynamic +- * speed switching. Until we have confirmation from Intel that a specific host +- * supports it, it's safer that we keep it disabled for all. +- * +- * https://edc.intel.com/content/www/us/en/design/products/platforms/details/raptor-lake-s/13th-generation-core-processors-datasheet-volume-1-of-2/005/pci-express-support/ +- * https://gitlab.freedesktop.org/drm/amd/-/issues/2663 +- */ +-static bool smu_v13_0_is_pcie_dynamic_switching_supported(void) +-{ +-#if IS_ENABLED(CONFIG_X86) +- struct cpuinfo_x86 *c = &cpu_data(0); +- +- if (c->x86_vendor == X86_VENDOR_INTEL) +- return false; +-#endif +- return true; +-} +- + int smu_v13_0_update_pcie_parameters(struct smu_context *smu, + uint32_t pcie_gen_cap, + uint32_t pcie_width_cap) +@@ -2484,7 +2465,7 @@ int smu_v13_0_update_pcie_parameters(str + uint32_t smu_pcie_arg; + int ret, i; + +- if (!smu_v13_0_is_pcie_dynamic_switching_supported()) { ++ if (!amdgpu_device_pcie_dynamic_switching_supported()) { + if (pcie_table->pcie_gen[num_of_levels - 1] < pcie_gen_cap) + pcie_gen_cap = pcie_table->pcie_gen[num_of_levels - 1]; + diff --git a/queue-6.4/platform-x86-amd-pmf-notify-os-power-slider-update.patch b/queue-6.4/platform-x86-amd-pmf-notify-os-power-slider-update.patch new file mode 100644 index 00000000000..ded48c34cbb --- /dev/null +++ b/queue-6.4/platform-x86-amd-pmf-notify-os-power-slider-update.patch @@ -0,0 +1,234 @@ +From 33c9ab5b493a0e922b06c12fed4fdcb862212cda Mon Sep 17 00:00:00 2001 +From: Shyam Sundar S K +Date: Fri, 14 Jul 2023 20:14:35 +0530 +Subject: platform/x86/amd/pmf: Notify OS power slider update + +From: Shyam Sundar S K + +commit 33c9ab5b493a0e922b06c12fed4fdcb862212cda upstream. + +APMF fn8 can notify EC about the OS slider position change. Add this +capability to the PMF driver so that it can call the APMF fn8 based on +the changes in the Platform profile events. + +Co-developed-by: Mario Limonciello +Signed-off-by: Mario Limonciello +Signed-off-by: Patil Rajesh Reddy +Signed-off-by: Shyam Sundar S K +Link: https://lore.kernel.org/r/20230714144435.1239776-2-Shyam-sundar.S-k@amd.com +Reviewed-by: Hans de Goede +Signed-off-by: Hans de Goede +Signed-off-by: Greg Kroah-Hartman +--- + drivers/platform/x86/amd/pmf/acpi.c | 21 ++++++++++ + drivers/platform/x86/amd/pmf/core.c | 9 +++- + drivers/platform/x86/amd/pmf/pmf.h | 16 +++++++ + drivers/platform/x86/amd/pmf/sps.c | 74 ++++++++++++++++++++++++++++++++++-- + 4 files changed, 114 insertions(+), 6 deletions(-) + +--- a/drivers/platform/x86/amd/pmf/acpi.c ++++ b/drivers/platform/x86/amd/pmf/acpi.c +@@ -106,6 +106,27 @@ int apmf_get_static_slider_granular(stru + data, sizeof(*data)); + } + ++int apmf_os_power_slider_update(struct amd_pmf_dev *pdev, u8 event) ++{ ++ struct os_power_slider args; ++ struct acpi_buffer params; ++ union acpi_object *info; ++ int err = 0; ++ ++ args.size = sizeof(args); ++ args.slider_event = event; ++ ++ params.length = sizeof(args); ++ params.pointer = (void *)&args; ++ ++ info = apmf_if_call(pdev, APMF_FUNC_OS_POWER_SLIDER_UPDATE, ¶ms); ++ if (!info) ++ err = -EIO; ++ ++ kfree(info); ++ return err; ++} ++ + static void apmf_sbios_heartbeat_notify(struct work_struct *work) + { + struct amd_pmf_dev *dev = container_of(work, struct amd_pmf_dev, heart_beat.work); +--- a/drivers/platform/x86/amd/pmf/core.c ++++ b/drivers/platform/x86/amd/pmf/core.c +@@ -71,7 +71,11 @@ static int amd_pmf_pwr_src_notify_call(s + return NOTIFY_DONE; + } + +- amd_pmf_set_sps_power_limits(pmf); ++ if (is_apmf_func_supported(pmf, APMF_FUNC_STATIC_SLIDER_GRANULAR)) ++ amd_pmf_set_sps_power_limits(pmf); ++ ++ if (is_apmf_func_supported(pmf, APMF_FUNC_OS_POWER_SLIDER_UPDATE)) ++ amd_pmf_power_slider_update_event(pmf); + + return NOTIFY_OK; + } +@@ -295,7 +299,8 @@ static void amd_pmf_init_features(struct + int ret; + + /* Enable Static Slider */ +- if (is_apmf_func_supported(dev, APMF_FUNC_STATIC_SLIDER_GRANULAR)) { ++ if (is_apmf_func_supported(dev, APMF_FUNC_STATIC_SLIDER_GRANULAR) || ++ is_apmf_func_supported(dev, APMF_FUNC_OS_POWER_SLIDER_UPDATE)) { + amd_pmf_init_sps(dev); + dev->pwr_src_notifier.notifier_call = amd_pmf_pwr_src_notify_call; + power_supply_reg_notifier(&dev->pwr_src_notifier); +--- a/drivers/platform/x86/amd/pmf/pmf.h ++++ b/drivers/platform/x86/amd/pmf/pmf.h +@@ -21,6 +21,7 @@ + #define APMF_FUNC_SBIOS_HEARTBEAT 4 + #define APMF_FUNC_AUTO_MODE 5 + #define APMF_FUNC_SET_FAN_IDX 7 ++#define APMF_FUNC_OS_POWER_SLIDER_UPDATE 8 + #define APMF_FUNC_STATIC_SLIDER_GRANULAR 9 + #define APMF_FUNC_DYN_SLIDER_AC 11 + #define APMF_FUNC_DYN_SLIDER_DC 12 +@@ -44,6 +45,14 @@ + #define GET_STT_LIMIT_APU 0x20 + #define GET_STT_LIMIT_HS2 0x21 + ++/* OS slider update notification */ ++#define DC_BEST_PERF 0 ++#define DC_BETTER_PERF 1 ++#define DC_BATTERY_SAVER 3 ++#define AC_BEST_PERF 4 ++#define AC_BETTER_PERF 5 ++#define AC_BETTER_BATTERY 6 ++ + /* Fan Index for Auto Mode */ + #define FAN_INDEX_AUTO 0xFFFFFFFF + +@@ -193,6 +202,11 @@ struct amd_pmf_static_slider_granular { + struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX][POWER_MODE_MAX]; + }; + ++struct os_power_slider { ++ u16 size; ++ u8 slider_event; ++} __packed; ++ + struct fan_table_control { + bool manual; + unsigned long fan_id; +@@ -383,6 +397,7 @@ int amd_pmf_send_cmd(struct amd_pmf_dev + int amd_pmf_init_metrics_table(struct amd_pmf_dev *dev); + int amd_pmf_get_power_source(void); + int apmf_install_handler(struct amd_pmf_dev *pmf_dev); ++int apmf_os_power_slider_update(struct amd_pmf_dev *dev, u8 flag); + + /* SPS Layer */ + int amd_pmf_get_pprof_modes(struct amd_pmf_dev *pmf); +@@ -393,6 +408,7 @@ void amd_pmf_deinit_sps(struct amd_pmf_d + int apmf_get_static_slider_granular(struct amd_pmf_dev *pdev, + struct apmf_static_slider_granular_output *output); + bool is_pprof_balanced(struct amd_pmf_dev *pmf); ++int amd_pmf_power_slider_update_event(struct amd_pmf_dev *dev); + + + int apmf_update_fan_idx(struct amd_pmf_dev *pdev, bool manual, u32 idx); +--- a/drivers/platform/x86/amd/pmf/sps.c ++++ b/drivers/platform/x86/amd/pmf/sps.c +@@ -119,14 +119,77 @@ int amd_pmf_get_pprof_modes(struct amd_p + return mode; + } + ++int amd_pmf_power_slider_update_event(struct amd_pmf_dev *dev) ++{ ++ u8 mode, flag = 0; ++ int src; ++ ++ mode = amd_pmf_get_pprof_modes(dev); ++ if (mode < 0) ++ return mode; ++ ++ src = amd_pmf_get_power_source(); ++ ++ if (src == POWER_SOURCE_AC) { ++ switch (mode) { ++ case POWER_MODE_PERFORMANCE: ++ flag |= BIT(AC_BEST_PERF); ++ break; ++ case POWER_MODE_BALANCED_POWER: ++ flag |= BIT(AC_BETTER_PERF); ++ break; ++ case POWER_MODE_POWER_SAVER: ++ flag |= BIT(AC_BETTER_BATTERY); ++ break; ++ default: ++ dev_err(dev->dev, "unsupported platform profile\n"); ++ return -EOPNOTSUPP; ++ } ++ ++ } else if (src == POWER_SOURCE_DC) { ++ switch (mode) { ++ case POWER_MODE_PERFORMANCE: ++ flag |= BIT(DC_BEST_PERF); ++ break; ++ case POWER_MODE_BALANCED_POWER: ++ flag |= BIT(DC_BETTER_PERF); ++ break; ++ case POWER_MODE_POWER_SAVER: ++ flag |= BIT(DC_BATTERY_SAVER); ++ break; ++ default: ++ dev_err(dev->dev, "unsupported platform profile\n"); ++ return -EOPNOTSUPP; ++ } ++ } ++ ++ apmf_os_power_slider_update(dev, flag); ++ ++ return 0; ++} ++ + static int amd_pmf_profile_set(struct platform_profile_handler *pprof, + enum platform_profile_option profile) + { + struct amd_pmf_dev *pmf = container_of(pprof, struct amd_pmf_dev, pprof); ++ int ret = 0; + + pmf->current_profile = profile; + +- return amd_pmf_set_sps_power_limits(pmf); ++ /* Notify EC about the slider position change */ ++ if (is_apmf_func_supported(pmf, APMF_FUNC_OS_POWER_SLIDER_UPDATE)) { ++ ret = amd_pmf_power_slider_update_event(pmf); ++ if (ret) ++ return ret; ++ } ++ ++ if (is_apmf_func_supported(pmf, APMF_FUNC_STATIC_SLIDER_GRANULAR)) { ++ ret = amd_pmf_set_sps_power_limits(pmf); ++ if (ret) ++ return ret; ++ } ++ ++ return 0; + } + + int amd_pmf_init_sps(struct amd_pmf_dev *dev) +@@ -134,10 +197,13 @@ int amd_pmf_init_sps(struct amd_pmf_dev + int err; + + dev->current_profile = PLATFORM_PROFILE_BALANCED; +- amd_pmf_load_defaults_sps(dev); + +- /* update SPS balanced power mode thermals */ +- amd_pmf_set_sps_power_limits(dev); ++ if (is_apmf_func_supported(dev, APMF_FUNC_STATIC_SLIDER_GRANULAR)) { ++ amd_pmf_load_defaults_sps(dev); ++ ++ /* update SPS balanced power mode thermals */ ++ amd_pmf_set_sps_power_limits(dev); ++ } + + dev->pprof.profile_get = amd_pmf_profile_get; + dev->pprof.profile_set = amd_pmf_profile_set; diff --git a/queue-6.4/platform-x86-amd-pmf-reduce-verbosity-of-apmf_get_system_params.patch b/queue-6.4/platform-x86-amd-pmf-reduce-verbosity-of-apmf_get_system_params.patch new file mode 100644 index 00000000000..fc2b7f456d6 --- /dev/null +++ b/queue-6.4/platform-x86-amd-pmf-reduce-verbosity-of-apmf_get_system_params.patch @@ -0,0 +1,33 @@ +From 839e90e75e695b3d9ee17f5a2811e7ee5aea8d4a Mon Sep 17 00:00:00 2001 +From: Shyam Sundar S K +Date: Fri, 14 Jul 2023 20:14:34 +0530 +Subject: platform/x86/amd/pmf: reduce verbosity of apmf_get_system_params + +From: Shyam Sundar S K + +commit 839e90e75e695b3d9ee17f5a2811e7ee5aea8d4a upstream. + +apmf_get_system_params() failure is not a critical event, reduce its +verbosity from dev_err to dev_dbg. + +Signed-off-by: Mario Limonciello +Signed-off-by: Shyam Sundar S K +Link: https://lore.kernel.org/r/20230714144435.1239776-1-Shyam-sundar.S-k@amd.com +Reviewed-by: Hans de Goede +Signed-off-by: Hans de Goede +Signed-off-by: Greg Kroah-Hartman +--- + drivers/platform/x86/amd/pmf/acpi.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/platform/x86/amd/pmf/acpi.c ++++ b/drivers/platform/x86/amd/pmf/acpi.c +@@ -310,7 +310,7 @@ int apmf_acpi_init(struct amd_pmf_dev *p + + ret = apmf_get_system_params(pmf_dev); + if (ret) { +- dev_err(pmf_dev->dev, "APMF apmf_get_system_params failed :%d\n", ret); ++ dev_dbg(pmf_dev->dev, "APMF apmf_get_system_params failed :%d\n", ret); + goto out; + } + diff --git a/queue-6.4/r8169-revert-2ab19de62d67-r8169-remove-aspm-restrictions-now-that-aspm-is-disabled-during-napi-poll.patch b/queue-6.4/r8169-revert-2ab19de62d67-r8169-remove-aspm-restrictions-now-that-aspm-is-disabled-during-napi-poll.patch new file mode 100644 index 00000000000..e80480e9295 --- /dev/null +++ b/queue-6.4/r8169-revert-2ab19de62d67-r8169-remove-aspm-restrictions-now-that-aspm-is-disabled-during-napi-poll.patch @@ -0,0 +1,83 @@ +From cf2ffdea0839398cb0551762af7f5efb0a6e0fea Mon Sep 17 00:00:00 2001 +From: Heiner Kallweit +Date: Tue, 18 Jul 2023 13:11:31 +0200 +Subject: r8169: revert 2ab19de62d67 ("r8169: remove ASPM restrictions now that ASPM is disabled during NAPI poll") + +From: Heiner Kallweit + +commit cf2ffdea0839398cb0551762af7f5efb0a6e0fea upstream. + +There have been reports that on a number of systems this change breaks +network connectivity. Therefore effectively revert it. Mainly affected +seem to be systems where BIOS denies ASPM access to OS. +Due to later changes we can't do a direct revert. + +Fixes: 2ab19de62d67 ("r8169: remove ASPM restrictions now that ASPM is disabled during NAPI poll") +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/netdev/e47bac0d-e802-65e1-b311-6acb26d5cf10@freenet.de/T/ +Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217596 +Signed-off-by: Heiner Kallweit +Link: https://lore.kernel.org/r/57f13ec0-b216-d5d8-363d-5b05528ec5fb@gmail.com +Signed-off-by: Jakub Kicinski +Signed-off-by: Greg Kroah-Hartman +--- + drivers/net/ethernet/realtek/r8169_main.c | 27 ++++++++++++++++++++++++++- + 1 file changed, 26 insertions(+), 1 deletion(-) + +--- a/drivers/net/ethernet/realtek/r8169_main.c ++++ b/drivers/net/ethernet/realtek/r8169_main.c +@@ -623,6 +623,7 @@ struct rtl8169_private { + int cfg9346_usage_count; + + unsigned supports_gmii:1; ++ unsigned aspm_manageable:1; + dma_addr_t counters_phys_addr; + struct rtl8169_counters *counters; + struct rtl8169_tc_offsets tc_offset; +@@ -2746,7 +2747,8 @@ static void rtl_hw_aspm_clkreq_enable(st + if (tp->mac_version < RTL_GIGA_MAC_VER_32) + return; + +- if (enable) { ++ /* Don't enable ASPM in the chip if OS can't control ASPM */ ++ if (enable && tp->aspm_manageable) { + /* On these chip versions ASPM can even harm + * bus communication of other PCI devices. + */ +@@ -5156,6 +5158,16 @@ done: + rtl_rar_set(tp, mac_addr); + } + ++/* register is set if system vendor successfully tested ASPM 1.2 */ ++static bool rtl_aspm_is_safe(struct rtl8169_private *tp) ++{ ++ if (tp->mac_version >= RTL_GIGA_MAC_VER_61 && ++ r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) ++ return true; ++ ++ return false; ++} ++ + static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) + { + struct rtl8169_private *tp; +@@ -5227,6 +5239,19 @@ static int rtl_init_one(struct pci_dev * + + tp->mac_version = chipset; + ++ /* Disable ASPM L1 as that cause random device stop working ++ * problems as well as full system hangs for some PCIe devices users. ++ * Chips from RTL8168h partially have issues with L1.2, but seem ++ * to work fine with L1 and L1.1. ++ */ ++ if (rtl_aspm_is_safe(tp)) ++ rc = 0; ++ else if (tp->mac_version >= RTL_GIGA_MAC_VER_46) ++ rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1_2); ++ else ++ rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1); ++ tp->aspm_manageable = !rc; ++ + tp->dash_type = rtl_check_dash(tp); + + tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; diff --git a/queue-6.4/series b/queue-6.4/series new file mode 100644 index 00000000000..f35b6600909 --- /dev/null +++ b/queue-6.4/series @@ -0,0 +1,5 @@ +platform-x86-amd-pmf-notify-os-power-slider-update.patch +platform-x86-amd-pmf-reduce-verbosity-of-apmf_get_system_params.patch +drm-amd-move-helper-for-dynamic-speed-switch-check-out-of-smu13.patch +drm-amd-align-smu11-smu_msg_overridepcieparameters-implementation-with-smu13.patch +r8169-revert-2ab19de62d67-r8169-remove-aspm-restrictions-now-that-aspm-is-disabled-during-napi-poll.patch -- 2.47.3