From 5a11e1dcbc8b64bc76dde2a8c96646bab5e41d6a Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 27 Nov 2012 20:15:20 +0100 Subject: [PATCH] clk: ux500: fix bit error commit 2630b17b6ee47ac79b4f5120ac49105027f644ea upstream. This fixes a bit error in the U8500 clock implementation: the unused p2_pclk12 registered at bit 12 in periphereral group 6 was defined as using bit 11 rather than bit 12. When walking over and disabling the unused clocks in the tree at late init time, p2_pclk12 was disabled, by effectively clearing the but for p2_pclk11 instead of bit 12 as it should have, thus disabling gpio block 6 and 7. Reported-by: Lee Jones Acked-by: Ulf Hansson Cc: Philippe Begnic Signed-off-by: Linus Walleij Signed-off-by: Mike Turquette Signed-off-by: Greg Kroah-Hartman --- drivers/clk/ux500/u8500_clk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c index e2c17d187d98b..6939009521f86 100644 --- a/drivers/clk/ux500/u8500_clk.c +++ b/drivers/clk/ux500/u8500_clk.c @@ -323,7 +323,7 @@ void u8500_clk_init(void) clk_register_clkdev(clk, NULL, "gpioblock1"); clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", U8500_CLKRST2_BASE, - BIT(11), 0); + BIT(12), 0); clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", U8500_CLKRST3_BASE, BIT(0), 0); -- 2.47.3