From 5b110ba4e12a7094f984e8a81007cd693dd9cb6f Mon Sep 17 00:00:00 2001 From: pthaugen Date: Fri, 5 Feb 2016 15:25:39 +0000 Subject: [PATCH] * config/rs6000/crypto.md (crypto_vpermxor_): Correct insn type. * config/rs6000/rs6000.md (mov_hardfloat): Likewise. (*ieee128_mfvsrd_64bit): Likewise. (*ieee128_mfvsrd_32bit): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@233179 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 7 +++++++ gcc/config/rs6000/crypto.md | 2 +- gcc/config/rs6000/rs6000.md | 6 +++--- 3 files changed, 11 insertions(+), 4 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3357d85ff437..1e166ae60d14 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2016-02-05 Pat Haugen + + * config/rs6000/crypto.md (crypto_vpermxor_): Correct insn type. + * config/rs6000/rs6000.md (mov_hardfloat): Likewise. + (*ieee128_mfvsrd_64bit): Likewise. + (*ieee128_mfvsrd_32bit): Likewise. + 2016-02-05 Ilya Enkovich PR target/69369 diff --git a/gcc/config/rs6000/crypto.md b/gcc/config/rs6000/crypto.md index 43015f01acb4..5957abb8f5d8 100644 --- a/gcc/config/rs6000/crypto.md +++ b/gcc/config/rs6000/crypto.md @@ -87,7 +87,7 @@ UNSPEC_VPERMXOR))] "TARGET_P8_VECTOR" "vpermxor %0,%1,%2,%3" - [(set_attr "type" "crypto")]) + [(set_attr "type" "vecperm")]) ;; 1 operand crypto instruction (define_insn "crypto_vsbox" diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 5614695c853d..67863427815d 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -6521,7 +6521,7 @@ mt%0 %1 mf%1 %0 nop" - [(set_attr "type" "*,load,store,fp,fp,vecsimple,integer,fpload,fpload,fpstore,fpstore,fpload,fpstore,mftgpr,mffgpr,mtjmpr,mfjmpr,*") + [(set_attr "type" "*,load,store,fp,fp,vecsimple,integer,fpload,fpload,fpstore,fpstore,fpload,fpstore,mffgpr,mftgpr,mtjmpr,mfjmpr,*") (set_attr "length" "4")]) (define_insn "*mov_softfloat" @@ -13524,7 +13524,7 @@ mfvsrd %0,%x1 stxsdx %x1,%y0 xxlor %x0,%x1,%x1" - [(set_attr "type" "mftgpr,vecsimple,fpstore")]) + [(set_attr "type" "mftgpr,fpstore,vecsimple")]) (define_insn "*ieee128_mfvsrd_32bit" @@ -13535,7 +13535,7 @@ "@ stxsdx %x1,%y0 xxlor %x0,%x1,%x1" - [(set_attr "type" "vecsimple,fpstore")]) + [(set_attr "type" "fpstore,vecsimple")]) (define_insn "*ieee128_mfvsrwz" [(set (match_operand:SI 0 "reg_or_indexed_operand" "=r,Z") -- 2.47.3