From 5edc74320bf0761469ea90c70fb876fb88680ec8 Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 14 Mar 2013 20:56:35 +0530 Subject: [PATCH] spi: zynq: Minor code cleanups on qspips - Remove few unnecessary comment lines - Remove few unnecessary reg_base args - Add comments - Remove XPSS_QSPI_LIN_BASEADDR Signed-off-by: Jagannadha Sutradharudu Teki --- drivers/spi/zynq_qspips.c | 14 +++++--------- include/configs/zynq_common.h | 1 - 2 files changed, 5 insertions(+), 10 deletions(-) diff --git a/drivers/spi/zynq_qspips.c b/drivers/spi/zynq_qspips.c index 689793a7c91..46a2b62af42 100644 --- a/drivers/spi/zynq_qspips.c +++ b/drivers/spi/zynq_qspips.c @@ -223,7 +223,6 @@ static struct xqspips_inst_format flash_inst[] = { /* * xqspips_init_hw - Initialize the hardware - * @regs_base: Base address of QSPI controller * @is_dual: Indicates whether dual memories are used * @cs: Indicates which chip select is used in dual stacked * @@ -243,8 +242,7 @@ static struct xqspips_inst_format flash_inst[] = { * - Set the little endian mode of TX FIFO and * - Enable the QSPI controller */ -static void xqspips_init_hw(void __iomem *regs_base, int is_dual, - unsigned int cs) +static void xqspips_init_hw(int is_dual, unsigned int cs) { u32 config_reg; @@ -514,7 +512,7 @@ static void xqspips_fill_tx_fifo(struct xqspips *xqspi) } /* - * xqspips_irq - Interrupt service routine of the QSPI controller + * xqspips_irq_poll - Interrupt service routine of the QSPI controller * @xqspi: Pointer to the xqspips structure * * This function handles TX empty and Mode Fault interrupts only. @@ -524,7 +522,8 @@ static void xqspips_fill_tx_fifo(struct xqspips *xqspi) * the SPI subsystem will identify the error as the remaining bytes to be * transferred is non-zero. * - * returns: IRQ_HANDLED always + * returns: 0 for poll timeout + * 1 transfer operation complete */ static int xqspips_irq_poll(struct xqspips *xqspi) { @@ -802,10 +801,7 @@ static int xqspips_transfer(struct spi_device *qspi, * * function will return -1, if there is no MIO configuration for * qspi flash. - * - * @regs_base: base address of SLCR */ - static int xqspips_check_is_dual_flash(void) { int is_dual = MODE_UNKNOWN; @@ -974,7 +970,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, return NULL; } - xqspips_init_hw((void *)XPSS_QSPI_BASEADDR, is_dual, cs); + xqspips_init_hw(is_dual, cs); pspi = malloc(sizeof(struct zynq_spi_slave)); if (!pspi) { diff --git a/include/configs/zynq_common.h b/include/configs/zynq_common.h index 768572d478e..9e53b680fcb 100644 --- a/include/configs/zynq_common.h +++ b/include/configs/zynq_common.h @@ -295,6 +295,5 @@ #define XPSS_NAND_BASEADDR 0xE1000000 #define XPSS_CRTL_PARPORT_BASEADDR 0xE000E000 #define SD_BASEADDR 0xE0100000 -#define XPSS_QSPI_LIN_BASEADDR 0xFC000000 #endif /* __CONFIG_ZYNQ_COMMON_H */ -- 2.47.3