From 612bb14d4a2f4db774bcc8dccd296325facaf075 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Thu, 12 Dec 2024 13:45:58 +0100 Subject: [PATCH] 5.15-stable patches added patches: drm-amd-display-correct-the-defined-value-for-amdgpu_dmub_notification_max.patch drm-amdgpu-rework-resume-handling-for-display-v2.patch --- ...lue-for-amdgpu_dmub_notification_max.patch | 36 ++++++ ...ework-resume-handling-for-display-v2.patch | 116 ++++++++++++++++++ queue-5.15/series | 2 + 3 files changed, 154 insertions(+) create mode 100644 queue-5.15/drm-amd-display-correct-the-defined-value-for-amdgpu_dmub_notification_max.patch create mode 100644 queue-5.15/drm-amdgpu-rework-resume-handling-for-display-v2.patch diff --git a/queue-5.15/drm-amd-display-correct-the-defined-value-for-amdgpu_dmub_notification_max.patch b/queue-5.15/drm-amd-display-correct-the-defined-value-for-amdgpu_dmub_notification_max.patch new file mode 100644 index 00000000000..5dfe903b971 --- /dev/null +++ b/queue-5.15/drm-amd-display-correct-the-defined-value-for-amdgpu_dmub_notification_max.patch @@ -0,0 +1,36 @@ +From ad28d7c3d989fc5689581664653879d664da76f0 Mon Sep 17 00:00:00 2001 +From: Wayne Lin +Date: Mon, 27 May 2024 15:33:48 +0800 +Subject: drm/amd/display: Correct the defined value for AMDGPU_DMUB_NOTIFICATION_MAX + +From: Wayne Lin + +commit ad28d7c3d989fc5689581664653879d664da76f0 upstream. + +[Why & How] +It actually exposes '6' types in enum dmub_notification_type. Not 5. Using smaller +number to create array dmub_callback & dmub_thread_offload has potential to access +item out of array bound. Fix it. + +Reviewed-by: Jerry Zuo +Acked-by: Zaeem Mohamed +Signed-off-by: Wayne Lin +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Signed-off-by: Guocai He +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +@@ -48,7 +48,7 @@ + + #define AMDGPU_DM_MAX_NUM_EDP 2 + +-#define AMDGPU_DMUB_NOTIFICATION_MAX 5 ++#define AMDGPU_DMUB_NOTIFICATION_MAX 6 + /* + #include "include/amdgpu_dal_power_if.h" + #include "amdgpu_dm_irq.h" diff --git a/queue-5.15/drm-amdgpu-rework-resume-handling-for-display-v2.patch b/queue-5.15/drm-amdgpu-rework-resume-handling-for-display-v2.patch new file mode 100644 index 00000000000..2557b601ed5 --- /dev/null +++ b/queue-5.15/drm-amdgpu-rework-resume-handling-for-display-v2.patch @@ -0,0 +1,116 @@ +From 73dae652dcac776296890da215ee7dec357a1032 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Mon, 25 Nov 2024 13:59:09 -0500 +Subject: drm/amdgpu: rework resume handling for display (v2) +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Alex Deucher + +commit 73dae652dcac776296890da215ee7dec357a1032 upstream. + +Split resume into a 3rd step to handle displays when DCC is +enabled on DCN 4.0.1. Move display after the buffer funcs +have been re-enabled so that the GPU will do the move and +properly set the DCC metadata for DCN. + +v2: fix fence irq resume ordering + +Reviewed-by: Christian König +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org # 6.11.x +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 45 +++++++++++++++++++++++++++-- + 1 file changed, 43 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +@@ -3197,7 +3197,7 @@ static int amdgpu_device_ip_resume_phase + * + * @adev: amdgpu_device pointer + * +- * First resume function for hardware IPs. The list of all the hardware ++ * Second resume function for hardware IPs. The list of all the hardware + * IPs that make up the asic is walked and the resume callbacks are run for + * all blocks except COMMON, GMC, and IH. resume puts the hardware into a + * functional state after a suspend and updates the software state as +@@ -3215,6 +3215,7 @@ static int amdgpu_device_ip_resume_phase + if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || + adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || + adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH || ++ adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE || + adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) + continue; + r = adev->ip_blocks[i].version->funcs->resume(adev); +@@ -3239,6 +3240,36 @@ static int amdgpu_device_ip_resume_phase + } + + /** ++ * amdgpu_device_ip_resume_phase3 - run resume for hardware IPs ++ * ++ * @adev: amdgpu_device pointer ++ * ++ * Third resume function for hardware IPs. The list of all the hardware ++ * IPs that make up the asic is walked and the resume callbacks are run for ++ * all DCE. resume puts the hardware into a functional state after a suspend ++ * and updates the software state as necessary. This function is also used ++ * for restoring the GPU after a GPU reset. ++ * ++ * Returns 0 on success, negative error code on failure. ++ */ ++static int amdgpu_device_ip_resume_phase3(struct amdgpu_device *adev) ++{ ++ int i, r; ++ ++ for (i = 0; i < adev->num_ip_blocks; i++) { ++ if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw) ++ continue; ++ if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) { ++ r = adev->ip_blocks[i].version->funcs->resume(adev); ++ if (r) ++ return r; ++ } ++ } ++ ++ return 0; ++} ++ ++/** + * amdgpu_device_ip_resume - run resume for hardware IPs + * + * @adev: amdgpu_device pointer +@@ -3268,6 +3299,13 @@ static int amdgpu_device_ip_resume(struc + + r = amdgpu_device_ip_resume_phase2(adev); + ++ if (r) ++ return r; ++ ++ amdgpu_fence_driver_hw_init(adev); ++ ++ r = amdgpu_device_ip_resume_phase3(adev); ++ + return r; + } + +@@ -4160,7 +4198,6 @@ int amdgpu_device_resume(struct drm_devi + dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r); + return r; + } +- amdgpu_fence_driver_hw_init(adev); + + r = amdgpu_device_ip_late_init(adev); + if (r) +@@ -4806,6 +4843,10 @@ int amdgpu_do_asic_reset(struct list_hea + if (r) + goto out; + ++ r = amdgpu_device_ip_resume_phase3(tmp_adev); ++ if (r) ++ goto out; ++ + if (vram_lost) + amdgpu_device_fill_reset_magic(tmp_adev); + diff --git a/queue-5.15/series b/queue-5.15/series index afc3d9a732d..c931f5eae43 100644 --- a/queue-5.15/series +++ b/queue-5.15/series @@ -563,3 +563,5 @@ arm64-sve-discard-stale-cpu-state-when-handling-sve-traps.patch arm64-smccc-remove-broken-support-for-smcccv1.3-sve-discard-hint.patch bluetooth-l2cap-fix-uaf-in-l2cap_connect.patch net-dsa-microchip-correct-ksz8795-static-mac-table-access.patch +drm-amd-display-correct-the-defined-value-for-amdgpu_dmub_notification_max.patch +drm-amdgpu-rework-resume-handling-for-display-v2.patch -- 2.47.3