From 67b98792407f41b369ecd799a4928db24dbb2058 Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:58:11 +0530 Subject: [PATCH] arm64: dts: ti: k3-am64-phycore-som: Add missing cfg for TI IPC Firmware The k3-am64-phycore SoM enables all R5F and M4F remote processors. Reserve the MAIN domain timers that are used by R5F remote processors for ticks to avoid rproc crashes. This config aligns with other AM64 boards and can be refactored out later. Signed-off-by: Beleswar Padhi Tested-by: Wadim Egorov Link: https://patch.msgid.link/20250908142826.1828676-20-b-padhi@ti.com Signed-off-by: Nishanth Menon --- .../boot/dts/ti/k3-am64-phycore-som.dtsi | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi index ba425b125d63b..5e0c82960a6c6 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi @@ -275,6 +275,30 @@ }; }; +/* main_timer8 is used by r5f0-0 */ +&main_timer8 { + status = "reserved"; +}; + +/* main_timer9 is used by r5f0-1 */ +&main_timer9 { + status = "reserved"; +}; + +/* main_timer10 is used by r5f1-0 */ +&main_timer10 { + status = "reserved"; +}; + +/* main_timer11 is used by r5f1-1 */ +&main_timer11 { + status = "reserved"; +}; + +&main_r5fss0 { + status = "okay"; +}; + &main_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; -- 2.47.3