From 6800aaee5f2f325aae2178a30d1dd0c59df8d113 Mon Sep 17 00:00:00 2001 From: Bill Schmidt Date: Wed, 20 Aug 2014 16:59:45 +0000 Subject: [PATCH] rs6000-c.c (rs6000_cpu_cpp_builtins): Provide builtin define __VEC_ELEMENT_REG_ORDER__. 2014-08-20 Bill Schmidt * config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Provide builtin define __VEC_ELEMENT_REG_ORDER__. From-SVN: r214236 --- gcc/ChangeLog | 5 +++++ gcc/config/rs6000/rs6000-c.c | 6 ++++++ 2 files changed, 11 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8f9b113e4dab..7742b84a7836 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2014-08-20 Bill Schmidt + + * config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Provide + builtin define __VEC_ELEMENT_REG_ORDER__. + 2014-08-20 Martin Jambor Wei Mi diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index 2b9cf7a0b383..40a17e26418f 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -497,6 +497,12 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfile) break; } + /* Vector element order. */ + if (BYTES_BIG_ENDIAN || (rs6000_altivec_element_order == 2)) + builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_BIG_ENDIAN__"); + else + builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_LITTLE_ENDIAN__"); + /* Let the compiled code know if 'f' class registers will not be available. */ if (TARGET_SOFT_FLOAT || !TARGET_FPRS) builtin_define ("__NO_FPRS__"); -- 2.47.3