From 6bc04dc1d6067de7d351c7a3a41ee63ce6fe143b Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Fri, 15 Mar 2019 17:46:46 +0530 Subject: [PATCH] net: phy: ti: Add support for 6-wire mode in SGMII configuration This patch adds 6 wire mode supports which enables SGMII clock to MAC from phy. The drivers gets this 6 wire mode info by reading the property "ti,6-wire-mode" from DT. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- doc/device-tree-bindings/net/ti,dp83867.txt | 1 + drivers/net/phy/ti.c | 13 +++++++++++++ 2 files changed, 14 insertions(+) diff --git a/doc/device-tree-bindings/net/ti,dp83867.txt b/doc/device-tree-bindings/net/ti,dp83867.txt index 034146f5f80..739a944ee9d 100644 --- a/doc/device-tree-bindings/net/ti,dp83867.txt +++ b/doc/device-tree-bindings/net/ti,dp83867.txt @@ -14,6 +14,7 @@ Required properties: TX/RX lanes. - ti,clk-output-sel - Clock output select - see dt-bindings/net/ti-dp83867.h for applicable values + - ti,6-wire-mode - Indicates that it enables SGMII differntial clock to MAC Default child nodes are standard Ethernet PHY device nodes as described in doc/devicetree/bindings/net/ethernet.txt diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c index 6db6edd0d0c..16702bc4d05 100644 --- a/drivers/net/phy/ti.c +++ b/drivers/net/phy/ti.c @@ -27,6 +27,7 @@ #define DP83867_STRAP_STS1 0x006E #define DP83867_RGMIIDCTL 0x0086 #define DP83867_IO_MUX_CFG 0x0170 +#define DP83867_SGMIITYPE 0x00D3 #define DP83867_SW_RESET BIT(15) #define DP83867_SW_RESTART BIT(14) @@ -100,6 +101,8 @@ /* CFG4 bits */ #define DP83867_CFG4_PORT_MIRROR_EN BIT(0) +#define DP83867_SGMIICLK_EN 0x4000 + enum { DP83867_PORT_MIRRORING_KEEP, DP83867_PORT_MIRRORING_EN, @@ -114,6 +117,7 @@ struct dp83867_private { bool rxctrl_strap_quirk; int port_mirroring; int clk_output_sel; + bool wiremode_6; }; /** @@ -254,6 +258,11 @@ static int dp83867_of_init(struct phy_device *phydev) if (ofnode_read_bool(node, "enet-phy-lane-no-swap")) dp83867->port_mirroring = DP83867_PORT_MIRRORING_DIS; + /* + * 6-wire mode enables differential SGMII clock to MAC + */ + if (dev_read_bool(phydev->dev, "ti,6-wire-mode")) + dp83867->wiremode_6 = true; /* Clock output selection if muxing property is set */ if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) { @@ -342,6 +351,10 @@ static int dp83867_config(struct phy_device *phydev) } } else if (phy_interface_is_sgmii(phydev)) { + if (dp83867->wiremode_6) + phy_write_mmd_indirect(phydev, DP83867_SGMIITYPE, + DP83867_DEVADDR, phydev->addr, + DP83867_SGMIICLK_EN); phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000)); -- 2.47.3