From 6fdcb1013f13f87cdebd94ab8aa2f8ea2c644a33 Mon Sep 17 00:00:00 2001 From: Rahul T R Date: Fri, 5 Sep 2025 15:13:25 +0530 Subject: [PATCH] arm64: dts: ti: k3-j721e-main: Add DSI and DPHY-TX TI's J721E SoC supports a DPI to DSI video signal conversion bridge on it's platform bus. The IP is from Cadence, and it has a custom TI wrapper around it to facilitate integration. This IP takes the DPI video signals from DSS and alongwith the DPHY IP, it transmits DSI video signals out of the SoC. Add support for DSI bridge and the DPHY-TX. Signed-off-by: Rahul T R Signed-off-by: Jayesh Choudhary Signed-off-by: Harikrishna Shenoy Link: https://patch.msgid.link/20250905094325.472473-1-h-shenoy@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 39 +++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index e748f704e3b61..d5fd30a01032f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1887,6 +1887,45 @@ }; }; + dphy2: phy@4480000 { + compatible = "ti,j721e-dphy"; + reg = <0x00 0x04480000 0x00 0x1000>; + clocks = <&k3_clks 296 1>, <&k3_clks 296 3>; + clock-names = "psm", "pll_ref"; + #phy-cells = <0>; + power-domains = <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 296 3>; + assigned-clock-parents = <&k3_clks 296 4>; + assigned-clock-rates = <19200000>; + status = "disabled"; + }; + + dsi0: dsi@4800000 { + compatible = "ti,j721e-dsi"; + reg = <0x00 0x04800000 0x00 0x100000>, <0x00 0x04710000 0x00 0x100>; + clocks = <&k3_clks 150 1>, <&k3_clks 150 5>; + clock-names = "dsi_p_clk", "dsi_sys_clk"; + power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>; + interrupt-parent = <&gic500>; + interrupts = ; + phys = <&dphy2>; + phy-names = "dphy"; + status = "disabled"; + + dsi0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + }; + }; + dss: dss@4a00000 { compatible = "ti,j721e-dss"; reg = -- 2.47.3