From 7164791280d625d34bdf2e946a116e4b11c03391 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Sun, 16 Oct 2022 12:30:28 +0200 Subject: [PATCH] 6.0-stable patches added patches: arm64-topology-move-store_cpu_topology-to-shared-code.patch --- ...ve-store_cpu_topology-to-shared-code.patch | 106 ++++++++++++++++++ queue-6.0/series | 1 + 2 files changed, 107 insertions(+) create mode 100644 queue-6.0/arm64-topology-move-store_cpu_topology-to-shared-code.patch diff --git a/queue-6.0/arm64-topology-move-store_cpu_topology-to-shared-code.patch b/queue-6.0/arm64-topology-move-store_cpu_topology-to-shared-code.patch new file mode 100644 index 00000000000..48ec5e37b87 --- /dev/null +++ b/queue-6.0/arm64-topology-move-store_cpu_topology-to-shared-code.patch @@ -0,0 +1,106 @@ +From 456797da792fa7cbf6698febf275fe9b36691f78 Mon Sep 17 00:00:00 2001 +From: Conor Dooley +Date: Fri, 15 Jul 2022 18:51:55 +0100 +Subject: arm64: topology: move store_cpu_topology() to shared code + +From: Conor Dooley + +commit 456797da792fa7cbf6698febf275fe9b36691f78 upstream. + +arm64's method of defining a default cpu topology requires only minimal +changes to apply to RISC-V also. The current arm64 implementation exits +early in a uniprocessor configuration by reading MPIDR & claiming that +uniprocessor can rely on the default values. + +This is appears to be a hangover from prior to '3102bc0e6ac7 ("arm64: +topology: Stop using MPIDR for topology information")', because the +current code just assigns default values for multiprocessor systems. + +With the MPIDR references removed, store_cpu_topolgy() can be moved to +the common arch_topology code. + +Reviewed-by: Sudeep Holla +Acked-by: Catalin Marinas +Reviewed-by: Atish Patra +Signed-off-by: Conor Dooley +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/kernel/topology.c | 40 ---------------------------------------- + drivers/base/arch_topology.c | 19 +++++++++++++++++++ + 2 files changed, 19 insertions(+), 40 deletions(-) + +--- a/arch/arm64/kernel/topology.c ++++ b/arch/arm64/kernel/topology.c +@@ -22,46 +22,6 @@ + #include + #include + +-void store_cpu_topology(unsigned int cpuid) +-{ +- struct cpu_topology *cpuid_topo = &cpu_topology[cpuid]; +- u64 mpidr; +- +- if (cpuid_topo->package_id != -1) +- goto topology_populated; +- +- mpidr = read_cpuid_mpidr(); +- +- /* Uniprocessor systems can rely on default topology values */ +- if (mpidr & MPIDR_UP_BITMASK) +- return; +- +- /* +- * This would be the place to create cpu topology based on MPIDR. +- * +- * However, it cannot be trusted to depict the actual topology; some +- * pieces of the architecture enforce an artificial cap on Aff0 values +- * (e.g. GICv3's ICC_SGI1R_EL1 limits it to 15), leading to an +- * artificial cycling of Aff1, Aff2 and Aff3 values. IOW, these end up +- * having absolutely no relationship to the actual underlying system +- * topology, and cannot be reasonably used as core / package ID. +- * +- * If the MT bit is set, Aff0 *could* be used to define a thread ID, but +- * we still wouldn't be able to obtain a sane core ID. This means we +- * need to entirely ignore MPIDR for any topology deduction. +- */ +- cpuid_topo->thread_id = -1; +- cpuid_topo->core_id = cpuid; +- cpuid_topo->package_id = cpu_to_node(cpuid); +- +- pr_debug("CPU%u: cluster %d core %d thread %d mpidr %#016llx\n", +- cpuid, cpuid_topo->package_id, cpuid_topo->core_id, +- cpuid_topo->thread_id, mpidr); +- +-topology_populated: +- update_siblings_masks(cpuid); +-} +- + #ifdef CONFIG_ACPI + static bool __init acpi_cpu_is_threaded(int cpu) + { +--- a/drivers/base/arch_topology.c ++++ b/drivers/base/arch_topology.c +@@ -841,4 +841,23 @@ void __init init_cpu_topology(void) + return; + } + } ++ ++void store_cpu_topology(unsigned int cpuid) ++{ ++ struct cpu_topology *cpuid_topo = &cpu_topology[cpuid]; ++ ++ if (cpuid_topo->package_id != -1) ++ goto topology_populated; ++ ++ cpuid_topo->thread_id = -1; ++ cpuid_topo->core_id = cpuid; ++ cpuid_topo->package_id = cpu_to_node(cpuid); ++ ++ pr_debug("CPU%u: package %d core %d thread %d\n", ++ cpuid, cpuid_topo->package_id, cpuid_topo->core_id, ++ cpuid_topo->thread_id); ++ ++topology_populated: ++ update_siblings_masks(cpuid); ++} + #endif diff --git a/queue-6.0/series b/queue-6.0/series index 66bf0a00e94..86310bae632 100644 --- a/queue-6.0/series +++ b/queue-6.0/series @@ -52,6 +52,7 @@ asoc-wcd934x-fix-order-of-slimbus-unprepare-disable.patch hwmon-gsc-hwmon-call-of_node_get-before-of_find_xxx-api.patch net-thunderbolt-enable-dma-paths-only-after-rings-are-enabled.patch regulator-qcom_rpm-fix-circular-deferral-regression.patch +arm64-topology-move-store_cpu_topology-to-shared-code.patch riscv-topology-fix-default-topology-reporting.patch risc-v-re-enable-counter-access-from-userspace.patch risc-v-make-port-i-o-string-accessors-actually-work.patch -- 2.47.3