From 72ac76be3abe9ed981037fe35da0c15bec5611ef Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Sun, 15 Jun 2003 07:51:35 +0000 Subject: [PATCH] alpha.md: Follow spelling conventions. * config/alpha/alpha.md: Follow spelling conventions. * config/arm/arm.c: Likewise. * config/arm/arm.h: Likewise. * config/arm/arm.md: Likewise. * config/arm/crtn.asm: Likewise. * config/m32r/m32r.c: Likewise. * config/m32r/m32r.md: Likewise. * config/rs6000/rs6000.c: Likewise. From-SVN: r67970 --- gcc/ChangeLog | 11 +++++++++++ gcc/config/alpha/alpha.md | 2 +- gcc/config/arm/arm.c | 4 ++-- gcc/config/arm/arm.h | 2 +- gcc/config/arm/arm.md | 2 +- gcc/config/arm/crtn.asm | 2 +- gcc/config/m32r/m32r.c | 2 +- gcc/config/m32r/m32r.md | 2 +- gcc/config/rs6000/rs6000.c | 2 +- 9 files changed, 20 insertions(+), 9 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e7448cd424e9..8bd85fa99d63 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2003-06-15 Kazu Hirata + + * config/alpha/alpha.md: Follow spelling conventions. + * config/arm/arm.c: Likewise. + * config/arm/arm.h: Likewise. + * config/arm/arm.md: Likewise. + * config/arm/crtn.asm: Likewise. + * config/m32r/m32r.c: Likewise. + * config/m32r/m32r.md: Likewise. + * config/rs6000/rs6000.c: Likewise. + 2003-06-15 Richard Henderson * config/alpha/alpha.c (alpha_output_mi_thunk_osf): Call diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index 8ae7aca27472..9ddeb9e7df15 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -5273,7 +5273,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none" ;; Split the load of an address into a four-insn sequence on Unicos/Mk. ;; Always generate a REG_EQUAL note for the last instruction to facilitate -;; optimisations. If the symbolic operand is a label_ref, generate REG_LABEL +;; optimizations. If the symbolic operand is a label_ref, generate REG_LABEL ;; notes and update LABEL_NUSES because this is not done automatically. ;; Labels may be incorrectly deleted if we don't do this. ;; diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 4a42f0b998e3..cd2b149ea3fb 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -5642,7 +5642,7 @@ arm_reload_in_hi (rtx *operands) 0)))); } -/* Handle storing a half-word to memory during reload by synthesising as two +/* Handle storing a half-word to memory during reload by synthesizing as two byte stores. Take care not to clobber the input values until after we have moved them somewhere safe. This code assumes that if the DImode scratch in operands[2] overlaps either the input value or output address @@ -7740,7 +7740,7 @@ arm_compute_save_reg_mask (void) it. If we are pushing other registers onto the stack however, we can save an instruction in the epilogue by pushing the link register now and then popping it back into the PC. This incurs extra memory - accesses though, so we only do it when optimising for size, and only + accesses though, so we only do it when optimizing for size, and only if we know that we will not need a fancy return sequence. */ if (regs_ever_live [LR_REGNUM] || (save_reg_mask diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 65e816608d90..c923e01f2c8e 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -2345,7 +2345,7 @@ extern int making_const_table; #endif /* Only perform branch elimination (by making instructions conditional) if - we're optimising. Otherwise it's of no use anyway. */ + we're optimizing. Otherwise it's of no use anyway. */ #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ if (TARGET_ARM && optimize) \ arm_final_prescan_insn (INSN); \ diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 2d231c1c0453..d03c193aba9c 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -509,7 +509,7 @@ " ) -; If there is a scratch available, this will be faster than synthesising the +; If there is a scratch available, this will be faster than synthesizing the ; addition. (define_peephole2 [(match_scratch:SI 3 "r") diff --git a/gcc/config/arm/crtn.asm b/gcc/config/arm/crtn.asm index 2f4b5422eb24..9ad75e3f2aab 100644 --- a/gcc/config/arm/crtn.asm +++ b/gcc/config/arm/crtn.asm @@ -39,7 +39,7 @@ # in crti.asm. If you change this macro you must also change # that macro match. # - # Note - we do not try any fancy optimisations of the return + # Note - we do not try any fancy optimizations of the return # sequences here, it is just not worth it. Instead keep things # simple. Restore all the save resgisters, including the link # register and then perform the correct function return instruction. diff --git a/gcc/config/m32r/m32r.c b/gcc/config/m32r/m32r.c index 8d42306b1f8c..55b7cf71d80b 100644 --- a/gcc/config/m32r/m32r.c +++ b/gcc/config/m32r/m32r.c @@ -1002,7 +1002,7 @@ large_insn_p (op, mode) return get_attr_length (op) != 2; } -/* Return non-zero if TYPE must be passed or returned in memory. +/* Return nonzero if TYPE must be passed or returned in memory. The m32r treats both directions the same so we handle both directions in this function. */ diff --git a/gcc/config/m32r/m32r.md b/gcc/config/m32r/m32r.md index e4febd77fdd6..7dad4e0f8f58 100644 --- a/gcc/config/m32r/m32r.md +++ b/gcc/config/m32r/m32r.md @@ -2540,7 +2540,7 @@ ;; Simialr code is produced for the subtract expression. With this ;; peephole the redundant move is eliminated. ;; -;; This optimisation only works if PRESERVE_DEATH_INFO_REGNO_P is +;; This optimization only works if PRESERVE_DEATH_INFO_REGNO_P is ;; defined in m32r.h (define_peephole diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index d3d92fad5836..8bd2a0cb78bc 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -1534,7 +1534,7 @@ easy_fp_constant (op, mode) abort (); } -/* Return non zero if all elements of a vector have the same value. */ +/* Return nonzero if all elements of a vector have the same value. */ static int easy_vector_same (op, mode) -- 2.47.3