From 77b89235e4aa9ec2841eedb4d83f52233200f471 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 8 May 2013 15:37:28 +0200 Subject: [PATCH] zynq: slcr: Wait 100ms till clk is properly setup If you don't wait you will loose the first sent packet even all bits in emacps are correctly setup. Signed-off-by: Michal Simek --- arch/arm/cpu/armv7/zynq/slcr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index e5f710d4e25..cfd66098620 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -166,7 +166,7 @@ void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk) /* Configure GEM_RCLK_CTRL */ writel(rclk, &slcr_base->gem0_rclk_ctrl); } - + udelay(100000); out: zynq_slcr_lock(); } -- 2.47.3