From 7a55f9202b3050af78b1205758f3427ec980497c Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@xilinx.com>
Date: Mon, 1 Feb 2016 15:05:58 +0100
Subject: [PATCH] ARM64: zynqmp: Add support for chip ID detection

Chip ID needs to be known for loading bitstream because
U-Boot checks ID from bitstream header in BIT format.
BIN format is completely unchecked.

SMC calls are disabled because code depends on ATF changes which are not
in release version.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
 board/xilinx/zynqmp/zynqmp.c | 97 ++++++++++++++++++++++++++++++++++--
 include/zynqmppl.h           |  3 +-
 2 files changed, 95 insertions(+), 5 deletions(-)

diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 4d6c8fcad6a..157f1a5124f 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -21,16 +21,105 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
+
+static const struct {
+	uint32_t id;
+	char *name;
+} zynqmp_devices[] = {
+	{
+		.id = 0x10,
+		.name = "3eg",
+	},
+	{
+		.id = 0x11,
+		.name = "2eg",
+	},
+	{
+		.id = 0x20,
+		.name = "5ev",
+	},
+	{
+		.id = 0x21,
+		.name = "4ev",
+	},
+	{
+		.id = 0x30,
+		.name = "7ev",
+	},
+	{
+		.id = 0x38,
+		.name = "9eg",
+	},
+	{
+		.id = 0x39,
+		.name = "6eg",
+	},
+	{
+		.id = 0x40,
+		.name = "11eg",
+	},
+	{
+		.id = 0x50,
+		.name = "15eg",
+	},
+	{
+		.id = 0x58,
+		.name = "19eg",
+	},
+	{
+		.id = 0x59,
+		.name = "17eg",
+	},
+};
+
+static int chip_id(void)
+{
+	struct pt_regs regs;
+	regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
+	regs.regs[1] = 0;
+	regs.regs[2] = 0;
+	regs.regs[3] = 0;
+
+/* Uncomment this when you have ATF version which supports this SMC call */
+#if 0
+	smc_call(&regs);
+#endif
+
+	return regs.regs[0];
+}
+
+static char *zynqmp_get_silicon_idcode_name(void)
+{
+	uint32_t i, id;
+
+	id = chip_id();
+	for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
+		if (zynqmp_devices[i].id == id) {
+			return zynqmp_devices[i].name;
+		}
+	}
+	return "unknown";
+}
 #endif
 
+#define ZYNQMP_VERSION_SIZE	9
+
 int board_init(void)
 {
 	printf("EL Level:\tEL%d\n", current_el());
 
-#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
-	fpga_init();
-	/* FIXME FPGA size/id will be handled via SMCs */
-	fpga_add(fpga_xilinx, &zynqmppl);
+#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && !defined(CONFIG_SPL_BUILD) || \
+    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
+	if (current_el() != 3) {
+		static char version[ZYNQMP_VERSION_SIZE];
+
+		strncat(version, "xczu", ZYNQMP_VERSION_SIZE);
+		zynqmppl.name = strncat(version, zynqmp_get_silicon_idcode_name(),
+					ZYNQMP_VERSION_SIZE);
+		printf("Chip ID:\t%s\n", zynqmppl.name);
+		fpga_init();
+		fpga_add(fpga_xilinx, &zynqmppl);
+	}
 #endif
 
 	return 0;
diff --git a/include/zynqmppl.h b/include/zynqmppl.h
index 67bf7c4a355..e14a9dc0696 100644
--- a/include/zynqmppl.h
+++ b/include/zynqmppl.h
@@ -13,10 +13,11 @@
 #define ZYNQMP_SIP_SVC_CSU_DMA_INFO		0x82002004
 #define ZYNQMP_SIP_SVC_CSU_DMA_LOAD		0x82002005
 #define ZYNQMP_SIP_SVC_CSU_DMA_DUMP		0x82002006
+#define ZYNQMP_SIP_SVC_CSU_DMA_CHIPID		0x82002007
 
 extern struct xilinx_fpga_op zynqmp_op;
 
 #define XILINX_ZYNQMP_DESC \
-{ xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op, "xczu9eg" }
+{ xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op }
 
 #endif /* _ZYNQMPPL_H_ */
-- 
2.47.3