From 7a90966de5d9d7a590ebb5ce225c1290767b6dfb Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Mon, 3 Jan 2022 10:40:04 +0100 Subject: [PATCH] 5.15-stable patches added patches: drm-amd-display-changed-pipe-split-policy-to-allow-for-multi-display-pipe-split.patch drm-amdgpu-add-support-for-ip-discovery-gc_info-table-v2.patch drm-amdgpu-when-the-vcn-1.0-block-is-suspended-powergating-is-explicitly-enabled.patch drm-nouveau-wait-for-the-exclusive-fence-after-the-shared-ones-v2.patch nfc-uapi-use-kernel-size_t-to-fix-user-space-builds.patch uapi-fix-linux-nfc.h-userspace-compilation-errors.patch --- ...o-allow-for-multi-display-pipe-split.patch | 119 ++++++++++++ ...rt-for-ip-discovery-gc_info-table-v2.patch | 175 ++++++++++++++++++ ...ed-powergating-is-explicitly-enabled.patch | 65 +++++++ ...usive-fence-after-the-shared-ones-v2.patch | 91 +++++++++ ...rnel-size_t-to-fix-user-space-builds.patch | 39 ++++ queue-5.15/series | 6 + ...x-nfc.h-userspace-compilation-errors.patch | 48 +++++ 7 files changed, 543 insertions(+) create mode 100644 queue-5.15/drm-amd-display-changed-pipe-split-policy-to-allow-for-multi-display-pipe-split.patch create mode 100644 queue-5.15/drm-amdgpu-add-support-for-ip-discovery-gc_info-table-v2.patch create mode 100644 queue-5.15/drm-amdgpu-when-the-vcn-1.0-block-is-suspended-powergating-is-explicitly-enabled.patch create mode 100644 queue-5.15/drm-nouveau-wait-for-the-exclusive-fence-after-the-shared-ones-v2.patch create mode 100644 queue-5.15/nfc-uapi-use-kernel-size_t-to-fix-user-space-builds.patch create mode 100644 queue-5.15/uapi-fix-linux-nfc.h-userspace-compilation-errors.patch diff --git a/queue-5.15/drm-amd-display-changed-pipe-split-policy-to-allow-for-multi-display-pipe-split.patch b/queue-5.15/drm-amd-display-changed-pipe-split-policy-to-allow-for-multi-display-pipe-split.patch new file mode 100644 index 00000000000..6eaafba63df --- /dev/null +++ b/queue-5.15/drm-amd-display-changed-pipe-split-policy-to-allow-for-multi-display-pipe-split.patch @@ -0,0 +1,119 @@ +From ee2698cf79cc759a397c61086c758d4cc85938bf Mon Sep 17 00:00:00 2001 +From: Angus Wang +Date: Thu, 9 Dec 2021 17:27:01 -0500 +Subject: drm/amd/display: Changed pipe split policy to allow for multi-display pipe split + +From: Angus Wang + +commit ee2698cf79cc759a397c61086c758d4cc85938bf upstream. + +[WHY] +Current implementation of pipe split policy prevents pipe split with +multiple displays connected, which caused the MCLK speed to be stuck at +max + +[HOW] +Changed the pipe split policies so that pipe split is allowed for +multi-display configurations + +Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1522 +Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1709 +Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1655 +Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1403 + +Note this is a backport of this commit from amdgpu drm-next for 5.16. + +Tested-by: Daniel Wheeler +Reviewed-by: Aric Cyr +Acked-by: Rodrigo Siqueira +Signed-off-by: Angus Wang +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +- + drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +- + drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c | 2 +- + drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c | 2 +- + drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c | 2 +- + drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c | 2 +- + drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 2 +- + 7 files changed, 7 insertions(+), 7 deletions(-) + +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +@@ -1067,7 +1067,7 @@ static const struct dc_debug_options deb + .timing_trace = false, + .clock_trace = true, + .disable_pplib_clock_request = true, +- .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, ++ .pipe_split_policy = MPC_SPLIT_DYNAMIC, + .force_single_disp_pipe_split = false, + .disable_dcc = DCC_ENABLE, + .vsr_support = true, +--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +@@ -874,7 +874,7 @@ static const struct dc_debug_options deb + .clock_trace = true, + .disable_pplib_clock_request = true, + .min_disp_clk_khz = 100000, +- .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, ++ .pipe_split_policy = MPC_SPLIT_DYNAMIC, + .force_single_disp_pipe_split = false, + .disable_dcc = DCC_ENABLE, + .vsr_support = true, +--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c +@@ -840,7 +840,7 @@ static const struct dc_debug_options deb + .timing_trace = false, + .clock_trace = true, + .disable_pplib_clock_request = true, +- .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, ++ .pipe_split_policy = MPC_SPLIT_DYNAMIC, + .force_single_disp_pipe_split = false, + .disable_dcc = DCC_ENABLE, + .vsr_support = true, +--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c +@@ -863,7 +863,7 @@ static const struct dc_debug_options deb + .disable_clock_gate = true, + .disable_pplib_clock_request = true, + .disable_pplib_wm_range = true, +- .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, ++ .pipe_split_policy = MPC_SPLIT_DYNAMIC, + .force_single_disp_pipe_split = false, + .disable_dcc = DCC_ENABLE, + .vsr_support = true, +--- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c +@@ -211,7 +211,7 @@ static const struct dc_debug_options deb + .timing_trace = false, + .clock_trace = true, + .disable_pplib_clock_request = true, +- .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, ++ .pipe_split_policy = MPC_SPLIT_DYNAMIC, + .force_single_disp_pipe_split = false, + .disable_dcc = DCC_ENABLE, + .vsr_support = true, +--- a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c +@@ -193,7 +193,7 @@ static const struct dc_debug_options deb + .timing_trace = false, + .clock_trace = true, + .disable_pplib_clock_request = true, +- .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, ++ .pipe_split_policy = MPC_SPLIT_DYNAMIC, + .force_single_disp_pipe_split = false, + .disable_dcc = DCC_ENABLE, + .vsr_support = true, +--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c +@@ -923,7 +923,7 @@ static const struct dc_debug_options deb + .timing_trace = false, + .clock_trace = true, + .disable_pplib_clock_request = false, +- .pipe_split_policy = MPC_SPLIT_AVOID, ++ .pipe_split_policy = MPC_SPLIT_DYNAMIC, + .force_single_disp_pipe_split = false, + .disable_dcc = DCC_ENABLE, + .vsr_support = true, diff --git a/queue-5.15/drm-amdgpu-add-support-for-ip-discovery-gc_info-table-v2.patch b/queue-5.15/drm-amdgpu-add-support-for-ip-discovery-gc_info-table-v2.patch new file mode 100644 index 00000000000..1b72a37451c --- /dev/null +++ b/queue-5.15/drm-amdgpu-add-support-for-ip-discovery-gc_info-table-v2.patch @@ -0,0 +1,175 @@ +From 5e713c6afa34c0fd6f113bf7bb1c2847172d7b20 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Wed, 15 Dec 2021 22:13:56 -0500 +Subject: drm/amdgpu: add support for IP discovery gc_info table v2 + +From: Alex Deucher + +commit 5e713c6afa34c0fd6f113bf7bb1c2847172d7b20 upstream. + +Used on gfx9 based systems. Fixes incorrect CU counts reported +in the kernel log. + +Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1833 +Reviewed-by: Hawking Zhang +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 76 ++++++++++++++++++-------- + drivers/gpu/drm/amd/include/discovery.h | 49 ++++++++++++++++ + 2 files changed, 103 insertions(+), 22 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +@@ -415,10 +415,15 @@ void amdgpu_discovery_harvest_ip(struct + } + } + ++union gc_info { ++ struct gc_info_v1_0 v1; ++ struct gc_info_v2_0 v2; ++}; ++ + int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) + { + struct binary_header *bhdr; +- struct gc_info_v1_0 *gc_info; ++ union gc_info *gc_info; + + if (!adev->mman.discovery_bin) { + DRM_ERROR("ip discovery uninitialized\n"); +@@ -426,27 +431,54 @@ int amdgpu_discovery_get_gfx_info(struct + } + + bhdr = (struct binary_header *)adev->mman.discovery_bin; +- gc_info = (struct gc_info_v1_0 *)(adev->mman.discovery_bin + ++ gc_info = (union gc_info *)(adev->mman.discovery_bin + + le16_to_cpu(bhdr->table_list[GC].offset)); +- +- adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->gc_num_se); +- adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->gc_num_wgp0_per_sa) + +- le32_to_cpu(gc_info->gc_num_wgp1_per_sa)); +- adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->gc_num_sa_per_se); +- adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->gc_num_rb_per_se); +- adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->gc_num_gl2c); +- adev->gfx.config.max_gprs = le32_to_cpu(gc_info->gc_num_gprs); +- adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->gc_num_max_gs_thds); +- adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->gc_gs_table_depth); +- adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->gc_gsprim_buff_depth); +- adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->gc_double_offchip_lds_buffer); +- adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->gc_wave_size); +- adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->gc_max_waves_per_simd); +- adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->gc_max_scratch_slots_per_cu); +- adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->gc_lds_size); +- adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->gc_num_sc_per_se) / +- le32_to_cpu(gc_info->gc_num_sa_per_se); +- adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->gc_num_packer_per_sc); +- ++ switch (gc_info->v1.header.version_major) { ++ case 1: ++ adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); ++ adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + ++ le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); ++ adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); ++ adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); ++ adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); ++ adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); ++ adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); ++ adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); ++ adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); ++ adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); ++ adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); ++ adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); ++ adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); ++ adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); ++ adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) / ++ le32_to_cpu(gc_info->v1.gc_num_sa_per_se); ++ adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc); ++ break; ++ case 2: ++ adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); ++ adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); ++ adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); ++ adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); ++ adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs); ++ adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); ++ adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds); ++ adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth); ++ adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth); ++ adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer); ++ adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); ++ adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); ++ adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); ++ adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); ++ adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / ++ le32_to_cpu(gc_info->v2.gc_num_sh_per_se); ++ adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); ++ break; ++ default: ++ dev_err(adev->dev, ++ "Unhandled GC info table %d.%d\n", ++ gc_info->v1.header.version_major, ++ gc_info->v1.header.version_minor); ++ return -EINVAL; ++ } + return 0; + } +--- a/drivers/gpu/drm/amd/include/discovery.h ++++ b/drivers/gpu/drm/amd/include/discovery.h +@@ -143,6 +143,55 @@ struct gc_info_v1_0 { + uint32_t gc_num_gl2a; + }; + ++struct gc_info_v1_1 { ++ struct gpu_info_header header; ++ ++ uint32_t gc_num_se; ++ uint32_t gc_num_wgp0_per_sa; ++ uint32_t gc_num_wgp1_per_sa; ++ uint32_t gc_num_rb_per_se; ++ uint32_t gc_num_gl2c; ++ uint32_t gc_num_gprs; ++ uint32_t gc_num_max_gs_thds; ++ uint32_t gc_gs_table_depth; ++ uint32_t gc_gsprim_buff_depth; ++ uint32_t gc_parameter_cache_depth; ++ uint32_t gc_double_offchip_lds_buffer; ++ uint32_t gc_wave_size; ++ uint32_t gc_max_waves_per_simd; ++ uint32_t gc_max_scratch_slots_per_cu; ++ uint32_t gc_lds_size; ++ uint32_t gc_num_sc_per_se; ++ uint32_t gc_num_sa_per_se; ++ uint32_t gc_num_packer_per_sc; ++ uint32_t gc_num_gl2a; ++ uint32_t gc_num_tcp_per_sa; ++ uint32_t gc_num_sdp_interface; ++ uint32_t gc_num_tcps; ++}; ++ ++struct gc_info_v2_0 { ++ struct gpu_info_header header; ++ ++ uint32_t gc_num_se; ++ uint32_t gc_num_cu_per_sh; ++ uint32_t gc_num_sh_per_se; ++ uint32_t gc_num_rb_per_se; ++ uint32_t gc_num_tccs; ++ uint32_t gc_num_gprs; ++ uint32_t gc_num_max_gs_thds; ++ uint32_t gc_gs_table_depth; ++ uint32_t gc_gsprim_buff_depth; ++ uint32_t gc_parameter_cache_depth; ++ uint32_t gc_double_offchip_lds_buffer; ++ uint32_t gc_wave_size; ++ uint32_t gc_max_waves_per_simd; ++ uint32_t gc_max_scratch_slots_per_cu; ++ uint32_t gc_lds_size; ++ uint32_t gc_num_sc_per_se; ++ uint32_t gc_num_packer_per_sc; ++}; ++ + typedef struct harvest_info_header { + uint32_t signature; /* Table Signature */ + uint32_t version; /* Table Version */ diff --git a/queue-5.15/drm-amdgpu-when-the-vcn-1.0-block-is-suspended-powergating-is-explicitly-enabled.patch b/queue-5.15/drm-amdgpu-when-the-vcn-1.0-block-is-suspended-powergating-is-explicitly-enabled.patch new file mode 100644 index 00000000000..0abc9656285 --- /dev/null +++ b/queue-5.15/drm-amdgpu-when-the-vcn-1.0-block-is-suspended-powergating-is-explicitly-enabled.patch @@ -0,0 +1,65 @@ +From b7865173cf6ae59942e2c69326a06e1c1df5ecf6 Mon Sep 17 00:00:00 2001 +From: chen gong +Date: Thu, 9 Dec 2021 19:47:10 +0800 +Subject: drm/amdgpu: When the VCN(1.0) block is suspended, powergating is explicitly enabled + +From: chen gong + +commit b7865173cf6ae59942e2c69326a06e1c1df5ecf6 upstream. + +Play a video on the raven (or PCO, raven2) platform, and then do the S3 +test. When resume, the following error will be reported: + +amdgpu 0000:02:00.0: [drm:amdgpu_ring_test_helper [amdgpu]] *ERROR* ring +vcn_dec test failed (-110) +[drm:amdgpu_device_ip_resume_phase2 [amdgpu]] *ERROR* resume of IP block + failed -110 +amdgpu 0000:02:00.0: amdgpu: amdgpu_device_ip_resume failed (-110). +PM: dpm_run_callback(): pci_pm_resume+0x0/0x90 returns -110 + +[why] +When playing the video: The power state flag of the vcn block is set to +POWER_STATE_ON. + +When doing suspend: There is no change to the power state flag of the +vcn block, it is still POWER_STATE_ON. + +When doing resume: Need to open the power gate of the vcn block and set +the power state flag of the VCN block to POWER_STATE_ON. +But at this time, the power state flag of the vcn block is already +POWER_STATE_ON. The power status flag check in the "8f2cdef drm/amd/pm: +avoid duplicate powergate/ungate setting" patch will return the +amdgpu_dpm_set_powergating_by_smu function directly. +As a result, the gate of the power was not opened, causing the +subsequent ring test to fail. + +[how] +In the suspend function of the vcn block, explicitly change the power +state flag of the vcn block to POWER_STATE_OFF. + +BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1828 +Signed-off-by: chen gong +Reviewed-by: Evan Quan +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +@@ -253,6 +253,13 @@ static int vcn_v1_0_suspend(void *handle + { + int r; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; ++ bool idle_work_unexecuted; ++ ++ idle_work_unexecuted = cancel_delayed_work_sync(&adev->vcn.idle_work); ++ if (idle_work_unexecuted) { ++ if (adev->pm.dpm_enabled) ++ amdgpu_dpm_enable_uvd(adev, false); ++ } + + r = vcn_v1_0_hw_fini(adev); + if (r) diff --git a/queue-5.15/drm-nouveau-wait-for-the-exclusive-fence-after-the-shared-ones-v2.patch b/queue-5.15/drm-nouveau-wait-for-the-exclusive-fence-after-the-shared-ones-v2.patch new file mode 100644 index 00000000000..9c3658fa21c --- /dev/null +++ b/queue-5.15/drm-nouveau-wait-for-the-exclusive-fence-after-the-shared-ones-v2.patch @@ -0,0 +1,91 @@ +From 67f74302f45d5d862f22ced3297624e50ac352f0 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= +Date: Tue, 7 Dec 2021 10:10:15 +0100 +Subject: drm/nouveau: wait for the exclusive fence after the shared ones v2 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Christian König + +commit 67f74302f45d5d862f22ced3297624e50ac352f0 upstream. + +Always waiting for the exclusive fence resulted on some performance +regressions. So try to wait for the shared fences first, then the +exclusive fence should always be signaled already. + +v2: fix incorrectly placed "(", add some comment why we do this. + +Signed-off-by: Christian König +Tested-by: Stefan Fritsch +Tested-by: Dan Moulding +Acked-by: Ben Skeggs +Signed-off-by: Christian König +Cc: +Link: https://patchwork.freedesktop.org/patch/msgid/20211209102335.18321-1-christian.koenig@amd.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/nouveau/nouveau_fence.c | 28 +++++++++++++++------------- + 1 file changed, 15 insertions(+), 13 deletions(-) + +--- a/drivers/gpu/drm/nouveau/nouveau_fence.c ++++ b/drivers/gpu/drm/nouveau/nouveau_fence.c +@@ -353,15 +353,22 @@ nouveau_fence_sync(struct nouveau_bo *nv + + if (ret) + return ret; +- } + +- fobj = dma_resv_shared_list(resv); +- fence = dma_resv_excl_fence(resv); ++ fobj = NULL; ++ } else { ++ fobj = dma_resv_shared_list(resv); ++ } + +- if (fence) { ++ /* Waiting for the exclusive fence first causes performance regressions ++ * under some circumstances. So manually wait for the shared ones first. ++ */ ++ for (i = 0; i < (fobj ? fobj->shared_count : 0) && !ret; ++i) { + struct nouveau_channel *prev = NULL; + bool must_wait = true; + ++ fence = rcu_dereference_protected(fobj->shared[i], ++ dma_resv_held(resv)); ++ + f = nouveau_local_fence(fence, chan->drm); + if (f) { + rcu_read_lock(); +@@ -373,20 +380,13 @@ nouveau_fence_sync(struct nouveau_bo *nv + + if (must_wait) + ret = dma_fence_wait(fence, intr); +- +- return ret; + } + +- if (!exclusive || !fobj) +- return ret; +- +- for (i = 0; i < fobj->shared_count && !ret; ++i) { ++ fence = dma_resv_excl_fence(resv); ++ if (fence) { + struct nouveau_channel *prev = NULL; + bool must_wait = true; + +- fence = rcu_dereference_protected(fobj->shared[i], +- dma_resv_held(resv)); +- + f = nouveau_local_fence(fence, chan->drm); + if (f) { + rcu_read_lock(); +@@ -398,6 +398,8 @@ nouveau_fence_sync(struct nouveau_bo *nv + + if (must_wait) + ret = dma_fence_wait(fence, intr); ++ ++ return ret; + } + + return ret; diff --git a/queue-5.15/nfc-uapi-use-kernel-size_t-to-fix-user-space-builds.patch b/queue-5.15/nfc-uapi-use-kernel-size_t-to-fix-user-space-builds.patch new file mode 100644 index 00000000000..f8d7961667b --- /dev/null +++ b/queue-5.15/nfc-uapi-use-kernel-size_t-to-fix-user-space-builds.patch @@ -0,0 +1,39 @@ +From 79b69a83705e621b258ac6d8ae6d3bfdb4b930aa Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski +Date: Sun, 26 Dec 2021 13:03:47 +0100 +Subject: nfc: uapi: use kernel size_t to fix user-space builds +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Krzysztof Kozlowski + +commit 79b69a83705e621b258ac6d8ae6d3bfdb4b930aa upstream. + +Fix user-space builds if it includes /usr/include/linux/nfc.h before +some of other headers: + + /usr/include/linux/nfc.h:281:9: error: unknown type name ‘size_t’ + 281 | size_t service_name_len; + | ^~~~~~ + +Fixes: d646960f7986 ("NFC: Initial LLCP support") +Cc: +Signed-off-by: Krzysztof Kozlowski +Signed-off-by: David S. Miller +Signed-off-by: Greg Kroah-Hartman +--- + include/uapi/linux/nfc.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/include/uapi/linux/nfc.h ++++ b/include/uapi/linux/nfc.h +@@ -278,7 +278,7 @@ struct sockaddr_nfc_llcp { + __u8 dsap; /* Destination SAP, if known */ + __u8 ssap; /* Source SAP to be bound to */ + char service_name[NFC_LLCP_MAX_SERVICE_NAME]; /* Service name URI */; +- size_t service_name_len; ++ __kernel_size_t service_name_len; + }; + + /* NFC socket protocols */ diff --git a/queue-5.15/series b/queue-5.15/series index 0efb1433583..97c235c927e 100644 --- a/queue-5.15/series +++ b/queue-5.15/series @@ -49,3 +49,9 @@ net-ncsi-check-for-error-return-from-call-to-nla_put.patch selftests-net-using-ping6-for-ipv6-in-udpgro_fwd.sh.patch fsl-fman-fix-missing-put_device-call-in-fman_port_pr.patch i2c-validate-user-data-in-compat-ioctl.patch +nfc-uapi-use-kernel-size_t-to-fix-user-space-builds.patch +uapi-fix-linux-nfc.h-userspace-compilation-errors.patch +drm-nouveau-wait-for-the-exclusive-fence-after-the-shared-ones-v2.patch +drm-amdgpu-when-the-vcn-1.0-block-is-suspended-powergating-is-explicitly-enabled.patch +drm-amdgpu-add-support-for-ip-discovery-gc_info-table-v2.patch +drm-amd-display-changed-pipe-split-policy-to-allow-for-multi-display-pipe-split.patch diff --git a/queue-5.15/uapi-fix-linux-nfc.h-userspace-compilation-errors.patch b/queue-5.15/uapi-fix-linux-nfc.h-userspace-compilation-errors.patch new file mode 100644 index 00000000000..65b44886c31 --- /dev/null +++ b/queue-5.15/uapi-fix-linux-nfc.h-userspace-compilation-errors.patch @@ -0,0 +1,48 @@ +From 7175f02c4e5f5a9430113ab9ca0fd0ce98b28a51 Mon Sep 17 00:00:00 2001 +From: "Dmitry V. Levin" +Date: Sun, 26 Dec 2021 16:01:27 +0300 +Subject: uapi: fix linux/nfc.h userspace compilation errors + +From: Dmitry V. Levin + +commit 7175f02c4e5f5a9430113ab9ca0fd0ce98b28a51 upstream. + +Replace sa_family_t with __kernel_sa_family_t to fix the following +linux/nfc.h userspace compilation errors: + +/usr/include/linux/nfc.h:266:2: error: unknown type name 'sa_family_t' + sa_family_t sa_family; +/usr/include/linux/nfc.h:274:2: error: unknown type name 'sa_family_t' + sa_family_t sa_family; + +Fixes: 23b7869c0fd0 ("NFC: add the NFC socket raw protocol") +Fixes: d646960f7986 ("NFC: Initial LLCP support") +Cc: +Signed-off-by: Dmitry V. Levin +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: David S. Miller +Signed-off-by: Greg Kroah-Hartman +--- + include/uapi/linux/nfc.h | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/include/uapi/linux/nfc.h ++++ b/include/uapi/linux/nfc.h +@@ -263,7 +263,7 @@ enum nfc_sdp_attr { + #define NFC_SE_ENABLED 0x1 + + struct sockaddr_nfc { +- sa_family_t sa_family; ++ __kernel_sa_family_t sa_family; + __u32 dev_idx; + __u32 target_idx; + __u32 nfc_protocol; +@@ -271,7 +271,7 @@ struct sockaddr_nfc { + + #define NFC_LLCP_MAX_SERVICE_NAME 63 + struct sockaddr_nfc_llcp { +- sa_family_t sa_family; ++ __kernel_sa_family_t sa_family; + __u32 dev_idx; + __u32 target_idx; + __u32 nfc_protocol; -- 2.47.3