From 7b40420613dee7e8b40ea15d49397c7e534ea93c Mon Sep 17 00:00:00 2001
From: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
Date: Tue, 17 May 2016 16:49:01 +0530
Subject: [PATCH] devicetree: phy: add device tree properties for ZynqMP GT
 core

This patch adds the ZynqMP GT core device-tree properties for
zynqmp.dtsi file.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Tested-by: Hyun Kwon <hyunk@xilinx.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
 arch/arm/dts/zynqmp.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index ca6fc6b2787..f0dedcdab2b 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -711,6 +711,27 @@
 			interrupt-names = "alarm", "sec";
 		};
 
+		serdes: zynqmp_phy@fd400000 {
+			compatible = "xlnx,zynqmp-psgtr";
+			status = "disabled";
+			reg = <0x0 0xfd400000 0x40000>, <0x0 0xfd3d0000 0x1000>,
+				<0x0 0xfd1a0000 0x1000>, <0x0 0xff5e0000 0x1000>;
+			reg-names = "serdes", "siou", "fpd", "lpd";
+			xlnx,tx_termination_fix;
+			lane0: lane@0 {
+				#phy-cells = <4>;
+			};
+			lane1: lane@1 {
+				#phy-cells = <4>;
+			};
+			lane2: lane@2 {
+				#phy-cells = <4>;
+			};
+			lane3: lane@3 {
+				#phy-cells = <4>;
+			};
+		};
+
 		sata: ahci@fd0c0000 {
 			compatible = "ceva,ahci-1v84";
 			status = "disabled";
-- 
2.47.3