From 7e3fb097ba77ce1a6e9860fdd82fff969b7155e2 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 15 Jan 2015 11:31:23 +0100 Subject: [PATCH] zynqmp: Get rid of XILINX_ZYNQMP and use CONFIG_TARGET_XILINX_ZYNQMP CONFIG_TARGET_XILINX_ZYNQMP is Kconfig entry which is better to use. Signed-off-by: Michal Simek --- drivers/mtd/spi/sf_params.c | 2 +- drivers/net/zynq_gem.c | 10 +++++----- drivers/spi/zynq_qspi.c | 6 +++--- include/configs/xilinx_zynqmp.h | 2 -- 4 files changed, 9 insertions(+), 11 deletions(-) diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c index 96e3ad2743f..0ee740c435d 100644 --- a/drivers/mtd/spi/sf_params.c +++ b/drivers/mtd/spi/sf_params.c @@ -86,7 +86,7 @@ const struct spi_flash_params spi_flash_params_table[] = { {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K}, {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K}, {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K}, -#ifdef XILINX_ZYNQMP +#ifdef CONFIG_TARGET_XILINX_ZYNQMP {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR}, #else {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K}, diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 527552c23cc..7c3c3b473e7 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -56,14 +56,14 @@ #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */ #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */ #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */ -#ifdef XILINX_ZYNQMP +#ifdef CONFIG_TARGET_XILINX_ZYNQMP #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x0001C0000 /* Div pclk by 224, 540MHz */ #else #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */ #endif #define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */ -#ifdef XILINX_ZYNQMP +#ifdef CONFIG_TARGET_XILINX_ZYNQMP # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ #else # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */ @@ -348,7 +348,7 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) priv->init++; } -#ifdef XILINX_ZYNQMP +#ifdef CONFIG_TARGET_XILINX_ZYNQMP if (!priv->init) { #endif phy_detection(dev); @@ -384,11 +384,11 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) clk_rate = ZYNQ_GEM_FREQUENCY_10; break; } -#ifdef XILINX_ZYNQMP +#ifdef CONFIG_TARGET_XILINX_ZYNQMP } #endif -#ifndef XILINX_ZYNQMP +#ifndef CONFIG_TARGET_XILINX_ZYNQMP /* Change the rclk and clk only not using EMIO interface */ if (!priv->emio) zynq_slcr_gem_clk_setup(dev->iobase != diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index 529b12244e8..4e7cd1a12c2 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -281,7 +281,7 @@ static void zynq_qspi_init_hw(int is_dual, unsigned int cs) config_reg |= ZYNQ_QSPI_CONFIG_IFMODE_MASK | ZYNQ_QSPI_CONFIG_MCS_MASK | ZYNQ_QSPI_CONFIG_PCS_MASK | ZYNQ_QSPI_CONFIG_FW_MASK | ZYNQ_QSPI_CONFIG_MSTREN_MASK; -#ifndef XILINX_ZYNQMP +#ifndef CONFIG_TARGET_XILINX_ZYNQMP if (is_dual == SF_DUAL_STACKED_FLASH) #endif config_reg |= 0x10; @@ -476,7 +476,7 @@ static int zynq_qspi_setup_transfer(struct spi_device *qspi, if (qspi->mode & SPI_CPOL) config_reg |= ZYNQ_QSPI_CONFIG_CPOL_MASK; -#ifndef XILINX_ZYNQMP +#ifndef CONFIG_TARGET_XILINX_ZYNQMP /* Set the clock frequency */ if (zqspi->speed_hz != req_hz) { baud_rate_val = 0; @@ -902,7 +902,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, return NULL; } -#ifndef XILINX_ZYNQMP +#ifndef CONFIG_TARGET_XILINX_ZYNQMP lqspi_frequency = zynq_clk_get_rate(lqspi_clk); #endif if (!lqspi_frequency) { diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 857a72c2a63..29855abbaa9 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -19,8 +19,6 @@ #define CONFIG_SYS_GENERIC_BOARD -#define XILINX_ZYNQMP - /* Generic Interrupt Controller Definitions */ #define CONFIG_GICV2 #define GICD_BASE 0xF9010000 -- 2.47.3