From 8041d7fcaabaa6bd833a7fc94362366596aa01c7 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 8 Apr 2025 08:49:07 +0200 Subject: [PATCH] 5.10-stable patches added patches: drm-amd-display-skip-inactive-planes-within-modesupportandsystemconfiguration.patch drm-amd-pm-fix-negative-array-index-read.patch --- ...in-modesupportandsystemconfiguration.patch | 80 +++++++++++++++++++ ...amd-pm-fix-negative-array-index-read.patch | 79 ++++++++++++++++++ queue-5.10/series | 2 + 3 files changed, 161 insertions(+) create mode 100644 queue-5.10/drm-amd-display-skip-inactive-planes-within-modesupportandsystemconfiguration.patch create mode 100644 queue-5.10/drm-amd-pm-fix-negative-array-index-read.patch diff --git a/queue-5.10/drm-amd-display-skip-inactive-planes-within-modesupportandsystemconfiguration.patch b/queue-5.10/drm-amd-display-skip-inactive-planes-within-modesupportandsystemconfiguration.patch new file mode 100644 index 0000000000..93228b5bc0 --- /dev/null +++ b/queue-5.10/drm-amd-display-skip-inactive-planes-within-modesupportandsystemconfiguration.patch @@ -0,0 +1,80 @@ +From a54f7e866cc73a4cb71b8b24bb568ba35c8969df Mon Sep 17 00:00:00 2001 +From: Hersen Wu +Date: Fri, 26 Apr 2024 16:39:37 -0400 +Subject: drm/amd/display: Skip inactive planes within ModeSupportAndSystemConfiguration + +From: Hersen Wu + +commit a54f7e866cc73a4cb71b8b24bb568ba35c8969df upstream. + +[Why] +Coverity reports Memory - illegal accesses. + +[How] +Skip inactive planes. + +Reviewed-by: Alex Hung +Acked-by: Tom Chung +Signed-off-by: Hersen Wu +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +[get_pipe_idx() was introduced as a helper by +dda4fb85e433 ("drm/amd/display: DML changes for DCN32/321") in v6.0. +This patch backports it to make code clearer. And minor conflict is +resolved due to code context change.] +Signed-off-by: Jianqi Ren +Signed-off-by: He Zhe +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 27 +++++++++++++++++- + 1 file changed, 26 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c +@@ -838,11 +838,30 @@ static unsigned int CursorBppEnumToBits( + } + } + ++static unsigned int get_pipe_idx(struct display_mode_lib *mode_lib, unsigned int plane_idx) ++{ ++ int pipe_idx = -1; ++ int i; ++ ++ ASSERT(plane_idx < DC__NUM_DPP__MAX); ++ ++ for (i = 0; i < DC__NUM_DPP__MAX ; i++) { ++ if (plane_idx == mode_lib->vba.pipe_plane[i]) { ++ pipe_idx = i; ++ break; ++ } ++ } ++ ASSERT(pipe_idx >= 0); ++ ++ return pipe_idx; ++} ++ + void ModeSupportAndSystemConfiguration(struct display_mode_lib *mode_lib) + { + soc_bounding_box_st *soc = &mode_lib->vba.soc; + unsigned int k; + unsigned int total_pipes = 0; ++ unsigned int pipe_idx = 0; + + mode_lib->vba.VoltageLevel = mode_lib->vba.cache_pipes[0].clks_cfg.voltage; + mode_lib->vba.ReturnBW = mode_lib->vba.ReturnBWPerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb]; +@@ -862,8 +881,14 @@ void ModeSupportAndSystemConfiguration(s + mode_lib->vba.DISPCLK = soc->clock_limits[mode_lib->vba.VoltageLevel].dispclk_mhz; + + // Total Available Pipes Support Check +- for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) ++ for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) { ++ pipe_idx = get_pipe_idx(mode_lib, k); ++ if (pipe_idx == -1) { ++ ASSERT(0); ++ continue; // skip inactive planes ++ } + total_pipes += mode_lib->vba.DPPPerPlane[k]; ++ } + ASSERT(total_pipes <= DC__NUM_DPP__MAX); + } + diff --git a/queue-5.10/drm-amd-pm-fix-negative-array-index-read.patch b/queue-5.10/drm-amd-pm-fix-negative-array-index-read.patch new file mode 100644 index 0000000000..63dd9a0290 --- /dev/null +++ b/queue-5.10/drm-amd-pm-fix-negative-array-index-read.patch @@ -0,0 +1,79 @@ +From c8c19ebf7c0b202a6a2d37a52ca112432723db5f Mon Sep 17 00:00:00 2001 +From: Jesse Zhang +Date: Tue, 30 Apr 2024 10:23:48 +0800 +Subject: drm/amd/pm: Fix negative array index read + +From: Jesse Zhang + +commit c8c19ebf7c0b202a6a2d37a52ca112432723db5f upstream. + +Avoid using the negative values +for clk_idex as an index into an array pptable->DpmDescriptor. + +V2: fix clk_index return check (Tim Huang) + +Signed-off-by: Jesse Zhang +Reviewed-by: Tim Huang +Signed-off-by: Alex Deucher +[Minor conflict resolved due to code context change.] +Signed-off-by: Jianqi Ren +Signed-off-by: He Zhe +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 21 ++++++++++++++++----- + 1 file changed, 16 insertions(+), 5 deletions(-) + +--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +@@ -900,19 +900,22 @@ static int navi10_get_current_clk_freq_b + value); + } + +-static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) ++static int navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) + { + PPTable_t *pptable = smu->smu_table.driver_pptable; + DpmDescriptor_t *dpm_desc = NULL; +- uint32_t clk_index = 0; ++ int clk_index = 0; + + clk_index = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_CLK, + clk_type); ++ if (clk_index < 0) ++ return clk_index; ++ + dpm_desc = &pptable->DpmDescriptor[clk_index]; + + /* 0 - Fine grained DPM, 1 - Discrete DPM */ +- return dpm_desc->SnapToDiscrete == 0 ? true : false; ++ return dpm_desc->SnapToDiscrete == 0 ? 1 : 0; + } + + static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_CAP cap) +@@ -964,7 +967,11 @@ static int navi10_print_clk_levels(struc + if (ret) + return size; + +- if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) { ++ ret = navi10_is_support_fine_grained_dpm(smu, clk_type); ++ if (ret < 0) ++ return ret; ++ ++ if (!ret) { + for (i = 0; i < count; i++) { + ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value); + if (ret) +@@ -1127,7 +1134,11 @@ static int navi10_force_clk_levels(struc + case SMU_UCLK: + case SMU_FCLK: + /* There is only 2 levels for fine grained DPM */ +- if (navi10_is_support_fine_grained_dpm(smu, clk_type)) { ++ ret = navi10_is_support_fine_grained_dpm(smu, clk_type); ++ if (ret < 0) ++ return ret; ++ ++ if (ret) { + soft_max_level = (soft_max_level >= 1 ? 1 : 0); + soft_min_level = (soft_min_level >= 1 ? 1 : 0); + } diff --git a/queue-5.10/series b/queue-5.10/series index 2a6710d792..f3cb182957 100644 --- a/queue-5.10/series +++ b/queue-5.10/series @@ -206,3 +206,5 @@ arcnet-add-null-check-in-com20020pci_probe.patch can-flexcan-only-change-can-state-when-link-up-in-sy.patch tty-serial-fsl_lpuart-use-uartmodir-register-bits-fo.patch tty-serial-fsl_lpuart-disable-transmitter-before-cha.patch +drm-amd-pm-fix-negative-array-index-read.patch +drm-amd-display-skip-inactive-planes-within-modesupportandsystemconfiguration.patch -- 2.47.3