From 84953731f9170b3b51013f1f4deb59cc916dfa7b Mon Sep 17 00:00:00 2001 From: =?utf8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 19 Sep 2025 22:29:55 +0300 Subject: [PATCH] drm/i915: Use increase_wm_latency() for the 16Gb DIMM w/a MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Bump the latency for all watermark levels in the 16Gb+ DIMM w/a. The spec does ask us to do it only for level 0, but it seems more sane to bump all the levels. If the actual memory access is slower then the wakeup (WM1+) should also potentially happen earlier. This also avoids the theoretical case that WM0 would get bumped higher than WM1+. Not that it is likely to happen because the WM0 latency is always significantly lower than the WM1 latency. Reviewed-by: Luca Coelho Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20250919193000.17665-9-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/skl_watermark.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 98ca592f6042e..21dd15be74f98 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -3256,7 +3256,7 @@ adjust_wm_latency(struct intel_display *display) * to avoid any underrun. */ if (need_16gb_dimm_wa(display)) - wm[0] += 1; + increase_wm_latency(display, 1); } static void mtl_read_wm_latency(struct intel_display *display) -- 2.47.3