From 865ad849241c63588ef3485871c8256aaf3e2f5f Mon Sep 17 00:00:00 2001 From: John Linn Date: Fri, 9 Jul 2010 10:39:46 -0600 Subject: [PATCH] Xilinx: ARM: Updates for NOR flash This commit changed the configuration to use the CFI driver so that there is no code needed to support NOR flash, except a bit of initialization for the SMC controller. There are other commits that are needed to make flash work together with this one as the CFI driver has a bug for the Numonyx flash in 8 bit mode. See the next commit for this fix. --- board/xilinx/dfe/Makefile | 2 - board/xilinx/dfe/board.c | 81 ++++++++++++++++++++++++++++++++++++++- include/configs/xpele.h | 19 ++++++--- 3 files changed, 93 insertions(+), 9 deletions(-) diff --git a/board/xilinx/dfe/Makefile b/board/xilinx/dfe/Makefile index ee65fc3624a..12777eb65a5 100644 --- a/board/xilinx/dfe/Makefile +++ b/board/xilinx/dfe/Makefile @@ -29,8 +29,6 @@ endif LIB = $(obj)lib$(BOARD).a COBJS := board.o \ - flash.o \ - pl353_x8.o \ xemacpss_g.o xemacpss_control.o xemacpss_sinit.o \ xemacpss_bdring.o xemacpss.o xgmac.o \ ../common/xbasic_types.o diff --git a/board/xilinx/dfe/board.c b/board/xilinx/dfe/board.c index bff519bd977..086c8c8bc43 100644 --- a/board/xilinx/dfe/board.c +++ b/board/xilinx/dfe/board.c @@ -3,13 +3,91 @@ */ #include +#include + +#define PARPORT_CRTL_BASEADDR XPSS_CRTL_PARPORT_BASEADDR +#define NOR_FLASH_BASEADDR XPSS_PARPORT1_BASEADDR + +#define PARPORT_MC_DIRECT_CMD 0x010 +#define PARPORT_MC_SET_CYCLES 0x014 +#define PARPORT_MC_SET_OPMODE 0x018 DECLARE_GLOBAL_DATA_PTR; +/* Where should these really go? */ + +static void Out32(u32 OutAddress, u32 Value) +{ + *(volatile u32 *) OutAddress = Value; +} + +static u32 In32(u32 InAddress) +{ + return *(u32 *) InAddress; +} + +static void Out8(u32 OutAddress, u8 Value) +{ + *(volatile u8 *) OutAddress = Value; +} + +static u8 In8(u32 InAddress) +{ + return *(u8 *) InAddress; +} + +/* + * init_nor_flash init the parameters of pl353 for the M29EW Flash + */ +void init_nor_flash() +{ + /* Init variables */ + + /* Write timing info to set_cycles registers */ + u32 set_cycles_reg = (0x0 << 20) | /* Set_t6 or we_time from sram_cycles */ + (0x1 << 17) | /* Set_t5 or t_tr from sram_cycles */ + (0x2 << 14) | /* Set_t4 or t_pc from sram_cycles */ + (0x5 << 11) | /* Set_t3 or t_wp from sram_cycles */ + (0x2 << 8) | /* Set_t2 t_ceoe from sram_cycles */ + (0x7 << 4) | /* Set_t1 t_wc from sram_cycles */ + (0x7); /* Set_t0 t_rc from sram_cycles */ + + Out32(PARPORT_CRTL_BASEADDR + PARPORT_MC_SET_CYCLES, set_cycles_reg); + + /* write operation mode to set_opmode registers */ + u32 set_opmode_reg = (0x1 << 13) | /* set_burst_align, see to 32 beats */ + (0x0 << 12) | /* set_bls, set to default I am not sure */ + (0x0 << 11) | /* set_adv bit, set to default */ + (0x0 << 10) | /* set_baa, I guess we don't use baa_n */ + (0x0 << 7) | /* set_wr_bl, write brust length, set to 0 */ + (0x0 << 6) | /* set_wr_sync, set to 0 */ + (0x0 << 3) | /* set_rd_bl, read brust lenght, set to 0 */ + (0x0 << 2) | /* set_rd_sync, set to 0 */ + (0x0 ); /* set_mw, memory width, 16bits width*/ + Out32(PARPORT_CRTL_BASEADDR + PARPORT_MC_SET_OPMODE, set_opmode_reg); + + /* + * Issue a direct_cmd by writing to direct_cmd register + * This is needed becuase the UpdatesReg flag in direct_cmd updates the state of SMC + * I think.... + */ + u32 direct_cmd_reg = (0x1 << 23) | /* chip 1 from interface 0 */ + (0x2 << 21) | /* UpdateRegs operation, to update the two reg we wrote earlier*/ + (0x0 << 20) | /* Not sure about this one cre, what does it do? */ + (0x0); /* addr, not use in UpdateRegs */ + Out32(PARPORT_CRTL_BASEADDR + PARPORT_MC_DIRECT_CMD, direct_cmd_reg); + + /* reset the flash itself so that it's ready to be accessed */ + + Out8(NOR_FLASH_BASEADDR + 0xAAA, 0xAA); + Out8(NOR_FLASH_BASEADDR + 0x555, 0x55); + Out8(NOR_FLASH_BASEADDR, 0xF0); +} + int board_init(void) { icache_enable(); - + init_nor_flash(); return 0; } @@ -17,6 +95,7 @@ int dram_init(void) { gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + return 0; } diff --git a/include/configs/xpele.h b/include/configs/xpele.h index f5a72f0c382..4f2cc33ccdb 100644 --- a/include/configs/xpele.h +++ b/include/configs/xpele.h @@ -70,16 +70,23 @@ #ifndef CONFIG_SYS_NO_FLASH /* FLASH organization */ -#define CONFIG_SYS_FLASH_BASE 0xE2000000 +#define CONFIG_SYS_FLASH_BASE 0xE4000000 #define CONFIG_SYS_FLASH_SIZE (16*1024*1024) /* i.e. 16MB */ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors/blocks on one chip */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors/blocks on one chip */ #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 +#define CONFIG_SYS_FLASH_WRITE_TOUT 5000 -#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CONFIG_FLASH_SHOW_PROGRESS 10 + +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_SYS_FLASH_EMPTY_INFO 0 +#define CONFIG_FLASH_CFI_DRIVER 1 + +#define CONFIG_SYS_FLASH_PROTECTION 0 /* use hardware protection */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */ #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000) -#define CONFIG_ENV_SECT_SIZE 0x10000 /*64 KB*/ +#define CONFIG_ENV_SECT_SIZE 0x20000 /*128 KB*/ #define CONFIG_ENV_IS_NOWHERE 1 //#define CONFIG_ENV_IS_IN_FLASH 1 @@ -120,7 +127,7 @@ #define CONFIG_GEM0 1 /* XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ */ -#define CONFIG_SYS_HZ 12500000 +#define CONFIG_SYS_HZ 5000000 /* And here... */ #define CONFIG_SYS_LOAD_ADDR 0 /* default? */ -- 2.47.3