From 8a0436cb79ccf797d0dbc02175fce1a254a1a691 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Sat, 17 Sep 2011 17:24:59 +0200 Subject: [PATCH] sse.md (VIMAX_AVX2): Change V4DI to V2TI. * config/i386/sse.md (VIMAX_AVX2): Change V4DI to V2TI. (sse2_avx, sseinsnmode): Add V2TI. (REDUC_SMINMAX_MODE): New mode iterator. (reduc_smax_v4sf, reduc_smin_v4sf, reduc_smax_v8sf, reduc_smin_v8sf, reduc_smax_v4df, reduc_smin_v4df): Remove. (reduc__): New smaxmin and umaxmin expanders. (sse2_lshrv1ti3): Rename to... (_lshr3): ... this. Use VIMAX_AVX2 mode iterator. Move before umaxmin expanders. * config/i386/i386.h (VALID_AVX256_REG_MODE, SSE_REG_MODE_P): Accept V2TImode. * config/i386/i386.c (ix86_expand_reduc): Handle V32QImode, V16HImode, V8SImode and V4DImode. From-SVN: r178930 --- gcc/ChangeLog | 16 +++++- gcc/config/i386/i386.c | 26 +++++++++ gcc/config/i386/i386.h | 6 ++- gcc/config/i386/sse.md | 120 ++++++++++++++++------------------------- 4 files changed, 91 insertions(+), 77 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3498f979aff1..007b8dffe325 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,19 @@ 2011-09-17 Jakub Jelinek + * config/i386/sse.md (VIMAX_AVX2): Change V4DI to V2TI. + (sse2_avx, sseinsnmode): Add V2TI. + (REDUC_SMINMAX_MODE): New mode iterator. + (reduc_smax_v4sf, reduc_smin_v4sf, reduc_smax_v8sf, + reduc_smin_v8sf, reduc_smax_v4df, reduc_smin_v4df): Remove. + (reduc__): New smaxmin and umaxmin expanders. + (sse2_lshrv1ti3): Rename to... + (_lshr3): ... this. Use VIMAX_AVX2 mode + iterator. Move before umaxmin expanders. + * config/i386/i386.h (VALID_AVX256_REG_MODE, + SSE_REG_MODE_P): Accept V2TImode. + * config/i386/i386.c (ix86_expand_reduc): Handle V32QImode, + V16HImode, V8SImode and V4DImode. + * config/i386/i386.c (ix86_build_const_vector): Handle V8SImode and V4DImode. (ix86_build_signbit_mask): Likewise. @@ -19,7 +33,7 @@ VI8_AVX2 mode iterator. (vcond, vcondu): New expanders. - + 2011-09-17 Richard Sandiford * config/ia64/itanium2.md: Use match_test rather than eq/ne symbol_ref diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index d4f589d8d194..57cc8e3b937c 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -32719,6 +32719,7 @@ ix86_expand_reduc (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in) { rtx tmp1, tmp2, tmp3, tmp4, tmp5; enum machine_mode mode = GET_MODE (in); + int i; tmp1 = gen_reg_rtx (mode); tmp2 = gen_reg_rtx (mode); @@ -32747,6 +32748,31 @@ ix86_expand_reduc (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in) emit_insn (fn (tmp2, tmp1, in)); emit_insn (gen_avx_shufpd256 (tmp3, tmp2, tmp2, const1_rtx)); break; + case V32QImode: + case V16HImode: + case V8SImode: + case V4DImode: + emit_insn (gen_avx2_permv2ti (gen_lowpart (V4DImode, tmp1), + gen_lowpart (V4DImode, in), + gen_lowpart (V4DImode, in), + const1_rtx)); + tmp4 = in; + tmp5 = tmp1; + for (i = 64; i >= GET_MODE_BITSIZE (GET_MODE_INNER (mode)); i >>= 1) + { + if (i != 64) + { + tmp2 = gen_reg_rtx (mode); + tmp3 = gen_reg_rtx (mode); + } + emit_insn (fn (tmp2, tmp4, tmp5)); + emit_insn (gen_avx2_lshrv2ti3 (gen_lowpart (V2TImode, tmp3), + gen_lowpart (V2TImode, tmp2), + GEN_INT (i))); + tmp4 = tmp2; + tmp5 = tmp3; + } + break; default: gcc_unreachable (); } diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 21f507552118..7d6e05827b0b 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -995,7 +995,8 @@ enum target_cpu_default #define VALID_AVX256_REG_MODE(MODE) \ ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ - || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode) + || (MODE) == V4DImode || (MODE) == V2TImode || (MODE) == V8SFmode \ + || (MODE) == V4DFmode) #define VALID_SSE2_REG_MODE(MODE) \ ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ @@ -1035,7 +1036,8 @@ enum target_cpu_default || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \ || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \ || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ - || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode) + || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode \ + || (MODE) == V2TImode) /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 5d605bb6f5be..4567ee920d14 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -100,7 +100,7 @@ [(V4DI "TARGET_AVX2") V2DI]) (define_mode_iterator VIMAX_AVX2 - [(V4DI "TARGET_AVX2") V1TI]) + [(V2TI "TARGET_AVX2") V1TI]) (define_mode_iterator SSESCALARMODE [(V4DI "TARGET_AVX2") TI]) @@ -140,7 +140,7 @@ (V8HI "sse2") (V16HI "avx2") (V4SI "sse2") (V8SI "avx2") (V2DI "sse2") (V4DI "avx2") - (V1TI "sse2")]) + (V1TI "sse2") (V2TI "avx2")]) (define_mode_attr ssse3_avx2 [(V16QI "ssse3") (V32QI "avx2") @@ -225,7 +225,7 @@ ;; SSE instruction mode (define_mode_attr sseinsnmode - [(V32QI "OI") (V16HI "OI") (V8SI "OI") (V4DI "OI") + [(V32QI "OI") (V16HI "OI") (V8SI "OI") (V4DI "OI") (V2TI "OI") (V16QI "TI") (V8HI "TI") (V4SI "TI") (V2DI "TI") (V1TI "TI") (V8SF "V8SF") (V4DF "V4DF") (V4SF "V4SF") (V2DF "V2DF") @@ -1257,58 +1257,30 @@ DONE; }) +;; Modes handled by reduc_sm{in,ax}* patterns. +(define_mode_iterator REDUC_SMINMAX_MODE + [(V32QI "TARGET_AVX2") (V16HI "TARGET_AVX2") + (V8SI "TARGET_AVX2") (V4DI "TARGET_AVX2") + (V8SF "TARGET_AVX") (V4DF "TARGET_AVX") + (V4SF "TARGET_SSE")]) -(define_expand "reduc_smax_v4sf" - [(match_operand:V4SF 0 "register_operand" "") - (match_operand:V4SF 1 "register_operand" "")] - "TARGET_SSE" -{ - ix86_expand_reduc (gen_smaxv4sf3, operands[0], operands[1]); - DONE; -}) - -(define_expand "reduc_smin_v4sf" - [(match_operand:V4SF 0 "register_operand" "") - (match_operand:V4SF 1 "register_operand" "")] - "TARGET_SSE" -{ - ix86_expand_reduc (gen_sminv4sf3, operands[0], operands[1]); - DONE; -}) - -(define_expand "reduc_smax_v8sf" - [(match_operand:V8SF 0 "register_operand" "") - (match_operand:V8SF 1 "register_operand" "")] - "TARGET_AVX" -{ - ix86_expand_reduc (gen_smaxv8sf3, operands[0], operands[1]); - DONE; -}) - -(define_expand "reduc_smin_v8sf" - [(match_operand:V8SF 0 "register_operand" "") - (match_operand:V8SF 1 "register_operand" "")] - "TARGET_AVX" -{ - ix86_expand_reduc (gen_sminv8sf3, operands[0], operands[1]); - DONE; -}) - -(define_expand "reduc_smax_v4df" - [(match_operand:V4DF 0 "register_operand" "") - (match_operand:V4DF 1 "register_operand" "")] - "TARGET_AVX" +(define_expand "reduc__" + [(smaxmin:REDUC_SMINMAX_MODE + (match_operand:REDUC_SMINMAX_MODE 0 "register_operand" "") + (match_operand:REDUC_SMINMAX_MODE 1 "register_operand" ""))] + "" { - ix86_expand_reduc (gen_smaxv4df3, operands[0], operands[1]); + ix86_expand_reduc (gen_3, operands[0], operands[1]); DONE; }) -(define_expand "reduc_smin_v4df" - [(match_operand:V4DF 0 "register_operand" "") - (match_operand:V4DF 1 "register_operand" "")] - "TARGET_AVX" +(define_expand "reduc__" + [(umaxmin:VI_256 + (match_operand:VI_256 0 "register_operand" "") + (match_operand:VI_256 1 "register_operand" ""))] + "TARGET_AVX2" { - ix86_expand_reduc (gen_sminv4df3, operands[0], operands[1]); + ix86_expand_reduc (gen_3, operands[0], operands[1]); DONE; }) @@ -5806,30 +5778,10 @@ operands[1] = gen_lowpart (V1TImode, operands[1]); }) -(define_expand "3" - [(set (match_operand:VI124_256 0 "register_operand" "") - (umaxmin:VI124_256 - (match_operand:VI124_256 1 "nonimmediate_operand" "") - (match_operand:VI124_256 2 "nonimmediate_operand" "")))] - "TARGET_AVX2" - "ix86_fixup_binary_operands_no_copy (, mode, operands);") - -(define_insn "*avx2_3" - [(set (match_operand:VI124_256 0 "register_operand" "=x") - (umaxmin:VI124_256 - (match_operand:VI124_256 1 "nonimmediate_operand" "%x") - (match_operand:VI124_256 2 "nonimmediate_operand" "xm")))] - "TARGET_AVX2 && ix86_binary_operator_ok (, mode, operands)" - "vp\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "type" "sseiadd") - (set_attr "prefix_extra" "1") - (set_attr "prefix" "vex") - (set_attr "mode" "OI")]) - -(define_insn "sse2_lshrv1ti3" - [(set (match_operand:V1TI 0 "register_operand" "=x,x") - (lshiftrt:V1TI - (match_operand:V1TI 1 "register_operand" "0,x") +(define_insn "_lshr3" + [(set (match_operand:VIMAX_AVX2 0 "register_operand" "=x,x") + (lshiftrt:VIMAX_AVX2 + (match_operand:VIMAX_AVX2 1 "register_operand" "0,x") (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n,n")))] "TARGET_SSE2" { @@ -5851,7 +5803,27 @@ (set_attr "atom_unit" "sishuf") (set_attr "prefix_data16" "1,*") (set_attr "prefix" "orig,vex") - (set_attr "mode" "TI")]) + (set_attr "mode" "")]) + +(define_expand "3" + [(set (match_operand:VI124_256 0 "register_operand" "") + (umaxmin:VI124_256 + (match_operand:VI124_256 1 "nonimmediate_operand" "") + (match_operand:VI124_256 2 "nonimmediate_operand" "")))] + "TARGET_AVX2" + "ix86_fixup_binary_operands_no_copy (, mode, operands);") + +(define_insn "*avx2_3" + [(set (match_operand:VI124_256 0 "register_operand" "=x") + (umaxmin:VI124_256 + (match_operand:VI124_256 1 "nonimmediate_operand" "%x") + (match_operand:VI124_256 2 "nonimmediate_operand" "xm")))] + "TARGET_AVX2 && ix86_binary_operator_ok (, mode, operands)" + "vp\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "type" "sseiadd") + (set_attr "prefix_extra" "1") + (set_attr "prefix" "vex") + (set_attr "mode" "OI")]) (define_expand "3" [(set (match_operand:VI124_256 0 "register_operand" "") -- 2.47.3