From 90faf2841c7a26a8ad515e1789851e25fabc3573 Mon Sep 17 00:00:00 2001 From: GCC Administrator Date: Tue, 25 May 2021 00:18:36 +0000 Subject: [PATCH] Daily bump. --- gcc/ChangeLog | 9 +++++++++ gcc/DATESTAMP | 2 +- gcc/testsuite/ChangeLog | 19 +++++++++++++++++++ 3 files changed, 29 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 01523448590d..7bee68240af7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2021-05-24 Alex Coplan + + Backported from master: + 2021-05-10 Alex Coplan + + PR target/99960 + * config/arm/mve.md (*mve_mov): Simplify output code. Use + vldrw.u32 and vstrw.32 for V2D[IF]mode loads and stores. + 2021-05-20 Andreas Krebbel Backported from master: diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index e2a9538cdbda..e64bfabbbe33 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20210524 +20210525 diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 60c48fb4c2f8..656c219446f7 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,22 @@ +2021-05-24 Alex Coplan + + Backported from master: + 2021-05-10 Alex Coplan + + PR target/99960 + * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c: + Update now that we're (correctly) using full 128-bit vector + loads/stores. + * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c: + Likewise. + * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c: + Likewise. + * gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c: + Likewise. + * gcc.target/arm/mve/intrinsics/vuninitializedq_int.c: Likewise. + * gcc.target/arm/mve/intrinsics/vuninitializedq_int1.c: + Likewise. + 2021-05-21 Eric Botcazou * gnat.dg/derived_type7.adb, gnat.dg/derived_type7.ads: New test. -- 2.47.3