From 93669da1d1e35cb8d4df7e7f9765721c998521e7 Mon Sep 17 00:00:00 2001 From: Nick Chan Date: Thu, 20 Feb 2025 20:21:44 +0800 Subject: [PATCH] arm64: dts: apple: t7001: Add CPU caches Add information about CPU caches in Apple A8X SoC. Signed-off-by: Nick Chan Link: https://lore.kernel.org/r/20250220-caches-v1-3-2c7011097768@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t7001.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t7001.dtsi b/arch/arm64/boot/dts/apple/t7001.dtsi index 8e2c67e19c416..a2efa81305df4 100644 --- a/arch/arm64/boot/dts/apple/t7001.dtsi +++ b/arch/arm64/boot/dts/apple/t7001.dtsi @@ -39,6 +39,9 @@ operating-points-v2 = <&typhoon_opp>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; }; cpu1: cpu@1 { @@ -49,6 +52,9 @@ operating-points-v2 = <&typhoon_opp>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; }; cpu2: cpu@2 { @@ -59,6 +65,16 @@ operating-points-v2 = <&typhoon_opp>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x200000>; }; }; -- 2.47.3