From 95a0ad1ea1e1b4fc66c1006c1f7231be1de04453 Mon Sep 17 00:00:00 2001 From: Adhemerval Zanella Date: Thu, 11 Sep 2025 10:49:46 -0300 Subject: [PATCH] atomic: Consolidate atomic_write_barrier implementation MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit All ABIs, except alpha and sparc, define it to atomic_full_barrier/__sync_synchronize, which can be mapped to __atomic_thread_fence (__ATOMIC_RELEASE). For alpha, it uses a 'wmb' which does not map to any of C11 barriers. For sparc it uses a stronger 'member #LoadStore | #StoreStore', where the release barrier maps to just 'membar #StoreLoad'. The patch keeps the sparc definition. For PowerPC, it allows the use of lwsync for additional chips (since _ARCH_PWR4 does not cover all chips that support it). Tested on aarch64-linux-gnu. Co-authored-by: Wilco Dijkstra Reviewed-by: Wilco Dijkstra   --- include/atomic.h | 2 +- sysdeps/generic/malloc-machine.h | 4 ---- sysdeps/powerpc/atomic-machine.h | 9 --------- sysdeps/x86/atomic-machine.h | 2 -- 4 files changed, 1 insertion(+), 16 deletions(-) diff --git a/include/atomic.h b/include/atomic.h index 866c11c11f..3dfefc2c18 100644 --- a/include/atomic.h +++ b/include/atomic.h @@ -113,7 +113,7 @@ #ifndef atomic_write_barrier -# define atomic_write_barrier() atomic_full_barrier () +# define atomic_write_barrier() __atomic_thread_fence (__ATOMIC_RELEASE) #endif diff --git a/sysdeps/generic/malloc-machine.h b/sysdeps/generic/malloc-machine.h index 4fb8e809cc..9b5e9b2dd1 100644 --- a/sysdeps/generic/malloc-machine.h +++ b/sysdeps/generic/malloc-machine.h @@ -22,10 +22,6 @@ #include -#ifndef atomic_write_barrier -# define atomic_write_barrier() atomic_full_barrier () -#endif - #ifndef DEFAULT_TOP_PAD # define DEFAULT_TOP_PAD 131072 #endif diff --git a/sysdeps/powerpc/atomic-machine.h b/sysdeps/powerpc/atomic-machine.h index e173b61e9c..e32408a09d 100644 --- a/sysdeps/powerpc/atomic-machine.h +++ b/sysdeps/powerpc/atomic-machine.h @@ -36,13 +36,4 @@ # define MUTEX_HINT_REL #endif -#ifdef _ARCH_PWR4 -/* - * "light weight" sync can also be used for the release barrier. - */ -# define atomic_write_barrier() __asm ("lwsync" ::: "memory") -#else -# define atomic_write_barrier() __asm ("sync" ::: "memory") -#endif - #endif diff --git a/sysdeps/x86/atomic-machine.h b/sysdeps/x86/atomic-machine.h index f46a0868e3..0051eede70 100644 --- a/sysdeps/x86/atomic-machine.h +++ b/sysdeps/x86/atomic-machine.h @@ -31,8 +31,6 @@ #define ATOMIC_EXCHANGE_USES_CAS 0 -#define atomic_write_barrier() __asm ("" ::: "memory") - #define atomic_spin_nop() __asm ("pause") #endif /* atomic-machine.h */ -- 2.47.3