From 965e37ec0f8d4926809526e5ee0916774376f007 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 20 Aug 2025 21:06:51 +0100 Subject: [PATCH] arm64: dts: renesas: r9a09g087: Add pinctrl node Add pinctrl node to RZ/N2H ("R9A09G087") SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250820200659.2048755-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi index 7dcaee711486e..ecbb7b93aed2c 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -216,6 +216,19 @@ #power-domain-cells = <0>; }; + pinctrl: pinctrl@802c0000 { + compatible = "renesas,r9a09g087-pinctrl"; + reg = <0 0x802c0000 0 0x10000>, + <0 0x812c0000 0 0x10000>, + <0 0x802b0000 0 0x10000>; + reg-names = "nsr", "srs", "srn"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 280>; + power-domains = <&cpg>; + }; + gic: interrupt-controller@83000000 { compatible = "arm,gic-v3"; reg = <0x0 0x83000000 0 0x40000>, -- 2.47.3