From 9a49e9712c81521e1e6da6c0b0baf21fb807c72f Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Mon, 30 Sep 2013 20:34:16 +0530 Subject: [PATCH] spi: zynq_qspi: Clear the previous config register value. Clear the old config register value read from previous SW before writing the new qspi configuration values on zynq_qspi_init_hw. Signed-off-by: Siva Durga Prasad Paladugu Acked-by: Jagannadha Sutradharudu Teki Signed-off-by: Michal Simek --- drivers/spi/zynq_qspi.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index 5fffb025b24..930ce363304 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -35,15 +35,30 @@ * of the QSPI controller */ #define ZYNQ_QSPI_CONFIG_IFMODE_MASK (1 << 31) /* Flash intrface mode*/ +#define ZYNQ_QSPI_CONFIG_HOLDB_MASK (1 << 19) /* Holdb Mask */ #define ZYNQ_QSPI_CONFIG_MSA_MASK (1 << 15) /* Manual start enb */ #define ZYNQ_QSPI_CONFIG_MCS_MASK (1 << 14) /* Manual chip select */ #define ZYNQ_QSPI_CONFIG_PCS_MASK (1 << 10) /* Peri chip select */ +#define ZYNQ_QSPI_CONFIG_REFCLK_MASK (1 << 8) /* Ref Clock Mask */ #define ZYNQ_QSPI_CONFIG_FW_MASK (0x3 << 6) /* FIFO width */ +#define ZYNQ_QSPI_CONFIG_BAUDRATE_MASK (0x7 << 3) /* Baudrate Divisor Mask */ #define ZYNQ_QSPI_CONFIG_MSTREN_MASK (1 << 0) /* Mode select */ #define ZYNQ_QSPI_CONFIG_MANSRT_MASK 0x00010000 /* Manual TX Start */ #define ZYNQ_QSPI_CONFIG_CPHA_MASK 0x00000004 /* Clock Phase Control */ #define ZYNQ_QSPI_CONFIG_CPOL_MASK 0x00000002 /* Clock Polarity Control */ #define ZYNQ_QSPI_CONFIG_SSCTRL_MASK 0x00003C00 /* Slave Select Mask */ +#define ZYNQ_QSPI_CONFIG_CLR_ALL_MASK (ZYNQ_QSPI_CONFIG_IFMODE_MASK | \ + ZYNQ_QSPI_CONFIG_HOLDB_MASK | \ + ZYNQ_QSPI_CONFIG_MANSRT_MASK | \ + ZYNQ_QSPI_CONFIG_MSA_MASK | \ + ZYNQ_QSPI_CONFIG_MCS_MASK | \ + ZYNQ_QSPI_CONFIG_PCS_MASK | \ + ZYNQ_QSPI_CONFIG_REFCLK_MASK | \ + ZYNQ_QSPI_CONFIG_FW_MASK | \ + ZYNQ_QSPI_CONFIG_BAUDRATE_MASK | \ + ZYNQ_QSPI_CONFIG_CPHA_MASK | \ + ZYNQ_QSPI_CONFIG_CPOL_MASK | \ + ZYNQ_QSPI_CONFIG_MSTREN_MASK) /* * QSPI Interrupt Registers bit Masks @@ -264,6 +279,8 @@ static void zynq_qspi_init_hw(int is_dual, unsigned int cs) writel(0x7F, &zynq_qspi_base->isr); config_reg = readl(&zynq_qspi_base->confr); + /* Clear all the bits before setting required configuration */ + config_reg &= ~ZYNQ_QSPI_CONFIG_CLR_ALL_MASK; config_reg |= ZYNQ_QSPI_CONFIG_IFMODE_MASK | ZYNQ_QSPI_CONFIG_MSA_MASK | ZYNQ_QSPI_CONFIG_MCS_MASK | ZYNQ_QSPI_CONFIG_PCS_MASK | ZYNQ_QSPI_CONFIG_FW_MASK | -- 2.47.3