From 9a9f7594fdd2f76e39f2dc20a19f0f1f5a4bc29b Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Sat, 12 Jul 2003 23:02:23 +0000 Subject: [PATCH] alpha.c: Fix comment typos. * config/alpha/alpha.c: Fix comment typos. * config/alpha/alpha.md: Likewise. * config/arm/arm.c: Likewise. * config/arm/arm.md: Likewise. * config/arm/lib1funcs.asm: Likewise. * config/avr/avr.md: Likewise. * config/arm/README-interworking: Fix typos. From-SVN: r69277 --- gcc/ChangeLog | 10 ++++++++++ gcc/config/alpha/alpha.c | 6 +++--- gcc/config/alpha/alpha.md | 4 ++-- gcc/config/arm/README-interworking | 2 +- gcc/config/arm/arm.c | 6 +++--- gcc/config/arm/arm.md | 28 ++++++++++++++-------------- gcc/config/arm/lib1funcs.asm | 2 +- gcc/config/avr/avr.md | 2 +- 8 files changed, 35 insertions(+), 25 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5a83f1ecc3ef..956f9ca4e3d5 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2003-07-12 Kazu Hirata + + * config/alpha/alpha.c: Fix comment typos. + * config/alpha/alpha.md: Likewise. + * config/arm/arm.c: Likewise. + * config/arm/arm.md: Likewise. + * config/arm/lib1funcs.asm: Likewise. + * config/avr/avr.md: Likewise. + * config/arm/README-interworking: Fix typos. + 2003-07-12 Kazu Hirata * c-format.c: Fix comment formatting. diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c index df386deb9375..92fe830b2d18 100644 --- a/gcc/config/alpha/alpha.c +++ b/gcc/config/alpha/alpha.c @@ -233,7 +233,7 @@ override_options (void) flag_pic = 0; } - /* On Unicos/Mk, the native compiler consistenly generates /d suffices for + /* On Unicos/Mk, the native compiler consistently generates /d suffices for floating-point instructions. Make that the default for this target. */ if (TARGET_ABI_UNICOSMK) alpha_fprm = ALPHA_FPRM_DYN; @@ -3481,7 +3481,7 @@ alpha_split_conditional_move (enum rtx_code code, rtx dest, rtx cond, be shared. */ if (f == 0 && exact_log2 (diff) > 0 - /* On EV6, we've got enough shifters to make non-arithmatic shifts + /* On EV6, we've got enough shifters to make non-arithmetic shifts viable over a longer latency cmove. On EV5, the E0 slot is a scarce resource, and on EV4 shift has the same latency as a cmove. */ && (diff <= 8 || alpha_cpu == PROCESSOR_EV6)) @@ -5120,7 +5120,7 @@ alpha_use_dfa_pipeline_interface (void) For EV4, loads can be issued to either IB0 or IB1, thus we have 2 alternative schedules. For EV5, we can choose between E0/E1 and - FA/FM. For EV6, an arithmatic insn can be issued to U0/U1/L0/L1. */ + FA/FM. For EV6, an arithmetic insn can be issued to U0/U1/L0/L1. */ static int alpha_multipass_dfa_lookahead (void) diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index 067f3fdf839e..6db16f711b29 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -120,7 +120,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none" ;; The ROUND_SUFFIX attribute marks which instructions require a ;; rounding-mode suffix. The value NONE indicates no suffix, -;; the value NORMAL indicates a suffix controled by alpha_fprm. +;; the value NORMAL indicates a suffix controlled by alpha_fprm. (define_attr "round_suffix" "none,normal,c" (const_string "none")) @@ -133,7 +133,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none" ;; V_SV_SVI accepts /v, /sv and /svi (cvttq only) ;; U_SU_SUI accepts /u, /su and /sui (most fp instructions) ;; -;; The actual suffix emitted is controled by alpha_fptm. +;; The actual suffix emitted is controlled by alpha_fptm. (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui" (const_string "none")) diff --git a/gcc/config/arm/README-interworking b/gcc/config/arm/README-interworking index de8b27841b24..0a03cdc3c9d9 100644 --- a/gcc/config/arm/README-interworking +++ b/gcc/config/arm/README-interworking @@ -404,7 +404,7 @@ Instead the pseudo op is attached to a new label .real_start_of_ (where is the name of the function) which indicates the start of the Thumb code. This does have the interesting side effect in that if this function is now called from a Thumb mode piece of code -outsside of the current file, the linker will generate a calling stub +outside of the current file, the linker will generate a calling stub to switch from Thumb mode into ARM mode, and then this is immediately overridden by the function's header which switches back into Thumb mode. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 737a0270c44d..747b93115dfc 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -452,7 +452,7 @@ static const struct processors all_architectures[] = { NULL, 0 } }; -/* This is a magic stucture. The 'string' field is magically filled in +/* This is a magic structure. The 'string' field is magically filled in with a pointer to the value specified by the user on the command line assuming that the user has specified such a value. */ @@ -10248,7 +10248,7 @@ arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) return VALID_IWMMXT_REG_MODE (mode); if (regno <= LAST_ARM_REGNUM) - /* We allow any value to be stored in the general regisetrs. */ + /* We allow any value to be stored in the general registers. */ return 1; if ( regno == FRAME_POINTER_REGNUM @@ -11648,7 +11648,7 @@ thumb_far_jump_used_p (int in_prologue) && get_attr_far_jump (insn) == FAR_JUMP_YES ) { - /* Record the fact that we have decied that + /* Record the fact that we have decided that the function does use far jumps. */ cfun->machine->far_jump_used = 1; return 1; diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 94e2c65edd6b..4a72c69ef3ca 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -75,18 +75,18 @@ ; and stack frame generation. Operand 0 is the ; register to "use". (UNSPEC_CHECK_ARCH 7); Set CCs to indicate 26-bit or 32-bit mode. - (UNSPEC_WSHUFH 8) ; Used by the instrinsic form of the iWMMXt WSHUFH instruction. - (UNSPEC_WACC 9) ; Used by the instrinsic form of the iWMMXt WACC instruction. - (UNSPEC_TMOVMSK 10) ; Used by the instrinsic form of the iWMMXt TMOVMSK instruction. - (UNSPEC_WSAD 11) ; Used by the instrinsic form of the iWMMXt WSAD instruction. - (UNSPEC_WSADZ 12) ; Used by the instrinsic form of the iWMMXt WSADZ instruction. - (UNSPEC_WMACS 13) ; Used by the instrinsic form of the iWMMXt WMACS instruction. - (UNSPEC_WMACU 14) ; Used by the instrinsic form of the iWMMXt WMACU instruction. - (UNSPEC_WMACSZ 15) ; Used by the instrinsic form of the iWMMXt WMACSZ instruction. - (UNSPEC_WMACUZ 16) ; Used by the instrinsic form of the iWMMXt WMACUZ instruction. - (UNSPEC_CLRDI 17) ; Used by the instrinsic form of the iWMMXt CLRDI instruction. - (UNSPEC_WMADDS 18) ; Used by the instrinsic form of the iWMMXt WMADDS instruction. - (UNSPEC_WMADDU 19) ; Used by the instrinsic form of the iWMMXt WMADDU instruction. + (UNSPEC_WSHUFH 8) ; Used by the intrinsic form of the iWMMXt WSHUFH instruction. + (UNSPEC_WACC 9) ; Used by the intrinsic form of the iWMMXt WACC instruction. + (UNSPEC_TMOVMSK 10) ; Used by the intrinsic form of the iWMMXt TMOVMSK instruction. + (UNSPEC_WSAD 11) ; Used by the intrinsic form of the iWMMXt WSAD instruction. + (UNSPEC_WSADZ 12) ; Used by the intrinsic form of the iWMMXt WSADZ instruction. + (UNSPEC_WMACS 13) ; Used by the intrinsic form of the iWMMXt WMACS instruction. + (UNSPEC_WMACU 14) ; Used by the intrinsic form of the iWMMXt WMACU instruction. + (UNSPEC_WMACSZ 15) ; Used by the intrinsic form of the iWMMXt WMACSZ instruction. + (UNSPEC_WMACUZ 16) ; Used by the intrinsic form of the iWMMXt WMACUZ instruction. + (UNSPEC_CLRDI 17) ; Used by the intrinsic form of the iWMMXt CLRDI instruction. + (UNSPEC_WMADDS 18) ; Used by the intrinsic form of the iWMMXt WMADDS instruction. + (UNSPEC_WMADDU 19) ; Used by the intrinsic form of the iWMMXt WMADDU instruction. ] ) @@ -243,7 +243,7 @@ ; Only model the write buffer for ARM6 and ARM7. Earlier processors don't ; have one. Later ones, such as StrongARM, have write-back caches, so don't -; suffer blockages enough to warrent modelling this (and it can adversely +; suffer blockages enough to warrant modelling this (and it can adversely ; affect the schedule). (define_attr "model_wbuf" "no,yes" (const (symbol_ref "arm_is_6_or_7"))) @@ -5106,7 +5106,7 @@ ;; Compare & branch insns -;; The range calcualations are based as follows: +;; The range calculations are based as follows: ;; For forward branches, the address calculation returns the address of ;; the next instruction. This is 2 beyond the branch instruction. ;; For backward branches, the address calculation returns the address of diff --git a/gcc/config/arm/lib1funcs.asm b/gcc/config/arm/lib1funcs.asm index f80af2dd60e0..0f35d8145c1a 100644 --- a/gcc/config/arm/lib1funcs.asm +++ b/gcc/config/arm/lib1funcs.asm @@ -165,7 +165,7 @@ lr .req r14 pc .req r15 #endif /* ------------------------------------------------------------------------ */ -/* Bodies of the divsion and modulo routines. */ +/* Bodies of the division and modulo routines. */ /* ------------------------------------------------------------------------ */ .macro ARM_DIV_MOD_BODY modulo LSYM(Loop1): diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md index 86ab6c72829d..ef449158c44c 100644 --- a/gcc/config/avr/avr.md +++ b/gcc/config/avr/avr.md @@ -2255,7 +2255,7 @@ ;; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -;; This instructin sets Z flag +;; This instruction sets Z flag (define_insn "sez" [(set (cc0) (const_int 0))] -- 2.47.3