From 9c040f8d85b33868d9b15d59ae12e981a737d433 Mon Sep 17 00:00:00 2001 From: Jagan Date: Tue, 12 Jun 2012 21:15:32 +0530 Subject: [PATCH] Xilinx: ARM: Renamed few legacy names as part of cleanup Renamed few legacy names with valid zynq based names. Removed ps7_init_hw header as it is not used. Signed-off-by: Jagan --- arch/arm/include/asm/arch-zynq/xparameters.h | 3 +- board/xilinx/zynq_common/lowlevel_init.S | 4 +- board/xilinx/zynq_common/ps7_init_hw.h | 307 ------------------- drivers/mmc/zynq_mmc.c | 14 +- drivers/serial/serial_xpsuart.c | 2 +- drivers/serial/serial_xpsuart.h | 4 +- drivers/spi/zynq_qspi_wrap.c | 16 +- 7 files changed, 20 insertions(+), 330 deletions(-) delete mode 100755 board/xilinx/zynq_common/ps7_init_hw.h diff --git a/arch/arm/include/asm/arch-zynq/xparameters.h b/arch/arm/include/asm/arch-zynq/xparameters.h index ec4ea360c0a..451e979b931 100755 --- a/arch/arm/include/asm/arch-zynq/xparameters.h +++ b/arch/arm/include/asm/arch-zynq/xparameters.h @@ -9,8 +9,7 @@ #define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 #define XPAR_DDR2_SDRAM_MEM_HIGHADDR 0x00FFFFFF -/* starting with PEEP8 designs, there is 256 MB of DDR */ - +/* starting with Emulation8 designs, there is 256 MB of DDR */ #define RTL_45 #ifdef RTL_45 #define XPAR_MEMORY_MB_SIZE 256 diff --git a/board/xilinx/zynq_common/lowlevel_init.S b/board/xilinx/zynq_common/lowlevel_init.S index 441e6e23569..f0b1b5a9933 100755 --- a/board/xilinx/zynq_common/lowlevel_init.S +++ b/board/xilinx/zynq_common/lowlevel_init.S @@ -1,7 +1,7 @@ /* - * This black box is a direct translation of init_ddrc.tcl. The Pele DDR controller - * is initialized herein. + * This black box is a direct translation of init_ddrc.tcl. + * The Zynq DDR controller is initialized herein. * It needs lots of love and attention some day. */ diff --git a/board/xilinx/zynq_common/ps7_init_hw.h b/board/xilinx/zynq_common/ps7_init_hw.h deleted file mode 100755 index abef71c778e..00000000000 --- a/board/xilinx/zynq_common/ps7_init_hw.h +++ /dev/null @@ -1,307 +0,0 @@ -#ifndef PS7_INIT_HW_H /* prevent circular inclusions */ -#define PS7_INIT_HW_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -#define XPS_SYS_CTRL_BASEADDR 0xF8000000 - -#define SLCR_BASE_ADDRESS XPS_SYS_CTRL_BASEADDR - -/* MIO registers */ -#define SLCR_LOCK (SLCR_BASE_ADDRESS + 0x4) -#define SLCR_UNLOCK (SLCR_BASE_ADDRESS + 0x8) -#define SLCR_MIO0 (SLCR_BASE_ADDRESS + 0x700) -#define SLCR_MIO1 (SLCR_BASE_ADDRESS + 0x704) -#define SLCR_MIO2 (SLCR_BASE_ADDRESS + 0x708) -#define SLCR_MIO3 (SLCR_BASE_ADDRESS + 0x70C) -#define SLCR_MIO4 (SLCR_BASE_ADDRESS + 0x710) -#define SLCR_MIO5 (SLCR_BASE_ADDRESS + 0x714) -#define SLCR_MIO6 (SLCR_BASE_ADDRESS + 0x718) -#define SLCR_MIO7 (SLCR_BASE_ADDRESS + 0x71C) -#define SLCR_MIO8 (SLCR_BASE_ADDRESS + 0x720) -#define SLCR_MIO9 (SLCR_BASE_ADDRESS + 0x724) -#define SLCR_MIO10 (SLCR_BASE_ADDRESS + 0x728) -#define SLCR_MIO11 (SLCR_BASE_ADDRESS + 0x72C) -#define SLCR_MIO12 (SLCR_BASE_ADDRESS + 0x730) -#define SLCR_MIO13 (SLCR_BASE_ADDRESS + 0x734) -#define SLCR_MIO14 (SLCR_BASE_ADDRESS + 0x738) -#define SLCR_MIO15 (SLCR_BASE_ADDRESS + 0x73C) -#define SLCR_MIO16 (SLCR_BASE_ADDRESS + 0x740) -#define SLCR_MIO17 (SLCR_BASE_ADDRESS + 0x744) -#define SLCR_MIO18 (SLCR_BASE_ADDRESS + 0x748) -#define SLCR_MIO19 (SLCR_BASE_ADDRESS + 0x74C) -#define SLCR_MIO20 (SLCR_BASE_ADDRESS + 0x750) -#define SLCR_MIO21 (SLCR_BASE_ADDRESS + 0x754) -#define SLCR_MIO22 (SLCR_BASE_ADDRESS + 0x758) -#define SLCR_MIO23 (SLCR_BASE_ADDRESS + 0x75C) -#define SLCR_MIO24 (SLCR_BASE_ADDRESS + 0x760) -#define SLCR_MIO25 (SLCR_BASE_ADDRESS + 0x764) -#define SLCR_MIO26 (SLCR_BASE_ADDRESS + 0x768) -#define SLCR_MIO27 (SLCR_BASE_ADDRESS + 0x76C) -#define SLCR_MIO28 (SLCR_BASE_ADDRESS + 0x770) -#define SLCR_MIO29 (SLCR_BASE_ADDRESS + 0x774) -#define SLCR_MIO30 (SLCR_BASE_ADDRESS + 0x778) -#define SLCR_MIO31 (SLCR_BASE_ADDRESS + 0x77C) -#define SLCR_MIO32 (SLCR_BASE_ADDRESS + 0x780) -#define SLCR_MIO33 (SLCR_BASE_ADDRESS + 0x784) -#define SLCR_MIO34 (SLCR_BASE_ADDRESS + 0x788) -#define SLCR_MIO35 (SLCR_BASE_ADDRESS + 0x78C) -#define SLCR_MIO36 (SLCR_BASE_ADDRESS + 0x790) -#define SLCR_MIO37 (SLCR_BASE_ADDRESS + 0x794) -#define SLCR_MIO38 (SLCR_BASE_ADDRESS + 0x798) -#define SLCR_MIO39 (SLCR_BASE_ADDRESS + 0x79C) -#define SLCR_MIO40 (SLCR_BASE_ADDRESS + 0x7A0) -#define SLCR_MIO41 (SLCR_BASE_ADDRESS + 0x7A4) -#define SLCR_MIO42 (SLCR_BASE_ADDRESS + 0x7A8) -#define SLCR_MIO43 (SLCR_BASE_ADDRESS + 0x7AC) -#define SLCR_MIO44 (SLCR_BASE_ADDRESS + 0x7B0) -#define SLCR_MIO45 (SLCR_BASE_ADDRESS + 0x7B4) -#define SLCR_MIO46 (SLCR_BASE_ADDRESS + 0x7B8) -#define SLCR_MIO47 (SLCR_BASE_ADDRESS + 0x7BC) -#define SLCR_MIO48 (SLCR_BASE_ADDRESS + 0x7C0) -#define SLCR_MIO49 (SLCR_BASE_ADDRESS + 0x7C4) -#define SLCR_MIO50 (SLCR_BASE_ADDRESS + 0x7C8) -#define SLCR_MIO51 (SLCR_BASE_ADDRESS + 0x7CC) -#define SLCR_MIO52 (SLCR_BASE_ADDRESS + 0x7D0) -#define SLCR_MIO53 (SLCR_BASE_ADDRESS + 0x7D4) -#define SLCR_SDIO0_WP_CD (SLCR_BASE_ADDRESS + 0x830) - -/* PLL registers */ -#define SLCR_ARM_PLL_CTRL (SLCR_BASE_ADDRESS + 0x100) /* ARM PLL Control */ -#define SLCR_DDR_PLL_CTRL (SLCR_BASE_ADDRESS + 0x104) /* DDR PLL Control */ -#define SLCR_IO_PLL_CTRL (SLCR_BASE_ADDRESS + 0x108) /* IO PLL Control */ -#define SLCR_PLL_STATUS (SLCR_BASE_ADDRESS + 0x10C) /* PLL Status */ -#define SLCR_ARM_PLL_CFG (SLCR_BASE_ADDRESS + 0x110) /* ARM PLL Configuration */ -#define SLCR_DDR_PLL_CFG (SLCR_BASE_ADDRESS + 0x114) /* DDR PLL Configuration */ -#define SLCR_IO_PLL_CFG (SLCR_BASE_ADDRESS + 0x118) /* IO PLL Configuration */ -#define SLCR_PLL_BG_CTRL (SLCR_BASE_ADDRESS + 0x11C) /* PLL Bandgap control */ -#define SLCR_ARM_CLK_CTRL (SLCR_BASE_ADDRESS + 0x120) /* CORTEX A9 Clock Control */ -#define SLCR_DDR_CLK_CTRL (SLCR_BASE_ADDRESS + 0x124) /* DDR Clock Control */ -#define SLCR_DCI_CLK_CTRL (SLCR_BASE_ADDRESS + 0x128) /* DCI clock control */ -#define SLCR_APER_CLK_CTRL (SLCR_BASE_ADDRESS + 0x12C) /* AMBA Peripheral Clock Control */ -#define SLCR_USB0_CLK_CTRL (SLCR_BASE_ADDRESS + 0x130) /* USB 0 ULPI Clock Control */ -#define SLCR_USB1_CLK_CTRL (SLCR_BASE_ADDRESS + 0x134) /* USB 1 ULPI Clock Control */ -#define SLCR_GEM0_RCLK_CTRL (SLCR_BASE_ADDRESS + 0x138) /* Gigabit Ethernet MAC 0 RX Clock Control */ -#define SLCR_GEM1_RCLK_CTRL (SLCR_BASE_ADDRESS + 0x13C) /* Gigabit Ethernet MAC 0 RX Clock Control */ -#define SLCR_GEM0_CLK_CTRL (SLCR_BASE_ADDRESS + 0x140) /* Gigabit Ethernet MAC 0 Ref Clock Control */ -#define SLCR_GEM1_CLK_CTRL (SLCR_BASE_ADDRESS + 0x144) /* Gigabit Ethernet MAC 1 Ref Clock Control */ -#define SLCR_SMC_CLK_CTRL (SLCR_BASE_ADDRESS + 0x148) /* SMC Reference Clock Control */ -#define SLCR_LQSPI_CLK_CTRL (SLCR_BASE_ADDRESS + 0x14C) /* Linear Quad-SPI Reference Clock Control */ -#define SLCR_SDIO_CLK_CTRL (SLCR_BASE_ADDRESS + 0x150) /* SDIO Reference Clock Control */ -#define SLCR_UART_CLK_CTRL (SLCR_BASE_ADDRESS + 0x154) /* UART Reference Clock Control */ -#define SLCR_SPI_CLK_CTRL (SLCR_BASE_ADDRESS + 0x158) /* SPI Reference Clock Control */ -#define SLCR_CAN_CLK_CTRL (SLCR_BASE_ADDRESS + 0x15C) /* CAN Reference Clock Control */ -#define SLCR_CAN_MIO_CLK_CTRL (SLCR_BASE_ADDRESS + 0x160) /* CAN MIO Clock Control */ -#define SLCR_DBG_CLK_CTRL (SLCR_BASE_ADDRESS + 0x164) /* DBG Clock Control */ -#define SLCR_PCAP_CLK_CTRL (SLCR_BASE_ADDRESS + 0x168) /* PCAP Clock Control */ -#define SLCR_TOPSW_CLK_CTRL (SLCR_BASE_ADDRESS + 0x16C) /* TOPSW Clock Control */ -#define SLCR_FPGA0_CLK_CTRL (SLCR_BASE_ADDRESS + 0x170) /* FPGA0 Clock Control */ -#define SLCR_FPGA1_CLK_CTRL (SLCR_BASE_ADDRESS + 0x180) /* FPGA1 Clock Control */ -#define SLCR_FPGA2_CLK_CTRL (SLCR_BASE_ADDRESS + 0x190) /* FPGA2 Clock Control */ -#define SLCR_FPGA3_CLK_CTRL (SLCR_BASE_ADDRESS + 0x1A0) /* FPGA3 Clock Control */ -#define SLCR_PLL_PREDIVISOR (SLCR_BASE_ADDRESS + 0x1C0) /* PLL pre devisor */ -#define SLCR_CLK_621_TRUE (SLCR_BASE_ADDRESS + 0x1C4) /* CPU enable the 6:2:1 mode */ - -/* MIO */ -#define MIO_LQSPI 0x02 -#define MIO_USB 0x04 -#define MIO_GEM 0x02 -#define MIO_UART 0xE0 -#define MIO_SPI 0xA0 -#define MIO_CAN 0x20 -#define MIO_I2C 0x40 -#define MIO_SDIO 0x80 -#define MIO_GPIO 0x00 -#define MIO_MDIO0 0x80 -#define MIO_MDIO1 0xA0 -#define MIO_NAND 0x10 -#define MIO_SRAM_NOR 0x08 -#define MIO_TTC 0xC0 -#define MIO_WDT 0x60 -#define MIO_MASK 0xFFF /* IOTYPE SPEED SEL TRI ENABLE Mask */ -#define SDIO0_CD_SEL_SHIFT 16 - -#define TRI_ENABLE_IN (1 << 0) -#define TRI_ENABLE_OUT (0 << 0) -#define TRI_ENABLE_IN_OUT (0 << 0) -#define SLOW_CMOS (0 << 8) -#define FAST_CMOS (1 << 8) -#define LVTTL (0 << 9) -#define LVCMOS18 (1 << 9) -#define LVCMOS25 (2 << 9) -#define LVCMOS33 (3 << 9) -#define HSTL (4 << 9) -#define PULLUP_ENABLE (1 << 12) -#define PULLUP_DISABLE (0 << 12) -#define DISABLE_RCVR (1 << 13) - -/* PLL */ -#define PLL_RESET (1 << 0) -#define PLL_PWRDWN (1 << 1) -#define PLL_BYPASS_QUAL (1 << 3) -#define PLL_BYPASS_FORCE (1 << 4) -#define PLL_FDIV_SHIFT 12 -#define UPDATE_CLR (0 << 24) -#define UPDATE_SERVICED (1 << 25) - -#define PLL_RES_SHIFT 4 -#define PLL_CP_SHIFT 8 -#define PLL_LOCK_CNT_SHIFT 12 - -/* CPU */ -#define CPU_SRCSEL_SHIFT 4 -#define CPU_DIVISOR_SHIFT 8 -#define CPU_6OR4XCLKACT_ENABLE (1 << 24) -#define CPU_3OR2XCLKACT_ENABLE (1 << 25) -#define CPU_2XCLKACT_ENABLE (1 << 26) -#define CPU_1XCLKACT_ENABLE (1 << 27) -#define CPU_PERI_CLKACT_ENABLE (1 << 28) - -/* DDR */ -#define DDR_3XCLKACT_ENABLE (1 << 0) -#define DDR_2XCLKACT_ENABLE (1 << 1) -#define DDR_3XCLK_DIVISOR_SHIFT 20 -#define DDR_2XCLK_DIVISOR_SHIFT 26 - -/* DCI */ -#define DCI_CLKACT_ENABLE (1 << 0) -#define DCI_DIVISOR0_SHIFT 8 -#define DCI_DIVISOR1_SHIFT 20 - -/* APER */ -#define SLCR_DMA_CPU_2XCLKACT_ENABLE (1 << 0) -#define SLCR_USB0_CPU_1XCLKACT_ENABLE (1 << 2) -#define SLCR_USB1_CPU_1XCLKACT_ENABLE (1 << 3) -#define SLCR_GEM0_CPU_1XCLKACT_ENABLE (1 << 6) -#define SLCR_GEM1_CPU_1XCLKACT_ENABLE (1 << 7) -#define SLCR_SDI0_CPU_1XCLKACT_ENABLE (1 << 10) -#define SLCR_SDI1_CPU_1XCLKACT_ENABLE (1 << 11) -#define SLCR_SPI0_CPU_1XCLKACT_ENABLE (1 << 14) -#define SLCR_SPI1_CPU_1XCLKACT_ENABLE (1 << 15) -#define SLCR_CAN0_CPU_1XCLKACT_ENABLE (1 << 16) -#define SLCR_CAN1_CPU_1XCLKACT_ENABLE (1 << 17) -#define SLCR_I2C0_CPU_1XCLKACT_ENABLE (1 << 18) -#define SLCR_I2C1_CPU_1XCLKACT_ENABLE (1 << 19) -#define SLCR_UART0_CPU_1XCLKACT_ENABLE (1 << 20) -#define SLCR_UART1_CPU_1XCLKACT_ENABLE (1 << 21) -#define SLCR_GPIO_CPU_1XCLKACT_ENABLE (1 << 22) -#define SLCR_LQSPI_CPU_1XCLKACT_ENABLE (1 << 23) -#define SLCR_SMC_CPU_1XCLKACT_ENABLE (1 << 24) - -/* PLL source */ -#define IO_PLL 0x0 -#define ARM_PLL 0x2 -#define DDR_PLL 0x3 - -/* CPU PLL source */ -#define CPU_ARM_PLL 0x0 -#define CPU_DDR_PLL 0x2 -#define CPU_IO_PLL 0x3 - -/* USB0 */ -#define USB0_CLKACT_ENABLE (1 << 0) -#define USB0_SRCSEL_SHIFT 4 -#define USB0_DIVISOR0_SHIFT 8 -#define USB0_DIVISOR1_SHIFT 20 - -/* USB1 */ -#define USB1_CLKACT_ENABLE (1 << 0) -#define USB1_SRCSEL_SHIFT 4 -#define USB1_DIVISOR0_SHIFT 8 -#define USB1_DIVISOR1_SHIFT 20 - -/* GEM0 RX */ -#define GEM0_RX_CLKACT_ENABLE (1 << 0) -#define GEM0_RX_SRCSEL_SHIFT 4 -#define GEM0_MIO_RX_CLK 0 -#define GEM0_FMIO_RX_CLK 1 -/* GEM1 RX */ -#define GEM1_RX_CLKACT_ENABLE (1 << 0) -#define GEM1_RX_SRCSEL_SHIFT 4 -#define GEM1_MIO_RX_CLK 0 -#define GEM1_FMIO_RX_CLK 1 -/* GEM0 */ -#define GEM0_CLKACT_ENABLE (1 << 0) -#define GEM0_SRCSEL_SHIFT 4 -#define GEM0_DIVISOR0_SHIFT 8 -#define GEM0_DIVISOR1_SHIFT 20 - -/* GEM1 */ -#define GEM1_CLKACT_ENABLE (1 << 0) -#define GEM1_SRCSEL_SHIFT 4 -#define GEM1_DIVISOR0_SHIFT 8 -#define GEM1_DIVISOR1_SHIFT 20 - -/* SMC */ -#define SMC_CLKACT_ENABLE (1 << 0) -#define SMC_SRCSEL_SHIFT 4 -#define SMC_DIVISOR_SHIFT 8 - -/* LQSPI */ -#define LQSPI_CLKACT_ENABLE (1 << 0) -#define LQSPI_SRCSEL_SHIFT 4 -#define LQSPI_DIVISOR_SHIFT 8 - -/* SDIO */ -#define SDIO0_CLKACT_ENABLE (1 << 0) -#define SDIO1_CLKACT_ENABLE (1 << 1) -#define SDIO_SRCSEL_SHIFT 4 -#define SDIO_DIVISOR_SHIFT 8 - -/* UART */ -#define UART0_CLKACT_ENABLE (1 << 0) -#define UART1_CLKACT_ENABLE (1 << 1) -#define UART_SRCSEL_SHIFT 4 -#define UART_DIVISOR_SHIFT 8 - -/* SPI */ -#define SPI0_CLKACT_ENABLE (1 << 0) -#define SPI1_CLKACT_ENABLE (1 << 1) -#define SPI_SRCSEL_SHIFT 4 -#define SPI_DIVISOR_SHIFT 8 - -/* CAN */ -#define CAN0_CLKACT_ENABLE (1 << 0) -#define CAN1_CLKACT_ENABLE (1 << 1) -#define CAN_SRCSEL_SHIFT 4 -#define CAN_DIVISOR0_SHIFT 8 -#define CAN_DIVISOR1_SHIFT 20 - -/* CAN MIO */ -#define CAN0_MUX -#define CAN0_REF_SEL -#define CAN1_MUX -#define CAN1_REF_SEL - -/* FPGA */ -#define FPGA0_SRCSEL_SHIFT 4 -#define FPGA0_DIVISOR0_SHIFT 8 -#define FPGA0_DIVISOR1_SHIFT 20 - -/* FPGA */ -#define FPGA1_SRCSEL_SHIFT 4 -#define FPGA1_DIVISOR0_SHIFT 8 -#define FPGA1_DIVISOR1_SHIFT 20 - -/* FPGA */ -#define FPGA2_SRCSEL_SHIFT 4 -#define FPGA2_DIVISOR0_SHIFT 8 -#define FPGA2_DIVISOR1_SHIFT 20 - -/* FPGA */ -#define FPGA3_SRCSEL_SHIFT 4 -#define FPGA3_DIVISOR0_SHIFT 8 -#define FPGA3_DIVISOR1_SHIFT 20 - -/* PCAP */ -#define PCAP_CLKACT_ENABLE (1 << 0) -#define PCAP_SRCSEL_SHIFT 4 -#define PCAP_DIVISOR_SHIFT 8 - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/drivers/mmc/zynq_mmc.c b/drivers/mmc/zynq_mmc.c index 820acd26e43..fc04026927e 100755 --- a/drivers/mmc/zynq_mmc.c +++ b/drivers/mmc/zynq_mmc.c @@ -211,7 +211,7 @@ make_command (unsigned cmd) return retval; } -static int pele_sdh_request(struct mmc *mmc, struct mmc_cmd *cmd, +static int zynq_sdh_request(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { u32 status; @@ -220,7 +220,7 @@ static int pele_sdh_request(struct mmc *mmc, struct mmc_cmd *cmd, int result = 0; #ifdef DEBUG_VERBOSE - printf("pele_sdh_request: cmdidx: %d arg: 0x%x\n", + printf("zynq_sdh_request: cmdidx: %d arg: 0x%x\n", cmd->cmdidx, cmd->cmdarg); #endif @@ -358,14 +358,14 @@ exit: return result; } -static void pele_sdh_set_ios(struct mmc *mmc) +static void zynq_sdh_set_ios(struct mmc *mmc) { #ifdef DEBUG printf("%s: voltages: 0x%x clock: 0x%x bus_width: 0x%x\n", __FUNCTION__, mmc->voltages, mmc->clock, mmc->bus_width); #endif } -static int pele_sdh_init(struct mmc *mmc) +static int zynq_sdh_init(struct mmc *mmc) { init_port(); return 0; @@ -385,9 +385,9 @@ int zynq_mmc_init(bd_t *bd) return -ENOMEM; } sprintf(mmc->name, "SDHCI"); - mmc->send_cmd = pele_sdh_request; - mmc->set_ios = pele_sdh_set_ios; - mmc->init = pele_sdh_init; + mmc->send_cmd = zynq_sdh_request; + mmc->set_ios = zynq_sdh_set_ios; + mmc->init = zynq_sdh_init; mmc->host_caps = MMC_MODE_4BIT; diff --git a/drivers/serial/serial_xpsuart.c b/drivers/serial/serial_xpsuart.c index 51c94beb48c..801b4a72699 100644 --- a/drivers/serial/serial_xpsuart.c +++ b/drivers/serial/serial_xpsuart.c @@ -1,5 +1,5 @@ /* - * U-boot driver for Xilinx Dragonfire UART. + * Xilinx Zynq Serial PS driver * Based on existing U-boot serial drivers. */ diff --git a/drivers/serial/serial_xpsuart.h b/drivers/serial/serial_xpsuart.h index 0c809c25bb1..55d4d731e1c 100644 --- a/drivers/serial/serial_xpsuart.h +++ b/drivers/serial/serial_xpsuart.h @@ -1,7 +1,5 @@ /* - * Adapted from: - * df_arm/trunk/ep3_1/sw/standalone/drivers/uart_v1_00_a/src/xuartepb_hw.h - * as of svn rev 1377. + * Xilinx Zynq Serial PS driver, headers */ #ifndef __XILINX_ZYNQ_UART_H__ diff --git a/drivers/spi/zynq_qspi_wrap.c b/drivers/spi/zynq_qspi_wrap.c index bee9c7a2f54..968bfa532a1 100644 --- a/drivers/spi/zynq_qspi_wrap.c +++ b/drivers/spi/zynq_qspi_wrap.c @@ -14,12 +14,12 @@ #include "zynq_qspi.h" -struct pele_spi_slave { +struct zynq_spi_slave { struct spi_slave slave; struct spi_device qspi; }; -#define to_pele_spi_slave(s) container_of(s, struct pele_spi_slave, slave) +#define to_zynq_spi_slave(s) container_of(s, struct zynq_spi_slave, slave) __attribute__((weak)) int spi_cs_is_valid(unsigned int bus, unsigned int cs) @@ -57,7 +57,7 @@ void spi_init() struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) { - struct pele_spi_slave *pspi; + struct zynq_spi_slave *pspi; #ifdef DEBUG printf("spi_setup_slave: bus: %d cs: %d max_hz: %d mode: %d\n", @@ -66,7 +66,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, xqspips_init_hw((void *)XPSS_QSPI_BASEADDR); - pspi = malloc(sizeof(struct pele_spi_slave)); + pspi = malloc(sizeof(struct zynq_spi_slave)); if (!pspi) { return NULL; } @@ -87,13 +87,13 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, void spi_free_slave(struct spi_slave *slave) { - struct pele_spi_slave *pspi; + struct zynq_spi_slave *pspi; #ifdef DEBUG printf("spi_free_slave: slave: 0x%08x\n", (u32)slave); #endif - pspi = to_pele_spi_slave(slave); + pspi = to_zynq_spi_slave(slave); free(pspi); } @@ -115,7 +115,7 @@ void spi_release_bus(struct spi_slave *slave) int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { - struct pele_spi_slave *pspi; + struct zynq_spi_slave *pspi; struct spi_transfer transfer; #ifdef DEBUG @@ -123,7 +123,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, (u32)slave, bitlen, (u32)dout, (u32)din, flags); #endif - pspi = (struct pele_spi_slave *)slave; + pspi = (struct zynq_spi_slave *)slave; transfer.tx_buf = dout; transfer.rx_buf = din; transfer.len = bitlen / 8; -- 2.47.3