From 9d484eac1ef859957b94437e10a4a6db95a9e427 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 12 Mar 2025 22:59:23 +0100 Subject: [PATCH] dt-bindings: reset: fix double id on rk3562-cru reset ids Id 173 was accidentially used two times for SRST_P_DDR_HWLP and SRST_P_DDR_PHY. This makes both resets ambiguous and also causes build warnings like: drivers/clk/rockchip/rst-rk3562.c:21:57: error: initialized field overwritten [-Werror=override-init] 21 | #define RK3562_DDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000*4 + reg * 16 + bit) | ^ drivers/clk/rockchip/rst-rk3562.c:266:9: note: in expansion of macro 'RK3562_DDRCRU_RESET_OFFSET' 266 | RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_PHY, 0, 8), | ^~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/clk/rockchip/rst-rk3562.c:21:57: note: (near initialization for 'rk3562_register_offset[173]') 21 | #define RK3562_DDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000*4 + reg * 16 + bit) | ^ drivers/clk/rockchip/rst-rk3562.c:266:9: note: in expansion of macro 'RK3562_DDRCRU_RESET_OFFSET' 266 | RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_PHY, 0, 8), | ^~~~~~~~~~~~~~~~~~~~~~~~~~ To fix that issue give SRST_P_DDR_PHY a new and now unique id. Reported-by: Stephen Boyd Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202503121743.0zcDf6nE-lkp@intel.com/ Fixes: dd113c4fefc8 ("dt-bindings: clock: Add RK3562 cru") Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20250312215923.275625-1-heiko@sntech.de Acked-by: Philipp Zabel Signed-off-by: Stephen Boyd --- include/dt-bindings/reset/rockchip,rk3562-cru.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/dt-bindings/reset/rockchip,rk3562-cru.h b/include/dt-bindings/reset/rockchip,rk3562-cru.h index a74471d7d2a93..8df95113056e3 100644 --- a/include/dt-bindings/reset/rockchip,rk3562-cru.h +++ b/include/dt-bindings/reset/rockchip,rk3562-cru.h @@ -217,7 +217,7 @@ #define SRST_MSCH_BRG_BIU 171 #define SRST_P_MSCH_BIU 172 #define SRST_P_DDR_HWLP 173 -#define SRST_P_DDR_PHY 173 +#define SRST_P_DDR_PHY 290 #define SRST_P_DDR_DFICTL 174 #define SRST_P_DDR_DMA2DDR 175 /********Name=DDRSOFTRST_CON01,Offset=0x20204********/ -- 2.47.3