From 9f14d9d98dc32fb8fe99ba5ae57a2fec3912d544 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Fri, 10 Oct 2025 17:50:40 +0200 Subject: [PATCH] target/riscv: Conceal MO_TE within gen_cmpxchg*() MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit All callers of gen_cmpxchg() / gen_cmpxchg64() set the MO_TE flag. Set it once in the callees. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-ID: <20251010155045.78220-10-philmd@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvzabha.c.inc | 2 +- target/riscv/insn_trans/trans_rvzacas.c.inc | 7 ++++--- target/riscv/translate.c | 1 + 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvzabha.c.inc b/target/riscv/insn_trans/trans_rvzabha.c.inc index c1f99b65f0..302c63f2a3 100644 --- a/target/riscv/insn_trans/trans_rvzabha.c.inc +++ b/target/riscv/insn_trans/trans_rvzabha.c.inc @@ -141,5 +141,5 @@ static bool trans_amocas_h(DisasContext *ctx, arg_amocas_h *a) { REQUIRE_ZACAS(ctx); REQUIRE_ZABHA(ctx); - return gen_cmpxchg(ctx, a, MO_ALIGN | MO_TE | MO_SW); + return gen_cmpxchg(ctx, a, MO_ALIGN | MO_SW); } diff --git a/target/riscv/insn_trans/trans_rvzacas.c.inc b/target/riscv/insn_trans/trans_rvzacas.c.inc index 5e7c7c92b7..d850b14264 100644 --- a/target/riscv/insn_trans/trans_rvzacas.c.inc +++ b/target/riscv/insn_trans/trans_rvzacas.c.inc @@ -25,7 +25,7 @@ static bool trans_amocas_w(DisasContext *ctx, arg_amocas_w *a) { REQUIRE_ZACAS(ctx); - return gen_cmpxchg(ctx, a, MO_ALIGN | MO_TE | MO_SL); + return gen_cmpxchg(ctx, a, MO_ALIGN | MO_SL); } static TCGv_i64 get_gpr_pair(DisasContext *ctx, int reg_num) @@ -76,6 +76,7 @@ static bool gen_cmpxchg64(DisasContext *ctx, arg_atomic *a, MemOp mop) TCGv src1 = get_address(ctx, a->rs1, 0); TCGv_i64 src2 = get_gpr_pair(ctx, a->rs2); + mop |= MO_TE; decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); tcg_gen_atomic_cmpxchg_i64(dest, src1, dest, src2, ctx->mem_idx, mop); @@ -88,10 +89,10 @@ static bool trans_amocas_d(DisasContext *ctx, arg_amocas_d *a) REQUIRE_ZACAS(ctx); switch (get_ol(ctx)) { case MXL_RV32: - return gen_cmpxchg64(ctx, a, MO_ALIGN | MO_TE | MO_UQ); + return gen_cmpxchg64(ctx, a, MO_ALIGN | MO_UQ); case MXL_RV64: case MXL_RV128: - return gen_cmpxchg(ctx, a, MO_ALIGN | MO_TE | MO_UQ); + return gen_cmpxchg(ctx, a, MO_ALIGN | MO_UQ); default: g_assert_not_reached(); } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 94af9853cf..2e6f39aa02 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1156,6 +1156,7 @@ static bool gen_cmpxchg(DisasContext *ctx, arg_atomic *a, MemOp mop) TCGv src1 = get_address(ctx, a->rs1, 0); TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); + mop |= MO_TE; decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); tcg_gen_atomic_cmpxchg_tl(dest, src1, dest, src2, ctx->mem_idx, mop); -- 2.47.3